GAL22LV10C-10LJ

FEATURES 2 ® Ne Tolew 5V Inp rant 22Luts on V10 D GAL22LV10 Low Voltage E2CMOS PLD Generic Array Logic™ FUNCTIONAL BLOCK DIAGRAM I/CLK RESET • HIGH PERFORMANCE E CMOS TECHNOLOGY — 4 ns Maximum Propagation Delay — Fmax = 250 MHz — 3 ns Maximum from Clock Input to Data Output — UltraMOS® Advanced CMOS Technology • 3.3V LOW VOLTAGE 22V10 ARCHITECTURE — JEDEC-Compatible 3.3V Interface Standard — 5V Compatible Inputs — I/O Interfaces with Standard 5V TTL Devices (GAL22LV10C) • ACTIVE PULL-UPS ON ALL PINS (GAL22LV10D) • E2 CELL TECHNOLOGY — Reconfigurable Logic — Reprogrammable Cells — 100% Tested/100% Yields — High Speed Electrical Erasure (