iCE40LM Family Data Sheet
DS1045 Version 1.6, October 2015
iCE40LM Family Data Sheet
Introduction
January 2014
Data Sheet DS1045
General Description
iCE40LM family is an ultra-low power FPGA and sensor manager designed for ultra-low power mobile applications, such as
smartphones, tablets and hand-held devices. The iCE40LM family includes integrated SPI & I2C blocks to interface with virtually all mobile sensors and application processors. The iCE40LM family also features two Strobe Generators that can
generates strobes in Microsecond ranges with the Low-Power Strobe Generator, and also generates strobes in Nanosecond ranges with the High-Speed Strobe Generator.
In addition, the iCE40LM family of devices includes logic to perform other functions such as mobile bridging, antenna tuning, GPIO expansion, motion/gesture recognition, IR remote control, bar code emulation and other custom functions.
The iCE40LM family features three device densities, from 1100 to 3520 Look Up Tables (LUTs) of logic with programmable
I/Os that can be used as either SPI/I2C interface ports or general purpose I/O’s. It also has up to 80 kbits of Block RAMs to
work with user logic.
Features
Flexible Logic Architecture
High Current Drive Outputs for LED
• Three devices with 1100 to 3520 LUTs
• 18 I/O pins for 25-pin WLCSP
Ultra-low Power Devices
• Advanced 40 nm ultra-low power process
• As low as 120 µW standby power typical
Embedded and Distributed Memory
• Up to 80 kbits sysMEM™ Embedded Block
RAM
• Three High Drive (HD) output in each device
• Source/sink nominal 24 mA
Flexible On-Chip Clocking
• Six low-skew global signal resource
Flexible Device Configuration
• SRAM is configured through SPI
Ultra-Small Form Factor
• As small as 25-pin WLCSP package
1.71 mm x 1.71 mm
Two Hardened I2C Interfaces
Two Hardened SPI Interfaces
Two On-Chip Strobe Generators
• Low-Power Strobe Generator
(Microsecond ranges)
• High-Speed Strobe Generator
(Nanosecond ranges)
Applications
• Smartphones
• Multi Sensor Management Applications
• Tablets and Consumer Handheld Devices
• Sensor Pre-processing & Sensor Fusion
• Handheld Commercial and Industrial Devices
• Always-On Sensor Applications
© 2014 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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1-1
DS1045 Introduction_01.3
Introduction
iCE40LM Family Data Sheet
Table 1-1. iCE40LM Family Selection Guide
Part Number
Logic Cells (LUT + Flip-Flop)
RAM4K Memory Blocks
RAM4K RAM Bits
iCE40LM1K
iCE40LM2K
iCE40LM4K
1100
2048
3520
16
20
20
80K
80K
64K
Package
Programmable I/O Count
25-pin WLCSP, 1.71 mm x 1.71 mm, 0.35 mm
18
18
18
36-pin ucBGA, 2.5 mm x 2.5 mm, 0.40 mm
28
28
28
49-pin ucBGA, 3 mm x 3 mm, 0.40 mm
37
37
37
Introduction
The iCE40LM family of ultra-low power FPGAs has three devices with densities ranging from 1100 to 3520 LookUp Tables (LUTs). In addition to LUT-based, low-cost programmable logic, these devices also feature Embedded
Block RAM (EBR), two Strobe Generators (LPSG, HSSG), two hardened I2C Controllers and two hardened SPI
Controllers. These features allow the devices to be used in low-cost, high-volume consumer and mobile applications.
The iCE40LM devices are fabricated on a 40nm CMOS low power process. The device architecture has several
features such as user configurable I2C and SPI Controllers, either as master or slave, and two Strobe Generators.
The iCE40LM FPGAs are available in very small form factor packages, with the smallest in 25-pin WLCSP. The 25pin WLCSP package has a 0.35 mm ball pitch, resulting to an overall package size of 1.71 mm x 1.71 mm that easily fits into a lot of mobile applications. Table 1-1 shows the LUT densities, package and I/O pin count.
The iCE40LM devices offer enhanced I/O features such as pull-up resistors. Pull-up features are controllable on a
“per-pin” basis.
Lattice provides a variety of design tools that allow complex designs to be efficiently implemented using the
iCE40LM family of devices. Popular logic synthesis tools provide synthesis library support for iCE40LM. Lattice
design tools use the synthesis tool output along with the user-specified preferences and constraints to place and
route the design in the iCE40LM device. These tools extract the timing from the routing and back-annotate it into
the design for timing verification.
Lattice provides many pre-engineered IP (Intellectual Property) modules, including a number of reference designs,
licensed free of charge, optimized for the iCE40LM FPGA family. Lattice also can provide fully verified bit-stream for
some of the widely used target functions in mobile device applications, such as ultra-low power sensor management, gesture recognition, IR remote, barcode emulator functions. Users can use these functions as offered by Lattice, or they can use the design to create their own unique required functions. For more information regarding
Lattice's Reference Designs or fully-verified bitstreams, please contact your local Lattice representative.
1-2
iCE40LM Family Data Sheet
Architecture
March 2016
Data Sheet DS1045
Architecture Overview
The iCE40LM family architecture contains an array of Programmable Logic Blocks (PLB), two Strobe Generators,
two user configurable I2C controllers, two user configurable SPI controllers, and blocks of sysMEM™ Embedded
Block RAM (EBR) surrounded by Programmable I/O (PIO). Figure 2-1shows the block diagram of the iCE40LM-4K
device.
Figure 2-1. iCE40LM-4K Device, Top View
I2C
I/O Bank 0
4 kbit RAM Blocks
4 kbit RAM Blocks
PLB
4 kbit RAM Blocks
LPSG
4 kbit RAM Blocks
HSSG
8 Logic Cells = Programmable Logic Block
I 2C
config
SPI
SPI
I/O Bank 2
Carry Logic
4-Input Look-up
Table (LUT)
Flip-flop with Enable
and Reset Controls
The logic blocks, Programmable Logic Blocks (PLB) and sysMEM EBR blocks, are arranged in a two-dimensional
grid with rows and columns. Each column has either logic blocks or EBR blocks. The PIO cells are located at the
top and bottom of the device, arranged in banks. The PLB contains the building blocks for logic, arithmetic, and register functions. The PIOs utilize a flexible I/O buffer referred to as a sysIO buffer that supports operation with a variety of interface standards. The blocks are connected with many vertical and horizontal routing channel resources.
The place and route software tool automatically allocates these routing resources.
In the iCE40LM family, There are two sysIO banks, one on top and one on bottom. User can connect both VCCIOs
together, if all the I/Os are using the same voltage standard. Refer to the details in later sections of this document.
The sysMEM EBRs are large 4 kbit, dedicated fast memory blocks. These blocks can be configured as RAM, ROM
or FIFO with user logic using PLBs.
Every device in the family has two user SPI ports, one of these (right side) SPI port also supports programming
and configuration of the device. The iCE40LM also includes two user I2C ports, and two Strobe Generators.
© 2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
2-1
DS1045 Architecture_01.5
Architecture
iCE40LM Family Data Sheet
PLB Blocks
The core of the iCE40LM device consists of Programmable Logic Blocks (PLB) which can be programmed to perform logic and arithmetic functions. Each PLB consists of eight interconnected Logic Cells (LC) as shown in
Figure 2-2. Each LC contains one LUT and one register.
Figure 2-2. PLB Block Diagram
Shared Block-Level Controls
Clock
Programmable Logic
Block (PLB)
Enable
FCOUT
1
Set/Reset
0
Logic Cell
Carry Logic
DFF
8 Logic Cells (LCs)
I0
D
O
Q
EN
I1
LUT
I2
SR
I3
FCIN
Four-input
Look-Up Table
(LUT)
Flip-flop with
optional enable and
set or reset controls
= Statically defined by configuration program
Logic Cells
Each Logic Cell includes three primary logic elements shown in Figure 2-2.
• A four-input Look-Up Table (LUT) builds any combinational logic function, of any complexity, requiring up to
four inputs. Similarly, the LUT element behaves as a 16x1 Read-Only Memory (ROM). Combine and cascade
multiple LUTs to create wider logic functions.
• A ‘D’-style Flip-Flop (DFF), with an optional clock-enable and reset control input, builds sequential logic functions. Each DFF also connects to a global reset signal that is automatically asserted immediately following
device configuration.
• Carry Logic boosts the logic efficiency and performance of arithmetic functions, including adders, subtracters,
comparators, binary counters and some wide, cascaded logic functions.
Table 2-1. Logic Cell Signal Descriptions
Function
Type
Input
Data signal
Input
Control signal
Signal Names
I0, I1, I2, I3
Enable
Description
Inputs to LUT
Clock enable shared by all LCs in the PLB
Input
Control signal
Set/Reset1
Asynchronous or synchronous local set/reset shared by all LCs in
the PLB.
Input
Control signal
Clock
Clock one of the eight Global Buffers, or from the general-purpose
interconnects fabric shared by all LCs in the PLB
Input
Inter-PLB signal
FCIN
Fast carry in
Output
Data signals
Output
Inter-PFU signal
O
FCOUT
LUT or registered output
Fast carry out
1. If Set/Reset is not used, then the flip-flop is never set/reset, except when cleared immediately after configuration.
2-2
Architecture
iCE40LM Family Data Sheet
Routing
There are many resources provided in the iCE40LM devices to route signals individually with related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) segments.
The inter-PLB connections are made with three different types of routing resources: Adjacent (spans two PLBs), x4
(spans five PLBs) and x12 (spans thirteen PLBs). The Adjacent, x4 and x12 connections provide fast and efficient
connections in the diagonal, horizontal and vertical directions.
The design tool takes the output of the synthesis tool and places and routes the design.
Clock/Control Distribution Network
Each iCE40LM device has six global inputs, two pins on the top bank and four pins on the bottom bank
These global inputs can be used as high fanout nets, clock, reset or enable signals. The dedicated global pins are
identified as Gxx and the global buffers are identified as GBUF[7:0]. These six inputs may be used as general purpose I/O if they are not used to drive the clock nets.
Table 2-2 lists the connections between a specific global buffer and the inputs on a PLB. All global buffers optionally
connect to the PLB CLK input. Any four of the eight global buffers can drive logic inputs to a PLB. Even-numbered
global buffers optionally drive the Set/Reset input to a PLB. Similarly, odd-numbered buffers optionally drive the
PLB clock-enable input. GBUF[7:6, 3:0] can connect directly to G[7:6, 3:0] pins respectively. GBUF4 and GBUF5
can connect to the two on-chip Strobe Generators (GBUF4 connects to LPSG, GBUF5 connects to HSSG).
Table 2-2. Global Buffer (GBUF) Connections to Programmable Logic Blocks
Global Buffer
Clock
Clock Enable
GBUF0
Yes
Yes
GBUF1
Yes
GBUF2
Yes
GBUF3
Yes
GBUF4
LUT Inputs
Yes, any 4 of 8
GBUF Inputs
Yes
GBUF5
Yes
GBUF6
Yes
GBUF7
Yes
Reset
Yes
Yes
Yes
Yes
Yes
Yes
Yes
The maximum frequency for the global buffers are shown in the iCE40LM External Switching Characteristics tables
later in this document.
Global Hi-Z Control
The global high-impedance control signal, GHIZ, connects to all I/O pins on the iCE40LM device. This GHIZ signal
is automatically asserted throughout the configuration process, forcing all user I/O pins into their high-impedance
state.
Global Reset Control
The global reset control signal connects to all PLB and PIO flip-flops on the iCE40LM device. The global reset signal is automatically asserted throughout the configuration process, forcing all flip-flops to their defined wake-up
state. For PLB flip-flops, the wake-up state is always reset, regardless of the PLB flip-flop primitive used in the
application.
2-3
Architecture
iCE40LM Family Data Sheet
sysCLOCK Phase Locked Loops (PLLs) - NOT SUPPORTED on the 25-Pin WLCSP
The sysCLOCK PLLs provide the ability to synthesize clock frequencies. The iCE40LM devices have one sysCLOCK PLL (Please note that the 25-pin WLCSP package does not support the PLL). REFERENCECLK is the reference frequency input to the PLL and its source can come from an external I/O pin, the internal strobe generator
or from internal routing. EXTFEEDBACK is the feedback signal to the PLL which can come from internal routing or
an external I/O pin. The feedback divider is used to multiply the reference frequency and thus synthesize a higher
frequency clock output.
The PLLOUT output has an output divider, thus allowing the PLL to generate different frequencies for each output.
The output divider can have a value from 1 to 64 (in increments of 2X). The PLLOUT outputs can all be used to
drive the iCE40 global clock network directly or general purpose routing resources can be used.
The LOCK signal is asserted when the PLL determines it has achieved lock and de-asserted if a loss of lock is
detected. A block diagram of the PLL is shown in Figure 2-3.
The timing of the device registers can be optimized by programming a phase shift into the PLLOUT output clock
which will advance or delay the output clock with reference to the REFERENCECLK clock. This phase shift can be
either programmed during configuration or can be adjusted dynamically. In dynamic mode, the PLL may lose lock
after a phase adjustment on the output used as the feedback source and not relock until the tLOCK parameter has
been satisfied.
The iCE40LM PLL functions the same as the PLLs in the iCE40 family. For more details on the PLL, see TN1251,
iCE40 sysCLOCK PLL Design and Usage Guide.
Figure 2-3. PLL Diagram
RESET
BYPASS
BYPASS
GNDPLL VCCPLL
REFERENCECLK
DIVR
Phase
Detector
Input
Divider
RANGE
Low-Pass
Filter
DIVQ
Voltage
Controlled
Oscillator
(VCO)
VCO
Divider
SIMPLE
DIVF
PLLOUTCORE
Feedback
Divider
Fine Delay
Adjustment
Feedback
Phase
Shifter
Fine Delay
Adjustment
Output Port
PLLOUTGLOBAL
Feedback_Path
LOCK
DYNAMICDELAY[7:0]
EXTFEEDBACK
LATCHINPUTVALUE
EXTERNAL
Low Power mode
(iCEgate enabled)
Table 2-3 provides signal descriptions of the PLL block.
2-4
Architecture
iCE40LM Family Data Sheet
Table 2-3. PLL Signal Descriptions
Signal Name
Direction
Description
REFERENCECLK
Input
Input reference clock
BYPASS
Input
The BYPASS control selects which clock signal connects to the PLLOUT output.
0 = PLL generated signal
1 = REFERENCECLK
EXTFEEDBACK
Input
External feedback input to PLL. Enabled when the FEEDBACK_PATH
attribute is set to EXTERNAL.
DYNAMICDELAY[7:0]
Input
Fine delay adjustment control inputs. Enabled when
DELAY_ADJUSTMENT_MODE is set to DYNAMIC.
LATCHINPUTVALUE
Input
When enabled, forces the PLL into low-power mode; PLL output is held
static at the last input clock value. Set ENABLE ICEGATE_PORTA and
PORTB to ‘1’ to enable.
PLLOUTGLOBAL
Output
Output from the Phase-Locked Loop (PLL). Drives a global clock network on the FPGA. The port has optimal connections to global clock
buffers GBUF4 and GBUF5.
PLLOUTCORE
Output
Output clock generated by the PLL, drives regular FPGA routing. The
frequency generated on this output is the same as the frequency of the
clock signal generated on the PLLOUTLGOBAL port.
LOCK
Output
When High, indicates that the PLL output is phase aligned or locked to
the input reference clock.
RESET
Input
Active low reset.
sysMEM Embedded Block RAM Memory
Larger iCE40LM device includes multiple high-speed synchronous sysMEM Embedded Block RAMs (EBRs), each
4 kbit in size. This memory can be used for a wide variety of purposes including data buffering, and FIFO.
sysMEM Memory Block
The sysMEM block can implement single port, pseudo dual port, or FIFO memories with programmable logic
resources. Each block can be used in a variety of depths and widths as shown in Table 2-4.
Table 2-4. sysMEM Block Configurations1
Block RAM
Configuration
and Size
WADDR Port
Size (Bits)
WDATA Port
Size (Bits)
RADDR Port
Size (Bits)
RDATA Port
Size (Bits)
MASK Port
Size (Bits)
SB_RAM256x16
SB_RAM256x16NR
SB_RAM256x16NW
SB_RAM256x16NRNW
256x16 (4K)
8 [7:0]
16 [15:0]
8 [7:0]
16 [15:0]
16 [15:0]
SB_RAM512x8
SB_RAM512x8NR
SB_RAM512x8NW
SB_RAM512x8NRNW
512x8 (4K)
9 [8:0]
8 [7:0]
9 [8:0]
8 [7:0]
No Mask Port
SB_RAM1024x4
SB_RAM1024x4NR
SB_RAM1024x4NW
SB_RAM1024x4NRNW
1024x4 (4K)
10 [9:0]
4 [3:0]
10 [9:0]
4 [3:0]
No Mask Port
SB_RAM2048x2
SB_RAM2048x2NR
SB_RAM2048x2NW
SB_RAM2048x2NRNW
2048x2 (4K)
11 [10:0]
2 [1:0]
11 [10:0]
2 [1:0]
No Mask Port
Block RAM
Configuration
1. For iCE40LM EBR primitives with a negative-edged Read or Write clock, the base primitive name is appended with a ‘N’ and a ‘R’ or ‘W’
depending on the clock that is affected.
2-5
Architecture
iCE40LM Family Data Sheet
RAM Initialization and ROM Operation
If desired, the contents of the RAM can be pre-loaded during device configuration.
By preloading the RAM block during the chip configuration cycle and disabling the write controls, the sysMEM block
can also be utilized as a ROM.
Memory Cascading
Larger and deeper blocks of RAM can be created using multiple EBR sysMEM Blocks.
RAM4k Block
Figure 2-4 shows the 256x16 memory configurations and their input/output names. In all the sysMEM RAM modes,
the input data and addresses for the ports are registered at the input of the memory array.
Figure 2-4. sysMEM Memory Primitives
Write Port
Read Port
WDATA[15:0]
RDATA[15:0]
MASK[15:0]
RADDR[7:0]
WADDR[7:0]
WE
RAM4K
RAM Block
(256x16)
RE
WCLKE
RCLKE
WCLK
RCLK
Table 2-5. EBR Signal Descriptions
Signal Name
Direction
Description
WDATA[15:0]
Input
Write Data input.
MASK[15:0]
Input
Masks write operations for individual data bit-lines.
0 = write bit; 1 = don’t write bit
WADDR[7:0]
Input
Write Address input. Selects one of 256 possible RAM locations.
WE
Input
Write Enable input.
WCLKE
Input
Write Clock Enable input.
WCLK
Input
Write Clock input. Default rising-edge, but with falling-edge option.
RDATA[15:0]
Output
Read Data output.
RADDR[7:0]
Input
Read Address input. Selects one of 256 possible RAM locations.
RE
Input
Read Enable input.
RCLKE
Input
Read Clock Enable input.
RCLK
Input
Read Clock input. Default rising-edge, but with falling-edge option.
The iCE40LM EBR block functions the same as EBR blocks in the iCE40 family. For further information on the sysMEM EBR block, please refer to TN1250, Memory Usage Guide for iCE40 Devices.
2-6
Architecture
iCE40LM Family Data Sheet
sysIO Buffer Banks
iCE40LM devices have up to two I/O banks with independent VCCIO rails. Configuration bank VCC_SPI for the SPI
I/Os is connected to VCCIO2 on the 25-pin WLCSP package.
Programmable I/O (PIO)
The programmable logic associated with an I/O is called a PIO. The individual PIOs are connected to their respective sysIO buffers and pads. The PIOs are placed on the top and bottom of the devices.
Figure 2-5. I/O Bank and Programmable I/O Cell
VCCIO
I/O Bank 0 or 2
Voltage Supply
Enabled ‘1’
Disabled ‘0’
0 = Hi-Z
1 = Output
Enabled
Pull-up
OE
VCC
VCCIO_0
Internal Core
Pull-up
Enable
I2C
I/O Bank 0
I2C
4 kbit RAM Blocks
4 kbit RAM Blocks
OUT
PAD
OUTCLK
PLB
4 kbit RAM Blocks
LPSG
4 kbit RAM Blocks
HSSG
PIO
OUTCLK
iCEGATE
HOLD
HD
IN
config
SPI
Latch inhibits
switching for
power saving
INCLK
SPI
I/O Bank 2
Gxx pins optionally
connect directly to
an associated
GBUF global
buffer
Bank
VCCIO_2
The PIO contains three blocks: an input register block, output register block iCEGate™ and tri-state register block.
To save power, the optional iCEGateTM latch can selectively freeze the state of individual, non-registered inputs
within an I/O bank. Note that the freeze signal is common to the bank. These blocks can operate in a variety of
modes along with the necessary clock and selection logic.
Input Register Block
The input register blocks for the PIOs on all edges contain registers that can be used to condition high-speed interface signals before they are passed to the device core.
Output Register Block
The output register block can optionally register signals from the core of the device before they are passed to the
sysIO buffers.
Figure 2-6 shows the input/output register block for the PIOs.
2-7
Architecture
iCE40LM Family Data Sheet
Figure 2-6. iCE I/O Register Block Diagram
PIO Pair
CLOCK_ENABLE
OUTPUT_CLK
INPUT_CLK
(1,0)
LATCH_INPUT_VALUE
D_IN_1
D_IN_0
Pad
D_OUT_1
D_OUT_0
(1,0)
0
1
OUTPUT_ENABLE
(1,0)
LATCH_INPUT_VALUE
D_IN_1
D_IN_0
Pad
D_OUT_1
D_OUT_0
(1,0)
0
1
OUTPUT_ENABLE
= Statically defined by configuration program.
Table 2-6. PIO Signal List
Pin Name
OUTPUT_CLK
I/O Type
Input
Description
Output register clock
CLOCK_ENABLE
Input
Clock enable
INPUT_CLK
Input
Input register clock
OUTPUT_ENABLE
Input
Output enable
D_OUT_0/1
Input
Data from the core
D_IN_0/1
LATCH_INPUT_VALUE
Output
Data to the core
Input
Latches/holds the Input Value
sysIO Buffer
Each I/O is associated with a flexible buffer referred to as a sysIO buffer. These buffers are arranged around the
periphery of the device in groups referred to as banks. The sysIO buffers allow users to implement a wide variety of
standards that are found in today’s systems with LVCMOS interfaces.
2-8
Architecture
iCE40LM Family Data Sheet
Typical I/O Behavior During Power-up
The internal power-on-reset (POR) signal is deactivated when VCC, VCCIO_0, VCCIO_2 and VCC_SPI (VCC_SPI is connected to VCCIO_2 on the 25-pin WLCSP and 36-pin ucBGA packages) reach the level defined in the Power-OnReset Voltage table in the DC and Switching Characteristics section of this data sheet. After the POR signal is
deactivated, the FPGA core logic becomes active. You must ensure that all VCCIO banks are active with valid input
logic levels to properly control the output logic states of all the I/O banks that are critical to the application. The
default configuration of the I/O pins in a device prior to configuration is tri-stated with a weak pull-up to VCCIO. The
I/O pins maintain the pre-configuration state until VCC and VCCIO_2 reach the defined levels. The I/Os take on the
software user-configured settings only after VCC_SPI reaches the level and the device performs a proper download/
configuration. Unused I/Os are automatically blocked and the pull-up termination is disabled.
Supported Standards
The iCE40LM sysIO buffer supports all single-ended input and output standards. The buffer supports the LVCMOS
1.8, 2.5, and 3.3 V standards. The buffer has individually configurable options for bus maintenance (weak pull-up or
none).
Table 2-7 and Table 2-8 show the I/O standards (together with their supply and reference voltages) supported by
the iCE40LM devices.
Table 2-7. Supported Input Standards
Input Standard
VCCIO (Typical)
3.3 V
2.5 V
1.8 V
Single-Ended Interfaces
LVCMOS33
Yes
LVCMOS25
Yes
LVCMOS18
Yes
Table 2-8. Supported Output Standards
Output Standard
VCCIO (Typical)
Single-Ended Interfaces
LVCMOS33
3.3
LVCMOS25
2.5
LVCMOS18
1.8
On-Chip Strobe Generators
The iCE40LM devices feature two different Strobe Generators. One is tailored for low-power operation (Low Power
Strobe Generator – LPSG), and generates periodic strobes in the Microsecond (µs) ranges. The other is tailored
for high speed operation (High Speed Strobe Generator – HSSG), and generates periodic strobes in the Nanosecond (ns) ranges.Add a paragraph:
The Strobe Generators (HSSG and LPSG) provide fixed periodic strobes, and these strobes can be used as a
clock source. When used as a clock source, the HSSG can provide strobe frequency in the range of 5 MHz - 20
MHz. The LPSG can provide strobe frequency in the range of 4 kHz - 20 kHz.
For further information on how to use the LPSG and HSSG, please refer to TN1275, iCE40LM On-Chip Strobe
Generator Usage Guide.
2-9
Architecture
iCE40LM Family Data Sheet
User I2C IP
The iCE40LM devices have two I2C IP cores. Either of the two cores can be configured either as an I2C master or
as an I2C slave. Both I2C cores have preassigned pins, or user can select different pins, when the core is used.
When the IP core is configured as master, it will be able to control other devices on the I2C bus through the preassigned pin interface. When the core is configured as the slave, the device will be able to provide I/O expansion to
an I2C Master. The I2C cores support the following functionality:
• Master and Slave operation
• 7-bit and 10-bit addressing
• Multi-master arbitration support
• Clock stretching
• Up to 400 kHz data transfer speed
• General Call support
For further information on the User I2C, please refer to TN1274, iCE40 I2C and SPI Hardened IP Usage Guide.
User SPI IP
The iCE40LM devices have two SPI IP cores. Both SPI cores have preassigned pins, or user can select different
pins, when the SPI core is used. Both SPI IP core can be configured as a SPI master or as a slave. When the SPI
IP core is configured as a master, it controls the other SPI enabled devices connected to the SPI Bus. When SPI IP
core is configured as a slave, the device will be able to interface to an external SPI master.
The SPI IP core supports the following functions:
• Configurable Master and Slave modes
• Full-Duplex data transfer
• Mode fault error flag with CPU interrupt capability
• Double-buffered data register
• Serial clock with programmable polarity and phase
• LSB First or MSB First Data Transfer
For further information on the User SPI, please refer to TN1274, iCE40 I2C and SPI Hardened IP Usage Guide.
High Drive I/O Pins
The iCE40LM family devices offer 3 High Drive (HD) outputs in each device in the family. The HD outputs are ideal
to drive LED signals on mobile application.
These HD outputs can be driven in different drive modes. The default is standard drive, which source/sink 8mA current nominally. When HD drive option is selected, these HD outputs can source/sink 24mA current nominally.
The pins on the HD I/Os are labeled with HD in it.
Power On Reset
iCE40LM devices have power-on reset circuitry to monitor VCC, VCCIO_0, VCCIO_2 and VCC_SPI voltage levels during power-up and operation. At power-up, the POR circuitry monitors these voltage levels. It then triggers download from the external Flash memory after reaching the power-up levels specified in the Power-On-Reset Voltage
table in the DC and Switching Characteristics section of this data sheet. Before and during configuration, the I/Os
are held in tri-state. I/Os are released to user functionality once the device has finished configuration.
2-10
Architecture
iCE40LM Family Data Sheet
iCE40LM Configuration
This section describes the programming and configuration of the iCE40LM family.
Device Configuration
There are various ways to configure the Configuration RAM (CRAM) including:
• From a SPI Flash (Master SPI mode)
• System microprocessor to drive a Serial Slave SPI port (SSPI mode)
For more details on configuring the iCE40LM, please see TN1248, iCE40 Programming and Configuration.
Power Saving Options
The iCE40LM devices feature iCEGate and PLL low power mode to allow users to meet the static and dynamic
power requirements of their applications. Table 2-9 describes the function of these features.
Table 2-9. iCE40LM Power Saving Features Description
Device Subsystem
Feature Description
PLL
When LATCHINPUTVALUE is enabled, forces the PLL into low-power mode; PLL output held static
at last input clock value.
iCEGate
To save power, the optional iCEGate latch can selectively freeze the state of individual, non-registered inputs within an I/O bank. Registered inputs are effectively frozen by their associated clock or
clock-enable control.
2-11
iCE40LM Family Data Sheet
DC and Switching Characteristics
March 2016
Data Sheet DS1045
Absolute Maximum Ratings1, 2, 3
Supply Voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 1.42 V
Output Supply Voltage VCCIO and VCC_SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.60 V
PLL Power Supply, VCCPLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 1.3 V
I/O Tri-state Voltage Applied. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.60 V
Dedicated Input Voltage Applied . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.60 V
Storage Temperature (Ambient). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65 °C to 150 °C
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55 °C to 125°C
1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
2. Compliance with the Lattice Thermal Management document is required.
3. All voltages referenced to GND.
Recommended Operating Conditions1
Symbol
Parameter
Min.
Max.
1.14
1.26
V
1.71
3.46
V
PLL Power Supply Voltage
1.14
1.26
V
Config SPI port Power Supply Voltage
1.71
3.46
V
Junction Temperature Industrial Operation
–40
100
°C
VCC1
Core Supply Voltage
VCCIO1, 2, 3
I/O Driver Supply Voltage
VCCPLL4
VCC_SPI5
tJIND
VCCIO_0, VCCIO_2
Units
1. Like power supplies must be tied together. VCCIO_0 to VCCIO_2 if they are at same supply voltage and if they meet the power up sequence
requirement. Please refer to Power Up Sequence section. VCC and VCCPLL are not recommended to be tied together. Please refer to
TN1252, iCE40 Hardware Checklist.
2. See recommended voltages by I/O standard in subsequent table.
3. VCCIO pins of unused I/O banks should be connected to the VCC power supply on boards.
4. For 25-pin WLCSP, PLL is not supported.
5. For 25-pin WLCSP and 36-pin ucBGA packages, VCC_SPI is connected to VCCIO_2 on the package. VCC_SPI is used to power the SPI1
ports in both configuration mode and user mode.
Power Supply Ramp Rates1, 2
Symbol
tRAMP
Parameter
Power supply ramp rates for all power supplies.
Min.
Max.
Units
0.01
10
V/ms
1. Assumes monotonic ramp rates.
2. Power up sequence must be followed. Please refer to Power Up Sequence section.
© 2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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3-1
DS1045 DC and Switching_01.6
DC and Switching Characteristics
iCE40LM Family Data Sheet
Power-On-Reset Voltage Levels1
Symbol
VPORUP
VPORDN
Parameter
Min.
Max.
Units
Power-On-Reset ramp-up trip point (circuit monitoring
VCC, VCCIO_2 and VCC_SPI)
VCC
0.67
0.99
V
VCCIO_2, VCC_SPI
0.70
1.59
V
Power-On-Reset ramp-down trip point (circuit monitoring VCC, VCCIO_2 and VCC_SPI)
VCC
—
0.66
V
VCCIO_2, VCC_SPII
—
1.59
V
1. These POR trip points are only provided for guidance. Device operation is only characterized for power supply voltages specified under recommended operating conditions.
Power Up Sequence
For all iCE40LM devices, it is required to have the VCC/VCCPLL power supply powered up before all other power
supplies. The VCC/VCCPLL has to be higher than 0.5 V before other supplies are powered from GND.
In addition, for all iCE40LM devices, it is required that VCCSPI not be the last power supply to ramp up. The VCCSPI
has to be higher than 0.5 V before the last supply is ramped.
In the required power up sequence, VCC/VCCPLL should be ramped first. Following VCC/VCCPLL, VCCSPI should be
ramped next, followed by the remaining supplies. On the 25-pin WLCSP, VCCPLL is connected to VCC, and is powered up together with VCC. On the 25-pin WLCSP and 36-pin caBGA, VCCIO_2 is connected to VCC_SPI, and should
be powered up right after VCC/VCCPLL with VCCSPI. Due to this connection, VCCIO_0 cannot connect to VCCIO_2
even if they are at the same supply voltage. The sequence is defined below:
• For 49-pin caBGA: VCC, VCCPLL, VCC_SPI, VCCIO_0 and VCCIO_2; Order of VCCIO_0 and VCCIO_2 is not important.
• For 36-pin caBGA: VCC, VCCPLL, VCC_SPI/VCCIO_2, VCCIO_0
• For 25-pin WLCSP: VCC/VCCPLL, VCC_SPI/VCCIO_2, VCCIO_0
There is no power down sequence required. However, when partial power supplies are powered down, it is
required that the above sequence is followed when these supplies are powered up again.
ESD Performance
Please contact Lattice Semiconductor for additional information.
DC Electrical Characteristics
Over Recommended Operating Conditions
Symbol
Parameter
Min.
Typ.
Max.
Units
IIL, IIH1, 3, 4
Input or I/O Leakage
0V < VIN < VCCIO + 0.2 V
Condition
—
—
+/–10
µA
C1
I/O Capacitance2
VCCIO = 3.3 V, 2.5 V, 1.8 V
VCC = Typ., VIO = 0 to VCCIO + 0.2 V
—
6
—
pf
C2
Global Input Buffer
Capacitance2
VCCIO = 3.3 V, 2.5 V, 1.8 V
VCC = Typ., VIO = 0 to VCCIO + 0.2 V
—
6
—
pf
VHYST
Input Hysteresis
VCCIO = 1.8 V, 2.5 V, 3.3 V
—
200
—
mV
–31
–72
–128
µA
Internal PIO Pull-up
Current
–3
–8
–11
—
IPU
VCCIO = 1.8 V, 0= L)
188
0 pF
VCCIO/2
VOL
VCCIO/2
VOH
LVCMOS (H -> Z)
VOH - 0.15
VOL
LVCMOS (L -> Z)
VOL - 0.15
VOH
Note: Output test conditions for all other interfaces are determined by the respective standards.
3-9
iCE40LM Family Data Sheet
Pinout Information
March 2016
Data Sheet DS1045
Signal Descriptions
Signal Name
Function
I/O
Description
VCC
Power
—
Core Power Supply
VCCIO_0,
VCCIO_2
Power
—
Power for I/Os in Bank 0 and 2.
VCC_SPI
Power
—
Power supply for SPI1 ports. For 25-pin WLCSP and
36-pin ucBGA packages, this signal is connected to
VCCIO_2.
VCCPLL
Power
—
Power supply for PLL. For 25-pin WLCSP, this is connected internally to VCC.
GROUND
—
Ground
CRESETB
Configuration
I
Configuration Reset, active LOW. No internal pull-up
resistor. Either actively driven externally or connect
an 10 kOhm pull-up to VCCIO_2.
CDONE
Configuration
I/O
Configuration Done. Includes a weak pull-up resistor
to VCCIO_2.
Configuration
I/O
This pin is shared with device configuration. During
configuration:
In Master SPI mode, this pin outputs the clock to
external SPI memory.
In Slave SPI mode, this pin inputs the clock from
external processor.
General I/O
I/O
In user mode, after configuration, this pin can be programmed as general I/O in user function [HD]=High
Drive I/O.
Configuration
Output
This pin is shared with device configuration. During
configuration:
In Master SPI mode, this pin outputs the command
data to external SPI memory.
In Slave SPI mode, this pin connects to the MISO pin
of the external processor.
General I/O
I/O
In user mode, after configuration, this pin can be programmed as general I/O in user function [HD]=High
Drive I/O.
Configuration
Input
This pin is shared with device configuration. During
configuration:
In Master SPI mode, this pin receives data from external SPI memory.
In Slave SPI mode, this pin connects to the MOSI pin
of the external processor.
General I/O
I/O
In user mode, after configuration, this pin can be programmed as general I/O in user function [HD]=High
Drive I/O.
Power Supplies
GND/GNDPLL
Configuration
Config SPI
Primary
Secondary
PIOB_xx[HD]
SPI_SCK
PIOB_xx[HD]
PIOB_xx[HD]
SPI_SDO
SPI_SI
© 2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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4-1
DS1045 Pinout Information_01.4
Pinout Information
iCE40LM Family Data Sheet
Signal Name
Function
I/O
Configuration
I/O
This pin is shared with device configuration. During
configuration:
In Master SPI mode, this pin outputs to the external
SPI memory.
In Slave SPI mode, this pin inputs from the external
processor.
General I/O
I/O
In user mode, after configuration, this pin can be programmed as general I/O in user function [HD]=High
Drive I/O.
General I/O
I/O
In user mode, after configuration, this pin can be programmed as general I/O in user function.
Global
Input
Global input used for high fanout, or clock/reset net.
The G0 pin drives the GBUF0 global buffer.
General I/O
I/O
In user mode, after configuration, this pin can be programmed as general I/O in user function.
Global
Input
Global input used for high fanout, or clock/reset net.
The G1 pin drives the GBUF1 global buffer.
General I/O
I/O
In user mode, after configuration, this pin can be programmed as general I/O in user function.
Global
Input
Global input used for high fanout, or clock/reset net.
The G3 pin drives the GBUF3 global buffer.
General I/O
I/O
In user mode, after configuration, this pin can be programmed as general I/O in user function.
Global
Input
Global input used for high fanout, or clock/reset net.
The G4 pin drives the GBUF4 global buffer.
General I/O
I/O
In user mode, after configuration, this pin can be programmed as general I/O in user function.
Global
Input
Global input used for high fanout, or clock/reset net.
The G5 pin drives the GBUF5 global buffer.
General I/O
I/O
In user mode, after configuration, this pin can be programmed as general I/O in user function.
Global
Input
Global input used for high fanout, or clock/reset net.
The G6 pin drives the GBUF6 global buffer.
PIOT_xx
General I/O
I/O
In user mode, with user's choice, this pin can be programmed as I/O in user function in the top (xx = I/O
location).
PIOB_xx
General I/O
I/O
In user mode, with user's choice, this pin can be programmed as I/O in user function in the bottom (xx =
I/O location) [HD]=High Drive I/O.
PIOB_xx[HD]
SPI_SS_B
Description
Global Signals
Primary
Secondary
PIOT_xx
G0
PIOT_xx
PIOT_xx
PIOT_xx
PIOT_xx
PIOB_xx
G1
G3
G4
G5
G6
LED Signals
4-2
Pinout Information
iCE40LM Family Data Sheet
Pin Information Summary
iCE40LM-1K
Pin Type
General Purpose I/O Per Bank
SWG25 CM36
iCE40LM-2K
CM49 SWG25 CM36
iCE40LM-4K
CM49 SWG25 CM36
CM49
Bank 0
7
15
20
7
15
20
7
15
20
Bank 21
11
13
17
11
13
17
11
13
17
Total General Purpose I/Os
18
28
37
18
28
37
18
28
37
Vcc
1
1
2
1
1
2
1
1
2
Bank 0
1
1
1
1
1
1
1
1
1
Bank 2
1
1
1
1
1
1
1
1
1
VCC_SPI
0
0
1
0
0
1
0
0
1
VCCPLL
0
1
1
0
1
1
0
1
1
Miscellaneous Dedicated Pins
2
2
2
2
2
2
2
2
2
GND
2
2
4
2
2
4
2
2
4
Vccio
NC
0
0
0
0
0
0
0
0
0
Reserved
0
0
0
0
0
0
0
0
0
25
36
49
25
36
49
25
36
49
0
0
0
0
0
0
0
0
0
Total Balls
SPI Interfaces
Bank 0
Bank 2
1
1
1
2
2
2
2
2
2
I2C Interfaces
Bank 0
1
1
1
2
2
2
2
2
2
Bank 2
0
0
0
0
0
0
0
0
0
1. Including General Purpose I/Os powered by VCC_SPI and VCCPLL.
4-3
iCE40LM Family Data Sheet
Ordering Information
March 2014
Data Sheet DS1045
iCE40LM Part Number Description
iCE40LMXXX - XXXXXXX
Device Family
iCE40LM FPGA
Shipping Method
TR = Tape and Reel
TR1K = Tape and Reel 1,000 units
Logic Cells
1K = 1,100 Logic Cells
2K = 2,048 Logic Cells
4K = 3,520 Logic Cells
Package
SWG25 = 25-Ball WLCSP (0.35 mm Ball Pitch)
SWG25TR1K = 25-Ball WLCSP (0.35 mm Ball Pitch)
in tape and reel 1,000 units
CM36 = 36-Ball ucBGA (0.4mm Ball Pitch)
CM36TR1K = 36-Ball ucBGA (0.4mm Ball Pitch)
in tape and reel 1,000 units
CM49 = 49-Ball ucBGA (0.4mm Ball Pitch)
CM49TR1K = 49-Ball ucBGA (0.4mm Ball Pitch)
in tape and reel 1,000 units
All parts are shipped in tape-and-reel.
Ordering Part Numbers
Part Number
LUTs
Supply Voltage
Package
Leads
Temp.
iCE40LM1K-SWG25TR
1100
1.2 V
Halogen-Free caBGA
25
IND
iCE40LM1K-SWG25TR1K
1100
1.2 V
Halogen-Free caBGA
25
IND
iCE40LM1K-CM36TR
1100
1.2 V
Halogen-Free ucBGA
36
IND
iCE40LM1K-CM36TR1K
1100
1.2 V
Halogen-Free ucBGA
36
IND
iCE40LM1K-CM49TR
1100
1.2 V
Halogen-Free ucBGA
49
IND
iCE40LM1K-CM49TR1K
1100
1.2 V
Halogen-Free ucBGA
49
IND
iCE40LM2K-SWG25TR
2048
1.2 V
Halogen-Free caBGA
25
IND
iCE40LM2K-SWG25TR1K
2048
1.2 V
Halogen-Free caBGA
25
IND
iCE40LM2K-CM36TR
2048
1.2 V
Halogen-Free ucBGA
36
IND
iCE40LM2K-CM36TR1K
2048
1.2 V
Halogen-Free ucBGA
36
IND
iCE40LM2K-CM49TR
2048
1.2 V
Halogen-Free ucBGA
49
IND
iCE40LM2K-CM49TR1K
2048
1.2 V
Halogen-Free ucBGA
49
IND
iCE40LM4K-SWG25TR
3520
1.2 V
Halogen-Free caBGA
25
IND
iCE40LM4K-SWG25TR1K
3520
1.2 V
Halogen-Free caBGA
25
IND
iCE40LM4K-CM36TR
3520
1.2 V
Halogen-Free ucBGA
36
IND
iCE40LM4K-CM36TR1K
3520
1.2 V
Halogen-Free ucBGA
36
IND
iCE40LM4K-CM49TR
3520
1.2 V
Halogen-Free ucBGA
49
IND
iCE40LM4K-CM49TR1K
3520
1.2 V
Halogen-Free ucBGA
49
IND
© 2014 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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5-1
DS1045 Order Info_01.4
iCE40LM Family Data Sheet
Supplemental Information
January 2014
Data Sheet DS1045
For Further Information
A variety of technical notes for the iCE40 family are available on the Lattice web site.
• TN1248, iCE40 Programming and Configuration
• TN1274, iCE40 I2C and SPI Hardened IP Usage Guide
• TN1275, iCE40LM On-Chip Strobe Generator Usage Guide
• TN1276, Advanced iCE40 I2C and SPI Hardened IP Usage Guide
• TN1250, Memory Usage Guide for iCE40 Devices
• TN1251, iCE40 sysCLOCK PLL Design and Usage Guide
• iCE40LM Pinout Files
• iCE40LM Pin Migration Files
• Thermal Management document
• Lattice design tools
• Schematic Symbols
© 2014 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
6-1
DS1045 Further Info_01.1
iCE40LM Family Data Sheet
Revision History
March 2016
Data Sheet DS1045
Date
Version
Section
Change Summary
March 2016
1.6
Architecture
Updated Typical I/O Behavior During Power-up section. Indicated 36-pin
ucBGA in package in description.
DC and Switching
Characteristics
Updated Recommended Operating Conditions1 section. Revised footnote 5.
Pinout Information
Updated Signal Descriptions section. General update of signal names
and descriptions.
March 2015
1.5
DC and Switching
Characteristics
Updated sysIO Single-Ended DC Electrical Characteristics section.
Changed LVCMOS 3.3 and LVCMOS 2. 5 VOH Min. (V) from 0.5 to 0.4.
August 2014
1.4
DC and Switching
Characteristics
Updated the Recommended Operating Conditions section. Added VCC
and VCCPLL information to footnote 1.
Updated Power Up Sequence section.Revised and added information
on required power up sequence.
March 2014
1.3
Ordering Information
01.2
Architecture
Updated Ordering Part Numbers section. Changed packages from
csBGA to ucBGA.
Updated Typical I/O Behavior During Power-up section. Added VCCIO_0
to the first statement.
Updated Power On Reset section. Added VCCIO_0 to the first statement.
Ordering Information
Updated iCE40LM Part Number Description section. Added shipping
method and packages.
Added part numbers in Ordering Part Numbers section.
January 2014
01.1
All
Introduction
October 2013
01.0
September 2013 00.2 EAP
August 2013
00.1 EAP
Updated document status from Advance.
Updated device features.
DC and Switching
Characteristics
Updated the following tables:
— sysCLOCK PLL Timing – Preliminary
— Supply Current
— sysCONFIG Port Timing Specifications.
Pinout Information
Updated SPI and Config SPI Ports information in Signal Descriptions
table.
All
General updates for product launch.
Pinout Information
Updated ball map to 25-pin WLCSP.
All
General updates to all sections.
All
Initial release.
© 2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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7-1
DS1045 Revision History
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