ICE40LP1K-BLINK-EVN

 iCEblink40-LP1K Evaluation Kit User’s Guide September 2012 Revision: EB75_01.1  iCEblink40-LP1K Evaluation Kit User’s Guide Introduction Thank you for choosing the Lattice Semiconductor iCEblink40™-LP1K Evaluation Kit. This guide describes how to begin using the iCEblink40-LP1K Evaluation Kit, an easy-to-use platform for rapidly prototyping designs using the iCE40™ FPGA. Features • Ultra low-power iCE40LP1K FPGA • USB programming, debugging, virtual I/O functions, and power supply • Four user LEDs • Four capacitive-touch buttons • 3.3 MHz clock source • 1Mbit SPI serial configuration PROM • Supported by Lattice iCEcube2™ design software • 63 LVCMOS/LVTTL (3.3V) digital I/O connections on 0.1” through-hole connections • Supports third-party I/O expansion boards and modules, including 3.3V Arduino Shield boards (requires additional sockets, not supplied) Figure 1. iCEblink40 LP1K Evaluation Board and Major Hardware Features USB Programming, Debug and Power Ultra-Low Power iCE40 FPGA 63 User I/O Pins (3.3V) Capacitive Touch Buttons User LEDs Software Requirements Before using the iCEblink40 board, please be sure to download and install iCEcube2 Release 2011.12 or later. This and later versions include the programming software for the iCEblink40 board. Currently, the programming software is only available for the Windows operating system. http://www.latticesemi.com/products/designsoftware/icecube2/downloads.cfm During the installation process, be sure to install the Adept USB Programming Software, as shown in Figure 2. 2 iCEblink40-LP1K Evaluation Kit User’s Guide 1. Make sure that Adept USB Programming Software is checked. This is the default setting. 2. Click Next. Figure 2. Select the Adept Programming Software for Installation 1 2 A few steps later, select the installation for the Adept programming software, as shown in Figure 3. 3. Make sure that both the Adept Runtime and Adept Application options are checked, which are the default settings. 4. Click Next. Figure 3. Adept Setup Options 3 4 Connecting to the iCEblink40 Evaluation Board Before connecting the iCEblink40 board, be sure to download and install a supported version of the iCEcube2 software. Connect the iCEblink40 evaluation board to your PC using the USB cable provided. The USB connector on the board is labeled with reference designator J3 and is located in the upper left corner. Once connected, the red 3 iCEblink40-LP1K Evaluation Kit User’s Guide power-good LED (LD5) adjacent to the USB connector illuminates. See Figure 4 to locate the power-good LED. Power and Configuration Status LEDs The iCEblink40 evaluation board has two status LEDs, as shown in Figure 4. These two status LEDs indicate the current status of the iCEblink40 board, as listed in Table 1. The red LED, LD5, located near the USB connector indicates if the USB power supply, the 3.3V supply, and the 1.2V supply are within the specified ranges. The yellow LED, LD6, located below the FPGA indicates whether the FPGA is configured properly. This LED lights up when the FPGA is correctly loaded with a valid bitstream. Figure 4. iCEblink40 Status LEDs Power-Good LED (LD5) (Red LED) iCE40 LP1K QN84 FPGA Configuration Done LED (LD6) (Yellow LED) Table 1. iCEblink40 Status LED Descriptions Power-Good LED (LD5) On Configuration DONE LED (LD6) On Off Off On Off Off On Description The board is powered, the FPGA successfully configured and the FPGA application is operating. Board is unpowered. Connect the board to a computer USB port, a powered hub, or a USB-based wall plug. If board is plugged in and previously operating, indicates that an SPI Flash programming operation is in progress The board is powered but the FPGA is not yet configured. ACTION: Program the onboard SPI Flash PROM with a valid FPGA configuration bitstream. ERROR: The board is powered but there is a problem with the USB power supply or with the on-board regulator. 4 iCEblink40-LP1K Evaluation Kit User’s Guide Pre-programmed Demonstration Design The iCEblink40 board comes preprogrammed with a demonstration application. The application supports two interfaces. 1. Control the LEDs from the four capacitive touch buttons on the board itself. 2. Control the LEDs and other internal logic using the USB-based I/O expansion interface. Operating the Capacitive Touch Buttons Upon power up, the green LEDs on the board scroll in an upward pattern, as described in Figure 5. Pressing any of the capacitive touch buttons stops the LEDs from scrolling and places the board in a different operating mode. Figure 5. Preprogrammed Demonstration Design LEDs Scroll Upward 1. Power On Green LEDs scroll upward. 2. Press any button to enter LED Toggle Mode. Toggle LED with Button Press 3. Press a button to toggle the associated LED on or off. If no button is pressed within five seconds, the board returns to Scroll LEDs Mode. In the second operating mode, toggle individual LEDs on and off by pressing the associated capacitive touch button. If no button was pressed during the last five seconds, the board returns to scrolling the LEDs. The demonstration application is available for download from the Lattice website at:  www.latticesemi.com/iceblink40-LP1K. Virtual I/O Expansion Debugging Interface The iCEblink40 board is powered and programmed via the USB interface. Additionally, the USB interface also provides a convenient means to monitor and control logic inside the FPGA, as shown in Figure 6. The USB controller drives a byte-wide parallel port expander implemented within the FPGA, controlled by software running on the PC. The Digilent ADEPT2 I/O Expansion screen, shown in Figure 7, provides a mix of virtual switches, pushbuttons, LEDs, light bars, and 32-bit input and outputs. 5 iCEblink40-LP1K Evaluation Kit User’s Guide Figure 6. iCEblink40 Board Supports Virtual I/O Connections over USB Debug I/O Expansion Core Debug I/O Expansion Core DB LightBar[23:0] ASTB USB Controller LEDs[7:0] Data[7:0] Address Strobe FromFPGA[31:0] DSTB Data Strobe WRITE Read/#Write WAIT To/From FPGA Switches[15:0] Buttons[15:0] Wait ToFPGA[31:0] FPGA Control and monitor FPGA logic values in real-time, over USB, from PC graphical interface Digilent Adept 2 Figure 7. Digilent Adept 2 I/O Expansion Interface and FPGA Connections VLightBar To FPGA [31:0] From FPGA [31:0] 23 0 VLEDs 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 2 1 0 VButtons VSwitches 7 7 6 5 4 3 2 1 6 5 4 3 0 Using the Virtual I/Os in the Demo Application By default, the virtual I/Os are disconnected and the USB controller’s I/O connections to the FPGA are high-impedance (Hi-Z). To connect the virtual I/O, perform the following steps outlined in Figure 8. 1. From the Windows Start menu, select Start > All Program > Digilent > Adept > Adept. 2. Ensure that the Adept interface connects to the iCE40. 3. Click the I/O Ex tab. 6 iCEblink40-LP1K Evaluation Kit User’s Guide 4. Click Start I/O. Remember, the associated I/O Expander design must be part of the compiled FPGA design before the Virtual I/Os work. 5. If the virtual I/O expansion design is functioning correctly, the green virtual status LED will turn from red to green. Figure 8. Starting the Digilent Adept Virtual I/O Expansion Application 2 3 4 5 To disconnect the virtual I/O interface, simply click the Stop I/O button in the graphical interface. Controlling the Physical LEDs from Virtual I/Os in the Demonstration Design When active, the virtual I/Os optionally control the physical LEDs on the board, as shown in Figure 9. For example, with the virtual I/Os active, change the position of virtual switch [7] (the bottom left switch in the graphical interface). Note how the physical LEDs on the board change direction. Change virtual switch [6] to the up position. Now, the physical LEDs are controlled by the virtual switches [3:0] and virtual pushbuttons [3:0]. The values of the virtual switches are XORed together inside the FPGA. The virtual slide switches set a specific value for the physical LEDs. The pushbutton momentarily inverts the value while the virtual pushbutton is pressed in the graphical interface. 7 iCEblink40-LP1K Evaluation Kit User’s Guide Figure 9. Controlling the Physical LEDs from Virtual I/O Virtual Switches [7] [3] [2] [1] [0] Virtual Pushbuttons [6] [3] [2] [1] [0] 1: Scroll down 0: Scroll up 1: Control LEDs from Virtual I/Os 0: Control LEDs from FPGA LD2 BTN1 LD3 BTN2 LD4 BTN3 LD5 BTN4 Physical Buttons and LEDs Direction Controlling the Virtual Light Bar in the Demonstration Design When the virtual I/Os are active, the virtual light bar lights up from left to right, controlled by logic inside the FPGA. The virtual pushbuttons [15] and [14] control the light bar. Pushbutton [15] resets the light bar, clearing all the lights. Pushbutton [14] forces the light bar to hold its current value. Figure 10. Controlling the Virtual Light Bar Lights Up from Left to Right Light Bar [15] [14] Reset Light Bar Hold Value Controlling the Virtual LEDs in the Demonstration Design The virtual I/O interface includes eight, round, green LEDs, as shown in Figure 11. The values displayed on these virtual LEDs depends on the settings of virtual switches [9] and [8]. The eight LEDs are separated into left and right halves. When both virtual switches [9] and [8] are Low—the down position—the left LEDs echo the scrolling pattern of the LEDs, regardless if a physical cap-sense button was pressed. Use virtual switch [7] to reverse the direction of these LEDs. The right-most LEDs show the current toggle status of the four physical cap-sense buttons. Changing virtual switch [8] to High—the up position—the four left-most LEDs then show the current value of the time-out counter than marks the five seconds after pressing a cap-sense button. Press a cap-sense button to reset the timer and note that the toggle status of the physical button changes on the right-most LEDs. The timer resets each time a physical button is pressed. Wait five seconds and the physical LEDs change back to the scrolling pattern. 8 iCEblink40-LP1K Evaluation Kit User’s Guide Figure 11. Controlling the Virtual LEDs LEDs [9] [8] [9] [8] [9] [8] Scrolling LED pattern Cap-sense time-out counter [3] [2] [1] [0] Toggle value of physical cap-sense buttons (push button to change) [3] [2] [1] [0] When virtual switch [9] is High—in the up position—then the left LEDs are controlled by virtual switches [3:0] and the right LEDs are controlled by virtual pushbuttons [3:0]. Virtual Values to and from FPGA in the Demonstration Design The virtual I/O interface also includes a 32-bit value from the FPGA logic and a 32-bit value to the FPGA logic, as shown in Figure 12. Two virtual switches, [14] and [15], control the behavior in of the virtual 32-bit values in the demonstration design. Figure 12. Virtual Values to and from the FPGA To FPGA 0x1000ffff From FPGA efff0000 Send Format: Hexadecimal [15] [14] No function Continuously increment No function Continuously decrement Input value One’s complement of input value Input value Reverse bit order of input value [15] [14] [15] [14] [15] [14] [13] Reset Clocking Resources The iCEblink40 board includes a Linear Technology LT1799 oscillator (X1 on the board and in the schematic) to generate a 3.33 MHz clock. FPGA Input The output from the LT1799 oscillator feeds pin A9 of the iCE40LP1K FPGA. FPGA pin A9 is also the global buffer input GBIN7. 9 iCEblink40-LP1K Evaluation Kit User’s Guide Supporting Other Frequencies On the iCEblink40 board, the LT1799 produces a 3.3 MHz clock output by default. Other frequencies are possible via simple modifications of the board using the 1x3 connections on JP2, as listed in Table 2. Table 2. Selecting Other Oscillator Frequencies Using Jumper JP2 Clock Frequency JP2 Setting Jumper Position 3.33 MHz (default) None 333 kHz Upper Position 33.3 MHz Lower Position User LEDs The iCEblink40 iCE40LP1K evaluation board includes four green user LEDs, located along the left side of the board, as shown in Figure 1. Operation To light a user LED, drive the associated FPGA pin High, as shown in Table 3. To darken the LED, drive the associated FPGA pin Low. Table 3. User LED Operation Operation FPGA Action Light LED Drive High (1) Darken LED Drive Low (0) The LEDs may appear to glow slightly before the FPGA is configured or if the FPGA pin is unused. This is because the FPGA I/Os have a soft pull-up resistor which may provide just enough current for the LED to glow dimly. To completely turn off an LED, drive it Low. FPGA Connections The FPGA drives the user LEDs using the FPGA pins listed in Table 4. These same signals also connect to the J12 header located in the lower left corner. 10 iCEblink40-LP1K Evaluation Kit User’s Guide Table 4. User LED Connections Designator Location FPGA Pin Header Connections LD1 LD1 [A29] A29 J12.1 LD2 LD2 [B20] B20 J12.2 LD3 LD3 [B19] B19 J12.3 LD4 LD4 [A25] A25 J12.4 Capacitive Touch Buttons The iCEblink40 iCE40LP1K evaluation board has four capacitive-touch buttons, located toward the left side of the board, as shown in Figure 1. These buttons have dedicated connections only to the FPGA. These signals go nowhere else on the board and are not available on any of the breakout headers. FPGA Connections Table 5 lists the four capacitive touch buttons on the iCEblink40 board and the associated FPGA pins. Table 5. Capacitive Touch Buttons Designator Location FPGA Pin BTN1 BTN1 [B22] B22 BTN2 BTN2 [B21] B21 BTN3 BTN3 [A27] A27 BTN4 BTN4 [A26] A26 Operation Figure 13 shows the circuit used for each capacitive-touch button. Each button is attached to one I/O pin on the FPGA. Each signal line includes a 100 k pull-up resistor to 3.3V and a 100 pF capacitor down to ground. Figure 13. Example Capacitive Touch Button Circuit I/O Pin Capacitive Touch Button Sample 100 kΩ Value 100 pF Figure 15 shows the general overall flowchart for the demonstration design to read the value on a capacitive touch button. The sampling signal drives the voltage on the capacitive-touch button to ground in order to bleed of any residual charge as shown in Figure 14. After a period of time, depending on the button sample frequency, the button is allowed to float High. Once the FPGA output goes to Hi-Z (high-impedance, floating, three-state), the 100k pull-up resistor to 3.3V charges the 100 pF capacitor. After about an RC time constant ( or tau), the voltage on the pad exceeds the input switching threshold of the FPGA. A finger pressed against the capacitive-touch button adds about another 5 pF of capacitance, increasing the RC constant and delaying the Low-to-High transition for a pressed button. 11 iCEblink40-LP1K Evaluation Kit User’s Guide Figure 14. Capacitive Touch Timing Examples Sampling Signal Drive pad to ground Button: No Finger Allow pad to float High Switching Threshold Button Value: No Finger τ = RCBUTTON Time delta between pressed and unpressed button ~300-500 ns Button: Finger Press Switching Threshold τ = R(CBUTTON + CFINGER) Button Value: Finger Press The switching time difference between an unpressed and one or more pressed buttons is roughly 300 to 500 ns. Using the 3.33 MHz input, this amounts to a one clock delay difference between an unpressed and pressed buttons. The simple circuit used on the iCEblink40 board detects simultaneous button presses on up to three of the capacitive-touch buttons. Pressing all four buttons is the same as pressing no buttons. 12 iCEblink40-LP1K Evaluation Kit User’s Guide Figure 15. iCEblink40 Demo Application Capacitive Touch Button Flowchart Start Drive pin connected to capacitive button Low long enough to guarantee that the pin is at GND, despite the attached RC network. Force pin to Hi-Z. The external pull-up resistor pulls the pin High and charges the capacitor. Did any pin go High? Yes Wait one 3.3 MHz clock period (300 ns). Sample all pin values. Yes No Are all buttons High? Did pin value change from last sample? Yes Toggle pin value 13 iCEblink40-LP1K Evaluation Kit User’s Guide User I/O Connections Figure 16 shows the location of the 3.3V-compatible digital I/O connections on the iCEblink40 board. Each connection shows the pin number of the FPGA I/O pin that attaches to the connection. Likewise, Table 6 lists the various I/O headers and their designed usage. Figure 16. Location of the 3.3V Digital I/O Connections and the FPGA Pin Number [ A5] GND [ B2] [ B1] [ A1] [ A47] [ A46] [ A45] [ A44] [ B32] [ A41] [ A40] [ A39] [ A35] [ A34] [ A33] [ B34] [ A43] [ B31] [ B30] [ B29] [ A38] [ B27] [ B26] 3.3V Arduino Shield compatible [ B4] [ B3] [ A4] [ A3] [ A2] [ A48] [ B36] [ B35] Digital I/ O (3.3V) Digital I /O (3.3V) 3.3V GND [ B8] [ A10 ] [ B9] [ A11 ] [ B5] [ A8] [ B7] PMOD SPI PROM Connections [ B18 ] [ B17 ] [ A22 ] [ A23 ] GND 3.3V PMOD PMOD12 3.3V GND PMOD [ A16 ] [ A14 ] [ A13 ] [ A12 ] PMOD [ B10] [ B12] [ B14] [ B15] [ B23] [ A32] PMOD12 Digilent 2x6 header Digilent 1x6 header Digital I /O (3.3V) 14 PMOD PMOD Clocks User LEDs PMOD12 [ B11] [ B13] [ A19] [ A20] [ A31] [ B24] GND 3.3V [ A9] [ A16 ] PMOD GND 3.3V [ A25] [ B19] [ B20] [ A29] PMOD iCEblink40-LP1K Evaluation Kit User’s Guide Table 6. Digital I/O Headers and Their Functions I/O Header Group Header Type Location Function J2 2x8 0.1” centers Top edge, middle 3.3V digital I/O. Compatible with 3.3V Arduino Shield boards. J4 2x8 0.1” centers Top edge, left side 3.3V digital I/O. Compatible with 3.3V Arduino Shield boards. J1 2x6 0.1” centers Left edge, top 3.3V digital I/O. 3.3V digital I/O. Compatible with Digilent 1x6 and 2x6 PMod modules. Also supports double PMod12 modules when used with header J6. J6 1x6 0.1” centers Left edge, bottom 3.3V digital I/O. Compatible with Digilent 1x6 PMod modules. J7 1x6 0.1” centers offset Left edge, top Production programming of USB controller. J11 1x6 0.1” centers offset Middle, toward left 3.3V digital I/O. Connections between the mobile FPGA and the SPI PROM. Compatible with Digilent 1x6 PMod modules. J5 2x8 0.1” centers Bottom edge, right side 3.3V digital I/O. Portions compatible with Digilent 1x6 and 2x6 PMod modules. Portions also compatible with 3.3V Arduino Shield boards. JP3 1x2 0.1” centers Middle, to left of FPGA 3.3V digital I/O. Clock connections from the LTC1799 oscillator (GBIN7) and possible into GBIN2. J12 1x6 0.1” centers Bottom edge, left side 3.3V digital I/O. Connections to the user LED I/O. Compatible with Digilent 1x6 Pmod modules. Supported Pmod Peripheral Modules As shown in Figure 16, the iCEblink40 board supports a variety of Pmod peripheral modules for easy I/O expansion. Table 7 lists the 0.1” through-hole headers on the iCEblink40 board that support Pmod modules. Pmod modules come in a few different form factors and each Pmod header includes power and ground supplies. Figure 17 shows the how the different Pmod form factors interrelate. The easiest way to support a Pmod module is to add the appropriate female socket listed, or an equivalent. Straight-through or right-angle through-hole sockets are listed. Male headers are also possible solutions when using the interface cable provided with most Pmod modules. Table 7. Pmod Module Headers Female Socket (Manufacturer/Part Number) Header Straight-through Right-angle 1x6 header on 0.1” centers. A six-pin Pmod header. Sullins Connector Solutions PPPC061LFBN-RC Sullins Connector Solutions PPPC061LGBN-RC J1 2x6 header on 0.1” centers. A Pmod12 header that also supports two six-pin Pmod modules. Sullins Connector Solutions PPPC062LFBN-RC Sullins Connector Solutions PPPC062LJBN-RC J5 2x8 header on 0.1” centers. The left side of header J5 forms a Pmod12 header, as shown in Figure 16. A 2x6 header similar to J1 can also be used but must be mounted toward the right end of the holes as marked. Sullins Connector Solutions PPPC082LFBN-RC Sullins Connector Solutions PPPC082LJBN-RC J6, J12 Type As shown in Figure 17, a Pmod module has six connections—four I/O plus power and ground. A Pmod12 module has 12 connections and the module is effectively two six-pin Pmod modules stacked together. Most of the Pmod modules also include interface cables to allow easy connection to other header types. 15 iCEblink40-LP1K Evaluation Kit User’s Guide Figure 17. Pmod Module Types 1 Pmod12 Pmod Pmod 1 3.3V I/O 3.3V I/O GN D Pmod GND Pmod12 For a complete list of Pmod peripheral modules, visit the Digilent web site. www.digilentinc.com/Products/Catalog.cfm?NavPath=2,401&Cat=9 Arduino Shield Board Support The iCEblink40 board also mechanically and electrically supports select 3.3V Arduino Shield boards popular in the microcontroller development community. The Shield connections are located on headers J4, J2, J8 and a portion of J5 as shown in Figure 18. Headers jumper J4 and J2 are 3.3V digital I/O connections. Header J8 provides power connections to the Shield board. The left side of header J5 also provides 3.3V digital I/O but the 3.3V and GND connections do not connect to the Shield board. Figure 18. Arduino Shield Board Connections Arduino Shield Connections Required Header Sockets To support Arduino Shield boards, the indicated headers must be loaded with female socket headers on 0.1” headers, as listed in Table 8. Table 8. Sockets to Support Arduino Shield Boards Header(s) Description Quantity Manufacturer/Part Number J2, J4, J5 2x8 female header socket on 0.1” centers 3 Sullins Connector Solutions PPPC082LFBN-RC J8 1x6 female header socket on 0.1” centers 1 Sullins Connector Solutions PPPC061LFBN-RC 16 iCEblink40-LP1K Evaluation Kit User’s Guide Tested Arduino Boards Figure 19 shows the Arduino Shield boards have been tested for basic compatibility. Other Arduino Shield boards may also be compatible. Figure 19. Compatible Arduino Shield Boards chipKITBasic I/O Shield chipKIT Pmod Shield-Uno USB Interface The iCEblink40 board is powered by connecting the board to a computer USB port, a power USB hub, or a USBbased AC adapter, commonly used in consumer electronics. A typical USB port provides up to 500 mA at 5V, providing up to 2.5W of total power. The iCE40LP1K consumes SIGNIFICANTLY LESS power, even when operating at full performance. However, be careful when using the board to power off-board peripheral funds. Connector The USB connector to the board is located in the upper left corner, labeled J3. The board connects using a standard USB cable with a male mini-B connector. Power Supply Figure 20 shows the iCEblink40 power supply circuit that derives power from the USB mini-B connector (J3). The USB connector provides up to 500 mA at +5V DC. An Analog Devices ADP2140 regulator generates +1.2V for the FPGA core VCC and +3.3V for all I/O connections. The regulator also indicates when power is good and lights up the red power-good LED (LD5). Figure 20. iCEblink40 USB Power Supply Circuit Power-Good LED (LD5) Mini-B USB Connector (J3) +5V (500 mA) (JP1) Analog Devices +1.2V VCC ADP2140 (300 mA) Voltage Regulator +3.3V (600 mA) iCE40LP1K FPGA VCCIO Configuration Done LED (LD6) 17 iCEblink40-LP1K Evaluation Kit User’s Guide Jumper JP1 provides a convenient location from which to measure core power to the FPGA. SPI Flash Programming The USB interface also provides Flash programming for the on-board SPI PROM, as described in “Programming the iCEblink40 Board” below. Digilent Parallel Port (DPP) The Digilent Parallel Port (DPP) interface is used for virtual I/O and debugging using a USB connection to the board from a Windows PC. See “Virtual I/O Expansion Debugging Interface” on page 5 for additional information. 1Mbit SPI Configuration PROM The configuration bitstream for the iCE40 FPGA is stored in a M25P10A 1Mbit SPI serial Flash PROM. The PROM is large enough to hold two configuration images and supports the iCE40 WarmBoot feature, if so enabled within the FPGA application. The PROM is physically located on the back side of the board. Programming the iCEblink40 Board The iCEblink40 board includes on-board USB-based programming support either from the Lattice iCEcube2 software or using a command from a console window or DOS box. From iCEcube2 Figure 21 shows the command sequence for programming the SPI Flash PROM on the iCEblink40 board using the iCEcube2 development software. Figure 21. Programming the iCEblink40 Board from iCEcube2 3 1 4 2 5 6 1. Select Tool > Programmer from the iCEcube2 menu bar. 2. Click the dropdown button ( ) under Programming Hardware. 3. Select iCEblink40. 4. The bitstream file should already be set appropriately based on the iCEcube2 project settings. If not, click Image Files Settings to select the configuration bitstream file. 5. Click Execute to program the iCEblink40 board. 18 iCEblink40-LP1K Evaluation Kit User’s Guide If all is working correctly, the power-on LED and the configuration done LED will both go out momentarily as iCEcube2 programs the on-board SPI Flash PROM. After programming is complete, both LEDs should light up again and the FPGA will execute the new configuration image. From Command Line The iCEblink40 programming software can also be executed from a console window or DOS box. To open a console window or DOS box, click the Start button and type cmd in the textbox immediately above the Start button. Executable Location After installation, the programming software executable is called iceutil.exe and is located in the \SbtTools\sbt_backend\bin\win32\opt directory. The iecutil.exe executable can be copied into the same directory as the FPGA bitstream image or can be pointed to on the command line. FPGA Bitstream Configuration File The required bitstream image is part of the iCEcube2 project. Multiple versions of the bitstream are stored in the _Implmnt\sbt\outputs\bitmap directory. The raw hexadecimal version of the bitstream is called _bitmap.hex. The alternate format of the same information is an Intel hexadecimal file called _bitmap_int.hex. Raw Hexadecimal Command Example /iceutil -d iCE40 -res -cr -m M25P10A -fh -w _bitmap.hex Intel Hexadecimal Command Example /iceutil -d iCE40 -res -cr -m M25P10A -fi -w _bitmap_int.hex Help /iceutil -help Testing Core Power Jumper JP1 provides the ability to measure core power consumption by the FPGA. Two power measurement methods are supported. Easy Method Using a Multimeter Connect the iCEblink40 board through your high-accuracy multimeter. Use a meter with a minimum of 10,000 counts; 50,000 counts or more is recommended for better accuracy. To take a quick measurement, follow these steps. 1. Disconnect power to the iCEblink40 board by removing the USB cable connection, either at the board or at the computer. 2. Remove the jumper JP1, which isolates the FPGA’s core supply from the 1.2V supply on the board. 3. Connect your multimeter’s alligator or test clips to the stake pins on header JP1. 4. Configure the multimeter to measure current using its highest mA or Amp range. This setting typically has the lowest voltage drop internally within the meter. 5. Re-connect the USB cable that supplies power to the iCEblink40 board and configure the FPGA device if necessary. 6. Observe the power reading on the multimeter. At low clock rates, which results in lower power consumption, switch the meter to a lower amperage setting for better accuracy. However, this also may increase the resistance across the meter leads. Using too low of a meter setting causes a large voltage drop within the meter, potentially violating the minimum input voltage specification to the FPGA device. 19 iCEblink40-LP1K Evaluation Kit User’s Guide 7. The value measured by the multimeter is a current. Convert the measurement to power using Equation 1. The voltage is the operating voltage, the voltage across the jumper. This value can be accurately measured with a second multimeter to show the voltage drop across the first. However, just measuring the initial voltage, before taking any current readings, usually provides acceptable accuracy and the voltage drop across the meter is generally small. Power = Current  Voltage (1) Although this method is easy, here are a few caveats and pointers. • Always start at the highest current setting for your meter. Using too small a setting may damage your meter! After determining the maximum current range for your measurement, then you can safely use the appropriate lower current setting. • The voltage drop across the meter leads may violate the minimum supply voltage specification for the mobileFPGA device. To determine the voltage drop, use a second multimeter to measure either the voltage across the first meter’s leads during a test or the resistance between the first meter’s leads. • Using the highest current measurement setting typically results in the lowest voltage drop. Using High-Precision, Small-Value Resistors For more-accurate, time-sensitive measurements, place a low-value resistor across the jumper test point. According to Ohm’s Law, the current passing through the resistor produces a voltage drop. Measure the voltage differential across the resistor during expected operation. Convert the measurement to power using Equation 2. The voltage is the measured voltage across the resistor; the resistance is the value of the resistor. 2  Voltage  Power = -------------------------Resistance (2) The following are a few guidelines on selecting a resistor. • Use a high-precision resistor. • The resistor must handle the power dissipated under the anticipated test conditions. • Too small a resistor value may result in too small a voltage difference across the resistor to measure with your test equipment. • Too large a resistor value may result in too large of a voltage difference across the resistor. Too large a voltage drop might violate the minimum voltage specifications for the FPGA device. Figure 22 shows an example header block designed to fit over one of the jump locations. Measure the voltage drop across the low-value resistor, either with a voltmeter or with data acquisition equipment. Figure 22. Resistor Header Block Voltmeter Low Ω, High Precision Resistor This method is recommended for taking power measurements over time. 20 iCEblink40-LP1K Evaluation Kit User’s Guide Mechanical Specifications Figure 23 shows the mechanical dimensions for the iCEblink40 board, including the location of the four mounting holes. With a jumper installed on JP1, the board height is approximately 0.700 inches high, including the four rubber feet mounted on the bottom side of the board. Figure 23. iCEblink40 LP1K Board Mechanical Dimension Ordering Information Description Ordering Part Number iCEblink40-LP1K Evaluation Kit China RoHS Environment-Friendly Use Period (EFUP) ICE40LP1K-BLINK-EVN Technical Support Assistance Hotline: 1-800-LATTICE (North America) +1-503-268-8001 (Outside North America) e-mail: techsupport@latticesemi.com Internet: www.latticesemi.com Revision History Date Version July 2012 01.0 Initial release. Change Summary September 2012 01.1 Nomenclature change from “mobileFPGA” to “FPGA”. © 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 21 D C B A AT90USB2 C3 1nF/250V J3 S4 S1 G ID D+ DV S2 IC3A IC3B USB-ASTB USB-DSTB USB-WRITE USB-WAIT 26 25 23 22 GND Lattice Semi GND USB3V3 D+ C38 0.1uF 22 C41 1uF 27 29 30 1 Chinese ROHS R38 22 R37 AT90USB2-16MU C37 0.1uF VCAP D+/SCK D-/SDATA C44 0.1uF ROHS GND C35 0.1uF VCC_3V3 USB-DB0 USB-DB1 USB-DB2 USB-DB3 USB-DB4 USB-DB5 USB-DB6 USB-DB7 USB-ON 6 7 8 9 10 11 12 13 CE 24 2 1 GND AT90USB2 PC1/RESET PC0/XTAL2 XTAL1 IC3D 3.0K R28 USB5V0 USB-SS_B USB-SCK USB-MOSI USB-MISO D+ DUSB5V0 GND 5 14 15 16 17 18 19 20 21 Atmel USB Programming Block USB5V0 USB3V3 D- IC3C S1 5 4 3 2 1 S2 NOT STUFFED 1x6 ISP-RESET 1 USB-MOSI 2 USB-MISO 3 USB-SCK 4 GND 5 USB3V3 6 J7 AT90USB2-16MU PD0/OC0B/INT0 PD1/AIN0/INT1 PD2/RXD1/AIN1/INT2 PD3/TXD1/INT3 PD4/INT4 PD5/XCK/PCINT12 PD6/RTS/INT6 PD7/CTS/HWB/T0/INT7 AT90USB2 AT90USB2-16MU PC4/PCINT10 PC5/OC1B/PCINT9 PC6/OC1A/PCINT8 PC7/INT4/ICP1/CLK0 PC2/PCINT11 AT90USB2 AT90USB2-16MU PB0/SS/PCINT0 PB1/SCLK/PCINT1 PB2/PDI/MOSI/PCINT2 PB3/PDO/MISO/PCINT3 PB4/T1/PCINT4 PB5/PCINT5 PB6/PCINT6 PB7/OC0A/OC1C/PCINT7 GND GND R4 1M S4 S3 R10 200 OUT SYSCLK 2 3.33 MHz (DEFAULT) 33.33 MHz 333 kHz C43 15pF ISP-RESET 8MHz X2 C42 15pF 200 R35 R32 10k DIV=OPEN DIV=VCC_3V3 DIV=GND SET V+ 5 iCE40-DB7 iCE40-DB6 iCE40-DB5 iCE40-DB4 iCE40-DB3 iCE40-DB2 iCE40-DB1 iCE40-DB0 iCE40-WAIT iCE40-WRITE iCE40-DSTB iCE40-ASTB iCE40-CDONE Basic oscillator X1 200 200 R25 R24 200 200 R23 R21 200 200 R20 R19 200 200 R17 R16 200 200 R15 R14 200 200 R13 R12 USB-ON iCE40-CRESET iCE40-SI iCE40-SO iCE40-SCK iCE40-SS_B LD5 R3 10 C1 8.2uF 2 10 5 9 8 7 VIN1 VIN2 PG EN1 EN2 4 2 6 C12 10nF C30 0.1uF A1 A2 B1 A3 B2 A4 B3 A5 B4 B5 A8 B7 A9 B8 A10 B9 A11 A12 C4 10uF 1uH L1 C32 10nF IC2A J1 VCC_3V3 3 C6 1uF VCC_3V3 A17 VCCIO_2 IC2B iCE40QN84 C8 10nF GND C7 0.1uF C2 1uF JP1 J6 VCC_3V3 3 VCCIO_0 C19 1uF VCC VCC VCC VCC C22 0.1uF VPP_2V5 VPP_FAST C21 0.1uF A36 A37 A7 A15 A28 B28 C23 10nF VCC_CORE R27 4.7K M25P10-SS_B iCE40-SCK iCE40-SO LD6 R30 10 R26 4.7K R34 10K WP C26 10nF 4 1 3 6 5 CS WP SCK SDI C40 10nF iCE40QN84 C39 1uF 1x6 1 2 3 4 5 6 J8 IC4 5 NOT STUFFED A35 B27 A34 B26 A33 A32 B24 A31 B23 B22 A29 B21 B20 A27 B19 A26 A25 R36 10K C17 10nF J2 R39 0 J10 1x2 1 2 NOT STUFFED JP3 VCC_3V3 NOT STUFFED VCC_3V3 GND LED1 LED2 LED3 LED4 LED3 LED2 1x6 1 2 3 4 5 6 J12 NOT STUFFED LED1 Foot F3 Foot F1 Foot F4 Foot F2 iCE40-SS_B iCE40-SO iCE40-SI iCE40-SCK GND VCC_3V3 5 1x6 1 2 3 4 5 6 J11 Date: File: J5 Number LED4 390 R31 390 R22 390 R11 390 R5 6/6/2012 C:\Users\..\iCEblink40-LP1K.SchDoc C36 100pF R29 100K 5% 1 1 1 1 6 A.0 Revision No Load CapButton BTN4 No Load CapButton BTN3 No Load CapButton BTN2 No Load CapButton BTN1 Sheet of 1/1 Drawn By: SK/GA GND 6013-500-003 LD4 GND C28 100pF R18 100K 5% VCC_3V3 CAPBTN4 LD3 GND C27 100pF R9 100K 5% VCC_3V3 CAPBTN3 LD2 GND VCC_3V3 CAPBTN2 LD1 6 C5 100pF R2 100K 5% VCC_3V3 CAPBTN1 iCEblink40-L1PK Tabloid Size Title NOT STUFFED Optional SPI PMOD support requested by SiliconBlue field sales. iCE40-SS_B M25P10-SS_B iCE40-WAIT SYSCLK NOT STUFFED DSC2-05 DSC2-04 DSC2-03 DSC2-02 DSC2-01 IMOD-1 IMOD-2 IMOD-4 IMOD-3 CAPBTN1 LED1 CAPBTN2 LED2 CAPBTN3 LED3 CAPBTN4 LED4 C16 0.1uF GND C15 1uF iCE40QN84 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 GBIN2/PIO1 GBIN3/PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 HLD J4 NOT STUFFED Mechanically compatible with Basic I/O shield. IC2D M25P10-AVMN6 7 2 iCE40-SI HOLD GND GND iCE40-SS_B NOT ST UFFE D SDO VCC_3V3 GND CDBU0520 D1 C25 10nF USB5V0 SPI_VCC IC2C R33 10K C34 10nF GND C33 1uF A24 4 iCE40-CRESET VCC_3V3 C24 10nF GND iCE40LP1K iCE40QN84 GND GND GND GND GND GND iCE40QN84 GND P A6 A18 A30 B33 IC2F C20 1uF IC2E iCE40QN84 GND A42 VCC_3V3 R40 Build Option No Load 0 Power Measurement Test Point SHUNT VCC_CORE PIO3 PIO3/DP00B PIO3/DP00A PIO3/DP01B PIO3/DP01A PIO3/DP02B PIO3/DP02A PIO3/DP03B PIO3/DP03A PIO3/DP04A GBIN7/PIO3/DP04B PIO3/DP05B GBIN6/PIO3/DP05A PIO3/DP06B PIO3/DP06A PIO3 PIO3 PIO3 GND C11 0.1uF GND C29 1uF DSC1-07 DSC1-08 DSC1-09 DSC1-10 DSC1-11 DSC1-12 DSC1-14 DSC1-15 DSC1-16 PMOD2-3 PMOD2-2 PMOD2-1 SYSCLK PMOD1-4 PMOD1-3 PMOD1-2 PMOD1-1 iCE40-ASTB C10 1uF GND IC1 FB SW VOUT2 ADP2140ACPZ3312R7 VCC_1V2 Mechanically compatible with Double Wide PMOD NOT STUFFED STUFFED NOT STUFFED VCC_3V3 2 4 DIV GND DIV GND LTC1799CS5#TRPBF JP2 3 1 75 R8 200 R7 75 R6 Power-On LED iCE40-CRESET R1 4.7K VCC_3V3 USB5V0 A GND GND PGND S3 1 31 UV CC 32 A V CC 4 V CC GND 3 PA D P UGND 28 B6 V CCIO_3 PIO2 GB IN5/PIO2 PIO2 PIO2 PIO2 GB IN4/PIO2 PIO2 PIO2 PIO2 PIO2/CB PIO2/C / B SE L 0 PIO2/CB PIO2/C / B SE L 1 A 13 A 14 B 10 B 11 A 16 B 12 B 13 B 14 A 19 B 15 A 20 iCE 40-DST B iCE 40-WR IT E iCE 40-DB 7 iCE 40-DB 6 iCE 40-WA IT iCE 40-DB 5 iCE 40-DB 4 iCE 40-DB 3 iCE 40-DB 2 iCE 40-DB 1 iCE 40-DB 0 3 P 1 Pmod 2x6 PMOD2-1 1 7 PMOD2-2 2 8 PMOD2-3 3 9 4 10 GND 5 11 6 12 PMOD1-1 PMOD1-2 PMOD1-3 PMOD1-4 GND iCE 40-A ST B iCE 40-DST B iCE 40-W R IT E iCE 40-W AIT GND DSC1-06 DSC1-05 DSC1-04 DSC1-03 DSC1-02 DSC1-01 DSC2-16 DSC2-15 DSC2-14 DSC2-13 DSC2-12 DSC2-11 DSC2-10 DSC2-09 DSC2-08 DSC2-07 DSC2-06 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 GB IN1/PIO0 GB IN0/PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIOS/SPI_SO PIOS/S / PI_SO PIOS/S PIOS/SPI_SI / PI_SI PIOS/SPI_SCK PIOS/S / PI_SCK / PI_SS_B PIOS/SPI_SS_B PIOS/S B 17 A 22 A 23 B 18 B 25 V CCIO_1 A 48 A 47 B 36 A 46 B 35 A 45 B 34 A 44 A 43 B 32 B 31 A 41 B 30 A 40 B 29 A 39 A 38 CDONE CR E SE T _B B 16 A 21 iCE 40-CDONE iCE 40-CR E SE T 1x6 1 2 3 4 5 6 8 V CC GND 22 4 DSC1-15 GND DSC1-11 DSC1-09 DSC1-07 DSC1-05 DSC1-03 DSC1-01 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 2x8 DSC1-16 DSC1-14 DSC1-12 DSC1-10 DSC1-08 DSC1-06 DSC1-04 DSC1-02 DSC2-15 DSC2-13 DSC2-11 DSC2-09 DSC2-07 DSC2-05 DSC2-03 DSC2-01 16 15 14 13 12 11 10 9 7 8 6 5 4 3 2 1 2x8 DSC2-16 DSC2-14 DSC2-12 DSC2-10 DSC2-08 DSC2-06 DSC2-04 DSC2-02 iCE 40-DB 6 iCE 40-DB 4 iCE 40-DB 2 iCE 40-DB 0 IMOD-4 IMOD-2 GND 16 15 14 13 12 11 10 9 7 8 6 5 3 4 2 1 2x8 iCE 40-DB 7 iCE 40-DB 5 iCE 40-DB 3 iCE 40-DB 1 IMOD-3 IMOD-1 GND USB Mini AB D C B A iCEblink40-LP1K Evaluation Kit User’s Guide Appendix A. Schematic Figure 24. Schematic iCEblink40-LP1K Evaluation Kit User’s Guide Appendix B. Bill of Materials (Major Components) Table 9. Bill of Materials Reference Vendor Part Number Description IC2 Lattice Semiconductor iCE40LP1K-QN84 iCE40 LP-series ultra low-power FPGA IC1 Analog Devices ADP2140ACPZ3312R7 Low-quiescent buck/LDO regulator (1.2V, 3.3V) X1 Linear Technology LTC1799CS5#TRPBF Oscillator IC4 Micron Technology M25P10-AVMN6 1Mbit SPI serial configuration Flash PROM IC3 Atmel Corporation AT90USB162-16MU USB programming and debugging interface 23