ICE40LP1K-CM36A

iCE40 LP/HX Family Data Sheet Data Sheet FPGA-DS-02029-3.6 October 2020 iCE40 LP/HX Family Data Sheet Data Sheet Disclaimers Lattice makes no warranty, representation, or guarantee regarding the accuracy of information contained in this document or the suitability of its products for any particular purpose. All information herein is provided AS IS and with all faults, and all risk associated with such information is entirely with Buyer. Buyer shall not rely on any data and performance specifications or parameters provided herein. Products sold by Lattice have been subject to limited testing and it is the Buyer's responsibility to independently determine the suitability of any products and to test and verify the same. No Lattice products should be used in conjunction with mission- or safety-critical or any other application in which the failure of Lattice’s product could create a situation where personal injury, death, severe property or environmental damage may occur. The information provided in this document is proprietary to Lattice Semiconductor, and Lattice reserves the right to make any changes to the information in this document or to any products at any time without notice. © 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 2 FPGA-DS-02029-3.6 iCE40 LP/HX Family Data Sheet Data Sheet Contents Acronyms in This Document ................................................................................................................................................. 6 1. General Description ...................................................................................................................................................... 7 1.1. Features .............................................................................................................................................................. 7 2. Product Family .............................................................................................................................................................. 8 3. Architecture .................................................................................................................................................................. 9 3.1. Architecture Overview ........................................................................................................................................ 9 3.1.1. PLB Blocks ..................................................................................................................................................... 10 3.1.2. Routing.......................................................................................................................................................... 11 3.1.3. Clock/Control Distribution Network ............................................................................................................. 11 3.1.4. sysCLOCK Phase Locked Loops (PLLs) ........................................................................................................... 12 3.1.5. sysMEM Embedded Block RAM Memory ..................................................................................................... 13 3.1.6. sysI/O ............................................................................................................................................................ 15 3.1.7. sysI/O Buffer ................................................................................................................................................. 18 3.1.8. Non-Volatile Configuration Memory ............................................................................................................ 19 3.1.9. Power On Reset ............................................................................................................................................ 19 3.2. Programming and Configuration ....................................................................................................................... 19 3.2.1. Power Saving Options ................................................................................................................................... 19 4. DC and Switching Characteristics ............................................................................................................................... 20 4.1. Absolute Maximum Ratings .............................................................................................................................. 20 4.2. Recommended Operating Conditions ............................................................................................................... 20 4.3. Power Supply Ramp Rates ................................................................................................................................ 21 4.4. Power-On-Reset Voltage Levels ........................................................................................................................ 21 4.5. ESD Performance .............................................................................................................................................. 22 4.6. DC Electrical Characteristics .............................................................................................................................. 22 4.7. Static Supply Current – LP Devices .................................................................................................................... 23 4.8. Static Supply Current – HX Devices ................................................................................................................... 23 4.9. Programming NVCM Supply Current – LP Devices ............................................................................................ 24 4.10. Programming NVCM Supply Current – HX Devices ........................................................................................... 24 4.11. Peak Startup Supply Current – LP Devices ........................................................................................................ 25 4.12. Peak Startup Supply Current – HX Devices ....................................................................................................... 26 4.13. sysI/O Recommended Operating Conditions .................................................................................................... 26 4.14. sysI/O Single-Ended DC Electrical Characteristics ............................................................................................. 27 4.15. sysI/O Differential Electrical Characteristics ..................................................................................................... 27 4.15.1. LVDS25...................................................................................................................................................... 27 4.15.2. subLVDS .................................................................................................................................................... 27 4.16. LVDS25E Emulation ........................................................................................................................................... 28 4.17. SubLVDS Emulation ........................................................................................................................................... 29 4.18. Typical Building Block Function Performance – LP Devices* ............................................................................ 30 4.18.1. Pin-to-Pin Performance (LVCMOS25) – LP Devices .................................................................................. 30 4.18.2. Register-to-Register Performance – LP Devices ....................................................................................... 30 4.19. Typical Building Block Function Performance – HX Devices*............................................................................ 31 4.19.1. Pin-to-Pin Performance (LVCMOS25) – HX Devices ................................................................................. 31 4.19.2. Register-to-Register Performance – HX Devices ...................................................................................... 31 4.20. Derating Logic Timing ........................................................................................................................................ 31 4.21. Maximum sysI/O Buffer Performance .............................................................................................................. 32 4.22. Timing Adders ................................................................................................................................................... 32 4.23. External Switching Characteristics – LP Devices................................................................................................ 33 4.24. External Switching Characteristics – HX Devices ............................................................................................... 35 4.25. sysClock PLL Timing ........................................................................................................................................... 36 4.26. SPI Master or NVCM Configuration Time .......................................................................................................... 37 4.27. sysCONFIG Port Timing Specifications .............................................................................................................. 38 4.28. Switching Test Conditions ................................................................................................................................. 39 © 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02029-3.6 3 iCE40 LP/HX Family Data Sheet Data Sheet 5. Pinout Information .....................................................................................................................................................40 5.1. Signal Descriptions ............................................................................................................................................40 5.1.1. General Purpose ...........................................................................................................................................40 5.1.2. PLL and Global Functions (Used as user-programmable I/O pins when not used for PLL or clock pins) ......40 5.1.3. Programming and Configuration ..................................................................................................................41 5.2. Pin Information Summary .................................................................................................................................42 5.3. iCE40 LP/HX Part Number Description ..............................................................................................................45 5.3.1. Ultra Low Power (LP) Devices .......................................................................................................................45 5.3.2. High Performance (HX) Devices ....................................................................................................................45 5.4. Ordering Information ........................................................................................................................................45 5.5. Ordering Part Numbers .....................................................................................................................................46 5.5.1. Ultra Low Power Industrial Grade Devices, Halogen Free (RoHS) Packaging ...............................................46 5.5.2. High-Performance Industrial Grade Devices, Halogen Free (RoHS) Packaging .............................................47 Supplemental Information..................................................................................................................................................48 Technical Support ...............................................................................................................................................................49 Revision History ..................................................................................................................................................................50 Figures Figure 3.1. iCE40LP/HX1K Device, Top View .........................................................................................................................9 Figure 3.2. PLB Block Diagram ............................................................................................................................................10 Figure 3.3. PLL Diagram ......................................................................................................................................................12 Figure 3.4. sysMEM Memory Primitives .............................................................................................................................14 Figure 3.5. I/O Bank and Programmable I/O Cell................................................................................................................16 Figure 3.6. iCE I/O Register Block Diagram .........................................................................................................................17 Figure 4.1. LVDS25E Using External Resistors .....................................................................................................................28 Figure 4.2. subLVDSE DC Conditions ...................................................................................................................................29 Figure 4.3. Output Test Load, LVCMOS Standards..............................................................................................................39 Figure 5.1. Low Power (LP) Devices ....................................................................................................................................45 Figure 5.2. High Performance (HX) Devices ........................................................................................................................45 Figure 5.3. High Performance (HX) Devices ........................................................................................................................46 © 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 4 FPGA-DS-02029-3.6 iCE40 LP/HX Family Data Sheet Data Sheet Tables Table 2.1. iCE40 LP/HX Family Selection Guide .................................................................................................................... 8 Table 3.1. Logic Cell Signal Descriptions ............................................................................................................................. 11 Table 3.2. Global Buffer (GBUF) Connections to Programmable Logic Blocks ................................................................... 11 Table 3.3. PLL Signal Descriptions ....................................................................................................................................... 13 Table 3.4. sysMEM Block Configurations* .......................................................................................................................... 14 Table 3.5. EBR Signal Descriptions ...................................................................................................................................... 15 Table 3.6. PIO Signal List ..................................................................................................................................................... 17 Table 3.7. Supported Input Standards ................................................................................................................................ 18 Table 3.8. Supported Output Standards ............................................................................................................................. 18 Table 3.9. Power Saving Features Description ................................................................................................................... 19 Table 4.1. Absolute Maximum Ratings* ............................................................................................................................. 20 Table 4.2. Recommended Operating Conditions1 .............................................................................................................. 20 Table 4.3. Power Supply Ramp Rates* ............................................................................................................................... 21 Table 4.4. Power-On-Reset Voltage Levels* ....................................................................................................................... 21 Table 4.5. DC Electrical Characteristics ............................................................................................................................... 22 Table 4.6. Supply Current– LP Devices1, 2, 3, 4....................................................................................................................... 23 Table 4.7. Supply Current– HX Devices1, 2, 3, 4 ...................................................................................................................... 23 Table 4.8. Programming NVCM Supply Current – LP Devices1, 2, 3, 4 .................................................................................... 24 Table 4.9. Programming NVCM Supply Current – HX Devices1, 2, 3, 4 ................................................................................... 24 Table 4.10. Peak Startup Supply Current – LP Devices ....................................................................................................... 25 Table 4.11. Peak Startup Supply Current – HX Devices ...................................................................................................... 26 Table 4.12. sysI/O Recommended Operating Conditions ................................................................................................... 26 Table 4.13. sysI/O Single-Ended DC Electrical Characteristics ............................................................................................ 27 Table 4.14. LVDS25 ............................................................................................................................................................. 27 Table 4.15. subLVDS ........................................................................................................................................................... 27 Table 4.16. LVDS25E DC Conditions.................................................................................................................................... 28 Table 4.17. subLVDSE DC Conditions .................................................................................................................................. 29 Table 4.18. Pin-to-Pin Performance (LVCMOS25) – LP Devices .......................................................................................... 30 Table 4.19. Register-to-Register Performance – LP Devices............................................................................................... 30 Table 4.20. Pin-to-Pin Performance (LVCMOS25) – HX Devices ......................................................................................... 31 Table 4.21. Register-to-Register Performance – HX Devices .............................................................................................. 31 Table 4.22. Register-to-Register Performance1 .................................................................................................................. 32 Table 4.23. Timing Adders – LP Devices* ........................................................................................................................... 32 Table 4.24. Timing Adders – HX Devices* ........................................................................................................................... 33 Table 4.25. External Switching Characteristics – LP Devices1, 2........................................................................................... 33 Table 4.26. External Switching Characteristics – HX Devices1, 2 .......................................................................................... 35 Table 4.27. sysClock PLL Timing .......................................................................................................................................... 36 Table 4.28. SPI Master or NVCM Configuration Time1, 2 ..................................................................................................... 37 Table 4.29. sysCONFIG Port Timing Specifications1 ............................................................................................................ 38 Table 4.30. Test Fixture Required Components, Non-Terminated Interfaces* .................................................................. 39 © 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02029-3.6 5 iCE40 LP/HX Family Data Sheet Data Sheet Acronyms in This Document A list of acronyms used in this document. Acronym Definition DFF DSP EBR HFOSC I2 C LFOSC LUT LVCMOS NVCM PFU PLB PLL SPI WLCSP D-style Flip-Flop Digital Signal Processor Embedded Block RAM High Frequency Oscillator Inter-Integrated Circuit Low Frequency Oscillator Look Up Table Low-Voltage Complementary Metal Oxide Semiconductor Non Volatile Configuration Memory Programmable Functional Unit Programmable Logic Blocks Phase Locked Loops Serial Peripheral Interface Wafer Level Chip Scale Packaging © 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 6 FPGA-DS-02029-3.6 iCE40 LP/HX Family Data Sheet Data Sheet 1. General Description The iCE40™ LP/HX family of ultra-low power, nonvolatile FPGAs has five devices with densities ranging from 384 to 7,680 Look-Up Tables (LUTs). In addition to LUT-based, low-cost programmable logic, these devices feature Embedded Block RAM (EBR), Nonvolatile Configuration Memory (NVCM) and Phase Locked Loops (PLLs). These features allow the devices to be used in low-cost, high-volume consumer and system applications. Select packages offer HighCurrent drivers that are ideal to drive three white LEDs, or one RGB LED. The iCE40 LP/HX devices are fabricated on a 40 nm CMOS low power process. The device architecture has several features such as programmable low-swing differential I/O and the ability to turn off on-chip PLLs dynamically. These features help manage static and dynamic power consumption, resulting in low static power for all members of the family. The iCE40 LP/HX devices are available in two versions – ultra low power (LP) and high performance (HX) devices. The iCE40 LP/HX FPGAs are available in a broad range of advanced halogen-free packages ranging from the space saving 1.40 mm x 1.48 mm WLCSP to the PCBfriendly 20 mm x 20 mm TQFP. Table 2.1 shows the LUT densities, package and I/O options, along with other key parameters. The iCE40 LP/HX devices offer enhanced I/O features such as pull-up resistors. Pull-up features are controllable on a per-pin basis. The iCE40 LP/HX devices also provide flexible, reliable and secure configuration from on-chip NVCM. These devices can also configure themselves from external SPI Flash or be configured by an external master such as a CPU. Lattice provides a variety of design tools that allow complex designs to be efficiently implemented using the iCE40 LP/HX family of devices. Popular logic synthesis tools provide synthesis library support for iCE40 LP/HX. Lattice design tools use the synthesis tool output along with the user-specified preferences and constraints to place and route the design in the iCE40 LP/HX device. These tools extract the timing from the routing and back-annotate it into the design for timing verification. Lattice provides many pre-engineered IP (Intellectual Property) modules, including a number of reference designs, licensed free of charge, optimized for the iCE40 LP/HX FPGA family. By using these configurable soft core IP cores as standardized blocks, users are free to concentrate on the unique aspects of their design, increasing their productivity. 1.1. Features           Flexible Logic Architecture  Five devices with 384 to 7,680 LUT4s and 10 to 206 I/O Ultra-low Power Devices  Advanced 40 nm low power process  As low as 21 µA standby power  Programmable low swing differential I/O Embedded and Distributed Memory  Up to 128 kb sysMEM™ Embedded Block RAM Pre-Engineered Source Synchronous I/O  DDR registers in I/O cells High Current LED Drivers  Three High Current Drivers used for three different LEDs or one RGB LED High Performance, Flexible I/O Buffer  Programmable sysI/O™ buffer supports wide range of interfaces:  LVCMOS 3.3/2.5/1.8  LVDS25E, subLVDS  Schmitt trigger inputs, to 200 mV typical hysteresis Programmable pull-up mode Flexible On-Chip Clocking  Eight low skew global signal resources  Up to two analog PLLs per device Flexible Device Configuration  SRAM is configured through:  Standard SPI Interface  Internal Nonvolatile Configuration Memory (NVCM) Broad Range of Package Options  WLCSP, QFN, VQFP, TQFP, ucBGA, caBGA, and csBGA package options  Small footprint package options  As small as 1.40 mm x 1.48 mm  Advanced halogen-free packaging © 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02029-3.6 7 iCE40 LP/HX Family Data Sheet Data Sheet 2. Product Family Table 2.1 lists device information and packages of the iCE40 LP/HX family. Table 2.1. iCE40 LP/HX Family Selection Guide Part Number LP384 LP640 LP1K LP4K LP8K HX1K Logic Cells (LUT + Flip-Flop) 384 640 1,280 3,520 7,680 1,280 RAM4K Memory Blocks 0 8 16 20 32 16 RAM4K RAM bits 0 32K 64K 80K 128K 64K Phase-Locked Loops (PLLs) 0 0 11 22 22 11 Maximum Programmable I/O Pins 63 25 95 167 178 95 Maximum Differential Input Pairs 8 3 12 20 23 11 High Current LED Drivers 0 3 3 0 0 0 Package Code Programmable I/O: Max Input (LVDS25) 16 WLCSP SWG16 10(0)1 10(0) — — — (1.40 mm x 1.48 mm, 0.35 mm) 32 QFN SG32 21(3) — — — — — (5 mm x 5 mm, 0.5 mm) 36 ucBGA CM36 25(3) — 25(3) — — — (2.5 mm x 2.5 mm, 0.4 mm) 49 ucBGA CM49 37(6) — 35(5) — — — (3 mm x 3 mm, 0.4 mm) 81 ucBGA CM81 — — 63(8) 63(9)2 63(9)2 — (4 mm x 4 mm, 0.4 mm) 81 csBGA CB81 — — 62(9) — — — (5 mm x 5 mm, 0.5 mm) 84 QFN QN84 — — 67(7) — — — (7 mm x 7 mm, 0.5 mm) 100 VQFP VQ100 — — — — — 72(9)1 (14 mm x 14 mm, 0.5 mm) 121 ucBGA CM121 — — 95(12) 93(13) 93(13) — (5 mm x 5 mm, 0.4 mm) 121 csBGA CB121 — — 92(12) — — — (6 mm x 6 mm, 0.5 mm) 121 caBGA BG121 — — — — — — (9 mm x 9 mm, 0.8 mm) 132 csBGA CB132 — — — — — 95(11) (8 mm x 8 mm, 0.5 mm) 144 TQFP TQ144 — — — — — 96(12) (20 mm x 20 mm, 0.5 mm) 225 ucBGA CM225 — — — 178(23) 178(23) — (7 mm x 7 mm, 0.4 mm) 256-ball caBGA CT256 — — — — — — (14 mm x 14 mm, 0.8 mm) Notes: 1. No PLL available on the 16 WLCSP, 36 ucBGA, 81 csBGA, 84 QFN, and 100 VQFP packages. 2. Only one PLL available on the 81 ucBGA package. 3. High Current I/O only available on the 16 WLCSP package. HX4K 3,520 20 80K 2 95 12 0 HX8K 7,680 32 128K 2 206 26 0 — — — — — — — — — — — — — — — — — — — — 93(13) 93(13) 95(12) 95(12) 107(14) — — 178(23) — 206(26) © 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 8 FPGA-DS-02029-3.6 iCE40 LP/HX Family Data Sheet Data Sheet 3. Architecture 3.1. Architecture Overview The iCE40 LP/HX family architecture contains an array of Programmable Logic Blocks (PLB), sysCLOCK™ PLLs, Nonvolatile Programmable Configuration Memory (NVCM) and blocks of sysMEM Embedded Block RAM (EBR) surrounded by Programmable I/O (PIO). Figure 3.1 shows the block diagram of the iCE40LP/HX1K device. Programmable Lo gic Block (PLB) 8 Logic Cells = Programmable Logic Block I/O Bank 0 PLB PLB PLB PLB PLB PLB PLB PLB I/O Bank 1 PLB PLB PLB PLB Programmable Interconnect PLB PLB PLB PLB PLB PLB PLB PLB PLB PLB PLB PLB 4 kbit RAM PLB PLB PLB PLB 4 kbit RAM PLB PLB PLB PLB Programmable Interconnect I/O Bank 3 Programmable Interconnect PLL NVCM I/O Bank 2 Non-volatile Configuration Memory (NVCM) Phase-Locked Loop SPI Bank Carry Logic 4-Input Look-up Table (LUT4) Flip-flop with Enable and Reset Controls Figure 3.1. iCE40LP/HX1K Device, Top View The logic blocks, Programmable Logic Blocks (PLB) and sysMEM EBR blocks, are arranged in a two-dimensional grid with rows and columns. Each column has either logic blocks or EBR blocks. The PIO cells are located at the periphery of the device, arranged in banks. The PLB contains the building blocks for logic, arithmetic, and register functions. The PIOs utilize a flexible I/O buffer referred to as a sysI/O buffer that supports operation with a variety of interface standards. The blocks are connected with many vertical and horizontal routing channel resources. The place and route software tool automatically allocates these routing resources. In the iCE40 LP/HX family, there are up to four independent sysI/O banks. Note on some packages VCCIO banks are tied together. There are different types of I/O buffers on the different banks. Refer to the details in later sections of this © 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02029-3.6 9 iCE40 LP/HX Family Data Sheet Data Sheet document. The sysMEM EBRs are large 4 kbit, dedicated fast memory blocks. These blocks can be configured as RAM, ROM or FIFO. The iCE40 LP/HX architecture also provides up to two sysCLOCK Phase Locked Loop (PLL) blocks. The PLLs have multiply, divide, and phase shifting capabilities that are used to manage the frequency and phase relationships of the clocks. Every device in the family has a SPI port that supports programming and configuration of the device. The iCE40 LP/HX includes on-chip, Nonvolatile Configuration Memory (NVCM). 3.1.1. PLB Blocks 8 Logic Cells (LCs) The core of the iCE40 LP/HX device consists of Programmable Logic Blocks (PLB) which can be programmed to perform logic and arithmetic functions. Each PLB consists of eight interconnected Logic Cells (LC) as shown in Figure 3.2. Each LC contains one LUT and one register. Figure 3.2. PLB Block Diagram Logic Cells Each Logic Cell includes three primary logic elements shown in Figure 3.2.  A four-input Look-Up Table (LUT) builds any combinational logic function, of any complexity, requiring up to four inputs. Similarly, the LUT4 element behaves as a 16 x 1 Read-Only Memory (ROM). Combine and cascade multiple LUT4s to create wider logic functions.  A D-style Flip-Flop (DFF), with an optional clock-enable and reset control input, builds sequential logic functions. Each DFF also connects to a global reset signal that is automatically asserted immediately following device configuration.  Carry Logic boosts the logic efficiency and performance of arithmetic functions, including adders, subtracters, comparators, binary counters and some wide, cascaded logic functions. Table 3.1 lists the logic cell signals. © 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 10 FPGA-DS-02029-3.6 iCE40 LP/HX Family Data Sheet Data Sheet Table 3.1. Logic Cell Signal Descriptions Function Type Signal Name Description Input Data signal I0, I1, I2, I3 Inputs to LUT4 Input Control signal Enable Clock enable shared by all LCs in the PLB Input Control signal Set/Reset* Asynchronous or synchronous local set/reset shared by all LCs in the PLB. Input Control signal Clock Clock one of the eight Global Buffers, or from the general-purpose interconnects fabric shared by all LCs in the PLB. Input Inter-PLB signal FCIN Fast carry in Output Data signals O LUT4 or registered output Output Inter-PFU signal FCOUT Fast carry out *Note: If Set/Reset is not used, then the flip-flop is never set/reset, except when cleared immediately after configuration. 3.1.2. Routing There are many resources provided in the iCE40 LP/HX devices to route signals individually with related control signals. The routing resources consist of switching circuitry, buffers, and metal interconnect (routing) segments. The inter-PLB connections are made with three different types of routing resources: Adjacent (spans two PLBs), x4 (spans five PLBs) and x12 (spans thirteen PLBs). The Adjacent, x4, and x12 connections provide fast and efficient connections in the diagonal, horizontal and vertical directions. The design tool takes the output of the synthesis tool and places and routes the design. 3.1.3. Clock/Control Distribution Network Each iCE40 LP/HX device has eight global inputs, two pins on each side of the device. Note that not all GBINs are available in all packages. These global inputs can be used as high fanout nets, clock, reset or enable signals. The dedicated global pins are identified as GBIN[7:0] and the global buffers are identified as-GBUF[7:0]. These eight inputs may be used as general purpose I/O if they are not used to drive the clock nets. Global buffer GBUF7 in I/O Bank 3 also provides an optional direct LVDS25 or subLVDS differential clock input. Table 3.2 lists the connections between a specific global buffer and the inputs on a PLB. All global buffers optionally connect to the PLB CLK input. Any four of the eight global buffers can drive logic inputs to a PLB. Even-numbered global buffers optionally drive the Set/Reset input to a PLB. Similarly, odd-numbered buffers optionally drive the PLB clockenable input. Table 3.2. Global Buffer (GBUF) Connections to Programmable Logic Blocks Global Buffer Clock Reset Clock Enable GBUF0 Yes Yes — GBUF1 Yes — Yes GBUF2 Yes Yes — GBUF3 Yes — Yes Yes Yes — GBUF5 Yes — Yes GBUF6 Yes Yes — GBUF7 Yes — Yes GBUF4 LUT Inputs Yes, any 4 of 8 GBUF Inputs The maximum frequency for the global buffers are listed in the External Switching Characteristics tables in this document. © 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02029-3.6 11 iCE40 LP/HX Family Data Sheet Data Sheet 3.1.3.1. Global Hi-Z Control The global high-impedance control signal, GHIZ, connects to all I/O pins on the iCE40 LP/HX device. This GHIZ signal is automatically asserted throughout the configuration process, forcing all user I/O pins into their high-impedance state. 3.1.3.2. Global Reset Control The global reset control signal connects to all PLB and PIO flip-flops on the iCE40 LP/HX device. The global reset signal is automatically asserted throughout the configuration process, forcing all flip-flops to their defined wake-up state. For PLB flip-flops, the wake-up state is always reset, regardless of the PLB flip-flop primitive used in the application. 3.1.4. sysCLOCK Phase Locked Loops (PLLs) The sysCLOCK PLLs provide the ability to synthesize clock frequencies. The iCE40 LP/HX devices have one sysCLOCK PLL. REFERENCECLK is the reference frequency input to the PLL and its source can come from an external I/O pin, the internal Oscillator Generators from internal routing. EXTFEEDBACK is the feedback signal to the PLL which can come from internal routing or an external I/O pin. The feedback divider is used to multiply the reference frequency and thus synthesize a higher frequency clock output. The PLLOUT output has an output divider, thus allowing the PLL to generate different frequencies for each output. The output divider can have a value from 1 to 64 (in increments of 2X). The PLLOUT outputs can all be used to drive the iCE40 LP/HX global clock network directly or general purpose routing resources can be used. The LOCK signal is asserted when the PLL determines it has achieved lock and de-asserted if a loss of lock is detected. A block diagram of the PLL is shown in Figure 3.3. The timing of the device registers can be optimized by programming a phase shift into the PLLOUT output clock which will advance or delay the output clock with reference to the REFERENCECLK clock. This phase shift can be either programmed during configuration or can be adjusted dynamically. In dynamic mode, the PLL may lose lock after a phase adjustment on the output used as the feedback source and not relock until the tLOCK parameter has been satisfied. RESET BYPAS S BYPAS S GNDPLL REFERENCECLK DIVR Phase Detector In put Divider RANGE Lo w-Pass Filter VCCPLL DIVQ Vol tage Control led Oscill ator (VCO) VCO Divider SIMPLE DIVF PLLOUTCORE Feed back Divider Fine Delay Adjustment Feed back Feed back_Path PLLOUTGLOBAL LOCK DYNAMICDELAY[7:0] EXTFEEDBACK LATCHINPUTVALUE Phase Shifter Fine Delay Adjustment Output Port EXTERNAL Lo w Power mode (iCEgate enabled) Figure 3.3. PLL Diagram Table 3.3 provides signal descriptions of the PLL block. © 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 12 FPGA-DS-02029-3.6 iCE40 LP/HX Family Data Sheet Data Sheet Table 3.3. PLL Signal Descriptions Signal Name Direction Description REFERENCECLK Input Input reference clock BYPASS Input The BYPASS control selects which clock signal connects to the PLLOUT output. 0 – PLL generated signal 1 – REFERENCECLK EXTFEEDBACK Input External feedback input to PLL. Enabled when the FEEDBACK_PATH attribute is set to EXTERNAL. DYNAMICDELAY[7:0] Input Fine delay adjustment control inputs. Enabled when DELAY_ADJUSTMENT_MODE is set to DYNAMIC. LATCHINPUTVALUE Input When enabled, puts the PLL into low-power mode; PLL output is held static at the last input clock value. Set ENABLE ICEGATE_PORTA and PORTB to 1 to enable. PLLOUTGLOBAL Output Output from the Phase-Locked Loop (PLL). Drives a global clock network on the FPGA. The port has optimal connections to global clock buffers GBUF4 and GBUF5. PLLOUTCORE Output LOCK Output RESET Input Output clock generated by the PLL, drives regular FPGA routing. The frequency generated on this output is the same as the frequency of the clock signal generated on the PLLOUTLGOBAL port. When High, indicates that the PLL output is phase aligned or locked to the input reference clock. Active low reset. SCLK Input Input, Serial Clock used for re-programming PLL settings. SDI Input Input, Serial Data used for re-programming PLL settings. 3.1.5. sysMEM Embedded Block RAM Memory Larger iCE40 LP/HX device includes multiple high-speed synchronous sysMEM Embedded Block RAMs (EBRs), each 4 kbit in size. This memory can be used for a wide variety of purposes including data buffering and FIFO. 3.1.5.1. sysMEM Memory Block The sysMEM block can implement single port, pseudo dual port, or FIFO memories with programmable logic resources. Each block can be used in a variety of depths and widths as listed in Table 3.4. © 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02029-3.6 13 iCE40 LP/HX Family Data Sheet Data Sheet Table 3.4. sysMEM Block Configurations* Block RAM Configuration SB_RAM256x16 SB_RAM256x16NR SB_RAM256x16NW SB_RAM256x16NRNW SB_RAM512x8 SB_RAM512x8NR SB_RAM512x8NW SB_RAM512x8NRNW SB_RAM1024x4 SB_RAM1024x4NR SB_RAM1024x4NW SB_RAM1024x4NRNW SB_RAM2048x2 SB_RAM2048x2NR SB_RAM2048x2NW SB_RAM2048x2NRNW Block RAM Configuration and Size WADDR Port Size (Bits) WDATA Port Size (Bits) RADDR Port Size (Bits) RDATA Port Size (Bits) MASK Port Size (Bits) 256 x 16 (4 k) 8 [7:0] 16 [15:0] 8 [7:0] 16 [15:0] 16 [15:0] 512 x 8 (4 k) 9 [8:0] 8 [7:0] 9 [8:0] 8 [7:0] No Mask Port 1024 x 4 (4 k) 10 [9:0] 4 [3:0] 10 [9:0] 4 [3:0] No Mask Port 2048 x 2 (4 k) 11 [10:0] 2 [1:0] 11 [10:0] 2 [1:0] No Mask Port *Note: For iCE40 LP/HX EBR primitives with a negative-edged Read or Write clock, the base primitive name is appended with a ‘N’ and a ‘R’ or W depending on the clock that is affected. 3.1.5.2. RAM Initialization and ROM Operation If desired, the contents of the RAM can be pre-loaded during device configuration. By preloading the RAM block during the chip configuration cycle and disabling the write controls, the sysMEM block can also be utilized as a ROM. Note that the sysMEM Embedded Block RAM Memory address 0 cannot be initialized. 3.1.5.3. Memory Cascading Larger and deeper blocks of RAM can be created using multiple EBR sysMEM Blocks. 3.1.5.4. RAM4k Block Figure 3.4 shows the 256 x 16 memory configurations and their input/output names. In all the sysMEM RAM modes, the input data and addresses for the ports are registered at the input of the memory array. Write Port Read Port WDATA[15:0] RDATA[15:0] MASK[15:0] RADDR[7:0] WADDR[7:0] RAM4K RAM Block (256 x 16) WE RE WCLKE RCLKE WCLK RCLK Figure 3.4. sysMEM Memory Primitives © 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 14 FPGA-DS-02029-3.6 iCE40 LP/HX Family Data Sheet Data Sheet Table 3.5 lists the EBR signals. Table 3.5. EBR Signal Descriptions Signal Name Direction WDATA[15:0] Input Write Data input. MASK[15:0] Input WADDR[7:0] Input Masks write operations for individual data bit-lines. 0 – Write bit 1 – Do not write bit Write Address input. Selects one of 256 possible RAM locations. WE Input Write Enable input. WCLKE Input Write Clock Enable input. Input Write Clock input. Default rising-edge, but with falling-edge option. WCLK Description RDATA[15:0] Output Read Data output. RADDR[7:0] Input Read Address input. Selects one of 256 possible RAM locations. RE Input Read Enable input. RCLKE Input Read Clock Enable input. RCLK Input Read Clock input. Default rising-edge, but with falling-edge option. For further information on the sysMEM EBR block, refer to Memory Usage Guide for iCE40 Devices (FPGA-TN-02002). 3.1.6. sysI/O Buffer Banks iCE40 LP/HX devices have up to four I/O banks with independent VCCIO rails with an additional configuration bank VCC_SPI for the SPI I/O. Programmable I/O (PIO) The programmable logic associated with an I/O is called a PIO. The individual PIOs are connected to their respective sysI/O buffers and pads. The PIOs are placed on the top and bottom of the devices. © 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02029-3.6 15 iCE40 LP/HX Family Data Sheet Data Sheet VCCIO I/O Bank 0, 1, 2, or 3 Voltage Supply 0 = Hi-Z 1 = Output Enabled Enabled 1 Disabled 0 OE VCCIO_0 VCC Internal Core P ull-up P ull-up Enable OUTCLK I/O Bank 0 General-Purpose I/O I/O Bank 2 General-Purpose I/O VCCIO_2 OUT PAD OUTCLK VCCIO_1 I/O Bank 1 General-Purpose I/O I/O Bank 3 Special/LVDS I/O VCCIO_3 PIO iCEGATE HOLD HD Latch inhibits switching for lowest power IN IN SPI Bank VCC_SPI INCLK GBIN pins optionally connect directly to an associated GBUF global buffer Programmable Input/Output = Statically defined by configuration program Figure 3.5. I/O Bank and Programmable I/O Cell The PIO contains three blocks: an input register block, output register block iCEgate™ and tri-state register block. To save power, the optional iCEgate latch can selectively freeze the state of individual, non-registered inputs within an I/O bank. Note that the freeze signal is common to the bank. These blocks can operate in a variety of modes along with the necessary clock and selection logic. Input Register Block The input register blocks for the PIOs on all edges contain registers that can be used to condition high-speed interface signals before they are passed to the device core. In Generic DDR mode, two registers are used to sample the data on the positive and negative edges of the system clock signal, creating two data streams. Output Register Block The output register block can optionally register signals from the core of the device before they are passed to the sysI/O buffers. In Generic DDR mode, two registers are used to capture the data on the positive and negative edge of the system clock and then muxed creating one data stream. Figure 3.6 shows the input/output register block for the PIOs. © 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 16 FPGA-DS-02029-3.6 iCE40 LP/HX Family Data Sheet Data Sheet PIO Pair CLOCK_ENABLE OUTPUT_CLK INPUT_CLK (1,0) LATCH_INPUT_VALUE D_IN_1 D_IN_0 Pad D_OUT_1 D_OUT_0 (1,0) 0 1 OUTPUT_ENABLE (1,0) LATCH_INPUT_VALUE D_IN_1 D_IN_0 Pad D_OUT_1 D_OUT_0 (1,0) 0 1 OUTPUT_ENABLE = Statically defined by configuration program. Figure 3.6. iCE I/O Register Block Diagram Table 3.6. PIO Signal List Pin Name I/O Type Description OUTPUT_CLK Input Output register clock CLOCK_ENABLE Input Clock enable INPUT_CLK Input Input register clock OUTPUT_ENABLE Input Output enable D_OUT_0/1 Input Data from the core D_IN_0/1 LATCH_INPUT_VALUE Output Input Data to the core Latches/holds the Input Value © 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02029-3.6 17 iCE40 LP/HX Family Data Sheet Data Sheet 3.1.7. sysI/O Buffer Each I/O is associated with a flexible buffer referred to as a sysI/O buffer. These buffers are arranged around the periphery of the device in groups referred to as banks. The sysI/O buffers allow users to implement a wide variety of standards that are found in today’s systems including LVCMOS and LVDS25. High Current LED Drivers combine three sysI/O buffers together. This allows for programmable drive strength. This also allows for high current drivers that are ideal to drive three white LEDs, or one RGB LED. Each bank is capable of supporting multiple I/O standards including single-ended LVCMOS buffers and differential LVDS25E output buffers. Bank 3 additionally supports differential LVDS25 input buffers. Each sysI/O bank has its own dedicated power supply. Typical I/O Behavior During Power-up The internal power-on-reset (POR) signal is deactivated when VCC, VCCIO_2, VPP_2V5, and VCC_SPI have reached the level defined in Table 4.4. After the POR signal is deactivated, the FPGA core logic becomes active. It is your responsibility to ensure that all VCCIO banks are active with valid input logic levels to properly control the output logic states of all the I/O banks that are critical to the application. The default configuration of the I/O pins in a device prior to configuration is tri-stated with a weak pull-up to VCCIO. The I/O pins will maintain the pre-configuration state until VCC and VCCIO (for I/O banks containing configuration I/O) have reached levels, at which time the I/O will take on the software userconfigured settings only after a proper download/configuration. Unused I/O are automatically blocked and the pull-up termination is disabled. Supported Standards The iCE40 LP/HX sysI/O buffer supports both single-ended input/output standards, and used as differential comparators. The buffer supports the LVCMOS 1.8 V, 2.5 V, and 3.3 V standards. The buffer has individually configurable options for bus maintenance (weak pull-up or none). Table 3.7 and Table 3.8 show the I/O standards (together with their supply and reference voltages) supported by the iCE40 LP/HX devices. Table 3.7. Supported Input Standards I/O Standard VCCIO (Typical) 3.3 V 2.5 V 1.8 V LVCMOS33 Yes — — LVCMOS25 — Yes — LVCMOS18 — — Yes LVDS25* — Yes — SubLVDS* — — Yes Single-Ended Interfaces Differential Interfaces *Note: Bank 3 only. Table 3.8. Supported Output Standards I/O Standard VCCIO (Typical) Single-Ended Interfaces LVCMOS33 3.3 V LVCMOS25 2.5 V LVCMOS18 1.8 V Differential Interfaces LVDS25* — SubLVDS* — *Note: These interfaces can be emulated with external resistors in all devices. © 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 18 FPGA-DS-02029-3.6 iCE40 LP/HX Family Data Sheet Data Sheet 3.1.8. Non-Volatile Configuration Memory All iCE40 LP/HX devices provide a Non-Volatile Configuration Memory (NVCM) block which can be used to configure the device. For more information on the NVCM, refer to iCE40 Programming and Configuration (FPGA-TN-02001). 3.1.9. Power On Reset iCE40 LP/HX devices have power-on reset circuitry to monitor VCC, VCCIO_2, VPP_2V5, and VCC_SPI voltage levels during power-up and operation. At power-up, the POR circuitry monitors VCC, VCCIO_2, VPP_2V5, and VCC_SPI (controls configuration) voltage levels. It then triggers download from the on-chip NVCM or external Flash memory after reaching the power-up levels specified in the Power-On-Reset Voltage table in the DC and Switching Characteristics section of this data sheet. Before and during configuration, the I/O are held in tri-state. I/O are released to user functionality once the device has finished configuration. 3.2. Programming and Configuration This section describes the programming and configuration of the iCE40 LP/HX family. Device Programming The NVCM memory can be programmed through the SPI port. Device Configuration There are various ways to configure the Configuration RAM (CRAM) including:  Internal NVCM Download  From an SPI Flash (Master SPI mode)  System microprocessor to drive a Serial Slave SPI port (SSPI mode) The image to configure the CRAM can be selected by the user on power up (Cold Boot) or once powered up (Warm Boot). For more details on configuring the iCE40 LP/HX device, refer to iCE40 Programming and Configuration (FPGA-TN02001). 3.2.1. Power Saving Options iCE40 LP/HX devices are available in two options for maximum flexibility: LP and HX devices. The LP devices have ultra low static and dynamic power consumption. HX devices are designed to provide high performance. Both the LP and the HX devices operate at 1.2 V VCC. iCE40 LP/HX devices feature iCEGate and PLL low power mode to allow users to meet the static and dynamic power requirements of their applications. While these features are available in both device types, these features are mainly intended for use with iCE40 LP devices to manage power consumption. Table 3.9. Power Saving Features Description Device Subsystem Feature Description PLL When LATCHINPUTVALUE is enabled, puts the PLL into low-power mode; PLL output held static at last input clock value. To save power, the optional iCEGate latch can selectively freeze the state of individual, non-registered inputs within an I/O bank. Registered inputs are effectively frozen by their associated clock or clockenable control. iCEGate © 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02029-3.6 19 iCE40 LP/HX Family Data Sheet Data Sheet 4. DC and Switching Characteristics 4.1. Absolute Maximum Ratings Table 4.1. Absolute Maximum Ratings* Parameter Supply Voltage VCC Min Max Unit –0.5 1.42 V Output Supply Voltage VCCIO –0.5 3.60 V NVCM Supply Voltage VPP_2V5 –0.5 3.60 V PLL Supply Voltage VCCPLL –0.5 1.42 V I/O Tri-state Voltage Applied –0.5 3.60 V Dedicated Input Voltage Applied –0.5 3.60 V Storage Temperature (Ambient) –65 150 °C Junction Temperature (TJ) –55 125 °C *Notes:  Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  Compliance with the Thermal Management document is required.  All voltages referenced to GND.  I/O can support a 200 mV Overshoot above the Recommended Operating Conditions VCCIO (Max) and -200 mV Undershoot below VIL (Min). Overshoot and Undershoot is permitted for 25% duty cycle but must not exceed 1.6 ns. 4.2. Recommended Operating Conditions Table 4.2. Recommended Operating Conditions1 Symbol VCC1 VPP_2V5 VPP_FAST4 VCCPLL5,6 VCCIO1,2,3 Parameter Min Max Unit Core Supply Voltage 1.14 1.26 V Slave SPI Configuration 1.71 3.46 V Master SPI Configuration 2.30 3.46 V 2.30 2.30 N/A 1.14 1.71 1.71 –40 10.00 3.46 3.00 N/A 1.26 3.46 3.46 100 30.00 V V V V V V °C °C VPP_2V5 NVCM Programming and Operating Supply Voltage Configuration from NVCM NVCM Programming Optional fast NVCM programming supply. Leave unconnected. PLL Supply Voltage VCCIO0-3 I/O Driver Supply Voltage VCC_SPI Junction Temperature, Industrial Operation Junction Temperature NVCM Programming tJIND tPROG Notes: 1. Like power supplies must be tied together. For example, if VCCIO and VCC_SPI are both the same voltage, they must also be the same supply. 2. See recommended voltages by I/O standard in subsequent table. 3. VCCIO pins of unused I/O banks should be connected to the VCC power supply on boards. 4. VPP_FAST, used only for fast production programming, must be left floating or unconnected in applications, except CM36 and CM49 packages MUST have the VPP_FAST ball connected to VCCIO_0 ball externally. 5. No PLL available on the iCE40LP384 and iCE40LP640 device. 6. VCCPLL is tied to VCC internally in packages without PLL pins. © 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 20 FPGA-DS-02029-3.6 iCE40 LP/HX Family Data Sheet Data Sheet 4.3. Power Supply Ramp Rates Table 4.3. Power Supply Ramp Rates* Symbol tRAMP Parameter Min Max Unit All configuration modes. No power supply sequencing. 0.40 10 V/ms Configuring from Slave SPI. No power supply sequencing, 0.01 10 V/ms Configuring from NVCM. VCC and VPP_2V5 to be powered 0.25 ms before VCC_SPI. 0.01 10 V/ms Configuring from MSPI. VCC and VPP_SPI to be powered 0.25 ms before VPP_2V5. 0.01 10 V/ms Min Max Unit VCC 0.67 0.99 V VCCIO_2 0.70 1.59 V VCC_SPI 0.70 1.59 V VPP_2V5 0.70 1.59 V VCC 0.55 0.75 V VCCIO_2 0.86 1.29 V VCC_SPI 0.86 1.29 V VPP_2V5 0.86 1.33 V Power-On-Reset ramp-down trip point (band gap VCC based circuit monitoring VCC, VCCIO_2, VCC_SPI and VCCIO_2 VPP_2V5) — 0.64 V — 1.59 V VCC_SPI — 1.59 V VPP_2V5 — 1.59 V Power-On-Reset ramp-down trip point (band gap VCC based circuit monitoring VCC, VCCIO_2, VCC_SPI and VCCIO_2 VPP_2V5) — 0.75 V — 1.29 V VCC_SPI — 1.29 V VPP_2V5 — 1.33 V Power supply ramp rates for all power supplies Notes:  Assumes monotonic ramp rates.  iCE40LP384 requires VCC to be greater than 0.7 V when VCCIO and VCC_SPI are above GND. 4.4. Power-On-Reset Voltage Levels Table 4.4. Power-On-Reset Voltage Levels* Symbol Device Parameter VPORUP Power-On-Reset ramp-up trip point (band gap based circuit monitoring VCC, VCCIO_2, VCC_SPI and VPP_2V5) iCE40LP384 iCE40LP640, iCE40LP/HX1K, iCE40LP/HX4K, iCE40LP/HX8K VPORDN iCE40LP384 iCE40LP640, iCE40LP/HX1K, iCE40LP/HX4K, iCE40LP/HX8K Power-On-Reset ramp-up trip point (band gap based circuit monitoring VCC, VCCIO_2, VCC_SPI and VPP_2V5) *Note: These POR trip points are only provided for guidance. Device operation is only characterized for power supply voltages specified under recommended operating conditions. © 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02029-3.6 21 iCE40 LP/HX Family Data Sheet Data Sheet 4.5. Power-up Supply Sequence It is recommended to bring up the power supplies in the order below. Note: There is no specified timing delay between the power supplies. There is, however, a requirement for each supply to reach a level of 0.5 V, or higher, before any subsequent power supplies in the sequence are applied. 1. VCC and VCCPLL should be the first two supplies to be applied. Note that these two supplies can be tied together subject to the recommendation to include a RC-based noise filter on the VCCPLL. Refer to iCE40 Hardware Checklist (FPGA-TN-02006). 2. SPI_VCCIO1 should be the next supply, and can be applied any time after the previous supplies (VCC and VCCPLL) have reached as level of 0.5 V or higher. 3. VPP_2V5 should be the next supply, and can be applied any time after previous supplies (VCC, VCCPLL and SPI_VCCIO1) have reached a level of 0.5 V or higher. 4. Other Supplies (VCCIO0 and VCCIO2) do not affect device power-up functionality, and they can be applied any time after the initial power supplies (VCC and VCCPLL) have reached a level of 0.5 V or greater. There is no power down sequence required. However, when partial power supplies are powered down, it is required the above sequence to be followed when these supplies are re-powered up again. 4.6. ESD Performance Please refer to the iCE40 Product Family Qualification Summary for complete qualification data, including ESD performance. 4.7. DC Electrical Characteristics Over recommended operating conditions. Table 4.5. DC Electrical Characteristics Symbol Parameter Condition Min Typ Max Unit IIL, IIH1, 3, 4, 5, 6, 7 Input or I/O Leakage 0 V < VIN < VCCIO + 0.2 V — — ±10 µA Capacitance2 VCCIO = 3.3 V, 2.5 V, 1.8 V VCC = Typ, VIO = 0 to VCCIO + 0.2 V — 6 — pf C26, 7 Global Input Buffer Capacitance2 VCCIO = 3.3 V, 2.5 V, 1.8 V VCC = Typ, VIO = 0 to VCCIO + 0.2 V — 6 — pf VHYST Input Hysteresis VCCIO = 1.8 V, 2.5 V, 3.3 V — 200 — mV Internal PIO Pull-up VCCIO = 1.8 V, 0 ≤ VIN ≤ 0.65 * VCCIO −3 — −31 µA VCCIO = 2.5 V, 0 ≤ VIN ≤ 0.65 * VCCIO −8 — −72 µA VCCIO = 3.3 V, 0 ≤ VIN ≤ 0.65 * VCCIO −11 — −128 µA I/O C16, 7 6, 7 IPU Notes: 1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tri-stated. It is not measured with the output driver active. Internal pull-up resistors are disabled. 2. TJ 25 oC, f = 1.0 MHz. 3. Refer to VIL and VIH in the sysI/O Single-Ended DC Electrical Characteristics table. 4. Only applies to I/O in the SPI bank following configuration. 5. Some products are clamped to a diode when VIN is larger than VCCIO. 6. High current I/O has three sysI/O buffers connected together. 7. The iCE40LP640 and iCE40LP1K SWG16 package has CDONE and a sysI/O buffer are connected together. © 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 22 FPGA-DS-02029-3.6 iCE40 LP/HX Family Data Sheet Data Sheet 4.8. Static Supply Current – LP Devices Table 4.6. Supply Current– LP Devices1, 2, 3, 4 Symbol ICC Parameter Typ VCC4 Unit iCE40LP384 21 µA iCE40LP640 100 µA iCE40LP1K 100 µA iCE40LP4K 250 µA Device Core Power Supply iCE40LP8K 250 µA ICCPLL5, 6 PLL Power Supply All devices 0.5 µA IPP_2V5 NVCM Power Supply All devices 1.0 µA All devices 3.5 µA ICCIO, ICC_SPI Bank Power VCCIO = 2.5 V Supply4 Notes: 1. Assumes blank pattern with the following characteristics: all outputs are tri-stated, all inputs are configured as LVCMOS and held at VCCIO or GND, on-chip PLL is off. For more detail with your specific design, use the Power Calculator tool. Power specified with master SPI configuration mode. Other modes may be up to 25% higher. 2. Frequency = 0 MHz. 3. TJ = 25 °C, power supplies at nominal voltage. 4. Does not include pull-up. 5. No PLL available on the iCE40LP384 and iCE40LP640 device. 6. VCCPLL is tied to VCC internally in packages without PLL pins. 4.9. Static Supply Current – HX Devices Table 4.7. Supply Current– HX Devices1, 2, 3, 4 Symbol Parameter ICC Core Power Supply ICCPLL 5 Typ VCC4 Unit iCE40HX1K 296 µA iCE40HX4K 1140 µA iCE40HX8K 1140 µA Device PLL Power Supply All devices 0.5 µA IPP_2V5 NVCM Power Supply All devices 1.0 µA ICCIO, ICC_SPI Bank Power Supply4 VCCIO = 2.5 V All devices 3.5 µA Notes: 1. Assumes blank pattern with the following characteristics: all outputs are tri-stated, all inputs are configured as LVCMOS and held at VCCIO or GND, on-chip PLL is off. For more detail with your specific design, use the Power Calculator tool. Power specified with master SPI configuration mode. Other modes may be up to 25% higher. 2. Frequency = 0 MHz. 3. TJ = 25 °C, power supplies at nominal voltage. 4. Does not include pull-up. 5. VCCPLL is tied to VCC internally in packages without PLL pins. © 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02029-3.6 23 iCE40 LP/HX Family Data Sheet Data Sheet 4.10. Programming NVCM Supply Current – LP Devices Table 4.8. Programming NVCM Supply Current – LP Devices1, 2, 3, 4 Symbol ICC Parameter Core Power Supply Typ VCC5 Unit iCE40LP384 60 µA iCE40LP640 120 µA iCE40LP1K 120 µA iCE40LP4K 350 µA iCE40LP8K 350 µA Device All devices 0.5 µA ICCPLL6, 7 PLL Power Supply All devices 2.5 mA IPP_2V5 NVCM Power Supply All devices 3.5 mA ICCIO8, ICC_SPI Bank Power Supply4 iCE40LP384 60 µA Notes: 1. Assumes all inputs are held at VCCIO or GND and all outputs are tri-stated. 2. Typical user pattern. 3. SPI programming is at 8 MHz. 4. TJ = 25 °C, power supplies at nominal voltage. 5. Per bank. VCCIO = 2.5 V. Does not include pull-up. 6. No PLL available on the iCE40LP384 and iCE40LP640 devices. 7. VCCPLL is tied to VCC internally in packages without PLLs pins. 8. VPP_FAST, used only for fast production programming, must be left floating or unconnected in applications, except CM36 and CM49 packages MUST have the VPP_FAST ball connected to VCCIO_0 ball externally. 4.11. Programming NVCM Supply Current – HX Devices Table 4.9. Programming NVCM Supply Current – HX Devices1, 2, 3, 4 Symbol Parameter ICC Core Power Supply Device iCE40HX1K iCE40HX4K iCE40HX8K All devices All devices All devices Typ. VCC5 278 1174 1174 0.5 2.5 3.5 ICCPLL6, 7 PLL Power Supply IPP_2V5 NVCM Power Supply ICCIO7, ICC_SPI Bank Power Supply5 Notes: 1. Assumes all inputs are held at VCCIO or GND and all outputs are tri-stated. 2. Typical user pattern. 3. SPI programming is at 8 MHz. 4. TJ = 25 °C, power supplies at nominal voltage. 5. Per bank. VCCIO = 2.5 V. Does not include pull-up. 6. VCCPLL is tied to VCC internally in packages without PLL pins. 7. VPP_FAST, used only for fast production programming, must be left floating or unconnected in applications. Units µA µA µA µA mA mA © 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 24 FPGA-DS-02029-3.6 iCE40 LP/HX Family Data Sheet Data Sheet 4.12. Peak Startup Supply Current – LP Devices Table 4.10. Peak Startup Supply Current – LP Devices Symbol Parameter ICCPEAK Core Power Supply ICCPLLPEAK1, 2, 4 PLL Power Supply IPP_2V5PEAK NVCM Power Supply IPP_FASTPEAK3 NVCM Programming Supply ICCIOPEAK5, ICC_SPIPEAK Bank Power Supply Device iCE40LP384 Max 7.7 Units mA iCE40LP640 iCE40LP1K iCE40LP4K iCE40LP8K iCE40LP1K iCE40LP640 iCE40LP4K iCE40LP8K iCE40LP384 iCE40LP640 iCE40LP1K iCE40LP4K iCE40LP8K iCE40LP384 iCE40LP640 iCE40LP1K iCE40LP384 iCE40LP640 iCE40LP1K iCE40LP4K 6.4 6.4 15.7 15.7 1.5 1.5 8.0 8.0 3.0 7.7 7.7 4.2 4.2 5.7 8.1 8.1 8.4 3.3 3.3 8.2 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA iCE40LP8K 8.2 mA Notes: 1. No PLL available on the iCE40LP384 and iCE40LP640 device. 2. VCCPLL is tied to VCC internally in packages without PLLs pins. 3. VPP_FAST, used only for fast production programming, must be left floating or unconnected in applications, except CM36 and CM49 packages MUST have the VPP_FAST ball connected to VCCIO_0 ball externally. 4. While no PLL is available in the iCE40LP640 the ICCPLLPEAK is additive to ICCPEAK. 5. iCE40LP384 requires VCC to be greater than 0.7 V when VCCIO and VCC_SPI are above GND. © 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02029-3.6 25 iCE40 LP/HX Family Data Sheet Data Sheet 4.13. Peak Startup Supply Current – HX Devices Table 4.11. Peak Startup Supply Current – HX Devices Symbol Parameter ICCPEAK Core Power Supply ICCPLLPEAK* PLL Power Supply IPP_2V5PEAK NVCM Power Supply ICCIOPEAK, ICC_SPIPEAK Bank Power Supply Device Max Units iCE40HX1K iCE40HX4K iCE40HX8K iCE40HX1K iCE40HX4K iCE40HX8K iCE40HX1K iCE40HX4K iCE40HX8K iCE40HX1K iCE40HX4K 6.9 22.3 22.3 1.8 6.4 6.4 2.8 4.1 4.1 6.8 6.8 mA mA mA mA mA mA mA mA mA mA mA 6.8 mA iCE40HX8K *Note: VCCPLL is tied to VCC internally in packages without PLLs pins. 4.14. sysI/O Recommended Operating Conditions Table 4.12. sysI/O Recommended Operating Conditions Input/Output Standard Min. 3.14 2.37 1.71 2.37 1.71 VCCIO (V) Typ. 3.3 2.5 1.8 2.5 1.8 LVCMOS 3.3 LVCMOS 2.5 LVCMOS 1.8 LVDS25E1, 2 subLVDSE1, 2 Notes: 1. Inputs on-chip. Outputs are implemented with the addition of external resistors. 2. Does not apply to Configuration Bank VCC_SPI. Max. 3.46 2.62 1.89 2.62 1.89 © 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 26 FPGA-DS-02029-3.6 iCE40 LP/HX Family Data Sheet Data Sheet 4.15. sysI/O Single-Ended DC Electrical Characteristics Table 4.13. sysI/O Single-Ended DC Electrical Characteristics Input/Output Standard VIH1 VIL Min. (V) –0.3 LVCMOS 3.3 –0.3 LVCMOS 2.5 –0.3 LVCMOS 1.8 Max. (V) 0.8 0.7 0.35VCCIO Min. (V) 2.0 1.7 0.65VCCIO Max. (V) VOL Max. (V) VOH Min. (V) IOL Max. (mA) 0.4 VCCIO – 0.4 8, 162, 242 0.2 VCCIO – 0.2 0.1 0.4 VCCIO – 0.4 6, 122, 182 0.2 VCCIO – 0.2 0.1 0.4 VCCIO – 0.4 4, 82, 122 0.2 VCCIO – 0.2 0.1 VCCIO + 0.2 V VCCIO + 0.2 V VCCIO + 0.2 V IOH Max. (mA) –8, –162, –242 –0.1 –6, –122, –182 –0.1 –4, –82, – 122 –0.1 Notes: 1. 2. Some products are clamped to a diode when VIN is larger than VCCIO. Only for High Drive LED outputs. 4.16. sysI/O Differential Electrical Characteristics The LVDS25E/subLVDSE differential output buffers are available on all banks but the LVDS/subLVDS input buffers are only available on Bank 3 of iCE40 LP/HX devices. 4.16.1. LVDS25 Over recommended operating conditions. Table 4.14. LVDS25 Parameter Symbol VINP, VINM VTHD VCM IIN *Note: Typical Parameter Description Input Voltage Differential Input Threshold Input Common Mode Voltage Input Current Test Conditions VCCIO* = 2.5 — Min. Typ. Max. Units 0 250 — 350 2.5 450 V mV VCCIO* = 2.5 (VCCIO/2) - 0.3 VCCIO/2 (VCCIO/2) + 0.3 V Power on — — ±10 µA Min. Typ. Max. Units 0 100 — 150 1.8 200 V mV 4.16.2. subLVDS Over recommended operating conditions. Table 4.15. subLVDS Parameter Symbol VINP, VINM VTHD VCM IIN *Note: Typical Parameter Description Input Voltage Differential Input Threshold Input Common Mode Voltage Input Current Test Conditions VCCIO* = 1.8 — VCCIO* = 1.8 Power on (VCCIO/2) 0.25 — VCCIO/2 — (VCCIO/2) + 0.25 ±10 V µA © 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02029-3.6 27 iCE40 LP/HX Family Data Sheet Data Sheet 4.17. LVDS25E Emulation iCE40 LP/HX devices can support LVDSE outputs via emulation on all banks. The output is emulated using complementary LVCMOS outputs in conjunction with resistors across the driver outputs on all devices. The scheme shown in Figure 4.1. LVDS25E Using External Resistors is one possible solution for LVDS25E standard implementation. Resistor values in Figure 4.1. LVDS25E Using External Resistors are industry standard values for 1% resistors. V CCIO R R R OD OCM Differential Output Pair Figure 4.1. LVDS25E Using External Resistors Over recommended operating conditions. Table 4.16. LVDS25E DC Conditions Parameter ZOUT RS RP Description Output impedance Driver series resistor Driver parallel resistor Typ. 20 150 140 Units Ω Ω Ω RT VOH VOL VOD VCM ZBACK IDC Receiver termination Output high voltage Output low voltage Output differential voltage Output common mode voltage Back impedance DC output current 100 1.43 1.07 0.30 1.25 100.5 6.03 Ω V V V V Ω mA © 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 28 FPGA-DS-02029-3.6 iCE40 LP/HX Family Data Sheet Data Sheet 4.18. SubLVDS Emulation The iCE40 LP/HX family supports the differential subLVDS standard. The output standard is emulated using complementary LVCMOS outputs in conjunction with resistors across the driver outputs on all banks of the devices. The subLVDS input standard is supported by the LVDS25 differential input buffer. The scheme shown in Figure 4.2 is one possible solution for subLVDSE output standard implementation. Use LVDS25E mode with suggested resistors for subLVDSE operation. Resistor values in Figure 4.2 are industry standard values for 1% resistors. V CCIO R R R OD OCM Differential Output Pair Figure 4.2. subLVDSE DC Conditions Over recommended operating conditions. Table 4.17. subLVDSE DC Conditions Parameter ZOUT RS RP Description Output impedance Driver series resistor Driver parallel resistor Typ. 20 270 120 Units Ω Ω Ω RT VOH VOL VOD VCM ZBACK IDC Receiver termination Output high voltage Output low voltage Output differential voltage Output common mode voltage Back impedance DC output current 100 1.43 1.07 0.35 0.9 100.5 2.8 Ω V V V V Ω mA © 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02029-3.6 29 iCE40 LP/HX Family Data Sheet Data Sheet 4.19. Typical Building Block Function Performance – LP Devices* 4.19.1. Pin-to-Pin Performance (LVCMOS25) – LP Devices Table 4.18. Pin-to-Pin Performance (LVCMOS25) – LP Devices Function Basic Functions 16-bit decoder 4:1 MUX 16:1 MUX Timing Units 11.0 12.0 13.0 ns ns ns 4.19.2. Register-to-Register Performance – LP Devices Table 4.19. Register-to-Register Performance – LP Devices Function Timing Units Basic Functions 16:1 MUX 190 MHz 16-bit adder 160 MHz 16-bit counter 175 MHz Embedded Memory Functions 256 x 16 Pseudo-Dual Port RAM 240 MHz *Notes:  The above timing numbers are generated using the iCECube2 design tool. Exact performance may vary with device and tool version. The tool uses internal parameters that have been characterized but are not tested on every device.  Using a VCC of 1.14 V at Junction Temp 85 °C. © 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 30 FPGA-DS-02029-3.6 iCE40 LP/HX Family Data Sheet Data Sheet 4.20. Typical Building Block Function Performance – HX Devices* 4.20.1. Pin-to-Pin Performance (LVCMOS25) – HX Devices Table 4.20. Pin-to-Pin Performance (LVCMOS25) – HX Devices Function Basic Functions 16-bit decoder 4:1 MUX 16:1 MUX Timing Units 10.0 9.0 9.5 ns ns ns 4.20.2. Register-to-Register Performance – HX Devices Table 4.21. Register-to-Register Performance – HX Devices Function Timing Units Basic Functions 16:1 MUX 305 MHz 16-bit adder 220 MHz 16-bit counter 255 MHz 64-bit counter 105 MHz Embedded Memory Functions 256 x 16 Pseudo-Dual Port RAM 403 MHz Notes:  The above timing numbers are generated using the iCECube2 design tool. Exact performance may vary with device and tool version. The tool uses internal parameters that have been characterized but are not tested on every device.  Using a VCC of 1.14 V at Junction Temp 85 °C. 4.21. Derating Logic Timing Logic timing provided in the following sections of the data sheet and the Lattice design tools are worst case numbers in the operating range. Actual delays may be much faster. Lattice design tools can provide logic timing numbers at a particular temperature and voltage. © 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02029-3.6 31 iCE40 LP/HX Family Data Sheet Data Sheet 4.22. Maximum sysI/O Buffer Performance Table 4.22. Register-to-Register Performance1 I/O Standard Inputs LVDS252 subLVDS182 LVCMOS33 LVCMOS25 LVCMOS18 Outputs LVDS25E subLVDS18E LVCMOS33 LVCMOS25 LVCMOS18 Notes: 1. Measured with a toggling pattern. 2. Supported in Bank 3 only. Max. Speed Units 400 400 250 250 250 MHz MHz MHz MHz MHz 250 155 250 250 MHz MHz MHz MHz 155 MHz 4.23. Timing Adders Over recommended operating conditions. Table 4.23. Timing Adders – LP Devices* Input Adjusters LVDS25 LVDS, VCCIO = 2.5 V –0.18 subLVDS subLVDS, VCCIO = 1.8 V 0.82 LVCMOS33 LVCMOS, VCCIO = 3.3 V 0.18 LVCMOS25 LVCMOS, VCCIO = 2.5 V 0.00 LVCMOS18 LVCMOS, VCCIO = 1.8 V 0.19 Output Adjusters LVDS25E LVDS, Emulated, VCCIO = 2.5 V 0.00 subLVDSE subLVDS, Emulated, VCCIO = 1.8 V 1.32 LVCMOS33 LVCMOS, VCCIO = 3.3 V –0.12 LVCMOS25 LVCMOS, VCCIO = 2.5 V 0.00 LVCMOS18 LVCMOS, VCCIO = 1.8 V 1.32 *Notes:  Timing adders are relative to LVCMOS25 and characterized but not tested on every device.  LVCMOS timing measured with the load specified in the Switching Test Condition table.  All other standards tested according to the appropriate specifications.  Commercial timing numbers are shown.  Not all I/O standards are supported for all banks. See the Architecture section of this data sheet for details. ns ns ns ns ns ns ns ns ns ns © 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 32 FPGA-DS-02029-3.6 iCE40 LP/HX Family Data Sheet Data Sheet Over recommended operating conditions. Table 4.24. Timing Adders – HX Devices* Input Adjusters LVDS25 LVDS, VCCIO = 2.5 V 0.13 subLVDS subLVDS, VCCIO = 1.8 V 1.03 LVCMOS33 LVCMOS, VCCIO = 3.3 V 0.16 LVCMOS25 LVCMOS, VCCIO = 2.5 V 0.00 LVCMOS18 LVCMOS, VCCIO = 1.8 V 0.23 Output Adjusters LVDS25E LVDS, Emulated, VCCIO = 2.5 V 0.00 subLVDSE subLVDS, Emulated, VCCIO = 1.8 V 1.76 LVCMOS33 LVCMOS, VCCIO = 3.3 V 0.17 LVCMOS25 LVCMOS, VCCIO = 2.5 V 0.00 LVCMOS18 LVCMOS, VCCIO = 1.8 V 1.76 *Notes:  Timing adders are relative to LVCMOS25 and characterized but not tested on every device.  LVCMOS timing measured with the load specified in the Switching Test Condition table.  All other standards tested according to the appropriate specifications.  Commercial timing numbers are shown.  Not all I/O standards are supported for all banks. See the Architecture section of this data sheet for details. ns ns ns ns ns ns ns ns ns ns 4.24. External Switching Characteristics – LP Devices Over recommended operating conditions. Table 4.25. External Switching Characteristics – LP Devices1, 2 Parameter Clock Global Clocks fMAX_GBUF tW_GBUF Description Device Min. Max. Units Frequency for Global Buffer Clock network Clock Pulse Width for Global Buffer tSKEW_GBUF Global Buffer Clock Skew Within a Device All iCE40 LP devices All iCE40 LP devices iCE40LP384 iCE40LP640 iCE40LP1K iCE40LP4K iCE40LP8K — 0.92 — — — — — 275 — 370 230 230 340 340 MHz ns ps ps ps ps ps All iCE40 LP devices — 9.36 ns iCE40LP384 iCE40LP640 iCE40LP1K iCE40LP4K iCE40LP8K iCE40LP384 iCE40LP640 — — — — — — — 300 200 200 280 280 6.33 5.91 ps ps ps ps ps ns ns iCE40LP1K iCE40LP4K iCE40LP8K — — — 5.91 6.58 6.58 ns ns ns Pin-LUT-Pin Propagation Delay tPD Best case propagation delay through one LUT-4 General I/O Pin Parameters (Using Global Buffer Clock without PLL)3 tSKEW_IO Data bus skew across a bank of IOs tCO Clock to Output - PIO Output Register © 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02029-3.6 33 iCE40 LP/HX Family Data Sheet Data Sheet Parameter Description Device Min. Max. Units iCE40LP384 — ns — ns — ns — ns iCE40LP8K –0.08 –0.33 –0.33 –0.63 –0.63 — ns iCE40LP384 iCE40LP640 iCE40LP1K iCE40LP4K iCE40LP8K 1.99 2.81 2.81 3.48 3.48 — — — — — ns ns ns ns ns iCE40LP1K iCE40LP4K iCE40LP8K iCE40LP1K iCE40LP4K iCE40LP8K iCE40LP1K iCE40LP4K iCE40LP8K — — — 5.23 6.13 6.13 –0.90 –0.80 –0.80 2.20 2.30 2.30 — — — — — — ns ns ns ns ns ns ns ns ns iCE40LP640 tSU Clock to Data Setup - PIO Input Register iCE40LP1K iCE40LP4K tH Clock to Data Hold - PIO Input Register General I/O Pin Parameters (Using Global Buffer Clock with PLL)3 tCOPLL Clock to Output - PIO Output Register tSUPLL Clock to Data Setup - PIO Input Register tHPLL Clock to Data Hold - PIO Input Register Notes: 1. Exact performance may vary with device and design implementation. Commercial timing numbers are shown at 85°C and 1.14 V. Other operating conditions can be extracted from the iCECube2 software. 2. General I/O timing numbers based on LVCMOS 2.5, 0 pf load. 3. Supported on devices with a PLL. © 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 34 FPGA-DS-02029-3.6 iCE40 LP/HX Family Data Sheet Data Sheet 4.25. External Switching Characteristics – HX Devices Over recommended operating conditions. Table 4.26. External Switching Characteristics – HX Devices1, 2 Parameter Clock Global Clocks fMAX_GBUF tW_GBUF Description Device Min. Max. Units Frequency for Global Buffer Clock network Clock Pulse Width for Global Buffer tSKEW_GBUF Global Buffer Clock Skew Within a Device All iCE40 HX devices All iCE40 HX devices iCE40HX1K iCE40HX4K iCE40HX8K — 0.88 — — — 275 — 727 300 300 MHz ns ps ps ps All iCE40 HX devices — 7.30 ns iCE40HX1K iCE40HX4K iCE40HX8K iCE40HX1K iCE40HX4K iCE40HX8K — — — — — — 696 290 290 5.00 5.41 5.41 ps ps ps ns ns ns iCE40HX1K — ns — ns iCE40HX8K –0.23 –0.43 –0.43 — ns iCE40HX1K iCE40HX4K iCE40HX8K 1.92 2.38 2.38 — — — ns ns ns iCE40HX1K iCE40HX4K iCE40HX8K iCE40HX1K iCE40HX4K — — — 3.10 4.16 2.96 2.51 2.51 — — ns ns ns ns ns iCE40HX8K iCE40HX1K iCE40HX4K iCE40HX8K 4.16 –0.60 –0.53 –0.53 — — — — ns ns ns ns Pin-LUT-Pin Propagation Delay tPD Best case propagation delay through one LUT-4 General I/O Pin Parameters (Using Global Buffer Clock without PLL) tSKEW_IO Data bus skew across a bank of IOs tCO Clock to Output - PIO Output Register tSU Clock to Data Setup - PIO Input Register tH Clock to Data Hold - PIO Input Register iCE40HX4K General I/O Pin Parameters (Using Global Buffer Clock with PLL)3 tCOPLL Clock to Output - PIO Output Register tSUPLL Clock to Data Setup - PIO Input Register tHPLL Clock to Data Hold - PIO Input Register Notes: 1. Exact performance may vary with device and design implementation. Commercial timing numbers are shown at 85 °C and 1.14 V. Other operating conditions, including industrial, can be extracted from the iCECube2 software. 2. General I/O timing numbers based on LVCMOS 2.5, 0pf load. 3. Supported on devices with a PLL. © 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02029-3.6 35 iCE40 LP/HX Family Data Sheet Data Sheet 4.26. sysClock PLL Timing Over recommended operating conditions. Table 4.27. sysClock PLL Timing Parameter fIN fOUT fVCO AC Characteristics Descriptions Input Clock Frequency (REFERENCECLK, EXTFEEDBACK) Output Clock Frequency (PLLOUT) PLL VCO Frequency tDT Output Clock Duty Cycle tPH Output Phase Accuracy Output Clock Period Jitter tOPJIT1, 5 Output Clock Cycle-to-cycle Jitter Output Clock Phase Jitter tW tLOCK2, 3 tUNLOCK Output Clock Pulse Width PLL Lock-in Time PLL Unlock Time tIPJIT4 Input Clock Period Jitter tFDTAP tSTABLE3 tSTABLE_PW3 tRST tRSTREC Fine Delay adjustment, per Tap LATCHINPUTVALUE LOW to PLL Stable LATCHINPUTVALUE Pulse Width RESET Pulse Width RESET Recovery Time tDYNAMIC_WD DYNAMICDELAY Pulse Width tPDBYPASS Propagation delay with the PLL in bypass mode Conditions Min. Max. Units — 10 133 MHz — — 16 533 275 1066 MHz MHz fOUT < 175 MHz 40 50 % 35 65 "% — — — — — — — 1.3 — — +/–12 450 0.05 750 0.10 275 0.05 — 50 50 deg ps p-p UIPP ps p-p UIPP ps p-p UIPP ns us ns — 1000 ps p-p 175 MHz < fOUT < 275 MHz — fOUT 100 MHz fOUT 100 MHz fPFD 25 MHz At 90% or 10% — — fPFD  20 MHz fPFD < 20 MHz — 0.02 UIPP — — — — — — 147 — — 10 10 195 500 100 — — ps ns ns ns us 100 — iCE40 LP iCE40 HX 1.18 1.73 4.68 4.07 VCO Cycles ns ns Notes: 1. Period jitter sample is taken over 10,000 samples of the primary PLL output with a clean reference clock. Cycle-to-cycle jitter is taken over 1000 cycles. Phase jitter is taken over 2000 cycles. All values per JESD65B. 2. Output clock is valid after tLOCK for PLL reset and dynamic delay adjustment. 3. At minimum fPFD. As the fPFD increases the time will decrease to approximately 60% the value listed. 4. Maximum limit to prevent PLL unlock from occurring. Does not imply the PLL will operate within the output specifications listed in this table. 5. The jitter values will increase with loading of the PLD fabric and in the presence of SSO noise. © 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 36 FPGA-DS-02029-3.6 iCE40 LP/HX Family Data Sheet Data Sheet 4.27. SPI Master or NVCM Configuration Time Table 4.28. SPI Master or NVCM Configuration Time1, 2 Symbol tCONFIG Parameter POR/CRESET_B to Device I/O Active Condition Typ. Units iCE40LP384 - Low Frequency (Default) iCE40LP384 - Medium Frequency iCE40LP384 - High Frequency iCE40LP640 - Low Frequency (Default) iCE40LP640 - Medium Frequency iCE40LP640 - High Frequency iCE40LP/HX1K - Low Frequency (Default) iCE40LP/HX1K - Medium Frequency iCE40LP/HX1K - High Frequency iCE40LP/HX4K - Low Frequency (Default) iCE40LP/HX4K - Medium Frequency 25 15 11 53 25 13 53 25 13 230 110 ms ms ms ms ms ms ms ms ms ms ms iCE40LP/HX4K - High Frequency iCE40LP/HX8K - Low Frequency (Default) iCE40LP/HX8K - Medium Frequency iCE40LP/HX8K - High Frequency 70 230 110 70 ms ms ms ms Notes: 1. Assumes sysMEM Block is initialized to an all zero pattern if they are used. 2. The NVCM download time is measured with a fast ramp rate starting from the maximum voltage of POR trip point. © 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02029-3.6 37 iCE40 LP/HX Family Data Sheet Data Sheet 4.28. sysCONFIG Port Timing Specifications Table 4.29. sysCONFIG Port Timing Specifications1 Symbol Parameter Min Typ Max Unit 200 — — ns 49 — — Clock Cycles iCE40LP384 600 — — us iCE40LP640, iCE40LP/HX1K 800 — — us iCE40LP/HX4K 1200 — — us iCE40LP/HX8K 1200 — — us Write 1 — 25 MHz Read iCE40LP3842 — 15 — MHz Read iCE40LP640, iCE40LP/HX1K2 — 15 — MHz Read iCE40LP/HX4K2 — 15 — MHz Read iCE40LP/HX8K2 — 15 — MHz All Configuration Modes tCRESET_B tDONE_IO Minimum CRESET_B Low pulse width required to — restart configuration, from falling edge to rising edge Number of configuration clock cycles after CDONE goes — High before the PIO pins are activated Slave SPI tCR_SCK tCR_SCK Minimum time from a rising edge on CRESET_B until the first SPI write operation, first SPI_SCK. During this time, the iCE40 device is clearing its internal configuration memory. Minimum time from a rising edge on CRESET_B until the first SPI write operation, first SPI_SCK. During this time, the iCE40 LP/HX device is clearing its internal configuration memory. tCCLKH CCLK clock pulse width high — 20 — — ns tCCLKL CCLK clock pulse width low — 20 — — ns tSTSU CCLK setup time — 12 — ns tSTH CCLK hold time — 12 — — ns tSTCO CCLK falling edge to valid output — 13 — — ns Off 0 iCE40LP384 - Low Frequency (Default) 600 iCE40LP384 - Medium Frequency 600 iCE40LP384 - High Frequency iCE40LP640, iCE40LP/HX1K - Low Frequency (Default) iCE40LP640, iCE40LP/HX1K - Medium 600 Frequency iCE40LP640, iCE40LP/HX1K - High Frequency iCE40LP/HX1K -Low Frequency (Default) 800 iCE40LP/HX1K - Medium Frequency 800 iCE40LP/HX1K - High Frequency 800 iCE40LP/HX4K - Low Frequency (Default) 1200 — — — — — — — — — — — — — — MHz High Frequency3 — — — — Master SPI fMCLK tMCLK MCLK clock frequency CRESET_B high to first MCLK edge Low Frequency (Default) Medium Frequency 3 800 800 800 7.5 24 40 — — — — — — — — — — MHz MHz MHz us us us us us us us us us us © 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 38 FPGA-DS-02029-3.6 iCE40 LP/HX Family Data Sheet Data Sheet Symbol Parameter Min Typ Max Unit iCE40LP/HX4K - Medium Frequency 1200 1200 iCE40LP/HX8K - Low Frequency (Default) 1200 iCE40LP/HX8K - Medium Frequency 1200 iCE40LP/HX8K - High Frequency 1200 — — — — — us iCE40LP/HX4K - high frequency — — — — — us us us us Notes: 1. 2. 3. Does not apply for NVCM. Supported only with 1.2 V VCC and at 25 °C. Extended range fMAX Write operations support up to 53 MHz only with 1.2 V VCC and at 25 °C. 4.29. Switching Test Conditions Figure 4.3 shows the output test load that is used for AC testing. The specific values for resistance, capacitance, voltage, and other test conditions are listed in Table 4.30. VT R1 Test Point DUT CL Figure 4.3. Output Test Load, LVCMOS Standards Table 4.30. Test Fixture Required Components, Non-Terminated Interfaces* Test Condition LVCMOS settings (L ≥ H, H ≥ L) R1 ∞ CL 0 pF Timing Reference VT LVCMOS 3.3 = 1.5 V — LVCMOS 2.5 = VCCIO/2 — LVCMOS 1.8 = VCCIO/2 — LVCMOS 3.3 (Z ≥ H) 1.5 V VOL LVCMOS 3.3 (Z ≥ L) 1.5 V VOH Other LVCMOS (Z ≥ H) Other LVCMOS (Z ≥ L) 188 0 pF VCCIO/2 VOL VCCIO/2 VOH LVCMOS (H ≥ Z) VOH – 0.15 V VOL LVCMOS (L ≥ Z) VOL – 0.15 V VOH *Note: Output test conditions for all other interfaces are determined by the respective standards. © 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02029-3.6 39 iCE40 LP/HX Family Data Sheet Data Sheet 5. Pinout Information 5.1. Signal Descriptions 5.1.1. General Purpose Signal Name I/O Description IO[Bank]_[Row/Column Number][A/B] I/O [Bank] indicates the bank of the device on which the pad is located. [Number] indicates I/O number on the device. IO[Bank]_[Row/Column Number][A/B] I/O HCIO[Bank]_[Number] I/O High Current I/O. [Bank] indicates the bank of the device on which the pad is located. [Number] indicates IO number. NC — No connect GND — GND – Ground. Dedicated pins. It is recommended that all GNDs are tied together. VCC — VCC – The power supply pins for core logic. Dedicated pins. It is recommended that all VCCs are tied to the same supply. VCCIO_x — VCCIO – The power supply pins for I/O Bank x. Dedicated pins. All VCCIOs located in the same bank are tied to the same supply. [Bank] indicates the bank of the device on which the pad is located. [Number] indicates I/O number on the device. [A/B] indicates the differential I/O. 'A' = negative input. 'B' = positive input. 5.1.2. PLL and Global Functions (Used as user-programmable I/O pins when not used for PLL or clock pins) Signal Name I/O Description VCCPLLx — PLL VCC – Power. Dedicated pins. The PLL requires a separate power and ground that is quiet and stable to reduce the output clock jitter of the PLL. GNDPLLx — PLL GND – Ground. Dedicated pins. The sysCLOCK PLL has the DC ground connection made on the FPGA, so the external PLL ground connection (GNDPLL) must NOT be connected to the board’s ground. GBINx — Global pads. Two per side. © 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 40 FPGA-DS-02029-3.6 iCE40 LP/HX Family Data Sheet Data Sheet 5.1.3. Programming and Configuration Signal Name I/O Description CBSEL[0:1] I/O Dual function pins. I/O when not used as CBSEL. Optional ColdBoot configuration Select input, if ColdBoot mode is enabled. CRESET_B I Configuration Reset, active Low. Dedicated input. No internal pull-up resistor. Either actively drive externally or connect a 10 kΩ pull-up resistor to VCCIO_2. CDONE I/O Configuration Done. Includes a permanent weak pull-up resistor to VCCIO_2. If driving external devices with CDONE output, an external pullup resistor to VCCIO_2 may be required. Refer to the iCE40 Programming and Configuration (FPGA-TN-02001) for more details. Following device configuration the iCE40LP640 and iCE40LP1K in the SWG16 package CDONE pin can be used as a user output. VCC_SPI — SPI interface voltage supply input. Must have a valid voltage even if configuring from NVCM. SPI_SCK I/O Input Configuration Clock for configuring an FPGA in Slave SPI mode. Output Configuration Clock for configuring an FPGA configuration modes. SPI_SS I/O SPI Slave Select. Active Low. Includes an internal weak pull-up resistor to VCC_SPI during configuration. During configuration, the logic level sampled on this pin determines the configuration mode used by the iCE40 LP/HX device. An input when sampled at the start of configuration. An input when in SPI Peripheral configuration mode (SPI_SS = Low). An output when in Master SPI Flash configuration mode. SPI_SI I/O Slave SPI serial data input and master SPI serial data output SPI_SO I/O Slave SPI serial data output and master SPI serial data input VPP_FAST — Optional fast NVCM programming supply. VPP_FAST, used only for fast production programming, must be left floating or unconnected in applications, except CM36 and CM49 packages MUST have the VPP_FAST ball connected to VCCIO_0 ball externally. VPP_2V5 — VPP_2V5 NVCM programming and operating supply © 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02029-3.6 41 iCE40 LP/HX Family Data Sheet Data Sheet 5.2. Pin Information Summary iCE40LP384 iCE40LP640 iCE40LP1K SG32 CM362 CM492 SWG16 SWG16 CM361, CM491, CM81 CB81 QN84 CM121 CB121 2 2 General Purpose I/O per Bank Bank 0 6 4 10 3 3 4 10 17 17 17 24 24 Bank 1 5 7 7 0 0 7 7 15 16 17 25 21 Bank 2 0 4 4 1 1 4 4 11 8 11 18 19 Bank 3 6 6 12 2 2 6 10 16 17 18 24 24 Configuration 4 4 4 4 4 4 4 4 4 4 4 4 21 25 37 10 10 25 35 63 62 67 95 92 Total General Purpose Single Ended I/O Outputs per Bank High Current Bank 0 0 0 0 3 3 0 0 0 0 0 0 0 Bank 1 0 0 0 0 0 0 0 0 0 0 0 0 Bank 2 0 0 0 0 0 0 0 0 0 0 0 0 Bank 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 3 0 0 0 0 0 0 0 Total Current Outputs Differential Inputs per Bank Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 Bank 1 0 0 0 0 0 0 0 0 0 0 0 0 Bank 2 0 0 0 0 0 0 0 0 0 0 0 0 Bank 3 3 3 6 1 1 3 5 8 9 7 12 12 3 3 6 1 1 3 5 8 9 7 12 12 Total Differential Inputs Dedicated Inputs per Bank Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 Bank 1 0 0 0 0 0 0 0 0 0 0 0 0 Bank 2 2 2 2 1 1 2 2 2 2 2 2 2 Bank 3 0 0 0 0 0 0 0 0 0 0 0 0 Configuration 0 0 0 0 0 0 0 0 0 0 0 0 2 2 2 1 1 2 2 2 2 2 2 2 Total Dedicated InputsPins Vccio Bank 0 1 1 1 1 1 1 1 1 1 1 2 1 Bank 1 1 1 1 0 0 0 0 1 1 1 2 1 Bank 2 1 1 1 1 1 1 1 1 1 1 2 1 Bank 3 1 0 0 0 0 0 0 1 1 1 2 2 VCC 1 1 2 1 1 1 2 3 3 4 4 4 VCC_SPI 1 1 1 0 0 1 1 1 1 1 1 1 VPP_2V5 1 1 1 0 0 1 1 1 1 1 1 1 VPP_FAST3 0 0 0 0 0 1 1 1 0 1 1 1 VCCPLL 0 0 0 0 0 0 1 1 0 0 1 1 GND 2 3 3 2 2 3 4 5 8 4 8 11 NC 0 0 0 0 0 0 0 0 0 0 0 3 32 36 49 16 16 36 49 81 81 84 121 121 Total Count of Bonded Pins Notes: 1. VCCIO0 and VCCIO1 are connected together. 2. VCCIO2 and VCCIO3 are connected together. 3. VPP_FAST, used only for fast production programming, must be left floating or unconnected in applications, except CM36 and CM49 packages MUST have the VPP_FAST ball connected to VCCIO_0 ball externally. © 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 42 FPGA-DS-02029-3.6 iCE40 LP/HX Family Data Sheet Data Sheet CM81 General Purpose I/O per Bank Bank 0 17 Bank 1 15 Bank 2 9 Bank 3 18 Configuration 4 63 Total General Purpose Single Ended I/O High Current Outputs per Bank Bank 0 0 Bank 1 0 Bank 2 0 Bank 3 0 0 Total Differential Inputs Differential Inputs per Bank Bank 0 0 Bank 1 0 Bank 2 0 Bank 3 9 9 Total Differential Inputs Dedicated Inputs per Bank Bank 0 0 Bank 1 0 Bank 2 2 Bank 3 0 Configuration 0 2 Total Dedicated Inputs Vccio Pins Bank 0 1 Bank 1 1 Bank 2 1 Bank 3 1 VCC 3 VCC_SPI 1 VPP_2V5 1 VPP_FAST* 1 VCCPLL 1 GND 5 NC 0 81 Total Count of Bonded Pins iCE40LP4K CM121 CM225 CM81 iCE40LP8K CM121 CM225 VQ100 iCE40HX1K CB132 TQ144 23 21 19 26 4 93 46 42 40 46 4 178 17 15 9 18 4 63 23 21 19 26 4 93 46 42 40 46 4 178 19 19 12 18 4 72 24 25 20 22 4 95 23 25 20 24 4 96 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13 13 0 0 0 23 23 0 0 0 9 9 0 0 0 13 13 0 0 0 23 23 0 0 0 9 9 0 0 0 11 11 0 0 0 12 12 0 0 2 0 0 2 0 1 2 0 0 3 0 0 2 0 0 2 0 0 2 0 0 2 0 1 2 0 0 3 0 0 2 0 0 2 0 0 2 0 0 2 0 0 2 0 0 2 1 1 1 2 4 1 1 1 2 12 0 121 3 3 3 4 8 1 1 1 2 18 0 225 1 1 1 1 3 1 1 1 1 5 0 81 1 1 1 2 4 1 1 1 2 12 0 121 3 3 3 4 8 1 1 1 2 18 0 225 2 2 2 3 4 1 1 1 0 10 0 100 2 2 2 3 5 1 1 1 1 14 2 132 2 2 2 2 4 1 1 1 1 10 19 144 *Note: 1VPP_FAST, used only for fast production programming, must be left floating or unconnected in applications © 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02029-3.6 43 iCE40 LP/HX Family Data Sheet Data Sheet General Purpose I/O per Bank Bank 0 Bank 1 Bank 2 Bank 3 Configuration Total General Purpose Single Ended I/O BG121 iCE40HX4K CB132 TQ144 BG121 23 21 19 26 4 93 24 25 18 24 4 95 27 29 19 28 4 107 23 21 19 26 4 93 iCE40HX8K CB132 CM225 24 25 18 24 4 95 46 42 40 46 4 178 High Current Outputs per Bank Bank 0 0 0 0 0 0 0 Bank 1 0 0 0 0 0 0 Bank 2 0 0 0 0 0 0 Bank 3 0 0 0 0 0 0 Total Differential Inputs 0 0 0 0 0 0 Differential Inputs per Bank Bank 0 0 0 0 0 0 0 Bank 1 0 0 0 0 0 0 Bank 2 0 0 0 0 0 0 Bank 3 13 12 14 13 12 23 Total Differential Inputs 13 12 14 13 12 23 Dedicated Inputs per Bank Bank 0 0 0 0 0 0 0 Bank 1 0 0 0 0 0 0 Bank 2 2 2 2 2 2 2 Bank 3 0 0 0 0 0 0 Configuration 0 0 0 0 0 0 Total Dedicated Inputs 2 2 2 2 2 2 Vccio Pins Bank 0 1 2 2 1 2 3 Bank 1 1 2 2 1 2 3 Bank 2 1 2 2 1 2 3 Bank 3 2 3 2 2 3 4 VCC 4 5 4 4 5 8 VCC_SPI 1 1 1 1 1 1 VPP_2V5 1 1 1 1 1 1 VPP_FAST* 1 1 1 1 1 1 VCCPLL 2 2 2 2 2 2 GND 12 15 11 12 15 18 NC 0 0 6 0 0 0 Total Count of Bonded Pins 121 132 144 121 132 225 *Note: VPP_FAST, used only for fast production programming, must be left floating or unconnected in applications. CT256 52 52 46 52 4 206 0 0 0 0 0 0 0 0 26 26 0 0 2 0 0 2 4 4 4 4 6 1 1 1 2 20 0 256 © 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 44 FPGA-DS-02029-3.6 iCE40 LP/HX Family Data Sheet Data Sheet 5.3. iCE40 LP/HX Part Number Description 5.3.1. Ultra Low Power (LP) Devices ICE40LPXXX – XXXXXXX Device Family Shipping Method iCE40 FPGA TR = Tape and Reel TR50 = Tape and Reel 50 units TR1K = Tape and Reel 1,000 units Series LP = Low Power Series Package Logic Cells SWG16 = 16-Ball WLCSP (0.35 mm Pitch) CM36 = 36-Ball ucBGA (0.4 mm Pitch) CM49 = 49-Ball ucBGA (0.4 mm Pitch) CM81 = 81-Ball ucBGA (0.4 mm Pitch) CB81 = 81-Ball csBGA (0.5 mm Pitch) CM121 = 121-Ball ucBGA (0.4 mm Pitch) CB121 = 121-Ball csBGA (0.5 mm Pitch) CM225 = 225-Ball ucBGA (0.4 mm Pitch) SG32 = 32-Pin QFN (0.5 mm Pitch) QN84 = 84-Pin QFN (0.5 mm Pitch) 384 = 384 Logic Cells 640 = 640 Logic Cells 1K = 1,280 Logic Cells 4K = 3,520 Logic Cells 8K = 7,680 Logic Cells Figure 5.1. Low Power (LP) Devices 5.3.2. High Performance (HX) Devices ICE40HXXX – XXXXXXX Device Family Shipping Method iCE40 Mobile FPGA TR = Tape and Reel Series HX = High Performance Series Package Logic Cells CB132 = 132-Ball csBGA (0.5 mm Pitch) CM225 = 225-Ball ucBGA (0.4 mm Pitch) CT256 = 256-Ball caBGA (0.8 mm Pitch) TQ144 = 144-Pin TQFP (0.5 mm Pitch) VQ100 = 100-Pin VQFP (0.5 mm Pitch) BG121 = 121-Ball caBGA (0.8 mm Pitch) 1K = 1,280 Logic Cells 4K = 3,520 Logic Cells 8K = 7,680 Logic Cells Figure 5.2. High Performance (HX) Devices Note: All parts shipped in trays unless noted. 5.4. Ordering Information iCE40 LP/HX devices have top-side markings as shown below: © 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02029-3.6 45 iCE40 LP/HX Family Data Sheet Data Sheet Industrial iCE40HX8K CM225 Datecode Figure 5.3. High Performance (HX) Devices Note: Markings are abbreviated for small packages. 5.5. Ordering Part Numbers 5.5.1. Ultra Low Power Industrial Grade Devices, Halogen Free (RoHS) Packaging Part Number LUTs Supply Voltage Leads Temperature ICE40LP384-CM36 384 1.2 V Package Halogen-Free ucBGA 36 IND ICE40LP384-CM36TR 384 1.2 V Halogen-Free ucBGA 36 IND ICE40LP384-CM36TR1K 384 1.2 V Halogen-Free ucBGA 36 IND ICE40LP384-CM49 384 1.2 V Halogen-Free ucBGA 49 IND ICE40LP384-CM49TR 384 1.2 V Halogen-Free ucBGA 49 IND ICE40LP384-CM49TR1K 384 1.2 V Halogen-Free ucBGA 49 IND ICE40LP384-SG32 384 1.2 V Halogen-Free QFN 32 IND ICE40LP384-SG32TR 384 1.2 V Halogen-Free QFN 32 IND ICE40LP384-SG32TR1K 384 1.2 V Halogen-Free QFN 32 IND ICE40LP640-SWG16TR 640 1.2 V Halogen-Free WLCSP 16 IND ICE40LP640-SWG16TR50 640 1.2 V Halogen-Free WLCSP 16 IND ICE40LP640-SWG16TR1K 640 1.2 V Halogen-Free WLCSP 16 IND ICE40LP1K-SWG16TR 1280 1.2 V Halogen-Free WLCSP 16 IND ICE40LP1K-SWG16TR50 1280 1.2 V Halogen-Free WLCSP 16 IND ICE40LP1K-SWG16TR1K 1280 1.2 V Halogen-Free WLCSP 16 IND ICE40LP1K-CM36 1280 1.2 V Halogen-Free ucBGA 36 IND ICE40LP1K-CM36TR 1280 1.2 V Halogen-Free ucBGA 36 IND ICE40LP1K-CM36TR1K 1280 1.2 V Halogen-Free ucBGA 36 IND ICE40LP1K-CM49 1280 1.2 V Halogen-Free ucBGA 49 IND ICE40LP1K-CM49TR 1280 1.2 V Halogen-Free ucBGA 49 IND ICE40LP1K-CM49TR1K 1280 1.2 V Halogen-Free ucBGA 49 IND ICE40LP1K-CM81 1280 1.2 V Halogen-Free ucBGA 81 IND ICE40LP1K-CM81TR 1280 1.2 V Halogen-Free ucBGA 81 IND ICE40LP1K-CM81TR1K 1280 1.2 V Halogen-Free ucBGA 81 IND ICE40LP1K-CB81 1280 1.2 V Halogen-Free csBGA 81 IND ICE40LP1K-CB81TR 1280 1.2 V Halogen-Free csBGA 81 IND ICE40LP1K-CB81TR1K 1280 1.2 V Halogen-Free csBGA 81 IND ICE40LP1K-CM121 1280 1.2 V Halogen-Free ucBGA 121 IND ICE40LP1K-CM121TR 1280 1.2 V Halogen-Free ucBGA 121 IND ICE40LP1K-CM121TR1K 1280 1.2 V Halogen-Free ucBGA 121 IND ICE40LP1K-CB121 1280 1.2 V Halogen-Free csBGA 121 IND © 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 46 FPGA-DS-02029-3.6 iCE40 LP/HX Family Data Sheet Data Sheet Part Number LUTs Supply Voltage Leads Temperature ICE40LP1K-QN84 1280 1.2 V Package Halogen-Free QFN 84 IND ICE40LP4K-CM81 3520 1.2 V Halogen-Free ucBGA 81 IND ICE40LP4K-CM81TR 3520 1.2 V Halogen-Free ucBGA 81 IND ICE40LP4K-CM81TR1K 3520 1.2 V Halogen-Free ucBGA 81 IND ICE40LP4K-CM121 3520 1.2 V Halogen-Free ucBGA 121 IND ICE40LP4K-CM121TR 3520 1.2 V Halogen-Free ucBGA 121 IND ICE40LP4K-CM121TR1K 3520 1.2 V Halogen-Free ucBGA 121 IND ICE40LP4K-CM225 3520 1.2 V Halogen-Free ucBGA 225 IND ICE40LP8K-CM81 7680 1.2 V Halogen-Free ucBGA 81 IND ICE40LP8K-CM81TR 7680 1.2 V Halogen-Free ucBGA 81 IND ICE40LP8K-CM81TR1K 7680 1.2 V Halogen-Free ucBGA 81 IND ICE40LP8K-CM121 7680 1.2 V Halogen-Free ucBGA 121 IND ICE40LP8K-CM121TR 7680 1.2 V Halogen-Free ucBGA 121 IND ICE40LP8K-CM121TR1K 7680 1.2 V Halogen-Free ucBGA 121 IND ICE40LP8K-CM225 7680 1.2 V Halogen-Free ucBGA 225 IND 5.5.2. High-Performance Industrial Grade Devices, Halogen Free (RoHS) Packaging Part Number LUTs Supply Voltage Leads Temperature ICE40HX1K-CB132 1280 1.2 V Package Halogen-Free csBGA 132 IND ICE40HX1K-VQ100 1280 1.2 V Halogen-Free VQFP 100 IND ICE40HX1K-TQ144 1280 1.2 V Halogen-Free TQFP 144 IND ICE40HX4K-BG121 3520 1.2 V Halogen-Free caBGA 121 IND ICE40HX4K-BG121TR 3520 1.2 V Halogen-Free caBGA 121 IND ICE40HX4K-CB132 3520 1.2 V Halogen-Free csBGA 132 IND ICE40HX4K-TQ144 3520 1.2 V Halogen-Free TQFP 144 IND ICE40HX8K-BG121 7680 1.2 V Halogen-Free caBGA 121 IND ICE40HX8K-BG121TR 7680 1.2 V Halogen-Free caBGA 121 IND ICE40HX8K-CB132 7680 1.2 V Halogen-Free csBGA 132 IND ICE40HX8K-CM225 7680 1.2 V Halogen-Free ucBGA 225 IND ICE40HX8K-CT256 7680 1.2 V Halogen-Free caBGA 256 IND © 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02029-3.6 47 iCE40 LP/HX Family Data Sheet Data Sheet Supplemental Information For Further Information A variety of technical documents for the iCE40 LP/HX family are available on the Lattice web site.  iCE40 Programming and Configuration (FPGA-TN-02001)  Memory Usage Guide for iCE40 Devices (FPGA-TN-02002)  iCE40 sysCLOCK PLL Design and Usage Guide (FPGA-TN-02009)  iCE40 Hardware Checklist (FPGA-TN-02006)  Using Differential I/O LVDS Sub-LVDS in iCE40 Devices (FPGA-TN-02213)  PCB Layout Recommendations for BGA Packages (FPGA-TN-02010)  iCE40 LED Driver Usage Guide (FPGA-TN-02021)  iCE40 Pinout Files  Thermal Management  Lattice design tools  IBIS  Package Diagrams  Schematic Symbols © 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 48 FPGA-DS-02029-3.6 iCE40 LP/HX Family Data Sheet Data Sheet Technical Support For assistance, submit a technical support case at www.latticesemi.com/techsupport. © 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02029-3.6 49 iCE40 LP/HX Family Data Sheet Data Sheet Revision History Revision 3.6, October 2020 Section Disclaimers Product Family Architecture DC and Switching Characteristics Change Summary Added this section. Updated Table 2.1. iCE40 LP/HX Family Selection Guide. Updated Figure 3.3. PLL Diagram.   Added Power-up Supply Sequence section. Updated Test Conditions values in Table 4.15. subLVDS. Revision 3.5, September 2018 Section All Pinout Information Change Summary  Changed document number from DS1040 to FPGA-DS-02029.  Updated document template. Changed signal name from SPI_SS_B to SPI_SS in Signal Descriptions table. Revision 3.4, October 2017 Section Pin Information Change Summary Modified the dedicated inputs for Bank 1 of iCE40HX1K (CB132, TQ144), iCE40HX4K (CB132, TQ144) and iCE40HX8K (CB132, CM225, CT256). Revision 3.3, March 2017 Section Introduction Architecture Pinout Information Ordering Information Supplemental Information Change Summary Updated Features section. Added 121-ball caBGA package for ICE40 HX4K/8K to Table 2.1, iCE40 LP/HX Family Selection Guide. Updated PLB Blocks section. Changed “subtracters” to “subtractors” in the Carry Logic description. Updated Clock/Control Distribution Network section. Switched the Clock Enable and the Reset headings in Table 3.1, Global Buffer (GBUF) Connections to Programmable Logic Blocks. Updated Pin Information Summary section. Added BG121 information under iCE40HX4K and iCE40HX8K. Updated iCE40 LP/HX Part Number Description section. Added Shipping Method and BG121 package under High Performance (HX) Devices. Updated Ordering Information section. Added part numbers for BG121 under HighPerformance Industrial Grade Devices, Halogen Free (RoHS) Packaging. Corrected reference to “Package Diagrams Data Sheet”. Revision 3.2, October 2015 Section Introduction DC and Switching Characteristics Change Summary Updated Features section. Added footnote to 16 WLCSP Programmable I/O: Max Inputs (LVDS25) in Table 2.1, iCE40 LP/HX Family Selection Guide. Updated sysCLOCK PLL Timing section. Changed tDT conditions. Updated Programming NVCM Supply Current – LP Devices section. Changed IPP_2V5 and ICCIO, ICC_SPI units. © 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 50 FPGA-DS-02029-3.6 iCE40 LP/HX Family Data Sheet Data Sheet Revision 3.1, March 2015 Section DC and Switching Characteristics Change Summary Updated sysI/O Single-Ended DC Electrical Characteristics section. Changed LVCMOS 3.3 and LVCMOS 2. 5 VOH Min. (V) from 0.5 to 0.4. Revision 3.0, July 2014 Section DC and Switching Characteristics Pinout Information Change Summary Revised and/or added Typ. VCC data in the following sections.  Static Supply Current – LP Devices  Static Supply Current – HX Devices  Programming NVCM Supply Current – LP Devices  Programming NVCM Supply Current – HX Devices In each section table, the footnote indicating Advanced device status was removed. Updated Pin Information Summary section. Added footnote 1 to CM49 under iCE40LP1K. Revision 2.9, April 2014 Section Ordering Information Change Summary Changed “i” to “I” in part number description and ordering part numbers. Added part numbers to the Ultra Low Power Industrial Grade Devices, Halogen Free (RoHS) Packaging table. Revision 2.8, February 2014 Section DC and Switching Characteristics Architecture DC and Switching Characteristics Ordering Information Change Summary Updated Features section.  Corrected standby power units.  Included High Current LED Drivers. Updated Table 2.1, iCE40 LP/HX Family Selection Guide.  Removed LP384 Programmable I/O for 81 ucBGA package. Updated Supported Standards section. Added information on High Current LED drivers. Corrected typos. Added footnote to the Peak Startup Supply Current – LP Devices table. Updated part number description in the Ultra Low Power (LP) Devices section. Added part numbers to the Ultra Low Power Industrial Grade Devices, Halogen Free (RoHS) Packaging table. Revision 2.7, October 2013 Section Introduction Architecture DC and Switching Characteristics Pinout Information Ordering Information Change Summary Updated Features list and iCE40 LP/HX Family Selection Guide table. Revised iCE40-1K device to iCE40LP/HX1K device. Added iCE40LP640 device information. Added iCE40LP640 and iCE40LP1K information. Added iCE40LP640 and iCE40LP1K information. © 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02029-3.6 51 iCE40 LP/HX Family Data Sheet Data Sheet Revision 2.6, September 2013 Section DC and Switching Characteristics Pinout Information Change Summary Updated Absolute Maximum Ratings section. Updated sysCLOCK PLL Timing – Preliminary table. Updated Pin Information Summary table. Revision 2.5, August 2013 Section Introduction DC and Switching Characteristics Pinout Information Change Summary Updated the iCE40 LP/HX Family Selection Guide table. Updated the following tables:  Absolute Maximum Ratings  Power-On-Reset Voltage Levels  Static Supply Current – LP Devices  Static Supply Current – HX Devices  Programming NVCM Supply Current – LP Devices  Programming NVCM Supply Current – HX Devices  Peak Startup Supply Current – LP Devices  sysI/O Recommended Operating Conditions  Typical Building Block Function Performance – HX Devices  External Switching Characteristics – HX Devices  sysCLOCK PLL Timing – Preliminary  SPI Master or NVCM Configuration Time Updated the Pin Information Summary table. Revision 2.4, July 2013 Section Introduction DC and Switching Characteristics Pinout Information Ordering Information Change Summary Updated the iCE40 LP/HX Family Selection Guide table. Updated the sysCONFIG Port Timing Specifications table. Updated footnote in DC Electrical Characteristics table. GDDR tables removed. Support to be provided in a technical note. Updated the Pin Information Summary table. Updated the top-side markings figure. Updated the Ultra Low Power Industrial Grade Devices, Halogen Free (RoHS) Packaging table. Revision 2.3, May 2013 Section DC and Switching Characteristics Change Summary Added new data from Characterization. Revision 2.2, April 2013 Section Introduction Architecture DC and Switching Characteristics Pinout Information Ordering Information Change Summary Added the LP8K 81 ucBGA. Corrected typos. Corrected typos. Added 7:1 LVDS waveforms. Corrected typos in signal descriptions. © 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 52 FPGA-DS-02029-3.6 iCE40 LP/HX Family Data Sheet Data Sheet Revision 2.1, March 2013 Section DC and Switching Characteristics Ordering Information Change Summary Recommended operating conditions added requirement for Master SPI. Updated Recommended Operating Conditions for VPP_2V5. Updated Power-On-Reset Voltage Levels and sequence requirements. Updated Static Supply Current conditions. Changed unit for tSKEW_IO from ns to ps. Updated range of CCLK fMAX. Updated ordering information to include tape and reel part numbers. Revision 2.0, September 2012 Section All Change Summary Merged SiliconBlue iCE40 LP and HX data sheets and updated to Lattice format. Revision 1.31, September 2012 Section Introduction Change Summary Updated Table 3.1. Revision 1.3, September 2012 Section All Architecture DC and Switching Characteristics Change Summary Production release.  Updated notes on Table 3.2: Recommended Operating Conditions.  Updated values in Table 3.3 and Table 3.4. Updated values in Table 4.2, Table 4.3 and Table 4.7. Revision 1.21, September 2012 Section Architecture Change Summary Updated Figure 3.3 and Figure 3.4 to specify iCE40. Revision 1.2, August 2012 Section All Change Summary Updated company name. Revision 1.1, July 2011 Section Product Family Change Summary Moved package specifications to iCE40 pinout Excel files. Updated Table 2.1 maximum I/O. Revision 1.01, July 2011 Section Product Family Change Summary Added 640, 1K and 4K to Table 4.3 configuration times. Updated Table 2.1 maximum I/O. Revision 1.0, July 2011 Section All Change Summary Initial release. © 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02029-3.6 53 www.latticesemi.com