iCE40 UltraPlus Breakout Board
User Guide
FPGA-UG-02001-1.2
April 2022
iCE40 UltraPlus Breakout Board
User Guide
Disclaimers
Lattice makes no warranty, representation, or guarantee regarding the accuracy of information contained in this document or the suitability of its
products for any particular purpose. All information herein is provided AS IS, with all faults and associated risk the responsibility entirely of the Buyer.
Buyer shall not rely on any data and performance specifications or parameters provided herein. Products sold by Lattice have been subject to limited
testing and it is the Buyer's responsibility to independently determine the suitability of any products and to test and verify the same. No Lattice
products should be used in conjunction with mission- or safety-critical or any other application in which the failure of Lattice’s product could create a
situation where personal injury, death, severe property or environmental damage may occur. The information provided in this document is
proprietary to Lattice Semiconductor, and Lattice reserves the right to make any changes to the information in this document or to any products at
any time without notice.
© 2016-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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iCE40 UltraPlus Breakout Board
User Guide
Contents
Acronyms in This Document ................................................................................................................................................. 5
1. Introduction .................................................................................................................................................................. 6
2. Features ........................................................................................................................................................................ 7
3. iCE40 UltraPlus Device .................................................................................................................................................. 8
4. Software Requirements ................................................................................................................................................ 9
5. Demonstration Design Shunts .................................................................................................................................... 10
6. Clock Sources .............................................................................................................................................................. 11
7. Board Power ............................................................................................................................................................... 12
8. Board Configuration and Programming....................................................................................................................... 13
9. Test Points .................................................................................................................................................................. 16
10.
RGB LED Demonstration Design and Software User Interface ............................................................................... 18
11.
Serial Communication Interface ............................................................................................................................. 21
11.1. LED Control through SPI .................................................................................................................................... 21
11.2. SPI Protocol ....................................................................................................................................................... 21
11.3. Register Definitions ........................................................................................................................................... 22
12.
Ordering Information.............................................................................................................................................. 24
Appendix A. Schematic Diagrams ....................................................................................................................................... 25
Appendix B. Bill of Materials............................................................................................................................................... 31
References .......................................................................................................................................................................... 35
Technical Support Assistance ............................................................................................................................................. 36
Revision History................................................................................................................................................................... 37
© 2016-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-UG-02001-1.2
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iCE40 UltraPlus Breakout Board
User Guide
Figures
Figure 2.1. iCE40 UltraPlus Breakout Board (Top Side) ........................................................................................................7
Figure 5.1. Default Shunt Locations ....................................................................................................................................10
Figure 8.1. Board Configuration for Programming Flash ....................................................................................................13
Figure 8.2. Device Property Settings for Programming Flash .............................................................................................14
Figure 8.3. Setting Status in Diamond Programmer for Programming Flash ......................................................................14
Figure 8.4. Device Property Settings for Programming iCE40 UltraPlus .............................................................................15
Figure 9.1. J52 Header ‘A’ Breakouts ..................................................................................................................................16
Figure 9.2. J2 Header ‘B’ Breakouts ....................................................................................................................................16
Figure 9.3. J3 Header ‘C’ Breakouts ....................................................................................................................................16
Figure 9.4. U6 PMOD Connector.........................................................................................................................................17
Figure 9.5. J1 Adardvark Connector ....................................................................................................................................17
Figure 9.6. Breakout Headers .............................................................................................................................................17
Figure 10.1. SPI Flash Selection (Horizontal) for J6 .............................................................................................................18
Figure 10.2. iCE40 UltraPlus Selection (Vertical) for J6.......................................................................................................19
Figure 10.3. iCE40 UltraPlus LED Demonstration Interface ................................................................................................19
Figure 11.1. SPI Physical Transaction ..................................................................................................................................21
Figure A.1. Block Diagram ...................................................................................................................................................25
Figure A.2. FTDI Connection ...............................................................................................................................................26
Figure A.3. DUT Connection ................................................................................................................................................27
Figure A.4. RGB,PMOD and HEADERS .................................................................................................................................28
Figure A.5. Regulator Connection .......................................................................................................................................29
Figure A.6. SPI .....................................................................................................................................................................30
Tables
Table 11.1. Register Address and Bit Field Allocation.........................................................................................................21
Table 11.2. Bit Field Functionality Definition ......................................................................................................................21
Table 11.3. RGB Color Code Definition ...............................................................................................................................22
Table 11.4. LED Brightness Code Definition .......................................................................................................................22
Table 11.5. Breathe Ramp Code Definition ........................................................................................................................23
Table 11.6. Blink Rate Code Definition ...............................................................................................................................23
Table 12.1. Ordering Information .......................................................................................................................................24
© 2016-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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iCE40 UltraPlus Breakout Board
User Guide
Acronyms in This Document
A list of acronyms used in this document.
Acronym
Definition
CMOS
FPGA
FTDI
I/O
LED
SPI
Complementary Metal-Oxide Semiconductor
Field Programmable Gate Array
Future Technology Devices International
Input/Output
Light-emitting Diode
Serial Peripheral Interface
© 2016-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-UG-02001-1.2
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iCE40 UltraPlus Breakout Board
User Guide
1. Introduction
Thank you for choosing the Lattice iCE40 UltraPlus™ Breakout Board.
This guide describes how to begin using the iCE40 UltraPlus Breakout Board, an easy-to-use platform for demonstrating
the high-current LED drive capabilities of the iCE40 UltraPlus, which has more memory to achieve functions mainly
required in the customer mobile market. Along with the evaluation board and accessories, this kit includes a pre-loaded
LED Driver Demo that demonstrates driving the RGB LEDs with a PWM circuit. In addition, most of the device's I/O pins
are accessible through one of the several header locations on the board, facilitating rapid prototyping of user functions.
The contents of this user guide include demo operation, top-level functional descriptions of the various portions of the
evaluation board, descriptions of the onboard connectors, shunts, and a complete set of schematics and the bill of
materials for the iCE40 UltraPlus Breakout Board.
Note: Static electricity can severely shorten the lifespan of electronic components. Be careful when handling the iCE40
UltraPlus Breakout Board as to not damage it from ESD.
© 2016-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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iCE40 UltraPlus Breakout Board
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2. Features
The iCE40 UltraPlus Breakout Board includes:
iCE40 UltraPlus Breakout Board – The iCE40 UltraPlus Breakout Board features the following on-board components
and circuits:
iCE40 UltraPlus (iCE40UP5K-SG48) device in a 48-PIN QFN package.
Example of a board using this 0.5mm pitch QFN package.
High-current LED output
iCE40 UltraPlus Current Measurements
Standard USB cable for device programming.
RoHS-compliant packaging and process
Pre-loaded Demo – The kit includes a pre-loaded demo to control the onboard RGB LED in conjunction with a
software run user interface.
USB Connector Cable – A mini B USB port provides power, a programming interface and communication for the
software RGB LED user interface to the iCE40 UltraPlus SPI port.
Figure 2.1 shows the top side of the iCE40 UltraPlus Breakout Board indicating the specific features that are designed on
the board.
USB
D13
Power Interface
LED Socket
iCE40UP5KSG48
RGB
LED
Figure 2.1. iCE40 UltraPlus Breakout Board (Top Side)
© 2016-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-UG-02001-1.2
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iCE40 UltraPlus Breakout Board
User Guide
3. iCE40 UltraPlus Device
The board features an iCE40UP5K FPGA with a 1.2 V core supply. The device package is 48-PIN QFN. For a complete
description of this device, see iCE40 UltraPlus Family Data Sheet (FPGA-DS-02008).
© 2016-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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FPGA-UG-02001-1.2
iCE40 UltraPlus Breakout Board
User Guide
4. Software Requirements
You should install the following software before you begin developing designs for the board:
Lattice iCEcube2 2017.01 (or higher)
Diamond Programmer 3. 9 (or higher)
These software are available at the Lattice website Design Software and IP page. Make sure you log in to
www.latticesemi.com, otherwise these software downloads are not visible. It is also recommended to download the
RGB LED software user interface which interfaces with the iCE40 UltraPlus Breakout Board. This user interface allows
you to control the RGB LED for color, brightness, blinking and breathing. Download the PC or MAC version of the user
interface at www.latticesemi.com.
© 2016-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-UG-02001-1.2
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iCE40 UltraPlus Breakout Board
User Guide
5. Demonstration Design Shunts
Lattice provides the RGB LED Driver Demo design programmed on the board. The RGB LED Driver Demo used in
conjunction with the software user interface illustrates the use of a PWM driver controlling the LEDs on the board.
Below is a description of the control jumpers for each LED.
The RGB LED transitions colors.
J27 can be used to probe RGB LED (Default shunted). If you remove J27, the RGB LED does not light up.
Figure 5.1 shows the default board shunt locations.
J28 – Enable DONE LED
J6 – Program SPI
Flash or iCE40UP
J7 – Isolate
SPI Flash CSn
J51 – Enable
12 MHz clock
J27 - RGB Shunts
Figure 5.1. Default Shunt Locations
© 2016-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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iCE40 UltraPlus Breakout Board
User Guide
6. Clock Sources
The board has a single 12 MHz clock source. The 12 MHz clock drives both the FTDI USB interface device, and the
iCE40UP5K device. The iCE40UP5K can be disconnected from the 12 MHz oscillator using J51. This is necessary, for
example, when iCE40UP5K device pin35 is mistakenly programmed as an output and prevents the FTDI USB interface
from operating.
© 2016-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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iCE40 UltraPlus Breakout Board
User Guide
7. Board Power
There are two versions of the Bill of Materials (BOM). Early versions have D11 populated with a CDBU0520 Schottky.
Later versions populate D11 with a CDSU4148. The later version diode complies with the voltage requirements on the
Vpp_2V5 pin for NVCM programming/configuration.
The board provides the following power features:
Board Power
Board power is derived from the USB connection.
D13 Blue LED indicates Board Power
iCE40 UltraPlus VCC/VCC_PLL
Onboard 1.2 V supply
ICC can be measured across the series resistor R76 (1 Ω) at TP11 and TP12
ICC_PLL can be measured across the series resistor R77 (1 Ω) at TP13 and TP14
iCE40 UltraPlus VCCIO
Onboard 3.3 V supply
ICC0 can be measured across the series resistor R73 (1 Ω) at TP5 and TP6
ICC1 can be measured across the series resistor R75 (1 Ω) at TP9 and TP10
ICC2 can be measured across the series resistor R74 (1 Ω) at TP7 and TP8
The power supplies on the iCE40 UltraPlus Breakout Board are simplified and suitable for booting from the external SPI
flash. The power supply sequencing does not conform to the NVCM boot requirements as specified in iCE40 UltraPlus
Family Data Sheet (FPGA-DS-02008). You may encounter intermittent boot success and/or higher than specified
startup currents when attempting to boot from NVCM.
© 2016-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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iCE40 UltraPlus Breakout Board
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8. Board Configuration and Programming
The board allows for programming of the iCE40 UltraPlus or the SPI Flash:
SPI Flash Programming J6 shunt pins 1-3 and 2-4 (Default shunted)
U5 Micron Technology Inc. part number N25Q032A13ESC40F
iCE40 UltraPlus Configuration or Programming J6 shunt pins 1-2 and 3-4
U1 iCE40UP5K – SG48
CRESETB can be asserted by pushing SW1
Can be probed with J11
Done LED D2
Can be probed with J28 (Default shunted)
The details of the iCE40 UltraPlus Board for SPI flash programming are shown in Figure 8.1.
J11 – CRESETB Probe
CRESETB Push-Button
J28 – Enable DONE LED
USB Interface
Socket
U5 – N25Q032A13ESC40F
J6 – Program SPI
Flash or iCE40 UltraPlus
J7 – Isolate SPI Flash CSn
J51 – Enable
12 MHz clock
U1 –
iCE40UP5K-SG48
Figure 8.1. Board Configuration for Programming Flash
To program SPI flash in Diamond Programmer:
1.
Make sure that the Standalone Diamond Programmer is installed.
2.
Connect the iCE40 UltraPlus breakout board through the USB cable to a PC or MAC.
3.
Start Diamond Programmer.
4.
Set Device Family to iCE40 UltraPlus” and Device to “iCE40UP5K”. Refer to Figure 8.3.
5.
Open the Device Properties dialog. Apply the settings highlighted in Figure 8.2.
Programming file is the bitmap file that will be programmed into the iCE40 UltraPlus breakout board.
Load from File button should be used to refresh fields such as “Data file size” and “End address(Hex)”.
© 2016-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-UG-02001-1.2
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iCE40 UltraPlus Breakout Board
User Guide
6.
Click OK to exit Device Properties dialog.
7.
Click the Program button in Diamond Programmer to download the bitstream file.
Figure 8.2. Device Property Settings for Programming Flash
Double-click to
set Device
Program button Family to iCE40
UltraPlus
Double-click to
set Device type
to iCE40UP5K
Double-click to
open the Device
Properties dialog
Figure 8.3. Setting Status in Diamond Programmer for Programming Flash
© 2016-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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iCE40 UltraPlus Breakout Board
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The differences between programming ICE40 UltraPlus and programming flash are described below.
To program ICE40 UltraPlus in Diamond Programmer:
1.
Change jumpers on J6, shunt pins 1-2 and 3-4.
2.
Apply the settings in the Device Properties dialog as shown in Figure 8.4.
Figure 8.4. Device Property Settings for Programming iCE40 UltraPlus
For more information on Diamond Programmer, please refer to its user guide.
© 2016-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-UG-02001-1.2
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iCE40 UltraPlus Breakout Board
User Guide
9. Test Points
The board features a number of headers and test connections which provide access to the iCE40 UltraPlus I/Os:
Figure 9.1. J52 Header ‘A’ Breakouts
Figure 9.2. J2 Header ‘B’ Breakouts
Figure 9.3. J3 Header ‘C’ Breakouts
© 2016-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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FPGA-UG-02001-1.2
iCE40 UltraPlus Breakout Board
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Figure 9.4. U6 PMOD Connector
Figure 9.5. J1 Adardvark Connector
The break-out headers and test connectors are shown in Figure 9.6.
U6 - "PMOD SOCKET"
J3 - "Header C"
J2 - "Header B"
J1 - "Aardvark SPI
emulator connector
J52 - "Header A"
Figure 9.6. Breakout Headers
© 2016-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-UG-02001-1.2
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iCE40 UltraPlus Breakout Board
User Guide
10. RGB LED Demonstration Design and Software User Interface
The iCE40 UltraPlus Breakout Board can demonstrate a complete controller for an RGB LED. Following are the steps to
run the demonstration. The software user interface tool used here is the same as the one used with the iCE40 Ultra
Breakout Board. You can refer to the Lattice website iCE40 Ultra Breakout Board page.
To run the demonstration:
1.
Ensure that the RGB LED user interface is installed.
2.
Make sure the jumpers on J6 are both in the horizontal position. This is the default pins 1-3 and 2-4 shorted
together.
Figure 10.1. SPI Flash Selection (Horizontal) for J6
3.
Connect the iCE40 UltraPlus breakout board through the USB cable to a PC or MAC.
4.
After the iCE40 UltraPlus device has initialized and the RGB LED is illuminated RED, change the J6 jumper positions
to vertical, shorting pins 1-2 and 3-4. This is required to allow the USB port to communicate with the iCE40UP5K
device.
© 2016-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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FPGA-UG-02001-1.2
iCE40 UltraPlus Breakout Board
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Figure 10.2. iCE40 UltraPlus Selection (Vertical) for J6
5.
Start the RGB user interface on the PC or MAC.
Figure 10.3. iCE40 UltraPlus LED Demonstration Interface
© 2016-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-UG-02001-1.2
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iCE40 UltraPlus Breakout Board
User Guide
Now you can control the RGB LED on the iCE40 UltraPlus Breakout Board. You can set the color, brightness, blinking
rate as well as breathing.
Note: The RGB user interface is the same demo tool used with iCE40 Ultra Breakout board.
© 2016-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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FPGA-UG-02001-1.2
iCE40 UltraPlus Breakout Board
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11. Serial Communication Interface
11.1. LED Control through SPI
The Software user interface demonstration program communicates with the iCE40 UltraPlus device using an SPI serial
communication channel. The SPI interface (mode 0) control link is implemented using a simple write-only protocol (see
Figure 11.1.)
CSn
SCK
MOSI
ADDR[7:0]
REG[15:8]
REG[7:0]
Figure 11.1. SPI Physical Transaction
11.2. SPI Protocol
Data on the MOSI serial line is transmitted MSB first.
Addr[7:0] – Controls which of the 16 bits are updated with REG data.
Note that Unspecified REG bits must be written, but are ignored.
Table 11.1. Register Address and Bit Field Allocation
Addr
Bits Written
Bit Position
0x13
0x14
0x15
0x16
0x19
REG[3:0]
REG[7:4]
REG[11:8]
REG[15:12]
REG[15:0]
------------dddd
--------cccc-------bbbb-------aaaa-----------aaaabbbbccccdddd
REG[15:0] – Consists of four control fields.
Table 11.2. Bit Field Functionality Definition
Field
aaaa
bbbb
cccc
dddd
Bit Positions
REG[15:12]
REG[11:8]
REG[7:4]
REG[3:0]
Function
RGB Color[3:0]
Brightness[3:0]
Breathe Ramp [3:0]
Blink Rate [3:0]
© 2016-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-UG-02001-1.2
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iCE40 UltraPlus Breakout Board
User Guide
11.3. Register Definitions
Table 11.3. RGB Color Code Definition
Default setting (hardware, software) is denoted by (*).
RGB Color[3:0]
0000*
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Color
Red
Orange
Yellow
Chartreuse
Green
Spring Green
Cyan
Azure
Blue
Violet
Magenta
Rose
—
—
—
White
Color Code
#FF0000
#FF7F00
#FFFF00
#7FFF00
#00FF00
#00FF7F
#00FFFF
#007FFF
#0000FF
#7F00FF
#FF00FF
#FF007F
—
—
—
#FFFFFF
Table 11.4. LED Brightness Code Definition
Brightness[3:0]
0000
Level (%)
6.25 (dim)
0001
0010
0011
0100
0101
0110
0111*
1000
1001
1010
1011
1100
1101
1110
1111
12.5
18.78
25
31.25
37.5
43.75
50
56.25
62.5
68.75
75
81.25
87.5
93.75
100 (bright)
© 2016-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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iCE40 UltraPlus Breakout Board
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Table 11.5. Breathe Ramp Code Definition
Breathe Ramp[3:0]
0000*
0001
Level (%)
.0x (fast)
.063x
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
.125x
.25x
.5x
1x
2x
4x (slow)
—
—
—
—
—
—
—
—
Table 11.6. Blink Rate Code Definition
Blink Rate[3:0]
0000
0001
0010
Level (%)
Always On
1/16 (fast)
1/8
0011
0100
0101*
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1/4
1/2
1
2
4
Always Off
—
—
—
—
—
—
—
© 2016-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-UG-02001-1.2
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iCE40 UltraPlus Breakout Board
User Guide
12. Ordering Information
Table 12.1. Ordering Information
Description
Ordering Part Number
iCE40 UltraPlus Breakout Board
iCE40UP5K-B-EVN
China RoHS Environment- Friendly
Use Period (EFUP)
© 2016-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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iCE40 UltraPlus Breakout Board
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Appendix A. Schematic Diagrams
5
4
3
2
1
BLOCK DIAGRAM
Page : 4
Header C
D
D
Page : 4
BANK 1 & 2
Switches
Page : 4
Aardvark Connector
iCE40UP5K-SG48
C
Page : 2
Page : 4
SPI
Page : 6
Page : 5
RGB
Header A
USB to SPI
Lattice Semiconductor FPGA
BANK 0
USB
Connector
BANK 1
SPI
C
BANK 0
B
B
Page : 3
Header B
Page : 4
A
A
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Title
Block Diagram
Size
B
Date:
5
4
3
Project
iCE40 UltraPlus Breakout Board
6-DEC-2015
2
Sheet
Schematic Rev
A
Board Rev
1
of 6
A
1
Figure A.1. Block Diagram
© 2016-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-UG-02001-1.2
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iCE40 UltraPlus Breakout Board
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5
4
3
2
1
FTDI CONNECTION
+3.3V
FB4
FB_60ohm
PART_NUMBER = HI0603P600R-10
Manufacturer = Laird-signal
C1
C2
4.7uF
0.1uF
+3.3V
D
D
FB5
VBUS_5V
R54
FB_60ohm
PART_NUMBER = HI0603P600R-10
Manufacturer = Laird-signal
1
1K
D13
Green
C64
C3
C4
4.7uF
0.1uF
VCC1_8FT
+3.3V
L4
0.1uF
2
600 OHM 800MA
0.1uF
+3.3V
SKT_MINIUSB_B_RA
VCC1_8FT
50
PART_NUMBER = 5075BMR-05-SM-CR
Manufacturer = Neltron
C
49
7
8
+3.3V
C10
C11
R9
10uF
R11
R12
R13
10K
10K
10K
20
31
42
56
ADBUS0
ADBUS1
ADBUS2
ADBUS3
ADBUS4
ADBUS5
ADBUS6
ADBUS7
VREGIN
VREGOUT
DM
DP
2.2K
14
+3.3V
VCCIO
VCCIO
VCCIO
VCCIO
C66
VPHY
VPLL
0
4
9
U2
FT2232HL
R49
VCORE
VCORE
VCORE
1
2
3
4
5
VCC
DD+
ID
GND
12
37
64
J5
0.1uF
R10
ACBUS0
ACBUS1
ACBUS2
ACBUS3
ACBUS4
ACBUS5
ACBUS6
ACBUS7
RESET#
12K
6
REF
U2
CS
CLK
DI
DO
1
2
3
4
63
62
61
FT_EECS
FT_EECLK
FT_EEDATA
93LC56-SO8
R19
2
2.2K
0.1uF
PART_NUMBER = 93LC56CT-I/SN
Manufacturer = Microchip
EECS
EECLK
EEDATA
BDBUS0
BDBUS1
BDBUS2
BDBUS3
BDBUS4
BDBUS5
BDBUS6
BDBUS7
OSCI
+3.3V
3
B
X1
C53
13
2
OE_ST#
GND
VDD
OUTPUT
4
0.1uF
FTDI High-Speed USB
3
12.0000MHZ
FT2232H
J51
2
1
ICE_CLK
3,4
2 PIN JPR
10
PART_NUMBER = SiT1602AC-12-33E-12.000
Manufacturer = SiTime
TEST
AGND
1
OSCO
PWREN#
SUSPEND#
R5
R6
R7
SS
0
R8
0
0
R70
R71
ICE_SCK
FLASH_MOSI
FLASH_MISO
3,4,6
6
6
ICE_SS
3,4,6
CDONE
CRESET_B
3
C
3
26
27
28
29
30
32
33
34
38
39
40
41
43
44
45
46
B
48
52
53
54
55
57
58
59
60
36
PART_NUMBER = FT2232HL-REEL
Manufacturer = FTDI
+3.3V
A
BCBUS0
BCBUS1
BCBUS2
BCBUS3
BCBUS4
BCBUS5
BCBUS6
BCBUS7
0
0
0
GND
GND
GND
GND
GND
GND
GND
GND
C12
VCC
NU
ORG
VSS
SCK
SI
SO
1
5
11
15
25
35
47
51
8
7
6
5
16
17
18
19
21
22
23
24
C5
0.1uF
C6
0.1uF
C7
0.1uF
C8
0.1uF
C9
0.1uF
A
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Title
FTDI Connection
Size
B
Date:
5
4
3
Project
iCE40 UltraPlus Breakout Board
6-DEC-2015
2
Sheet
Schematic Rev
A
Board Rev
2
of 6
A
1
Figure A.2. FTDI Connection
© 2016-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
26
FPGA-UG-02001-1.2
iCE40 UltraPlus Breakout Board
User Guide
5
4
3
2
1
DUT CONNECTION
TP12
DNI
VCC
1
R76
C98
0.1uF
10nF
5
30
100
C97
C96
10uF
100nF
29
+3.3V
VCC
SPI_VCCIO1
VCC
IOB_35B_SPI_SS
IOB_34A_SPI_SCK
IOB_33B_SPI_SI
IOB_32A_SPI_SO
VCCPLL
24
VPP_2V5
iCE40UP5K - SG48
CDSU4148
0.1uF
33
4
4
4
4
IOT_37A
IOT_36B
IOT_39A
IOT_38B
4
4
IOT_43A
IOT_42B
IOT_345A_G1
IOT_44B
IOT_49A
IOT_48B
IOT_51A
IOT_50B
IOT_41A
ICE_CLK
4
TP6
DNI
VCCIO_0
23
25
26
27
IOT_43A
IOT_42B
IOT_45A_G1
IOT_44B
IOT_49A
IOT_48B
IOT_51A
IOT_50B
IOT_41A
IOT_46B_G0
32
31
37
34
43
36
42
38
28
35
VCCIO_0
IOT_37A
IOT_36B
IOT_39A
IOT_38B
IOT_43A
IOT_42B
IOT_45A_G1
IOT_44B
IOT_49A
IOT_48B
IOT_51A
IOT_50B
IOT_41A
IOT_46B_G0
1
C87
C101
1uF
0.1uF
10nF
4
4
4
39
40
41
LED_BLUE
LED_GREEN
LED_RED
IOB_22A
IOB_23B
IOB_24A
IOB_25B_G3
IOB_29B
IOB_31B
IOB_20A
IOB_18A
IOB_16A
IOB_13B
16
15
17
14
ICE_SS
ICE_SCK
ICE_MOSI
ICE_MISO
8
7
CRESET_B
CDONE
12
21
13
20
19
18
11
10
9
6
VCCIO_2
IOB_8A
IOB_9B
IOB_4A
IOB_5B
IOB_2A
IOB_3B_G6
IOB_0A
IOB_6A
IOB_22A
IOB_23B
IOB_24A
IOB_25B_G3
IOB_29B
IOB_31B
IOB_20A
IOB_18A
IOB_16A
IOB_13B
ICE_SS
ICE_SCK
ICE_MOSI
ICE_MISO
CRESET_B
CDONE
IOB_22A
IOB_23B
IOB_24A
IOB_25B_G3
IOB_29B
IOB_31B
IOB_20A
IOB_18A
IOB_16A
IOB_13B
C99
2,4,6
2,4,6
4,6
4,6
1uF
C91
1
C92
10nF
0.1uF
2
2
4
4
4
4
4
4
4
4
4
C
4
TP8
DNI
1
4
3
48
45
47
44
46
2
TP9 +3.3V
DNI
R75
R74
IOB_8A
IOB_9B
IOB_4A
IOB_5B
IOB_2A
IOB_3B_G6
IOB_0A
IOB_6A
IOB_8A
IOB_9B
IOB_4A
IOB_5B
IOB_2A
IOB_3B_G6
IOB_0A
4
IOB_6A
4
C100
4
4
4
4
4
C89
0.1uF
1uF
C90
TP7 +3.3V
DNI
1
10nF
4
RGB0
RGB1
RGB2
B
iCE40UP5K- SG48
Paddle
GND
B
C88
CRESET_B
CDONE
22
VCCIO_2
1
R73
1
+3.3V TP5
DNI
4
4
4
4
4
4
2,4
IOT_37A
IOT_36B
IOT_39A
IOT_38B
Bank0
C
Bank2
C93
2
Bank1
D11
1
TP10
DNI
VCCIO_1
U1
R14
1
D
VCC_PLL
1
1
R77
TP14
DNI
C94
1uF
1
+1.2V TP13
DNI
C95
1
1
1
D
1
1
+1.2V TP11
DNI
+3.3V
Done LED
+3.3V
R34
10k
CRESETB Button
J11
Default: Open
SW1
2
1
CRESET_B
CRST
A
PART_NUMBER = TL1015AF160QG
Manufacturer = E-Switch
R35
2k2
J28
CRESET_B
1
2
A
CDONE
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
D3
PART_NUMBER = LG L29K-G2J1-24-Z
Green Manufacturer = Osram
CRST
PART_NUMBER = 77311-801-02LF
Manufacturer = FCI
DONE
PART_NUMBER = 77311-801-02LF
Manufacturer = FCI
Title
DUT Connection
Size
B
Date:
5
4
3
Project
iCE40 UltraPlus Breakout Board
6-DEC-2015
2
Sheet
Schematic Rev
A
Board Rev
3
of 6
A
1
Figure A.3. DUT Connection
© 2016-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-UG-02001-1.2
27
iCE40 UltraPlus Breakout Board
User Guide
5
4
3
2
1
RGB, PMOD and HEADERS
RGB LED
D
PMOD Socket
D
VBUS_5V
U10
R97
SM_R_0603
110
DI
1
3
5
R94
SM_R_0603
62
DI
2
5
2
1
CDBU0520
D10
R95
SM_R_0603
62
DI
1
6
2
HEADER 3X2
1
CDBU0520
J27
3,4
3,4
3,4
LED_RED
LED_GREEN
LED_BLUE
LED_RED
LED_GREEN
LED_BLUE
2
4
6
Default: Shunt
4
2
D9
+3.3V
+3.3V
D8
3
1
CDBU0520
U11
1
2
3
4
5
6
ICE_SS
ICE_MOSI
ICE_MISO
ICE_SCK
7
8
9
10
11
12
IOT_38B
IOT_39A
IOT_43A
IOT_42B
(Bank 0)
PMOD socket
DNI
Manufacturer = Seoul Semiconductor Inc
PART_NUMBER = SFT722N-S
LED TRI-COLOUR_1
C
C
+3.3V
+3.3V
+3.3V
MAKE PWR TRACES
CAPABLE OF 1A
C73
0.1uF
+3.3V
+3.3V
C75
0.1uF
C72
0.1uF
J52
3,4,6
3,4,6
2,3,4,6
2,3,4,6
ICE_MOSI
ICE_MISO
ICE_SCK
ICE_SS
ICE_MOSI
ICE_MISO
ICE_SCK
ICE_SS
2
4
6
8
10
11
J2
1
3
5
7
9
12
3
3
3,4
3,4
3,4
3,4
LED_BLUE
LED_GREEN
LED_RED
3
B
C76
0.1uF
C74
0.1uF
3
3
HEADER 5X2_0
DNI
IOT_37A
IOT_36B
IOT_39A
IOT_38B
IOT_43A
IOT_42B
IOT_37A
IOT_36B
IOT_39A
IOT_38B
IOT_43A
IOT_42B
IOT_345A_G1
IOT_44B
IOT_49A
IOT_44B
IOT_49A
J3
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
IOT_48B
IOT_51A
IOT_50B
IOT_41A
ICE_CLK
3
3
3
3
2,3
3
3
3
3
3
3
3
3
IOB_8A
IOB_9B
IOB_4A
IOB_5B
IOB_2A
IOB_3B_G6
IOB_0A
IOB_6A
1
3
5
7
9
11
13
15
17
19
Header2x10
DNI
R80
A
3
B
HEADER C
R79
R78
R72
DNI
DNI
DNI
DNI
4.7K
4.7K
4.7K
4.7K
SW2
1
2
3
4
1
2
3
4
A
8
7
6
5
8
7
6
5
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Title
RGB, PMOD and HEADERS
SW-DIP4
Size
B
Date:
4
3
3
3
3
3
3
PLACE THE RESISTORS ON THE TOP LAYER
IOT_37A
IOT_36B
IOT_44B
IOT_49A
5
3
3
3
(Bank 1)
(Bank 2)
HEADER B
VCCIO_0
IOB_22A
IOB_23B
IOB_24A
IOB_25B_G3
IOB_29B
IOB_31B
IOB_20A
IOB_18A
IOB_16A
IOB_13B
Header2x10
DNI
(Bank 0)
HEADER A
2
4
6
8
10
12
14
16
18
20
3
Project
iCE40 UltraPlus Breakout Board
6-DEC-2015
2
Sheet
Schematic Rev
A
Board Rev
4
of 6
A
1
Figure A.4. RGB,PMOD and HEADERS
© 2016-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
28
FPGA-UG-02001-1.2
iCE40 UltraPlus Breakout Board
User Guide
5
4
3
2
1
REGULATOR CONNECTION
D
D
VBUS_5V
+3.31V
Part Reference = U7
VCC_3.3V
+3.3V
R68
18
17
14
13
C65
R63
R62
20
10uF
1M
1M
11
IN1_1
IN1_2
IN2_1
IN2_2
OUT1_1
OUT1_2
3
4
C46
0.1
12
600 OHM 800MA
R64
C47
R66
C84
C49
357K
10uF
100
22uF
0.1uF
0.01uF
SHDN1
BYP1
SHDN2
ADJ1
2
R65
210K
1
VCC_1.2V
+1.22V
19
L6
+1.2V
R69
PWRGD1
OUT2_1
PWRGD2
OUT2_2
+3.3V
L7
7
8
0.1
C48
600 OHM 800MA
C67
R67
C85
4.7uF
100
22uF
0.01uF
BYP2
C43
C44
C45
10uF
1uF
0.1uF
0.01uF
C
+1.2V
LT3030EFE#TRPBF
PART_NUMBER = LT3030EFE#TRPBF
Manufacturer = Linear
+3.3V
B
DNI
DNI
DNI
TP1
TP2
TP3
1
GND3
GND2
C42
10
GND4
6
5
15
16
GND1
ADJ2
9
1
C
THERMPAD
1
21
+1.2V
C35
C36
C37
C38
C39
C40
C41
10uF
1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.01uF
B
A
A
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Title
Regulator Connection
Size
B
Date:
5
4
3
Project
iCE40 UltraPlus Breakout Board
6-DEC-2015
2
Sheet
Schematic Rev
A
Board Rev
5
of 6
A
1
Figure A.5. Regulator Connection
© 2016-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-UG-02001-1.2
29
iCE40 UltraPlus Breakout Board
User Guide
5
4
3
2
1
SPI
+3.3V
R25
10K
D
D
C63
Aardvark Connector
0.1uF
C15
ICE_SS
2
4
6
8
10
0.1uF
FLASH_MOSI
FLASH_MOSI
2,6
J1
SPI PGM
PART_NUMBER = 77313-801-10LF
U5
5
FLASH_MOSI
Manufacturer = FCI
2,3,4
6
ICE_SCK
J7
2,3,4,6
ICE_SS
3
1
2
1
SDI
CS
4
JU3
63429-202LF
63429-202LF
63429-202LF
R60
10K
10K
SDO
2
FLASH_MISO
WP
Short-circuit Jumper
JU2
R59
10K
SCK
C
JU1
R58
8
FLASH_MISO
ICE_SCK
GND1
NC2
NC1
MOSI
GND2
VCC
FLASH_MISO
ICE_SCK
ICE_SS
SS2
SS3
MISO
SCLK
SS1
GND
2,6
2,3,4
2,3,4,6
1
3
5
7
9
HOLD
7
C
N25Q032A13ESC40F
J9: Remove shunt only for Programming iCE.
Replace shunt for programming Flash and for normal operation.
J6
2,6
3,4
FLASH_MOSI
ICE_MOSI
3
1
ICE_MISO
4
2
FLASH_MISO
3,4
2,6
B
B
For programming Flash - Shunt 1,3 and 2,4 (default)
For programming iCE - Shunt 3,4 and 1,2
A
A
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Title
SPI
Size
B
Date:
5
4
3
Project
iCE40 UltraPlus Breakout Board
6-DEC-2015
2
Sheet
Schematic Rev
A
Board Rev
6
of 6
A
1
Figure A.6. SPI
© 2016-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
30
FPGA-UG-02001-1.2
iCE40 UltraPlus Breakout Board
User Guide
Appendix B. Bill of Materials
Item
Reference
Qty
Part
PCB Footprint
Part Number
Manufacturer
Description
1
C1,C3,C67
3
4.7uF
cc0603
ECJ-1VB0J475K
Panasonic
CAP CER 4.7UF 6.3V
10% X5R 0603
2
C2,C4,C5,C6,C7, C8,C9,C11,C12,
C15,C37,C38,C39,C40,C44,C49,C53,C63,C64,C66,C87,C89,C91,
C93,C94
25
0.1uF
cc0402
C0402C104K4RAC
TU
Kemet
CAP CER 0.1UF 16V
10% X7R 0402
3
C10,C35,C42,C47,C65
5
10uF
cc0603
4
C36,C43
2
1uF
cc0402
5
C41,C45,C46,C48
4
0.01uF
cc0402
6
C72,C73,C74,C75,C76
5
0.1uF
cc0603
7
C84,C85
2
22uF
cc0805
8
C88, C95, C99, C100
4
1uF
cc0402
9
C90, C92, C98, C101
4
10nF
cc0402
10
C96
1
100nF
cc0402
11
C97
1
10uF
cc0402
12
D3
1
Green
SM_D_0603
LG L29K-G2J1-24-Z
Osram
13
D8,D9,D10
3
CDBU0130R
diode_sod523f
CDBU0130R
Comchip
14
D11 (Older Version)
1
CDBU0520
diode_sod523f
CDBU0520
Comchip
15
D11 (Later Version)
1
CDSU4148
diode_sod523f
CDSU4148
Compchip
16
D13
1
Blue
led_0603
LTST-C190TBKT
LITE-On Inc.
LMK107BJ106MAL
TD
C0402C105K9PAC
TU
C0402C103J4RACT
U
C0603C104K4RAC
TU
LMK212BJ226MGT
C0402C105K4PAC
7867
C0402C103J4RACT
U
C0402C104K4RAC
TU
CL05A106MP5NU
NC
Taiyo Yuden
Kemet
Kemet
Kemet
Taiyo Yuden
Kemet
Kemet
Kemet
Samsung
CAP CER 10UF 10V
20% X5R 0603
CAP CER 1UF 6.3V
10% X5R 0402
CAP CER 10000PF
16V 5% X7R 0402
CAP CER 0.1UF 16V
10% X7R 0603
CAP CER 22UF 10V
20% X5R 0805
CAP CER 1UF 16V
10% X5R 0402
CAP CER 10000PF
16V 5% X7R 0402
CAP CER 0.1UF 16V
10% X7R 0402
CAP CER 10UF 10V
X5R 0402
LED SMARTLED
GREEN 570NM
0603
DIODE SCHOTTKY
30V 100MA 0603
DIODE SCHOTTKY
30V 100MA 0603
DIODE SCHOTTKY
30V 150MA 0603
LED BLUE CLEAR
0603 SMD
© 2016-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-UG-02001-1.2
31
iCE40 UltraPlus Breakout Board
User Guide
Item
Reference
Qty
Part
PCB Footprint
Part Number
Manufacturer
Description
FERRITE CHIP
POWER 60 Ω SMD
CONN HEADER .100
DUAL STR 10POS
CONN HEADER
20POS .100" TH
DUAL
CONN MINI USB
RCPT RA TYPE B
SMD
CONN HEADER
4POS .100" DBL
CONN HEADER
2POS .100" SGL
GOLD
CONN HEADER .100
SINGL STR 2POS
17
FB4,FB5
2
FB_60ohm
L0603
HI0603P600R-10
Laird-signal
18
J1
1
SPI PGM
hdr5x2
77313-801-10LF
FCI
19
J2,J3
2
Header2x10
hdr_samtec_m
tsw_2x10_100
MTSW-110-08-TD-300
Samtec
20
J5
1
SKT_MINIUS
B_B_RA
skt_miniusb_b
_ra
5075BMR-05-SMCR
Neltron
21
J6
1
TSW-102-07F-D
hdr_samtec_ts
w_2x2_100
TSW-102-07-F-D
Samtec
22
J7
1
TSW-102-07G-S
hdr_samtec_ts
w_1x2_100
TSW-102-07-G-S
Samtec
23
J11
1
CRST
HDR1X2-40
77311-801-02LF
FCI
24
J27
1
HEADER 3X2
HDR3x2
—
—
—
25
J28
1
DONE
HDR1X2-40
77311-801-02LF
FCI
CONN HEADER .100
SINGL STR 2POS
26
J51
1
2 PIN JPR
2PIN_100MIL
—
—
—
27
J52
1
HDR_6X2
—
—
—
28
L4,L6,L7
3
fb0603
BLM18HE601SN1
D
Murata
29
R5,R6,R7,R8,R49,R70,R71
7
0
cr0603
RC0603JR-070RL
Yageo
30
R9,R19
2
2.2K
cr0402
RC0402FR-072K2L
Yageo
31
R10
1
12K
cr0402
RC0402FR-0712KL
Yageo
32
R11,R12,R13,R25,R58,R59,R60
7
10K
cr0402
RC0402FR-0710KL
Yageo
33
R14
1
100
R0603
CRCW0603100RFK
EAHP
Vishay
HEADER
6X2_0
600 OHM
800MA
FERRITE CHIP 600 Ω
800MA 0603
RES 0.0 Ω 1/10W
JUMP 0603 SMD
RES 2.20 K Ω 1/16W
1% 0402 SMD
RES 12.0 K Ω 1/16W
1% 0402 SMD
RES 10.0 K Ω 1/16W
1% 0402 SMD
RES 100 Ω 0.25W
1% 0603 SMD
© 2016-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
32
FPGA-UG-02001-1.2
iCE40 UltraPlus Breakout Board
User Guide
Item
Reference
Qty
Part
PCB Footprint
Part Number
Manufacturer
34
R34
1
10k
R0603
ERJ-3EKF1002V
Panasonic
35
R35
1
2k2
R0603
ERJ-3EKF2201V
Panasonic
36
R54
1
1K
cr0402
ERJ-2GEJ102X
Panasonic
37
R62,R63
2
1M
cr0402
RC0402JR-071ML
Yageo
38
R64
1
357K
cr0603
ERJ-3EKF3573V
Panasonic
39
R65
1
210K
cr0402
ERJ-2RKF2103X
Panasonic
40
R66,R67
2
100
cr0603
RC0603FR07100RL
Yageo
41
R68,R69
2
0.1
cr0603
ERJ-3RSFR10V
Panasonic
42
R72,R78,R79,R80
4
4.7K
cr0603
CRCW06034K70FK
EA
Vishay
43
R73,R74,R75,R76,R77
5
1
cr0603
RC0603FR-071RL
Yageo
44
R94,R95
2
62
SM_R_0603
ERJ-3EKF62R0V
Panasonic
45
R97
1
110
SM_R_0603
ERJ-3EKF1100V
Panasonic
46
SW1
1
CRST
2psmd_eswitc
h
TL1015AF160QG
E-Switch
47
SW2
1
SW-DIP4
sw_sp_st_cts_
195-4mst
195-4MST
CTS
Electrocompo
nents
48
TP1,TP2,TP3
3
TP_S_40_63
tp_s_40_63
—
—
49
TP5,TP6,TP7,TP8,TP9,TP10,TP11,TP12,TP13,TP14
10
DNI
tp_s_40_63
—
—
Description
RES 10 K Ω 1/10W
1% 0603 SMD
RES 2.2 K Ω 1/10W
1% 0603 SMD
RES SMD 1 K Ω 5%
1/10W 0402
RES 1.0M Ω 1/16W
5% 0402 SMD
RES SMD 357 K Ω
1% 1/10W 0603
RES SMD 210 K Ω
1% 1/10W 0402
RES 100 Ω 1/10W
1% 0603 SMD
RES .10 Ω 1/10W
1% 0603 SMD
RES 4.70 K Ω 1/10W
1% 0603 SMD
RES SMD 1 Ω 1%
1/10W 0603
RES 62 Ω 1/10W 1%
0603 SMD
RES 110 Ω 1/10W
1% 0603 SMD
SWITCH TACTILE
SPST-NO 0.05 A 12V
SWITCH SIDE
ACTUATED 4 SEC
50V
Square test point,
40mil inner
diameter,
63mil outer
diameter
Square test point,
40mil inner
diameter,
© 2016-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-UG-02001-1.2
33
iCE40 UltraPlus Breakout Board
User Guide
Item
Reference
Qty
Part
PCB Footprint
Part Number
Manufacturer
Description
63mil outer
diameter
50
U1
1
iCE40UP5K/
3K- SG48
51
U2
1
FT2232HL
52
U3
1
93LC56-SO8
53
U4
1
LED TRICOLOUR_1
N25Q032A1
3ESC40F
iCE40UP5K_SG
48
tqfp64_0p5_12
p2x12p2_h1p6
—
—
FT2232HL-REEL
FTDI
so8_50_244
93LC56CT-I/SN
Microchip
6-PLCC
SFT722N-S
Seoul
Semiconducto
r Inc.
LED RED/GRN/BLU
CLEAR LENS 6PLCC
so8_50_244
N25Q032A13ESC4
0F
Micron
IC Flash Mem SerialSPI 3V/3.3V 32M-Bit
4M 7ns 8-Pin SO
T/R
HDR_2X6
—
—
—
tssop20_26_26
0_thrm_pad
LT3030EFE#TRPBF
Linear
54
U5
1
55
U6
1
56
U7
1
57
X1
1
12.0000MHZ
2_5mmx2mm
SiT1602AC-1233E-12.000
SiTime
58
iCE40 ULTRAPLUS BREAKOUT BOARD PCB
1
—
—
305-PD-16-0084
PACTRON
PMOD
socket
LT3030EFE#
TRPBF
—
IC USB HS DUAL
UART/FIFO 64-LQFP
IC EEPROM 2KBIT
3MHZ 8SOIC
IC REG LDO ADJ
20TSSOP
OSC MEMS 12MHZ
H/LV-CMOS SMD
—
© 2016-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
34
FPGA-UG-02001-1.2
iCE40 UltraPlus Breakout Board
User Guide
References
The standards used in this document and their abbreviations are listed on the table below.
Abbreviation
Standards Publication, Organization, and Date
HDMI
HCTS
High Definition Multimedia Interface, Revision 1.4a, HDMI Licensing LLC., March 2010
HDMI Compliance Test Specification, Revision 1.4a, HDMI Licensing LLC., March 2010
High-bandwidth Digital Content Protection, Revision 2.2, Digital Content Protection, LLC; February 2013
High-bandwidth Digital Content Protection, Revision 1.4, Digital Content Protection, LLC; July 2009
Digital Visual Interface, Revision 1.0, Digital Display Working Group, April 1999
Enhanced Extended Display Identification Data Standard, Release A Revision 1, VESA; February 2000
A DTV Profile For Uncompressed High Speed Digital Interfaces, EIA/CEA, July 2006
Enhanced Display Data Channel Standard, Version 1, VESA, September 1999
MHL (Mobile High-definition Link) Specification, Version 3.0, MHL, LLC, August 2013
HDCP
DVI
E-EDID
CEA-861-D
EDDC
MHL
For more information on the specifications that are applied in this document, contact the responsible standards groups
listed on the table below.
Standards Group
ANSI/EIA/CEA
VESA
HDCP
DVI
HDMI
MHL
Web URL
http://global.ihs.com
http://www.vesa.org
http://www.digital-cp.com
http://www.ddwg.org
http://www.hdmi.org
http://www.mhlconsortium.org
© 2016-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-UG-02001-1.2
35
iCE40 UltraPlus Breakout Board
User Guide
Technical Support Assistance
Submit a technical support case through www.latticesemi.com/techsupport.
© 2016-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
36
FPGA-UG-02001-1.2
iCE40 UltraPlus Breakout Board
User Guide
Revision History
Revision 1.2 April 2022
Section
Change Summary
All
Acronyms in This Document
Disclaimers
Board Power
Serial Communication Interface
Appendix A. Schematic Diagram
Appendix B. Bill of Materials
Revision History
Adjustments in formatting across the document.
Updated document ID of reference document iCE40 UltraPlus Family Datasheet from
DS1056 to FPGA-DS-02008.
Updated last page of the document.
Added this section.
Added this section.
Added a paragraph regarding BOM.
Changed section name form GUI Serial Communication Interface to Serial Communication
Interface.
Updated Figure A.3. DUT Connection to change CDBU0520 to CDSU4148.
Updated table to create two new rows for D11.
Updated table to new template.
Revision 1.1, March 2017
Section
All
Software Requirements
Appendix A. Schematic Diagram
Lattice Semiconductor
Documents
Change Summary
Corrected document status; removed “Preliminary”.
iCE40 UtraPlus Family Datasheet document number changed to DS1056.
Updated Lattice iCEcube2 to version 2017.01 and Diamond Programmer version to 3.9.
Updated figures.
Removed this section.
Revision 1.0, September 2016
Section
All
Change Summary
Initial release.
© 2016-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-UG-02001-1.2
37
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