ICE5LP1K-SWG36ITR50

iCE40 Ultra™ Family Data Sheet DS1048 Version 2.0, June 2016 iCE40 Ultra Family Data Sheet Introduction June 2016 Data Sheet DS1048 General Description iCE40 Ultra family is an ultra-low power FPGA and sensor manager designed for ultra-low power mobile applications, such as smartphones, tablets and hand-held devices. The iCE40 Ultra family includes integrated SPI and I2C blocks to interface with virtually all mobile sensors and application processors. The iCE40 Ultra family also features two on-chip oscillators, 10 kHz and 48 MHz. The LFOSC (10 kHz) is ideal for low power function in always-on applications, while HFOSC (48 MHz) can be used for awaken activities. The iCE40 Ultra family also features DSP functional block to off-load Application Processor to pre-process information sent from the mobile sensors. The embedded RGB PWM IP, with the three 24 mA constant current RGB outputs on the iCE40 Ultra provides all the necessary logic to directly drive the service LED, without the need of external MOSFET or buffer. The 500 mA constant current IR driver output provides a direct interface to external LED for application such as IrDA functions. Users simply implement the modulation logic that meets his needs, and connect the IR driver directly to the LED, without the need of external MOSFET or buffer. This high current IR driver can also be used as Barcode Emulation, sending barcode information to external Barcode Reader. The iCE40 Ultra family of devices are targeting for mobile applications to perform functions such as IrDA, Service LED, Barcode Emulation, GPIO Expander, SDIO Level Shift, and other custom functions. The iCE40 Ultra family features three device densities, from 1100 to 3520 Look Up Tables (LUTs) of logic with programmable I/Os that can be used as either SPI/I2C interface ports or general purpose I/O’s. It also has up to 80 kbits of Block RAMs to work with user logic. Features  Flexible Logic Architecture  On-chip DSP • Signed and unsigned 8-bit or 16-bit functions • Functions include Multiplier, Accumulator, and Multiply-Accumulate (MAC) • Three devices with 1100 to 3520 LUTs • Offered in WLCS, ucfBGA and QFN packages  Ultra-low Power Devices  Flexible On-Chip Clocking • Advanced 40 nm ultra-low power process • As low as 71 µA standby current typical • Eight low skew global signal resource, six can be directly driven from external pins • One PLL with dynamic interface per device  Embedded Memory • Up to 80 kbits sysMEM™ Embedded Block RAM  Two Hardened I2C Interfaces  Two Hardened SPI Interfaces  Two On-Chip Oscillators • Low Frequency Oscillator – 10 kHz • High Frequency Oscillator – 48 MHz  24 mA Current Drive RGB LED Outputs • Three drive outputs in each device • User selectable sink current up to 24 mA  Flexible Device Configuration • SRAM is configured through: — Standard SPI Interface — Internal Nonvolatile Configuration Memory (NVCM)  Ultra-Small Form Factor • As small as 2.078 mm x 2.078 mm  Applications  500 mA Current Drive IR LED Output • • • • • • • • One IR drive output in each device • User selectable sink current up to 500 mA Smartphones Tablets and Consumer Handheld Devices Handheld Commercial and Industrial Devices Multi Sensor Management Applications Sensor Pre-processing and Sensor Fusion Always-On Sensor Applications USB 3.1 Type C Cable Detect / Power Delivery Applications © 2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1-1 DS1048 Introduction_01.8 Introduction iCE40 Ultra Family Data Sheet Table 1-1. iCE40 Ultra Family Selection Guide Part Number iCE5LP1K iCE5LP2K iCE5LP4K Logic Cells (LUT + Flip-Flop) 1100 2048 3520 16 20 20 64 k 80 k 80 k 1 1 1 Yes Yes Yes 2 4 4 EBR Memory Blocks EBR Memory Bits PLL Block NVCM DSP Blocks (MULT16 with 32-bit Accumulator) Hardened I2C, SPI 1,1 2,2 2,2 HF Oscillator (48 MHz) 1 1 1 LF Oscillator (10 kHz) 1 1 1 24 mA LED Sink 3 3 3 500 mA LED Sink Embedded PWM IP 1 1 1 Yes Yes No Packages, ball pitch, dimension Total User I/O Count 36-ball WLCSP, 0.35 mm, 2.078 mm x 2.078 mm 26 26 26 36-ball ucfBGA, 0.40 mm, 2.5 mm x 2.5 mm 26 26 26 48-ball QFN Package, 0.5 mm, 7.0 mm x 7.0 mm 39 39 39 Introduction The iCE40 Ultra family of ultra-low power FPGAs has three devices with densities ranging from 1100 to 3520 LookUp Tables (LUTs) fabricated in a 40 nm Low Power CMOS process. In addition to LUT-based, low-cost programmable logic, these devices also feature Embedded Block RAM (EBR), on-chip Oscillators (LFOSC, HFOSC), two hardened I2C Controllers, two hardened SPI Controllers, three 24 mA RGB LED open-drain drivers, a 500 mA IR LED open-drain drivers, and DSP blocks. These features allow the devices to be used in low-cost, high-volume consumer and mobile applications. The iCE40 Ultra FPGAs are available in very small form factor packages, as small as 2.078 mm x 2.078 mm. The small form factor allows the device to easily fit into a lot of mobile applications, where space can be limited. Table 1-1 shows the LUT densities, package and I/O pin count. The iCE40 Ultra devices offer I/O features such as pull-up resistors. Pull-up features are controllable on a “per-pin” basis. The iCE40 Ultra devices also provide flexible, reliable and secure configuration from on-chip NVCM. These devices can also configure themselves from external SPI Flash, or be configured by an external master such as a CPU. Lattice provides a variety of design tools that allow complex designs to be efficiently implemented using the iCE40 Ultra family of devices. Popular logic synthesis tools provide synthesis library support for iCE40 Ultra. Lattice design tools use the synthesis tool output along with the user-specified preferences and constraints to place and route the design in the iCE40 Ultra device. These tools extract the timing from the routing and back-annotate it into the design for timing verification. Lattice provides in the iCE40 Ultra 1K and 2K device the embedded RGB PWM IP at no extra cost of LUT available to the user, to perform controlling the RGB LED function. This embedded IP allow users to control color, LED ON/ OFF time, and breathe rate of the LED. For more information, please refer to Usage Guide in Lattice Design Software. Lattice provides many pre-engineered IP (Intellectual Property) modules, including a number of reference designs, licensed free of charge, optimized for the iCE40 Ultra FPGA family. Lattice also can provide fully verified bitstream for some of the widely used target functions in mobile device applications, such as ultra-low power sensor management, gesture recognition, IR remote, barcode emulator functions. Users can use these functions as offered by Lattice, or they can use the design to create their own unique required functions. For more information regarding Lattice's reference designs or fully-verified bitstreams, please contact your local Lattice representative. 1-2 iCE40 Ultra Family Data Sheet Architecture June 2016 Data Sheet DS1048 Architecture Overview The iCE40 Ultra family architecture contains an array of Programmable Logic Blocks (PLB), two Oscillator Generators, two user configurable I2C controllers, two user configurable SPI controllers, and blocks of sysMEM™ Embedded Block RAM (EBR) surrounded by Programmable I/O (PIO). Figure 2-1shows the block diagram of the iCE5LP4K device. Figure 2-1. iCE5LP-4K Device, Top View I2C NVCM 5 4 Kbit RAM 5 4 Kbit RAM DSP 5 4 Kbit RAM LFOSC 5 4 Kbit RAM DSP DSP HFOSC IR Drv 8 Logic Cells = Programmable Logic Block I/O Bank 0 DSP RGB Drv PLB I2C config SPI I/O Bank 2 I/O Bank 1 SPI Carry Logic 4-Input Look-up Table (LUT) Flip-flop with Enable and Reset Controls The Programmable Logic Blocks (PLB) and sysMEM EBR blocks, are arranged in a two-dimensional grid with rows and columns. Each column has either PLB or EBR blocks. The PIO cells are located at the top and bottom of the device, arranged in banks. The PLB contains the building blocks for logic, arithmetic, and register functions. The PIOs utilize a flexible I/O buffer referred to as a sysIO buffer that supports operation with a variety of interface standards. The blocks are connected with many vertical and horizontal routing channel resources. The place and route software tool automatically allocates these routing resources. In the iCE40 Ultra family, there are three sysIO banks, one on top and two at the bottom. User can connect some VCCIOs together, if all the I/Os are using the same voltage standard. Refer to the details in later sections of this document on Power Up Sequence. The sysMEM EBRs are large 4 kbit, dedicated fast memory blocks. These blocks can be configured as RAM, ROM or FIFO with user logic using PLBs. Every device in the family has two user SPI ports, one of these (right side) SPI port also supports programming and configuration of the device. The iCE40 Ultra also includes two user I2C ports, two Oscillators, and high current RGB and IR LED sinks. © 2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 2-1 DS1048 Architecture_01.7 Architecture iCE40 Ultra Family Data Sheet PLB Blocks The core of the iCE40 Ultra device consists of Programmable Logic Blocks (PLB) which can be programmed to perform logic and arithmetic functions. Each PLB consists of eight interconnected Logic Cells (LC) as shown in Figure 2-2. Each LC contains one LUT and one register. Figure 2-2. PLB Block Diagram Shared Block-Level Controls Clock Programmable Logic Block (PLB) Enable FCOUT 1 Set/Reset 0 Logic Cell Carry Logic DFF 8 Logic Cells (LCs) I0 D O Q EN I1 LUT I2 SR I3 FCIN Four-input Look-Up Table (LUT) Flip-flop with optional enable and set or reset controls = Statically defined by configuration program Logic Cells Each Logic Cell includes three primary logic elements shown in Figure 2-2. • A four-input Look-Up Table (LUT) builds any combinational logic function, of any complexity, requiring up to four inputs. Similarly, the LUT element behaves as a 16x1 Read-Only Memory (ROM). Combine and cascade multiple LUTs to create wider logic functions. • A ‘D’-style Flip-Flop (DFF), with an optional clock-enable and reset control input, builds sequential logic functions. Each DFF also connects to a global reset signal that is automatically asserted immediately following device configuration. • Carry Logic boosts the logic efficiency and performance of arithmetic functions, including adders, subtracters, comparators, binary counters and some wide, cascaded logic functions. Table 2-1. Logic Cell Signal Descriptions Function Type Input Data signal Input Control signal Signal Names I0, I1, I2, I3 Enable Description Inputs to LUT Clock enable shared by all LCs in the PLB Input Control signal Set/Reset1 Asynchronous or synchronous local set/reset shared by all LCs in the PLB. Input Control signal Clock Clock one of the eight Global Buffers, or from the general-purpose interconnects fabric shared by all LCs in the PLB Input Inter-PLB signal FCIN Fast carry in Output Data signals Output Inter-PFU signal O FCOUT LUT or registered output Fast carry out 1. If Set/Reset is not used, then the flip-flop is never set/reset, except when cleared immediately after configuration. 2-2 Architecture iCE40 Ultra Family Data Sheet Routing There are many resources provided in the iCE40 Ultra devices to route signals individually with related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) segments. The inter-PLB connections are made with three different types of routing resources: Adjacent (spans two PLBs), x4 (spans five PLBs) and x12 (spans thirteen PLBs). The Adjacent, x4 and x12 connections provide fast and efficient connections in the diagonal, horizontal and vertical directions. The design tool takes the output of the synthesis tool and places and routes the design. Clock/Control Distribution Network Each iCE40 Ultra device has six global inputs, two pins on the top bank and four pins on the bottom bank These global inputs can be used as high fanout nets, clock, reset or enable signals. The dedicated global pins are identified as Gxx and each drives one of the eight global buffers. The global buffers are identified as GBUF[7:0]. These six inputs may be used as general purpose I/O if they are not used to drive the clock nets. Table 2-2 lists the connections between a specific global buffer and the inputs on a PLB. All global buffers optionally connect to the PLB CLK input. Any four of the eight global buffers can drive logic inputs to a PLB. Even-numbered global buffers optionally drive the Set/Reset input to a PLB. Similarly, odd-numbered buffers optionally drive the PLB clock-enable input. GBUF[7:6, 3:0] can connect directly to G[7:6, 3:0] pins respectively. GBUF4 and GBUF5 can connect to the two on-chip Oscillator Generators (GBUF4 connects to LFOSC, GBUF5 connects to HFOSC). Table 2-2. Global Buffer (GBUF) Connections to Programmable Logic Blocks Global Buffer Clock Clock Enable GBUF0   GBUF1  GBUF2  GBUF3  GBUF4 LUT Inputs Yes, any 4 of 8 GBUF Inputs  GBUF5  GBUF6  GBUF7  Reset        The maximum frequency for the global buffers are shown in the iCE40 Ultra External Switching Characteristics tables later in this document. Global Hi-Z Control The global high-impedance control signal, GHIZ, connects to all I/O pins on the iCE40 Ultra device. This GHIZ signal is automatically asserted throughout the configuration process, forcing all user I/O pins into their high-impedance state. Global Reset Control The global reset control signal connects to all PLB and PIO flip-flops on the iCE40 Ultra device. The global reset signal is automatically asserted throughout the configuration process, forcing all flip-flops to their defined wake-up state. For PLB flip-flops, the wake-up state is always reset, regardless of the PLB flip-flop primitive used in the application. 2-3 Architecture iCE40 Ultra Family Data Sheet sysCLOCK Phase Locked Loops (PLLs) The sysCLOCK PLLs provide the ability to synthesize clock frequencies. The iCE40 Ultra devices have one sysCLOCK PLL. REFERENCECLK is the reference frequency input to the PLL and its source can come from an external I/O pin, the internal Oscillator Generators from internal routing. EXTFEEDBACK is the feedback signal to the PLL which can come from internal routing or an external I/O pin. The feedback divider is used to multiply the reference frequency and thus synthesize a higher frequency clock output. The PLLOUT output has an output divider, thus allowing the PLL to generate different frequencies for each output. The output divider can have a value from 1 to 64 (in increments of 2X). The PLLOUT outputs can all be used to drive the iCE40 Ultra global clock network directly or general purpose routing resources can be used. The LOCK signal is asserted when the PLL determines it has achieved lock and de-asserted if a loss of lock is detected. A block diagram of the PLL is shown in Figure 2-3. The timing of the device registers can be optimized by programming a phase shift into the PLLOUT output clock which will advance or delay the output clock with reference to the REFERENCECLK clock. This phase shift can be either programmed during configuration or can be adjusted dynamically. In dynamic mode, the PLL may lose lock after a phase adjustment on the output used as the feedback source and not relock until the tLOCK parameter has been satisfied. There is an additional feature in the iCE40 Ultra PLL. There are 2 FPGA controlled inputs, SCLK and SDI, that allows the user logic to serially shift in data thru SDI, clocked by SCLK clock. The data shifted in would change the configuration settings of the PLL. This feature allows the PLL to be time multiplexed for different functions, with different clock rates. After the data is shifted in, user would simply pulse the RESET input of the PLL block, and the PLL will re-lock with the new settings. For more details, please refer to TN1251, iCE40 sysCLOCK PLL Design and Usage Guide. Figure 2-3. PLL Diagram RESET BYPASS BYPASS GNDPLL VCCPLL REFERENCECLK DIVR Phase Detector Input Divider RANGE Low-Pass Filter DIVQ Voltage Controlled Oscillator (VCO) VCO Divider SIMPLE SCLK DIVF PLLOUTCORE Feedback Divider Fine Delay Adjustment Feedback SDI Phase Shifter Fine Delay Adjustment Output Port PLLOUTGLOBAL Feedback_Path LOCK DYNAMICDELAY[7:0] EXTFEEDBACK LATCHINPUTVALUE EXTERNAL Low Power mode Table 2-3 provides signal descriptions of the PLL block. 2-4 Architecture iCE40 Ultra Family Data Sheet Table 2-3. PLL Signal Descriptions Signal Name Direction Description REFERENCECLK Input Input reference clock BYPASS Input The BYPASS control selects which clock signal connects to the PLLOUT output. 0 = PLL generated signal 1 = REFERENCECLK EXTFEEDBACK Input External feedback input to PLL. Enabled when the FEEDBACK_PATH attribute is set to EXTERNAL. DYNAMICDELAY[7:0] Input Fine delay adjustment control inputs. Enabled when DELAY_ADJUSTMENT_MODE is set to DYNAMIC. LATCHINPUTVALUE Input When enabled, puts the PLL into low-power mode; PLL output is held static at the last input clock value. Set ENABLE ICEGATE_PORTA and PORTB to ‘1’ to enable. PLLOUTGLOBAL Output Output from the Phase-Locked Loop (PLL). Drives a global clock network on the FPGA. The port has optimal connections to global clock buffers GBUF4 and GBUF5. PLLOUTCORE Output Output clock generated by the PLL, drives regular FPGA routing. The frequency generated on this output is the same as the frequency of the clock signal generated on the PLLOUTLGOBAL port. LOCK Output When High, indicates that the PLL output is phase aligned or locked to the input reference clock. RESET Input Active low reset. SCLK Input Input, Serial Clock used for re-programming PLL settings. SDI Input Input, Serial Data used for re-programming PLL settings. sysMEM Embedded Block RAM Memory Larger iCE40 Ultra device includes multiple high-speed synchronous sysMEM Embedded Block RAMs (EBRs), each 4 kbit in size. This memory can be used for a wide variety of purposes including data buffering, and FIFO. sysMEM Memory Block The sysMEM block can implement single port, pseudo dual port, or FIFO memories with programmable logic resources. Each block can be used in a variety of depths and widths as shown in Table 2-4. 2-5 Architecture iCE40 Ultra Family Data Sheet Table 2-4. sysMEM Block Configurations1 Block RAM Configuration and Size WADDR Port Size (Bits) WDATA Port Size (Bits) RADDR Port Size (Bits) RDATA Port Size (Bits) MASK Port Size (Bits) SB_RAM256x16 SB_RAM256x16NR SB_RAM256x16NW SB_RAM256x16NRNW 256x16 (4 k) 8 [7:0] 16 [15:0] 8 [7:0] 16 [15:0] 16 [15:0] SB_RAM512x8 SB_RAM512x8NR SB_RAM512x8NW SB_RAM512x8NRNW 512x8 (4 k) 9 [8:0] 8 [7:0] 9 [8:0] 8 [7:0] No Mask Port SB_RAM1024x4 SB_RAM1024x4NR SB_RAM1024x4NW SB_RAM1024x4NRNW 1024x4 (4 k) 10 [9:0] 4 [3:0] 10 [9:0] 4 [3:0] No Mask Port SB_RAM2048x2 SB_RAM2048x2NR SB_RAM2048x2NW SB_RAM2048x2NRNW 2048x2 (4 k) 11 [10:0] 2 [1:0] 11 [10:0] 2 [1:0] No Mask Port Block RAM Configuration 1. For iCE40 Ultra, the primitive name without "Nxx" uses rising-edge Read and Write clocks. "NR" uses rising-edge Write clock, falling-edge Read clock. "NW" uses falling-edge Write clock and rising-edge Read clock. "NRNW" uses falling-edge clocks on both Read and Write. 2-6 Architecture iCE40 Ultra Family Data Sheet RAM Initialization and ROM Operation If desired, the contents of the RAM can be pre-loaded during device configuration. By preloading the RAM block during the chip configuration cycle and disabling the write controls, the sysMEM block can also be utilized as a ROM. Memory Cascading Larger and deeper blocks of RAM can be created using multiple EBR sysMEM Blocks. RAM4k Block Figure 2-4 shows the 256x16 memory configurations and their input/output names. In all the sysMEM RAM modes, the input data and addresses for the ports are registered at the input of the memory array. Figure 2-4. sysMEM Memory Primitives Write Port Read Port WDATA[15:0] RDATA[15:0] MASK[15:0] RADDR[7:0] WADDR[7:0] WE RAM4K RAM Block (256x16) RE WCLKE RCLKE WCLK RCLK Table 2-5. EBR Signal Descriptions Signal Name Direction Description WDATA[15:0] Input Write Data input. MASK[15:0] Input Masks write operations for individual data bit-lines. 0 = write bit 1 = do not write bit WADDR[7:0] Input Write Address input. Selects one of 256 possible RAM locations. WE Input Write Enable input. WCLKE Input Write Clock Enable input. WCLK Input Write Clock input. Default rising-edge, but with falling-edge option. RDATA[15:0] Output RADDR[7:0] Input Read Data output. Read Address input. Selects one of 256 possible RAM locations. RE Input Read Enable input. RCLKE Input Read Clock Enable input. RCLK Input Read Clock input. Default rising-edge, but with falling-edge option. For further information on the sysMEM EBR block, please refer to TN1250, Memory Usage Guide for iCE40 Devices. 2-7 Architecture iCE40 Ultra Family Data Sheet sysDSP The iCE40 Ultra family provides an efficient sysDSP architecture that is very suitable for low-cost Digital Signal Processing (DSP) functions for mobile applications. Typical functions used in these applications are Multiply, Accumulate, and Multiply-Accumulate. The block can also be used for simple Add and Subtract functions. iCE40 Ultra sysDSP Architecture Features The iCE40 Ultra sysDSP supports many functions that include the following: • Single 16-bit x 16-bit Multiplier, or two independent 8-bit x 8-bit Multipliers • Optional independent pipeline control on Input Register, Output Register, and Intermediate Reg faster clock performance • Single 32-bit Accumulator, or two independent 16-bit Accumulators • Single 32-bit, or two independent 16-bit Adder/Subtracter functions, registered or asynchronous • Cascadable to create wider Accumulator blocks Figure 2-5 shows the block diagram of the sysDSP block. The block consists Multiplier section, with an bypassable Output register. The Input Register, Intermediate register between Multiplier and AC timing to achieve the highest performance. Figure 2-5. sysDSP Functional Block Diagram (16-bit x 16-bit Multiply-Accumulate) Input Registers SIGNEXTOUT C O COCAS Accumulator 0 1 Multiplier Q[31:16] 1 16x16 Pipeline Registers F A[15:8] 0 1 D B[15:8] C1 R 8x8 Q 0 D B[15:8] Q C22 J + [7:0] D Q [15:8] 8x8 0 B[15:0] BHLD D Q HLD C2 R B Q R 0 D Q [31:16] 0 1 LCO 1 [15:0] HLD R H C10 C7 LCOCA S Q[15:0 [7:0] 1 [7:0] 0 8x8 1 16x16=32 L [15:0] C6 R D B[7:0] P[23:16] K HLD A[7:0] C11 16x16 Pipeline Register 1 0 B[7:0] P[31:24] [15:0] + G [15:8] [15:0] [7:0] 1 C5 + P[15:8] OLADS Y 0 P[7:0] C19 ± Z 0 D 1 8x8=16 0 1 2 R 3 O[15:0] C16 D OLRST OLHLD OLLDA LCI C18 C17 1 C3 ILRST CLK ENA SIGNEXTIN 2-8 CICAS CI C20 1 3 1 0 2 0 C21 ASGND =C23 BSGND =C24 Lo C15 HLD R 0 Z[15] 2 Q Q HLD 0 3 D S R 1 1 D[15:0] DHLD Hi OHRST OHHLD OHLDA HCI 3 8x8 PowerSave A[15:8] C9 C8 2 [15:8] [15:8] IHRST O[31:16] X[15] 1 C6 R 3 0 8x8=16 HLD 8x8 2 R [15:0] 1 C4 R A[7:0] 1 HLD C14 Q HLD Q C13 D D 1 3 A[15:0] AHLD A 0 0 2 [15:0] 0 CSA R P ± X C12 C0 1 Q HLD Q 0 1 D 1 CSA C[15:0] CHLD OHADS W 0 C 0 0 Architecture iCE40 Ultra Family Data Sheet Table 2-6. sysDSP Input/Output List Primitive Port Name Width Input / Output CLK CLK 1 Input Clock Input. Applies to all clocked elements in the sysDSP block ENA CE 1 Input Clock Enable Input. Applies to all clocked elements in the sysDSP block. 0 = Not Enabled 1 = Enabled 0: Enabled A[15:0] A[15:0] 16 Input Input to the A Register. Feeds the Multiplier or is a direct input to the Adder Accumulator 16'b0 B[15:0] B[15:0] 16 Input Input to the B Register. Feeds the Multiplier or is a direct input to the Adder Accumulator 16'b0 C[15:0] C[15:0] 16 Input Input to the C Register. It is a direct input to the Adder Accumulator 16'b0 D[15:0] D[15:0] 16 Input Input to the D Register. It is a direct input to the Adder Accumulator 16'b0 AHLD AHOLD 1 Input A Register Hold. 0 = Update 1 = Hold 0: Update BHLD BHOLD 1 Input B Register Hold. 0 = Update 1 = Hold 0: Update CHLD CHOLD 1 Input C Register Hold. 0 = Update 1 = Hold 0: Update DHLD DHOLD 1 Input D Register Hold. 0 = Update 1 = Hold 0: Update IHRST IRSTTOP 1 Input Reset input to A and C input registers, and the pipeline registers in the upper half of the Multiplier Section. 0 = No Reset 1 = Reset 0: No Reset ILRST IRSTBOT 1 Input Reset input to B and D input registers, and the pipeline registers in the lower half of the Multiplier Section. It also resets the Multiplier result pipeline register. 0 = No Reset 1 = Reset 0: No Reset O[31:0] O[31:0] 32 Output Output of the sysDSP block. This output can be: — O[31:0] – 32-bit result of 16x16 Multiplier or MAC — O[31:16] – 16-bit result of 8x8 upper half Multiplier or MAC — O[15:0] – 16-bit result of 8x8 lower half Multiplier or MAC OHHLD OHOLDTOP 1 Input High-order (upper half) Accumulator Register Hold. 0 = Update 1 = Hold OHRST ORSTTOP 1 Input Reset input to high-order (upper half) bits of the Accumulator Register. 0 = No Reset 1 = Reset Signal Function 2-9 Default 0: Update 0: No Reset Architecture iCE40 Ultra Family Data Sheet Primitive Port Name Width Input / Output OHLDA OLOADTOP 1 Input High-order (upper half) Accumulator Register 0: AccumuAccumulate/Load control. late 0 = Accumulate, register is loaded with Adder/Subtracter results 1 = Load, register is loaded with Input C or C Register OHADS ADDSUBTOP 1 Input High-order (upper half) Accumulator Add or Subtract select. 0 = Add 1 = Subtract 0: Add OLHLD OHOLDBOT 1 Input Low-order (lower half) Accumulator Register Hold. 0 = Update 1 = Hold 0: Update OLRST ORSTBOT 1 Input Reset input to Low-order (lower half) bits of the Accumulator Register. 0 =No Reset 1 = Reset OLLDA OLOADBOT 1 Input Low-order (lower half) Accumulator Register Accu- 0: Accumulate mulate/Load control. 0 = Accumulate, register is loaded with Adder/Subtracter results 1 = Load, register is loaded with Input C or C Register OLADS ADDSUBBOT 1 Input Low-order (lower half) Accumulator Add or Subtract select. 0 = Add 1 = Subtract CICAS ACCUMCI 1 Input Cascade Carry/Borrow input from previous sysDSP block Signal CI COCAS CO SIGNEXTIN SIGNEXTOUT Function CI 1 Input ACCUMCO 1 Output Cascade Carry/Borrow output to next sysDSP block CO 1 Output Carry/Borrow output to higher logic tile SIGNEXTIN 1 Input SIGNEXTOUT 1 Output Carry/Borrow input from lower logic tile Sign extension input from previous sysDSP block Sing extension output to next sysDSP block The iCE40 Ultra sysDSP can support the following functions: • 8-bit x 8-bit Multiplier • 16-bit x 16-bit Multiplier • 16-bit Adder/Subtracter • 32-bit Adder/Subtracter • 16-bit Accumulator • 32-bit Accumulator • 8-bit x 8-bit Multiply-Accumulate • 16-bit x 16-bit Multiply-Accumulate Figure 2-6 shows the path for an 8-bit x 8-bit Multiplier using the upper half of sysDSP block. 2-10 Default 0: No Reset 0: Add Architecture iCE40 Ultra Family Data Sheet Figure 2-6. sysDSP 8-bit x 8-bit Multiplier Input Registers SIGNEXTOUT CO COCAS Accumulator 0 1 Multiplier Q[ 31 :16 ] OHADS W 0 0 C C[ 15 :0 ] CHLD D Q Q P 1 0 0 1 X C12 HLD D 1 C0 16 x16 Pipeline Registers R [ 15 :0 ] 1 Q O[ 31 :16 ] HLD 2 R 3 High X[ 15 ] 0 A 0 F A[ 15 :8 ] 0 C9 8 x8 =16 C8 1 OHRST OHHLD OHLDA [ 15:0 ] 2 Q [15:8] 1 3 R J 0 A[ 7 :0 ] D Q HLD CSA C6 R [15:8] C22 A[ 15 :8 ] 0 D Q BHLD Q H LCO 0 [ 15: 0 ] LCOCAS Q[ 15 :0 R 0 Q [ 15 :8 ] + OLADS P[ 15: 8 ] Y 0 [ 15: 0 ] [7:0] C19 8 x8 HLD R C5 D 1 8 x8 = 16 Q HLD R B C2 0 0 Z P[ 7: 0 ] 1 S R 1 B[ 7 :0 ] 1 1 C7 [7:0] 1 [ 31: 16 ] 1 [7:0] A[ 7 :0 ] Q D R C6 D 0 HLD K G D 16 x16 =32 [ 15: 0 ] HLD 8 x8 Register P[ 23: 16] L B[ 7 :0 ] B[ 15 :0 ] + 8 x8 PowerSave CSA IHRST C10 16 x 16 Pipeline [7:0] [15:0 ] [15:8] 8 x8 0 C11 1 B[ 15 :8 ] HCI P[ 31: 24] C13 8 x8 R + C4 C14 D B[ 15 :8 ] C1 3 1 2 Q HLD 1 D 0 1 AHLD 0 A[ 15 :0 ] O[ 15 :0 ] 2 3 Low Z[ 15 ] 0 R C16 C15 1 OLRST OLHLD 2 3 OLLDA LCI 0 1 D C18 C17 D[ 15 :0 ] DHLD D Q 1 HLD C3 C20 3 0 BSGND = C 24 2 C21 ASGND = C 23 1 R ILRST CLK 0 1 ENA ( 25 - FEB- 2012 ) SIGNEXTIN CICAS CI Figure 2-7 shows the path for an 16-bit x 16-bit Multiplier using the upper half of sysDSP block. 2-11 Architecture iCE40 Ultra Family Data Sheet Figure 2-7. DSP 16-bit x 16-bit Multiplier Input Registers SIGNEXTOUT COCAS CO Accumulator 0 1 Mulplier 1:16] Q[31 1 16x16 Pipeline Registers Q 1 D B[15::8] HLD C1 R 8xx8 Q A[7::0] Q HLD 8xx8 0 8xx8==16 J IHRST 0 D Q R B[15::0] BHLD D Q HLD 1 C2 R B 8xx8 Q R C10 16x16=32 16 L 0 D Q 1:16] [31 LCO 1 0 5:0] [15 HLD R H C7 1 LCOCAS 0] [7:0 1 0 D B[7::0] 16x16 Pipeline Register P[23 3:16 6] K Q[15 5:0 [7:0 0] C6 A[7::0] 0 + [15:0] [[1 15 1 5: 0 HLD 8xx8 C11 [15 5:8] 8xx8 PowerSave A[15::8] B[7::0] 1:24 4] P[31 5:0 0] [ 15 1 G [15:8] 15:0] [15 [ 7:0 7: 0] 1 C5 + P[15 5:8] OLADS Y 0 1 7:0] P[7 C19 0 1 8xx8=16 1 2 R 3 5:0] O[15 C16 D Low OLRST OLHLD OLLDA LCI C18 C17 1 0 BSGND =C24 C20 C21 ASGND =C23 3 C3 2 R 0 C15 1 Q HLD HL Q HLD 0 3 D D Z[15] 2 D[15::0] DHLD S R ± Z 1 0 High OHRST OHHLD OHLDA HCI 3 + [15 5:8] C22 C9 2 [7:0 0] C6 R O[31 1:16] C8 1 [15 5:8] 1 0 D B[15::8] 3 [ 15 5:0] C4 R 2 R C14 D 1 13 C1 A[15::0] AHLD 0 Q HLD X[15 5] F A[15::8] D 1 3 0 A 0 0 2 [15::0] 0 R Q P ± X C12 C0 1 Q HLD CSA D 1 CSA C[15::0] CHLD OHADS W 0 C 0 1 0 ILRST CLK ENA 0 SIGNEXTIN 2-12 1 CICAS CI (25 2) 5-FEB B-2012 Architecture iCE40 Ultra Family Data Sheet sysIO Buffer Banks iCE40 Ultra devices have up to three I/O banks with independent VCCIO rails. The configuration SPI interface signals are powered by SPI_VCCIO1. Please refer to the Pin Information Summary table. Programmable I/O (PIO) The programmable logic associated with an I/O is called a PIO. The individual PIOs are connected to their respective sysIO buffers and pads. The PIOs are placed on the top and bottom of the devices. Figure 2-8. I/O Bank and Programmable I/O Cell VCCIO I/O Bank 0 or 2 Voltage Supply I/O Bank 0 IR Drv I2C 0 = Hi-Z 1 = Output Enabled Pull-up Enable NVCM 5 4 Kbit RAM 5 4 Kbit RAM DSP 5 4 Kbit RAM OUTCLK LPSG Pull-up OE LFOSC 5 4 Kbit RAM DSP DSP HFOSC PLB RGB Drv OUT PAD OUTCLK iCEGATE HOLD DSP I2C PIO Enabled ‘1’ Disabled ‘0’ HD Latch inhibits switching for power saving IN config SPI I/O Bank 2 I/O Bank 1 SPI INCLK Gxx pins optionally connect directly to an associated GBUF global buffer The PIO contains three blocks: an input register block, output register block iCEGate™ and tri-state register block. To save power, the optional iCEGateTM latch can selectively freeze the state of individual, non-registered inputs within an I/O bank. Note that the freeze signal is common to the bank. These blocks can operate in a variety of modes along with the necessary clock and selection logic. Input Register Block The input register blocks for the PIOs on all edges contain registers that can be used to condition high-speed interface signals before they are passed to the device core. Output Register Block The output register block can optionally register signals from the core of the device before they are passed to the sysIO buffers. Figure 2-9 shows the input/output register block for the PIOs. 2-13 Architecture iCE40 Ultra Family Data Sheet Figure 2-9. iCE I/O Register Block Diagram PIO Pair CLOCK_ENABLE OUTPUT_CLK INPUT_CLK (1,0) LATCH_INPUT_VALUE D_IN_1 D_IN_0 Pad D_OUT_1 D_OUT_0 (1,0) 0 1 OUTPUT_ENABLE (1,0) LATCH_INPUT_VALUE D_IN_1 D_IN_0 Pad D_OUT_1 D_OUT_0 (1,0) 0 1 OUTPUT_ENABLE = Statically defined by configuration program. Table 2-7. PIO Signal List Pin Name OUTPUT_CLK I/O Type Input Description Output register clock CLOCK_ENABLE Input Clock enable INPUT_CLK Input Input register clock OUTPUT_ENABLE Input Output enable D_OUT_0/1 Input Data from the core D_IN_0/1 LATCH_INPUT_VALUE Output Data to the core Input Latches/holds the Input Value sysIO Buffer Each I/O is associated with a flexible buffer referred to as a sysIO buffer. These buffers are arranged around the periphery of the device in groups referred to as banks. The sysIO buffers allow users to implement a wide variety of standards that are found in today’s systems with LVCMOS interfaces. 2-14 Architecture iCE40 Ultra Family Data Sheet Typical I/O Behavior During Power-up The internal power-on-reset (POR) signal is deactivated when VCC, SPI_VCCIO1, and VPP_2V5 reach the level defined in the Power-On-Reset Voltage table in the DC and Switching Characteristics section of this data sheet. After the POR signal is deactivated, the FPGA core logic becomes active. You must ensure that all VCCIO banks are active with valid input logic levels to properly control the output logic states of all the I/O banks that are critical to the application. The default configuration of the I/O pins in a device prior to configuration is tri-stated with a weak pull-up to VCCIO. The I/O pins maintain the pre-configuration state until VCC, SPI_VCCIO1, and VPP_2V5 reach the defined levels. The I/Os take on the software user-configured settings only after POR signal is deactivated and the device performs a proper download/configuration. Unused I/Os are automatically blocked and the pull-up termination is disabled. Supported Standards The iCE40 Ultra sysIO buffer supports both single-ended input/output standards, and used as differential comparators. The buffer supports the LVCMOS 1.8, 2.5, and 3.3 V standards. The buffer has individually configurable options for bus maintenance (weak pull-up or none). Table 2-8 and Table 2-9 show the I/O standards (together with their supply and reference voltages) supported by the iCE40 Ultra devices. Differential Comparators The iCE40 Ultra devices provide differential comparator on pairs of I/O pins. These comparators are useful in some mobile applications. Please refer to the Pin Information Summary section to locate the corresponding paired I/Os with differential comparators. Table 2-8. Supported Input Standards Input Standard VCCIO (Typical) 3.3 V 2.5 V 1.8 V Single-Ended Interfaces LVCMOS33   LVCMOS25  LVCMOS18 Table 2-9. Supported Output Standards Output Standard VCCIO (Typical) Single-Ended Interfaces LVCMOS33 3.3 V LVCMOS25 2.5 V LVCMOS18 1.8 V On-Chip Oscillator The iCE40 Ultra devices feature two different frequency Oscillator. One is tailored for low-power operation that runs at low frequency (LFOSC). Both Oscillators are controlled with internally generated current. The LFOSC runs at nominal frequency of 10 kHz. The high frequency oscillator (HFOSC) runs at a nominal frequency of 48 MHz, divisible to 24 MHz, 12 MHz, or 6 MHz by user option. The LFOSC can be used to perform all always-on functions, with the lowest power possible. The HFOSC can be enabled when the always-on functions detect a condition that would need to wake up the system to perform higher frequency functions. 2-15 Architecture iCE40 Ultra Family Data Sheet User I2C IP The iCE40 Ultra devices have two I2C IP cores. Either of the two cores can be configured either as an I2C master or as an I2C slave. The pins for the I2C interface are not pre-assigned. User can use any General Purpose I/O pins. In each of the two cores, there are options to delay the either the input or the output, or both, by 50 ns nominal, using dedicated on-chip delay elements. This provides an easier interface with any external I2C components. When the IP core is configured as master, it will be able to control other devices on the I2C bus through the preassigned pin interface. When the core is configured as the slave, the device will be able to provide I/O expansion to an I2C Master. The I2C cores support the following functionality: • Master and Slave operation • 7-bit and 10-bit addressing • Multi-master arbitration support • Clock stretching • Up to 400 kHz data transfer speed • General Call support • Optionally delaying input or output data, or both For further information on the User I2C, please refer to TN1274, iCE40 SPI/I2C Hardened IP Usage Guide. User SPI IP The iCE40 Ultra devices have two SPI IP cores. The pins for the SPI interface are not pre-assigned. User can use any General Purpose I/O pins. Both SPI IP cores can be configured as a SPI master or as a slave. When the SPI IP core is configured as a master, it controls the other SPI enabled devices connected to the SPI Bus. When SPI IP core is configured as a slave, the device will be able to interface to an external SPI master. The SPI IP core supports the following functions: • Configurable Master and Slave modes • Full-Duplex data transfer • Mode fault error flag with CPU interrupt capability • Double-buffered data register • Serial clock with programmable polarity and phase • LSB First or MSB First Data Transfer For further information on the User SPI, please refer to TN1274, iCE40 SPI/I2C Hardened IP Usage Guide. High Current LED Drive I/O Pins The iCE40 Ultra family devices offer multiple high current LED drive outputs in each device in the family to allow the iCE40 Ultra product to drive LED signals directly on mobile applications. There are three outputs on each device that can sink up to 24 mA current. These outputs are open-drain outputs, and provides sinking current to an LED connecting to the positive supply. These three outputs are designed to drive the RBG LEDs, such as the service LED found in a lot of mobile devices. An embedded RGB PWM IP is also offered in the family. This RGB drive current is user programmable from 4 mA to 24 mA, in increments of 4 mA. This output functions as General Purpose I/O with open-drain when the high current LED drive is not needed. 2-16 Architecture iCE40 Ultra Family Data Sheet There is one output on each device that can sink up to 500 mA current. This output is open-drain, and provides sinking current to drive an external IR LED connecting to the positive supply. This IR drive current is user programmable from 50 mA to 500 mA in increments of 50 mA. This output functions as General Purpose I/O with opendrain when the high current LED drive is not needed. Embedded PWM IP To provide an easier usage of the RGB high current drivers to drive RGB LED, a Pulse-Width Modulator IP can be embedded into the user design. This PWM IP provides the flexibility for user to dynamically change the settings on the ON-time duration, OFF-time duration, and ability to turn the LED lights on and off gradually with user set breath-on and breath-off time. For additional information on the embedded PWM IP, please refer to TN1288, iCE40 LED Driver Usage Guide. Non-Volatile Configuration Memory All iCE40 Ultra devices provide a Non-Volatile Configuration Memory (NVCM) block which can be used to configure the device. For more information on the NVCM, please refer to TN1248, iCE40 Programming and Configuration. iCE40 Ultra Programming and Configuration This section describes the programming and configuration of the iCE40 Ultra family. Device Programming The NVCM memory can be programmed through the SPI port. The SPI port is located in Bank 1, using SPI_VCCIO1 power supply. Device Configuration There are various ways to configure the Configuration RAM (CRAM), using SPI port, including: • From a SPI Flash (Master SPI mode) • System microprocessor to drive a Serial Slave SPI port (SSPI mode) For more details on configuring the iCE40 Ultra, please see TN1248, iCE40 Programming and Configuration. Power Saving Options The iCE40 Ultra devices feature iCEGate and PLL low power mode to allow users to meet the static and dynamic power requirements of their applications. Table 2-10 describes the function of these features. Table 2-10. iCE40 Ultra Power Saving Features Description Device Subsystem Feature Description PLL When LATCHINPUTVALUE is enabled, puts the PLL into low-power mode; PLL output held static at last input clock value. iCEGate To save power, the optional iCEGate latch can selectively freeze the state of individual, non-registered inputs within an I/O bank. Registered inputs are effectively frozen by their associated clock or clock-enable control. 2-17 iCE40 Ultra Family Data Sheet DC and Switching Characteristics June 2016 Data Sheet DS1048 Absolute Maximum Ratings1, 2, 3 Supply Voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 1.42 V Output Supply Voltage VCCIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.60 V NVCM Supply Voltage VPP_2V5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.60 V PLL Supply Voltage VCCPLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 1.42 V I/O Tri-state Voltage Applied. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.60 V Dedicated Input Voltage Applied . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.60 V Storage Temperature (Ambient). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65 °C to 150 °C Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65 °C to 125 °C 1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. 2. Compliance with the Lattice Thermal Management document is required. 3. All voltages referenced to GND. Recommended Operating Conditions1 Symbol VCC1 VPP_2V5 Parameter Min. Max. Units Core Supply Voltage 1.14 1.26 V 3.46 V 3.46 V VPP_2V5 NVCM Programming and Operating Supply Voltage VCCIO1, 2, 3 I/O Driver Supply Voltage VCCPLL 4 Slave SPI Configuration 1.71 Master SPI Configuration 2.30 Configuration from NVCM 2.30 3.46 V NVCM Programming 2.30 3.00 V VCCIO_0, SPI_VCCIO1, VCCIO_2 1.71 3.46 V 1.14 1.26 V PLL Supply Voltage tJCOM Junction Temperature Commercial Operation 0 85 °C tJIND Junction Temperature Industrial Operation –40 100 °C tPROG Junction Temperature NVCM Programming 10.00 30.00 °C 1. Like power supplies must be tied together if they are at the same supply voltage and they meet the power up sequence requirement. Please refer to Power-Up Supply Sequencing section. VCC and VCCPLL are recommended to tie to same supply with an RC-based noise filter between them. Please refer to TN1252, iCE40 Hardware Checklist. 2. See recommended voltages by I/O standard in subsequent table. 3. VCCIO pins of unused I/O banks should be connected to the VCC power supply on boards. 4. VPP_2V5 can, optionally, be connected to a 1.8 V (+/-5%) power supply in Slave SPI Configuration mode subject to the condition that none of the HFOSC/LFOSC and RGB LED / IR LED driver features are used. Otherwise, VPP_2V5 must be connected to a power supply with a minimum 2.30 V level. Power Supply Ramp Rates1, 2 Symbol tRAMP Parameter Power supply ramp rates for all power supplies. Min. Max. Units 0.6 10 V/ms 1. Assumes monotonic ramp rates. 2. Power up sequence must be followed. Please refer to Power-Up Supply Sequencing section. © 2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 3-1 DS1048 DC and Switching_02.0 DC and Switching Characteristics iCE40 Ultra Family Data Sheet Power-On Reset All iCE40 Ultra devices have on-chip Power-On-Reset (POR) circuitry to ensure proper initialization of the device. Only three supply rails are monitored by the POR circuitry as follows: (1) VCC, (2) SPI_VCCIO1 and (3) VPP_2V5. All other supply pins have no effect on the power-on reset feature of the device. Note that all supply voltage pins must be connected to power supplies for normal operation (including device configuration). Power-Up Supply Sequencing It is recommended to bring up the power supplies in the following order. Note that there is no specified timing delay between the power supplies, however, there is a requirement for each supply to reach a level of 0.5V, or higher, before any subsequent power supplies in the sequence are applied. 1. VCC and VCCPLL should be the first two supplies to be applied. Note that these two supplies can be tied together subject to the recommendation to include a RC-based noise filter on the VCCPLL (Please refer to TN1252, iCE40 Hardware Checklist.) 2. SPI_VCCIO1 should be the next supply, and can be applied any time after the previous supplies (VCC and VCCPLL) have reached as level of 0.5 V or higher. 3. VPP_2V5 should be the next supply, and can be applied any time after previous supplies (VCC, VCCPLL and SPI_VCCIO1) have reached a level of 0.5 V or higher. 4. Other Supplies (VCCIO0 and VCCIO2) do not affect device power-up functionality, and they can be applied any time after the initial power supplies (VCC and VCCPLL) have reached a level of 0.5 V or greater. There is no power down sequence required. However, when partial power supplies are powered down, it is required the above sequence to be followed when these supplies are repowered up again. External Reset When all power supplies have reached to their minimum operating voltage defined in Minimum Operation Condition Table, it is required to either keep CRESET_B LOW, or toggle CRESET_B from HIGH to LOW, for a duration of tCRESET_B, and release it to go HIGH, to start configuration download from either the internal NVCM or the external Flash memory. Figure 3-1 shows Power-Up sequence when SPI_VCCIO1 and VPP_2V5 are connected separately, and the CRESET_B signal triggers configuration download. Figure 3-2 shows when SPI_VCCIO1 and VPP_2V5 connected together. All power supplies should be powered up during configuration. Before and during configuration, the I/Os are held in tri-state. I/Os are released to user functionality once the device has finished configuration. Figure 3-1. Power Up Sequence with SPI_VCCIO1 and VPP_2V5 Not Connected Together VSUPPLY(MIN) VPP_2V5, VCCIO0 and VCCIO2= 2.5 V / 3.3 V SPI_VCCIO1 = 1.8 V VCC/VCC_PLL = 1.2 V CRESET_B tCRESET_B 0.5 V 3-2 DC and Switching Characteristics iCE40 Ultra Family Data Sheet Figure 3-2. Power Up Sequence with All Supplies Connected Together SPI_VCCIO, VPP_2V5, VCCIO0 and VCCIO2= 1.8 V / 2.5 V / 3.3 V VSUPPLY(MIN) VCC/VCC_PLL = 1.2 V tCRESET_B CRESET_B 0.5 V Power-On-Reset Voltage Levels1 Symbol VPORUP VPORDN Parameter Power-On-Reset ramp-up trip point (circuit monitoring VCC, SPI_VCCIO1, VPP_2V5) Power-On-Reset ramp-down trip point (circuit monitoring VCC, SPI_VCCIO1, VPP_2V5) Min. Max. Units VCC 0.62 0.92 V SPI_VCCIO1 0.87 1.50 V VPP_2V5 0.90 1.53 V VCC — 0.79 V SPI_VCCIO1 — 1.50 V VPP_2V5 — 1.53 V 1. These POR trip points are only provided for guidance. Device operation is only characterized for power supply voltages specified under recommended operating conditions. ESD Performance Please contact Lattice Semiconductor for additional information. DC Electrical Characteristics Over Recommended Operating Conditions Symbol Parameter Min. Typ. Max. Units IIL, IIH1, 3, 4 Input or I/O Leakage 0V < VIN < VCCIO + 0.2 V — — +/–10 µA C1 I/O Capacitance, excluding LED Drivers2 VCCIO = 3.3 V, 2.5 V, 1.8 V VCC = Typ., VIO = 0 to VCCIO + 0.2 V — 6 — pF C2 Global Input Buffer Capacitance2 VCCIO = 3.3 V, 2.5 V, 1.8 V VCC = Typ., VIO = 0 to VCCIO + 0.2 V — 6 — pF C3 RGB Pin Capacitance2 VCC = Typ., VIO = 0 to 3.5 V — 15 — pF C4 IRLED Pin Capacitance2 VCC = Typ., VIO = 0 to 3.5 V — 53 — pF VHYST Input Hysteresis VCCIO = 1.8 V, 2.5 V, 3.3 V — 200 — mV –3 –8 –11 — –31 –72 –128 µA IPU Internal PIO Pull-up Current Condition VCCIO = 1.8 V, 0== 0.8 V –14 +14 % Switching Test Conditions Figure 3-3 shows the output test load used for AC testing. The specific values for resistance, capacitance, voltage, and other test conditions are shown in Table 3-1. Figure 3-3. Output Test Load, LVCMOS Standards VT R1 DUT Test Poi nt CL Table 3-1. Test Fixture Required Components, Non-Terminated Interfaces Test Condition LVCMOS settings (L -> H, H -> L) R1  CL 0 pF Timing Reference VT LVCMOS 3.3 = 1.5 V — LVCMOS 2.5 = VCCIO/2 — LVCMOS 1.8 = VCCIO/2 — LVCMOS 3.3 (Z -> H) 1.5 V VOL LVCMOS 3.3 (Z -> L) 1.5 V VOH Other LVCMOS (Z -> H) Other LVCMOS (Z -> L) 188 0 pF VCCIO/2 VOL VCCIO/2 VOH LVCMOS (H -> Z) VOH – 0.15 V VOL LVCMOS (L -> Z) VOL – 0.15 V VOH Note: Output test conditions for all other interfaces are determined by the respective standards. 3-10 iCE40 Ultra Family Data Sheet Pinout Information June 2016 Data Sheet DS1048 Signal Descriptions Signal Name Function I/O Description VCC Power — Core Power Supply VCCIO_0, SPI_VCCIO1, VCCIO_2 Power — Power for I/Os in Bank 0, 1 and 2. VPP_2V5 Power — Power for NVCM programming and operations. VCCPLL Power — Power for PLL GND GROUND — Ground GND_LED GROUND — Ground for LED drivers. Should connect to GND on board. CRESETB Configuration I Configuration Reset, active LOW. No internal pull-up resistor. Either actively driven externally or connect an 10 kOhm pull-up to VCCIO_1. CDONE Configuration I/O Configuration Done. Includes a weak pull-up resistor to SPI_VCCIO1. General I/O I/O In user mode, after configuration, this pin can be programmed as general I/O in user function. — Configuration I Configuration Reset, active LOW. No internal pull-up resistor. Either actively driven externally or connect an 10 kOhm pull-up to SPI_VCCIO1. CDONE Configuration I/O Configuration Done. Includes a weak pull-up resistor to SPI_VCCIO1. General I/O I/O In user mode, after configuration, this pin can be programmed as general I/O in user function. Configuration I/O This pin is shared with device configuration. During configuration: In Master SPI mode, this pin outputs the clock to external SPI memory. In Slave SPI mode, this pin inputs the clock from external processor. General I/O I/O In user mode, after configuration, this pin can be programmed as general I/O in user function Configuration Output This pin is shared with device configuration. During configuration: In Master SPI mode, this pin outputs the command data to external SPI memory. In Slave SPI mode, this pin connects to the MISO pin of the external processor. General I/O I/O In user mode, after configuration, this pin can be programmed as general I/O in user function. Power Supplies Configuration Config SPI Primary Secondary CRESETB PIOB_xx Config SPI Primary Secondary PIOB_34a SPI_SCK PIOB_32a SPI_SDO © 2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 4-1 DS1048 Pinout Information_01.7 Pinout Information iCE40 Ultra Family Data Sheet Signal Name PIOB_33b PIOB_35b SPI_SI SPI_SS_B Function I/O Description Configuration Input This pin is shared with device configuration. During configuration: In Master SPI mode, this pin receives data from external SPI memory. In Slave SPI mode, this pin connects to the MOSI pin of the external processor. General I/O I/O In user mode, after configuration, this pin can be programmed as general I/O in user function. Configuration I/O This pin is shared with device configuration. During configuration: In Master SPI mode, this pin outputs to the external SPI memory. In Slave SPI mode, this pin inputs from the external processor. General I/O I/O In user mode, after configuration, this pin can be programmed as general I/O in user function. General I/O I/O In user mode, after configuration, this pin can be programmed as general I/O in user function Global Input Global input used for high fanout, or clock/reset net. The G0 pin drives the GBUF0 global buffer General I/O I/O In user mode, after configuration, this pin can be programmed as general I/O in user function Global Input Global input used for high fanout, or clock/reset net. The G1 pin drives the GBUF1 global buffer General I/O I/O In user mode, after configuration, this pin can be programmed as general I/O in user function Global Input Global input used for high fanout, or clock/reset net. The G3 pin drives the GBUF3 global buffer General I/O I/O In user mode, after configuration, this pin can be programmed as general I/O in user function Global Input Global input used for high fanout, or clock/reset net. The G4 pin drives the GBUF4 global buffer General I/O I/O In user mode, after configuration, this pin can be programmed as general I/O in user function Global Input Global input used for high fanout, or clock/reset net. The G5 pin drives the GBUF5 global buffer General I/O I/O In user mode, after configuration, this pin can be programmed as general I/O in user function Global Input Global input used for high fanout, or clock/reset net. The G6 pin drives the GBUF6 global buffer Global Signals Primary PIOT_46b PIOT_45a PIOT_25b PIOT_12a PIOT_11b PIOB_3b Secondary G0 G1 G3 G4 G5 G6 LED Signals RGB0 General I/O LED RGB1 General I/O LED Open-Drain I/O In user mode, with user's choice, this pin can be programmed as open drain I/O in user function Open-Drain Output In user mode, with user's choice, this pin can be programmed as open drain 24mA output to drive external LED Open-Drain I/O In user mode, with user's choice, this pin can be programmed as open drain I/O in user function Open-Drain Output 4-2 In user mode, with user's choice, this pin can be programmed as open drain 24mA output to drive external LED Pinout Information iCE40 Ultra Family Data Sheet Signal Name RGB2 Function General I/O LED IRLED General I/O I/O Description Open-Drain I/O In user mode, with user's choice, this pin can be programmed as open drain I/O in user function Open-Drain Output In user mode, with user's choice, this pin can be programmed as open drain 24mA output to drive external LED Open-Drain I/O In user mode, with user's choice, this pin can be programmed as open drain I/O in user function LED Open-Drain Output In user mode, with user's choice, this pin can be programmed as open drain 500mA output to drive external LED PIOT_xx General I/O I/O In user mode, with user's choice, this pin can be programmed as I/O in user function in the top (xx = I/O location) PIOB_xx General I/O I/O In user mode, with user's choice, this pin can be programmed as I/O in user function in the bottom (xx = I/ O location) 4-3 Pinout Information iCE40 Ultra Family Data Sheet Pin Information Summary iCE5LP1K Pin Type General Purpose I/O Per Bank CM36 iCE5LP2K SWG36 SG481 CM36 iCE5LP4K SWG36 SG481 CM36 SWG36 SG481 Bank 0 12 5 17 12 5 17 12 5 17 Bank 1 4 15 14 4 15 14 4 15 14 10 6 8 10 6 8 10 6 8 Total General Purpose I/Os Bank 2 26 26 39 26 26 39 26 26 39 VCC 1 1 2 1 1 2 1 1 2 Bank 0 1 1 1 1 1 1 1 1 1 Bank 1 1 1 1 1 1 1 1 1 1 Bank 2 1 1 1 1 1 1 1 1 1 VCCPLL 1 1 1 1 1 1 1 1 1 VPP_2V5 1 1 1 1 1 1 1 1 1 VCCIO Dedicated Config Pins 1 1 2 1 1 2 1 1 2 GND 2 2 0 2 2 0 2 2 0 GND_LED 1 1 0 1 1 0 1 1 0 Total Balls 36 36 48 36 36 48 36 36 48 1. 48-pin QFN package (SG48) requires the package paddle to be connected to GND. 4-4 iCE40 Ultra Family Data Sheet Ordering Information June 2016 Data Sheet DS1048 iCE5LP Part Number Description iCE5LPXX-XXXXXITR Device Family iCE5LP FPGA TR TR = Tape and Reel (See quantity below) TR50 = Tape and Reel, 50 units TR1K = Tape and Reel, 1,000 units Logic Cells 1K = 1,100 Logic Cells 2K = 2,048 Logic Cells 4K = 3,520 Logic Cells Grade I = Industrial Package CM36 = 36-Ball ucfBGA (0.40 mm Ball Pitch) SWG36 = 36-Ball WLCSP (0.35 mm Ball Pitch) SG48 = 48-Pin QFN (0.50 mm Pin Pitch) All parts are shipped in tape-and-reel. Tape and Reel Quantity Package TR Quantity CM36 4,000 SWG36 5,000 SG48 2,000 © 2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 5-1 DS1048 Order Info_01.9 Ordering Information iCE40 Ultra Family Data Sheet Ordering Part Numbers Industrial LUTs Supply Voltage Package Pins Temp. iCE5LP1K-CM36ITR Part Number 1100 1.2 V Halogen-Free ucfBGA 36 IND iCE5LP1K-CM36ITR50 1100 1.2 V Halogen-Free ucfBGA 36 IND iCE5LP1K-CM36ITR1K 1100 1.2 V Halogen-Free ucfBGA 36 IND iCE5LP1K-SWG36ITR 1100 1.2 V Halogen-Free WLCSP 36 IND iCE5LP1K-SWG36ITR50 1100 1.2 V Halogen-Free WLCSP 36 IND iCE5LP1K-SWG36ITR1K 1100 1.2 V Halogen-Free WLCSP 36 IND iCE5LP1K-SG48ITR 1100 1.2 V Halogen-Free QFN 48 IND iCE5LP1K-SG48ITR50 1100 1.2 V Halogen-Free QFN 48 IND iCE5LP2K-CM36ITR 2048 1.2 V Halogen-Free ucfBGA 36 IND iCE5LP2K-CM36ITR50 2048 1.2 V Halogen-Free ucfBGA 36 IND iCE5LP2K-CM36ITR1K 2048 1.2 V Halogen-Free ucfBGA 36 IND iCE5LP2K-SWG36ITR 2048 1.2 V Halogen-Free WLCSP 36 IND iCE5LP2K-SWG36ITR50 2048 1.2 V Halogen-Free WLCSP 36 IND iCE5LP2K-SWG36ITR1K 2048 1.2 V Halogen-Free WLCSP 36 IND iCE5LP2K-SG48ITR 2048 1.2 V Halogen-Free QFN 48 IND iCE5LP2K-SG48ITR50 2048 1.2 V Halogen-Free QFN 48 IND iCE5LP4K-CM36ITR 3520 1.2 V Halogen-Free ucfBGA 36 IND iCE5LP4K-CM36ITR50 3520 1.2 V Halogen-Free ucfBGA 36 IND iCE5LP4K-CM36ITR1K 3520 1.2 V Halogen-Free ucfBGA 36 IND iCE5LP4K-SWG36ITR 3520 1.2 V Halogen-Free WLCSP 36 IND iCE5LP4K-SWG36ITR50 3520 1.2 V Halogen-Free WLCSP 36 IND iCE5LP4K-SWG36ITR1K 3520 1.2 V Halogen-Free WLCSP 36 IND iCE5LP4K-SG48ITR 3520 1.2 V Halogen-Free QFN 48 IND iCE5LP4K-SG48ITR50 3520 1.2 V Halogen-Free QFN 48 IND 5-2 iCE40 Ultra Family Data Sheet Supplemental Information October 2014 Data Sheet DS1048 For Further Information A variety of technical notes for the iCE40 Ultra family are available on the Lattice web site. • TN1248, iCE40 Programming and Configuration • TN1274, iCE40 SPI/I2C Hardened IP Usage Guide • TN1276, Advanced iCE40 SPI/I2C Hardened IP Usage Guide • TN1250, Memory Usage Guide for iCE40 Devices • TN1251, iCE40 sysCLOCK PLL Design and Usage Guide • TN1252, iCE40 Hardware Checklist • TN1288, iCE40 LED Driver Usage Guide • TN1295, DSP Function Usage Guide for iCE40 Devices • TN1296, iCE40 Oscillator Usage Guide • iCE40 Ultra Pinout Files • iCE40 Ultra Pin Migration Files • Thermal Management document • Lattice design tools • Schematic Symbols © 2014 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 6-1 DS1048 Further Info_01.4 iCE40 Ultra Family Data Sheet Revision History June 2016 Data Sheet DS1048 Date Version Section Change Summary June 2016 2.0 Introduction Updated General Description section. Changed “high current driver” to “high current IR driver”. Updated Features section. In Table 1-1, iCE40 Ultra Family Selection Guide, corrected HF Oscillator (48 kHz) to (48 MHz). Architecture Updated Architecture Overview section. — Changed content to “The Programmable Logic Blocks (PLB) and sysMEM EBR blocks, are arranged in a two-dimensional grid with rows and columns. Each column has either PLB or EBR blocks." — Changed “high current LED sink” to "high current RGB and IR LED sinks". Updated sysCLOCK Phase Locked Loops (PLLs) section. Corrected VCCPLL character format in Figure 2-3, PLL Diagram. Updated sysMEM Embedded Block RAM Memory section. Updated footnote in Table 2-4, sysMEM Block Configurations. Updated sysIO Buffer Banks section. — Changed statement to “The configuration SPI interface signals are powered by SPI_VCCIO1.” — Corrected VCCIO character format in Figure 2-8, I/O Bank and Programmable I/O Cell. Updated Typical I/O Behavior During Power-up section. Modified text content. Updated Supported Standards section. Changed statement to “The iCE40 Ultra sysIO buffer supports both single-ended input/output standards, and used as differential comparators.” Updated On-Chip Oscillator section. Changed statement to “The high frequency oscillator (HFOSC) runs at a nominal frequency of 48 MHz, divisible to 24 MHz, 12 MHz, or 6 MHz by user option.” Updated section heading to High Current LED Drive I/O Pins. Changed “high current drive” to “high current LED drive”. Removed Power On Reset section. DC and Switching Characteristics Updated Absolute Maximum Ratings section. — Corrected symbol character format. Updated Recommended Operating Conditions section. — Corrected symbol character format. — Revised footnote 1. — Added footnote 4. Updated Power Supply Ramp Rates section. Changed tRAMP Max. value. Added Power-On Reset section. Updated section heading to Power-Up Supply Sequencing. Revised text content. Added External Reset section. Updated DC Electrical Characteristics section. Revised footnote 4. © 2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 7-1 DS1048 Revision History Revision History iCE40 Ultra Family Data Sheet Date Version Section Change Summary Updated Supply Current section. — Corrected IPP2V5STDBY parameter. — Added Typ. VCC = 1.2 V values for ICCPEAK, IPP_2V5PEAK, ISPI_VCCIO1PEAK, and ICCIOPEAK. — Added footnote 5. — Corrected SPI_VCCIO1 character format. Updated User SPI Specifications section. Removed parameters and added footnotes. Updated Internal Oscillators (HFOSC, LFOSC) section. Added Commercial and Industrial Temp values for DCHCLKHF. Updated sysIO Single-Ended DC Electrical Characteristics section. Removed footnote. Updated Register-to-Register Performance section. Modified footnotes. Updated iCE40 Ultra External Switching Characteristics section. Modified footnote. Updated sysCLOCK PLL Timing section. Reversed tOPJIT conditions. Updated sysCONFIG Port Timing Specifications section. — Modified tCR_SCK Min. value. — Added footnote 4 to tSU parameter. — Modified tSU Min. value. — Modified tHD parameter. Updated section heading to RGB LED and IR LED Drive. Modified ILED_ACCURACY and IIR_ACCURACY parameters, Min. and Max. values. Pinout Information Updated Signal Descriptions section. Changed VCCIO_1 to SPI_VCCIO1 in the CDONE, CRESETB and PIOB_xx descriptions. Updated Pin Information Summary section. — Corrected symbol character format. — Corrected VCPP_2V5 to VPP_2V5. 1.9 Introduction Updated Features section. Updated BGA package to ucfBGA. DC and Switching Characteristics Updated Differential Comparator Electrical Characteristics section. Corrected typo in VREF Max. value. Pinout Information Updated Signal Descriptions section. — Changed PIOB_12a to PIOB_xx — Changed SPI_CSN to SPI_SS_B and revised description when in Slave SPI mode. — Corrected minor typo errors. Updated Pin Information Summary section. Added footnote to SG48. Ordering Information Updated iCE5LP Part Number Description section. Updated BGA package to ucfBGA. Updated Ordering Part Numbers section. Updated BGA package to ucfBGA. June 2015 1.8 DC and Switching Characteristics Ordering Information Updated Internal Oscillators (HFOSC, LFOSC) section. Removed decimals. Updated iCE5LP Part Number Description section. — Added TR items. — Corrected formatting errors. Updated Ordering Part Numbers section. Updated CM36 and SG48 packages. 7-2 Revision History iCE40 Ultra Family Data Sheet Date Version Section April 2015 1.7 Architecture Ordering Information Change Summary Updated sysDSP section. Revised the following figures: — Figure 2-5, sysDSP Functional Block Diagram  (16-bit x 16-bit Multiply-Accumulate) — Figure 2-6, sysDSP 8-bit x 8-bit Multiplier — Figure 2-7, DSP 16-bit x 16-bit Multiplier Updated iCE5LP Part Number Description section. Added TR items. Updated Ordering Part Numbers section. Added CM36, SW36 and SG48 part numbers. March 2015 1.6 Introduction DC and Switching Characteristics Updated Features section. — Added BGA and QFN packages in Flexible Logic Architecture. — Added USB 3.1 Type C Cable Detect / Power Delivery Applications in Applications. — Updated Table 1-1, iCE40 Ultra Family Selection Guide. Added 36ball ucfBGA and 48-ball QFN packages. Changed subheading to Total User I/O Count. Changed RBW IP to PWM IP. Deleted footnotes. Updated Power-up Sequence section. Indicated all devices in second paragraph. Updated sysIO Single-Ended DC Electrical Characteristics section. Changed LVCMOS 3.3 and LVCMOS 2. 5 VOH Min. (V) from 0.5 to 0.4. Replaced the Differential Comparator Electrical Characteristics table. Pinout Information Updated Pin Information Summary section. — Added CM36 and SG48 values. — Changed CRESET_B to Dedicated Config Pins. Ordering Information Updated iCE5LP Part Number Description section. — Added CM36 and SG48 package. — Added TR items. Updated Ordering Part Numbers section. Added CM36, SW36 and SG48 part numbers. October 2014 1.5 Introduction Updated Features section. — Removed 26 I/O pins for 36-pin WLCSP under Flexible Logic Architecture. — Changed form factor to 2.078 mm x 2.078 mm. — Updated Table 1-1, iCE40 Ultra Family Selection Guide. Removed 20-Ball WLCSP. Updated Introduction section. Changed form factor to 2.078 mm x 2.078 mm. Architecture DC and Switching Characteristics Updated sysCLOCK Phase Locked Loops (PLLs) section. Removed note in heading regarding sysCLOCK PLL support. Updated Recommended Operating Conditions section. Removed footnote on sysCLOCK PLL support. Updated Power-up Sequence section. Removed information on 20-pin WLCSP. Pinout Information Updated Signal Descriptions section. Removed references 20-pin WLCSP. Updated Pin Information Summary section. Removed references to UWG20 values. Ordering Information Updated iCE5LP Part Number Description section. Removed 20-ball WLCSP. Updated Ordering Part Numbers section. Removed UWG20 part numbers. Further Information Added technical note references. 7-3 Revision History iCE40 Ultra Family Data Sheet Date Version Section August 2014 1.4 All Introduction Change Summary Removed Preliminary document status. Updated General Description section. Added information on high current driver. Updated Features section. — Changed standby current typical to as low as 71 µA. — Changed feature to Embedded Memory. — Updated Table 1-1, iCE40 Ultra Family Selection Guide. Added NVCM and Embedded PWM IP rows. Added (MULT16 with 32-bit Accumulator) to DSP Block. Added Total I/O (Dedicated I/O) Count data. General update to Introduction section. Architecture Updated Architecture Overview section. — Revised and added information on sysIO banks. — Updated reference for embedded PWM IP. Updated iCE40 Ultra Programming and Configuration section. — Changed SPI1 to SPI. — Changed VCCIO_1 to SPI_VCCIO1. DC and Switching Characteristics Updated Absolute Maximum Ratings section. Changed PLL Supply Voltage VCCPLL value. Updated Recommended Operating Conditions section. Added footnote to VCCPLL. Updated Power-up Sequence section. General update. Updated Power-On-Reset Voltage Levels section. Changed the VPORUP VCC Max.value. Updated DC Electrical Characteristics section. Added C3 and C4 information. Updated Supply Current section. — Completed Typ. VCC =1.2 V4 data. — Changed symbols to ISPI_VCCIO1STDBY and ISPI_VCCIO1PEAK. — Added information to footnote 3. Updated Internal Oscillators (HFOSC, LFOSC) section. General update. Updated iCE40 Ultra External Switching Characteristics section. Added Max. value for tCOPLL. Added Min. values for tSUPLL and tHPLL. Updated sysCLOCK PLL Timing section. Added Max. value for tOPJIT. Updated sysCONFIG Port Timing Specifications section. — Added TSU and THD information. — Added footnote 3 to Master SPI. Updated High Current LED and IR LED Drive section. Updated Min. value. July 2014 1.3 All Introduction DC and Switching Characteristics Changed document status from Advance to Preliminary. Updated Features section. Adjusted Ultra-low Power Devices standby current. Updated AC/DC specifications numbers. 7-4 Revision History iCE40 Ultra Family Data Sheet Date Version Section June 2014 1.2 All Introduction Change Summary Product name changed to iCE40 Ultra. Updated Table 1-1, iCE40 Ultra Family Selection Guide. Removed 30ball WLCSP. DC and Switching Characteristics Updated values in the following sections: — Supply Current — Internal Oscillators (HFOSC, LFOSC) — Power Supply Ramp Rates — Power-On-Reset Voltage Levels — SPI Master or NVCM Configuration Time Pinout Information Updated Signal Descriptions section. Removed 30-pin WLCSP. Indicated TBD for values to be determined. Updated Pin Information Summary section. Removed SWG30 values. Ordering Information Updated iCE5LP Part Number Description section. Removed 30-ball WLCSP. Updated Ordering Part Numbers section. Removed SWG30 and UWG30 part numbers. May 2014 01.1 Introduction Updated General Description, Features, and Introduction sections. Removed hardened RGB PWM IP information. Architecture Updated Architecture Overview section. Removed the RGB IP block in Figure 2-1, iCE5LP-4K Device, Top View, Figure 2-8, I/O Bank and Programmable I/O, and in the text content. Updated High Current Drive I/O Pins section. Removed hardened RGB PWM IP information. Updated Power On Reset section. Removed content on Vccio_2 power down option. Replaced RGB PWM Block section with Embedded PWM IP section. DC and Switching Characteristics April 2014 01.0 All Removed RGB PWM Block Timing section. Initial release. 7-5