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ICE65L04F-TCS63I

ICE65L04F-TCS63I

  • 厂商:

    LATTICE(莱迪思半导体)

  • 封装:

    -

  • 描述:

    IC FPGA 48 I/O 63WLCSP

  • 详情介绍
  • 数据手册
  • 价格&库存
ICE65L04F-TCS63I 数据手册
iCE65™ Ultra Low-Power mobileFPGA™ Family March 30, 2012 (2.42) Data Sheet  First high-density, ultra low-power Figure 1: iCE65 Family Architectural Features single-chip, SRAM mobileFPGA family specifically designed for hand-held applications and long battery life  12 µA in static mode  Two power/speed options –L: Low Power –T: High speed 12 µA at f =0 kHz (Typical) I/O Bank 0 CMOS technology  Low leakage, µW static power  Lower core voltage, lowest dynamic power SPI Config Carry logic Four-input Look-Up Table (LUT4) Nonvolatile Configuration Memory (NVCM) Flip-flop with enable and reset controls  Plentiful, fast, on-chip 4Kbit RAM blocks  Low-cost, space-efficient packaging options  Flexible programmable logic and programmable interconnect fabric  Over 7,600 look-up tables (LUT4) and flip-flops  Low-power logic and interconnect  Known-good die (KGD) options available  Complete iCEcube™ development system  Flexible I/O pins to simplify system interfaces  Up to 222 programmable I/O pins  Four independently-powered I/O banks; support for 3.3V, 2.5V, 1.8V, and 1.5V voltage standards  LVCMOS, MDDR, LVDS, and SubLVDS I/O standards      Windows® and Linux® support VHDL and Verilog logic synthesis Place and route software Design and IP core libraries Low-cost iCEman65 development board Table 1: iCE65 Ultra Low-Power Programmable Logic Family Summary iCE65L01 iCE65L04 Logic Cells (LUT + Flip-Flop) RAM4K Memory Blocks RAM4K RAM bits Configuration bits (maximum) Typical Current at 0 kHz, 1.0 V Maximum Programmable I/O Pins Maximum Differential Input Pairs 8 Logic Cells = Programmable Logic Block I/O Bank 1 PLB PLB PLB PLB PLB PLB I/O Bank 2 Programmable Interconnect PLB PLB PLB PLB PLB PLB PLB PLB PLB PLB PLB PLB PLB PLB PLB PLB PLB PLB 4Kbit RAM Programmable Interconnect JTAG NVCM 4Kbit RAM PLB PLB PLB PLB PLB PLB PLB PLB I/O Bank 3 sources and methods  Processor-like mode self-configures from external, commodity SPI serial Flash PROM  Downloaded by processor using SPI-like serial interface in as little as 20 µs  In-system programmable, ASIC-like mode loads from secure, internal Nonvolatile Configuration Memory (NVCM)  Ideal for volume production  Superior design and intellectual property protection; no exposed data Programmable Interconnect Programmable Interconnect  Up to 256 MHz internal performance  Reprogrammable from a variety of  Proven, high-volume 65 nm, low-power Programmable Logic Block (PLB) 1,280 16 64K 245 Kb 12 µA 95 0 © 2007-2012 by Lattice Semiconductor Corporation. All rights reserved. www.latticesemi.com 3,520 20 80K 533 Kb 26 µA 176 20 iCE65L08 7,680 32 128K 1,057 Kb 54 µA 222 25 (2.42, 30-MAR-2012) 1 iCE65 Ultra Low-Power mobileFPGA™ Family Overview The Lattice Semiconductor iCE65 programmable logic family is specifically designed to deliver the lowest static and dynamic power consumption of any comparable CPLD or FPGA device. iCE65 devices are designed for costsensitive, high-volume applications and provide on-chip, nonvolatile configuration memory (NVCM) to customize for a specific application. iCE65 devices can self-configure from a configuration image stored in an external commodity SPI serial Flash PROM or be downloaded from an external processor over an SPI-like serial port. The three iCE65 components, highlighted in Table 1, deliver from approximately 1K to nearly 8K logic cells and flipflops while consuming a fraction of the power of comparable programmable logic devices. Each iCE65 device includes between 16 to 32 RAM blocks, each with 4Kbits of storage, for on-chip data storage and data buffering. As pictured in Figure 1, each iCE65 device consists of four primary architectural elements.  An array of Programmable Logic Blocks (PLBs)  Each PLB contains eight Logic Cells (LCs); each Logic Cell consists of …  A fast, four-input look-up table (LUT4) capable of implementing any combinational logic function of up to four inputs, regardless of complexity  A ‘D’-type flip-flop with an optional clock-enable and set/reset control  Fast carry logic to accelerate arithmetic functions such as adders, subtracters, comparators, and counters.  Common clock input with polarity control, clock-enable input, and optional set/reset control input to the PLB is shared among all eight Logic Cells  Two-port, 4Kbit RAM blocks (RAM4K)  256x16 default configuration; selectable data width using programmable logic resources  Simultaneous read and write access; ideal for FIFO memory and data buffering applications  RAM contents pre-loadable during configuration  Four I/O banks with independent supply voltage, each with multiple Programmable Input/Output (PIO) blocks  LVCMOS I/O standards and LVDS outputs supported in all banks  I/O Bank 3 supports additional SSTL, MDDR, LVDS, and SubLVDS I/O standards  Programmable interconnections between the blocks  Flexible connections between all programmable logic functions  Eight dedicated low-skew, high-fanout clock distribution networks (2.42, 30-MAR-2012) 2 Lattice Semiconductor Corporation www.latticesemi.com Packaging Options iCE65 components are available in a variety of package options to support specific application requirements. The available options, including the number of available user-programmable I/O pins (PIOs), are listed in Table 2. Fullytested Known-Good Die (KGD) DiePlus™ are available for die stacking and highly space-conscious applications. All iCE65 devices are provided exclusively in Pb-free, RoHS-compliant packages. Table 2: iCE65 Family Packaging Options, Maximum I/O per Package Package Ball/Lead Body Package Pitch Package 65L01 (mm) Code (mm) 81-ball chip-scale BGA 5x5 CB81 0.5 63 (0) 84-pin quad flat no-lead package 7x7 QN84 0.5 67 (0) 100-pin very thin quad flat package 14 x 14 VQ100 0.5 72 (0) 121-ball chip-scale BGA 6x6 CB121 92 (0) 132-ball chip-scale BGA 8x8 CB132 93 (0) 0.5 196-ball chip-scale BGA 8x8 CB196 — 284-ball chip-scale BGA 12 x 12 CB284 — See DiePlus Known Good Die DI — 95 (0) data sheet = Common footprint allows each density migration on the same printed circuit board. (Differential 65L04 65L08 — — 72 (9) — 95 (11) 150 (18) 176 (20) — — — — 95 (12) 150 (18) 222 (25) 176 (20) 222 (25) input count). The iCE65L04 and the iCE65L08 are both available in the CB196 package and have similar footprints but are not completely pin compatible. See “Pinout Differences between iCE65L04 and iCE65L08 in CB196 Package” on page 73 for more information. When iCE65 components are supplied in the same package style, devices of different gate densities share a common footprint. The common footprint improves manufacturing flexibility. Different models of the same product can share a common circuit board. Feature-rich versions of the end application mount a larger iCE65 device on the circuit board. Low-end versions mount a smaller iCE65 device. Lattice Semiconductor Corporation www.latticesemi.com (2.42, 30-MAR-2011) 3 iCE65 Ultra Low-Power mobileFPGA™ Family Ordering Information Figure 2 describes the iCE65 ordering codes for all packaged, non-NVCM Programed components. See the separate DiePlus data sheets when ordering die-based products. Figure 2: iCE65 Ordering Codes Standard Device iCE65L 04 F -L CB 132 C Logic Cells (x1,000) Temperature Range C = Commercial 04, 01, 04,0808 (TAJ = 0° to 70° Celsius) Configuration Memory I = Industrial (TAJ = –40° to 85° Celsius) F = NVCM + reprogrammable Package Leads Power Consumption/ Speed -L = Low power -T = High speed Package Style CB = chip-scale ball grid CS = wafer level chip-scale package (0.4 mm pitch) VQ = very-thin quad flat pack package QN = quad flat no-lead package iCE65 devices offer two power consumption, speed options. Standard products (“-L” ordering code) have low standby and dynamic power consumption. The “-T” provides higher-speed logic. Similarly, iCE65 devices are available in two operating temperature ranges, one for typical commercial applications, the other with an extended temperature range for industrial and telecommunications applications. The ordering code also specifies the device package option, as described further in Table 2. Figure 3 describes the iCE65 ordering codes for all packaged, NVCM Programmed components. Figure 3: iCE65 Ordering Codes NVCM Programmed Device iCE65L 01 F – ZZZ ZZZZ Logic Cells (x1000) NVCM Program Code Revision 01, 04, 08 Configuration Memory Customer Program Code F = NVCM + reprogrammable (2.42, 30-MAR-2012) 4 Lattice Semiconductor Corporation www.latticesemi.com Programmable Logic Block (PLB) Generally, a logic design for an iCE65 component is created using a high-level hardware description language such as Verilog or VHDL. The Lattice Semiconductor development software then synthesizes the high-level description into equivalent functions built using the programmable logic resources within each iCE65 device. Both sequential and combinational functions are constructed from an array of Programmable Logic Blocks (PLBs). Each PLB contains eight Logic Cells (LCs), as pictured in Figure 4, and share common control inputs, such as clocks, reset, and enable controls. PLBs are connected to one another and other logic functions using the rich Programmable Interconnect resources. Logic Cell (LC) Each iCE65 device contains thousands of Logic Cells (LCs), as listed in Table 1. Each Logic Cell includes three primary logic elements, shown in Figure 4.  A four-input Look-Up Table (LUT4) builds any combinational logic function, of any complexity, of up to four inputs. Similarly, the LUT4 element behaves as a 16x1 Read-Only Memory (ROM). Combine and cascade multiple LUT4s to create wider logic functions. Figure 4: Programmable Logic Block and Logic Cell  A ‘D’-style Flip-Flop (DFF), with an optional clock-enable and reset control input, builds sequential logic functions. Each DFF also connects to a global reset signal that is automatically asserted immediately following device configuration.  Carry Logic boosts the logic efficiency and performance of arithmetic functions, including adders, subtracters, comparators, binary counters and some wide, cascaded logic functions. The output from a Logic Cell is available to all inputs to all eight Logic Cells within the Programmable Logic Block. Similarly, the Logic Cell output feeds into fabric to connect to other features on the iCE65 device. Shared Block-Level Controls Clock Programmable Logic Block (PLB) Enable Set/Reset 1 0 Logic Cell 8 Logic Cells (LCs) Carry Logic I0 I1 I2 I3 LUT4 Four-input Look-Up Table (LUT4) DFF D Q EN SR O Flip-flop with optional enable and set or reset controls = Statically defined by configuration program Lattice Semiconductor Corporation www.latticesemi.com (2.42, 30-MAR-2011) 5 iCE65 Ultra Low-Power mobileFPGA™ Family Look-Up Table (LUT4) The four-input Look-Up Table (LUT4) function implements any and all combinational logic functions, regardless of complexity, of between zero and four inputs. Zero-input functions include “High” (1) and “Low” (0). The LUT4 function has four inputs, labeled I0, I1, I2, and I3. Three of the four inputs are shared with the Carry Logic function, as shown in Figure 4. The bottom-most LUT4 input connects either to the I3 input or to the Carry Logic output from the previous Logic Cell. The output from the LUT4 function connects to the flip-flop within the same Logic Cell. The LUT4 output or the flip-flop output then connects to the programmable interconnect. For detailed LUT4 internal timing, see Table 54. ‘D’-style Flip-Flop (DFF) The ‘D’-style flip-flop (DFF) optionally stores state information for the application. The flip-flop has a data input, ‘D’, and a data output, ‘Q’. Additionally, each flip-flop has up to three control signals that are shared among all flip-flops in all Logic Cells within the PLB, as shown in Figure 4. Table 3 describes the behavior of the flip-flop based on inputs and upon the specific DFF design primitive used or synthesized. Table 3: ‘D’-Style Flip-Flop Behavior DFF Primitive All SB_DFFR Operation Cleared Immediately after Configuration Hold Present Value (Disabled) Hold Present Value (Static Clock) Load with Input Data Asynchronous Reset Inputs EN SR CLK Output Q X X 0 0 X X Q X X X 1 or 0 Q D X 1* X 0* 1 ↑ X D 0 1 X 1 1 ↑ 0 1 ↑ 1 Flip-Flop Mode D X X X X Asynchronous Reset SB_DFFS Asynchronous Set Asynchronous X X Set SB_DFFSR Synchronous Reset Synchronous X 1* Reset SB_DFFSS Synchronous Set Synchronous X 1* Set X = don’t care, ↑ = rising clock edge (default polarity), 1* = High or unused, 0* = Low or unused The CLK clock signal is not optional and is shared among all flip-flops in a Programmable Logic Block. By default, flip-flops are clocked by the rising edge of the PLB clock input, although the clock polarity can be inverted for all the flip-flops in the PLB. The CLK input optionally connects to one of the following clock sources.  The output from any one of the eight Global Buffers, or  A connection from the general-purpose interconnect fabric The EN clock-enable signal is common to all Logic Cells in a Programmable Logic Block. If the enable signal is not used, then the flip-flop is always enabled. This condition is indicated as “1*” in Table 3. The asterisk indicates that this is the default state if the control signal is not connected in the application. Similarly, the SR set/reset signal is common to all Logic Cells in a Programmable Logic Block. If not used, then the flip-flop is never set/reset, except when cleared immediately after configuration or by the Global Reset signal. This condition is indicated as “0*” in Table 3. The asterisk indicates that this is the default state if the control signal is not connected in the application. (2.42, 30-MAR-2012) 6 Lattice Semiconductor Corporation www.latticesemi.com Each flip-flop has an additional control that defines its set or reset behavior. As defined in the configuration image, the control defines whether the set or reset operation is synchronized to the active CLK clock edge or whether it is completely asynchronous.  The SB_DFFR and SB_DFFS primitives are asynchronously controlled, solely by the SR input. If the SR input is High, then an SB_DFFR primitive is asynchronously reset and an SB_DFFS primitive is asynchronously set.  The SB_DFFSR and SB_DFFRSS primitives are synchronously controlled by both the SR input and the clock input. If the SR input is High at a rising edge of the clock input, then an SB_DFFSR primitive is synchronously reset and an SB_DFFSS primitive is synchronously set. The LUT4 output or the flip-flop output then connects to the programmable interconnect. Because of the shared control signals, the design software can pack flip-flops with common control inputs into a single PLB block, as described by Table 4. There are eight total packing options. Table 4: Flip-flop Packing/Sharing within a PLB Group Active Clock Edge 1 2 3 4 5 6 7 8         Clock Enable Set or Reset Control (Sync. or Async) None None (always enabled) PLB set/reset control Selective (controlled by PLB clock enable) None PLB set/reset control For detailed flip-flop internal timing, see Table 54. Carry Logic The dedicated Carry Logic within each Logic Cell primarily accelerates and improves the efficiency of arithmetic logic such as adders, accumulators, subtracters, incrementers, decrementers, counters, ALUs, and comparators. The Carry Logic also supports wide combinational logic functions. COUT = I1 ● I2 + CIN ●I1 + CIN ● I2 [Equation 1] Equation 1 and Figure 5 describe the Carry Logic structure within a Logic Cell. The Carry Logic shares inputs with the associated Look-Up Table (LUT4). The LUT4’s I1 and I2 inputs directly feed the Carry Logic; inputs I0 and I3 do not. A signal cascades between Logic Cells within the Programmable Logic Block. The carry input from the previous adjacent Logic Cell optionally provides an alternate input to the LUT4 function, supplanting the I3 input. Low-Power Disable To save power and prevent unnecessary signal switching, the Carry Logic function within a Logic Cell is disabled if not used. The output of a Logic Cell’s Carry Logic is forced High. PLB Carry Input and Carry Output Connections As shown in Figure 5, each Programmable Logic Block has a carry input signal that can be initialized High, Low, or come from the carry output signal from PLB immediately below. Similarly, the Carry Logic output from the Programmable Logic Block connects to the PLB immediately above, which allows the Carry Logic to span across multiple PLBs in a column. As shown in Figure 6, the Carry Logic chain can be tapped mid-way through a chain or a PLB by feeding the value through a LUT4 function. Adder Example Figure 6 shows an example design that uses the Carry Logic. The example is a 2-bit adder, which can be expanded into an adder of arbitrary size. The LUT4 function within a Logic Cell is programmed to calculate the sum of the two input values and the carry input, A[i] + B[i] + CARRY_IN[i-1] = SUM[i]. Lattice Semiconductor Corporation www.latticesemi.com (2.42, 30-MAR-2011) 7 iCE65 Ultra Low-Power mobileFPGA™ Family The Carry Logic generates the carry value to feed the next bit in the adder. The calculated carry value replaces the I3 input to the next LUT4 in the upper Logic Cell. If required by the application, the carry output from the final stage of the adder is available by passing it through the final LUT4. Figure 5: Carry Logic Structure within a Logic Cell and between PLBs Adjacent PLB To upper adjacent Logic Cell Carry Logic I0 I1 LUT4 I2 I3 From lower adjacent Logic Cell 0 Carry Logic initialization into Programmable Logic 1 Block (PLB) Adjacent PLB = Statically defined by configuration program (2.42, 30-MAR-2012) 8 Lattice Semiconductor Corporation www.latticesemi.com Implementing Subtracters, Decrementers As mentioned earlier, the Carry Logic generates a High output whenever the sum of I1 + I2 + CARRY_IN generates a carry. The Carry Logic does not specifically have a subtract mode. To implement a subtract function or decrement function, logically invert either the I1 or I2 input and invert the initial carry input. This performs a 2s complement subtract operation. Figure 6: Two-bit Adder Example LUT4 I0 GND I1 GND I2 I3 CARRY_OUT Carry Logic LUT4 I0 A[1] I1 B[1] I2 I3 SUM[1] Carry Logic LUT4 I0 A[0] I1 B[0] I2 I3 SUM[0] CARRY_IN Lattice Semiconductor Corporation www.latticesemi.com (2.42, 30-MAR-2011) 9 iCE65 Ultra Low-Power mobileFPGA™ Family Programmable Input/Output Block (PIO) Programmable Input/Output (PIO) blocks surround the periphery of the device and connect external components to the Programmable Logic Blocks (PLBs) and RAM4K blocks via programmable interconnect. Individual PIO pins are grouped into one of four I/O banks, as shown in Figure 7. I/O Bank 3 has additional capabilities, including LVDS differential I/O and the ability to interface to Mobile DDR memories. Figure 7 also shows the logic within a PIO pin. When used in an application, a PIO pin becomes a signal input, an output, or a bidirectional I/O pin with a separate direction control input. Figure 7: Programmable Input/Output (PIO) Pin VCCIO I/O Bank 0, 1, or 2 Voltage Supply 0 = Hi-Z 1 = Output Enabled Enabled ‘1’ Disabled ‘0’ VCC Internal Core OE VCCIO_0 1.5V to 3.3V Pull-up not in I/O Bank 3 Pull-up Enable I/O Bank 0 I/O Bank 1 General-Purpose I/O I/O Bank 3 I/O Bank 2 General-Purpose I/O VCCIO_2 OUT VCCIO_1 PIO Special/LVDS I/O VCCIO_3 1.5 to 3.3V General-Purpose I/O PAD iCEGATE HOLD Latch inhibits switching for lowest power HD IN GBIN pins optionally connect directly to an associated GBUF global buffer SPI Config Programmable Input/Output SPI_VCC = Statically defined by configuration program I/O Banks PIO blocks are organized into four separate I/O banks, each with its own voltage supply input, as shown in Table 5. The voltage applied to the VCCIO pin on a bank defines the I/O standard used within the bank. Table 50 and Table 51 describe the I/O drive capabilities and switching thresholds by I/O standard. On iCE65L04 and iCE65L08 devices, I/O Bank 3, along the left edge of the die, is different than the others and supports specialized I/O standards. I/O Bank Voltage Supply Inputs Support Different I/O Standards Because each I/O bank has its own voltage supply, iCE65 components become the ideal bridging device between different interface standards. For example, the iCE65 device allows a 1.8V-only processor to interface cleanly with a 3.3V bus interface. The iCE65 device replaces external voltage translators. Bank 0 1 2 3 Device Edge Top Right Bottom Left SPI Bottom Right (2.42, 30-MAR-2012) 10 Table 5: Supported Voltages by I/O Bank Supply Input 3.3V 2.5V VCCIO_0 Yes Yes VCCIO_1 Yes Yes VCCIO_2 Yes Yes VCCIO_3 Yes Yes SPI_VCC Yes Yes 1.8V Yes Yes Yes Yes Yes 1.5V Outputs only Outputs only Outputs only iCE65L01: Outputs only iCE65L04/08: Yes No Lattice Semiconductor Corporation www.latticesemi.com If not connected to an external SPI PROM, the four pins associated with the SPI Master Configuration Interface can be used as PIO pins, supplied by the SPI_VCC input, essentially forming a fifth “mini” I/O bank. If using an SPI Flash PROM, then connect SPI_VCC to 3.3V. I/O Banks 0, 1, 2, SPI and Bank 3 of iCE65L01 Table 6 highlights the available I/O standards when using an iCE65 device, indicating the drive current options, and in which bank(s) the standard is supported. I/O Banks 0, 1, 2 and SPI interface support the same standards. I/O Bank 3 has additional capabilities in iCE65L04 and iCE65L08, including support for MDDR memory standards and LVDS differential I/O. Table 6: I/O Standards for I/O Banks 0, 1, 2, SPI Interface Bank, and Bank 3 of iCE65L01 I/O Standard Supply Voltage Drive Current (mA) Attribute Name 5V Input Tolerance LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 outputs 3.3V 3.3V 2.5V 1.8V 1.5V N/A ±11 ±8 ±5 ±4 N/A SB_LVCMOS IBIS Models for I/O Banks 0, 1, 2 and the SPI Bank The IBIS (I/O Buffer Information Specification) file that describes the output buffers used in I/O Banks 0, 1, 2, SPI Bank and Bank 3 of iCE65L01 is available from the following link.  IBIS Models for I/O Banks 0, 1, 2, SPI Bank and Bank 3 of iCE65L01 I/O Bank 3 of iCE65L04 and iCE65L08 I/O Bank 3, located along the left edge of the die, has additional special I/O capabilities to support memory components and differential I/O signaling (LVDS). Table 7 lists the various I/O standards supported by I/O Bank 3. The SSTL2 and SSTL18 I/O standards require the VREF voltage reference input pin which is only available on the CB284 package. Also see Table 51 for electrical characteristics. Table 7: I/O Standards for I/O Bank 3 Only of iCE65L04 and iCE65L08 Supply VREF Pin (CB284 or Target I/O Standard Voltage DiePlus) Required? Drive Current (mA) Attribute Name LVCMOS33 LVCMOS25 3.3V No ±8 SB_LVCMOS33_8 No ±16 ±12 ±8 ±4 SB_LVCMOS25_16 SB_LVCMOS25_12 SB_LVCMOS25_8 SB_LVCMOS25_4 No ±10 ±8 ±4 ±2 SB_LVCMOS18_10 SB_LVCMOS18_8 SB_LVCMOS18_4 SB_LVCMOS18_2 No ±4 ±2 SB_LVCMOS15_4 SB_LVCMOS15_2 Yes ±16.2 ±8.1 SB_SSTL2_CLASS_2 SB_SSTL2_CLASS_1 Yes ±13.4 ±6.7 SB_SSTL18_FULL SB_SSTL18_HALF No ±10 ±8 ±4 ±2 SB_MDDR10 SB_MDDR8 SB_MDDR4 SB_MDDR2 No N/A SB_LVDS_INPUT 2.5V LVCMOS18 1.8V LVCMOS15 1.5V SSTL2_II SSTL2_I 2.5V SSTL18_II SSTL18_I 1.8V MDDR 1.8V LVDS 2.5V Lattice Semiconductor Corporation www.latticesemi.com (2.42, 30-MAR-2011) 11 iCE65 Ultra Low-Power mobileFPGA™ Family Table 8 lists the I/O standards that can co-exist in I/O Bank 3, depending on the VCCIO_3 voltage. Table 8: Compatible I/O Standards in I/O Bank 3 of iCE65L04 and iCE65L08 VCCIO_3 Voltage 3.3V 2.5V 1.8V 1.5V SB_LVCMOS33_8 Any SB_LVCMOS25 Any SB_LVCMOS18 Any SB_LVCMOS15 Compatible I/O SB_SSTL2_Class_2 SB_SSTL18_FULL Standards SB_SSTL2_Class_1 SB_LVDS_INPUT SB_SSTL18_HALF SB_MDDR10 SB_MDDR8 SB_MDDR4 SB_MDDR2 SB_LVDS_INPUT Programmable Output Drive Strength Each PIO in I/O Bank 3 offers programmable output drive strength, as listed in Table 8. For the LVCMOS and MDDR I/O standards, the output driver has settings for static drive currents ranging from 2 mA to 16 mA output drive current, depending on the I/O standard and supply voltage. The SSTL18 and SSTL2 I/O standards offer full- and half-strength drive current options Differential Inputs and Outputs All PIO pins support “single-ended” I/O standards, such as LVCMOS. However, iCE65 FPGAs also support differential I/O standards where a single data value is represented by two complementary signals transmitted or received using a pair of PIO pins. The PIO pins in I/O Bank 3 of iCE65L04 and iCE65L08L08 support Low-Voltage Differential Swing (LVDS) and SubLVDS inputs as shown in Figure 8. Differential outputs are available in all four I/O banks. Differential Inputs Only on I/O Bank 3 of iCE65L04 and iCE65L08 Differential receivers are required for popular applications such as LVDS and LVPECL clock inputs, camera interfaces, and for various telecommunications standards. Specific pairs of PIO pins in I/O Bank 3 form a differential input. Each pair consists of a DPxxA and DPxxB pin, where “xx” represents the pair number. The DPxxB receives the true version of the signal while the DPxxA receives the complement of the signal. Typically, the resulting signal pair is routed on the printed circuit board (PCB) with matched 50Ω signal impedance. The differential signaling, the low voltage swing, and the matched signal routing are ideal for communicating very-high frequency signals. Differential signals are generally also more tolerant of system noise and generate little EMI themselves. The LVDS input circuitry requires 2.5V on the VCCIO_3 voltage supply. Similarly, the SubLVDS input circuitry requires 1.8V on the VCCIO_3 voltage supply. For electrical specifications, see “Differential Inputs” on page 100. Each differential input pair requires an external 100 Ω termination resistor, as shown in Figure 8. The PIO pins that make up a differential input pair are indicated with a blue bounding box in the footprint diagrams and in the pinout tables. (2.42, 30-MAR-2012) 12 Lattice Semiconductor Corporation www.latticesemi.com Figure 8: Differential Inputs in iCE65L04 and iC65L08 I/O Bank 3 Impedance-matched signal traces VCCIO_3 = 1.8V or 2.5V DPxxB 100Ω 50Ω 50Ω DPxxA iC65 Differential Input External 100Ω termination resistor 1 0 1 0 Noise pulse affects both traces similarly. Difference between signals remains nearly constant. Differential Outputs in Any Bank Differential outputs are built using a pair of single-ended PIO pins as shown in Figure 9. Each differential I/O pair requires a three-resistor termination network to adjust output characteristic to match those for the specific differential I/O standard. The output characteristics depend on the values of the parallel resistors (RP) and series resistor (RS). Differential outputs must be located in the same I/O tile. Figure 9: Differential Output Pair External output compensation resistor network Impedance-matched signal traces VCCIO_x RS RS 50Ω RP 50Ω iC65 Differential Output Pair 1 0 1 0 Noise pulse affects both traces similarly. Difference is signals remains nearly constant. For electrical characteristics, see “Differential Outputs” on page 100. The PIO pins that make up a differential output pair are indicated with a blue bounding box in the in the tables in “Die Cross Reference” starting on page 84. Lattice Semiconductor Corporation www.latticesemi.com (2.42, 30-MAR-2011) 13 iCE65 Ultra Low-Power mobileFPGA™ Family Input Signal Path As shown in Figure 7, a signal from a package pin optionally feeds directly into the device, or is held in an input register. The input signal connects to the programmable interconnect resources through the IN signal. Table 9 describes the input behavior, assuming that the output path is not used or if a bidirectional I/O, that the output driver is in its high-impedance state (Hi-Z). Table 9 also indicates the effect of the Power-Saving I/O Bank iCEgate Latch and the Input Pull-Up Resistors on I/O Banks 0, 1, and 2. See Input and Output Register Control per PIO Pair for information about the registered input path. Power-Saving I/O Bank iCEgate Latch To save power, the optional iCEgate latch can selectively freeze the state of individual, non-registered inputs within an I/O bank. Registered inputs are effectively frozen by their associated clock or clock-enable control. As shown in Figure 10, the iCEgate HOLD control signal captures the external value from the associated asynchronous input. The HOLD signal prevents switching activity on the PIO pad from affecting internal logic or programmable interconnect. Minimum power consumption occurs when there is no switching. However, individual pins within the I/O bank can bypass the iCEgate latch and directly feed into the programmable interconnect, remaining active during low-power operation. This behavior is described in Table 9. The decision on which asynchronous inputs use the iCEgate feature and which inputs bypass it is determined during system design. In other words, the iCEgate function is part of the source design used to create the iCE65 configuration image. Figure 10: Power-Saving iCEgate Latch PIO PAD D HOLD Controlled by configuration image; allows pin-by-pin option to freeze input with iCEgate Q LE Optional iCEgate Latch PAD HOLD Input Follow value on PAD Freeze last value Follow value on PAD Table 9: PIO Non-Registered Input Operations HOLD Operation Data Input Pad Floating, No Pull-up Pad Floating, Pull-up Data Input, Latch Bypassed Pad Floating, No Pull-up, Latch Bypassed Pad Floating, Pull-up, Latch Bypassed Low Power Mode, Hold Last Value iCEgate Latch 0 0 0 X Bitstream Setting Controlled Input Pullby iCEgate? Up Enabled? X X X No X Yes No X PAD Pin Value PAD Z Z PAD IN Input Value to Interconnect PAD Value (Undefined) 1 PAD Value X No No Z (Undefined) X No Yes Z 1 1 Yes X X Last Captured PAD Value There are four iCEgate HOLD controls, one per each I/O bank. The iCEgate HOLD control input originates within the interconnect fabric, near the middle of the I/O edge. Consequently, the HOLD signal is optionally controlled externally through a PIO pin or from other logic within the iCE65 device. (2.42, 30-MAR-2012) 14 Lattice Semiconductor Corporation www.latticesemi.com For best possible performance, the global buffer inputs (GBIN[7:-0]) connect directly to the their associated global buffers (GBUF[7:0]), bypassing the PIO logic and iCEgate circuitry as shown in Figure 7. Consequently, the direct GBIN-to-GBUF connection cannot be blocked by the iCEgate circuitry. However, it is possible to use iCEgate to block PIO-to-GBUF clock connections. i For additional information on using the iCEgate feature, please refer to the following application note. AN002: Using iCEgate Blocking for Ultra-Low Power Input Pull-Up Resistors on I/O Banks 0, 1, and 2 The PIO pins in I/O Banks 0, 1, and 2 have an optional input pull-up resistor. Pull-up resistors are not provided in iCE65L04 and iCE65L08 I/O Bank 3. During the iCE65 configuration process, the input pull-up resistor is unconditionally enabled and pulls the input to within a diode drop of the associated I/O bank supply voltage (VCCIO_#). This prevents any signals from floating on the circuit board during configuration. After iCE65 configuration is complete, the input pull-up resistor is optional, defined by a configuration bit. The pull-up resistor is also useful to tie off unused PIO pins. The Lattice iCEcube development software defines all unused PIO pins in I/O Banks 0, 1 and 2 as inputs with the pull-up resistor turned on. The pull-up resistor value depends on the VCCIO voltage applied to the bank, as shown in Table 49. ! Note: JTAG inputs TCK, TDI and TMS do not have the input pull-up resistor and must be tied off to GND when unused, else VCCIO_1 draws current. No Input Pull-up Resistors on I/O Bank 3 of iCE65L04 and iCE65L08 The PIO pins in I/O Bank 3 do not have an internal pull-up resistor. To minimize power consumption, tie unused PIO pins in Bank 3 to a known logic level or drive them as a disabled high-impedance output. Input Hysteresis Inputs typically have about 50 mV of hysteresis, as indicated in Table 49. Output and Output Enable Signal Path As shown in Figure 7, a signal from programmable interconnect feeds the OUT signal on a Programmable I/O pad. This output connects either directly to the associated package pin or is held in an optional output flip-flop. Because all flip-flops are automatically reset after configuration, the output from the output flip-flop can be optionally inverted so that an active-Low output signal is held in the disabled (High) state immediately after configuration. Similarly, each Programmable I/O pin has an output enable or three-state control called OE. When OE = High, the OUT output signal drives the associated pad, as described in Table 10. When OE = Low, the output driver is in the high-impedance (Hi-Z) state. The OE output enable control signal itself connects either directly to the output buffer or is held in an optional register. The output buffer is optionally permanently enabled or permanently disabled, either to unconditionally drive output signals, or to allow input-only signals. Table 10: PIO Output Operations (non-registered operation, no inversions) OUT OE Data Output Enable Three-State X 0 Drive Output Data OUT 1* X = don’t care, 1* = High or unused, Hi-Z = high-impedance, three-stated, floating. Operation PAD Hi-Z OUT See Input and Output Register Control per PIO Pair for information about the registered input path. Lattice Semiconductor Corporation www.latticesemi.com (2.42, 30-MAR-2011) 15 iCE65 Ultra Low-Power mobileFPGA™ Family Input and Output Register Control per PIO Pair PIO pins are grouped into pairs for synchronous control. Registers within pairs of PIO pins share common input clock, output clock, and I/O clock enable control signals, as illustrated in Figure 11. The combinational logic paths are removed from the drawing for clarity. The INCLK clock signal only controls the input flip-flops within the PIO pair. The OUTCLK clock signal controls the output flip-flops and the output-enable flip-flops within the PIO pair. If desired in the iCE65 application, the INCLK and OUTCLK signals can be connected together. The IOENA clock-enable input, if used, enables all registers in the PIO pair, as shown in Figure 11. By default, the registers are always enabled. ! Before laying out your printed-circuit board, run the design through the iCEcube development software to verify that your selected pinout complies with these I/O register pairing requirements. See tables in “Die Cross Reference” starting on page 84. Figure 11: PIO Pairs Share Clock and Clock Enable Controls (only registered paths shown for clarity) PIO Pair OUTCLK IOENA 1 INCLK OE OE PAD EN EN 0 = Hi-Z 1 = Output Enabled PAD OUT IN 0 = Hi-Z 1 = Output Enabled Output Clock EN I/O Register Enable IN Input Clock OUT EN EN EN = Statically defined by configuration program The pairing of PIO pairs is most evident in the tables in “Die Cross Reference” starting on page 84. (2.42, 30-MAR-2012) 16 Lattice Semiconductor Corporation www.latticesemi.com Double Data Rate (DDR) Flip-Flops Each individual PIO pin optionally has two sets of double data rate (DDR) flip-flops; one input pair and one output pair. Figure 12 demonstrates the functionality of the output DDR flip-flop. Two signals from within the iCE65 device drive the DDR output flip-flop. The D_OUT_0 signal is clocked by the rising edge of the OUTCLK signal while the D_OUT_1 signal is clocked by the falling edge of the OUTCLK signal, assuming no optional clock polarity inversion. Internally, the two individual flip-flops are multiplexed together before the data appears at the pad, effectively doubling the output data rate. Figure 12: DDR Output Flip-Flop OE IOENA D_OUT_1 D Q 0 D_OUT_0 D Q 1 S EN EN PAD PIO OUTCLK OUTCLK PAD D0 D1 D0 D1 D0 D1 Similarly, Figure 13 demonstrates the DDR input flip-flop functionality. A double data rate (DDR) signal arrives at the pad. Internally, one value is clocked by the rising edge of the INCLK signal and another value is clocked by the falling edge of the INCLK signal. The DDR data stream is effectively de-multiplexed within the PIO pin and presented to the programmable interconnect on D_IN_0 and D_IN_1. Figure 13: DDR Input Flip-Flop IOENA PIO D Q D_IN_1 D Q D_IN_0 EN PAD EN INCLK INCLK PAD D_IN_0 D_IN_1 D0 D1 D0 D0 D1 D0 D0 D1 D1 D0 D1 D1 The DDR flip-flops provide several design advantages. Internally within the iCE65 device, the clock frequency is half the effective external data rate. The lower clock frequency eases internal timing, doubling the clock period, and slashes the clock-related power in half. Lattice Semiconductor Corporation www.latticesemi.com (2.42, 30-MAR-2011) 17 iCE65 Ultra Low-Power mobileFPGA™ Family Global Routing Resources Global Buffers Each iCE65 component has eight global buffer routing connections, illustrated in Figure 14. There are eight highdrive buffers, connected to the eight low-skew, global lines. These lines are designed primarily for clock distribution but are also useful for other high-fanout signals such as set/reset and enable signals. The global buffers originate either from the Global Buffer Inputs (GBINx) or from programmable interconnect. The associated GBINx pin represents the best pin to drive a global buffer from an external source. However, the application with an iCE65 FPGA can also drive a global buffer via any other PIO pin or from internal logic using the programmable interconnect. If not used in an application, individual global buffers are turned off to save power. Figure 14: High-drive, Low-skew, High-fanout Global Buffer Routing Resources GBUF6 Global Buffer GBUF3 Global Buffer GBIN3 I/O Bank 2 GBIN4 GBIN5 GBIN2 I/O Bank 1 Global Buffer GBUF2 Global Buffer GBUF5 Global Buffer GBUF7 and its associated are best for direct GBUF7 PIO differential clock inputs GBUF4 Global Buffer I/O Bank 3 GBIN6 Global Buffer GBUF1 GBUF0 Global Buffer GBIN7 GBIN1 GBIN0 I/O Bank 0 Table 11 lists the connections between a specific global buffer and the inputs on a Programmable Logic Block (PLB). All global buffers optionally connect to all clock inputs. Any four of the eight global buffers can drive logic inputs to a PLB. Even-numbered global buffers optionally drive the Reset input to a PLB. Similarly, odd-numbered buffers optionally drive the PLB clock-enable input. Table 11: Global Buffer (GBUF) Connections to Programmable Logic Block (PLB) Global Buffer LUT Inputs Clock Clock Enable Reset GBUF0 GBUF1 GBUF2 GBUF3 GBUF4 GBUF5 GBUF6 GBUF7 (2.42, 30-MAR-2012) 18 Yes, any 4 of 8 GBUF buffers Yes Yes Yes Yes Yes Yes Yes Yes Yes No Yes No Yes No Yes No No Yes No Yes No Yes No Yes Lattice Semiconductor Corporation www.latticesemi.com Table 12 and Table 13 list the connections between a specific global buffer and the inputs on a Programmable I/O (PIO) pair. Although there is no direct connection between a global buffer and a PIO output, such a connection is possible by first connecting through a PLB LUT4 function. Again, all global buffers optionally drive all clock inputs. However, even-numbered global buffers optionally drive the clock-enable input on a PIO pair. ! The PIO clock enable connect is different between the iCE65L01/iCE65L04 and iCE65L08. Table 12: iCE65L01 & iCE65L04: Global Buffer (GBUF) Connections to Programmable I/O (PIO) Pair Output Global Buffer Connections Input Clock Output Clock Clock Enable GBUF0 GBUF1 GBUF2 GBUF3 GBUF4 GBUF5 GBUF6 GBUF7 No (connect through PLB LUT) Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No Yes No Yes No Yes No Yes Table 13: iCE64L08: Global Buffer (GBUF) Connections to Programmable I/O (PIO) Pair Output Global Buffer Connections Input Clock Output Clock Clock Enable GBUF0 GBUF1 GBUF2 GBUF3 GBUF4 GBUF5 GBUF6 GBUF7 No (connect through PLB LUT) Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No Yes No Yes No Yes No Global Buffer Inputs The iCE65 component has eight specialized GBIN/PIO pins that are optionally direct inputs to the global buffers, offering the best overall clock characteristics. As shown in Figure 15, each GBIN/PIO pin is a full-featured I/O pin but also provides a direct connection to its associated global buffer. The direct connection to the global buffer bypasses the iCEgate input-blocking latch and other PIO input logic. These special PIO pins are allocated two to an I/O Bank, a total of eight. These pins are labeled GBIN0 through GBIN7, as shown in Figure 14 and the pin locations for each GBIN input appear in Table 14. Table 14: Global Buffer Input Ball/Pin Number by Package Global Buffer Input (GBIN) I/O Bank VQ100 90 89 CB132 A6 A7 ‘L04 CB196 A7 E7 ‘L08 CB196 A7 E7 CB284 E10 E11 GBIN0 GBIN1 0 GBIN2 GBIN3 1 63 62 G14 F14 F10 G12 F10 G12 L18 K18 GBIN4 GBIN5 2 34 33 P8 P7 L7 P5 N8 M7 V12 V11 GBIN6 GBIN7 3 15 13 H1 G1 H1 G1 H1 H3 M5 L5 Lattice Semiconductor Corporation www.latticesemi.com (2.42, 30-MAR-2011) 19 iCE65 Ultra Low-Power mobileFPGA™ Family ! Note the clock differences between the iCE65L04 and iCE65L08 in the CB196 package. Figure 15: GBIN/PIO Pin VCCIO GBIN/PIO Pin Enabled ‘1’ Disabled ‘0’ 0 = Hi-Z 1 = Output Enabled OE Pull-up not in I/O Bank 3 Pull-up Enable OUT PAD iCEGATE HOLD HD Latch inhibits switching for lowest power IN GBIN pins optionally connect directly to an associated GBUF global buffer Optional connection from internal programmable interconnect. GBUF Differential Global Buffer Input All eight global buffer inputs support single-ended I/O standards such as LVCMOS. Global buffer GBUF7 in I/O Bank 3 also provides an optional direct SubLVDS, LVDS, or LVPECL differential clock input, as shown in Figure 16. The GBIN7 and its associated differential I/O pad accept a differential clock signal. A 100 Ω termination resistor is required across the two pads. Optionally, swap the outputs from the LVDS or LVPECL clock driver to invert the clock as it enters the iCE65 device. Figure 16: LVDS or LVPECL Clock Input 100Ω GBIN7/DP##B LVDS/ LVPECL Clock Driver DP##A GBUF7 Table 15 lists the pin or ball numbers for the differential global buffer input by package style. Although this differential input is the only one that connects directly to a global buffer, other differential inputs can connect to a global buffer using general-purpose interconnect, with slightly more signal delay. Table 15: Differential Global Buffer Input Ball/Pin Number by Package Differential Global Buffer Input ‘L04 ‘L08 I/O (GBIN) VQ100 CB132 CB196 CB196 Bank GBIN7/DPxxB DPxxA ! 3 13 12 N/A N/A G1 G2 H3 H4 CB284 L5 L3 The differential global buffer input is not available for iCE65 devices in the CB132 package. This restriction is an artifact of the pin compatibility between the CB132 and CB284 package. Note the clock differences between the iCE65L04 and iCE65L08 in the CB196 package. (2.42, 30-MAR-2012) 20 Lattice Semiconductor Corporation www.latticesemi.com Automatic Global Buffer Insertion, Manual Insertion The iCEcube development software automatically assigns high-fanout signals to a global buffer. However, to manual insert a global buffer input/global buffer (GBIN/GBUF) combination, use the SB_IO_GB primitive. To insert just a global buffer (GBUF), use the SB_GB primitive. Global Hi-Z Control The global high-impedance control signal, GHIZ, connects to all I/O pins on the iCE65 device. This GHIZ signal is automatically asserted throughout the configuration process, forcing all user-I/O pins into their high-impedance state. Similarly, the PIO pins can be forced into their high-impedance state via the JTAG controller. Global Reset Control The global reset control signal connects to all PLB and PIO flip-flops on the iCE65 device. The global reset signal is automatically asserted throughout the configuration process, forcing all flip-flops to their defined wake-up state. For PLB flip-flops, the wake-up state is always reset, regardless of the PLB flip-flop primitive used in the application. See Table 3 for more information. The PIO flip-flops are always reset during configuration, although the output flip-flop can be inverted before leaving the iCE65 device, as shown in Figure 11. RAM Each iCE65 device includes multiple high-speed synchronous RAM blocks (RAM4K), each 4Kbit in size. As shown in Table 16 a single iCE65 integrates between 16 to 96 such blocks. Each RAM4K block is generically a 256-word deep by 16-bit wide, two-port register file, as illustrated in Figure 17. The input and output connections, to and from a RAM4K block, feed into the programmable interconnect resources. Figure 17: RAM4K Memory Block Write Port Read Port WDATA[15:0] RDATA[15:0] MASK[15:0] WADDR[7:0] WE Device RAM4K Blocks iCE65L01 16 iCE65L04 20 iCE65L08 32 RAM4K RAM Block (256x16) RADDR[7:0] RE WCLKE RCLKE WCLK RCLK Table 16: RAM4K Blocks per Device Default Configuration RAM Bits per Block Block RAM Bits 64K 256 x 16 4K (4,096) 80K 128K Using programmable logic resources, a RAM4K block implements a variety of logic functions, each with configurable input and output data width.  Random-access memory (RAM)  Single-port RAM with a common address, enable, and clock control lines  Two-port RAM with separate read and write control lines, address inputs, and enable Lattice Semiconductor Corporation www.latticesemi.com (2.42, 30-MAR-2011) 21 iCE65 Ultra Low-Power mobileFPGA™ Family     Register file and scratchpad RAM First-In, First-Out (FIFO) memory for data buffering applications Circuit buffer A 256-deep by 16-wide ROM with registered outputs, contents loaded during configuration  Sixteen different 8-input look-up tables  Function or waveform tables such as sine, cosine, etc.  Correlators or pattern matching operations  Counters, sequencers As pictured in Figure 17, a RAM4K block has separate write and read ports, each with independent control signals. Table 17 lists the signals for both ports. Additionally, the write port has an active-Low bit-line write-enable control; optionally mask write operations on individual bits. By default, input and output data is 16 bits wide, although the data width is configurable using programmable logic and, if needed, multiple RAM4K blocks. The WCLK and RCLK inputs optionally connect to one of the following clock sources.  The output from any one of the eight Global Buffers, or  A connection from the general-purpose interconnect fabric The data contents of the RAM4K block are optionally pre-loaded during iCE65 device configuration. If the RAM4K blocks are not pre-loaded during configuration, then the resulting configuration bitstream image is smaller. However, if an uninitialized RAM4K block is used in the application, then the application must initialize the RAM contents to guarantee the data value. See Table 56 for detailed timing information. Signals Table 17 lists the signal names, direction, and function of each connection to the RAM4K block. See also Figure 17. Signal Name WDATA[15:0] MASK[15:0] Direction Input Input WADDR[7:0] WE WCLKE WCLK RDATA[15:0] RADDR[7:0] RE RCLKE RCLK Input Input Input Input Output Input Input Input Input Table 17: RAM4K Block RAM Signals Description Write Data input. Masks write operations for individual data bit-lines. 0 = Write bit; 1 = Don’t write bit Write Address input. Selects one of 256 possible RAM locations. Write Enable input. Write Clock Enable input. Write Clock input. Default rising-edge, but with falling-edge option. Read Data output. Read Address input. Selects one of 256 possible RAM locations. Read Enable input. Read Clock Enable input. Read Clock input. Default rising-edge, but with falling-edge option. Write Operations Figure 18 shows the logic involved in writing a data bit to a RAM location. Table 18 describes various write operations for a RAM4K block. By default, all RAM4K write operations are synchronized to the rising edge of WCLK although the clock is invertible as shown in Figure 18. (2.42, 30-MAR-2012) 22 Lattice Semiconductor Corporation www.latticesemi.com Figure 18: RAM4K Bit Write Logic RAM[LOCATION][BIT] D WDATA[BIT] MASK[BIT] WE DECODE LOCATION WADDR[7:0] EN WCLKE WCLK When the WCLKE signal is Low, the clock to the RAM4K block is disabled, keeping the RAM in its lowest power mode. WDATA[15:0] Operation Disabled Disabled Disabled Write Data Masked Write Table 18: RAM4K Write Operations MASK[15:0] WADDR[7:0] WE Write Mask Bit Address Enable X X X X WDATA[i] X MASK[i] = 0 X WADDR 0 1 WCLKE Clock Enable X 0 X 1 X MASK[i] = 1 WADDR 1 1 Data X WCLK ↑ Clock 0 X X ↑ RAM Location No change No change No change RAM[WADDR][i] = WDATA[i] RAM[WADDR][i] = No change To write data into the RAM4K block, perform the following operations.  Supply a valid address on the WADDR[7:0] address input port  Supply valid data on the WDATA[15:0] data input port  To write or mask selected data bits, set the associated MASK input port accordingly. For example, write operations on data bit D[i] are controlled by the associated MASK[i] input.  MASK[i] = 0: Write operations are enabled for data line WDATA[i]  MASK[i] = 1: Mask write operations are disabled for data line WDATA[i]  Enable the RAM4K write port (WE = 1)  Enable the RAM4K write clock (WCLKE = 1)  Apply a rising clock edge on WCLK (assuming that the clock is not inverted) Read Operations Figure 19 shows the logic involved in reading a location from RAM. Table 19 describes various read operations for a RAM4K block. By default, all RAM4K read operations are synchronized to the rising edge of RCLK although the clock is invertible as shown in Figure 19. Lattice Semiconductor Corporation www.latticesemi.com (2.42, 30-MAR-2011) 23 iCE65 Ultra Low-Power mobileFPGA™ Family Figure 19: RAM4K Read Logic Select Location Output Register RAM[LOCATION] Q D Q RDATA[15:0] EN RADDR[7:0] RE RCLKE RCLK Operation After configuration, before first valid Read Data operation Disabled Disabled Disabled Read Data Table 19: RAM4K Read Operations RADDR[7:0] RE RCLKE Read Clock Address Enable Enabe RCLK Clock RDATA[15:0] X X X X Undefined X X X 0 1 X 0 X 1 0 X X ↑ No Change No Change No change RAM[RADDR] X RADDR To read data from the RAM4K block, perform the following operations.  Supply a valid address on the RADDR[7:0] address input port  Enable the RAM4K read port (RE = 1)  Enable the RAM4K read clock (RCLKE = 1)  Apply a rising clock edge on RCLK  After the clock edge, the RAM contents located at the specified address (RADDR) appear on the RDATA output port Read Data Register Undefined Immediately after Configuration Unlike the flip-flops in the Programmable Logic Blocks and Programmable I/O pins, the RDATA[15:0] read data output register is not automatically reset after configuration. Consequently, immediately following configuration and before the first valid Read Data operation, the initial RDATA[15:0] read value is undefined. Pre-loading RAM Data The data contents for a RAM4K block can be optionally pre-loaded during iCE65 configuration. If not pre-loaded during configuration, then the RAM contents must be initialized by the iCE65 application before the RAM contents are valid. Pre-loading the RAM data in the configuration bitstream increases the size of the configuration image accordingly. RAM Contents Preserved during Configuration RAM contents are preserved (write protected) during configuration, assuming that voltage supplies are maintained throughout. Consequently, data can be passed between multiple iCE65 configurations by leaving it in a RAM4K block and then skipping pre-loading during the subsequent reconfiguration. See “Cold Boot Configuration Option” and “Warm Boot Configuration Option” for more information. Low-Power Setting To place a RAM4K block in its lowest power mode, keep WCLKE = 0 and RCLKE = 0. In other words, when not actively using a RAM4K block, disable the clock inputs. (2.42, 30-MAR-2012) 24 Lattice Semiconductor Corporation www.latticesemi.com Device Configuration As described in Table 20, iCE65 components are configured for a specific application by loading a binary configuration bitstream image, generated by the Lattice development system. For high-volume applications, the bitstream image is usually permanently programmed in the on-chip NVCM, However, the bitstream image can also be stored external in a standard, low-cost commodity SPI serial Flash PROM. The iCE65 component can automatically load the image using the SPI Master Configuration Interface. Similarly, the iCE65 configuration data can be downloaded from an external processor, microcontroller, or DSP processor using an SPI-like serial interface or an IEEE 1149 JTAG interface. Table 20: iCE65 Device Configuration Modes Configuration Data Source Mode Analogy NVCM ASIC SPI Flash Microprocessor SPI Peripheral Processor Peripheral Configured by external device, such as a processor, microcontroller, or DSP using practically any data source, such as system Flash, a disk image, or over a network connection. JTAG JTAG JTAG configuration requires sending a special command sequence on the SPI interface to enable JTAG configuration. Configuration is controlled by and external device. Internal, lowest-cost, secure, one-time programmable Nonvolatile Configuration Memory (NVCM) External, low-cost, commodity, SPI serial Flash PROM Configuration Mode Selection The iCE65 configuration mode is selected according to the following priority described below and illustrated in Figure 20.  After exiting the Power-On Reset (POR) state or when CRESET_B returns High after being held Low for 250 ns or more, the iCE65 FPGA samples the logical value on its SPI_SS_B pin. Like other programmable I/O pins, the SPI_SS_B pin has an internal pull-up resistor (see Input Pull-Up Resistors on I/O Banks 0, 1, and 2).  If the SPI_SS_B pin is sampled as a logic ‘1’ (High), then …  Check if the iCE65 is enabled to configure from the Nonvolatile Configuration Memory (NVCM). If the iCE65 device has NVCM memory (‘F’ ordering code) but the NVCM is yet unprogrammed, then the iCE65 device is not enabled to configure from NVCM. Conversely, if the NVCM is programmed, the iCE65 device will configure from NVCM.  If enabled to configure from NVCM, the iCE65 device configures itself using NVCM.  If not enabled to configure from NVCM, then the iCE65 FPGA configures using the SPI Master Configuration Interface.  If the SPI_SS_B pin is sampled as a logic ‘0’ (Low), then the iCE65 device waits to be configured from an external controller or from another iCE65 device in SPI Master Configuration Mode using an SPI-like interface. Lattice Semiconductor Corporation www.latticesemi.com (2.42, 30-MAR-2011) 25 iCE65 Ultra Low-Power mobileFPGA™ Family Figure 20: Device Configuration Control Flow Power-Up CDONE = 0 No Is Power-On Reset (POR) Released? iCE65 checks that all required supply voltages are within acceptable range Yes No CRESET_B = High? Holding CRESET_B Low delays the start of configuration of SPI_SS_B Yes State pin sampled SPI_SS_B = High? Yes NVCM Enabled for Configuration? No Configure Configureas from SPI Periphal NVCM A device with an unprogrammed NVCM is not enabled for configuration. Yes Configure from NVCM No Configure from SPI Flash PROM CDONE = 1 No CRESET_B = Low? After configuration ends, pulse the CRESET_B pin Low for 250 ns or longer to restart configuration process or cycle the power Yes Configuration Image Size Table 23 shows the number of memory bits required to configure an iCE65 device. Two values are provided for each device. The “Logic Only” value indicates the minimum configuration size, the number of bits required to configure only the logic fabric, leaving the RAM4K blocks uninitialized. The “Logic + RAM4K” column indicates the maximum configuration size, the number of bits to configure the logic fabric and to pre-initialize all the RAM4K blocks. (2.42, 30-MAR-2012) 26 Lattice Semiconductor Corporation www.latticesemi.com Device Table 21: iCE65 Configuration Image Size (Kbits) MINIMUM MAXIUM Logic Only Logic + RAM4K (RAM4K not initialized) (RAM4K pre-initialized) iCE65L01 181 Kbits 245 Kbits* iCE65L04 453 Kbits 533 Kbits iCE65L08 929 Kbits 1,057 Kbits * Note: only 14 of the 16 RAM4K Memory Blocks may be pre-initialized in the iCE65L01. Nonvolatile Configuration Memory (NVCM) All standard iCE65 devices have an internal, nonvolatile configuration memory (NVCM). The NVCM is large enough to program a complete iCE65 device, including initializing all RAM4K block locations (MAXIMUM column in Table 23. The NVCM memory also has very high programming yield due to extensive error checking and correction (ECC) circuitry. The NVCM is ideal for cost-sensitive, high-volume production applications, saving the cost and board space associated with an external configuration PROM. Furthermore, the NVCM provides exceptional design security, protecting critical intellectual property (IP). The NVCM contents are entirely contained within the iCE65 device and are not readable once protected by the one-time programmable Security bits. Furthermore, there is no observable difference between a programmed or un-programmed memory cell using optical or electron microscopy. The NVCM memory has a programming interface similar to a 25-series SPI serial Flash PROM. Consequently, it can be programmed using standard device programmers before or after circuit board assembly or programmed in-system from a microprocessor or other intelligent controller. NVCM programming requires VCCIO_1, Bank 1 voltage to be applied on power-up, at the same time as other voltage supplies. Configuration Control Signals The iCE65 configuration process is self-timed and controlled by a few internal signals and device I/O pins, as described in Table 22. Table 22: iCE65 Configuration Control Signals Signal Name POR OSC CRESET_B CDONE Direction Internal control Internal control Input Open-drain Output Description Internal Power-On Reset (POR) circuit. Internal configuration oscillator. Configuration Reset input. Active-Low. No internal pull-up resistor. Configuration Done output. Permanent, weak pull-up resistor to VCCIO_2. The Power-On Reset circuit, POR, automatically resets the iCE65 component to a known state during power-up (cold boot). The POR circuit monitors the relevant voltage supply inputs, as shown in Figure 22. Once all supplies exceed their minimum thresholds, the configuration controller can start the configuration process. The configuration controller begins configuring the iCE65 device, clocked by the Internal Oscillator, OSC. The OSC oscillator continues controlling configuration unless the iCE65 device is configured using the SPI Peripheral Configuration Interface. Lattice Semiconductor Corporation www.latticesemi.com (2.42, 30-MAR-2011) 27 iCE65 Ultra Low-Power mobileFPGA™ Family Figure 21: iCE65 Configuration Control Pins Optional Pull-up Required if driven by open-drain output VCCIO_2 Optional Pull-up SiliconBlue iCE65 Recommended if driving another device VCCIO_2 I/O Bank 2 10 kΩ CRESET_B Rising edge starts configuration process. Pulse CRESET_B Low for 200 ns to restart configuration Low resets iCE65 10 kΩ CDONE Configured PIOs activate 49 configuration clock cycles after CDONE goes High Unconfigured Figure 21 shows the two iCE65 configuration control pins, CRESET_B and CDONE. Table 23 lists the ball/pin numbers for the configuration control pins by package. When driven Low for at least 200 ns, the dedicated Configuration Reset input, CRESET_B, resets the iCE65 device. When CRESET_B returns High, the iCE65 FPGA restarts the configuration process from its power-on conditions (Cold Boot). The CRESET_B pin is a pure input with no internal pull-up resistor. If driven by open-drain driver or un-driven, then connect the CRESET_B pin to a 10 kΩ pull-up resistor connected to the VCCIO_2 supply. Table 23: Configuration Control Ball/Pin Numbers by Package Configuration Control Pins CRESET_B CDONE CB81 J6 H6 QN84 A21 B16 VQ100 44 43 CB132 L10 M10 CB196 L10 M10 CB284 R14 T14 The iCE65 device signals the end of the configuration process by actively turning off the internal pull-down transistor on the Configuration Done output pin, CDONE. The pin has a permanent, weak internal pull-up resistor to the VCCIO_2 rail. If the iCE65 device drives other devices, then optionally connect the CDONE pin to a 10 kΩ pull-up resistor connected to the VCCIO_2 supply. The PIO pins activate according to their configured function after 49 configuration clock cycles. The internal oscillator is the configuration clock source for the SPI Master Configuration Interface and when configuring from * Note: only 14 of the 16 RAM4K Memory Blocks may be pre-initialized in the iCE65L01. Nonvolatile Configuration Memory (NVCM). When using the SPI Peripheral Configuration Interface, the configuration clock source is the SPI_SCK clock input pin. Internal Oscillator During SPI Master or NVCM configuration mode, the controlling clock signal is generated from an internal oscillator. The oscillator starts operating at the Default frequency. During the configuration process, however, bit settings within the configuration bitstream can specify a higher-frequency mode in order to maximize SPI bandwidth and reduce overall configuration time. See Table 57: Internal Oscillator Frequency on page 105 for the specified oscillator frequency range. Using the SPI Master Configuration Interface, internal oscillator controls all the interface timing and clocks the SPI serial Flash PROM via the SPI_SCK clock output pin. The oscillator output, which also supplies the SPI SCK clock output during the SPI Flash configuration process, has a 50% duty cycle. Internal Device Reset Figure 22 presents the various signals that internally reset the iCE65 internal logic.  Power-On Reset (POR)  CRESET_B Pin  JTAG Interface (2.42, 30-MAR-2012) 28 Lattice Semiconductor Corporation www.latticesemi.com Figure 22: iCE65 Internal Reset Circuitry Device Pins SPI_VCC Internal Voltage Thresholds SPI_VCCT Power-on Reset (POR) Time-out Delay VCC VCCT VCCIO_2 VCCIO_2T VPP_2V5 VPP_2V5T CRESET_B Internal Reset Glitch Filter TDI TMS TCK JTAG TDO TRST_B Power-On Reset (POR) The Power-on Reset (POR) circuit monitors specific voltage supply inputs and holds the device in reset until all the relevant supplies exceed the internal voltage thresholds. The SPI_VCC supply also has an additional time-out delay to allow an attached SPI serial PROM to power up properly. Table 24 shows the POR supply inputs. The Nonvolatile Configuration Memory (NVCM) requires that the VPP_2V5 supply be connected, even if the application does not use the NVCM. Table 24: Power-on Reset (POR) Voltage Resources Supply Rail iCE65 Production Devices VCC SPI_VCC VCCIO_1 VCCIO_2 VPP_2V5 Yes Yes No Yes Yes CRESET_B Pin The CRESET_B pin resets the iCE65 internal logic when Low. JTAG Interface Specific command sequences also reset the iCE65 internal logic. SPI Master Configuration Interface All iCE65 devices, including those with NVCM, can be configured from an external, commodity SPI serial Flash PROM, as shown in Figure 23. The SPI configuration interface is essentially its own independent I/O bank, powered by the VCC_SPI supply input. Presently, most commercially-available SPI serial Flash PROMs require a 3.3V supply. Lattice Semiconductor Corporation www.latticesemi.com (2.42, 30-MAR-2011) 29 iCE65 Ultra Low-Power mobileFPGA™ Family Figure 23: iCE65 SPI Master Configuration Interface +3.3V SPI_VCC 10 kΩ SPI_SO SiliconBlue iCE65 (SPI bank) SPI_SI SPI_SS_B Commodity SPI Serial Flash PROM SPI_SCK The SPI configuration interface is used primarily during development before mass production, where the configuration is then permanently programmed in the NVCM configuration memory. However, the SPI interface can also be the primary configuration interface allowing easy in-system upgrades and support for multiple configuration images. The SPI control signals are defined in Table 25. Table 26 lists the SPI interface ball or pins numbers by package. Table 25: SPI Master Configuration Interface Pins (SPI_SS_B High before Configuration) Signal Name SPI_VCC SPI_SO SPI_SI SPI_SS_B SPI_SCK Direction Supply Output Input Output Output SPI SPI SPI SPI SPI Description Flash PROM voltage supply input. Serial Output from the iCE65 device. Serial Input to the iCE65 device, driven by the select SPI serial Flash PROM. Slave Select output from the iCE65 device. Active Low. Slave Clock output from the iCE65 device. After configuration, the SPI port pins are available to the user-application as additional PIO pins, supplied by the SPI_VCC input voltage, essentially providing a fifth “mini” I/O bank. Table 26: SPI Interface Ball/Pin Numbers by Package SPI Interface SPI_VCC PIOS/SPI_SO PIOS/SPI_SI PIOS/SPI_SS_B PIOS/SPI_SCK VQ100 50 45 46 49 48 CB132 L11 M11 P11 P13 P12 CB196 L11 M11 P11 P13 P12 CB284 R15 T15 V15 V17 V16 SPI PROM Requirements The iCE65 mobileFPGA SPI Flash configuration interface supports a variety of SPI Flash memory vendors and product families. However, Lattice Semiconductor does not specifically test, qualify, or otherwise endorse any specific SPI Flash vendor or product family. The iCE65 SPI interface supports SPI PROMs that they meet the following requirements.  The PROM must operate at 3.3V or 2.5V in order to trigger the iCE65 FPGA’s power-on reset circuit.  The PROM must support the 0x0B Fast Read command, using a 24-bit start address and has 8 dummy bits before the PROM provides first data (see Figure 25: SPI Fast Read Command).  The PROM must have enough bits to program the iCE65 device (see Table 27: Smallest SPI PROM Size (bits), by Device, by Number of Images).  The PROM must support data operations at the upper frequency range for the selected iCE65 internal oscillator frequency (see Table 57). The oscillator frequency is selectable when creating the FPGA bitstream image. (2.42, 30-MAR-2012) 30 Lattice Semiconductor Corporation www.latticesemi.com  For lowest possible power consumption after configuration, the PROM should also support the 0xB9 Deep Power Down command and the 0xAB Release from Deep Power-down Command (see Figure 24 and Figure 26). The low-power mode is optional.  The PROM must be ready to accept commands 10 µs after meeting its power-on conditions. In the PROM data sheet, this may be specified as tVSL or tVCSL. It is possible to use slower PROMs by holding the CRESET_B input Low until the PROM is ready, then releasing CRESET_B, either under program control or using an external power-on reset circuit. The Lattice iCEman65 development board and associated programming software uses an ST Micro/Numonyx M25Pxx SPI serial Flash PROM. SPI PROM Size Requirements Table 27 lists the minimum SPI PROM size required to configure an iCE65 device. Larger PROM sizes are allowed, but not required unless the end application uses the additional space. SPI serial PROM sizes are specified in bits. For each device size, the table shows the required minimum PROM size for “Logic Only” (no BRAM initialization) and “Logic + RAM4K” (RAM4K blocks pre-initialized). Furthermore, the table shows the PROM size for varying numbers of configuration images. Most applications will use a single image. Applications that use the Cold Boot or Warm Boot features may use more than one image. Device Table 27: Smallest SPI PROM Size (bits), by Device, by Number of Images 1 Image 2 Images 3 Images 4 Images Logic Logic + Logic Logic + Logic Logic + Logic Logic + Only RAM4K Only RAM4K Only RAM4K Only RAM4K iCE65L01 256K 256K 512K 512K 1M 1M 1M 1M iCE65L04 512K 1M 1M 2M 2M 2M 2M 4M iCE65L08 1M 2M 2M 4M 4M 4M 4M 8M Enabling SPI Configuration Interface To enable the SPI configuration mode, the SPI_SS_B pin must be allowed to float High. The SPI_SS_B pin has an internal pull-up resistor. If SPI_SS_B is Low, then the iCE65 component defaults to the SPI Slave configuration mode. SPI Master Configuration Process The iCE65 SPI Master Configuration Interface supports a variety of modern, high-density, low-cost SPI serial Flash PROMs. Most modern SPI PROMs include a power-saving Deep Power-down mode. The iCE65 component exploits this mode for additional system power savings. The iCE65 SPI interface starts by driving SPI_SS_B Low, and then sends a Release from Power-down command to the SPI PROM, hexadecimal command code 0xAB. Figure 24 provides an example waveform. This initial command wakes up the SPI PROM if it is already in Deep Power-down mode. If the PROM is not in Deep Power-down mode, the extra command has no adverse affect other than that it requires a few additional microseconds during the configuration process. The iCE65 device transmits data on the SPI_SO output, on the falling edge of the SPI_SCK output. The SPI PROM does not provide any data to the iCE65 device’s SPI_SI input. After sending the last command bit, the iCE65 device de-asserts SPI_SS_B High, completing the command. The iCE65 device then waits a minimum of 10 µS before sending the next SPI PROM command. Lattice Semiconductor Corporation www.latticesemi.com (2.42, 30-MAR-2011) 31 iCE65 Ultra Low-Power mobileFPGA™ Family Figure 24: SPI Release from Deep Power-down Command SPI_SCK SPI_SS_B SPI_SO 1 0 1 0 1 0 1 1 0xAB Release from Deep Power-down Figure 25 illustrates the next command issued by the iCE65 device. The iCE65 SPI interface again drives SPI_SS_B Low, followed by a Fast Read command, hexadecimal command code 0x0B, followed by a 24-bit start address, transmitted on the SPI_SO output. The iCE65 device provides data on the falling edge of SPI_SS_B. Upon initial power-up, the start address is always 0x00_0000. After waiting eight additional clock cycles, the iCE65 device begins reading serial data from the SPI PROM. Before presenting data, the SPI PROM’s serial data output is highimpedance. The SPI_SI input pin has an internal pull-up resistor and sees high-impedance as logic ‘1’. Figure 25: SPI Fast Read Command SPI_SCK SPI_SO 0 0 0 0 1 0 1 1 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 SPI_SS_B X X X X X X X X 0x0B 24-bit Start Address Don’t Care Dummy Byte Fast Read SPI_SI D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 PROM output is Hi-Z. Pulled High in SPI_SI pin via internal pull-up resistor. Data Byte 0 The external SPI PROM supplies data on the falling edge of the iCE65 device’s SPI_SCK clock output. The iCE65 device captures each PROM data value on the SPI_SI input, using the rising edge of the SPI_SCK clock signal. The SPI PROM data starts at the 24-bit address presented by the iCE65 device. PROM data is serially output, byte by byte, with most-significant bit, D7, presented first. The PROM automatically increments an internal byte counter as long as the PROM is selected and clocked. After transferring the required number configuration data bits, the iCE65 device ends the Fast Read command by de-asserting its SPI_SS_B PROM select output, as shown in Figure 26. To conserve power, the iCE65 device then optionally issues a final Deep Power-down command, hexadecimal command code 0xB9. After de-asserting the SPI_SS_B output, the SPI PROM enters its Deep Power-down mode. The final power-down step is optional; the application may use the SPI PROM and can skip this step, controlled by a configuration option. Figure 26: Final Configuration Data, SPI Deep Power-down Command SPI_SCK SPI_SS_B SPI_SO 1 0 1 1 1 0 0 1 0xB9 SPI_SI D7 D6 D5 D4 D3 D2 D1 D0 Deep Power-down Last Data Byte Fast Read data (2.42, 30-MAR-2012) 32 Lattice Semiconductor Corporation www.latticesemi.com Cold Boot Configuration Option By default, the iCE65 FPGA is programmed with a single configuration image, either from internal NVCM memory, from an external SPI Flash PROM, or externally from a processor or microcontroller. Figure 27: ColdBoot and WarmBoot Configuration At power-up or after reset CBSEL1 CBSEL0 CRESET_B Jump based on settings Cold Boot Control Cold/Warm Boot Applet 0 Enable/Disable Cold Boot Enable/Disable Warm Boot Jump vector addresses (4) Vector Address 0 Power-On Reset (0,0) Configuration Image 0 SB_WARMBOOT Vector Address 1 S1 S0 BOOT Warm Boot Control (0,1) Configuration Image 1 Vector Address 2 Controlled by currently loaded iCE65 application (1,0) Configuration Image 2 Vector Address 3 (1,1) Configuration Image 3 SPI PROM When self loading from NVCM or from an SPI Flash PROM, there is an additional configuration option called Cold Boot mode. When this option is enabled in the configuration bitstream, the iCE65 FPGA boots normally from power-on or a master reset (CRESET_B = Low pulse), but monitors the value on two PIO pins that are borrowed during configuration, as shown in Figure 27. These pins, labeled PIO2/CBSEL0 and PIO2/CBSEL1, tell the FPGA which of the four possible SPI configurations to load into the device. Table 30 provides the pin or ball locations for these pins.  Load from initial location, either from NVCM or from address 0 in SPI Flash PROM. For Cold Boot or Warm Boot applications, the initial configuration image contains the cold boot/warm boot applet.  Check if Cold Boot configuration feature is enabled in the bitstream.  If not enabled, FPGA configures normally.  If Cold Boot is enabled, then the FPGA reads the logic values on pins CBSEL[1:0]. The FPGA uses the value as a vector and then reads from the indicated vector address.  At the selected CBSEL[1:0] vector address, there is a starting address for the selected configuration image.  For SPI Flash PROMs, the new address is a 24-bit start address in Flash.  If the selected bitstream is in NVCM, then the address points to the internal NVCM.  Using the new start address, the FPGA restarts reading configuration memory from the new location. Lattice Semiconductor Corporation www.latticesemi.com (2.42, 30-MAR-2011) 33 iCE65 Ultra Low-Power mobileFPGA™ Family Table 28: ColdBoot Select Ball/Pin Numbers by Package ColdBoot Select PIO2/CBSEL0 PIO2/CBSEL1 CB81 G5 H5 QN84 B15 A20 VQ100 41 42 CB132 L9 P10 CB196 L9 P10 CB284 R13 V14 When creating the initial configuration image, the Lattice development software loads the start address for up to four configuration images in the bitstream. The value on the CBSEL[1:0] pins tell the configuration controller to read a specific start address, then to load the configuration image stored at the selected address. The multiple bitstreams are stored either in the SPI Flash or in the internal NVCM. After configuration, the CBSEL[1:0] pins become normal PIO pins available to the application. The Cold Boot feature allows the iCE65 to be reprogrammed for special application requirements such as the following.  A normal operating mode and a self-test or diagnostics mode.  Different applications based on switch settings.  Different applications based on a card-slot ID number. Warm Boot Configuration Option The Warm Boot configuration is similar to the Cold Boot feature, but is completely under the control of the FPGA application. A special design primitive, SB_WARMBOOT, allows an FPGA application to choose between four configuration images using two internal signal ports, S1 and S0, as shown in Figure 27. These internal signal ports connect to programmable interconnect, which in turn can connect to PLB logic and/or PIO pins. After selecting the desired configuration image, the application then asserts the internal signal BOOT port High to force the FPGA to restart the configuration process from the specified vector address stored in PROM. ! A Warm Boot application can only jump to another configuration image that DOES NOT have Warm Boot enabled. There is no such restriction for Cold Boot applications. Time-Out and Retry When configuring from external SPI Flash, the iCE65 device looks for a synchronization word. If the device does not find a synchronization word within its timeout period, the device automatically attempts to restart the configuration process from the very beginning. This feature is designed to address any potential power-sequencing issues that may occur between the iCE65 device and the external PROM. The iCE65 device attempts to reconfigure six times. If not successful after six attempts, the iCE65 FPGA automatically goes into low-power mode. SPI Peripheral Configuration Interface Using the SPI peripheral configuration interface, an application processor (AP) serially writes a configuration image to an iCE65 FPGA using the iCE65’s SPI interface, as shown in Figure 23. The iCE65’s SPI configuration interface is a separate, independent I/O bank, powered by the VCC_SPI supply input. Typically, VCC_SPI is the same voltage as the application processor’s I/O. The configuration control signals, CDONE and CRESET_B, are supplied by the separate I/O Bank 2 voltage input, VCCIO_2. This same SPI peripheral interface supports programming for the iCE65’s Nonvolatile Configuration Memory (NVCM). (2.42, 30-MAR-2012) 34 Lattice Semiconductor Corporation www.latticesemi.com Figure 28: iCE65 SPI Peripheral Configuration Interface AP_VCCIO VCCIO_2 VCCIO_2 10 kΩ AP_VCCIO 10 kΩ CDONE CRESET_B iCE65 (I/O Bank 2) SPI_VCC Application Processor SPI_SI SPI_SO SPI_SS_B iCE65 (SPI Bank) SPI_SCK 10 kΩ The SPI control signals are defined in Table 25. Table 29: SPI Peripheral Configuration Interface Pins (SPI_SS_B Low when CRESET_B Released) Signal Name CDONE Direction AP  iCE65 CRESET_B AP  iCE65 SPI_VCC SPI_SI SPI_SO Supply AP  iCE65 AP  iCE65 SPI_SS_B AP  iCE65 SPI_SCK AP  iCE65 iCE65 I/O Supply VCCIO_2 SPI_VCC Description Configuration Done output from iCE65. Connect to a 10kΩ pull-up resistor to the application processor I/O voltage, AP_VCC. Configuration Reset input on iCE65. Typically driven by AP using an open-drain driver, which also requires a 10kΩ pull-up resistor to VCCIO_2. SPI Flash PROM voltage supply input. SPI Serial Input to the iCE65 FPGA, driven by the application processor. SPI Serial Output from CE65 device to the application processor. Not actually used during SPI peripheral mode configuration but required if the SPI interface is also used to program the NVCM. SPI Slave Select output from the application processor. Active Low. Optionally hold Low prior to configuration using a 10kΩ pull-down resistor to ground. SPI Slave Clock output from the application processor. After configuration, the SPI port pins are available to the user-application as additional PIO pins, supplied by the SPI_VCC input voltage, essentially providing a fifth “mini” I/O bank. Enabling SPI Configuration Interface The optional 10 kΩ pull-down resistor on the SPI_SS_B signal ensures that the iCE65 FPGA powers up in the SPI peripheral mode. Optionally, the application processor drives the SPI_SS_B pin Low when CRESET_B is released, forcing the iCE65 FPGA into SPI peripheral mode. SPI Peripheral Configuration Process Figure 29 illustrates the interface timing for the SPI peripheral mode and Figure 30 outlines the resulting configuration process. The actual timing specifications appear in Table 60. The application processor (AP) begins by driving the iCE65 CRESET_B pin Low, resetting the iCE65 FPGA. Similarly, the AP holds the iCE65’s SPI_SS_B pin Low. The AP must hold the CRESET_B pin Low for at least 200 ns. Ultimately, the AP either releases the CRESET_B pin and allows it to float High via the 10 kΩ pull-up resistor to VCCIO_2 or drives CRESET_B High. The iCE65 FPGA enters SPI peripheral mode when the CRESET_B pin returns High while the SPI_SS_B pin is Low. Lattice Semiconductor Corporation www.latticesemi.com (2.42, 30-MAR-2011) 35 iCE65 Ultra Low-Power mobileFPGA™ Family After driving CRESET_B High or allowing it to float High, the AP must wait a minimum of tCR_SCK µs, (see Table 60) allowing the iCE65 FPGA to clear its internal configuration memory. After waiting for the configuration memory to clear, the AP sends the configuration image generated by the iCEcube development system. An SPI peripheral mode configuration image must not use the ColdBoot or WarmBoot options. Send the entire configuration image, without interruption, serially to the iCE65’s SPI_SI input on the falling edge of the SPI_SCK clock input. Once the AP sends the 0x7EAA997E synchronization pattern, the generated SPI_SCK clock frequency must be within the specified 1 MHz to 25 MHz range (40 ns to 1 µs clock period) while sending the configuration image. Send each byte of the configuration image with most-significant bit (msb) first. The AP sends data to the iCE65 FPGA on the falling edge of the SPI_SCK clock. The iCE65 FPGA internally captures each incoming SPI_SI data bit on the rising edge of the SPI_SCK clock. The iCE65’s SPI_SO output pin is not used during SPI peripheral mode but must connect to the AP if the AP also programs the iCE65’s Nonvolatile Configuration Memory (NVCM). ! Prior to sending the iCE65 configuration image , an SPI NVCM shut-off sequence must be sent. See AN014 for details. The iCE65 configuration image must be sent as one contiguous stream without interruption. The SPI_SCK clock period must be between 40 ns to 1 µs (1 MHz to 25 MHz). After sending the entire image, the iCE65 FPGA releases the CDONE output allowing it to float High via the 10 kΩ pull-up resistor to AP_VCC. If the CDONE pin remains Low, then an error occurred during configuration and the AP should handle the error accordingly for the application. After the CDONE output pin goes High, send at least 49 additional dummy bits, effectively 49 additional SPI_SCK clock cycles measured from rising-edge to rising-edge. After the additional SPI_CLK cycles, the SPI interface pins then become available to the user application loaded in FPGA. To reconfigure the iCE65 FPGA or to load a different configuration image, merely restart the configuration process by pulsing CRESET_B Low or power-cycling the FPGA. Figure 29: Application Processor Waveforms for SPI Peripheral Mode Configuration Process CDONE 49 SPI_SCK Cycles Rising edge to rising edge ≥ 200 ns CRESET_B iCE65L01: ≥ 800 µs iCE65L04: ≥ 800 µs iCE65L08: ≥ 1200 µs iCE65 enters SPI Peripheral mode with SPI_SS_B = Low on rising edge of CRESET_B SPI_SCK iCE65 captures SPI_SI data on SPI_SCK rising edge. SPI_SS_B D7 D6 D5 D4 D3 D2 D1 D0 SPI_SI D7 D6 D5 D4 D3 D2 D1 D0 Configuration image always starts with 0x7EAA997E synchronization word. X X X Entire Configuration Images Send most-significant bit of each byte first X X X Don’t Care 49 dummy bits Pulled High in SPI_SO pin via internal pull-up resistor. Not used for SPI Peripheral mode configuration. Used when programming NVCM via SPI itnterface. SPI_SO ! SPI Interface pins available as user-defined I/O pins iCE65 clears internal configuration memory The iCE65 configuration image must be sent as one contiguous stream without interruption. The SPI_SCK clock period must be between 40 ns to 1 µs (1 MHz to 25 MHz). (2.42, 30-MAR-2012) 36 Lattice Semiconductor Corporation www.latticesemi.com Figure 30: SPI Peripheral Configuration Process SPI Peripheral Configuration Drive CRESET_B = 0 Drive SPI_SS_B = 0, SPI_SCK = 1 Wait a minimum of 200 ns Release CRESET_B or drive CRESET_B = 1 Wait a minimum of iC65L01: 800 µs iC65L04: 800 µs iC65L08: 1200 µs to clear internal config. memory Send NVCM shut-off sequence Send configuration image serially on SPI_SI to iCE65, mostsignificant bit first, on falling edge of SPI_SCK. Send the entire image, without interruption. Ensure that SPI_SCK frequency is between 1 MHz and 25 MHz. CDONE = 1? NO ERROR! YES Send a minimum of 49 additional dummy bits and 49 additional SPI_SCK clock cycles (rising-edge to rising-edge) to active the user-I/O pins. SPI interface pins available as userdefined I/O pins in application Reconfigure? NO YES Voltage Compatibility As shown in Figure 23, there are potentially three different supply voltages involved in the SPI Peripheral interface, described in Table 30. Supply Voltage AP_VCCIO VCC_SPI VCCIO_2 Table 30: SPI Peripheral Mode Supply Voltages Description I/O supply to the Application Processor (AP) Voltage supply for the iCE65 SPI interface. Supply voltage for the iCE65 I/O Bank 2. Lattice Semiconductor Corporation www.latticesemi.com (2.42, 30-MAR-2011) 37 iCE65 Ultra Low-Power mobileFPGA™ Family Table 31 describes how to maintain voltage compatibility for two interface scenarios. The easiest interface is when the Application Processor’s (AP) I/O supply rail and the iCE65’s SPI and VCCIO_2 bank supply rails all connect to the same voltage. The second scenario is when the AP’s I/O supply voltage is greater than the iCE65’s VCCIO_2 supply voltage. Condition Table 31: CRESET_B and CDONE Voltage Compatibility CRESET_B OpenCDONE PullDirect Drain Pull-up up Requirement VCCIO_AP = VCC_SPI OK OK with pull-up Required if using open-drain output Recommended AP can directly drive CRESET_B High and Low although an open-drain output recommended is if multiple devices control CRESET_B. If using an open-drain driver, the CRESET_B input must include a 10 kΩ pull-up resistor to VCCIO_2. The 10 kΩ pull-up resistor to AP_VCCIO is also recommended. N/A Required, requires pull-up Required Required The AP must control CRESET_B with an open-drain output, which requires a 10 kΩ pull-up resistor to VCCIO_2. The 10 kΩ pull-up resistor to AP_VCCIO is required. VCCIO_AP = VCCIO_2 AP_VCCIO > VCCIO_2 JTAG Boundary Scan Port Overview Each iCE65 device includes an IEEE 1149.1-compatible JTAG boundary-scan port. The port supports printed-circuit board (PCB) testing and debugging. It also provides an alternate means to configure the iCE65 device. Signal Connections The JTAG port connections are listed in Table 32. Table 32: iCE65 JTAG Boundary Scan Signals Signal Name TDI TMS TCK TDO TRST_B Direction Input Input Input Output Input Description Test Data Input. Must be tied off to GND when unused. (no pull-up resistor)* Test Mode Select. Must be tied off to GND when unused. (no pull-up resistor)* Test Clock. Must be tied off to GND when unused. (no pull-up resistor)* Test Data Output. Test Reset, active Low. Must be Low during normal device operation. Must be High to enable JTAG operations.* * Must be tied off to GND or VCCIO_1, else VCCIO_1 draws current. Table 33 lists the ball/pin numbers for the JTAG interface by package code. The JTAG interface is available in select package types. The JTAG port is located in I/O Bank 1 along the right edge of the iCE65 device and powered by the VCCIO_1 supply inputs. Consequently, the JTAG interface uses the associated I/O standards for I/O Bank 1. Table 33: JTAG Interface Ball/Pin Numbers by Package JTAG Interface VQ100 TDI TMS TCK TDO TRST_B N/A (2.42, 30-MAR-2012) 38 CB132 M12 P14 L12 N14 M14 CB196 M12 P14 L12 N14 M14 CB284 T16 V18 R16 U18 T18 Lattice Semiconductor Corporation www.latticesemi.com Supported JTAG Commands The JTAG interface supports the IEEE 1149.1 mandatory instructions, including EXTEST, SAMPLE/PRELOAD, and BYPASS. Package and Pinout Information Maximum User I/O Pins by Package and by I/O Bank Table 34 lists the maximum number of user-programmable I/O pins by package, with additional detail showing user I/O pins by I/O bank. In some cases, a smaller iCE65 device is packaged in a larger package with unconnected (N.C.) pins or balls, resulting in fewer overall I/O pins. See Table 35 for device-specific I/O counts by package. Table 34: User I/O by Package, by I/O Bank Package Leads Package Body (mm) Ball Array (balls) Ball/Lead Pitch (mm) Maximum user I/O, all I/O banks PIO Pins in Bank 0 PIO Pins in Bank 1 PIO Pins in Bank 2 PIO Pins in Bank 3 PIO Pins in SPI Interface CB81 81 5x5 9x9 0.5 QN84 84 7x7 N/A 0.5 VQ100 100 14 x 14 N/A 0.5 CB132 132 8x8 14 x 14 0.5 CB196 196 8x8 14 x 14 0.5 CB284 284 12 x 12 22 x 22 0.5 63 67 72 95 150 222 17 16 12 18 17 17 11 18 19 19 12 18 26 21 20 24 37 38 35 36 60 55 53 50 4 4 4 4 4 4 Printed Circuit Board Layout Information For information on how to use the iCE65 packages on a printed circuit board (PCB) design, consult the following application note.  AN010: iCE65 Printed Circuit Board (PCB Layout) Guidelines Maximum User I/O by Device and Package Table 35 lists the maximum available user I/O by device and by and package type. Not all devices are available in all packages. Similarly, smaller iCE65 devices may have unconnected balls in some packages. Devices sharing a common package have similar footprints. Package CB81 QN84 VQ100 CB132 CB196 CB284 Table 35: Maximum User I/O by Device and Package Device iCE65L01 iCE65L04 63 67 72 93 — — Lattice Semiconductor Corporation www.latticesemi.com — — 72 95 150 176 iCE65L08 — — — 150 222 (2.42, 30-MAR-2011) 39 iCE65 Ultra Low-Power mobileFPGA™ Family iCE65 Pin Descriptions Table 36 lists the various iCE65 pins, alphabetically by name. The table indicates the directionality of the signal and the associated I/O bank. The table also indicates if the signal has an internal pull-up resistor enabled during configuration. Finally, the table describes the function of the pin. Signal Name CDONE CRESET_B GBIN0/PIO0 GBIN1/PIO0 GBIN2/PIO1 GBIN3/PIO1 GBIN4/PIO2 GBIN5/PIO2 Direction Output Input Input/IO Input/IO Input/IO GBIN6/PIO3 Input/IO GBIN7/PIO3 Input/IO GND PIOx_yy Supply I/O PIO2/CBSEL0 Input/IO PIO2/CBSEL1 Input/IO PIO3_yy/ DPwwz I/O PIOS/SPI_SO PIOS /SPI_SI I/O I/O PIOS / SPI_SS_B I/O PIOS/ SPI_SCK I/O TDI (2.42, 30-MAR-2012) 40 Input Table 36: iCE65 Pin Description Pull-up I/O during Bank Config Description Configuration Done. Dedicated output. Includes a permanent weak pull-up resistor to VCCIO_2.. If driving external devices 2 Yes with CDONE output, connect a 10 kΩ pull-up resistor to VCCIO_2. Configuration Reset, active Low. Dedicated input. No internal 2 No pull-up resistor. Either actively drive externally or connect a 10 kΩ pull-up resistor to VCCIO_2. 0 Global buffer input from I/O Bank 0. Optionally, a full-featured Yes PIO pin. 1 Global buffer input from I/O Bank 1. Optionally, a full-featured Yes PIO pin. 2 Global buffer input from I/O Bank 2. Optionally, a full-featured Yes PIO pin. Global buffer input from I/O Bank 3. Optionally, a full-featured 3 No PIO pin. Global buffer input from I/O Bank 3. Optionally, a full-featured 3 No PIO pin. Optionally, a differential clock input using the associated differential input pin. All N/A Ground. All must be connected. Programmable I/O pin defined by the iCE65 configuration bitstream. The ‘x’ number specifies the I/O bank number in 0,1,2 Yes which the I/O pin resides. The “yy’ number specifies the I/O number in that bank. Optional ColdBoot configuration SELect input, if ColdBoot mode 2 Yes is enabled. A full-featured PIO pin after configuration. Optional ColdBoot configuration SELect input, if ColdBoot mode 2 Yes is enabled. A full-featured PIO pin after configuration. Programmable I/O pin that is also half of a differential I/O pair. Only available in I/O Bank 3. The “yy” number specifies the I/O 3 No number in that bank. The “ww” number indicates the differential I/O pair. The ‘z’ indicates the polarity of the pin in the differential pair. ‘A’=negative input. ‘B’=positive input. SPI Yes SPI Serial Output. A full-featured PIO pin after configuration. SPI Yes SPI Serial Input. A full-featured PIO pin after configuration. SPI Slave Select. Active Low. Includes an internal weak pull-up resistor to SPI_VCC during configuration. During configuration, the logic level sampled on this pin determines the configuration mode used by the iCE65 device, as shown in Figure 20. An SPI Yes input when sampled at the start of configuration. An input when in SPI Peripheral configuration mode (SPI_SS_B = Low). An output when in SPI Flash configuration mode. A full-featured PIO pin after configuration. SPI Slave Clock. An input when in SPI Peripheral configuration SPI Yes mode (SPI_SS_B = Low). An output when in SPI Flash configuration mode. A full-featured PIO pin after configuration. JTAG Test Data Input. If using the JTAG interface, use a 10kΩ 1 No pull-up resistor to VCCIO_1. Tie off to GND when unused. Lattice Semiconductor Corporation www.latticesemi.com Direction I/O Bank Pull-up during Config TMS Input 1 No TCK Input 1 No TDO Output 1 No TRST_B Input 1 No VCC Supply All N/A VCCIO_0 Supply 0 N/A VCCIO_1 Supply 1 N/A VCCIO_2 Supply 2 N/A VCCIO_3 Supply 3 N/A SPI_VCC Supply SPI N/A VPP_FAST Supply All N/A VPP_2V5 Supply All N/A 3 N/A Signal Name VREF Voltage Reference Description JTAG Test Mode Select. If using the JTAG interface, use a 10kΩ pull-up resistor to VCCIO_1. Tie off to GND when unused. JTAG Test Clock. If using the JTAG interface, use a 10kΩ pullup resistor to VCCIO_1. Tie off to GND when unused. JTAG Test Data Output. JTAG Test Reset, active Low. Keep Low during normal operation; High for JTAG operation. Internal core voltage supply. All must be connected. Voltage supply to I/O Bank 0. All such pins or balls on the package must be connected. Can be disconnected or turned off without affecting the Power-On Reset (POR) circuit. Voltage supply to I/O Bank 1. All such pins or balls on the package must be connected. Required to guarantee a valid input voltage on TRST_B JTAG pin. Voltage supply to I/O Bank 2. All such pins or balls on the package must be connected. Required input to the Power-On Reset (POR) circuit. Voltage supply to I/O Bank 3. All such pins or balls on the package must be connected. Can be disconnected or turned off without affecting the Power-On Reset (POR) circuit. SPI interface voltage supply input. Must have a valid voltage even if configuring from NVCM. Required input to the Power-On Reset (POR) circuit. Direct programming voltage supply. If unused, leave floating or unconnected during normal operation. Programming supply voltage. When the iCE65 device is active, VPP_2V5 must be in the valid range between 2.3 V to 3.47 V to release the Power-On Reset circuit, even if the application is not using the NVCM. Input reference voltage in I/O Bank 3 for the SSTL I/O standard. This pin only appears on the CB284 package and for die-based products. N/A = Not Applicable iCE65 Package Footprint Diagram Conventions Figure 31 illustrates the naming conventions used in the following footprint diagrams. Each PIO pin is associated with an I/O Bank. PIO pins in I/O Bank 3 that support differential inputs are also numbered by differential input pair. Figure 31: CB Package Footprint Diagram Conventions 1 Ball row number Ball column number Single-ended PIO Numbering A PIO0 PIO0 Ball number A1 I/O bank number B PIO3/ DP07A C PIO3/ DP07B Differential Input Pair Indicators Lattice Semiconductor Corporation www.latticesemi.com Differential Input Pair Numbering PIO0/ DP07A Pair pin polarity Pair number Differential Pair Dot indicates unconnected pin for iCE65L04 in CB284 package (2.42, 30-MAR-2011) 41 iCE65 Ultra Low-Power mobileFPGA™ Family CB81 Chip-Scale Ball-Grid Array The CB81 package is a full ball grid array with 0.5 mm ball pitch. The iCE65L01 device is available in this package. Footprint Diagram Figure 32 shows the iCE65 footprint diagram for the CB81 package. Figure 31 shows the conventions used in the diagram. Also see Table 37 for a complete, detailed pinout for the 81-ball BGA package. The signal pins are also grouped into the four I/O Banks and the SPI interface. Figure 32: iCE65L01 CB81 Chip-Scale BGA Footprint (Top View) 2 3 I/O Bank 3 GND PIO0 PIO0 VCCIO_0 8 9 PIO0 PIO0 GND A B PIO3 PIO3 PIO3 PIO0 PIO0 PIO0 PIO0 PIO0 VPP_ 2V5 B C PIO3 PIO3 PIO3 PIO0 PIO0 PIO0 PIO1 PIO1 PIO1 C D E F G H J GBIN7 GBIN1 PIO3 PIO3 PIO3 PIO0 PIO1 PIO1 VCCIO_1 /PIO3 /PIO0 GBIN6 PIO3 PIO3 GND GND PIO0 PIO1 PIO1 PIO1 /PIO3 PIO3 GND PIO1 GBIN2 GBIN3 PIO3 PIO3 GND /PIO1 /PIO1 PIO2/ PIO1 PIO1 PIO1 PIO3 PIO3 PIO2 PIO2 SEL0 GBIN5 PIO2/ CDONE PIOS/ PIOS/ PIO3 PIO3 PIO2 SPI_SO SPI_SS_B /PIO2 SEL1 GBIN4 VCCIO_2 VCC CRESET_B PIOS/ PIOS/ GND PIO2 SPI_SI SPI_SCK /PIO2 VCCIO_3 1 (2.42, 30-MAR-2012) 42 GBIN0 PIO0 VCC /PIO0 7 2 3 4 5 6 I/O Bank 2 7 8 D E PIO1 F PIO1 G SPI_ VCC H GND J I/O Bank 1 1 I/O Bank 0 4 5 6 9 Lattice Semiconductor Corporation www.latticesemi.com Pinout Table Table 37 provides a detailed pinout table for the CB81 package. Pins are generally arranged by I/O bank, then by ball function. Table 37: iCE65 CB81 Chip-scale BGA Pinout Table Ball Function PIO0 PIO0 GBIN0/PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 GBIN1/PIO0 PIO0 VCCIO_0 Ball Number A2 A3 A4 A7 A8 B4 B5 B6 B7 B8 C4 C5 C6 D4 D5 D6 E6 A6 Pin Type PIO PIO GBIN PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO GBIN PIO VCCIO Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 GBIN2/PIO1 GBIN3/PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 VCCIO_1 C7 C8 C9 D7 D8 E7 E8 E9 F6 F7 F8 F9 G6 G7 G8 G9 D9 PIO PIO PIO PIO PIO PIO PIO PIO PIO GBIN GBIN PIO PIO PIO PIO PIO VCCIO 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CDONE CRESET_B PIO2 PIO2 PIO2/CBSEL0 PIO2 GBIN5/PIO2 PIO2/CBSEL1 PIO2 GBIN4/PIO2 VCCIO_2 H6 J6 G3 G4 G5 H3 H4 H5 J2 J3 J4 CONFIG CONFIG PIO PIO PIO PIO PIO PIO PIO PIO PIO 2 2 2 2 2 2 2 2 2 2 2 Lattice Semiconductor Corporation www.latticesemi.com (2.42, 30-MAR-2011) 43 iCE65 Ultra Low-Power mobileFPGA™ Family Ball Function Ball Number Pin Type Bank PIO3 PIO3 PIO3 PIO3 PIO3 PIO3 GBIN7/PIO3 PIO3 PIO3 GBIN6/PIO3 PIO3 PIO3 PIO3 PIO3 PIO3 PIO3 PIO3 PIO3 VCCIO_3 B1 B2 B3 C1 C2 C3 D1 D2 D3 E1 E2 E3 F2 F3 G1 G2 H1 H2 F1 PIO PIO PIO PIO PIO PIO GBIN PIO PIO GBIN PIO PIO PIO PIO PIO PIO PIO PIO VCCIO 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 PIOS/SPI_SO PIOS/SPI_SI PIOS/SPI_SCK PIOS/SPI_SS_B SPI_VCC H7 J7 J8 H8 H9 SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI GND GND GND GND GND GND GND GND VCC VCC A1 A9 J9 J1 E4 E5 F4 F5 A5 J5 GND GND GND GND GND GND GND GND VCC VCC GND GND GND GND GND GND GND GND VCC VCC VPP_2V5 B9 VPP VPP (2.42, 30-MAR-2012) 44 Lattice Semiconductor Corporation www.latticesemi.com Package Mechanical Drawing Figure 33: CB81 Package Mechanical Drawing CB81: 5 x 5 mm, 81-ball, 0.5 mm ball-pitch, chip-scale ball grid array Top View Bottom View A E F G H J C e D B SiliconBlue iCE65L01F-T CB81C NXXXX YYWW © CCCCC D D1 C A D B 1 2 3 4 5 6 7 8 9 9 8 7 6 5 4 3 2 1 Mark pin 1 dot E F G H J b e A A1 E1 E Side View Description Symbol Min. Nominal n E D e 4.90 4.90 — 9 9 81 5.00 5.00 0.50 5.10 5.10 — b E1 D1 A A1 0.2 — — — 0.15 — 4.00 4.00 — — 0.3 — — 1.00 0.25 Number of Ball Columns X Number of Ball Rows Y Number of Signal Balls X Body Size Y Ball Pitch Ball Diameter Edge Ball Center to Center Package Height Stand Off X Y Top Marking Format Line Content 1 Logo iCE65P01F 2 -T CB81C 3 ENG 4 NXXXX 5 YYWW 6 © CCCCCC Lattice Semiconductor Corporation www.latticesemi.com Description Logo Part number Power/Speed Package type Engineering Lot Number Date Code Country Max. Units Columns Rows Balls mm Thermal Resistance Junction-to-Ambient θ (⁰C/W) 0 LFM 200 LFM 67 57 (2.42, 30-MAR-2011) 45 iCE65 Ultra Low-Power mobileFPGA™ Family QN84 Quad Flat Pack No-Lead The QN84 is a Quad Flat Pack No-Lead package with a 0.5 mm pad pitch. Footprint Diagram Figure 34 shows the iCE65 footprint diagram for the QN84 package. Also see Table 38 for a complete, detailed pinout for the QN84 package. The signal pins are also grouped into the four I/O Banks and the SPI interface. PIO0 PIO0 PIO0 PIO0 PIO0 GBIN1/PIO0 VCCIO_0 PIO0 PIO0 PIO0 PIO0 VPP_FAST A47 A46 A45 A44 VCC A6 A7 GBIN7/PIO3 A8 GBIN6/PIO3 A9 A43 A42 A41 A40 A39 A38 A37 PIO3 B4 PIO3 B5 PIO3 B6 VCCIO_3 B7 PIO3 B8 PIO3 B9 PIO3 B15 PIO2/CBSELSEL0 B14 PIO2 B13 PIO2 B12 PIO2 B11 PIO2 VCC B28 PIO0 B29 A34 PIO1 A33 PIO1 A32 PIO1 PIO1 B24 PIO1 B23 A31 PIO1 A30 GND A29 GBIN3/PIO1 A28 VCC A27 PIO1 A26 PIO1 A25 PIO1 PIO1 B21 PIO1 B20 PIO1 B19 CRESET_B A21 PIO2/CBSEL1 A20 SPI Bank PIO2 A19 GND A18 VCCIO_2 A17 GBIN5/PIO2 A16 VCC A15 GBIN4/PIO2 A14 PIO2 A13 I/O Bank 2 (2.42, 30-MAR-2012) 46 PIO1 VCCIO_1 B25 GBIN2/PIO1 B22 B10 PIO2 PIO3 A12 PIO0 B30 PIO0 B31 SILICONBLUE iCE65L01F-T QN84 0948 PIO3 A10 PIO3 A11 A35 PIO1 B26 I/O Bank 1 GND I/O Bank 3 B3 VPP_2V5 SPI_VCC A24 A5 PIO3 PIOS/SPI_SCK A23 PIO3 B2 B18 PIOS/SPI_SS_B A4 B17 PIOS/SPI_SO PIO3 A36 PIO1 B27 PIOS/SPI_SI A22 A3 PIO3 B16 CDONE PIO3 GBIN0/PIO0 B32 B1 GND B33 A2 PIO0 B34 PIO3 I/O Bank 0 PIO0 B35 A1 PIO0 B36 PIO3 A48 Figure 34: iCE65 QN84 Quad Flat Pack No-Lead Footprint (Top View) Lattice Semiconductor Corporation www.latticesemi.com Pinout Table Table 38 provides a detailed pinout table for the QN84 package. Pins are generally arranged by I/O bank, then by ball function. The QN84 package has no JTAG pins. Table 38: iCE65 QN84 Chip-scale BGA Pinout Table Ball Function GBIN0/PIO0 GBIN1/PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 VCCIO_0 Ball Number B32 A43 A38 A39 A40 A41 A44 A45 A46 A47 A48 B29 B30 B31 B34 B35 B36 A42 Pin Type GBIN GBIN PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO VCCIO Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GBIN2/PIO1 GBIN3/PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 VCCIO_1 B22 A29 A25 A26 A27 A31 A32 A33 A34 A35 B19 B20 B21 B23 B24 B26 B27 B25 GBIN GBIN PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO VCCIO 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CDONE CRESET_B GBIN4/PIO2 GBIN5/PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 B16 A21 A14 A16 A13 B12 A19 B10 B11 B13 CONFIG CONFIG GBIN GBIN PIO PIO PIO PIO PIO PIO 2 2 2 2 2 2 2 2 2 2 Lattice Semiconductor Corporation www.latticesemi.com (2.42, 30-MAR-2011) 47 iCE65 Ultra Low-Power mobileFPGA™ Family Ball Function PIO2 PIO2/CBSEL0 PIO2/CBSEL1 VCCIO_2 Ball Number B14 B15 A20 A17 Pin Type PIO PIO PIO PIO Bank 2 2 2 2 GBIN6/PIO3 GBIN7/PIO3 PIO3 PIO3 PIO3 PIO3 PIO3 PIO3 PIO3 PIO3 PIO3 PIO3 PIO3 PIO3 PIO3 PIO3 PIO3 PIO3 VCCIO_3 A9 A8 A1 A2 A3 A4 A5 A10 A11 A12 B1 B2 B3 B4 B5 B7 B8 B9 B6 GBIN GBIN PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO VCCIO 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 PIOS/SPI_SO PIOS/SPI_SI PIOS/SPI_SCK PIOS/SPI_SS_B SPI_VCC B17 A22 A23 B18 A24 SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI GND GND GND GND VCC VCC VCC VCC A6 A18 A30 B33 A7 A15 A28 B28 GND GND GND GND VCC VCC VCC VCC GND GND GND GND VCC VCC VCC VCC VPP_2V5 VPP_FAST A36 A37 VPP VPP VPP VPP (2.42, 30-MAR-2012) 48 Lattice Semiconductor Corporation www.latticesemi.com Package Mechanical Drawing Figure 35: QN84 Package Mechanical Drawing Top View Bottom View Underside metal is at ground potential 7.00 Mark pin 1 dot A48 A47 A46 A45 A44 A43 A42 A41 A40 A39 A38 A37 A1 B36 B35 B34 B33 B32 B31 B30 B29 B28 A36 A35 A2 B27 B1 B26 B2 A34 A3 A33 A4 4.40 0.10 B25 B3 A32 iCE65L01F-T QN84C NXXXXXXX YYWW © CCCCCC A5 B24 B4 B23 B5 7.00 A31 A6 A7 4.40 0.10 A30 B22 A29 B21 A28 B6 A8 B7 A9 B20 B8 B19 B9 A27 A10 A26 0.40 0.10 0.85 0.10 A13 0.50 A12 A14 A15 A16 A17 0.15 B10 B11 B12 A18 A19 A20 A21 0.50 B13 B14 B15 B16 A22 A23 A24 Side View B17 B18 A25 A11 0.65 0.22 0.05 Notes: 1. All dimensions are in millimeters Top Marking Format Line Content 1 Logo iCE65L01F 2 -T QN84C 3 ENG 4 NXXXXXXX 5 YYWW 6 © CCCCCC Lattice Semiconductor Corporation www.latticesemi.com Description Logo Part number Power/Speed Package type Engineering Lot Number Date Code Country Thermal Resistance Junction-to-Ambient * θ (⁰C/W) 0 LFM 200 LFM 45 44 * With PCB thermal vias (2.42, 30-MAR-2011) 49 iCE65 Ultra Low-Power mobileFPGA™ Family VQ100 Very-thin Quad Flat Package The VQ100 package is a very-thin quad-flat package with 0.5 mm lead pitch. The iCE65L01 and iCE65L04 devices are available in this package. Footprint Diagram Figure 36 shows the footprint diagram for the 100-lead very-thin quad-flat package (VQ100). See Table 40 for a complete, detailed pinout for the 100-lead very-thin quad-flat package. The signal pins are also grouped into the four I/O Banks and the SPI interface. PIO3/DP00A 1 PIO3/DP00B PIO3/DP01A PIO3/DP01B 2 GND VCCIO_3 PIO3/DP02A 5 PIO3/DP02B PIO3/DP03A PIO3/DP03B 8 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 PIO0 GND PIO0 PIO0 PIO0 PIO0 PIO0 VCCIO_0 PIO0 GBIN0/PIO0 GBIN1/PIO0 VCCIO_0 PIO0 PIO0 PIO0 GND PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 VCC VPP_FAST 98 I/O Bank 0 3 Pin 1 indicator 70 SiliconBlue 9 69 68 67 10 I/O Bank 1 iCE65L04F-L VQ100 65 64 PIO1 GND PIO1 PIO1 VCCIO_1 PIO1 PIO1 PIO1 63 GBIN2/PIO1 62 GBIN3/PIO1 61 VCC 60 PIO1 17 59 PIO3/DP06A PIO3/DP06B 18 58 19 57 PIO1 VCCIO_1 PIO1 PIO3/DP07A PIO3/DP07B VCCIO_3 20 56 21 55 22 54 GND 23 53 PIO3/DP08A 24 52 51 PIO1 PIO1 PIO1 50 49 48 47 46 45 44 43 42 41 40 39 38 32 31 30 29 28 27 SPI Bank PIO1 GND PIO1 PIO2 PIO2 PIO2 PIO2 PIO2 VCCIO_2 GND GBIN5/ PIO2 (GBIN4/PIO2) (PIO2) GBIN4/PIO2 VCC (GBIN5/PIO2)PIO2 PIO2 VCCIO_2 GND PIO2 PIO2/CBSEL0 PIO2/CBSEL1 CDONE CRESET_B PIOS/SPI_SO PIOS/SPI_SI GND PIOS/SPI_SCK PIOS/SPI_SS_B SPI_VCC 37 I/O Bank 2 25 26 PIO3/DP08B 36 GND 35 16 34 PIO3/DP05B 33 GBIN6/PIO3/DP05A 15 66 I/O Bank 3 14 PIO1 PIO1 PIO1 71 R 7 13 VPP_2V5 74 72 6 12 75 73 4 VCC 11 PIO3/DP04A GBIN7/PIO3/DP04B VCCIO_3 99 100 PIO0 Figure 36: iCE65 VQ100 Footprint (Top View) (L01 only, only,see seeTable Table40) 39) (L01 Pinout Table Table 39 provides a detailed pinout table for the VQ100 package. Pins are generally arranged by I/O bank, then by pin function. The table also highlights the differential I/O pairs in I/O Bank 3. The VQ100 package has no JTAG pins. (2.42, 30-MAR-2012) 50 Lattice Semiconductor Corporation www.latticesemi.com Table 39: iCE65 VQ100 Pinout Table Pin Function Pin Number Type Bank GBIN0/PIO0 GBIN1/PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 VCCIO_0 VCCIO_0 90 89 78 79 80 81 82 83 85 86 87 91 93 94 95 96 97 99 100 88 92 GBIN GBIN PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO VCCIO VCCIO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GBIN2/PIO1 GBIN3/PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 VCCIO_1 VCCIO_1 63 62 51 52 53 54 56 57 59 60 64 65 66 68 69 71 72 73 74 58 67 GBIN GBIN PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO VCCIO VCCIO 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CONFIG CONFIG GBIN 2 2 2 GBIN 2 PIO PIO 2 2 CDONE CRESET_B GBIN4/PIO2 GBIN5/PIO2 PIO2 PIO2 Lattice Semiconductor Corporation www.latticesemi.com 43 44 iCE65L01: iCE65L04: iCE65L01: iCE65L04: 26 27 33 34 36 33 (2.42, 30-MAR-2011) 51 iCE65 Ultra Low-Power mobileFPGA™ Family Pin Function Pin Number Type Bank PIO2 PIO2 PIO2 PIO2 PIO PIO PIO PIO 2 2 2 2 PIO2 PIO2 PIO2/CBSEL0 PIO2/CBSEL1 VCCIO_2 VCCIO_2 28 29 30 iCE65L01: 34 iCE65L04: 36 37 40 41 42 31 38 PIO PIO PIO PIO VCCIO VCCIO 2 2 2 2 2 2 PIO3/DP00A PIO3/DP00B 1 2 PIO/DPIO PIO/DPIO 3 3 PIO3/DP01A PIO3/DP01B 3 4 PIO/DPIO PIO/DPIO 3 3 PIO3/DP02A PIO3/DP02B 7 8 PIO/DPIO PIO/DPIO 3 3 PIO3/DP03A PIO3/DP03B 9 10 PIO/DPIO PIO/DPIO 3 3 PIO3/DP04A GBIN7/PIO3/DP04B 12 13 PIO/DPIO GBIN/DPIO 3 3 GBIN6/PIO3/DP05A 15 GBIN/DPIO 3 PIO3/DP05B 16 PIO/DPIO 3 PIO3/DP06A PIO3/DP06B 18 19 PIO/DPIO PIO/DPIO 3 3 PIO3/DP07A PIO3/DP07B 20 21 PIO/DPIO PIO/DPIO 3 3 PIO3/DP08A PIO3/DP08B 24 25 PIO/DPIO PIO/DPIO 3 3 VCCIO_3 VCCIO_3 VCCIO_3 6 14 22 VCCIO VCCIO VCCIO 3 3 3 PIOS/SPI_SO PIOS/SPI_SI PIOS/SPI_SCK PIOS/SPI_SS_B SPI_VCC 45 46 48 49 50 SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI GND GND GND GND GND GND GND GND GND GND 5 17 23 32 39 47 55 70 84 98 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC VCC 11 35 VCC VCC VCC VCC (2.42, 30-MAR-2012) 52 Lattice Semiconductor Corporation www.latticesemi.com Pin Function Pin Number Type Bank VCC VCC 61 77 VCC VCC VCC VCC VPP_2V5 VPP_FAST 75 76 VPP VPP VPP VPP Package Mechanical Drawing Figure 37: VQ100 Package Mechanical Drawing: Standard Device Marking Top View Mark pin 1 dot 100 76 1 e 75 b iCE65L01F-T ENG VQ100C NXXXXXXX YYWW D2 D D1 Pin 1 indicator © CCCCCC 25 26 50 51 E2 E1 E Side View Description Leads per Edge Symbol Maximum Size (lead tip to lead tip) Body Size Edge Pin Center to Center Lead Pitch Lead Width Total Package Height Stand Off Body Thickness Lead Length Lead Thickness Coplanarity Min. Nominal — — — — — — — 0.17 — 0.05 0.95 — 0.09 — 25 25 100 16.0 16.0 14.0 14.0 12.0 12.0 0.50 0.20 1.20 — 1.00 1.00 — 0.08 X Y Number of Signal Leads X Y X Y X Y n E D E1 D1 E2 D2 e b A A1 A2 L1 c Lattice Semiconductor Corporation www.latticesemi.com A1 L1 A A2 c Max. Units Leads — — — — — — — 0.27 — 0.15 1.05 — 0.20 — mm Top Marking Format Line Content 1 Logo iCE65L01F 2 -T ENG 3 VQ100C NXXXXXXX 4 YYWW 5 N/A 6 © CCCCCC Description Logo Part number Power/Speed Engineering Package type and Lot number Date Code Blank Country Thermal Resistance Junction-to-Ambient θ (⁰C/W) 0 LFM 200 LFM 38 32 (2.42, 30-MAR-2011) 53 iCE65 Ultra Low-Power mobileFPGA™ Family Figure 38: VQ100 Package Mechanical Drawing: NVCM Programmed Device Marking Top View Mark pin 1 dot 100 76 1 e 75 25 26 b iCE65L01F-T ENG VQ100C NXXXXXXX ZZZZZZZZ YYWW © CCCCCC D2 D D1 Pin 1 indicator 50 51 E2 E1 E Side View Description Leads per Edge Symbol Maximum Size (lead tip to lead tip) Body Size Edge Pin Center to Center Lead Pitch Lead Width Total Package Height Stand Off Body Thickness Lead Length Lead Thickness Coplanarity (2.42, 30-MAR-2012) 54 Min. Nominal — — — — — — — 0.17 — 0.05 0.95 — 0.09 — 25 25 100 16.0 16.0 14.0 14.0 12.0 12.0 0.50 0.20 1.20 — 1.00 1.00 — 0.08 X Y Number of Signal Leads X Y X Y X Y n E D E1 D1 E2 D2 e b A A1 A2 L1 c A1 L1 A A2 c Max. Units Top Marking Format Leads — — — — — — — 0.27 — 0.15 1.05 — 0.20 — mm Line Content 1 Logo iCE65L01F 2 -T ENG 3 VQ100C NXXXXXXX 4 ZZZZZZZZ 5 YYWW 6 © CCCCCC Description Logo Part number Power/Speed Engineering Package type and Lot number NVCM Program. code Date Code Country Thermal Resistance Junction-to-Ambient θ (⁰C/W) 0 LFM 200 LFM 38 32 Lattice Semiconductor Corporation www.latticesemi.com CB121 Chip-Scale Ball-Grid Array The CB121 package is a chip-scale, fully-populated, ball-grid array with 0.5 mm ball pitch. Footprint Diagram Figure 39 shows the iCE65L01 chip-scale BGA footprint for the 6 x 6 mm CB121 package. Also see Table 40 for a complete, detailed pinout for the 121-ball chip-scale BGA packages. The signal pins are also grouped into the four I/O Banks and the SPI interface. Figure 39: iCE65L01 CB121 Chip-Scale BGA Footprint (Top View) I/O Bank 0 I/O Bank 3 A VCCIO_3 2 3 4 5 6 7 8 9 10 11 PIO0 PIO0 PIO0 PIO0 PIO0 NC VPP_ PIO0 FAST PIO1 PIO1 VCCIO_0 PIO0 PIO0 GND PIO1 B VPP_ PIO1 2V5 C PIO0 PIO1 PIO1 PIO1 PIO1 D B PIO3 GND PIO0 PIO0 PIO0 VCC C PIO3 PIO3 PIO3 PIO3 PIO0 D PIO3 PIO3 GBIN7/ PIO3 PIO0 E GND PIO3 PIO3 F VCC PIO3 PIO3 G PIO3 VCCIO_3 H PIO3 J PIO3 GBIN1/ PIO0 GBIN0/ PIO0 PIO0 PIO0 PIO0 PIO3 PIO0 PIO0 PIO0 PIO1 PIO1 A PIO1 E GND GND PIO0 VCC PIO1 PIO1 PIO1 F PIO3 GND GND PIO1 PIO1 PIO1 PIO1 GND G PIO3 PIO2/ PIO1 PIO1 PIO1 PIO1 PIO2 PIO3 PIO2 PIO2 H PIO3 PIO3 SPI_ PIO3 PIO2 PIO2 PIO2/ CDONE PIOS/ PIOS/ CBSEL1 SPI_SO SPI_SS_B VCC PIO2 J K NC GND PIO2 PIO2 PIOS/ PIOS/ GND PIO2 K L NC PIO2 PIO2 PIO2 PIO2 1 PIO3 GBIN6/ PIO3 VCCIO_1 GBIN3/ GBIN2/ CBSEL0 2 3 VCC CRESET_B NC NC 4 5 6 I/O Bank 2 7 VCCIO_2 SPI_SI SPI_SCK GBIN4/ GBIN5/ PIO2 PIO2 PIO2 PIO2 I/O Bank 1 1 L 8 9 10 11 SPI Bank Pinout Table Table 40 provides a detailed pinout table for the iCE65L01 in the CB121 chip-scale BGA package. Pins are generally arranged by I/O bank, then by ball function. Table 40: iCE65L01 CB121 Chip-scale BGA Pinout Table Ball Function GBIN0/PIO0 GBIN1/PIO0 PIO0 PIO0 PIO0 Lattice Semiconductor Corporation www.latticesemi.com Ball Number D6 C6 A2 A3 A4 Pin Type GBIN GBIN PIO PIO PIO Bank 0 0 0 0 0 (2.42, 30-MAR-2011) 55 iCE65 Ultra Low-Power mobileFPGA™ Family Ball Function PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 VCCIO_0 Ball Number A5 A6 A8 A10 B3 B4 B5 B8 B9 C5 C7 C8 C9 D5 D7 E5 E6 E7 F7 B7 Pin Type PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO VCCIO Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GBIN2/PIO1 GBIN3/PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 VCCIO_1 F9 F8 A11 B11 C11 D8 D9 D10 D11 E8 E9 E11 F10 G7 G8 G9 G10 H7 H8 H9 H10 E10 GBIN GBIN PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO VCCIO 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CDONE CRESET_B GBIN4/PIO2 GBIN5/PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 J7 K7 L8 L9 H4 H5 H11 J4 J5 CONFIG CONFIG GBIN GBIN PIO PIO PIO PIO PIO 2 2 2 2 2 2 2 2 2 (2.42, 30-MAR-2012) 56 Lattice Semiconductor Corporation www.latticesemi.com Ball Function PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2/CBSEL0 PIO2/CBSEL1 VCCIO_2 Ball Number J11 K3 K4 K11 L2 L3 L4 L5 L10 L11 H6 J6 K5 Pin Type PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO VCCIO Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 PIO3 PIO3 PIO3 PIO3 PIO3 PIO3 PIO3 PIO3 PIO3 PIO3 PIO3 PIO3 PIO3 GBIN6/PIO3 GBIN7/PIO3 PIO3 PIO3 PIO3 PIO3 PIO3 PIO3 PIO3 PIO3 PIO3 VCCIO_3 VCCIO_3 C1 B1 D1 E2 C2 D2 C3 C4 E4 D4 F3 G3 G4 F4 D3 E3 F2 G1 H1 J1 H2 H3 J3 J2 A1 G2 PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO GBIN GBIN PIO PIO PIO PIO PIO PIO PIO PIO PIO VCCIO VCCIO 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 PIOS/SPI_SO PIOS/SPI_SI PIOS/SPI_SCK PIOS/SPI_SS_B SPI_VCC J8 K8 K9 J9 J10 SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI GND GND GND GND GND GND GND GND B2 B10 E1 F5 F6 G5 G6 G11 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Lattice Semiconductor Corporation www.latticesemi.com (2.42, 30-MAR-2011) 57 iCE65 Ultra Low-Power mobileFPGA™ Family Ball Function GND GND Ball Number K2 K10 Pin Type GND GND Bank GND GND VCC VCC VCC VCC B6 F1 F11 K6 VCC VCC VCC VCC VCC VCC VCC VCC VPP_2V5 VPP_FAST C10 A9 VPP VPP VPP VPP (2.42, 30-MAR-2012) 58 Lattice Semiconductor Corporation www.latticesemi.com Package Mechanical Drawing Figure 40: CB121 Package Mechanical Drawing CB121: 6 x 6 mm, 121-ball, 0.5 mm ball-pitch, fully-populated, chip-scale ball grid array Top View Bottom View 1 2 3 4 5 6 7 8 9 10 11 11 10 9 8 7 6 5 4 3 2 1 Mark pin 1 dot A A B B F G H J K C D e E SiliconBlue iCE65L01F-T CB121I NXXXX YYWW © CCCCC E F G D1 D D C H J K L L e E1 A A1 b Side View E Description Symbol Number of Ball Columns X Number of Ball Rows Y Number of Signal Balls X Body Size Y Ball Pitch Ball Diameter X Edge Ball Center to Center Y Package Height Stand Off n E D e b E1 D1 A A1 Top Marking Format Li ne Content 1 Logo i CE65L01F 2 -T CB121I 3 ENG 4 NXXXX 5 YYWW 6 © CCCCCC Lattice Semiconductor Corporation www.latticesemi.com Des cription Logo Pa rt number Power/Speed Pa cka ge type Engi neering LotNumber Da te Code Country Min. Nominal 5.90 5.90 — 0.2 — — — 0.12 11 11 121 6.00 6.00 0.50 — 5.00 5.00 — — Max. Units Columns Rows Balls 6.10 6.10 — 0.3 — — 1.00 0.20 mm Thermal Resistance Juncti on-to-Ambient θJA ( C/W) 0 LFM 200 LFM 64 55 (2.42, 30-MAR-2011) 59 iCE65 Ultra Low-Power mobileFPGA™ Family CB132 Chip-Scale Ball-Grid Array The CB132 package is a partially-populated ball grid array with 0.5 mm ball pitch. The empty ball rings simplify PCB layout. The iCE65L01, iCE65L04 and iCE65L08 devices are available in this package. Footprint Diagram Figure 41, Figure 42 and Figure 43 show the iCE65 footprint diagrams for the CB132 package in iCE65L01, iCE65L04 and iCE65L08 devices. See Figure 48 for the “universal” chip-scale BGA footprint for the CB132 and CB284 packages. The 8 x 8 mm CB132 package fits within the same ball pattern as the 12 x 12 mm CB284 package. Figure 31 shows the conventions used in the diagram. Also see Table 41 for a complete, detailed pinout for the 132-ball BGA package. The signal pins are also grouped into the four I/O Banks and the SPI interface. Figure 41: iCE65L01 CB132 Chip-Scale BGA Footprint (Top View) I/O Bank 0 2 I/O Bank 3 PIO0 PIO0 3 NC 4 5 PIO0 PIO0 6 7 GBIN1/ GBIN0/ PIO0 PIO0 8 VCCIO_0 9 10 11 12 13 14 GND PIO0 NC VPP_ VPP_ 2V5 A PIO1 B PIO0 FAST B PIO3 C PIO3 PIO3 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO1 C D PIO3 PIO3 PIO3 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO1 PIO1 D E PIO3 VCCIO_3 PIO3 PIO1 PIO1 PIO1 E F GND PIO3 PIO3 PIO3 PIO3 VCC GND GND GND PIO1 PIO1 PIO3 PIO3 PIO3 GND GND GND VCC PIO1 PIO1 VCCIO_1 H PIO3 PIO3 VCC VCC GND PIO1 PIO1 GND J PIO3 PIO3 PIO1 PIO1 PIO1 K GBIN7/ G PIO3 H J GBIN6/ K VCCIO_3 VCCIO_0 VCCIO_3 GND VCC PIO1 PIO1 VCCIO_1 VCCIO_2 GBIN3/ PIO1 GBIN2/ PIO1 F G L PIO3 SPI_ GND PIO2 PIO2 PIO2 PIO2 PIO2 PIO2/ CRESET_B VCC TCK PIO1 L M PIO3 PIO2 PIO2 PIOS/ TDI SPI_SO TRST_B M N PIO3 TDO N P PIO3 PIO2 PIO2 PIO2 PIO2 GND PIOS/ PIOS/ TMS PIO2 PIO2/ PIOS/ SPI_SI SPI_SCK SPI_SS_B P 1 (2.42, 30-MAR-2012) 60 CBSEL0 VCCIO_2 PIO2 PIO2 PIO2 PIO2 CDONE SPI Bank 2 3 4 5 6 GBIN5/ GBIN4/ PIO2 PIO2 7 8 9 I/O Bank 2 CBSEL1 I/O Bank 1 1 10 11 12 13 14 Lattice Semiconductor Corporation www.latticesemi.com Figure 42: iCE65L04 CB132 Chip-Scale BGA Footprint (Top View) I/O Bank 0 2 3 4 5 PIO0 PIO0 PIO0 PIO0 PIO0 6 7 GBIN0/ GBIN1/ PIO0 PIO0 8 VCCIO_0 9 10 11 12 13 14 VPP_ VPP_ 2V5 A PIO1 B GND PIO0 PIO0 PIO0 FAST PIO3/ B DP00A PIO3/ C DP00B PIO3/ PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 DP01A PIO1 C PIO3/ D DP03A PIO3/ PIO3/ PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO1 DP01B DP02A PIO1 D PIO3/ E DP03B VCCIO_3 PIO1 E PIO1 PIO1 GBIN3/ GND PIO3/ PIO3/ DP04B DP04A GBIN7/ PIO3/ PIO3/ DP05A DP05B VCC GND GND GND PIO1 PIO1 PIO3 PIO3/ PIO3/ DP06A DP06B GND GND GND VCC PIO1 PIO1 VCCIO_1 H PIO3/ DP07B PIO3/ VCC DP07A VCC GND PIO1 PIO1 GND J K VCCIO_3 PIO3/ PIO3/ DP08A DP08B PIO1 PIO1 PIO1 K SPI_ GND PIO2 PIO2 PIO2 PIO2 PIO2 PIO2/ CRESET_B VCC TCK PIO1 L PIOS/ TDI SPI_SO TRST_B M TDO N PIOS/ PIOS/ TMS PIO2 PIO2/ PIOS/ SPI_SI SPI_SCK SPI_SS_B P F I/O Bank 3 PIO3/ DP02B G PIO3 H J L GBIN6/ PIO3/ DP09A VCCIO_0 VCCIO_3 GND VCC PIO1 PIO1 VCCIO_1 VCCIO_2 CBSEL0 PIO3/ M DP09B PIO2 PIO2 VCCIO_2 PIO2 PIO2 PIO2 PIO2 CDONE PIO3/ N DP10A PIO3/ P DP10B 1 SPI Bank PIO2 PIO2 PIO2 PIO2 GND 2 3 4 Lattice Semiconductor Corporation www.latticesemi.com 5 6 GBIN5/ GBIN4/ PIO2 PIO2 7 8 9 I/O Bank 2 PIO1 GBIN2/ PIO1 CBSEL1 F G I/O Bank 1 1 10 11 12 13 14 (2.42, 30-MAR-2011) 61 iCE65 Ultra Low-Power mobileFPGA™ Family Figure 43: iCE65L08 CB132 Chip-Scale BGA Footprint (Top View) I/O Bank 0 2 3 4 5 PIO0 PIO0 PIO0 PIO0 PIO0 6 7 GBIN0/ GBIN1/ PIO0 PIO0 8 VCCIO_0 9 10 11 12 13 14 VPP_ VPP_ 2V5 A PIO1 B GND PIO0 PIO0 PIO0 FAST PIO3/ B DP00A PIO3/ C DP00B PIO3/ PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 DP01A PIO1 C PIO3/ D DP03A PIO3/ PIO3/ PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO1 DP01B DP02A PIO1 D PIO3/ E DP03B VCCIO_3 PIO1 E PIO1 PIO1 GBIN3/ GND PIO3/ PIO3/ DP04B DP04A G GBIN7/ DP05B PIO3/ PIO3/ DP05A DP11B VCC GND GND GND PIO1 PIO1 H GBIN6/ DP06A PIO3/ PIO3/ DP06B DP11A GND GND GND VCC PIO1 PIO1 VCCIO_1 H PIO3/ DP07B PIO3/ VCC DP07A VCC GND PIO1 PIO1 GND J K VCCIO_3 PIO3/ PIO3/ DP08A DP08B PIO1 PIO1 PIO1 K SPI_ GND PIO2 PIO2 PIO2 PIO2 PIO2 PIO2/ CRESET_B VCC TCK PIO1 L PIOS/ TDI SPI_SO TRST_B M TDO N PIOS/ PIOS/ TMS PIO2 PIO2/ PIOS/ SPI_SI SPI_SCK SPI_SS_B P F I/O Bank 3 PIO3/ DP02B J L PIO3/ DP09A VCCIO_0 VCCIO_3 GND VCC PIO1 PIO1 VCCIO_1 VCCIO_2 CBSEL0 PIO3/ M DP09B PIO2 PIO2 VCCIO_2 PIO2 PIO2 PIO2 PIO2 CDONE PIO3/ N DP10A PIO3/ P DP10B SPI Bank PIO2 PIO2 PIO2 PIO2 GND 1 (2.42, 30-MAR-2012) 62 2 3 4 5 6 GBIN5/ GBIN4/ PIO2 PIO2 7 8 9 I/O Bank 2 PIO1 GBIN2/ PIO1 CBSEL1 F G I/O Bank 1 1 10 11 12 13 14 Lattice Semiconductor Corporation www.latticesemi.com Pinout Table Table 41 provides a detailed pinout table for the CB132 package. Pins are generally arranged by I/O bank, then by ball function. The table also highlights the differential I/O pairs in I/O Bank 3. Table 41: iCE65 CB132 Chip-scale BGA Pinout Table Ball Function GBIN0/PIO0 GBIN1/PIO0 PIO0 PIO0 iCE65L01: (NC) iCE65L04/L08: PIO0 PIO0 PIO0 PIO0 iCE65L01: (NC) iCE65L04/L08: PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 VCCIO_0 VCCIO_0 GBIN2/PIO1 GBIN3/PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 Lattice Semiconductor Corporation www.latticesemi.com Ball Number iCE65L01: A7 iCE65L04/L08: A6 iCE65L01: A6 iCE65L04/08: A7 A1 A2 A3 Pin Type GBIN Bank 0 GBIN 0 0 0 0 A12 C10 C11 C12 C4 C5 C6 C7 C8 C9 D5 D6 D7 D8 D9 D10 D11 A8 F6 PIO PIO iCE65L01: (NC) iCE65L04: PIO0 PIO PIO PIO iCE65L01: (NC) iCE65L04: PIO0 PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO VCCIO VCCIO G14 F14 B14 C14 D12 D14 E11 E12 E14 F11 F12 G11 G12 H11 GBIN GBIN PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A4 A5 A10 A11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (2.42, 30-MAR-2011) 63 iCE65 Ultra Low-Power mobileFPGA™ Family Ball Function PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 TCK TDI TDO TMS TRST_B VCCIO_1 VCCIO_1 Ball Number H12 J11 J12 K11 K12 K14 L14 L12 M12 N14 P14 M14 F9 H14 Pin Type PIO PIO PIO PIO PIO PIO PIO JTAG JTAG JTAG JTAG JTAG VCCIO VCCIO Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CDONE CRESET_B GBIN4/PIO2 GBIN5/PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2/CBSEL0 PIO2/CBSEL1 VCCIO_2 VCCIO_2 M10 L10 P8 P7 L4 L5 L6 L7 L8 M3 M4 M6 M7 M8 M9 P2 P3 P4 P5 P9 L9 P10 J9 M5 CONFIG CONFIG GBIN GBIN PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 PIO3/DP00A PIO3/DP00B B1 C1 DPIO DPIO 3 3 PIO3/DP01A PIO3/DP01B C3 D3 DPIO DPIO 3 3 PIO3/DP02A PIO3/DP02B D4 E4 DPIO DPIO 3 3 PIO3/DP03A PIO3/DP03B D1 E1 DPIO DPIO 3 3 PIO3/DP04A PIO3/DP04B F4 F3 DPIO DPIO 3 3 L01/L04: GBIN6/PIO3 L08: GBIN6/DP06A H1 GBIN 3 (2.42, 30-MAR-2012) 64 Lattice Semiconductor Corporation www.latticesemi.com Ball Function L01/L04: GBIN7/PIO3 L08: GBIN7/DP05B Ball Number G1 Pin Type GBIN Bank 3 L01/L04: PIO3/DP05A L08: PIO3/DP05A L01/L04: PIO3/DP05B L08: PIO3/DP11B G3 DPIO 3 G4 DPIO 3 L01/L04: PIO3/DP06A L08: PIO3/DP06B L01/L04: PIO3/DP06B L08: PIO3/DP11A H3 DPIO 3 H4 DPIO 3 PIO3/DP07A PIO3/DP07B J3 J1 DPIO DPIO 3 3 PIO3/DP08A PIO3/DP08B K3 K4 DPIO DPIO 3 3 PIO3/DP09A PIO3/DP09B L1 M1 DPIO DPIO 3 3 PIO3/DP10A PIO3/DP10B N1 P1 DPIO DPIO 3 3 VCCIO_3 VCCIO_3 VCCIO_3 E3 J6 K1 VCCIO VCCIO VCCIO 3 3 3 PIOS/SPI_SO PIOS/SPI_SI PIOS/SPI_SCK PIOS/SPI_SS_B SPI_VCC M11 P11 P12 P13 L11 SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI GND GND GND GND GND GND GND GND GND GND GND GND GND VCC VCC VCC VCC VCC A9 F1 F7 G7 G8 G9 H6 H7 H8 J8 J14 L3 P6 F8 G6 H9 J4 J7 GND GND GND GND GND GND GND GND GND GND GND GND GND VCC VCC VCC VCC VCC GND GND GND GND GND GND GND GND GND GND GND GND GND VCC VCC VCC VCC VCC VPP_2V5 VPP_FAST A14 A13 VPP VPP VPP VPP Lattice Semiconductor Corporation www.latticesemi.com (2.42, 30-MAR-2011) 65 iCE65 Ultra Low-Power mobileFPGA™ Family Package Mechanical Drawing Figure 44: CB132 Package Mechanical Drawing CB132: 8 x 8 mm, 132-ball, 0.5 mm ball-pitch, chip-scale ball grid array Top View Bottom View 1 2 3 4 5 6 7 8 9 10 11 12 13 14 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Mark pin 1 dot A B B C C D D e A E H J K L M N P iCE65L04F-T CB132C ENG NXXXXXXX YYWW © CCCCCC E F G D1 G D F H J K L M N P b e A A1 E1 Side View E Description Symbol Number of Ball Columns X Number of Ball Rows Y Number of Signal Balls X Body Size Y Ball Pitch Ball Diameter Edge Ball Center to Center Package Height Stand Off (2.42, 30-MAR-2012) 66 X Y Min. Nominal Max. n E D e 7.90 7.90 — 14 14 132 8.00 8.00 0.50 8.10 8.10 — b E1 D1 A A1 0.27 — — — 0.16 — 6.50 6.50 — — 0.37 — — 1.00 0.26 Top Marking Format Units Columns Rows Balls mm Line Content 1 Logo iCE65L04F 2 -T CB132C 3 ENG 4 NXXXXXXX 5 YYWW 6 © CCCCCC Description Logo Part number Power/Speed Package type Engineering Lot Number Date Code Country Thermal Resistance Junction-to-Ambient θ (⁰C/W) 0 LFM 200 LFM 42 34 Lattice Semiconductor Corporation www.latticesemi.com CB196 Chip-Scale Ball-Grid Array The CB196 package is a chip-scale, fully-populated, ball-grid array with 0.5 mm ball pitch. Footprint Diagram Figure 45 shows the iCE65L04 chip-scale BGA footprint for the 8 x 8 mm CB196 package. The footprint for the iCE65L08 is different than the iCE64L04 footprint, as shown in Figure 46. The pinout differences are highlighted by warning diamonds () in the footprint diagrams and summarized in Table 43. Although both the iCE65L04 and iCE65L08 are both available in the CB196 package and almost completely pin compatible, there are differences as shown in Table 43. ! Figure 31 shows the conventions used in the diagram. Also see Table 42 for a complete, detailed pinout for the 196ball chip-scale BGA packages. The signal pins are also grouped into the four I/O Banks and the SPI interface. Figure 45: iCE65L04 CB196 Chip-Scale BGA Footprint (Top View) 2 3 4 GBIN0/ 9 10 11 12 13 14 A PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 VPP_ VPP_ 2V5 A B PIO3/ PIO0 PIO0 PIO0 PIO0 PIO0 VCC PIO0 PIO0 PIO0 PIO0 GND PIO1 PIO1 DP00B B C PIO3/ PIO1/ GND DP01B PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO1 PIO1 PIO1 DP00A C D PIO3/ PIO3/ PIO1/ PIO3/ PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO1 PIO1 PIO1 PIO1 DP02A DP02B DP01A DP04A D E PIO3/ PIO3/ DP03A DP03B GBIN1/ PIO3/ PIO3/ PIO0 PIO0 PIO0 PIO1 PIO1 PIO1 PIO1 PIO1 DP04B DP06B PIO0 E F GND VCC DP05A DP05B DP06A   G H  VCCIO_3  PIO3/ PIO3/ PIO3/ GBIN7/ PIO3/ PIO3/ PIO3/ PIO3/ PIO3/ DP07A DP09A DP09B DP13B DP07B  GBIN6/ PIO3/ PIO3/ PIO3/ PIO3/ PIO3/ DP08B DP11B DP11A DP13A DP08A   VCCIO_0 PIO0 VCCIO_0 GND VCC GND PIO0 PIO0 PIO0 FAST VCCIO_1 GBIN2/ PIO1 PIO1 PIO1 PIO1 PIO1 VCC GND GND GND PIO1 PIO1 GBIN3/ PIO1 PIO1 PIO1 GND GND GND VCC PIO1 PIO1 PIO1 PIO1 VCCIO_1 F G H J PIO3/ PIO3/ PIO3/ VCC GND DP10A DP10B DP12B K VCCIO_3 L GBIN4/ PIO3/ PIO3/ SPI_ GND PIO2 PIO2 PIO2 PIO2 PIO2/ CRESET_B VCC DP14A DP14B PIO2 CBSEL0 M PIO3/ PIO3/ PIO2 PIO2 DP15A DP15B PIO2 PIO2 PIO2 PIO2 CDONE PIOS/ TDI PIO1 N PIO3/ PIO3/ PIO2 PIO2 PIO2 PIO2 VCC PIO2 PIO2 DP17A DP17B VCCIO_2 PIO2 PIO2 PIO2 TDO N P PIO2 PIO2 PIO2 PIO2 GND PIO2 PIO2 PIO2 PIO2/ PIOS/ PIOS/ PIOS/ TMS P PIO1 PIO1 PIO1 PIO1 GND J PIO3/ PIO3/ PIO3/ PIO2 PIO2 PIO2 PIO2 PIO2 GND PIO1 PIO1 VCC PIO1 DP12A DP16A DP16B K  VCCIO_3 VCC GND VCCIO_2  VCCIO_2  TCK PIO1 PIO1 SPI_SO TRST_B  1 2 3 GBIN5/ PIO2 4 5 6 7 I/O Bank 2 Lattice Semiconductor Corporation www.latticesemi.com CBSEL1 SPI_SI SPI_SCK SPI_SS_B 8 9 I/O Bank 1 I/O Bank 3 1 I/O Bank 0 5 6 7 8 L M 10 11 12 13 14 SPI Bank (2.42, 30-MAR-2011) 67 iCE65 Ultra Low-Power mobileFPGA™ Family Figure 46: iCE65L08 CB196 Chip-Scale BGA Footprint (Top View) 2 3 4 GBIN0/ 9 10 11 12 13 14 A PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 VPP_ VPP_ 2V5 A B PIO3/ PIO0 PIO0 PIO0 PIO0 PIO0 VCC PIO0 PIO0 PIO0 PIO0 GND PIO1 PIO1 DP00B B C PIO3/ PIO1/ GND DP01B PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO1 PIO1 PIO1 DP00A C D PIO3/ PIO3/ PIO1/ PIO3/ PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO1 PIO1 PIO1 PIO1 DP02A DP02B DP01A DP04A D E PIO3/ PIO3/ DP03B DP03A GBIN1/ PIO3/ PIO3/ PIO0 PIO0 PIO0 PIO1 PIO1 PIO1 PIO1 PIO1 DP04B DP06B PIO0 E F GND VCC DP05B DP05A DP06A   PIO1 PIO1 PIO1 PIO1 F G GBIN3/ PIO3/ PIO3/ PIO3/ PIO3/ PIO3/ VCC GND GND GND PIO1 PIO1 PIO1 PIO1 DP11A DP11B DP09A DP09B DP13B PIO1   G  VCCIO_3  PIO3/ PIO3/ PIO3/ VCCIO_0 PIO0 VCCIO_0 GND VCC GND PIO0 PIO0 PIO0 FAST VCCIO_1 GBIN2/ PIO1 H GBIN6/ PIO3/ DP08A PIO3/ GBIN7/ PIO3/ PIO3/ PIO3/ GND GND GND VCC PIO1 PIO1 PIO1 PIO1 DP08B DP07B DP07A DP13A  J PIO3/ PIO3/ PIO3/ VCC GND DP10A DP10B DP12B K VCCIO_3 L PIO3/ PIO3/ SPI_ GND PIO2 PIO2 PIO2 PIO2 PIO2 PIO2/ CRESET_B VCC DP14A DP14B CBSEL0  M PIO3/ PIO3/ PIO2 PIO2 DP15A DP15B PIO2 PIO2 CDONE PIOS/ TDI PIO1 N GBIN4/ PIO3/ PIO3/ PIO2 PIO2 PIO2 PIO2 VCC PIO2 DP17A DP17B PIO2 VCCIO_2 PIO2 PIO2 PIO2 TDO N P PIO2 PIO2 PIO2 PIO2 PIO2 GND PIO2 PIO2 PIO2 PIO2/ PIOS/ PIOS/ PIOS/ TMS P H PIO1 PIO1 PIO1 PIO1 GND J PIO3/ PIO3/ PIO3/ PIO2 PIO2 PIO2 PIO2 PIO2 GND PIO1 PIO1 VCC PIO1 DP12A DP16B DP16A K  VCCIO_3 VCC GND VCCIO_1 VCCIO_2  VCCIO_2 PIO2 GBIN5/ PIO2 2 3 4 5 6 7 I/O Bank 2 SPI_SO 8 9 L TRST_B CBSEL1 SPI_SI SPI_SCK SPI_SS_B  1 TCK PIO1 PIO1 I/O Bank 1 I/O Bank 3 1 I/O Bank 0 5 6 7 8 M 10 11 12 13 14 SPI Bank Pinout Table Table 42 provides a detailed pinout table for the iCE65L04 in the CB196 chip-scale BGA package. Pins are generally arranged by I/O bank, then by ball function. The pinout for the iCE65L08 is different than the iCE64L04 pinout. ! Although both the iCE65L04 and iCE65L08 are both available in the CB196 package and almost completely pin compatible, there are differences as shown in Table 43. Table 42: iCE65L04 CB196 Chip-scale BGA Pinout Table Ball Function GBIN0/PIO0 GBIN1/PIO0 PIO0 PIO0 PIO0 PIO0 (2.42, 30-MAR-2012) 68 Ball Number A7 E7 A1 A2 A3 A4 Pin Type GBIN GBIN PIO PIO PIO PIO Bank 0 0 0 0 0 0 Lattice Semiconductor Corporation www.latticesemi.com Ball Function PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 VCCIO_0 VCCIO_0 Ball Number A5 A6 A10 A11 A12 B2 B3 B4 B5 B6 B8 B9 B10 B11 C4 C5 C6 C7 C8 C9 C10 C11 D5 D6 D7 D8 D9 D10 E6 E8 E9 A8 F6 Pin Type PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO VCCIO VCCIO Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GBIN2/PIO1 GBIN3/PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 F10 G12 B13 B14 C12 C13 C14 D11 D12 D13 D14 E10 E11 E12 E13 E14 F11 F12 F13 GBIN GBIN PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Lattice Semiconductor Corporation www.latticesemi.com (2.42, 30-MAR-2011) 69 iCE65 Ultra Low-Power mobileFPGA™ Family Ball Function PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 TCK TDI TDO TMS TRST_B VCCIO_1 VCCIO_1 Ball Number F14 G10 G11 G13 G14 H10 H11 H12 H13 J10 J11 J12 J13 K11 K12 K14 L13 L14 M13 L12 M12 N14 P14 M14 F9 H14 Pin Type PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO JTAG JTAG JTAG JTAG JTAG VCCIO VCCIO Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CDONE CRESET_B GBIN4/PIO2 () M10 L10 CONFIG CONFIG GBIN 2 2 2 GBIN 2 PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO 2 2 2 2 2 2 2 2 2 2 2 2 2 PIO PIO PIO PIO PIO PIO 2 2 2 2 2 2 GBIN5/PIO2 () PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 () PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 (2.42, 30-MAR-2012) 70 iCE65L04: iCE65L08: iCE65L04: iCE65L08: L7 N8 P5 M7 K5 K6 K7 K8 K9 L4 L5 L6 L8 M3 M4 M6 iCE65L04: M7 iCE65L08: P5 M8 M9 N3 N4 N5 N6 Lattice Semiconductor Corporation www.latticesemi.com Ball Function PIO2 () Ball Number iCE65L04: N8 iCE65L08: L7 Pin Type PIO Bank 2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2/CBSEL0 PIO2/CBSEL1 VCCIO_2 VCCIO_2 VCCIO_2 N9 N11 N12 N13 P1 P2 P3 P4 P7 P8 P9 L9 P10 J9 M5 N10 PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO VCCIO VCCIO VCCIO 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 PIO3/DP00A PIO3/DP00B PIO3/DP01A PIO3/DP01B PIO3/DP02A PIO3/DP02B PIO3/DP03A () C1 B1 D3 C3 D1 D2 DPIO DPIO DPIO DPIO DPIO DPIO DPIO 3 3 3 3 3 3 3 DPIO 3 DPIO DPIO DPIO 3 3 3 DPIO 3 DPIO DPIO DPIO 3 3 3 GBIN 3 GBIN DPIO DPIO DPIO DPIO DPIO DPIO 3 3 3 3 3 3 3 DPIO 3 DPIO DPIO 3 3 PIO3/DP03B () PIO3/DP04A PIO3/DP04B PIO3/DP05A () PIO3/DP05B () PIO3/DP06A PIO3/DP06B PIO3/DP07A () GBIN7/PIO3/DP07B () GBIN6/PIO3/DP08A PIO3/DP08B PIO3/DP09A PIO3/DP09B PIO3/DP10A PIO3/DP10B PIO3/DP11A () PIO3/DP11B () PIO3/DP12A PIO3/DP12B Lattice Semiconductor Corporation www.latticesemi.com iCE65L04: E1 iCE65L08: E2 iCE65L04: E2 iCE65L04: E1 D4 E4 iCE65L04: F3 iCE65L08: F4 iCE65L04: F4 iCE65L08: F3 F5 E5 iCE65L04: G2 iCE65L08: H4 iCE65L04: G1 iCE65L08: H3 H1 H2 G3 G4 J1 J2 iCE65L04: iCE65L08: iCE65L04: iCE65L08: K2 J3 H4 G1 H3 G2 (2.42, 30-MAR-2011) 71 iCE65 Ultra Low-Power mobileFPGA™ Family Ball Function Ball Number Pin Type Bank PIO3/DP13A PIO3/DP13B H5 G5 DPIO DPIO 3 3 PIO3/DP14A PIO3/DP14B L1 L2 DPIO DPIO 3 3 PIO3/DP15A PIO3/DP15B PIO3/DP16A () M1 M2 DPIO DPIO 3 3 iCE65L04: K3 iCE65L08: K4 iCE65L08: K4 iCE65L08: K3 DPIO 3 DPIO 3 PIO3/DP17A PIO3/DP17B N1 N2 DPIO DPIO 3 3 VCCIO_3 VCCIO_3 VCCIO_3 E3 J6 K1 VCCIO VCCIO VCCIO 3 3 3 PIOS/SPI_SO PIOS/SPI_SI PIOS/SPI_SCK PIOS/SPI_SS_B SPI_VCC M11 P11 P12 P13 L11 SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND A9 B12 C2 F1 F7 G7 G8 G9 H6 H7 H8 J5 J8 J14 K10 L3 P6 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC VCC VCC VCC VCC VCC VCC VCC VCC B7 F2 F8 G6 H9 J4 J7 K13 N7 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VPP_2V5 VPP_FAST A14 A13 VPP VPP VPP VPP PIO3/DP16B () (2.42, 30-MAR-2012) 72 Lattice Semiconductor Corporation www.latticesemi.com Pinout Differences between iCE65L04 and iCE65L08 in CB196 Package Table 43 lists the package balls that are different between the pinouts for iCE65L04 and the iCE65L08 in the CB196 package. The table also describes the functional differences between these pins, which is critical when designing a CB196 footprint that supports both the iCE65L04 and the iCE65L08 devices. In some cases, only the differential inputs are swapped; single-ended I/Os are not affected. A swapped differential pair can be inverted internally for functional equivalence. In other cases, a global buffer input is swapped with another PIO pin in the same bank. Table 43: Pinout Differences between iCE65L04 and iCE65L08 in CB196 Package Ball Number iCE65L04 iCE65L08 Functional Difference E1 E2 F3 F4 G1 G2 H3 H4 K3 K4 L7 N8 M7 P5 PIO3/DP03A PIO3/DP03B PIO3/DP05A PIO3/DP05B GBIN7/PIO3/DP07B PIO3/DP07A PIO3/DP11B PIO3/DP11A PIO3/DP16A PIO3/DP16B GBIN4/PIO2 PIO2 PIO2 GBIN5/PIO2 Lattice Semiconductor Corporation www.latticesemi.com PIO3/DP03B PIO3/DP03A PIO3/DP05B PIO3/DP05A PIO3/DP11A PIO3/DP11B GBIN7/PIO3/DP07B PIO3/DP07A PIO3/DP16B PIO3/DP16A PIO2 GBIN4/PIO2 GBIN5/PIO2 PIO2 Differential inputs swapped, single-ended I/Os not affected Differential inputs swapped, single-ended I/Os not affected Global buffer input GBIN7 and its associated differential input is swapped with another differential pair in I/O Bank 3 Differential inputs swapped, single-ended I/Os not affected Global buffer input GBIN4 swapped with another PIO pin in I/O Bank 2 Global buffer input GBIN5 swapped with another PIO pin in I/O Bank 2 (2.42, 30-MAR-2011) 73 iCE65 Ultra Low-Power mobileFPGA™ Family Package Mechanical Drawing Figure 47: (a) iCE65L04 CB196 Package Mechanical Drawing CB196: 8 x8 mm, 196-ball, 0.5 mm ball-pitch, fully-populated, chip-scale ball grid array Top View Bottom View 1 2 3 4 5 6 7 8 9 10 11 12 13 14 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Mark pin 1 dot A B B C C D D e A E H J K L M N P E F iCE65L04F-T CB196I NXXXXXXX YYWW © CCCCCC G D1 G D F H J K L M N P e A A1 b E1 Side View E Top Marking Format Description Number of Ball Columns X Number of Ball Rows Y Number of Signal Balls X Body Size Y Ball Pitch Ball Diameter X Edge Ball Center to Center Y Package Height Stand Off (2.42, 30-MAR-2012) 74 Symbol n E D e b E1 D1 A A1 Min. Nominal 7.90 7.90 — 0.27 — — — 0.16 14 14 196 8.00 8.00 0.50 — 6.50 6.50 — — Max. Units Columns Rows Balls 8.10 8.10 — 0.37 — — 1.00 0.26 mm Line Content 1 Logo iCE65L04F 2 -T CB196I 3 ENG 4 NXXXXXXX 5 YYWW 6 © CCCCCC Description Logo Part number Power/Speed Package type Engineering Lot Number Date Code Country Thermal Resistance Junction-to-Ambient θ (⁰C/W) 0 LFM 200 LFM 42 34 Lattice Semiconductor Corporation www.latticesemi.com (b) iCE65L08 CB196 Package Mechanical Drawing CB196: 8 x8 mm, 196-ball, 0.5 mm ball-pitch, fully-populated, chip-scale ball grid array Top View Bottom View 1 2 3 4 5 6 7 8 9 10 11 12 13 14 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Mark pin 1 dot A B B C C D D e A E H J K L M N P E F iCE65L08F-T CB196C ENG NXXXXXXX YYWW © CCCCCC G D1 G D F H J K L M N P A A1 b e E1 Side View E Top Marking Format Description Number of Ball Columns X Number of Ball Rows Y Number of Signal Balls X Body Size Y Ball Pitch Ball Diameter X Edge Ball Center to Center Y Package Height Stand Off Lattice Semiconductor Corporation www.latticesemi.com Symbol n E D e b E1 D1 A A1 Min. Nominal 7.90 7.90 — 0.27 — — — 0.16 14 14 196 8.00 8.00 0.50 — 6.50 6.50 — — Max. Units Columns Rows Balls 8.10 8.10 — 0.37 — — 1.00 0.26 mm Line Content 1 Logo iCE65L08F 2 -T CB196C 3 ENG 4 NXXXXXXX 5 YYWW 6 © CCCCCC Description Logo Part number Power/Speed Package type Engineering Lot Number Date Code Country Thermal Resistance Junction-to-Ambient θ (⁰C/W) 0 LFM 200 LFM 42 34 (2.42, 30-MAR-2011) 75 iCE65 Ultra Low-Power mobileFPGA™ Family CB284 Chip-Scale Ball-Grid Array The CB284 package, partially-populated 0.5 mm pitch, ball grid array simplifies PCB layout with empty ball rings. Footprint Diagram Figure 48 shows the CB284 chip-scale BGA footprint. The 8 x 8 mm CB132 package fits within the same ball pattern as the 12 x 12 mm CB284 package. In other words, the central 8 x 8 section of the CB284 footprint matches the CB132 footprint. Figure 31 shows the conventions used in the diagram. Also see Table 44 for a complete, detailed pinout for the 132-ball and 284-ball chip-scale BGA packages. The signal pins are also grouped into the four I/O Banks and the SPI interface. A 2 3 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 VCCIO_0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO3/ B DP07A PIO1 A PIO1 B PIO3/ C DP07B PIO0 PIO0 PIO0 PIO0 PIO0 VCC PIO0 PIO0 PIO0 GND PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO1 PIO1 C PIO3/ D DP08A VCC PIO1 PIO1 D PIO3/ E DP08B PIO3/ DP05A PIO0 PIO0 PIO0 PIO0 PIO0 VPP_ VPP_ 2V5 PIO1 PIO1 E F VCCIO_3 PIO3/ DP05B PIO3/ DP00A PIO1 PIO1 PIO1 F G GND PIO3/ DP06A PIO3/ DP00B PIO3/ PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 DP01A PIO1 PIO1 PIO1 G PIO3/ H DP09A PIO3/ DP06B PIO3/ DP03A PIO3/ PIO3/ PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO1 DP01B DP02A PIO1 PIO1 VCCIO_1 H PIO3/ DP09B GND PIO3/ DP03B VCCIO_3 PIO1 VCCIO_1 PIO1 J PIO1 PIO1 K VCC PIO1 L J PIO3/ K DP10A I/O Bank 3 VCCIO_0 GBIN0/ GBIN1/ PIO0 PIO0 VCCIO_0 GND PIO0 PIO0 PIO0 FAST PIO3/ DP02B PIO1 PIO1 PIO3/ PIO3/ DP04B DP04A VCCIO_3 GND PIO3/ DP10B PIO3/ DP11A PIO3/ PIO3/ DP19A DP19B VCC GND GND GND PIO1 PIO1 M VREF PIO3/ DP15A GBIN7/ PIO3/ DP11B GBIN6/ PIO3/ DP15A PIO3/ PIO3/ DP20A DP20B GND GND GND VCC PIO1 PIO1 VCCIO_1 PIO1 PIO1 M GND PIO3/ DP16A PIO3/ DP21B PIO3/ VCC DP21A VCC GND PIO1 PIO1 GND GND PIO1 N PIO3/ DP16B VCCIO_3 PIO3/ PIO3/ DP22A DP22B PIO1 PIO1 PIO1 PIO1 PIO1 P L N P VCCIO_3 VCCIO_0 VCCIO_3 GND VCC PIO1 PIO1 GBIN3/ VCCIO_1 VCCIO_2 PIO1 GBIN2/ PIO1 R GND VCCIO_3 PIO3/ DP23A SPI_ GND PIO2 PIO2 PIO2 PIO2 PIO2 PIO2/ CRESET_B VCC TCK PIO1 PIO1 PIO1 R T PIO3/ DP12A GND PIO3/ DP23B PIO2 PIO2 PIOS/ TDI TRST_B PIO1 PIO1 T U DP12B PIO3/ PIO3/ DP17A PIO3/ DP24A TDO PIO1 PIO1 U GND PIO3/ DP17B GBIN5/ GBIN4/ PIO3/ PIO2 PIO2 PIO2 PIO2 GND PIO2 PIO2/ PIOS/ PIOS/ PIOS/ TMS DP24B PIO2 PIO2 CBSEL1 SPI_SI SPI_SCK SPI_SS_B PIO1 PIO1 V PIO3/ WDP13A PIO3/ DP18A PIO1 PIO1 W PIO3/ Y DP13B PIO3/ PIO2 PIO2 PIO2 PIO2 VCC PIO2 PIO2 VCCIO_2 GND PIO2 PIO2 PIO2 GND PIO2 PIO2 PIO2 PIO2 DP18B PIO1 Y V CBSEL0 VCCIO_2 PIO2 PIO2 PIO2 PIO2 CDONE SPI_SO SPI Bank I/O Bank 1 1 Figure 48: iCE65 CB284 Chip-Scale BGA Footprint (Top View) I/O Bank 0 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 AA PIO3/ DP14A PIO1 AA AB PIO3/ PIO2 PIO2 PIO2 GND PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 DP14B AB 1 2 3 (2.42, 30-MAR-2012) 76 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 I/O Bank 2 Lattice Semiconductor Corporation www.latticesemi.com Pinout Table Table 44 provides a detailed pinout table for the two chip-scale BGA packages. Pins are generally arranged by I/O bank, then by ball function. The balls with a black circle () are unconnected balls (N.C.) for the iCE65L04 in the CB284 package. The CB132 package fits within the CB284 package footprint as shown in Figure 48. The right-most column shows which CB132 ball corresponds to the CB284. The table also highlights the differential I/O pairs in I/O Bank 3. Table 44: iCE65 CB284 Chip-scale BGA Pinout Table (with CB132 cross reference) Ball Function GBIN0/PIO0 GBIN1/PIO0 PIO0 () PIO0 () PIO0 () PIO0 () PIO0 PIO0 PIO0 PIO0 () PIO0 () PIO0 () PIO0 () PIO0 () PIO0 PIO0 PIO0 PIO0 PIO0 () PIO0 () PIO0 () PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 Ball Number iCE65L04 iCE65L08 E10 E11 A1 A2 A3 A4 A5 A6 A7 A9 A10 A11 A12 A13 A15 A16 A17 A18 A14 A19 A20 C3 C4 C5 C6 C7 C9 C10 C11 C13 C14 C15 C16 C17 C18 C19 E5 E6 E7 E8 E9 E14 Lattice Semiconductor Corporation www.latticesemi.com Pin Type by Device iCE65L04 GBIN GBIN N.C. N.C. N.C. N.C. PIO PIO PIO N.C. N.C. N.C. N.C. N.C. PIO PIO PIO PIO N.C. N.C. N.C. PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO iCE65L08 GBIN GBIN PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CB132 Ball Equivalent A6 A7 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — A1 A2 A3 A4 A5 A10 (2.42, 30-MAR-2011) 77 iCE65 Ultra Low-Power mobileFPGA™ Family Ball Function PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 VCCIO_0 VCCIO_0 VCCIO_0 VCCIO_0 Ball Number iCE65L04 iCE65L08 E15 E16 G8 G9 G10 G11 G12 G13 G14 G15 G16 H9 H10 H11 H12 H13 H14 H15 A8 A21 E12 K10 iCE65L04 PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO VCCIO VCCIO VCCIO VCCIO iCE65L08 PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO VCCIO VCCIO VCCIO VCCIO Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CB132 Ball Equivalent A11 A12 C4 C5 C6 C7 C8 C9 C10 C11 C12 D5 D6 D7 D8 D9 D10 D11 — — A8 F6 GBIN2/PIO1 GBIN3/PIO1 PIO1 () PIO1 () PIO1 () PIO1 PIO1 () PIO1 PIO1 () PIO1 PIO1 () PIO1 PIO1 PIO1 () PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 () PIO1 PIO1 PIO1 PIO1 () L18 K18 A22 AA22 B22 C20 C22 D20 D22 E20 E22 F18 F20 F22 G18 G20 G22 H16 H18 H20 J15 J16 J18 J22 K15 K16 K20 K22 GBIN GBIN N.C. N.C. N.C. PIO N.C. PIO N.C. PIO N.C. PIO PIO N.C. PIO PIO PIO PIO PIO PIO PIO PIO PIO N.C. PIO PIO PIO N.C. GBIN GBIN PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 G14 F14 — — — — — — — — — B14 — — C14 — — D12 D14 — E11 E12 E14 — F11 F12 — — (2.42, 30-MAR-2012) 78 Pin Type by Device Lattice Semiconductor Corporation www.latticesemi.com Ball Function PIO1 PIO1 PIO1 () PIO1 PIO1 PIO1 PIO1 () PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 () PIO1 PIO1 () PIO1 PIO1 () PIO1 () TCK TDI TDO TMS TRST_B VCCIO_1 VCCIO_1 VCCIO_1 VCCIO_1 Ball Number iCE65L04 iCE65L08 L15 L16 L22 M15 M16 M20 M22 N15 N16 N22 P15 P16 P18 P20 P22 R18 R20 R22 T20 T22 U20 U22 V20 V22 W20 W22 Y22 R16 T16 U18 V18 T18 H22 J20 K13 M18 iCE65L04 PIO PIO N.C. PIO PIO PIO N.C. PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO N.C. PIO N.C. PIO N.C. N.C. JTAG JTAG JTAG JTAG JTAG VCCIO VCCIO VCCIO VCCIO iCE65L08 PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO JTAG JTAG JTAG JTAG JTAG VCCIO VCCIO VCCIO VCCIO Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CB132 Ball Equivalent G11 G12 — H11 H12 — — J11 J12 — K11 K12 K14 — — L14 — — — — — — — — — — — L12 M12 N14 P14 M14 — — F9 H14 CDONE CRESET_B GBIN4/PIO2 GBIN5/PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 T14 R14 V12 V11 R8 R9 R10 R11 R12 T7 T8 T10 T11 T12 CONFIG CONFIG GBIN GBIN PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO CONFIG CONFIG GBIN GBIN PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO 2 2 2 2 2 2 2 2 2 2 2 2 2 2 M10 L10 P7 P8 L4 L5 L6 L7 L8 M3 M4 M6 M7 M8 Lattice Semiconductor Corporation www.latticesemi.com Pin Type by Device (2.42, 30-MAR-2011) 79 iCE65 Ultra Low-Power mobileFPGA™ Family Ball Function PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 () PIO2 () PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 () PIO2 () PIO2 () PIO2 () PIO2 () PIO2 () PIO2 () PIO2/CBSEL0 PIO2/CBSEL1 VCCIO_2 VCCIO_2 VCCIO_2 Ball Number iCE65L04 iCE65L08 T13 V6 V7 V8 V9 V13 Y4 Y5 Y6 Y7 Y9 Y10 Y13 Y14 Y15 Y17 Y18 Y19 Y20 AB2 AB3 AB4 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 R13 V14 N13 T9 Y11 iCE65L04 PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO N.C. N.C. PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO N.C. N.C. N.C. N.C. N.C. N.C. N.C. PIO PIO VCCIO VCCIO VCCIO iCE65L08 PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO VCCIO VCCIO VCCIO Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 CB132 Ball Equivalent M9 P2 P3 P4 P5 P9 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — L9 P10 J9 M5 — PIO3/DP00A PIO3/DP00B PIO3/DP01A PIO3/DP01B F5 G5 G7 H7 DPIO DPIO DPIO DPIO DPIO DPIO DPIO DPIO 3 3 3 3 B1 C1 C3 D3 PIO3/DP02A PIO3/DP02B H8 J8 DPIO DPIO DPIO DPIO 3 3 D4 E4 (2.42, 30-MAR-2012) 80 Pin Type by Device Lattice Semiconductor Corporation www.latticesemi.com Ball Function Ball Number iCE65L04 iCE65L08 iCE65L04 iCE65L08 Bank CB132 Ball Equivalent PIO3/DP03A PIO3/DP03B H5 J5 DPIO DPIO DPIO DPIO 3 3 D1 E1 PIO3/DP04A PIO3/DP04B K8 K7 DPIO DPIO DPIO DPIO 3 3 F4 F3 PIO3/DP05A PIO3/DP05B E3 F3 DPIO DPIO DPIO DPIO 3 3 — — PIO3/DP06A PIO3/DP06B G3 H3 DPIO DPIO DPIO DPIO 3 3 — — PIO3/DP07A () PIO3/DP07B () B1 C1 N.C. N.C. DPIO DPIO 3 3 — — PIO3/DP08A () PIO3/DP08B () D1 E1 N.C. N.C. DPIO DPIO 3 3 — — PIO3/DP09A PIO3/DP09B H1 J1 DPIO DPIO DPIO DPIO 3 3 — — PIO3/DP10A PIO3/DP10B K1 L1 DPIO DPIO DPIO DPIO 3 3 — — PIO3/DP11A GBIN7/PIO3/DP11B L3 L5 DPIO GBIN DPIO GBIN 3 3 — G1 PIO3/DP12A () PIO3/DP12B () T1 U1 N.C. N.C. DPIO DPIO 3 3 — — PIO3/DP13A () PIO3/DP13B () W1 Y1 N.C. N.C. DPIO DPIO 3 3 — — PIO3/DP14A () PIO3/DP14B () AA1 AB1 N.C. N.C. DPIO DPIO 3 3 — — GBIN6/PIO3/DP15A PIO3/DP15B M5 M3 GBIN DPIO GBIN DPIO 3 3 H1 — PIO3/DP16A PIO3/DP16B N3 P3 DPIO DPIO DPIO DPIO 3 3 — — PIO3/DP17A PIO3/DP17B U3 V3 DPIO DPIO DPIO DPIO 3 3 — — PIO3/DP18A PIO3/DP18B W3 Y3 DPIO DPIO DPIO DPIO 3 3 — — PIO3/DP19A PIO3/DP19B L7 L8 DPIO DPIO DPIO DPIO 3 3 G3 G4 PIO3/DP20A PIO3/DP20B M7 M8 DPIO DPIO DPIO DPIO 3 3 H3 H4 PIO3/DP21A PIO3/DP21B N7 N5 DPIO DPIO DPIO DPIO 3 3 J3 J1 PIO3/DP22A PIO3/DP22B P7 P8 DPIO DPIO DPIO DPIO 3 3 K3 K4 PIO3/DP23A PIO3/DP23B R5 T5 DPIO DPIO DPIO DPIO 3 3 L1 M1 PIO3/DP24A PIO3/DP24B U5 V5 DPIO DPIO DPIO DPIO 3 3 N1 P1 VCCIO_3 VCCIO_3 F1 P1 VCCIO VCCIO VCCIO VCCIO 3 3 — — Lattice Semiconductor Corporation www.latticesemi.com Pin Type by Device (2.42, 30-MAR-2011) 81 iCE65 Ultra Low-Power mobileFPGA™ Family Ball Function VCCIO_3 VCCIO_3 VCCIO_3 VCCIO_3 VCCIO_3 VREF Ball Number iCE65L04 iCE65L08 J7 K3 N10 P5 R3 M1 iCE65L04 VCCIO VCCIO VCCIO VCCIO VCCIO VREF iCE65L08 VCCIO VCCIO VCCIO VCCIO VCCIO VREF Bank 3 3 3 3 3 3 CB132 Ball Equivalent E3 — J6 K1 — — PIOS/SPI_SO PIOS/SPI_SI PIOS/SPI_SCK PIOS/SPI_SS_B SPI_VCC T15 V15 V16 V17 R15 SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI M11 P11 P12 P13 L11 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND C12 E13 J3 K5 K11 L11 L12 L13 M10 M11 M12 N1 N12 N18 N20 R7 T3 V1 V10 Y12 Y16 AB5 G1 R1 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND — A9 — F1 F7 G7 G8 G9 H6 H7 H8 — J8 J14 — L3 — — P6 — — — — — VCC VCC VCC VCC VCC VCC VCC VCC VCC C8 D3 K12 L10 L20 M13 N8 N11 Y8 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC — — F8 G6 — H9 J4 J7 — VPP_2V5 VPP_FAST E18 E17 VPP VPP VPP VPP VPP VPP A14 A13 (2.42, 30-MAR-2012) 82 Pin Type by Device Lattice Semiconductor Corporation www.latticesemi.com Package Mechanical Drawing Figure 49: CB284 Package Mechanical Drawing 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 CB284: 12 x 12 mm, 284-ball, 0.5 mm ball-pitch, chip-scale ball grid array Mark pin 1 dot Top View Bottom View A B B C C D D e A E E F F G G H H J J M N P R T K i CE65L08F-T EN G CB284C N XXXXXXX YYWW L D1 L D K M N P R T U U V V W Y AA © CCCCCC W Y AA AB AB e E1 A A1 b Side View E Top Marking Format Description Number of Ball Columns X Number of Ball Rows Y Number of Signal Balls X Body Size Y Ball Pitch Ball Diameter X Edge Ball Center to Center Y Package Height Stand Off Symbol n E D e b E1 D1 A A1 Min. Nominal 11.90 11.90 — 0.27 — — — 0.16 22 22 284 12.00 12.00 0.50 — 10.50 10.50 — — Max. Units Columns Rows Balls 12.10 12.10 — 0.37 — — 1.00 0.26 mm Line Content 1 Logo iCE65L08F 2 -T ENG 3 CB284C NXXXXXXX 4 YYWW 5 N/A 6 © CCCCCC Description Logo Part number Power/Speed Engineering Package type and Lot number Date Code Blank Country Thermal Resistance Junction-to-Ambient θ (⁰C/W) 0 LFM 200 LFM 35 28 Lattice Semiconductor Corporation www.latticesemi.com (2.42, 30-MAR-2011) 83 iCE65 Ultra Low-Power mobileFPGA™ Family Die Cross Reference The tables in this section list all the pads on a specific die type and provide a cross reference on how a specific pad connects to a ball or pin in each of the available package offerings. Similarly, the tables provide the pad coordinates for the die-based version of the product (DiePlus). These tables also provide a way to prototype with one package option and then later move to a different package or die. As described in “Input and Output Register Control per PIO Pair” on page 16, PIO pairs share register control inputs. Similarly, as described in “Differential Inputs and Outputs” on page 12, a PIO pair can form a differential input or output. PIO pairs in I/O Bank 3 are optionally differential inputs or differential outputs. PIO pairs in all other I/O Banks are optionally differential outputs. In the tables, differential pairs are surrounded by a heavy blue box. iCE65L04 Table 45 lists all the pads on the iCE65L04 die and how these pads connect to the balls or pins in the supported package styles. Most VCC, VCCIO, and GND pads are double-bonded inside the package although the table shows only a single connection. For additional information on the iCE65L04 DiePlus product, please refer to the following data sheet. DiePlus Advantage FPGA Known Good Die Table 45: iCE65L04 Die Cross Reference iCE65L04 Pad Name VQ100 CB132 DiePlus CB196 CB284 Pad PIO3_00/DP00A PIO3_01/DP00B 1 2 B1 C1 C1 B1 F5 G5 1 2 129.40 231.40 2,687.75 2,642.74 PIO3_02/DP01A PIO3_03/DP01B 3 4 C3 D3 D3 C3 G7 H7 3 4 129.40 231.40 2,597.75 2,552.74 GND GND VCCIO_3 VCCIO_3 5 — 6 — F1 — E3 — F1 — E3 — K5 — J7 — 5 6 7 8 129.40 231.40 129.40 231.40 2,507.75 2,462.74 2,417.75 2,372.74 PIO3_04/DP02A PIO3_05/DP02B 7 8 D4 E4 D1 D2 H8 J8 9 10 129.40 231.40 2,327.75 2,292.74 PIO3_06/DP03A PIO3_07/DP03B — — D1 E1 E1 E2 H5 J5 11 12 129.40 231.40 2,257.75 2,222.74 VCC — — H9 D3 13 129.40 2,187.75 PIO3_08/DP04A PIO3_09/DP04B 9 10 F4 F3 D4 E4 K8 K7 14 15 231.40 129.40 2,152.74 2,117.75 PIO3_10/DP05A PIO3_11/DP05B — — — — F3 F4 E3 F3 16 17 231.40 129.40 2,082.74 2,047.75 X (µm) Y (µm) GND — H6 A9 M10 18 231.40 2,012.74 PIO3_12/DP06A PIO3_13/DP06B — — — — F5 E5 G3 H3 19 20 129.40 231.40 1,977.75 1,942.74 GND GND — — — — A9 — J3 — 21 22 129.40 231.40 1,907.75 1,872.74 PIO3_14/DP07A PIO3_15/DP07B — — — — — — H1 J1 23 24 129.40 231.40 1,837.75 1,802.74 VCCIO_3 VCC — 11 — G6 K1 G6 K3 L10 25 26 129.40 231.40 1,767.75 1,732.74 PIO3_16/DP08A PIO3_17/DP08B — — — — — — K1 L1 27 28 129.40 231.40 1,697.75 1,662.74 (2.42, 30-MAR-2012) 84 Lattice Semiconductor Corporation www.latticesemi.com iCE65L04 Pad Name VQ100 CB132 DiePlus CB196 CB284 Pad PIO3_18/DP09A GBIN7/PIO3_19/DP09B 12 13 — G1 G2 G1 L3 L5 29 30 129.40 231.40 1,627.75 1,592.74 VCCIO_3 VREF GND 14 N/A — J6 N/A — J6 N/A A9 N10 M1 N1 31 32 33 129.40 231.40 129.40 1,557.75 1,522.74 1,487.75 GBIN6/PIO3_20/DP10A PIO3_21/DP10B 15 16 H1 — H1 H2 M5 M3 34 35 231.40 129.40 1,452.74 1,417.75 GND 17 H7 A9 M11 36 231.40 1,382.74 PIO3_22/DP11A PIO3_23/DP11B — — — — G3 G4 N3 P3 37 38 129.40 231.40 1,347.75 1,312.74 VCCIO_3 VCCIO_3 GND GND — — — — — — — — K1 — A9 — R3 — T3 — 39 40 41 42 129.40 231.40 129.40 231.40 1,277.75 1,242.74 1,207.75 1,172.74 PIO3_24/DP12A PIO3_25/DP12B — — — — J1 J2 U3 V3 43 44 129.40 231.40 1,137.75 1,102.74 GND — — A9 V1 45 129.40 1,067.75 PIO3_26/DP13A PIO3_27/DP13B — — — — H4 H3 W3 Y3 46 47 231.40 129.40 1,032.74 997.75 PIO3_28/DP14A PIO3_29/DP14B 18 19 G3 G4 K2 J3 L7 L8 48 49 231.40 129.40 962.74 927.75 PIO3_30/DP15A PIO3_31/DP15B — — H3 H4 H5 G5 M7 M8 50 51 231.40 129.40 892.74 857.75 VCC — J4 F2 N8 52 231.40 822.74 PIO3_32/DP16A PIO3_33/DP16B 20 21 J3 J1 L1 L2 N7 N5 53 54 129.40 231.40 787.75 752.74 VCCIO_3 VCCIO_3 GND GND 22 — 23 — K1 — L3 — K1 — L3 — P5 — R7 — 55 56 57 58 129.40 231.40 129.40 231.40 717.75 682.74 637.75 592.74 PIO3_34/DP17A PIO3_35/DP17B — — K3 K4 M1 M2 P7 P8 59 60 129.40 231.40 547.75 502.74 PIO3_36/DP18A PIO3_37/DP18B 24 25 L1 M1 K3 K4 R5 T5 61 62 129.40 231.40 457.75 412.74 PIO3_38/DP19A PIO3_39/DP19B — — N1 P1 N1 N2 U5 V5 63 64 129.40 231.40 367.75 322.74 PIO2_00 PIO2_01 — — — P2 — L4 AB2 V6 65 66 545.00 595.00 139.20 37.20 PIO2_02 GND PIO2_03 — — 26 M3 — L4 M3 C2 P1 T7 AB5 R8 67 68 69 645.00 695.00 745.00 139.20 37.20 139.20 PIO2_04 PIO2_05 27 28 P3 M4 N3 P2 V7 T8 70 71 795.00 845.00 37.20 139.20 PIO2_06 PIO2_07 29 30 L5 P4 L5 M4 R9 V8 72 73 895.00 930.00 37.20 139.20 Lattice Semiconductor Corporation www.latticesemi.com X (µm) Y (µm) (2.42, 30-MAR-2011) 85 iCE65 Ultra Low-Power mobileFPGA™ Family iCE65L04 Pad Name VQ100 CB132 CB196 CB284 Pad X (µm) PIO2_08 VCCIO_2 PIO2_09 — 31 — L6 M5 P5 P3 M5 K5 R10 T9 V9 74 75 76 965.00 1,000.00 1,035.00 37.20 139.20 37.20 PIO2_10 GND PIO2_11 — 32 — M6 P6 — N4 H7 P4 T10 V10 Y4 77 78 79 1,070.00 1,105.00 1,140.00 139.20 37.20 139.20 PIO2_12 PIO2_13 — — — — L6 — Y5 AB6 80 81 1,175.00 1,210.00 37.20 139.20 PIO2_14 PIO2_15 — — — — — — AB7 AB8 82 83 1,245.00 1,280.00 37.20 139.20 PIO2_16 PIO2_17 — — — — — — AB9 AB10 84 85 1,315.00 1,350.00 37.20 139.20 PIO2_18 GND PIO2_19 — — — — J8 — — H8 K6 AB11 N12 Y6 86 87 88 1,385.00 1,420.00 1,455.00 37.20 139.20 37.20 PIO2_20 VCC PIO2_21 — — — — — — N5 J4 M6 Y7 Y8 Y9 89 90 91 1,490.00 1,525.00 1,560.00 139.20 37.20 139.20 PIO2_22 GBIN5/PIO2_23 — 33 — P7 N6 P5 Y10 V11 92 93 1,595.00 1,630.00 37.20 139.20 GBIN4/PIO2_24 PIO2_25 34 — P8 — L7 — V12 AB12 94 95 1,665.00 1,700.00 37.20 139.20 VCCIO_2 — — J9 Y11 96 1,735.00 37.20 PIO2_26 PIO2_27 — — — — — K7 AB13 AB14 97 98 1,770.00 1,805.00 139.20 37.20 GND — — J5 Y12 99 1,840.00 139.20 PIO2_28 PIO2_29 — — — — K9 M7 AB15 Y13 100 101 1,875.00 1,910.00 37.20 139.20 PIO2_30 PIO2_31 — — — — K8 P7 Y14 Y15 102 103 1,945.00 1,980.00 37.20 139.20 PIO2_32 PIO2_33 — — — — L8 P8 Y17 Y18 104 105 2,015.00 2,050.00 37.20 139.20 PIO2_34 PIO2_35 — — — — N8 M8 Y19 Y20 106 107 2,085.00 2,120.00 37.20 139.20 VCC VCC 35 — J7 — J7 — N11 — 108 109 2,155.00 2,190.00 37.20 139.20 PIO2_36 PIO2_37 36 37 P9 M7 P9 N9 V13 T11 110 111 2,225.00 2,260.00 37.20 139.20 VCCIO_2 38 J9 N10 N13 112 2,295.00 37.20 PIO2_38 GND PIO2_39 — 39 — L7 H8 M8 M9 J8 N12 R11 M12 T12 113 114 115 2,330.00 2,365.00 2,400.00 139.20 37.20 139.20 PIO2_40 PIO2_41 — 40 L8 M9 N11 N13 R12 T13 116 117 2,435.00 2,470.00 37.20 139.20 PIO2_42/CBSEL0 PIO2_43/CBSEL1 41 42 L9 P10 L9 P10 R13 V14 118 119 2,505.00 2,540.00 37.20 139.20 CDONE 43 M10 M10 T14 120 2,575.00 37.20 (2.42, 30-MAR-2012) 86 DiePlus Y (µm) Lattice Semiconductor Corporation www.latticesemi.com iCE65L04 Pad Name DiePlus CB132 L10 CB196 L10 CB284 R14 Pad X (µm) CRESET_B VQ100 44 121 2,625.00 139.20 PIOS_00/SPI_SO PIOS_01/SPI_SI 45 46 M11 P11 M11 P11 T15 V15 122 123 2,690.00 2,740.00 37.20 139.20 GND 47 — P6 Y16 124 2,790.00 37.20 PIOS_02/SPI_SCK PIOS_03/SPI_SS_B 48 49 P12 P13 P12 P13 V16 V17 125 126 2,840.00 2,890.00 139.20 37.20 SPI_VCC 50 L11 L11 R15 127 2,990.00 37.20 TDI TMS TCK TDO TRST_B N/A N/A N/A N/A N/A M12 P14 L12 N14 M14 M12 P14 L12 N14 M14 T16 V18 R16 U18 T18 128 129 130 131 132 3,610.80 3,712.80 3,610.80 3,712.80 3,610.80 342.00 392.00 442.00 492.00 542.00 PIO1_00 PIO1_01 51 52 L14 K12 K11 L13 R18 P16 133 134 3,712.80 3,610.80 592.00 642.00 PIO1_02 PIO1_03 53 54 K11 K14 K12 M13 P15 P18 135 136 3,712.80 3,610.80 692.00 727.00 GND GND 55 55 J14 J14 J14 J14 N18 N18 137 138 3,712.80 3,610.80 762.00 797.00 PIO1_04 PIO1_05 56 57 J12 J11 J10 L14 N16 N15 139 140 3,712.80 3,610.80 832.00 867.00 VCCIO_1 VCCIO_1 58 — H14 — H14 — M18 — 141 142 3,712.80 3,610.80 902.00 937.00 PIO1_06 PIO1_07 59 60 H12 H11 J11 K14 M16 M15 143 144 3,712.80 3,610.80 972.00 1,007.00 PIO1_08 PIO1_09 — — — — H10 J13 W20 V20 145 146 3,712.80 3,610.80 1,042.00 1,077.00 PIO1_10 VCC VCC PIO1_11 — 61 — — — H9 — — J12 N7 — H13 U20 M13 — T22 147 148 149 150 3,712.80 3,610.80 3,712.80 3,610.80 1,112.00 1,147.00 1,182.00 1,217.00 PIO1_12 PIO1_13 — — — — H12 — R22 P22 151 152 3,712.80 3,610.80 1,252.00 1,287.00 PIO1_14 PIO1_15 — — — — G13 N22 T20 153 154 3,712.80 3,610.80 1,322.00 1,357.00 PIO1_16 PIO1_17 — — — — H11 G14 R20 P20 155 156 3,712.80 3,610.80 1,392.00 1,427.00 GND GND — — — — K10 — N20 — 157 158 3,712.80 3,610.80 1,462.00 1,497.00 PIO1_18 GBIN3/PIO1_19 — 62 — F14 G10 G12 M20 K18 159 160 3,712.80 3,610.80 1,532.00 1,567.00 GBIN2/PIO1_20 PIO1_21 63 — G14 — F10 F14 L18 K20 161 162 3,712.80 3,610.80 1,602.00 1,637.00 VCCIO_1 VCCIO_1 — — — — H14 — J20 — 163 164 3,712.80 3,610.80 1,672.00 1,707.00 PIO1_22 PIO1_23 — — — — F13 D13 H20 G20 165 166 3,712.80 3,610.80 1,742.00 1,777.00 Lattice Semiconductor Corporation www.latticesemi.com Y (µm) (2.42, 30-MAR-2011) 87 iCE65 Ultra Low-Power mobileFPGA™ Family iCE65L04 Pad Name VQ100 CB132 DiePlus CB196 CB284 Pad X (µm) Y (µm) PIO1_24 PIO1_25 — — — — G11 F11 F20 E20 167 168 3,712.80 3,610.80 1,812.00 1,847.00 PIO1_26 PIO1_27 — — — — E10 E14 D20 C20 169 170 3,712.80 3,610.80 1,882.00 1,917.00 GND GND — — G8 — G8 — L12 — 171 172 3,712.80 3,610.80 1,952.00 1,987.00 PIO1_28 PIO1_29 — — — G12 F12 D14 G22 L16 173 174 3,712.80 3,610.80 2,022.00 2,057.00 PIO1_30 PIO1_31 64 65 G11 F12 E13 C14 L15 K16 175 176 3,712.80 3,610.80 2,092.00 2,127.00 VCC VCC — — — — K13 — L20 — 177 178 3,712.80 3,610.80 2,162.00 2,197.00 PIO1_32 PIO1_33 66 — E14 F11 E11 C13 J18 K15 179 180 3,712.80 3,610.80 2,232.00 2,267.00 VCCIO_1 VCCIO_1 67 — F9 — F9 — K13 — 181 182 3,712.80 3,610.80 2,302.00 2,337.00 PIO1_34 PIO1_35 68 69 E12 D14 E12 B14 J16 H18 183 184 3,712.80 3,610.80 2,377.00 2,427.00 GND 70 G9 G9 L13 185 3,712.80 2,477.00 PIO1_36 PIO1_37 71 72 E11 D12 B13 D12 J15 H16 186 187 3,610.80 3,712.80 2,527.00 2,577.00 PIO1_38 PIO1_39 73 74 C14 B14 C12 D11 G18 F18 188 189 3,610.80 3,712.80 2,627.00 2,677.00 VPP_2V5 75 A14 A14 E18 190 3,610.80 2,739.68 VPP_FAST VCC VCC 76 77 77 A13 F8 F8 A13 F8 F8 E17 K12 K12 191 192 193 3,097.00 2,997.00 2,947.00 2,962.80 2,860.80 2,962.80 PIO0_00 PIO0_01 78 — A12 C12 C11 — E16 G16 194 195 2,897.00 2,847.00 2,860.80 2,962.80 PIO0_02 PIO0_03 79 80 A11 C11 A12 B11 E15 G15 196 197 2,797.00 2,747.00 2,860.80 2,962.80 PIO0_04 PIO0_05 — 81 D11 A10 — D10 H15 E14 198 199 2,697.00 2,647.00 2,860.80 2,962.80 PIO0_06 PIO0_07 82 83 C10 D10 A11 D9 G14 H14 200 201 2,612.00 2,577.00 2,860.80 2,962.80 GND GND 84 — A9 — H6 — E13 — 202 203 2,542.00 2,507.00 2,860.80 2,962.80 PIO0_08 PIO0_09 85 86 C9 D9 C10 A10 G13 H13 204 205 2,472.00 2,437.00 2,860.80 2,962.80 PIO0_10 PIO0_11 87 — C8 D8 B10 E9 G12 H12 206 207 2,402.00 2,367.00 2,860.80 2,962.80 PIO0_12 PIO0_13 — — — — — — A18 A17 208 209 2,332.00 2,297.00 2,860.80 2,962.80 PIO0_14 PIO0_15 — — — — — — A16 A15 210 211 2,262.00 2,227.00 2,860.80 2,962.80 VCCIO_0 VCCIO_0 88 — A8 — A8 — E12 — 212 213 2,192.00 2,157.00 2,860.80 2,962.80 (2.42, 30-MAR-2012) 88 Lattice Semiconductor Corporation www.latticesemi.com iCE65L04 Pad Name VQ100 CB132 DiePlus CB196 CB284 Pad X (µm) Y (µm) PIO0_16 PIO0_17 — — — — — C9 C19 C18 214 215 2,122.00 2,087.00 2,860.80 2,962.80 PIO0_18 PIO0_19 — — — — B9 D8 C17 C16 216 217 2,052.00 2,017.00 2,860.80 2,962.80 PIO0_20 PIO0_21 — — — — C8 E8 C15 C14 218 219 1,982.00 1,947.00 2,860.80 2,962.80 PIO0_22 GBIN1/PIO0_23 — 89 — A7 B8 E7 C13 E11 220 221 1,912.00 1,877.00 2,860.80 2,962.80 GND GND — — — — B12 — C12 — 222 223 1,842.00 1,807.00 2,860.80 2,962.80 GBIN0/PIO0_24 PIO0_25 90 — A6 — A7 D7 E10 C11 224 225 1,772.00 1,737.00 2,860.80 2,962.80 PIO0_26 PIO0_27 — — — — C7 E6 C10 C9 226 227 1,702.00 1,667.00 2,860.80 2,962.80 VCC VCC — — — — B7 — C8 — 228 229 1,632.00 1,597.00 2,860.80 2,962.80 PIO0_28 PIO0_29 — — — — A6 B6 C7 C6 230 231 1,562.00 1,527.00 2,860.80 2,962.80 PIO0_30 PIO0_31 — — — — A5 D6 C5 C4 232 233 1,492.00 1,457.00 2,860.80 2,962.80 GND GND — — F7 — F7 — K11 — 234 235 1,422.00 1,387.00 2,860.80 2,962.80 PIO0_32 PIO0_33 — — — — — — C3 A7 236 237 1,352.00 1,317.00 2,860.80 2,962.80 PIO0_34 PIO0_35 — — — — — — A6 A5 238 239 1,282.00 1,247.00 2,860.80 2,962.80 PIO0_36 VCCIO_0 VCCIO_0 PIO0_37 91 92 92 93 C7 F6 F6 D7 C6 F6 F6 C5 G11 K10 K10 H11 240 241 242 243 1,212.00 1,177.00 1,142.00 1,107.00 2,860.80 2,962.80 2,860.80 2,962.80 PIO0_38 PIO0_39 94 95 C6 A5 B5 A4 G10 E9 244 245 1,072.00 1,037.00 2,860.80 2,962.80 PIO0_40 PIO0_41 96 97 D6 C5 B4 D5 H10 G9 246 247 1,002.00 967.00 2,860.80 2,962.80 PIO0_42 GND PIO0_43 — 98 99 A4 G7 D5 A3 G7 B3 E8 L11 H9 248 249 250 917.00 867.00 817.00 2,860.80 2,962.80 2,860.80 PIO0_44 PIO0_45 — 100 C4 A3 C4 A2 G8 E7 251 252 767.00 717.00 2,962.80 2,860.80 PIO0_46 PIO0_47 — — A2 A1 A1 B2 E6 E5 253 254 667.00 617.00 2,962.80 2,860.80 Lattice Semiconductor Corporation www.latticesemi.com (2.42, 30-MAR-2011) 89 iCE65 Ultra Low-Power mobileFPGA™ Family iCE65L08 Table 46 lists all the pads on the iCE65L08 die and how these pads connect to the balls or pins in the supported package styles. Most VCC, VCCIO, and GND pads are double-bonded inside the package although the table shows only a single connection. For additional information on the iCE65L08 DiePlus product, please refer to the following data sheet.  DiePlusAdvantage FPGA Known Good Die Table 46: iCE65L08 Die Cross Reference iCE65L08 Pad Name Available Packages CB196 CB284 Pad DiePlus X (µm) Y (µm) PIO3_00/DP00A PIO3_01/DP00B — — B1 C1 1 2 129.735 231.735 3,882.665 3,837.665 PIO3_02/DP01A PIO3_03/DP01B C1 B1 F5 G5 3 4 129.735 231.735 3,792.665 3,747.665 GND GND VCCIO_3 VCCIO_3 C2 — E3 — K5 — J7 — 5 6 7 8 129.735 231.735 129.735 231.735 3,702.665 3,657.665 3,612.665 3,567.665 PIO3_04/DP02A PIO3_05/DP02B D3 C3 E3 F3 9 10 129.735 231.735 3,512.665 3,477.665 PIO3_06/DP03A PIO3_07/DP03B D1 D2 G3 H3 11 12 129.735 231.735 3,442.665 3,407.665 VCC VCC F2 — D3 — 13 14 129.735 231.735 3,372.665 3,337.665 PIO3_08/DP04A PIO3_09/DP04B D4 E4 D1 E1 15 16 129.735 231.735 3,302.665 3,267.665 PIO3_10/DP05A PIO3_11/DP05B — — H1 J1 17 18 129.735 231.735 3,232.665 3,197.665 GND GND F1 — M10 — 19 20 129.735 231.735 3,162.665 3,127.665 PIO3_12/DP06A PIO3_13/DP06B E2 E1 H5 J5 21 22 129.735 231.735 3,092.665 3,057.665 GND GND L3 — J3 — 23 24 129.735 231.735 3,022.665 2,987.665 PIO3_14/DP07A PIO3_15/DP07B F5 E5 K1 L1 25 26 129.735 231.735 2,952.665 2,917.665 VCCIO_3 VCCIO_3 VCC VCC E3 — G6 — K3 — L10 — 27 28 29 30 129.735 231.735 129.735 231.735 2,882.665 2,847.665 2,812.665 2,777.665 PIO3_16/DP08A PIO3_17/DP08B F4 F3 G7 H7 31 32 129.735 231.735 2,742.665 2,707.665 VCCIO_3 VCCIO_3 GND GND K1 — — — F1 — G1 — 33 34 35 36 129.735 231.735 129.735 231.735 2,672.665 2,637.665 2,602.665 2,567.665 PIO3_18/DP09A PIO3_19/DP09B G3 G4 K8 K7 37 38 129.735 231.735 2,532.665 2,497.665 (2.42, 30-MAR-2012) 90 Lattice Semiconductor Corporation www.latticesemi.com iCE65L08 Pad Name Available Packages CB196 CB284 Pad DiePlus X (µm) Y (µm) PIO3_20/DP10A PIO3_21/DP10B — — H8 J8 39 40 129.735 231.735 2,462.665 2,427.665 PIO3_22/DP11A PIO3_23/DP11B G1 G2 T1 U1 41 42 129.735 231.735 2,392.665 2,357.665 VCCIO_3 VCCIO_3 VREF VREF GND GND VCCIO_3 VCCIO_3 GND GND K1 — N/A N/A J5 — J6 — H6 — N10 — M1 — N1 — P1 — R1 — 43 44 45 46 47 48 49 50 51 52 129.735 231.735 129.735 231.735 129.735 231.735 129.735 231.735 129.735 231.735 2,322.665 2,287.665 2,252.665 2,217.665 2,182.665 2,147.665 2,112.665 2,077.665 2,042.665 2,007.665 PIO3_24/DP12A GBIN7/PIO3_25/DP12B H4 H3 L3 L5 53 54 129.735 231.735 1,972.665 1,937.665 GND H7 V1 55 129.735 1,902.665 GBIN6/PIO3_26/DP13A PIO3_27/DP13B H1 H2 M5 M3 56 57 231.735 129.735 1,867.665 1,832.665 PIO3_28/DP14A PIO3_29/DP14B — — N7 N5 58 59 231.735 129.735 1,798.665 1,762.665 PIO3_30/DP15A PIO3_31/DP15B J1 J2 N3 P3 60 61 231.735 129.735 1,727.665 1,692.665 GND GND J5 — M11 — 62 63 231.735 129.735 1,657.665 1,622.665 PIO3_32/DP16A PIO3_33/DP16B H5 G5 W1 Y1 64 65 231.735 129.735 1,587.665 1,552.665 VCCIO_3 VCCIO_3 GND GND J6 — J5 — R3 — T3 — 66 67 68 69 231.735 129.735 231.735 129.735 1,517.665 1,482.665 1,447.665 1,412.665 PIO3_34/DP17A PIO3_35/DP17B K2 J3 AA1 AB1 70 71 231.735 129.735 1,377.665 1,342.665 PIO3_36/DP18A PIO3_37/DP18B — — L7 L8 72 73 231.735 129.735 1,307.665 1,272.665 PIO3_38/DP19A PIO3_39/DP19B — — M7 M8 74 75 231.735 129.735 1,237.665 1,202.665 PIO3_40/DP20A PIO3_41/DP20B L1 L2 P7 P8 76 77 231.735 129.735 1,167.665 1,132.665 VCC VCC J4 — N8 — 78 79 231.735 129.735 1,097.665 1,062.665 PIO3_42/DP21A PIO3_43/DP21B K4 K3 R5 T5 80 81 231.735 129.735 1,027.665 992.665 VCCIO_3 VCCIO_3 GND GND K1 — L3 — P5 — R7 — 82 83 84 85 231.735 129.735 231.735 129.735 957.665 912.665 867.665 822.67 Lattice Semiconductor Corporation www.latticesemi.com (2.42, 30-MAR-2011) 91 iCE65 Ultra Low-Power mobileFPGA™ Family iCE65L08 Pad Name Available Packages CB196 CB284 Pad DiePlus X (µm) Y (µm) PIO3_44/DP22A PIO3_45/DP22B M1 M2 U3 V3 86 87 231.735 129.735 777.67 732.67 PIO3_46/DP23A PIO3_47/DP23B N1 N2 U5 V5 88 89 231.735 129.735 687.67 642.67 PIO3_48/DP24A PIO3_49/DP24B — — W3 Y3 90 91 231.735 129.735 597.67 552.665 PIO2_00 PIO2_01 P1 M3 AB2 R8 92 93 510.0 560.0 139.5 37.5 PIO2_02 GND GND PIO2_03 P2 P6 — M4 Y4 AB5 — T7 94 95 96 97 610.0 660.0 710.0 760.0 139.5 37.5 139.5 37.5 PIO2_04 PIO2_05 N3 — AB3 R9 98 99 810.0 859.3 139.5 37.5 PIO2_06 PIO2_07 — L4 Y5 T8 100 101 910.0 960.0 139.5 37.5 PIO2_08 VCCIO_2 VCCIO_2 PIO2_09 P3 M5 — P4 V6 T9 — R10 102 103 104 105 1,012.5 1,047.5 1,082.5 1,117.5 139.5 37.5 139.5 37.5 PIO2_10 GND GND PIO2_11 N4 H8 — K5 AB4 V10 — V7 106 107 108 109 1,152.5 1,187.5 1,222.5 1,257.5 139.5 37.5 139.5 37.5 PIO2_12 PIO2_13 P5 — Y7 V9 110 111 1,292.5 1,327.5 139.5 37.5 PIO2_14 PIO2_15 — — Y6 AB7 112 113 1,362.5 1,397.5 139.5 37.5 PIO2_16 PIO2_17 — L5 AB6 Y9 114 115 1,432.5 1,467.5 139.5 37.5 PIO2_18 GND GND PIO2_19 N5 P6 — N6 V8 N12 — AB8 116 117 118 119 1,502.3 1,537.3 1,572.5 1,607.5 139.5 37.5 139.5 37.5 PIO2_20 VCC VCC PIO2_21 K6 J7 — L6 AB9 Y8 — T10 120 121 122 123 1,642.5 1,677.5 1,712.5 1,747.5 139.5 37.5 139.5 37.5 PIO2_22 PIO2_23 M6 — AB10 AB11 124 125 1,782.5 1,817.5 139.5 37.5 PIO2_24 PIO2_25 — L7 AB12 Y10 126 127 1,852.5 1,887.5 139.5 37.5 PIO2_26 PIO2_27 P7 K7 AB13 AB14 128 129 1,922.5 1,957.5 139.5 37.5 VCCIO_2 VCCIO_2 N10 — Y11 — 130 131 1,992.5 2,027.5 139.5 37.5 (2.42, 30-MAR-2012) 92 Lattice Semiconductor Corporation www.latticesemi.com iCE65L08 Pad Name Available Packages CB196 CB284 Pad DiePlus X (µm) Y (µm) PIO2_28 GBIN5/PIO2_29 — M7 Y13 V11 132 133 2,062.5 2,097.5 139.5 37.5 GBIN4/PIO2_30 GND GND PIO2_31 N8 J8 — P8 V12 Y12 — Y14 134 135 136 137 2,132.5 2,167.5 2,202.5 2,237.5 139.5 37.5 139.5 37.5 PIO2_32 PIO2_33 — M8 AB15 V13 138 139 2,272.5 2,307.5 139.5 37.5 PIO2_34 PIO2_35 — L8 AB16 Y15 140 141 2,342.5 2,377.5 139.5 37.5 PIO2_36 PIO2_37 — N9 AB17 AB18 142 143 2,412.5 2,447.5 139.5 37.5 PIO2_38 PIO2_39 — — AB19 AB20 144 145 2,482.5 2,517.5 139.5 37.5 PIO2_40 PIO2_41 — — AB21 Y17 146 147 2,552.5 2,587.5 139.5 37.5 PIO2_42 PIO2_43 — — AB22 Y18 148 149 2,622.5 2,657.5 139.5 37.5 PIO2_44 VCC VCC PIO2_45 P9 N7 — M9 Y19 N11 — Y20 150 151 152 153 2,692.5 2,727.5 2,762.5 2,797.5 139.5 37.5 139.5 37.5 PIO2_46 VCCIO_2 VCCIO_2 PIO2_47 K8 J9 — N11 T11 N13 — R11 154 155 156 157 2,832.5 2,867.5 2,902.5 2,937.5 139.5 37.5 139.5 37.5 GND GND J8 — M12 — 158 159 2,972.5 3,007.5 139.5 37.5 PIO2_48 PIO2_49 N12 K9 T12 R12 160 161 3,042.5 3,077.5 139.5 37.5 PIO2_50 N13 T13 162 3,112.5 139.5 PIO2_51/CBSEL0 PIO2_52/CBSEL1 L9 P10 R13 V14 163 164 3,147.5 3,182.5 37.5 139.5 CDONE CRESET_B M10 L10 T14 R14 165 166 3,217.5 3,260.0 37.5 139.5 PIOS_00/SPI_SO PIOS_01/SPI_SI M11 P11 T15 V15 167 168 3,320.0 3,370.0 37.5 139.5 GND GND J8 — Y16 — 169 170 3,420.0 3,470.0 37.5 139.5 PIOS_02/SPI_SCK PIOS_03/SPI_SS_B P12 P13 V16 V17 171 172 3,520.0 3,570.0 37.5 139.5 VCC VCC SPI_VCC SPI_VCC — — L11 — — — R15 — 173 174 175 176 3,620.0 3,670.0 3,720.0 3,770.0 37.5 139.5 37.5 139.5 Lattice Semiconductor Corporation www.latticesemi.com (2.42, 30-MAR-2011) 93 iCE65 Ultra Low-Power mobileFPGA™ Family iCE65L08 Pad Name Available Packages CB196 CB284 Pad DiePlus X (µm) Y (µm) TDI TMS TCK TDO TRST_B M12 P14 L12 N14 M14 T16 V18 R16 U18 T18 177 178 179 180 181 4,470.5 4,572.5 4,470.5 4,572.5 4,470.5 634.615 684.615 734.615 784.615 834.615 PIO1_00 PIO1_01 M13 K11 R18 P16 182 183 4,572.5 4,470.5 884.615 934.615 PIO1_02 PIO1_03 L13 L14 P15 P18 184 185 4,572.5 4,470.5 984.615 1,034.615 GND GND G9 — N18 — 186 187 4,572.5 4,470.5 1,084.615 1,134.615 PIO1_04 PIO1_05 J11 K12 N16 N15 188 189 4,572.5 4,470.5 1,184.615 1,234.62 VCCIO_1 VCCIO_1 F9 — M18 — 190 191 4,572.5 4,470.5 1,287.115 1,322.115 PIO1_06 PIO1_07 J12 K14 M15 M16 192 193 4,572.5 4,470.5 1,357.115 1,392.115 PIO1_08 PIO1_09 — — T20 W20 194 195 4,572.5 4,470.5 1,427.115 1,462.115 PIO1_10 VCC VCC PIO1_11 — H9 — — V20 M13 — R20 196 197 198 199 4,572.5 4,470.5 4,572.5 4,470.5 1,497.115 1,532.115 1,567.115 1,602.115 PIO1_12 PIO1_13 — — Y22 AA22 200 201 4,572.5 4,470.5 1,637.115 1,672.115 PIO1_14 PIO1_15 — J13 U20 W22 202 203 4,572.5 4,470.5 1,707.115 1,742.115 PIO1_16 PIO1_17 H11 J10 P20 V22 204 205 4,572.5 4,470.5 1,777.115 1,812.115 PIO1_18 GND GND PIO1_19 H12 K10 — H13 U22 N20 — T22 206 207 208 209 4,572.5 4,470.5 4,572.5 4,470.5 1,847.115 1,882.115 1,917.110 1,952.115 PIO1_20 PIO1_21 — H10 M20 R22 210 211 4,572.5 4,470.5 1,987.115 2,022.115 PIO1_22 VCCIO_1 VCCIO_1 PIO1_23 — F9 — G10 P22 J20 — M22 212 213 214 215 4,572.5 4,470.5 4,572.5 4,470.5 2,057.115 2,092.115 2,127.115 2,162.115 PIO1_24 PIO1_25 G11 — N22 K22 216 217 4,572.5 4,470.5 2,197.115 2,232.115 PIO1_26 GBIN3/PIO1_27 — G12 L22 K18 218 219 4,572.5 4,470.5 2,267.115 2,302.11 GBIN2/PIO1_28 PIO1_29 F10 — L18 J22 220 221 4,572.5 4,470.5 2,337.115 2,372.115 (2.42, 30-MAR-2012) 94 Lattice Semiconductor Corporation www.latticesemi.com iCE65L08 Pad Name Available Packages CB196 CB284 Pad DiePlus X (µm) Y (µm) PIO1_30 PIO1_31 PIO1_32 PIO1_33 PIO1_34 PIO1_35 GND GND PIO1_36 VCCIO_1 VCCIO_1 PIO1_37 PIO1_38 PIO1_39 PIO1_40 PIO1_41 PIO1_42 PIO1_43 PIO1_44 PIO1_45 PIO1_46 VCC VCC PIO1_47 PIO1_48 VCCIO_1 VCCIO_1 PIO1_49 PIO1_50 GND GND PIO1_51 PIO1_52 PIO1_53 PIO1_54 VPP_2V5 — G14 — F11 F12 G13 G8 — E10 H14 — F14 E11 D12 F13 E13 E12 E14 — — — K13 — D14 D11 H14 — C14 D13 J14 — B14 C13 B13 C12 A14 K20 F22 G22 E22 L16 D22 L12 — K16 H22 — H20 J18 C22 J16 B22 H18 G20 L15 A22 H16 L20 — F20 K15 K13 — E20 J15 L13 — D20 G18 C20 F18 E18 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 4,572.5 4,470.5 4,572.5 4,470.5 4,572.5 4,470.5 4,572.5 4,470.5 4,572.5 4,470.5 4,572.5 4,470.5 4,572.5 4,470.5 4,572.5 4,470.5 4,572.5 4,470.5 4,572.5 4,470.5 4,572.5 4,470.5 4,572.5 4,470.5 4,572.5 4,470.5 4,572.5 4,470.5 4,572.5 4,470.5 4,572.5 4,470.5 4,572.5 4,470.5 4,572.5 4,470.5 2,407.115 2,442.115 2,477.115 2,512.115 2,547.115 2,582.115 2,617.115 2,652.115 2,687.12 2,722.12 2,757.12 2,792.12 2,827.12 2,862.12 2,897.12 2,932.12 2,967.12 3,002.12 3,037.12 3,072.12 3,107.12 3,142.12 3,177.12 3,229.615 3,279.615 3,329.615 3,379.615 3,429.62 3,479.615 3,529.615 3,579.615 3,629.615 3,679.595 3,729.595 3,779.595 3,879.575 VPP_FAST VCC VCC PIO0_00 PIO0_01 PIO0_02 PIO0_03 PIO0_04 VCCIO_0 PIO0_05 A13 F8 — — — C11 — A12 F6 B11 E17 K12 — G16 C19 H15 C18 H14 A21 C17 258 259 260 261 262 263 264 265 266 267 3,866.975 3,766.98 3,716.98 3,666.98 3,616.98 3,566.98 3,516.98 3,466.98 3,416.98 3,366.98 4,054.5 4,156.5 4,054.5 4,156.5 4,054.5 4,156.5 4,054.5 4,156.5 4,054.5 4,156.5 PIO0_06 PIO0_07 D10 A11 E16 G15 268 269 3,316.98 3,266.98 4,054.5 4,156.5 Lattice Semiconductor Corporation www.latticesemi.com (2.42, 30-MAR-2011) 95 iCE65 Ultra Low-Power mobileFPGA™ Family iCE65L08 Pad Name Available Packages CB196 CB284 Pad DiePlus X (µm) Y (µm) GND GND F7 — E13 — 270 271 3,216.98 3,166.98 4,054.5 4,156.5 PIO0_08 PIO0_09 D9 C10 E15 G14 272 273 3,116.98 3,064.48 4,054.5 4,156.5 PIO0_10 PIO0_11 A10 B10 A20 H13 274 275 3,029.48 2,994.48 4,054.5 4,156.5 PIO0_12 PIO0_13 — E9 A19 G13 276 277 2,959.48 2,924.48 4,054.5 4,156.5 PIO0_14 PIO0_15 — — C16 E14 278 279 2,889.48 2,854.48 4,054.5 4,156.5 VCCIO_0 VCCIO_0 F6 — E12 — 280 281 2,819.48 2,784.48 4,054.5 4,156.5 PIO0_16 PIO0_17 — — A18 A17 282 283 2,749.48 2,714.48 4,054.5 4,156.5 PIO0_18 PIO0_19 C9 — C15 A16 284 285 2,679.48 2,644.48 4,054.5 4,156.5 PIO0_20 PIO0_21 B9 — C14 H12 286 287 2,609.48 2,574.48 4,054.5 4,156.5 PIO0_22 PIO0_23 D8 C8 A15 H11 288 289 2,539.48 2,504.48 4,054.5 4,156.5 PIO0_24 PIO0_25 E8 — C13 A14 290 291 2,469.48 2,434.48 4,054.5 4,156.5 GND GND B12 — C12 — 292 293 2,399.48 2,364.48 4,054.5 4,156.5 PIO0_26 PIO0_27 B8 D7 A13 A12 294 295 2,329.48 2,294.48 4,054.5 4,156.5 PIO0_28 GBIN1/PIO0_29 — E7 C11 E11 296 297 2,259.48 2,224.48 4,054.5 4,156.5 GBIN0/PIO0_30 PIO0_31 A7 — E10 G12 298 299 2,189.48 2,154.48 4,054.5 4,156.5 VCCIO_0 VCCIO_0 A8 — A8 — 300 301 2,119.48 2,084.48 4,054.5 4,156.5 PIO0_32 PIO0_33 C7 — A11 G11 302 303 2,049.48 2,014.48 4,054.5 4,156.5 PIO0_34 PIO0_35 E6 — A10 C10 304 305 1,979.48 1,944.48 4,054.5 4,156.5 VCC VCC B7 — C8 — 306 307 1,909.48 1,874.48 4,054.5 4,156.5 PIO0_36 PIO0_37 — A6 A9 A7 308 309 1,839.48 1,804.48 4,054.5 4,156.5 PIO0_38 PIO0_39 B6 A5 C9 A6 310 311 1,769.48 1,734.48 4,054.5 4,156.5 GND G7 K11 312 1,699.48 4,054.5 GND — — 313 1,664.48 4,156.5 PIO0_40 PIO0_41 D6 C6 E9 G10 314 315 1,629.48 1,594.48 4,054.5 4,156.5 (2.42, 30-MAR-2012) 96 Lattice Semiconductor Corporation www.latticesemi.com iCE65L08 Pad Name Available Packages CB196 CB284 Pad DiePlus X (µm) Y (µm) PIO0_42 PIO0_43 C5 B5 A5 G9 316 317 1,559.48 1,524.48 4,054.5 4,156.5 PIO0_44 PIO0_45 A4 — A3 A4 318 319 1,489.48 1,454.48 4,054.5 4,156.5 PIO0_46 PIO0_47 — — A2 C7 320 321 1,419.48 1,384.48 4,054.5 4,156.5 PIO0_48 VCCIO_0 VCCIO_0 PIO0_49 — A8 — — C6 K10 — E8 322 323 324 325 1,331.98 1,281.98 1,231.98 1,181.98 4,054.5 4,156.5 4,054.5 4,156.5 PIO0_50 PIO0_51 B4 C4 A1 E7 326 327 1,131.98 1,081.98 4,054.5 4,156.5 PIO0_52 PIO0_53 A3 B3 C5 E6 328 329 1,031.98 981.98 4,054.5 4,156.5 PIO0_54 GND GND PIO0_55 D5 A9 — B2 C3 L11 — G8 330 331 332 333 931.98 881.98 831.98 781.98 4,054.5 4,156.5 4,054.5 4,156.5 PIO0_56 PIO0_57 A2 A1 C4 H10 334 335 731.98 681.98 4,054.5 4,156.5 PIO0_58 PIO0_59 — — E5 H9 336 337 631.98 581.98 4,054.5 4,156.5 Lattice Semiconductor Corporation www.latticesemi.com (2.42, 30-MAR-2011) 97 iCE65 Ultra Low-Power mobileFPGA™ Family Electrical Characteristics All parameter limits are specified under worst-case supply voltage, temperature, and processing conditions. Absolute Maximum Ratings Stresses beyond those listed under Table 47 may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions beyond those listed under the Recommended Operating Conditions is not implied. Exposure to absolute maximum conditions for extended periods of time adversely affects device reliability. Table 47: Absolute Maximum Ratings Symbol Min Max Units VCC VPP_2V5 VPP_FAST VCCIO_0 VCCIO_1 VCCIO_2 SPI_VCC VCCIO_3 Core supply Voltage VPP_2V5 NVCM programming and operating supply Optional fast NVCM programming supply I/O bank supply voltage (I/O Banks 0, 1, and 2 plus SPI interface) Description –0.5 1.42 –0.5 4.00 V V V V I/O Bank 3 supply voltage –0.5 V VIN_0 VIN_1 VIN_2 VIN_SPI VIN_3 VIN_VREF IOUT TJ TSTG Voltage applied to PIO pin within a specific I/O bank (I/O Banks 0, 1, and 2 plus SPI interface) –1.0 iCE65L01: 4.00 iCE65L04/08: 3.6 5.5 Voltage applied to PIO pin within I/O Bank 3 –0.5 V DC output current per pin Junction temperature Storage temperature, no bias — –55 –65 iCE65L01: 4.00 iCE65L04/08: 3.6 20 125 150 V mA °C °C Recommended Operating Conditions Table 48: Recommended Operating Conditions Symbol VCC VPP_2V5 VPP_FAST SPI_VCC VCCIO_0 VCCIO_1 VCCIO_2 VCCIO_3 SPI_VCC VCCIO_3 TA TPROG NOTE: Description –L: Ultra-Low Power mode –L: Low Power –T: High Performance VPP_2V5 NVCM Release from Power-on Reset programming and operating Configure from NVCM supply NVCM programming Optional fast NVCM programming supply SPI interface supply voltage I/O standards, all banks* LVCMOS33 Non-standard voltage: in between 2.5V and 3.3V use LVCMOS25 in iCEcube2 LVCMOS25, LVDS LVCMOS18, SubLVDS LVCMOS15 I/O standards only available SSTL2 in iCE65L04/08 I/O Bank 3* SSTL18 MDDR Ambient temperature Commercial (C) Industrial (I) NVCM programming temperature Core supply voltage Minimum 0.95 1.14 Nominal 1.00 1.20 Maximum 1.05 1.26 1.30 — 3.47 2.30 — 3.47 2.30 — 3.00 Leave unconnected in application 1.71 — 3.47 3.14 3.30 3.47 Units V V V V V V V Nominal -5% 2.5< Nominal
ICE65L04F-TCS63I
1. 物料型号:iCE65L01F-T 2. 器件简介:文档中描述了iCE65 Ultra Low-Power mobileFPGA™ Family,这是一款超低功耗的移动FPGA系列产品。 3. 引脚分配:文档提供了详细的引脚分配图和表格,例如CB121 Chip-Scale Ball-Grid Array的引脚分配,包括信号引脚、电源引脚、地引脚等。 4. 参数特性:文档中列出了iCE65L01F-T的电气特性,包括但不限于输入泄漏电流、三态I/O引脚泄漏电流、PIO引脚输入电容、GBIN全局缓冲器引脚输入电容等。 5. 功能详解:文档详细解释了iCE65L01F-T的功能,包括其逻辑块、I/O特性、时序指南等。 6. 应用信息:虽然文档没有直接提供应用案例,但从其超低功耗的特性可以推断,该器件适用于对功耗有严格要求的移动或便携式设备。 7. 封装信息:文档提供了CB121、CB132、CB196和CB284等封装的机械绘图和热阻抗信息。
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