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ICE65P04F-TCB284I

ICE65P04F-TCB284I

  • 厂商:

    LATTICE(莱迪思半导体)

  • 封装:

    284-VFBGA, CSPBGA

  • 描述:

    IC FPGA 174 I/O 284CBGA

  • 数据手册
  • 价格&库存
ICE65P04F-TCB284I 数据手册
iCE65™ P-Series Ultra Low-Power mobileFPGA™ Family R SiliconBlue April 22, 2011 (1.31) Data Sheet Figure 1: iCE65P P-Series Family Architectural Features  High-density, ultra low-power single-chip, SRAM mobileFPGA family specifically designed for hand-held applications and long battery life Programmable Logic Block (PLB) 9+ µA at kHz (Typical) 45μA at ff ≤= 32.768 0 kHz (Typical)  Integrated Phase-Locked Loop (PLL) I/O Bank 0  Clock multiplication/division for display, serializer/deserializer (SerDes) , and memory interface applications  superior design security: no exposed data Phase-Locked Loop  Proven, high-volume 65 nm, low-power Nonvolatile Configuration Memory (NVCM) CMOS technology  Flexible programmable logic and programmable interconnect fabric  Over 12K look-up tables (LUT4) and flip-flops  Low-power logic and interconnect 8 Logic Cells = Programmable Logic Block I/O Bank 1 JTAG PLB I/O Bank 2 Programmable Interconnect PLB PLB PLB PLB PLB PLB PLB PLB PLB PLB PLB PLB PLB PLB PLB PLB PLB PLB PLB PLB PLL NVCM  ideal for volume production PLB 4Kbit RAM PLB 4Kbit RAM PLB PLB PLB PLB PLB PLB PLB PLB methods and sources  Self configuration from external, commodity SPI serial Flash PROM  Slave configuration by a processor using SPI-like serial interface in as little as 20 us.  Self configuration from embedded, secure Nonvolatile Configuration Memory (NVCM) PLB I/O Bank 3  Up to 533 MHz PLL Output  Reprogrammable from a variety of Programmable Interconnect Programmable Interconnect SPI Config Carry logic Four-input Look-Up Table (LUT4) Flip-flop with enable and reset controls  Plentiful, fast, on-chip 4Kbit RAM blocks  Low-cost, space-efficient packaging options  DiePlus™ known-good die (KGD) options available  Complete iCEcube™ development system  Flexible I/O pins to simplify system interfaces  Up to 174 programmable I/O pins  Four independently-powered I/O banks; support for 3.3V, 2.5V, 1.8V, and 1.5V voltage standards  LVCMOS, MDDR, LVDS, and SubLVDS I/O standards      Windows® and Linux® support VHDL and Verilog logic synthesis Place and route software Design and IP core libraries Low-cost iCEman65P development board Table 1: iCE65P Ultra Low-Power Programmable Logic Family Summary iCE65P04 Logic Cells (LUT + Flip-Flop) Approximate System Gate Count Typical Equivalent Macrocells RAM4K Memory Blocks RAM4K RAM bits Phase-Locked Loops (PLLs) Configuration bits (maximum) Core Operating Current at 0 KHz Maximum Programmable I/O Pins Maximum Differential Input Pairs iCE65P08 iCE65P12 3,520 200K 2,700 20 80K 1 533 Kb 45 µA 174 20 © 2007-2011 by SiliconBlue Technologies Corporation. All rights reserved. www.SiliconBlueTech.com (1.31, 22-APR-2011) 1 iCE65 P-Series Ultra-Low Power mobileFPGA™ Family Overview The SiliconBlue Technologies iCE65P P-Series programmable logic family is specifically designed to deliver the lowest static and dynamic power consumption of any comparable CPLD or FPGA device. iCE65P FPGAs are designed specifically for cost-sensitive, high-volume applications. iCE65P FPGA are fully user-programmable and can self-configure from a configuration image stored in on-chip, nonvolatile configuration memory (NVCM) or stored in an external commodity SPI serial Flash PROM or downloaded from an external processor over an SPI-like serial port. The three iCE65P components, highlighted in Table 1, deliver from approximately 3,500 to 12,000 logic cells and flipflops while consuming a fraction of the power of comparable programmable logic devices. Each iCE65P device includes between 20 or more RAM blocks, each with 4Kbits of storage, for on-chip data storage and data buffering. As pictured in Figure 1, each iCE65P device consists of five primary architectural elements.  An array of Programmable Logic Blocks (PLBs)  Each PLB contains eight Logic Cells (LCs); each Logic Cell consists of …  A fast, four-input look-up table (LUT4) capable of implementing any combinational logic function of up to four inputs, regardless of complexity  A „D‟-type flip-flop with an optional clock-enable and set/reset control  Fast carry logic to accelerate arithmetic functions such as adders, subtracters, comparators, and counters.  Common clock input with polarity control, clock-enable input, and optional set/reset control input to the PLB is shared among all eight Logic Cells  Two-port, 4Kbit RAM blocks (RAM4K)  256x16 default configuration; selectable data width using programmable logic resources  Simultaneous read and write access; ideal for FIFO memory and data buffering applications  RAM contents pre-loadable during configuration  Four I/O banks with independent supply voltage, each with multiple Programmable Input/Output (PIO) blocks  LVCMOS I/O standards and LVDS outputs supported in all banks  I/O Bank 3 supports additional SSTL, MDDR, LVDS, and SubLVDS I/O standards  One or more Phase-Locked Loops (PLL)  Very low power  Clock multiplication and division  Phase shifting in fixed 90° increments  Static or dynamic phase shifting  Programmable interconnections between the blocks  Flexible connections between all programmable logic functions  Eight dedicated low-skew, high-fanout clock distribution networks (1.31, 22-APR-2011) 2 SiliconBlue Technologies Corporation www.SiliconBlueTech.com SiliconBlue Packaging Options iCE65P components are available in a variety of package options to support specific application requirements. The available options, including the number of available user-programmable I/O pins (PIOs), are listed in Table 2. Fullytested Known-Good Die (KGD) DiePlus™ are available for die stacking and highly space-conscious applications. All iCE65P devices are provided exclusively in Pb-free, RoHS-compliant packages. Table 2: iCE65P Family Packaging Options, Maximum I/O per Package Board Area (mm) 6x6 8x8 12 x 12 See die data sheet Package 121-ball chip-scale BGA 196-ball chip-scale BGA 284-ball chip-scale BGA DiePlus known good die Package Code CB121 CB196 CB284 Ball/Lead Pitch (mm) 0.5 95 (13) 148 (18) 174 (20) DI — 174 (20) iCE65P04 iCE65P08 iCE65P12 Feature-rich versions of the end application mount a larger iCE65P device on the circuit board. Low-end versions mount a smaller iCE65P device. Ordering Information Figure 2 describes the iCE65P ordering codes for all packaged components. See the separate DiePlus data sheets when ordering die-based products. Figure 2: iCE65P Ordering Codes (packaged, non-die components) iCE65P 04 F -T CB 284 C Logic Cells (x1,000) 04, 08 12 04, 08, Configuration Memory Temperature Range C = Commercial (TAJ = 0° to 70° Celsius) I = Industrial (TJA = –40° to 85° Celsius) F = NVCM + reprogrammable Package Leads Power Consumption/ Speed -T = High speed Package Style CB = chip-scale ball grid CS = wafer level chip-scale package (0.4 mm pitch) VQ = very-thin quad flat pack package iCE65P devices come standard in the higher speed “-T” version. iCE65P devices are available in two operating temperature ranges, one for typical commercial applications, the other with an extended temperature range for industrial and telecommunications applications. The ordering code also specifies the device package option, as described further in Table 2. Programmable Logic Block (PLB) Generally, a logic design for an iCE65P component is created using a high-level hardware description language such as Verilog or VHDL. The SiliconBlue Technologies development software then synthesizes the high-level description into equivalent functions built using the programmable logic resources within each iCE65P device. Both sequential and combinational functions are constructed from an array of Programmable Logic Blocks (PLBs). Each PLB contains eight Logic Cells (LCs), as pictured in Figure 3, and share common control inputs, such as clocks, reset, and enable controls. PLBs are connected to one another and other logic functions using the rich Programmable Interconnect resources. SiliconBlue Technologies Corporation www.SiliconBlueTech.com (1.31, 22-APR-2011) 3 iCE65 P-Series Ultra-Low Power mobileFPGA™ Family Logic Cell (LC) Each iCE65P device contains thousands of Logic Cells (LCs), as listed in Table 1. Each Logic Cell includes three primary logic elements, shown in Figure 3.  A four-input Look-Up Table (LUT4) builds any combinational logic function, of any complexity, of up to four inputs. Similarly, the LUT4 element behaves as a 16x1 Read-Only Memory (ROM). Combine and cascade multiple LUT4s to create wider logic functions.  A „D‟-style Flip-Flop (DFF), with an optional clock-enable and reset control input, builds sequential logic functions. Each DFF also connects to a global reset signal that is automatically asserted immediately following device configuration.  Carry Logic boosts the logic efficiency and performance of arithmetic functions, including adders, subtracters, comparators, binary counters and some wide, cascaded logic functions. The output from a Logic Cell is available to all inputs to all eight Logic Cells within the Programmable Logic Block. Similarly, the Logic Cell output feeds into the Error! Reference source not found. fabric to connect to other eatures on the iCE65P device. Look-Up Table (LUT4) The four-input Look-Up Table (LUT4) function implements any and all combinational logic functions, regardless of complexity, of between zero and four inputs. Zero-input functions include “High” (1) and “Low” (0). The LUT4 function has four inputs, labeled I0, I1, I2, and I3. Three of the four inputs are shared with the Carry Logic function, as shown in Figure 3. The bottom-most LUT4 input connects either to the I3 input or to the Carry Logic output from the previous Logic Cell. The output from the LUT4 function connects to the flip-flop within the same Logic Cell. The LUT4 output or the flip-flop output then connects to the programmable interconnect. For detailed LUT4 internal timing, see Table 57. ‘D’-style Flip-Flop (DFF) The „D‟-style flip-flop (DFF) optionally stores state information for the application. Figure 3: Programmable Logic Block and Logic Cell Shared Block-Level Controls Clock Programmable Logic Block (PLB) Enable Set/Reset 1 0 Logic Cell 8 Logic Cells (LCs) Carry Logic I0 I1 I2 I3 LUT4 Four-input Look-Up Table (LUT4) DFF D Q EN SR O Flip-flop with optional enable and set or reset controls = Statically defined by configuration program (1.31, 22-APR-2011) 4 SiliconBlue Technologies Corporation www.SiliconBlueTech.com SiliconBlue The flip-flop has a data input, „D‟, and a data output, „Q‟. Additionally, each flip-flop has up to three control signals that are shared among all flip-flops in all Logic Cells within the PLB, as shown in Figure 3. Table 3 describes the behavior of the flip-flop based on inputs and upon the specific DFF design primitive used or synthesized. Table 3: ‘D’-Style Flip-Flop Behavior DFF Primitive All Operation Cleared Immediately after Configuration Hold Present Value (Disabled) Hold Present Value (Static Clock) Load with Input Data Asynchronous Reset Flip-Flop Mode X D Inputs EN SR X X X X 0 X 0 X X Q X X X 1 or 0 Q 0* ↑ D 1 X 0 1 X 1 1 ↑ 0 1 ↑ 1 D 1* Asynchronous X X Reset SB_DFFS Asynchronous Set Asynchronous X X Set SB_DFFSR Synchronous Reset Synchronous X 1* Reset SB_DFFSS Synchronous Set Synchronous X 1* Set X = don‘t care, ↑ = rising clock edge (default polarity), 1* = High or unused, 0* SB_DFFR CLK Output Q = Low or unused The CLK clock signal is not optional and is shared among all flip-flops in a Programmable Logic Block. By default, flip-flops are clocked by the rising edge of the PLB clock input, although the clock polarity can be inverted for all the flip-flops in the PLB. The CLK input optionally connects to one of the following clock sources.  The output from any one of the eight Global Buffers, or  A connection from the general-purpose interconnect fabric The EN clock-enable signal is common to all Logic Cells in a Programmable Logic Block. If the enable signal is not used, then the flip-flop is always enabled. This condition is indicated as “1*” in Table 3. The asterisk indicates that this is the default state if the control signal is not connected in the application. Similarly, the SR set/reset signal is common to all Logic Cells in a Programmable Logic Block. If not used, then the flip-flop is never set/reset, except when cleared immediately after configuration or by the Global Reset signal. This condition is indicated as “0*” in Table 3. The asterisk indicates that this is the default state if the control signal is not connected in the application. Each flip-flop has an additional control that defines its set or reset behavior. As defined in the configuration image, the control defines whether the set or reset operation is synchronized to the active CLK clock edge or whether it is completely asynchronous.  The SB_DFFR and SB_DFFS primitives are asynchronously controlled, solely by the SR input. If the SR input is High, then an SB_DFFR primitive is asynchronously reset and an SB_DFFS primitive is asynchronously set.  The SB_DFFSR and SB_DFFRSS primitives are synchronously controlled by both the SR input and the clock input. If the SR input is High at a rising edge of the clock input, then an SB_DFFSR primitive is synchronously reset and an SB_DFFSS primitive is synchronously set. The LUT4 output or the flip-flop output then connects to the programmable interconnect. Because of the shared control signals, the design software can pack flip-flops with common control inputs into a single PLB block, as described by Table 4. There are eight total packing options. SiliconBlue Technologies Corporation www.SiliconBlueTech.com (1.31, 22-APR-2011) 5 iCE65 P-Series Ultra-Low Power mobileFPGA™ Family Table 4: Flip-flop Packing/Sharing within a PLB Group Active Clock Edge 1 2 3 4 5 6 7 8         Clock Enable Set or Reset Control (Sync. or Async) None None (always enabled) PLB set/reset control Selective (controlled by PLB clock enable) None PLB set/reset control For detailed flip-flop internal timing, see Table 57. Carry Logic The dedicated Carry Logic within each Logic Cell primarily accelerates and improves the efficiency of arithmetic logic such as adders, accumulators, subtracters, incrementers, decrementers, counters, ALUs, and comparators. The Carry Logic also supports wide combinational logic functions. COUT = I1 ● I2 + CIN ●I1 + CIN ● I2 [Equation 1] Equation 1 and Figure 4 describe the Carry Logic structure within a Logic Cell. The Carry Logic shares inputs with the associated Look-Up Table (LUT4). The LUT4‟s I1 and I2 inputs directly feed the Carry Logic; inputs I0 and I3 do not. A signal cascades between Logic Cells within the Programmable Logic Block. The carry input from the previous adjacent Logic Cell optionally provides an alternate input to the LUT4 function, supplanting the I3 input. Low-Power Disable To save power and prevent unnecessary signal switching, the Carry Logic function within a Logic Cell is disabled if not used. The output of a Logic Cell‟s Carry Logic is forced High. PLB Carry Input and Carry Output Connections As shown in Figure 4, each Programmable Logic Block has a carry input signal that can be initialized High, Low, or come from the carry output signal from PLB immediately below. Similarly, the Carry Logic output from the Programmable Logic Block connects to the PLB immediately above, which allows the Carry Logic to span across multiple PLBs in a column. As shown in Figure 5, the Carry Logic chain can be tapped mid-way through a chain or a PLB by feeding the value through a LUT4 function. Adder Example Figure 5 shows an example design that uses the Carry Logic. The example is a 2-bit adder, which can be expanded into an adder of arbitrary size. The LUT4 function within a Logic Cell is programmed to calculate the sum of the two input values and the carry input, A[i] + B[i] + CARRY_IN[i-1] = SUM[i]. The Carry Logic generates the carry value to feed the next bit in the adder. The calculated carry value replaces the I3 input to the next LUT4 in the upper Logic Cell. If required by the application, the carry output from the final stage of the adder is available by passing it through the final LUT4. (1.31, 22-APR-2011) 6 SiliconBlue Technologies Corporation www.SiliconBlueTech.com SiliconBlue Figure 4: Carry Logic Structure within a Logic Cell and between PLBs Adjacent PLB To upper adjacent Logic Cell Carry Logic I0 I1 LUT4 I2 I3 From lower adjacent Logic Cell 0 Carry Logic initialization into Programmable Logic 1 Block (PLB) Adjacent PLB = Statically defined by configuration program SiliconBlue Technologies Corporation www.SiliconBlueTech.com (1.31, 22-APR-2011) 7 iCE65 P-Series Ultra-Low Power mobileFPGA™ Family Implementing Subtracters, Decrementers As mentioned earlier, the Carry Logic generates a High output whenever the sum of I1 + I2 + CARRY_IN generates a carry. The Carry Logic does not specifically have a subtract mode. To implement a subtract function or decrement function, logically invert either the I1 or I2 input and invert the initial carry input. This performs a 2s complement subtract operation. Figure 5: Two-bit Adder Example LUT4 I0 GND I1 GND I2 I3 CARRY_OUT Carry Logic LUT4 I0 A[1] I1 B[1] I2 I3 SUM[1] Carry Logic LUT4 I0 A[0] I1 B[0] I2 I3 SUM[0] CARRY_IN (1.31, 22-APR-2011) 8 SiliconBlue Technologies Corporation www.SiliconBlueTech.com SiliconBlue Programmable Input/Output Block (PIO) Programmable Input/Output (PIO) blocks surround the periphery of the device and connect external components to the Programmable Logic Blocks (PLBs) and RAM4K blocks via programmable interconnect. Individual PIO pins are grouped into one of four I/O banks, as shown in Figure 6. I/O Bank 3 has additional capabilities, including LVDS differential I/O and the ability to interface to Mobile DDR memories. Figure 6 also shows the logic within a PIO pin. When used in an application, a PIO pin becomes a signal input, an output, or a bidirectional I/O pin with a separate direction control input. Figure 6: Programmable Input/Output (PIO) Pin VCCIO I/O Bank 0, 1, or 2 Voltage Supply 0 = Hi-Z 1 = Output Enabled Enabled ‘1’ Disabled ‘0’ VCC Internal Core 1.5V to 3.3V Pull-up not in I/O Bank 3 OE VCCIO_0 Pull-up Enable I/O Bank 0 I/O Bank 1 General-Purpose I/O I/O Bank 3 I/O Bank 2 General-Purpose I/O VCCIO_2 OUT VCCIO_1 PIO Special/LVDS I/O VCCIO_3 1.5 to 3.3V General-Purpose I/O PAD iCEGATE HOLD HD Latch inhibits switching for lowest power IN IN GBIN pins optionally connect directly to an associated GBUF global buffer SPI Config Programmable Input/Output SPI_VCC = Statically defined by configuration program I/O Banks PIO blocks are organized into four separate I/O banks, each with its own voltage supply input, as shown in Table 5. The voltage applied to the VCCIO pin on a bank defines the I/O standard used within the bank. Table 53 and Table 54 describe the I/O drive capabilities and switching thresholds by I/O standard. I/O Bank 3, along the left edge of the die, is different than the others and supports specialized I/O standards. Because each I/O bank has its own voltage supply, iCE65P components become the ideal bridging device between different interface standards. For example, the iCE65P device allows a 1.8V-only processor to interface cleanly with a 3.3V bus interface. The iCE65P device replaces external voltage translators. Table 5: Supported Voltages by I/O Bank Bank 0 1 2 3 SPI Device Edge Top Right Bottom Left Bottom Right Supply Input VCCIO_0 VCCIO_1 VCCIO_2 VCCIO_3 SPI_VCC 3.3V Yes Yes Yes Yes Yes 2.5V Yes Yes Yes Yes Yes 1.8V Yes Yes Yes Yes Yes 1.5V Outputs only Outputs only Outputs only Yes No If not connected to an external SPI PROM, the four pins associated with the SPI Master Configuration Interface can be used as PIO pins, supplied by the SPI_VCC input, essentially forming a fifth “mini” I/O bank. If using an SPI Flash PROM, then connect SPI_VCC to 3.3V. SiliconBlue Technologies Corporation www.SiliconBlueTech.com (1.31, 22-APR-2011) 9 iCE65 P-Series Ultra-Low Power mobileFPGA™ Family Table 6 highlights the available I/O standards when using an iCE65P device, indicating the drive current options, and in which bank(s) the standard is supported. I/O Banks 0, 1, 2 and SPI interface support the same standards. I/O Bank 3 has additional capabilities, including support for MDDR memory standards and LVDS differential I/O. Table 6: I/O Standards for I/O Banks 0, 1, 2 and SPI Interface Bank I/O Standard Supply Voltage Drive Current (mA) Attribute Name 5V Input Tolerance LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 outputs 3.3V 3.3V 2.5V 1.8V 1.5V N/A ±11 ±8 ±5 ±4 N/A SB_LVCMOS I/O Bank 3 I/O Bank 3, located along the left edge of the die, has additional special I/O capabilities to support memory components and differential I/O signaling (LVDS). Table 7 lists the various I/O standards supported by I/O Bank 3. The SSTL2 and SSTL18 I/O standards require the VREF voltage reference input pin which is only available on the CB284 package. Also see Table 54 for electrical characteristics. Table 7: I/O Standards for I/O Bank 3 Only I/O Standard Supply Voltage VREF Pin (CB284 or iCE DiCE) Required? Target Drive Current (mA) Attribute Name LVCMOS33 3.3V No ±8 SB_LVCMOS33_8 No ±16 ±12 ±8 ±4 SB_LVCMOS25_16 SB_LVCMOS25_12 SB_LVCMOS25_8 SB_LVCMOS25_4 No ±10 ±8 ±4 ±2 SB_LVCMOS18_10 SB_LVCMOS18_8 SB_LVCMOS18_4 SB_LVCMOS18_2 No ±4 ±2 SB_LVCMOS15_4 SB_LVCMOS15_2 Yes ±16.2 ±8.1 SB_SSTL2_CLASS_2 SB_SSTL2_CLASS_1 Yes ±13.4 ±6.7 SB_SSTL18_FULL SB_SSTL18_HALF No ±10 ±8 ±4 ±2 SB_MDDR10 SB_MDDR8 SB_MDDR4 SB_MDDR2 No N/A SB_LVDS_INPUT LVCMOS25 2.5V LVCMOS18 1.8V LVCMOS15 1.5V SSTL2_II SSTL2_I 2.5V SSTL18_II SSTL18_I 1.8V MDDR 1.8V LVDS 2.5V (1.31, 22-APR-2011) 10 SiliconBlue Technologies Corporation www.SiliconBlueTech.com SiliconBlue Table 8 lists the I/O standards that can co-exist in I/O Bank 3, depending on the VCCIO_3 voltage. Table 8: Compatible I/O Standards in I/O Bank 3 VCCIO_3 Voltage Compatible I/O Standards 3.3V 2.5V 1.8V 1.5V SB_LVCMOS33_8 Any SB_LVCMOS25 SB_SSTL2_Class_2 SB_SSTL2_Class_1 SB_LVDS_INPUT Any SB_LVCMOS18 SB_SSTL18_FULL SB_SSTL18_HALF SB_MDDR10 SB_MDDR8 SB_MDDR4 SB_MDDR2 SB_LVDS_INPUT Any SB_LVCMOS15 Programmable Output Drive Strength Each PIO in I/O Bank 3 offers programmable output drive strength, as listed in Table 8. For the LVCMOS and MDDR I/O standards, the output driver has settings for static drive currents ranging from 2 mA to 16 mA output drive current, depending on the I/O standard and supply voltage. The SSTL18 and SSTL2 I/O standards offer full- and half-strength drive current options Differential Inputs and Outputs All PIO pins support “single-ended” I/O standards, such as LVCMOS. However, iCE65P FPGAs also support differential I/O standards where a single data value is represented by two complementary signals transmitted or received using a pair of PIO pins. The PIO pins in I/O Bank 3 support Low-Voltage Differential Swing (LVDS) and SubLVDS inputs as shown in Figure 7. Differential outputs are available in all four I/O banks. Differential Inputs Only on I/O Bank 3 Differential receivers are required for popular applications such as LVDS and LVPECL clock inputs, camera interfaces, and for various telecommunications standards. Specific pairs of PIO pins in I/O Bank 3 form a differential input. Each pair consists of a DPxxA and DPxxB pin, where “xx” represents the pair number. The DPxxB receives the true version of the signal while the DPxxA receives the complement of the signal. Typically, the resulting signal pair is routed on the printed circuit board (PCB) with matched 50Ω signal impedance. The differential signaling, the low voltage swing, and the matched signal routing are ideal for communicating very-high frequency signals. Differential signals are generally also more tolerant of system noise and generate little EMI themselves. The LVDS input circuitry requires 2.5V on the VCCIO_3 voltage supply. Similarly, the SubLVDS input circuitry requires 1.8V on the VCCIO_3 voltage supply. For electrical specifications, see “Differential Inputs” on page 75. Each differential input pair requires an external 100 Ω termination resistor, as shown in Figure 7. The PIO pins that make up a differential input pair are indicated with a blue bounding box in the footprint diagrams and in the pinout tables. SiliconBlue Technologies Corporation www.SiliconBlueTech.com (1.31, 22-APR-2011) 11 iCE65 P-Series Ultra-Low Power mobileFPGA™ Family Figure 7: Differential Inputs in I/O Bank 3 Impedance-matched signal traces VCCIO_3 = 1.8V or 2.5V DPxxB 100Ω 50Ω 50Ω DPxxA iC65 Differential Input External 100Ω termination resistor 1 0 1 0 Noise pulse affects both traces similarly. Difference between signals remains nearly constant. Differential Outputs in Any Bank Differential outputs are built using a pair of single-ended PIO pins as shown in Figure 8. Each differential I/O pair requires a three-resistor termination network to adjust output characteristic to match those for the specific differential I/O standard. The output characteristics depend on the values of the parallel resistors (RP) and series resistor (RS). Differential outputs must be located in the same I/O tile. Figure 8: Differential Output Pair External output compensation resistor network Impedance-matched signal traces VCCIO_x RS RS 50Ω RP 50Ω iC65 Differential Output Pair 1 0 1 0 Noise pulse affects both traces similarly. Difference is signals remains nearly constant. For electrical characteristics, see “Differential Outputs” on page 75. The PIO pins that make up a differential output pair are indicated with a blue bounding box in the in the tables in “Die Cross Reference” starting on page 67. (1.31, 22-APR-2011) 12 SiliconBlue Technologies Corporation www.SiliconBlueTech.com SiliconBlue Input Signal Path As shown in Figure 6, a signal from a package pin optionally feeds directly into the device, or is held in an input register. The input signal connects to the programmable interconnect resources through the IN signal. Table 9 describes the input behavior, assuming that the output path is not used or if a bidirectional I/O, that the output driver is in its high-impedance state (Hi-Z). Table 9 also indicates the effect of the Power-Saving I/O Bank iCEgate Latch and the Input Pull-Up Resistors on I/O Banks 0, 1, and 2. See Input and Output Register Control per PIO Pair for information about the registered input path. Power-Saving I/O Bank iCEgate Latch To save power, the optional iCEgate latch can selectively freeze the state of individual, non-registered inputs within an I/O bank. Registered inputs are effectively frozen by their associated clock or clock-enable control. As shown in Figure 9, the iCEgate HOLD control signal captures the external value from the associated asynchronous input. The HOLD signal prevents switching activity on the PIO pad from affecting internal logic or programmable interconnect. Minimum power consumption occurs when there is no switching. However, individual pins within the I/O bank can bypass the iCEgate latch and directly feed into the programmable interconnect, remaining active during lowpower operation. This behavior is described in Table 9. The decision on which asynchronous inputs use the iCEgate feature and which inputs bypass it is determined during system design. In other words, the iCEgate function is part of the source design used to create the iCE65P configuration image. Figure 9: Power-Saving iCEgate Latch PIO PAD D HOLD Controlled by configuration image; allows pin-by-pin option to freeze input with iCEgate Q LE Optional iCEgate Latch PAD HOLD Input Follow value on PAD Freeze last value Follow value on PAD Table 9: PIO Non-Registered Input Operations HOLD Operation Data Input Pad Floating, No Pull-up Pad Floating, Pull-up Data Input, Latch Bypassed Pad Floating, No Pull-up, Latch Bypassed Pad Floating, Pull-up, Latch Bypassed Low Power Mode, Hold Last Value iCEgate Latch 0 0 0 X Bitstream Setting Controlled Input Pullby iCEgate? Up Enabled? X X X No X Yes No X PAD Pin Value PAD Z Z PAD IN Input Value to Interconnect PAD Value (Undefined) 1 PAD Value X No No Z (Undefined) X No Yes Z 1 1 Yes X X Last Captured PAD Value There are four iCEgate HOLD controls, one per each I/O bank. The iCEgate HOLD control input originates within the interconnect fabric, near the middle of the I/O edge. Consequently, the HOLD signal is optionally controlled externally through a PIO pin or from other logic within the iCE65P device. SiliconBlue Technologies Corporation www.SiliconBlueTech.com (1.31, 22-APR-2011) 13 iCE65 P-Series Ultra-Low Power mobileFPGA™ Family i For best possible performance, the global buffer inputs (GBIN[7:-0]) connect directly to the their associated global buffers (GBUF[7:0]), bypassing the PIO logic and iCEgate circuitry as shown in Figure 6. Consequently, the direct GBIN-to-GBUF connection cannot be blocked by the iCEgate circuitry. However, it is possible to use iCEgate to block PIO-to-GBUF clock connections. For additional information on using the iCEgate feature, please refer to the following application note. AN002: Using iCEgate Blocking for Ultra-Low Power www.siliconbluetech.com/media/AN2iCEGATErev1.1.pdf Input Pull-Up Resistors on I/O Banks 0, 1, and 2 The PIO pins in I/O Banks 0, 1, and 2 have an optional input pull-up resistor. Pull-up resistors are not provided in I/O Bank 3. During the iCE65P configuration process, the input pull-up resistor is unconditionally enabled and pulls the input to within a diode drop of the associated I/O bank supply voltage (VCCIO_#). This prevents any signals from floating on the circuit board during configuration. After iCE65P configuration is complete, the input pull-up resistor is optional, defined by a configuration bit. The pull-up resistor is also useful to tie off unused PIO pins. The SiliconBlue iCEcube development software defines all unused PIO pins in I/O Banks 0, 1 and 2 as inputs with the pull-up resistor turned on. The pull-up resistor value depends on the VCCIO voltage applied to the bank, as shown in Table 52. No Input Pull-up Resistors on I/O Bank 3 The PIO pins associated with I/O Bank 3 do not have an internal pull-up resistor. To minimize power consumption, tie unused PIO pins in Bank 3 to a known logic level or drive them as a disabled high-impedance output. Input Hysteresis Inputs typically have about 50 mV of hysteresis, as indicated in Table 52. Output and Output Enable Signal Path As shown in Figure 6, a signal from programmable interconnect feeds the OUT signal on a Programmable I/O pad. This output connects either directly to the associated package pin or is held in an optional output flip-flop. Because all flip-flops are automatically reset after configuration, the output from the output flip-flop can be optionally inverted so that an active-Low output signal is held in the disabled (High) state immediately after configuration. Similarly, each Programmable I/O pin has an output enable or three-state control called OE. When OE = High, the OUT output signal drives the associated pad, as described in Table 10. When OE = Low, the output driver is in the high-impedance (Hi-Z) state. The OE output enable control signal itself connects either directly to the output buffer or is held in an optional register. The output buffer is optionally permanently enabled or permanently disabled, either to unconditionally drive output signals, or to allow input-only signals. Table 10: PIO Output Operations (non-registered operation, no inversions) OUT OE Data Output Enable Three-State X 0 Drive Output Data OUT 1* X = don‘t care, 1* = High or unused, Hi-Z = high-impedance, three-stated, floating. Operation PAD Hi-Z OUT See Input and Output Register Control per PIO Pair for information about the registered input path. Input and Output Register Control per PIO Pair PIO pins are grouped into pairs for synchronous control. Registers within pairs of PIO pins share common input clock, output clock, and I/O clock enable control signals, as illustrated in Figure 10. The combinational logic paths are removed from the drawing for clarity. The INCLK clock signal only controls the input flip-flops within the PIO pair. The OUTCLK clock signal controls the output flip-flops and the output-enable flip-flops within the PIO pair. (1.31, 22-APR-2011) 14 SiliconBlue Technologies Corporation www.SiliconBlueTech.com SiliconBlue If desired in the iCE65P application, the INCLK and OUTCLK signals can be connected together using Error! eference source not found.. The IOENA clock-enable input, if used, enables all registers in the PIO pair, as shown in Figure 10. By default, the registers are always enabled. ! Before laying out your printed-circuit board, run the design through the iCEcube development software to verify that your selected pinout complies with these I/O register pairing requirements. See tables in “Die Cross Reference” starting on page 67. Figure 10: PIO Pairs Share Clock and Clock Enable Controls (only registered paths shown for clarity) PIO Pair OUTCLK IOENA 1 INCLK OE IN EN OE 0 = Hi-Z 1 = Output Enabled PAD EN Output Clock OUT I/O Register Enable Input Clock EN EN 0 = Hi-Z 1 = Output Enabled PAD OUT EN IN EN = Statically defined by configuration program The pairing of PIO pairs is most evident in the tables in “Die Cross Reference” starting on page 67. Double Data Rate (DDR) Flip-Flops Each individual PIO pin optionally has two sets of double data rate (DDR) flip-flops; one input pair and one output pair. Figure 11 demonstrates the functionality of the output DDR flip-flop. Two signals from within the iCE65P device drive the DDR output flip-flop. The D_OUT_0 signal is clocked by the rising edge of the OUTCLK signal while the D_OUT_1 signal is clocked by the falling edge of the OUTCLK signal, assuming no optional clock polarity inversion. Internally, the two individual flip-flops are multiplexed together before the data appears at the pad, effectively doubling the output data rate. SiliconBlue Technologies Corporation www.SiliconBlueTech.com (1.31, 22-APR-2011) 15 iCE65 P-Series Ultra-Low Power mobileFPGA™ Family Figure 11: DDR Output Flip-Flop OE IOENA D_OUT_1 D Q 0 D_OUT_0 D Q 1 S EN EN PAD PIO OUTCLK OUTCLK PAD D0 D1 D0 D1 D0 D1 Similarly, Figure 12 demonstrates the DDR input flip-flop functionality. A double data rate (DDR) signal arrives at the pad. Internally, one value is clocked by the rising edge of the INCLK signal and another value is clocked by the falling edge of the INCLK signal. The DDR data stream is effectively de-multiplexed within the PIO pin and presented to the programmable interconnect on D_IN_0 and D_IN_1. Figure 12: DDR Input Flip-Flop IOENA PIO D Q D_IN_1 D Q D_IN_0 EN PAD EN INCLK INCLK PAD D_IN_0 D_IN_1 D0 D1 D0 D0 D1 D0 D0 D1 D1 D0 D1 D1 The DDR flip-flops provide several design advantages. Internally within the iCE65P device, the clock frequency is half the effective external data rate. The lower clock frequency eases internal timing, doubling the clock period, and slashes the clock-related power in half. (1.31, 22-APR-2011) 16 SiliconBlue Technologies Corporation www.SiliconBlueTech.com SiliconBlue Global Routing Resources Global Buffers Each iCE65P component has eight global buffer routing connections, illustrated in Figure 13. There are eight high-drive buffers, connected to the eight low-skew, global lines. These lines are designed primarily for clock distribution but are also useful for other high-fanout signals such as set/reset and enable signals. The global buffers originate either from the Global Buffer Inputs (GBINx) or from programmable interconnect. The associated GBINx pin represents the best pin to drive a global buffer from an external source. However, the application with an iCE65P FPGA can also drive a global buffer via any other PIO pin or from internal logic using the programmable interconnect. If not used in an application, individual global buffers are turned off to save power. Figure 13: High-drive, Low-skew, High-fanout Global Buffer Routing Resources GBUF6 Global Buffer GBUF3 Global Buffer GBIN3 I/O Bank 2 GBIN4 GBIN5 GBIN2 I/O Bank 1 Global Buffer GBUF2 Global Buffer GBUF5 Global Buffer GBUF7 and its associated are best for direct GBUF7 PIO differential clock inputs GBUF4 Global Buffer I/O Bank 3 GBIN6 Global Buffer GBUF1 GBUF0 Global Buffer GBIN7 GBIN1 GBIN0 I/O Bank 0 Table 11 lists the connections between a specific global buffer and the inputs on a Programmable Logic Block (PLB). All global buffers optionally connect to all clock inputs. Any four of the eight global buffers can drive logic inputs to a PLB. Even-numbered global buffers optionally drive the Reset input to a PLB. Similarly, odd-numbered buffers optionally drive the PLB clock-enable input. Table 11: Global Buffer (GBUF) Connections to Programmable Logic Block (PLB) Global Buffer LUT Inputs Clock Clock Enable Reset GBUF0 GBUF1 GBUF2 GBUF3 GBUF4 GBUF5 GBUF6 GBUF7 Yes, any 4 of 8 GBUF buffers Yes Yes Yes Yes Yes Yes Yes Yes Yes No Yes No Yes No Yes No No Yes No Yes No Yes No Yes SiliconBlue Technologies Corporation www.SiliconBlueTech.com (1.31, 22-APR-2011) 17 iCE65 P-Series Ultra-Low Power mobileFPGA™ Family Table 12 and Table 13 list the connections between a specific global buffer and the inputs on a Programmable I/O (PIO) pair. Although there is no direct connection between a global buffer and a PIO output, such a connection is possible by first connecting through a PLB LUT4 function. Again, all global buffers optionally drive all clock inputs. However, even-numbered global buffers optionally drive the clock-enable input on a PIO pair. Table 12: iCE65P04: Global Buffer (GBUF) Connections to Programmable I/O (PIO) Pair Global Buffer GBUF0 GBUF1 GBUF2 GBUF3 GBUF4 GBUF5 GBUF6 GBUF7 Output Connections No (connect through PLB LUT) Input Clock Output Clock Clock Enable Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No Yes No Yes No Yes No Yes Table 13: iCE64L08: Global Buffer (GBUF) Connections to Programmable I/O (PIO) Pair Global Buffer GBUF0 GBUF1 GBUF2 GBUF3 GBUF4 GBUF5 GBUF6 GBUF7 Output Connections No (connect through PLB LUT) Input Clock Output Clock Clock Enable Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No Yes No Yes No Yes No Global Buffer Inputs The iCE65P component has eight specialized GBIN/PIO pins that are optionally direct inputs to the global buffers, offering the best overall clock characteristics. As shown in Figure 14, each GBIN/PIO pin is a full-featured I/O pin but also provides a direct connection to its associated global buffer. The direct connection to the global buffer bypasses the iCEgate input-blocking latch and other PIO input logic. These special PIO pins are allocated two to an I/O Bank, a total of eight. These pins are labeled GBIN0 through GBIN7, as shown in Figure 13 and the pin locations for each GBIN input appear in Table 14. (1.31, 22-APR-2011) 18 SiliconBlue Technologies Corporation www.SiliconBlueTech.com SiliconBlue Table 14: Global Buffer Input Ball Number by Package Global Buffer Input (GBIN) Package Code I/O Bank ‘P04 CB121 D6 C6 ‘P04 CB196 A7 E7 ‘P04 CB284 E10 E11 GBIN0 GBIN1 0 GBIN2 GBIN3 1 F9 F8 F10 G12 L18 K18 GBIN4 GBIN5 2 L9 L8 L7 P5 V12 V11 GBIN6 GBIN7 3 F4 D3 H1 G1 M5 L5 Figure 14: GBIN/PIO Pin GBIN/PIO Pin Enabled ‘1’ Disabled ‘0’ VCCIO 0 = Hi-Z 1 = Output Enabled OE Pull-up not in I/O Bank 3 Pull-up Enable OUT PAD iCEGATE HOLD HD Latch inhibits switching for lowest power IN GBIN pins optionally connect directly to an associated GBUF global buffer Optional connection from internal programmable interconnect. GBUF Differential Global Buffer Input All eight global buffer inputs support single-ended I/O standards such as LVCMOS. Global buffer GBUF7 in I/O Bank 3 also provides an optional direct SubLVDS, LVDS, or LVPECL differential clock input, as shown in Figure 15. The GBIN7 and its associated differential I/O pad accept a differential clock signal. A 100 Ω termination resistor is required across the two pads. Optionally, swap the outputs from the LVDS or LVPECL clock driver to invert the clock as it enters the iCE65P device. Figure 15: LVDS or LVPECL Clock Input 100Ω GBIN7/DP##B LVDS/ LVPECL Clock Driver DP##A SiliconBlue Technologies Corporation www.SiliconBlueTech.com GBUF7 (1.31, 22-APR-2011) 19 iCE65 P-Series Ultra-Low Power mobileFPGA™ Family Table 15 lists the pin or ball numbers for the differential global buffer input by package style. Although this differential input is the only one that connects directly to a global buffer, other differential inputs can connect to a global buffer using general-purpose interconnect, with slightly more signal delay. Table 15: Differential Global Buffer Input Ball Number by Package Differential Global Buffer Input (GBIN) GBIN7/DPxxB DPxxA Package Code I/O Bank 3 ‘P04 CB121 D3 E3 ‘P04 CB196 G1 G2 ‘P04 CB284 L5 L3 Automatic Global Buffer Insertion, Manual Insertion The iCEcube development software automatically assigns high-fanout signals to a global buffer. However, to manual insert a global buffer input/global buffer (GBIN/GBUF) combination, use the SB_IO_GB primitive. To insert just a global buffer (GBUF), use the SB_GB primitive. Global Hi-Z Control The global high-impedance control signal, GHIZ, connects to all I/O pins on the iCE65P device. This GHIZ signal is automatically asserted throughout the configuration process, forcing all user-I/O pins into their high-impedance state. Similarly, the PIO pins can be forced into their high-impedance state via the JTAG controller. Global Reset Control The global reset control signal connects to all PLB and PIO flip-flops on the iCE65P device. The global reset signal is automatically asserted throughout the configuration process, forcing all flip-flops to their defined wake-up state. For PLB flip-flops, the wake-up state is always reset, regardless of the PLB flip-flop primitive used in the application. See Table 3 for more information. The PIO flip-flops are always reset during configuration, although the output flip-flop can be inverted before leaving the iCE65P device, as shown in Figure 10. Phase-Locked Loop (PLL) To support a variety of display, imager, and memory interface applications, the iCE65P FPGA family includes an ultra-low power Phase Locked Loop (PLL), as shown in Figure 16. The iCEcube development software provides three PLL macro variants, depending on whether the clock originates inside the FPGA or from an external source, and whether only the PLL output connects to a global buffer, or whether both the PLL output and the clock input pad, as described in Table 16. Figure 16: Phase-Locked Loop (PLL) PLL LATCHINPUTVALUE DYNAMICDELAY[3:0] EXTFEEDBACK BYPASS RESET REFERENCECLK (1.31, 22-APR-2011) 20 LOCK PLLOUT SiliconBlue Technologies Corporation www.SiliconBlueTech.com SiliconBlue PLL Macro Name Table 16: PLL Macro Types Clock Input GBUF SB_PLL_CORE SB_PLL_PAD SB_PLL_2_PAD FPGA routing PAD PAD PLL output PLL output PLL output GBUF N/A N/A Clock input from pad The PLL provides the following functions for the iCE65P application.  Generates a new output clock frequency  Clock multiplication  Clock division  Clock scaling to maximize performance or to minimize power consumption  De-skews or phase-aligns an output clock to the input reference clock.  Faster input setup time  Faster clock-to-output time  Corrects output clock to have nearly a 50% duty cycle, which is important for Double Data Rate (DDR) applications.  Optionally phase shifts the output clock relative to the input reference clock.  Optimal data sampling within the available bit period  Fixed quadrant phase shifting at 0°, 90°, 180°, and 270°.  Optional fine delay adjustments of up to 2.5 ns (nominal) in 165 ps increments (nominal). Signals Table 17 lists the signal names, direction, and function of each connection to the PLL. Some of the signals have an associated attribute or property, listed in Table 18. Table 17: PLL Signals Signal Name Direction REFERENCECLK RESET BYPASS Input Input Input EXTFEEDBACK Input DYNAMIC_DELAY[3:0] Input LATCHINPUTVALUE Input PLLOUT Output LOCK Output SiliconBlue Technologies Corporation www.SiliconBlueTech.com Description Input reference clock Reset When FEEDBACK_PATH is set to SIMPLE, the BYPASS control selects which clock signal connects to the PLLOUT output. 0 = PLL generated signal 1 = REFERENCECLK External feedback input to PLL. Enabled when FEEDBACK_PATH attribute set to EXTERNAL. Fine delay adjustment control inputs. Enabled when DELAY_ADJUSTMENT_MODE set to DYNAMIC When enabled, forces the PLL into low-power mode; PLL output held static at last input clock value. Set ENABLE ICEGATE_PORTA and PORTB to ‗1‘ to enable. Output from the Phase-Locked Loop (PLL). Connects to programmable interconnect and has optimal connections to global clock buffers GBUF4 and GBUF5. When High, indicates that the PLL output is phase aligned or locked to the input reference clock. (1.31, 22-APR-2011) 21 iCE65 P-Series Ultra-Low Power mobileFPGA™ Family Attributes/Properties Table 18 lists the attributes or properties associated with the PLL and the allowable settings for each attribute.. Table 18: PLL Attributes and Settings Attribute/Property FEEDBACK_PATH Description Selects the feedback path to the PLL Setting SIMPLE DELAY PHASE_AND_DELAY DELAY_ADJUSTMENT_MODE FIXED_DELAY_ADJUSTMENT PLL_OUT_PHASE DIVR DIVF DIVQ RANGE ENABLE_ICEGATE Selects the control input for the fine delay adjustment. Delays the PLLOUT output nominally by (n+1) • 150 ps Sets the constant value for the fine delay adjustment when DELAY_ADJUSTMENT mode set to FIXED Controls the phase alignment of the PLLOUT output relative to the input reference clock; see Figure 18 Divider value for the input clock Divider value for feedback Divider value for the VCO output, generates PLLOUT Controls the PLL operating range Enables iCEgate to disable GBUF transitions EXTERNAL FIXED DYNAMIC 0, 1, ..., 15 NONE 0deg 90deg 180deg 270deg 0, 1, ..., 15 0, 1, ..., 63 0, 1, ..., 5 Description Feedback directly from VCO Feedback from VCO through fine delay adjustment Feedback from VCO through the fine delay adjustment and phase shifter; feedback is further divided by four Feedback from EXTFEEDBACK input Delay controlled by FIXED_DELAY_ADJUSTMENT setting Delay controlled by current value of DYNAMIC_DELAY[3:0] Delays the PLLOUT output by specified setting Phase alignment disabled, no dutycycle correction 0° phase shift (no phase shift) 90° phase shift (quarter cycle shift) 180° phase shift (half-cycle shift) 270° phase shift (three-quarter cycle shift) These attributes control the PLL output frequency. See Equation 2 and Equation 3 and the Frequency Synthesis spreadsheet. 0, 1, ..., 7 0 1 GBUF disabled GBUF enabled Clock Input Requirements For proper operation, the PLL requires ...     A stable monotonic (single frequency) reference clock input. The reference clock input must be within the input clock frequency range, FREF, specified in Table 60. The reference clock must have a duty cycle that meets the requirement specified in Table 60. The jitter on the reference input clock must not exceed the limits specified in Table 60. PLL Output Requirements The PLL output clock, PLLOUT requires the following restrictions.  The PLLOUT output frequency must be within the limits specified in Table 60.  The PLLOUT output is not valid or stable until the PLL‟s LOCK output remains High. (1.31, 22-APR-2011) 22 SiliconBlue Technologies Corporation www.SiliconBlueTech.com SiliconBlue Voltage Controlled Oscillator Supply Inputs The phase-locked loop (PLL) uses separate analog supply inputs for the voltage-controlled oscillator (VCO). Table 19: PLL Supply Ball Numbers by Package Package Code ColdBoot Select CB121 L6 L7 PLLGND PLLVCC CB196 M6 N6 CB284 Y9 Y10 Clock Multiplication and Division The PLL optionally multiplies and/or divides the input reference clock to generate a PLLOUT output clock of another frequency. The output frequency depends on the frequency of the REFERENCLK input clock and the settings for the DIVR, DIVF, DIVQ, RANGE, and FEEDBACK_PATH attribute settings, as indicated in Figure 17. Figure 17: PLL Frequency Synthesis PLLVCC REFERENCE CLK Phase Detector DIVR RANGE Input Divider PLLGND DIVQ VoltageControlled Oscillator (VCO) Low-Pass Filter VCO Divider SIMPLE DIVF DELAY Feedback Divider FEEDBACK_PATH Fine Delay Adjust EXTFEED BACK PLLOUT Phase Shifter ÷ 4 0 0 , 90 , 180 , 270 PHASE_AND_DELAY EXTERNAL The PLL‟s phase detector and Voltage Controlled Oscillator (VCO) synthesize a new output clock frequency based on the attribute settings. The VCO is an analog circuit and has independent voltage supply and ground connections labeled PLLVCC and PLLGND. The simplest method to determine the optimal settings for a specific application is to use the Frequency Synthesis Spreadsheet PLLOUT Frequency for All Modes Except FEEDBACK_PATH = SIMPLE For all the FEEDBACK_PATH modes, except SIMPLE, the PLLOUT frequency is the result of Equation 2. FPLLOUT  FREFERNCECLK  (DIVF  1) DIVR  1 [Equation 2] PLLOUT Frequency for FEEDBACK_PATH = SIMPLE If the SIMPLE feedback mode, the PLL feedback signal taps directly from the output of the VCO, before the final divider stage. Consequently, the PLL output frequency has an additions divider step, DIVQ, contributed by the final divider step as shown in Equation 3. (DIVF, DIVQ and DIVR are binary) FPLLOUT  FREFERNCECLK  (DIVF  1) 2 ( DIVQ)  (DIVR  1) [Equation 3] Fixed Quadrant Phase Shift The PLL optional phase feature shifts the PLLOUT output by a specified quadrant or quarter clock cycle as shown in Figure 18 and Table 20. The quadrant phase shift option is only available when the FEEDBACK_PATH attribute is set to PHASE_AND_DELAY. SiliconBlue Technologies Corporation www.SiliconBlueTech.com (1.31, 22-APR-2011) 23 iCE65 P-Series Ultra-Low Power mobileFPGA™ Family Table 20: PLL Phase Shift Options PLLOUT_PHASE Duty Cycle Correction Phase Shift (Degrees) Fraction Clock Cycle NONE No 0° None 0deg Yes 0° None 90deg Yes 90° Quarter Cycle 180deg Yes 180° Half Cycle 270deg Yes 270° Three-quarter Cycle Figure 18: Fixed Quadrant Phase Shift Control (PLLOUT_PHASE) ¼ ½ ¾ Clock Period 0° 90° 180° 270° 0° REFERENCECLK Duty-cycle correction PLLOUT PLLOUT_PHASE="0deg" PLLOUT PLLOUT_PHASE="90deg" PLLOUT PLLOUT_PHASE="180deg" PLLOUT PLLOUT_PHASE="270deg" 90° 180° 270° Unlike the Fine Delay Adjustment, the quadrant phase shifter always shifts by a fixed phase angle. The resulting phase shift, measured in delay, depends on the clock period and the PLLOUT_PHASE phase shift setting, as shown in Equation 4. Delay  Phase_Shift  Clock_Period 360 [Equation 4] Fine Delay Adjustment As shown in Figure 19, the PLL provides an optional fine delay adjustment that controls the delay of the PLLOUT output relative to the input reference clock, to an external feedback signal, or relative to the selected quadrant phase shifted clock. The delay is adjusted by selecting one or more of the 16 delay taps. Each tap is approximately 165 ps. The fine delay adjustment option is available when the FEEDBACK_PATH attribute is set to DELAY, PHASE_AND_DELAY, or EXTERNAL, as shown in Figure 19 and Figure 17. (1.31, 22-APR-2011) 24 SiliconBlue Technologies Corporation www.SiliconBlueTech.com SiliconBlue Figure 19: Fine Delay Adjust Controls Clock Reference Buffer delay = ~165 ps ="DELAY" PLLOUT EXTFEEDBACK ="EXTERNAL" ="PHASE_AND_DELAY" 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Quadrant Phase ="0deg" FEEDBACK_DELAY ="90deg" PLLOUT ="180deg" ="270deg" PLLOUT_PHASE FIXED_DELAY_ADJUSTMENT 3 2 1 0 DYNAMICDELAY[3:0] Delay Adjusment ="FIXED" Fine Delay Adjustment Control ="DYNAMIC" DELAY_ADJUSTMENT_MODE Fine Adjustment Control The number of delay taps is controlled either statically using the FIXED_DELAY_ADJUSTMENT option or dynamically by the application using the PLL‟s DYNAMIC_DELAY[3:0] inputs, as described in Table 21. Table 21: Fine Delay Adjustment Control DELAY_ADJUSTMENT_MODE Setting Adjustment Control FIXED FIXED_DELAY_ADJUSTMENT attribute setting DYNAMIC DYNAMIC_DELAY[3:0] control inputs Fine Adjustment Delay The resulting nominal fine adjustment delay value is shown in Equation 5, where n is either the value of the FIXED_DELAY_ADJUSTMENT attribute setting or the dynamic binary value presented on the DYNAMIC_DELAY[3:0] inputs. The actual delay varies slightly due to the slight differences in the delay tap buffer delay. Fine Delay Adjustment (nominal) = (n + 1) • 165 ps [Equation 5] Phase Angle Equivalent The fine delay adjustment feature always injects an actual delay value, not a fixed phase angle like the Fixed Quadrant Phase Shift feature. Use Equation 6 to convert the fine adjustment delay to a resulting phase angle. Phase_Shift  Fine_Delay_Adjustment  360 Clock_Period [Equation 6] Low Power Mode The phase-lock loop (PLL) has low operating power by default. The PLL can be dynamically disabled to further reduce power. The low-power mode must first be enabled by setting the ENABLE_ICEGATE attribute to „1‟. Once enabled, use the LATCHINPUTVALUE to control the PLL‟s operation, as shown in Table 22. The PLL must reacquire the input clock and LOCK when LATCHINPUTVALUE returns from „1‟ to „0‟, external feedback is used and path goes out into the fabric. Table 22: PLL LATCHINPUTVALUE Control ENABLE_ICEGATE Attribute LATCHINPUTVALUE Input 0 Don‘t care 0 1 1 SiliconBlue Technologies Corporation www.SiliconBlueTech.com Function PLL is always enabled PLL is enabled and operating PLL is in low-power mode; PLLOUT output holds last clock state (1.31, 22-APR-2011) 25 iCE65 P-Series Ultra-Low Power mobileFPGA™ Family RAM Each iCE65P device includes multiple high-speed synchronous RAM blocks (RAM4K), each 4Kbit in size. As shown in Table 23 a single iCE65P integrates between 16 to 96 such blocks. Each RAM4K block is generically a 256word deep by 16-bit wide, two-port register file, as illustrated in Figure 20. The input and output connections, to and from a RAM4K block, feed into the programmable interconnect resources. Figure 20: RAM4K Memory Block Write Port Read Port WDATA[15:0] RDATA[15:0] MASK[15:0] WADDR[7:0] WE RAM4K RAM Block (256x16) RADDR[7:0] RE WCLKE RCLKE WCLK RCLK Table 23: RAM4K Blocks per Device Device RAM4K Blocks Default Configuration iCE65P04 20 256 x 16 RAM Bits per Block 4K (4,096) Block RAM Bits 80K Using programmable logic resources, a RAM4K block implements a variety of logic functions, each with configurable input and output data width.  Random-access memory (RAM)  Single-port RAM with a common address, enable, and clock control lines  Two-port RAM with separate read and write control lines, address inputs, and enable     Register file and scratchpad RAM First-In, First-Out (FIFO) memory for data buffering applications Circuit buffer A 256-deep by 16-wide ROM with registered outputs, contents loaded during configuration  Sixteen different 8-input look-up tables  Function or waveform tables such as sine, cosine, etc.  Correlators or pattern matching operations  Counters, sequencers As pictured in Figure 20, a RAM4K block has separate write and read ports, each with independent control signals. Table 24 lists the signals for both ports. Additionally, the write port has an active-Low bit-line write-enable control; optionally mask write operations on individual bits. By default, input and output data is 16 bits wide, although the data width is configurable using programmable logic and, if needed, multiple RAM4K blocks. The WCLK and RCLK inputs optionally connect to one of the following clock sources.  The output from any one of the eight Global Buffers, or  A connection from the general-purpose interconnect fabric (1.31, 22-APR-2011) 26 SiliconBlue Technologies Corporation www.SiliconBlueTech.com SiliconBlue The data contents of the RAM4K block are optionally pre-loaded during iCE65P device configuration. If the RAM4K blocks are not pre-loaded during configuration, then the resulting configuration bitstream image is smaller. However, if an uninitialized RAM4K block is used in the application, then the application must initialize the RAM contents to guarantee the data value. See Table 59 for detailed timing information. Signals Table 24 lists the signal names, direction, and function of each connection to the RAM4K block. See also Figure 20. Table 24: RAM4K Block RAM Signals Signal Name WDATA[15:0] MASK[15:0] Direction Input Input WADDR[7:0] WE WCLKE WCLK RDATA[15:0] RADDR[7:0] RE RCLKE RCLK Input Input Input Input Output Input Input Input Input Description Write Data input. Masks write operations for individual data bit-lines. 0 = Write bit; 1 = Don‘t write bit Write Address input. Selects one of 256 possible RAM locations. Write Enable input. Write Clock Enable input. Write Clock input. Default rising-edge, but with falling-edge option. Read Data output. Read Address input. Selects one of 256 possible RAM locations. Read Enable input. Read Clock Enable input. Read Clock input. Default rising-edge, but with falling-edge option. Write Operations Figure 21 shows the logic involved in writing a data bit to a RAM location. Table 25 describes various write operations for a RAM4K block. By default, all RAM4K write operations are synchronized to the rising edge of WCLK although the clock is invertible as shown in Figure 21. Figure 21: RAM4K Bit Write Logic RAM[LOCATION][BIT] D WDATA[BIT] MASK[BIT] WE DECODE LOCATION WADDR[7:0] EN WCLKE WCLK When the WCLKE signal is Low, the clock to the RAM4K block is disabled, keeping the RAM in its lowest power mode. SiliconBlue Technologies Corporation www.SiliconBlueTech.com (1.31, 22-APR-2011) 27 iCE65 P-Series Ultra-Low Power mobileFPGA™ Family Table 25: RAM4K Write Operations WDATA[15:0] MASK[15:0] WADDR[7:0] Data X Mask Bit X Address X WE Write Enable X X WDATA[i] X MASK[i] = 0 X WADDR X MASK[i] = 1 WADDR Operation Disabled Disabled Disabled Write Data Masked Write WCLK 0 1 WCLKE Clock Enable X 0 X 1 1 1 ↑ Clock 0 X X ↑ RAM Location No change No change No change RAM[WADDR][i] = WDATA[i] RAM[WADDR][i] = No change To write data into the RAM4K block, perform the following operations.  Supply a valid address on the WADDR[7:0] address input port  Supply valid data on the WDATA[15:0] data input port  To write or mask selected data bits, set the associated MASK input port accordingly. For example, write operations on data bit D[i] are controlled by the associated MASK[i] input.  MASK[i] = 0: Write operations are enabled for data line WDATA[i]  MASK[i] = 1: Mask write operations are disabled for data line WDATA[i]  Enable the RAM4K write port (WE = 1)  Enable the RAM4K write clock (WCLKE = 1)  Apply a rising clock edge on WCLK (assuming that the clock is not inverted) Read Operations Figure 22 shows the logic involved in reading a location from RAM. Table 26 describes various read operations for a RAM4K block. By default, all RAM4K read operations are synchronized to the rising edge of RCLK although the clock is invertible as shown in Figure 22. Figure 22: RAM4K Read Logic Select Location Output Register RAM[LOCATION] Q D Q RDATA[15:0] EN RADDR[7:0] RE RCLKE RCLK (1.31, 22-APR-2011) 28 SiliconBlue Technologies Corporation www.SiliconBlueTech.com SiliconBlue Operation After configuration, before first valid Read Data operation Disabled Disabled Disabled Read Data Table 26: RAM4K Read Operations RADDR[7:0] RE RCLKE Read Clock Address Enable Enabe RCLK Clock RDATA[15:0] X X X X Undefined X X X 0 1 X 0 X 1 0 X X ↑ No Change No Change No change RAM[RADDR] X RADDR To read data from the RAM4K block, perform the following operations.  Supply a valid address on the RADDR[7:0] address input port  Enable the RAM4K read port (RE = 1)  Enable the RAM4K read clock (RCLKE = 1)  Apply a rising clock edge on RCLK  After the clock edge, the RAM contents located at the specified address (RADDR) appear on the RDATA output port Read Data Register Undefined Immediately after Configuration Unlike the flip-flops in the Programmable Logic Blocks and Programmable I/O pins, the RDATA[15:0] read data output register is not automatically reset after configuration. Consequently, immediately following configuration and before the first valid Read Data operation, the initial RDATA[15:0] read value is undefined. Pre-loading RAM Data The data contents for a RAM4K block can be optionally pre-loaded during iCE65P configuration. If not pre-loaded during configuration, then the RAM contents must be initialized by the iCE65P application before the RAM contents are valid. Pre-loading the RAM data in the configuration bitstream increases the size of the configuration image accordingly. RAM Contents Preserved during Configuration RAM contents are preserved (write protected) during configuration, assuming that voltage supplies are maintained throughout. Consequently, data can be passed between multiple iCE65P configurations by leaving it in a RAM4K block and then skipping pre-loading during the subsequent reconfiguration. See “Cold Boot Configuration Option” and “Warm Boot Configuration Option” for more information. Low-Power Setting To place a RAM4K block in its lowest power mode, keep WCLKE = 0 and RCLKE = 0. In other words, when not actively using a RAM4K block, disable the clock inputs. SiliconBlue Technologies Corporation www.SiliconBlueTech.com (1.31, 22-APR-2011) 29 iCE65 P-Series Ultra-Low Power mobileFPGA™ Family Device Configuration As described in Table 27, iCE65P components are configured for a specific application by loading a binary configuration bitstream image, generated by the SiliconBlue development system. For high-volume applications, the bitstream image is usually permanently programmed in the on-chip Nonvolatile Configuration Memory (NVCM). However, the bitstream image can also be stored external in a standard, low-cost commodity SPI serial Flash PROM. The iCE65P component can automatically load the image using the SPI Master Configuration Interface. Similarly, the iCE65P configuration data can be downloaded from an external processor, microcontroller, or DSP processor using an SPI-like serial interface or an IEEE 1149 JTAG interface. Table 27: iCE65P Device Configuration Modes Mode Analogy NVCM ASIC Configuration Data Source SPI Flash Microprocessor SPI Peripheral Processor Peripheral Configured by external device, such as a processor, microcontroller, or DSP using practically any data source, such as system Flash, a disk image, or over a network connection. JTAG JTAG JTAG configuration requires sending a special command sequence on the SPI interface to enable JTAG configuration. Configuration is controlled by and external device. Internal, lowest-cost, secure, one-time programmable Nonvolatile Configuration Memory (NVCM) External, low-cost, commodity, SPI serial Flash PROM Configuration Mode Selection The iCE65P configuration mode is selected according to the following priority described below and illustrated in Figure 23.  After exiting the Power-On Reset (POR) state or when CRESET_B returns High after being held Low for 250 ns or more, the iCE65P FPGA samples the logical value on its SPI_SS_B pin. Like other programmable I/O pins, the SPI_SS_B pin has an internal pull-up resistor (see Input Pull-Up Resistors on I/O Banks 0, 1, and 2).  If the SPI_SS_B pin is sampled as a logic „1‟ (High), then …  Check if the iCE65P is enabled to configure from the Nonvolatile Configuration Memory (NVCM). If the iCE65P device has NVCM memory („F‟ ordering code) but the NVCM is yet unprogrammed, then the iCE65P device is not enabled to configure from NVCM. Conversely, if the NVCM is programmed, the iCE65P device will configure from NVCM.  If enabled to configure from NVCM, the iCE65P device configures itself using the Nonvolatile Configuration Memory (NVCM).  If not enabled to configure from NVCM, then the iCE65P FPGA configures using the SPI Master Configuration Interface.  If the SPI_SS_B pin is sampled as a logic „0‟ (Low), then the iCE65P device waits to be configured from an external controller or from another iCE65P device in SPI Master Configuration Mode using an SPI-like interface. (1.31, 22-APR-2011) 30 SiliconBlue Technologies Corporation www.SiliconBlueTech.com SiliconBlue Figure 23: Device Configuration Control Flow Power-Up CDONE = 0 No iCE65 checks that all required supply voltages are within acceptable range Is Power-On Reset (POR) Released? Yes No Holding CRESET_B Low delays the start of configuration CRESET_B = High? of SPI_SS_B Yes State pin sampled No Configure Configureas from SPI SPI_SS_B = High? Yes Periphal NVCM A device with an unprogrammed NVCM is not enabled for configuration. NVCM Enabled for Configuration? Yes Configure from NVCM No Configure from SPI Flash PROM CDONE = 1 No CRESET_B = Low? After configuration ends, pulse the CRESET_B pin Low for 250 ns or longer to restart configuration process or cycle the power Yes Configuration Image Size Table 28 shows the number of memory bits required to configure an iCE65P device. Two values are provided for each device. The “Logic Only” value indicates the minimum configuration size, the number of bits required to configure only the logic fabric, leaving the RAM4K blocks uninitialized. The “Logic + RAM4K” column indicates the maximum configuration size, the number of bits to configure the logic fabric and to pre-initialize all the RAM4K blocks. Table 28: iCE65P Configuration Image Size (Kbits) Device MINIMUM Logic Only (RAM4K not initialized) MAXIUM Logic + RAM4K (RAM4K pre-initialized) iCE65P04 453 Kbits 533 Kbits SiliconBlue Technologies Corporation www.SiliconBlueTech.com (1.31, 22-APR-2011) 31 iCE65 P-Series Ultra-Low Power mobileFPGA™ Family Nonvolatile Configuration Memory (NVCM) All standard iCE65P devices have an internal, nonvolatile configuration memory (NVCM). The NVCM is large enough to program a complete iCE65P device, including initializing all RAM4K block locations (MAXIMUM column in Table 28). The NVCM memory also has very high programming yield due to extensive error checking and correction (ECC) circuitry. The NVCM is ideal for cost-sensitive, high-volume production applications, saving the cost and board space associated with an external configuration PROM. Furthermore, the NVCM provides exceptional design security, protecting critical intellectual property (IP). The NVCM contents are entirely contained within the iCE65P device and are not readable once protected by the one-time programmable Security bits. Furthermore, there is no observable difference between a programmed or un-programmed memory cell using optical or electron microscopy. The NVCM memory has a programming interface similar to a 25-series SPI serial Flash PROM. Consequently, it can be programmed using standard device programmers before or after circuit board assembly or programmed in-system from a microprocessor or other intelligent controller. Configuration Control Signals The iCE65P configuration process is self-timed and controlled by a few internal signals and device I/O pins, as described in Table 29. Table 29: iCE65P Configuration Control Signals Signal Name POR OSC CRESET_B CDONE Direction Internal control Internal control Input Open-drain Output Description Internal Power-On Reset (POR) circuit. Internal configuration oscillator. Configuration Reset input. Active-Low. No internal pull-up resistor. Configuration Done output. Permanent, weak pull-up resistor to VCCIO_2. The Power-On Reset circuit, POR, automatically resets the iCE65P component to a known state during power-up (cold boot). The POR circuit monitors the relevant voltage supply inputs, as shown in Figure 25. Once all supplies exceed their minimum thresholds, the configuration controller can start the configuration process. The configuration controller begins configuring the iCE65P device, clocked by the Internal Oscillator, OSC. The OSC oscillator continues controlling configuration unless the iCE65P device is configured using the SPI Peripheral Configuration Interface. Figure 24: iCE65P Configuration Control Pins Optional Pull-up Required if driven by open-drain output VCCIO_2 Optional Pull-up SiliconBlue iCE65 Recommended if driving another device VCCIO_2 I/O Bank 2 10 kΩ CRESET_B Rising edge starts Pulse configuration process. CRESET_B Low for 200 ns to restart configuration Low resets iCE65 10 kΩ CDONE Configured PIOs activate 49 configuration clock cycles after CDONE goes High Unconfigured Figure 24 shows the two iCE65P configuration control pins, CRESET_B and CDONE. Table 30 lists the Ball numbers for the configuration control pins by package. When driven Low for at least 200 ns, the dedicated Configuration Reset input, CRESET_B, resets the iCE65P device. When CRESET_B returns High, the iCE65P FPGA restarts the configuration process from its power-on conditions (Cold Boot). The CRESET_B pin is a pure input with no internal pull-up resistor. If driven by open-drain driver or un-driven, then connect the CRESET_B pin to a 10 kΩ pull-up resistor connected to the VCCIO_2 supply. (1.31, 22-APR-2011) 32 SiliconBlue Technologies Corporation www.SiliconBlueTech.com SiliconBlue Table 30: Configuration Control Ball Numbers by Package Configuration Control Pins Package Code CB121 K7 J7 CRESET_B CDONE CB196 L10 M10 CB284 R14 T14 The iCE65P device signals the end of the configuration process by actively turning off the internal pull-down transistor on the Configuration Done output pin, CDONE. The pin has a permanent, weak internal pull-up resistor to the VCCIO_2 rail. If the iCE65P device drives other devices, then optionally connect the CDONE pin to a 10 kΩ pull-up resistor connected to the VCCIO_2 supply. The PIO pins activate according to their configured function after 49 configuration clock cycles. The internal oscillator is the configuration clock source for the SPI Master Configuration Interface and when configuring from Nonvolatile Configuration Memory (NVCM). When using the SPI Peripheral Configuration Interface, the configuration clock source is the SPI_SCK clock input pin. Internal Oscillator During SPI Master or NVCM configuration mode, the controlling clock signal is generated from an internal oscillator. The oscillator starts operating at the Default frequency. During the configuration process, however, bit settings within the configuration bitstream can specify a higher-frequency mode in order to maximize SPI bandwidth and reduce overall configuration time. See Table 61: Internal Oscillator Frequency on page 81 for the specified oscillator frequency range. Using the SPI Master Configuration Interface, internal oscillator controls all the interface timing and clocks the SPI serial Flash PROM via the SPI_SCK clock output pin. The oscillator output, which also supplies the SPI SCK clock output during the SPI Flash configuration process, has a 50% duty cycle. Internal Device Reset Figure 25 presents the various signals that internally reset the iCE65P internal logic.  Power-On Reset (POR)  CRESET_B Pin  JTAG Interface Figure 25: iCE65P Internal Reset Circuitry Device Pins SPI_VCC Internal Voltage Thresholds SPI_VCCT Power-on Reset (POR) Time-out Delay VCC VCCT VCCIO_2 VCCIO_2T VPP_2V5 VPP_2V5T CRESET_B SiliconBlue Technologies Corporation www.SiliconBlueTech.com Internal Reset Glitch Filter (1.31, 22-APR-2011) 33 iCE65 P-Series Ultra-Low Power mobileFPGA™ Family Power-On Reset (POR) The Power-on Reset (POR) circuit monitors specific voltage supply inputs and holds the device in reset until all the relevant supplies exceed the internal voltage thresholds. The SPI_VCC supply also has an additional time-out delay to allow an attached SPI serial PROM to power up properly. Table 31 shows the POR supply inputs. The Nonvolatile Configuration Memory (NVCM) requires that the VPP_2V5 supply be connected, even if the application does not use the NVCM. Table 31: Power-on Reset (POR) Voltage Resources Supply Rail iCE65P Production Devices VCC SPI_VCC VCCIO_1 VCCIO_2 VPP_2V5 Yes Yes No Yes Yes CRESET_B Pin The CRESET_B pin resets the iCE65P internal logic when Low. JTAG Interface Specific command sequences also reset the iCE65P internal logic. SPI Master Configuration Interface All iCE65P devices, including those with NVCM, can be configured from an external, commodity SPI serial Flash PROM, as shown in Figure 26. The SPI configuration interface is essentially its own independent I/O bank, powered by the VCC_SPI supply input. Presently, most commercially-available SPI serial Flash PROMs require a 3.3V supply. Figure 26: iCE65P SPI Master Configuration Interface +3.3V SPI_VCC 10 kΩ SPI_SO SiliconBlue iCE65 (SPI bank) SPI_SI SPI_SS_B Commodity SPI Serial Flash PROM SPI_SCK The SPI configuration interface is used primarily during development before mass production, where the configuration is then permanently programmed in the NVCM configuration memory. However, the SPI interface can also be the primary configuration interface allowing easy in-system upgrades and support for multiple configuration images. The SPI control signals are defined in Table 32. Table 33 lists the SPI interface ball or pins numbers by package. Table 32: SPI Master Configuration Interface Pins (SPI_SS_B High before Configuration) Signal Name SPI_VCC SPI_SO SPI_SI SPI_SS_B SPI_SCK (1.31, 22-APR-2011) 34 Direction Supply Output Input Output Output SPI SPI SPI SPI SPI Description Flash PROM voltage supply input. Serial Output from the iCE65P device. Serial Input to the iCE65P device, driven by the select SPI serial Flash PROM. Slave Select output from the iCE65P device. Active Low. Slave Clock output from the iCE65P device. SiliconBlue Technologies Corporation www.SiliconBlueTech.com SiliconBlue After configuration, the SPI port pins are available to the user-application as additional PIO pins, supplied by the SPI_VCC input voltage, essentially providing a fifth “mini” I/O bank. Table 33: SPI Interface Ball Numbers by Package Package Code SPI Interface CB121 J10 J8 K8 J9 K9 SPI_VCC PIOS/SPI_SO PIOS/SPI_SI PIOS/SPI_SS_B PIOS/SPI_SCK CB196 L11 M11 P11 P13 P12 CB284 R15 T15 V15 V17 V16 SPI PROM Requirements The iCE65P mobileFPGA SPI Flash configuration interface supports a variety of SPI Flash memory vendors and product families. However, SiliconBlue Technologies does not specifically test, qualify, or otherwise endorse any specific SPI Flash vendor or product family. The iCE65P SPI interface supports SPI PROMs that they meet the following requirements.  The PROM must operate at 3.3V or 2.5V in order to trigger the iCE65P FPGA‟s power-on reset circuit.  The PROM must support the 0x0B Fast Read command, using a 24-bit start address and has 8 dummy bits before the PROM provides first data (see Figure 28: SPI Fast Read Command).  The PROM must have enough bits to program the iCE65P device (see Table 34: Smallest SPI PROM Size (bits), by Device, by Number of Images).  The PROM must support data operations at the upper frequency range for the selected iCE65P internal oscillator frequency (see Table 61). The oscillator frequency is selectable when creating the FPGA bitstream image.  For lowest possible power consumption after configuration, the PROM should also support the 0xB9 Deep Power Down command and the 0xAB Release from Deep Power-down Command (see Figure 27 and Figure 29). The low-power mode is optional.  The PROM must be ready to accept commands 10 µs after meeting its power-on conditions. In the PROM data sheet, this may be specified as tVSL or tVCSL. It is possible to use slower PROMs by holding the CRESET_B input Low until the PROM is ready, then releasing CRESET_B, either under program control or using an external power-on reset circuit. The SiliconBlue iCEman65 development board and associated programming software uses an ST Micro/Numonyx M25Pxx SPI serial Flash PROM. SPI PROM Size Requirements Table 34 lists the minimum SPI PROM size required to configure an iCE65P device. Larger PROM sizes are allowed, but not required unless the end application uses the additional space. SPI serial PROM sizes are specified in bits. For each device size, the table shows the required minimum PROM size for “Logic Only” (no BRAM initialization) and “Logic + RAM4K” (RAM4K blocks pre-initialized). Furthermore, the table shows the PROM size for varying numbers of configuration images. Most applications will use a single image. Applications that use the Cold Boot or Warm Boot features may use more than one image. Table 34: Smallest SPI PROM Size (bits), by Device, by Number of Images Device iCE65P04 1 Image Logic Logic + Only RAM4K 512K 1M SiliconBlue Technologies Corporation www.SiliconBlueTech.com 2 Images Logic Logic + Only RAM4K 1M 2M 3 Images Logic Logic + Only RAM4K 2M 2M 4 Images Logic Logic + Only RAM4K 2M 4M (1.31, 22-APR-2011) 35 iCE65 P-Series Ultra-Low Power mobileFPGA™ Family Enabling SPI Configuration Interface To enable the SPI configuration mode, the SPI_SS_B pin must be allowed to float High. The SPI_SS_B pin has an internal pull-up resistor. If SPI_SS_B is Low, then the iCE65P component defaults to the SPI Slave configuration mode. SPI Master Configuration Process The iCE65P SPI Master Configuration Interface supports a variety of modern, high-density, low-cost SPI serial Flash PROMs. Most modern SPI PROMs include a power-saving Deep Power-down mode. The iCE65P component exploits this mode for additional system power savings. The iCE65P SPI interface starts by driving SPI_SS_B Low, and then sends a Release from Power-down command to the SPI PROM, hexadecimal command code 0xAB. Figure 27 provides an example waveform. This initial command wakes up the SPI PROM if it is already in Deep Power-down mode. If the PROM is not in Deep Power-down mode, the extra command has no adverse affect other than that it requires a few additional microseconds during the configuration process. The iCE65P device transmits data on the SPI_SO output, on the falling edge of the SPI_SCK output. The SPI PROM does not provide any data to the iCE65P device‟s SPI_SI input. After sending the last command bit, the iCE65P device de-asserts SPI_SS_B High, completing the command. The iCE65P device then waits a minimum of 10 µS before sending the next SPI PROM command. Figure 27: SPI Release from Deep Power-down Command SPI_SCK SPI_SS_B SPI_SO 1 0 1 0 1 0 1 1 0xAB Release from Deep Power-down Figure 28 illustrates the next command issued by the iCE65P device. The iCE65P SPI interface again drives SPI_SS_B Low, followed by a Fast Read command, hexadecimal command code 0x0B, followed by a 24-bit start address, transmitted on the SPI_SO output. The iCE65P device provides data on the falling edge of SPI_SS_B. Upon initial power-up, the start address is always 0x00_0000. After waiting eight additional clock cycles, the iCE65P device begins reading serial data from the SPI PROM. Before presenting data, the SPI PROM‟s serial data output is high-impedance. The SPI_SI input pin has an internal pull-up resistor and sees high-impedance as logic „1‟. Figure 28: SPI Fast Read Command SPI_SCK 0 0 0 0 1 0 1 1 X X X X X X X X 0x0B 24-bit Start Address Don’t Care Fast Read SPI_SI PROM output is Hi-Z. Pulled High in SPI_SI pin via internal pull-up resistor. Dummy Byte D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 SPI_SO A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 SPI_SS_B Data Byte 0 The external SPI PROM supplies data on the falling edge of the iCE65P device‟s SPI_SCK clock output. The iCE65P device captures each PROM data value on the SPI_SI input, using the rising edge of the SPI_SCK clock signal. The SPI PROM data starts at the 24-bit address presented by the iCE65P device. PROM data is serially output, byte by byte, with most-significant bit, D7, presented first. The PROM automatically increments an internal byte counter as long as the PROM is selected and clocked. (1.31, 22-APR-2011) 36 SiliconBlue Technologies Corporation www.SiliconBlueTech.com SiliconBlue After transferring the required number configuration data bits, the iCE65P device ends the Fast Read command by de-asserting its SPI_SS_B PROM select output, as shown in Figure 29. To conserve power, the iCE65P device then optionally issues a final Deep Power-down command, hexadecimal command code 0xB9. After de-asserting the SPI_SS_B output, the SPI PROM enters its Deep Power-down mode. The final power-down step is optional; the application may wish to use the SPI PROM and can skip this step, controlled by a configuration option. Figure 29: Final Configuration Data, SPI Deep Power-down Command SPI_SCK SPI_SS_B SPI_SO 1 0 1 1 1 0 0 1 0xB9 SPI_SI D7 D6 D5 D4 D3 D2 D1 D0 Deep Power-down Last Data Byte Fast Read data Cold Boot Configuration Option By default, the iCE65P FPGA is programmed with a single configuration image, either from internal NVCM memory, from an external SPI Flash PROM, or externally from a processor or microcontroller. Figure 30: ColdBoot and WarmBoot Configuration At power-up or after reset CBSEL1 CBSEL0 CRESET_B Jump based on settings Cold Boot Control Cold/Warm Boot Applet 0 Enable/Disable Cold Boot Enable/Disable Warm Boot Jump vector addresses (4) Vector Address 0 Power-On Reset (0,0) Configuration Image 0 SB_WARMBOOT Vector Address 1 S1 S0 BOOT Warm Boot Control (0,1) Configuration Image 1 Vector Address 2 Controlled by currently loaded iCE65 application (1,0) Configuration Image 2 Vector Address 3 (1,1) Configuration Image 3 SPI PROM SiliconBlue Technologies Corporation www.SiliconBlueTech.com (1.31, 22-APR-2011) 37 iCE65 P-Series Ultra-Low Power mobileFPGA™ Family When self-loading from NVCM or from an SPI Flash PROM, the FPGA supports an additional configuration option called Cold Boot mode. When this option is enabled in the configuration bitstream, the iCE65P FPGA boots normally from power-on or a master reset (CRESET_B = Low pulse), but monitors the value on two PIO pins that are borrowed during configuration, as shown in Figure 30. These pins, labeled PIO2/CBSEL0 and PIO2/CBSEL1, tell the FPGA which of the four possible SPI configurations to load into the device. Table 35 provides the pin or ball locations for these pins.  Load from initial location, either from NVCM or from address 0 in SPI Flash PROM. For Cold Boot or Warm Boot applications, the initial configuration image contains the cold boot/warm boot applet.  Check if Cold Boot configuration feature is enabled in the bitstream.  If not enabled, FPGA configures normally.  If Cold Boot is enabled, then the FPGA reads the logic values on pins CBSEL[1:0]. The FPGA uses the value as a vector and then reads from the indicated vector address.  At the selected CBSEL[1:0] vector address, there is a starting address for the selected configuration image.  For SPI Flash PROMs, the new address is a 24-bit start address in Flash.  If the selected bitstream is in NVCM, then the address points to the internal NVCM.  Using the new start address, the FPGA restarts reading configuration memory from the new location. Table 35: ColdBoot Select Ball Numbers by Package ColdBoot Select PIO2/CBSEL0 PIO2/CBSEL1 Package Code CB121 H6 J6 CB196 L9 P10 CB284 R13 V14 When creating the initial configuration image, the SiliconBlue development software loads the start address for up to four configuration images in the bitstream. The value on the CBSEL[1:0] pins tell the configuration controller to read a specific start address, then to load the configuration image stored at the selected address. The multiple bitstreams are stored either in the SPI Flash or in the internal NVCM. After configuration, the CBSEL[1:0] pins become normal PIO pins available to the application. The Cold Boot feature allows the iCE65P to be reprogrammed for special application requirements such as the following.  A normal operating mode and a self-test or diagnostics mode.  Different applications based on switch settings.  Different applications based on a card-slot ID number. Warm Boot Configuration Option The Warm Boot configuration is similar to the Cold Boot feature, but is completely under the control of the FPGA application. A special design primitive, SB_WARMBOOT, allows an FPGA application to choose between four configuration images using two internal signal ports, S1 and S0, as shown in Figure 30. These internal signal ports connect to programmable interconnect, which in turn can connect to PLB logic and/or PIO pins. After selecting the desired configuration image, the application then asserts the internal signal BOOT port High to force the FPGA to restart the configuration process from the specified vector address stored in PROM. Time-Out and Retry When configuring from external SPI Flash, the iCE65P device looks for a synchronization word. If the device does not find a synchronization word within its timeout period, the device automatically attempts to restart the configuration process from the very beginning. This feature is designed to address any potential power-sequencing issues that may occur between the iCE65P device and the external PROM. (1.31, 22-APR-2011) 38 SiliconBlue Technologies Corporation www.SiliconBlueTech.com SiliconBlue The iCE65P device attempts to reconfigure six times. If not successful after six attempts, the iCE65P FPGA automatically goes into low-power mode. SPI Peripheral Configuration Interface Using the SPI peripheral configuration interface, an application processor (AP) serially writes a configuration image to an iCE65P FPGA using the iCE65‟s SPI interface, as shown in Figure 26. The iCE65‟s SPI configuration interface is a separate, independent I/O bank, powered by the VCC_SPI supply input. Typically, VCC_SPI is the same voltage as the application processor‟s I/O. The configuration control signals, CDONE and CRESET_B, are supplied by the separate I/O Bank 2 voltage input, VCCIO_2. This same SPI peripheral interface supports programming for the iCE65‟s Nonvolatile Configuration Memory (NVCM). Figure 31: iCE65P SPI Peripheral Configuration Interface AP_VCCIO VCCIO_2 VCCIO_2 10 kΩ AP_VCCIO 10 kΩ CDONE CRESET_B iCE65 (I/O Bank 2) SPI_VCC Application Processor SPI_SI SPI_SO SPI_SS_B iCE65 (SPI Bank) SPI_SCK 10 kΩ The SPI control signals are defined in Table 32. Table 36: SPI Peripheral Configuration Interface Pins (SPI_SS_B Low when CRESET_B Released) Signal Name CDONE Direction AP  iCE65 CRESET_B AP  iCE65 SPI_VCC SPI_SI SPI_SO Supply AP  iCE65 AP  iCE65 SPI_SS_B AP  iCE65 SPI_SCK AP  iCE65 iCE65P I/O Supply VCCIO_2 SPI_VCC Description Configuration Done output from iCE65. Connect to a 10kΩ pull-up resistor to the application processor I/O voltage, AP_VCC. Configuration Reset input on iCE65. Typically driven by AP using an open-drain driver, which also requires a 10kΩ pull-up resistor to VCCIO_2. SPI Flash PROM voltage supply input. SPI Serial Input to the iCE65P FPGA, driven by the application processor. SPI Serial Output from CE65 device to the application processor. Not actually used during SPI peripheral mode configuration but required if the SPI interface is also used to program the NVCM. SPI Slave Select output from the application processor. Active Low. Optionally hold Low prior to configuration using a 10kΩ pull-down resistor to ground. SPI Slave Clock output from the application processor. After configuration, the SPI port pins are available to the user-application as additional PIO pins, supplied by the SPI_VCC input voltage, essentially providing a fifth “mini” I/O bank. SiliconBlue Technologies Corporation www.SiliconBlueTech.com (1.31, 22-APR-2011) 39 iCE65 P-Series Ultra-Low Power mobileFPGA™ Family Enabling SPI Configuration Interface The optional 10 kΩ pull-down resistor on the SPI_SS_B signal ensures that the iCE65P FPGA powers up in the SPI peripheral mode. Optionally, the application processor drives the SPI_SS_B pin Low when CRESET_B is released, forcing the iCE65P FPGA into SPI peripheral mode. SPI Peripheral Configuration Process Figure 32 illustrates the interface timing for the SPI peripheral mode and Figure 33 outlines the resulting configuration process. The actual timing specifications appear in Table 64. The application processor (AP) begins by driving the iCE65P CRESET_B pin Low, resetting the iCE65P FPGA. Similarly, the AP holds the iCE65‟s SPI_SS_B pin Low. The AP must hold the CRESET_B pin Low for at least 200 ns. Ultimately, the AP either releases the CRESET_B pin and allows it to float High via the 10 kΩ pull-up resistor to VCCIO_2 or drives CRESET_B High. The iCE65P FPGA enters SPI peripheral mode when the CRESET_B pin returns High while the SPI_SS_B pin is Low, After driving CRESET_B High or allowing it to float High, the AP must wait a minimum of 300 µs, allowing the iCE65P FPGA to clear its internal configuration memory. After waiting for the configuration memory to clear, the AP sends the configuration image generated by the iCEcube development system. An SPI peripheral mode configuration image must not use the ColdBoot or WarmBoot options. Send the entire configuration image, without interruption, serially to the iCE65‟s SPI_SI input on the falling edge of the SPI_SCK clock input. Once the AP sends the 0x7EAA997E synchronization pattern, the generated SPI_SCK clock frequency must be within the specified 1 MHz to 25 MHz range (40 ns to 1 µs clock period) while sending the configuration image. Send each byte of the configuration image with most-significant bit (msb) first. The AP sends data to the iCE65P FPGA on the falling edge of the SPI_SCK clock. The iCE65P FPGA internally captures each incoming SPI_SI data bit on the rising edge of the SPI_SCK clock. The iCE65‟s SPI_SO output pin is not used during SPI peripheral mode but must connect to the AP if the AP also programs the iCE65‟s Nonvolatile Configuration Memory (NVCM). ! The iCE65P configuration image must be sent as one contiguous stream without interruption. The SPI_SCK clock period must be between 40 ns to 1 µs (1 MHz to 25 MHz). After sending the entire image, the iCE65P FPGA releases the CDONE output allowing it to float High via the 10 kΩ pull-up resistor to AP_VCC. If the CDONE pin remains Low, then an error occurred during configuration and the AP should handle the error accordingly for the application. After the CDONE output pin goes High, send at least 49 additional dummy bits, effectively 49 additional SPI_SCK clock cycles measured from rising-edge to rising-edge. After the additional SPI_CLK cycles, the SPI interface pins then become available to the user application loaded in FPGA. To reconfigure the iCE65P FPGA or to load a different configuration image, merely restart the configuration process by pulsing CRESET_B Low or power-cycling the FPGA. (1.31, 22-APR-2011) 40 SiliconBlue Technologies Corporation www.SiliconBlueTech.com SiliconBlue Figure 32: Application Processor Waveforms for SPI Peripheral Mode Configuration Process CDONE 49 SPI_SCK Cycles Rising edge to rising edge ≥ 200 ns CRESET_B ≥ 800 µs iCE65 enters SPI Peripheral mode with SPI_SS_B = Low on rising edge of CRESET_B SPI_SCK iCE65 captures SPI_SI data on SPI_SCK rising edge. SPI_SS_B D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Configuration image always starts with 0x7EAA997E synchronization word. SPI_SI X X X Entire Configuration Images Send most-significant bit of each byte first X X X Don’t Care 49 dummy bits Pulled High in SPI_SO pin via internal pull-up resistor. Not used for SPI Peripheral mode configuration. Used when programming NVCM via SPI itnterface. SPI_SO ! SPI Interface pins available as user-defined I/O pins iCE65 clears internal configuration memory The iCE65 configuration image must be sent as one contiguous stream without interruption. The SPI_SCK clock period must be between 40 ns to 1 µs (1 MHz to 25 MHz). SiliconBlue Technologies Corporation www.SiliconBlueTech.com (1.31, 22-APR-2011) 41 iCE65 P-Series Ultra-Low Power mobileFPGA™ Family Figure 33: SPI Peripheral Configuration Process SPI Peripheral Configuration Drive CRESET_B = 0 Drive SPI_SS_B = 0, SPI_SCK = 1 Wait a minimum of 200 ns Release CRESET_B or drive CRESET_B = 1 Wait a minimum of 300 µs to clear internal configuration memory Send configuration image serially on SPI_SI to iCE65, mostsignificant bit first, on falling edge of SPI_SCK. Send the entire image, without interruption. Ensure that SPI_SCK frequency is between 1 mHz and 25 MHz. CDONE = 1? NO ERROR! YES Send a minimum of 49 additional dummy bits and 49 additional SPI_SCK clock cycles (rising-edge to rising-edge) to active the user-I/O pins. SPI interface pins available as userdefined I/O pins in application Reconfigure? NO YES Voltage Compatibility As shown in Figure 26, there are potentially three different supply voltages involved in the SPI Peripheral interface, described in Table 37. Table 37: SPI Peripheral Mode Supply Voltages Supply Voltage AP_VCCIO VCC_SPI VCCIO_2 (1.31, 22-APR-2011) 42 Description I/O supply to the Application Processor (AP) Voltage supply for the iCE65P SPI interface. Supply voltage for the iCE65P I/O Bank 2. SiliconBlue Technologies Corporation www.SiliconBlueTech.com SiliconBlue Table 38 describes how to maintain voltage compatibility for two interface scenarios. The easiest interface is when the Application Processor‟s (AP) I/O supply rail and the iCE65‟s SPI and VCCIO_2 bank supply rails all connect to the same voltage. The second scenario is when the AP‟s I/O supply voltage is greater than the iCE65‟s VCCIO_2 supply voltage. Table 38: CRESET_B and CDONE Voltage Compatibility CRESET_B OpenDrain Pull-up CDONE Pullup Condition Direct VCCIO_AP = VCC_SPI OK OK with pull-up Required if using open-drain output Recommended AP can directly drive CRESET_B High and Low although an open-drain output recommended is if multiple devices control CRESET_B. If using an open-drain driver, the CRESET_B input must include a 10 kΩ pull-up resistor to VCCIO_2. The 10 kΩ pull-up resistor to AP_VCCIO is also recommended. N/A Required, requires pull-up Required Required The AP must control CRESET_B with an open-drain output, which requires a 10 kΩ pull-up resistor to VCCIO_2. The 10 kΩ pull-up resistor to AP_VCCIO is required. VCCIO_AP = VCCIO_2 AP_VCCIO > VCCIO_2 Requirement JTAG Boundary Scan Port Overview Each iCE65P device includes an IEEE 1149.1-compatible JTAG boundary-scan port. The port supports printed-circuit board (PCB) testing and debugging. It also provides an alternate means to configure the iCE65P device. Signal Connections The JTAG port connections are listed in Table 39. Table 39: iCE65P JTAG Boundary Scan Signals Signal Name TDI TMS TCK TDO TRST_B Direction Input Input Input Output Input Description Test Data Input. Test Mode Select. Test Clock. Test Data Output. Test Reset, active Low. Must be Low during normal device operation. Must be High to enable JTAG operations. Table 40 lists the Ball numbers for the JTAG interface by package code. The JTAG interface is available in select package types. The JTAG port is located in I/O Bank 1 along the right edge of the iCE65P device and powered by the VCCIO_1 supply inputs. Consequently, the JTAG interface uses the associated I/O standards for I/O Bank 1. Table 40: JTAG Interface Ball Numbers by Package JTAG Interface TDI TMS TCK TDO TRST_B SiliconBlue Technologies Corporation www.SiliconBlueTech.com Package Code CB196 M12 P14 L12 N14 M14 CB284 T16 V18 R16 U18 T18 (1.31, 22-APR-2011) 43 iCE65 P-Series Ultra-Low Power mobileFPGA™ Family Supported JTAG Commands The JTAG interface supports the IEEE 1149.1 mandatory instructions, including EXTEST, SAMPLE/PRELOAD, and BYPASS. Package and Pinout Information Maximum User I/O Pins by Package and by I/O Bank Table 41 lists the maximum number of user-programmable I/O pins by package, with additional detail showing user I/O pins by I/O bank. In some cases, a smaller iCE65P device is packaged in a larger package with unconnected (N.C.) pins or balls, resulting in fewer overall I/O pins. See Table 2 and Table 42 for device-specific I/O counts by package. Table 41: User I/O by Package, by I/O Bank Package Code Package Leads Package Area (mm) Ball Array (balls) Ball/Lead Pitch (mm) Maximum user I/O, all I/O banks PIO Pins in Bank PIO Pins in Bank PIO Pins in Bank PIO Pins in Bank PIO Pins in SPI Interface 0 1 2 3 CB121 121 6x6 11 x 11 CB196 196 8x8 14 x 14 CB284 284 12 x 12 22 x 22 0.5 0.5 0.5 95 148 220 25 21 23 26 37 38 33 36 60 55 51 50 4 4 4 Maximum User I/O by Device and Package Table 42 lists the maximum available user I/O by device and by and package type. Not all devices are available in all packages. Similarly, smaller iCE65P devices may have unconnected balls in some packages. Devices sharing a common package have similar footprints. Table 42: Maximum User I/O by Device and Package Package Device iCE65P04 CB121 CB196 CB284 95 148 174 (1.31, 22-APR-2011) 44 SiliconBlue Technologies Corporation www.SiliconBlueTech.com SiliconBlue iCE65P Pin Descriptions Table 43 lists the various iCE65P pins, alphabetically by name. The table indicates the directionality of the signal and the associated I/O bank. The table also indicates if the signal has an internal pull-up resistor enabled during configuration. Finally, the table describes the function of the pin. Table 43: iCE65P Pin Description Signal Name CDONE CRESET_B GBIN0/PIO0 GBIN1/PIO0 GBIN2/PIO1 GBIN3/PIO1 GBIN4/PIO2 GBIN5/PIO2 Direction I/O Bank Pull-up during Config Output 2 Yes Input 2 No Input/IO Input/IO Input/IO 0 1 2 Yes Yes Yes GBIN6/PIO3 Input/IO 3 No GBIN7/PIO3 Input/IO 3 No Supply All N/A I/O 0,1,2 Yes PIO2/CBSEL0 Input/IO 2 Yes PIO2/CBSEL1 Input/IO 2 Yes PIO3_yy/ DPwwz I/O 3 No PIOS/SPI_SO PIOS /SPI_SI I/O I/O SPI SPI Yes Yes PIOS / SPI_SS_B I/O SPI Yes PIOS/ SPI_SCK I/O SPI Yes PLLGND Supply PLL N/A GND PIOx_yy SiliconBlue Technologies Corporation www.SiliconBlueTech.com Description Configuration Done. Dedicated output. Includes a permanent weak pull-up resistor to VCCIO_2.. If driving external devices with CDONE output, connect a 10 kΩ pull-up resistor to VCCIO_2. Configuration Reset, active Low. Dedicated input. No internal pull-up resistor. Either actively drive externally or connect a 10 kΩ pull-up resistor to VCCIO_2. Global buffer input from I/O Bank 0. Optionally, a full-featured PIO pin. Global buffer input from I/O Bank 1. Optionally, a full-featured PIO pin. Global buffer input from I/O Bank 2. Optionally, a full-featured PIO pin. Global buffer input from I/O Bank 3. Optionally, a full-featured PIO pin. Global buffer input from I/O Bank 3. Optionally, a full-featured PIO pin. Optionally, a differential clock input using the associated differential input pin. Ground. All must be connected. Programmable I/O pin defined by the iCE65P configuration bitstream. The ‗x‘ number specifies the I/O bank number in which the I/O pin resides. The ―yy‘ number specifies the I/O number in that bank. Optional ColdBoot configuration SELect input, if ColdBoot mode is enabled. A full-featured PIO pin after configuration. Optional ColdBoot configuration SELect input, if ColdBoot mode is enabled. A full-featured PIO pin after configuration. Programmable I/O pin that is also half of a differential I/O pair. Only available in I/O Bank 3. The ―yy‖ number specifies the I/O number in that bank. The ―ww‖ number indicates the differential I/O pair. The ‗z‘ indicates the polarity of the pin in the differential pair. ‗A‘=negative input. ‗B‘=positive input. SPI Serial Output. A full-featured PIO pin after configuration. SPI Serial Input. A full-featured PIO pin after configuration. SPI Slave Select. Active Low. Includes an internal weak pull-up resistor to SPI_VCC during configuration. During configuration, the logic level sampled on this pin determines the configuration mode used by the iCE65P device, as shown in Figure 23. An input when sampled at the start of configuration. An input when in SPI Peripheral configuration mode (SPI_SS_B = Low). An output when in SPI Flash configuration mode. A full-featured PIO pin after configuration. SPI Slave Clock. An input when in SPI Peripheral configuration mode (SPI_SS_B = Low). An output when in SPI Flash configuration mode. A full-featured PIO pin after configuration. Analog ground for Phase Lock Loop (PLL). If unused, tie to ground. (1.31, 22-APR-2011) 45 iCE65 P-Series Ultra-Low Power mobileFPGA™ Family Direction I/O Bank Pull-up during Config PLLVCC Supply PLL N/A TDI Input 1 No TMS Input 1 No TCK Input 1 No TDO Output 1 No TRST_B Input 1 No VCC Supply All N/A VCCIO_0 Supply 0 N/A VCCIO_1 Supply 1 N/A VCCIO_2 Supply 2 N/A VCCIO_3 Supply 3 N/A SPI_VCC Supply SPI N/A VPP_FAST Supply All N/A VPP_2V5 Supply All N/A 3 N/A Signal Name VREF Voltage Reference Description Analog voltage supply for Phase Lock Loop (PLL). If unused, tie to ground. JTAG Test Data Input. If using the JTAG interface, use a 10kΩ pull-up resistor to VCCIO_1. JTAG Test Mode Select. If using the JTAG interface, use a 10kΩ pull-up resistor to VCCIO_1. JTAG Test Clock. If using the JTAG interface, use a 10kΩ pullup resistor to VCCIO_1. JTAG Test Data Output. JTAG Test Reset, active Low. Keep Low during normal operation; High for JTAG operation. Internal core voltage supply. All must be connected. Voltage supply to I/O Bank 0. All such pins or balls on the package must be connected. Can be disconnected or turned off without affecting the Power-On Reset (POR) circuit. Voltage supply to I/O Bank 1. All such pins or balls on the package must be connected. Required to guarantee a valid input voltage on TRST_B JTAG pin. Voltage supply to I/O Bank 2. All such pins or balls on the package must be connected. Required input to the Power-On Reset (POR) circuit. Voltage supply to I/O Bank 3. All such pins or balls on the package must be connected. Can be disconnected or turned off without affecting the Power-On Reset (POR) circuit. SPI interface voltage supply input. Must have a valid voltage even if configuring from NVCM. Required input to the Power-On Reset (POR) circuit. Direct programming voltage supply. If unused, leave floating or unconnected during normal operation. Programming supply voltage. When the iCE65P device is active, VPP_2V5 must be in the valid range between 2.3 V to 3.47 V to release the Power-On Reset circuit, even if the application is not using the NVCM. Input reference voltage in I/O Bank 3 for the SSTL I/O standard. This pin only appears on the CB284 package and for die-based products. N/A = Not Applicable (1.31, 22-APR-2011) 46 SiliconBlue Technologies Corporation www.SiliconBlueTech.com SiliconBlue iCE65P Package Footprint Diagram Conventions Figure 34 illustrates the naming conventions used in the following footprint diagrams. Each PIO pin is associated with an I/O Bank. PIO pins in I/O Bank 3 that support differential inputs are also numbered by differential input pair. Figure 34: CS and CB Package Footprint Diagram Conventions Ball column number 1 Ball row number Single-ended PIO Numbering A PIO0 PIO0 Ball number A1 I/O bank number B PIO3/ DP07A C PIO3/ DP07B Differential Input Pair Indicators Differential Input Pair Numbering PIO0/ DP07A Pair pin polarity Pair number Differential Pair Dot indicates unconnected pin for iCE65L04 in CB284 package Pinout Differences between iCE65P04 and iCE65L04 The iCE65P04 FPGA is designed to be nearly pin-compatible with the iCE65L04 FPGA. The primary difference is that the iCE65P04 requires power and ground inputs for the PLL as shown in Table 44 and Table 45. The tables list the package balls that are different between the iCE65P04 and the iCE65L04 pinouts for the CB196 and CB284 packages. Table 44: Pinout Differences between iCE65P04 and iCE65L04 in CB196 Package Ball Number iCE65P04 iCE65L04 M6 N6 PLLGND PLLVCC PIO2 PIO2 Table 45: Pinout Differences between iCE65P04 and iCE65L04 in CB284 Package Ball Number iCE65P04 iCE65L04 Y9 Y10 PLLGND PLLVCC PIO2 PIO2 SiliconBlue Technologies Corporation www.SiliconBlueTech.com (1.31, 22-APR-2011) 47 iCE65 P-Series Ultra-Low Power mobileFPGA™ Family CB121 Chip-Scale Ball-Grid Array The CB121 package is a chip-scale, fully-populated, ball-grid array with 0.5 mm ball pitch. Footprint Diagram Figure 35 shows the iCE65P04 chip-scale BGA footprint for the 6 x 6 mm CB121 package. Figure 34 shows the conventions used in the diagram. Also see Table 46 for a complete, detailed pinout for the 121-ball chip-scale BGA packages. The signal pins are also grouped into the four I/O Banks and the SPI interface. Figure 35: iCE65P04 CB121 Chip-Scale BGA Footprint (Top View) A VCCIO_3 7 8 9 10 11 VPP_ PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 FAST PIO0 PIO1 A B PIO3/ GND PIO0 PIO0 PIO0 VCC DP00B PIO0 PIO0 GND PIO1 B C GBIN1/ PIO3/ PIO3/ PIO3/ PIO3/ VPP_ PIO0 PIO0 PIO0 PIO0 2V5 PIO1 DP00A DP02A DP03A DP03B PIO0 C E PIO3/ PIO3/ GBIN7/ PIO3/ DP01A DP02B DP07B PIO3/ PIO3/ GND DP01B DP07A F VCC PIO3/ PIO3/ VCCIO_0 GBIN0/ PIO3/ PIO0 PIO0 PIO1 PIO1 PIO1 PIO1 DP04B PIO0 D PIO3/ PIO0 PIO0 PIO0 PIO1 PIO1 DP04A PIO1 E GND GND PIO0 VCC PIO1 PIO1 PIO1 F GND GND PIO1 PIO1 PIO1 PIO1 GND G H PIO3/ PIO3/ PIO3/ PIO2 PIO2/ PIO1 PIO1 PIO1 PIO1 PIO2 DP09A DP10A DP10B PIO2 CBSEL0 H J PIO3/ PIO3/ PIO3/ SPI_ PIO2 PIO2 PIO2/ CDONE PIOS/ PIOS/ VCC DP09B DP11B DP11A CBSEL1 SPI_SO SPI_SS_B PIO2 J K PIO3/ GND PIO2 PIO2 DP12A PIOS/ PIOS/ GND PIO2 K L PLL PLL GBIN5/ GBIN4/ PIO3/ PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 DP12B GND VCC PIO2 PIO2 L D I/O Bank 3 2 DP08A DP05A GBIN6/ PIO3/ DP06A PIO3/ PIO3/ PIO3/ VCCIO_3 G DP08B DP05B DP06B 1 2 3 VCCIO_1 GBIN3/ GBIN2/ VCCIO_2 VCC 4 5 6 I/O Bank 2 CRESET_B 7 SPI_SI SPI_SCK I/O Bank 1 1 I/O Bank 0 3 4 5 6 8 9 10 11 SPI Bank Pinout Table Table 46 provides a detailed pinout table for the iCE65P04 in the CB121 chip-scale BGA package. Pins are generally arranged by I/O bank, then by ball function. Table 46: iCE65P04 CB121 Chip-scale BGA Pinout Table Ball Function GBIN0/PIO0 GBIN1/PIO0 PIO0 PIO0 (1.31, 22-APR-2011) 48 Ball Number D6 C6 A2 A3 Pin Type GBIN GBIN PIO PIO Bank 0 0 0 0 SiliconBlue Technologies Corporation www.SiliconBlueTech.com SiliconBlue Ball Function PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 VCCIO_0 Ball Number A4 A5 A6 A7 A8 A10 B3 B4 B5 B8 B9 C5 C7 C8 C9 D5 D7 E5 E6 E7 F7 B7 Pin Type PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO VCCIO Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GBIN2/PIO1 GBIN3/PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 VCCIO_1 F9 F8 A11 B11 C11 D8 D9 D10 D11 E8 E9 E11 F10 G7 G8 G9 G10 H7 H8 H9 H10 E10 GBIN GBIN PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO VCCIO 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CDONE CRESET_B GBIN4/PIO2 GBIN5/PIO2 PIO2 PIO2 PIO2 J7 K7 L9 L8 H4 H5 H11 CONFIG CONFIG GBIN GBIN PIO PIO PIO 2 2 2 2 2 2 2 SiliconBlue Technologies Corporation www.SiliconBlueTech.com (1.31, 22-APR-2011) 49 iCE65 P-Series Ultra-Low Power mobileFPGA™ Family Ball Function PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2/CBSEL0 PIO2/CBSEL1 VCCIO_2 Ball Number J4 J5 J11 K3 K4 K11 L2 L3 L4 L5 L10 L11 H6 J6 K5 Pin Type PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO VCCIO Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 PIO3/DP00A PIO3/DP00B PIO3/DP01A PIO3/DP01B PIO3/DP02A PIO3/DP02B PIO3/DP03A PIO3/DP03B PIO3/DP04A PIO3/DP04B PIO3/DP05A PIO3/DP05B PIO3/DP06B GBIN6/PIO3/DP06A GBIN7/PIO3/DP07B PIO3/DP07A PIO3/DP08A PIO3/DP08B PIO3/DP09A PIO3/DP09B C1 B1 D1 E2 C2 D2 C3 C4 E4 D4 F3 G3 G4 F4 D3 E3 F2 G1 H1 J1 DPIO DPIO DPIO DPIO DPIO DPIO DPIO DPIO DPIO DPIO DPIO DPIO DPIO GBIN GBIN DPIO DPIO DPIO DPIO DPIO 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 PIO3/DP10A PIO3/DP10B H2 H3 DPIO DPIO 3 3 PIO3/DP11A PIO3/DP11B J3 J2 DPIO DPIO 3 3 PIO3/DP12A PIO3/DP12B K1 L1 DPIO DPIO 3 3 VCCIO_3 VCCIO_3 A1 G2 VCCIO VCCIO 3 3 PIOS/SPI_SO PIOS/SPI_SI PIOS/SPI_SCK PIOS/SPI_SS_B SPI_VCC J8 K8 K9 J9 J10 SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI PLLGND PLLVCC L6 L7 PLLGND PLLVCC PLL PLL (1.31, 22-APR-2011) 50 SiliconBlue Technologies Corporation www.SiliconBlueTech.com SiliconBlue Ball Function Ball Number Pin Type Bank GND GND GND GND GND GND GND GND GND GND B2 B10 E1 F5 F6 G5 G6 G11 K2 K10 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC VCC VCC VCC B6 F1 F11 K6 VCC VCC VCC VCC VCC VCC VCC VCC VPP_2V5 VPP_FAST C10 A9 VPP VPP VPP VPP SiliconBlue Technologies Corporation www.SiliconBlueTech.com (1.31, 22-APR-2011) 51 iCE65 P-Series Ultra-Low Power mobileFPGA™ Family Package Mechanical Drawing Figure 36: CB121 Package Mechanical Drawing CB121: 6 x 6 mm, 121-ball, 0.5 mm ball-pitch, fully-populated, chip-scale ball grid array Top View Bottom View A A B B F G H J K C D e E SiliconBlue iCE65P04F-T CB121C NXXXX YYWW © CCCCC E F G D1 D D C H J K L L e E1 A A1 b Side View E Description Symbol Number of Ball Columns X Number of Ball Rows Y Number of Signal Balls X Body Size Y Ball Pitch Ball Diameter X Edge Ball Center to Center Y Package Height Stand Off n E D e b E1 D1 A A1 Top Marking Format Line Content 1 Logo iCE65P04F 2 -T CB121C 3 ENG 4 NXXXX 5 YYWW 6 © CCCCCC (1.31, 22-APR-2011) 52 1 2 3 4 5 6 7 8 9 10 11 11 10 9 8 7 6 5 4 3 2 1 Mark pin 1 dot Description Logo Part number Power/Speed Package type Engineering Lot Number Date Code Country Min. Nominal 5.90 5.90 — 0.2 — — — 0.12 11 11 121 6.00 6.00 0.50 — 5.00 5.00 — — Max. Units Columns Rows Balls 6.10 6.10 — 0.3 — — 1.00 0.20 mm Thermal Resistance Junction-to-Ambient θ (⁰C/W) 0 LFM 200 LFM 54 45 SiliconBlue Technologies Corporation www.SiliconBlueTech.com SiliconBlue CB196 Chip-Scale Ball-Grid Array The CB196 package is a chip-scale, fully-populated, ball-grid array with 0.5 mm ball pitch. Footprint Diagram Figure 37 shows the iCE65P04 chip-scale BGA footprint for the 8 x 8 mm CB196 package. Figure 34 shows the conventions used in the diagram. Also see Table 47 for a complete, detailed pinout for the 196-ball chip-scale BGA packages. The signal pins are also grouped into the four I/O Banks and the SPI interface. Figure 37: iCE65P04 CB196 Chip-Scale BGA Footprint (Top View) 2 3 4 GBIN0/ 9 10 11 12 13 14 A PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 VPP_ VPP_ 2V5 A B PIO3/ PIO0 PIO0 PIO0 PIO0 PIO0 VCC PIO0 PIO0 PIO0 PIO0 GND PIO1 PIO1 DP00B B C PIO3/ PIO1/ GND DP01B PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO1 PIO1 PIO1 DP00A C D PIO3/ PIO3/ PIO1/ PIO3/ PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO1 PIO1 PIO1 PIO1 DP02A DP02B DP01A DP04A D E PIO3/ PIO3/ DP03A DP03B GBIN1/ PIO3/ PIO3/ PIO0 PIO0 PIO0 PIO1 PIO1 PIO1 PIO1 PIO1 DP04B DP06B PIO0 E F GND VCC DP05A DP05B DP06A   G H  VCCIO_3  PIO3/ PIO3/ PIO3/ GBIN7/ PIO3/ PIO3/ PIO3/ PIO3/ PIO3/ DP07A DP09A DP09B DP13B DP07B  GBIN6/ PIO3/ PIO3/ PIO3/ PIO3/ PIO3/ DP08B DP11B DP11A DP13A DP08A   VCCIO_0 PIO0 VCCIO_0 GND VCC GND PIO0 PIO0 PIO0 FAST VCCIO_1 GBIN2/ PIO1 PIO1 PIO1 PIO1 PIO1 VCC GND GND GND PIO1 PIO1 PIO3/ PIO3/ PIO3/ VCC GND DP10A DP10B DP12B K VCCIO_3 L GBIN4/ PIO3/ PIO3/ SPI_ GND PIO2 PIO2 PIO2 PIO2 PIO2/ CRESET_B VCC DP14A DP14B PIO2 CBSEL0 M PIO3/ PIO3/ PIO2 PIO2 DP15A DP15B P PIO1 PIO1 H J PIO3/ PIO3/ PIO3/ PIO2 PIO2 PIO2 PIO2 PIO2 GND PIO1 PIO1 VCC PIO1 DP12A DP16A DP16B K VCCIO_3 VCC GND VCCIO_1 G PIO1 PIO1 PIO1 PIO1 GND  VCCIO_2  PLL PIO2 PIO2 PIO2 GND  PLL PIO3/ PIO3/ PIO2 PIO2 PIO2 VCC PIO2 PIO2 DP17A DP17B VCC  PIO2 PIO2 PIO2 PIO2 1 PIO1 GND GND GND VCC PIO1 PIO1 PIO1 PIO1 J N GBIN3/ F 2 3 PIO2 L CDONE PIOS/ TDI PIO1 VCCIO_2 PIO2 PIO2 PIO2 TDO N GND PIO2 PIO2 PIO2 PIO2/ PIOS/ PIOS/ PIOS/ TMS P VCCIO_2 GBIN5/ TCK PIO1 PIO1 4 5 6 7 I/O Bank 2 SPI_SO TRST_B CBSEL1 SPI_SI SPI_SCK SPI_SS_B 8 9 I/O Bank 1 I/O Bank 3 1 I/O Bank 0 5 6 7 8 M 10 11 12 13 14 SPI Bank Pinout Table Table 47 provides a detailed pinout table for the iCE65P04 in the CB196 chip-scale BGA package. Pins are generally arranged by I/O bank, then by ball function. SiliconBlue Technologies Corporation www.SiliconBlueTech.com (1.31, 22-APR-2011) 53 iCE65 P-Series Ultra-Low Power mobileFPGA™ Family Table 47: iCE65P04 CB196 Chip-scale BGA Pinout Table Ball Function GBIN0/PIO0 GBIN1/PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 VCCIO_0 VCCIO_0 Ball Number A7 E7 A1 A2 A3 A4 A5 A6 A10 A11 A12 B2 B3 B4 B5 B6 B8 B9 B10 B11 C4 C5 C6 C7 C8 C9 C10 C11 D5 D6 D7 D8 D9 D10 E6 E8 E9 A8 F6 Pin Type GBIN GBIN PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO VCCIO VCCIO Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GBIN2/PIO1 GBIN3/PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 F10 G12 B13 B14 C12 C13 C14 D11 D12 D13 D14 E10 GBIN GBIN PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO 1 1 1 1 1 1 1 1 1 1 1 1 (1.31, 22-APR-2011) 54 SiliconBlue Technologies Corporation www.SiliconBlueTech.com SiliconBlue Ball Function PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 TCK TDI TDO TMS TRST_B VCCIO_1 VCCIO_1 Ball Number E11 E12 E13 E14 F11 F12 F13 F14 G10 G11 G13 G14 H10 H11 H12 H13 J10 J11 J12 J13 K11 K12 K14 L13 L14 M13 L12 M12 N14 P14 M14 F9 H14 Pin Type PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO JTAG JTAG JTAG JTAG JTAG VCCIO VCCIO Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CDONE CRESET_B GBIN4/PIO2 () GBIN5/PIO2 () PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 () PIO2 PIO2 PIO2 M10 L10 CONFIG CONFIG GBIN GBIN PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 SiliconBlue Technologies Corporation www.SiliconBlueTech.com iCE65P04: L7 iCE65P04: P5 K5 K6 K7 K8 K9 L4 L5 L6 L8 M3 M4 iCE65P04: M7 M8 M9 N3 (1.31, 22-APR-2011) 55 iCE65 P-Series Ultra-Low Power mobileFPGA™ Family Ball Function PIO2 PIO2 PIO2 () PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2/CBSEL0 PIO2/CBSEL1 VCCIO_2 VCCIO_2 VCCIO_2 Ball Number N4 N5 iCE65P04: N8 N9 N11 N12 N13 P1 P2 P3 P4 P7 P8 P9 L9 P10 J9 M5 N10 Pin Type PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO VCCIO VCCIO VCCIO Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 PIO3/DP00A PIO3/DP00B PIO3/DP01A PIO3/DP01B PIO3/DP02A PIO3/DP02B PIO3/DP03A () PIO3/DP03B () PIO3/DP04A PIO3/DP04B PIO3/DP05A () PIO3/DP05B () PIO3/DP06A PIO3/DP06B PIO3/DP07A () GBIN7/PIO3/DP07B () GBIN6/PIO3/DP08A PIO3/DP08B PIO3/DP09A PIO3/DP09B PIO3/DP10A PIO3/DP10B PIO3/DP11A () PIO3/DP11B () C1 B1 D3 C3 D1 D2 iCE65P04: H4 iCE65P04: H3 DPIO DPIO DPIO DPIO DPIO DPIO DPIO DPIO DPIO DPIO DPIO DPIO DPIO DPIO DPIO GBIN GBIN DPIO DPIO DPIO DPIO DPIO DPIO DPIO 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 PIO3/DP12A PIO3/DP12B K2 J3 DPIO DPIO 3 3 PIO3/DP13A PIO3/DP13B H5 G5 DPIO DPIO 3 3 PIO3/DP14A PIO3/DP14B L1 L2 DPIO DPIO 3 3 PIO3/DP15A PIO3/DP15B M1 M2 DPIO DPIO 3 3 (1.31, 22-APR-2011) 56 iCE65P04: E1 iCE65P04: E2 D4 E4 iCE65P04: F3 iCE65P04: F4 F5 E5 iCE65P04: G2 iCE65P04: G1 H1 H2 G3 G4 J1 J2 SiliconBlue Technologies Corporation www.SiliconBlueTech.com SiliconBlue Ball Function Ball Number Pin Type Bank PIO3/DP16A () PIO3/DP16B () iCE65P04: K3 iCE65P08: K4 DPIO DPIO 3 3 PIO3/DP17A PIO3/DP17B N1 N2 DPIO DPIO 3 3 VCCIO_3 VCCIO_3 VCCIO_3 E3 J6 K1 VCCIO VCCIO VCCIO 3 3 3 PIOS/SPI_SO PIOS/SPI_SI PIOS/SPI_SCK PIOS/SPI_SS_B SPI_VCC M11 P11 P12 P13 L11 SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI PLLGND PLLVCC M6 N6 PLLGND PLLVCC PLL PLL GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND A9 B12 C2 F1 F7 G7 G8 G9 H6 H7 H8 J5 J8 J14 K10 L3 P6 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC VCC VCC VCC VCC VCC VCC VCC VCC B7 F2 F8 G6 H9 J4 J7 K13 N7 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VPP_2V5 VPP_FAST A14 A13 VPP VPP VPP VPP Package Mechanical Drawing Figure 38: CB196 Package Mechanical Drawing SiliconBlue Technologies Corporation www.SiliconBlueTech.com (1.31, 22-APR-2011) 57 iCE65 P-Series Ultra-Low Power mobileFPGA™ Family CB196: 8 x8 mm, 196-ball, 0.5 mm ball-pitch, fully-populated, chip-scale ball grid array Top View Bottom View 1 2 3 4 5 6 7 8 9 10 11 12 13 14 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Mark pin 1 dot A B B C C D D e A E H J K L M N P E F iCE65P04F-T CB196I NXXXXXXX YYWW © CCCCCC G D1 G D F H J K L M N P A A1 b e E1 Side View E Top Marking Format Description Number of Ball Columns X Number of Ball Rows Y Number of Signal Balls X Body Size Y Ball Pitch Ball Diameter X Edge Ball Center to Center Y Package Height Stand Off (1.31, 22-APR-2011) 58 Symbol n E D e b E1 D1 A A1 Min. Nominal 7.90 7.90 — 0.27 — — — 0.16 14 14 196 8.00 8.00 0.50 — 6.50 6.50 — — Max. Units Columns Rows Balls 8.10 8.10 — 0.37 — — 1.00 0.26 mm Li ne Content 1 Logo i CE65P04F 2 -T CB196I 3 ENG 4 NXXXXXXX 5 YYWW 6 © CCCCCC Des cription Logo Pa rt number Power/Speed Pa cka ge type Engi neering Lot Number Da te Code Country Thermal Resistance Juncti on-to-Ambient θ (⁰C/W) 0 LFM 200 LFM 42 34 SiliconBlue Technologies Corporation www.SiliconBlueTech.com SiliconBlue CB284 Chip-Scale Ball-Grid Array The CB284 package, partially-populated 0.5 mm pitch, ball grid array simplifies PCB layout with empty ball rings. Footprint Diagram Figure 39 shows the CB284 chip-scale BGA footprint. Figure 34 shows the conventions used in the diagram. Also see Table 48 for a complete, detailed pinout for the 284-ball chip-scale BGA packages. The signal pins are also grouped into the four I/O Banks and the SPI interface. A 2 3 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 VCCIO_0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO3/ B DP07A PIO1 A PIO1 B PIO3/ C DP07B PIO0 PIO0 PIO0 PIO0 PIO0 VCC PIO0 PIO0 PIO0 GND PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO1 PIO1 C PIO3/ D DP08A VCC PIO1 PIO1 D E DP08B PIO3/ PIO3/ DP05A PIO0 PIO0 PIO0 PIO0 PIO0 VPP_ VPP_ 2V5 PIO1 PIO1 E F VCCIO_3 PIO3/ DP05B PIO3/ DP00A PIO1 PIO1 PIO1 F G GND PIO3/ DP06A PIO3/ DP00B PIO3/ PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 DP01A PIO1 PIO1 PIO1 G PIO3/ H DP09A PIO3/ DP06B PIO3/ DP03A PIO3/ PIO3/ PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO1 DP01B DP02A PIO1 PIO1 VCCIO_1 H PIO3/ DP09B GND PIO3/ DP03B VCCIO_3 PIO1 VCCIO_1 PIO1 J VCCIO_3 GND PIO3/ PIO3/ DP04B DP04A PIO1 PIO1 K PIO3/ DP10B PIO3/ DP11A PIO3/ PIO3/ DP19A DP19B VCC GND GND GND PIO1 PIO1 VCC PIO1 L M VREF PIO3/ DP15A GBIN7/ PIO3/ DP11B GBIN6/ PIO3/ DP15A PIO3/ PIO3/ DP20A DP20B GND GND GND VCC PIO1 PIO1 VCCIO_1 PIO1 PIO1 M GND PIO3/ DP16A PIO3/ DP21B PIO3/ VCC DP21A VCC GND PIO1 PIO1 GND GND PIO1 N PIO3/ DP16B VCCIO_3 PIO3/ PIO3/ DP22A DP22B PIO1 PIO1 PIO1 PIO1 PIO1 P J PIO3/ K DP10A I/O Bank 3 VCCIO_0 L N P VCCIO_3 GBIN0/ GBIN1/ PIO0 PIO0 VCCIO_0 GND PIO0 PIO0 PIO0 FAST PIO3/ DP02B PIO1 PIO1 VCCIO_0 VCCIO_3 GND VCC PIO1 PIO1 VCCIO_1 VCCIO_2 GBIN3/ PIO1 GBIN2/ PIO1 R GND VCCIO_3 PIO3/ DP23A SPI_ GND PIO2 PIO2 PIO2 PIO2 PIO2 PIO2/ CRESET_B VCC TCK PIO1 PIO1 PIO1 R T PIO3/ DP12A GND PIO3/ DP23B PIO2 PIO2 PIOS/ TDI TRST_B PIO1 PIO1 T PIO3/ U DP12B PIO3/ DP17A PIO3/ DP24A TDO PIO1 PIO1 U PIO3/ PIO2 PIO2 PIO2 PIO2 GND PIO2 PIO2/ PIOS/ PIOS/ PIOS/ TMS DP24B PIO2 PIO2 CBSEL1 SPI_SI SPI_SCK SPI_SS_B PIO1 PIO1 V CBSEL0 VCCIO_2 PIO2 PIO2 PIO2 PIO2 CDONE SPI_SO SPI Bank GBIN5/ GBIN4/ GND PIO3/ DP17B PIO3/ W DP13A PIO3/ DP18A PIO1 PIO1 W PIO3/ Y DP13B PLL PLL PIO3/ VCCIO_2 GND PIO2 PIO2 PIO2 GND PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 VCC DP18B GND VCC PIO1 Y V I/O Bank 1 1 Figure 39: iCE65P CB284 Chip-Scale BGA Footprint (Top View) I/O Bank 0 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 AA PIO3/ DP14A PIO1 AA AB PIO3/ PIO2 PIO2 PIO2 GND PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 DP14B AB 1 2 3 4 5 6 7 SiliconBlue Technologies Corporation www.SiliconBlueTech.com 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 I/O Bank 2 (1.31, 22-APR-2011) 59 iCE65 P-Series Ultra-Low Power mobileFPGA™ Family Pinout Table Table 48 provides a detailed pinout table for the two chip-scale BGA packages. Pins are generally arranged by I/O bank, then by ball function. The balls with a black circle () are unconnected balls (N.C.) for the iCE65P04 in the CB284 package. The table also highlights the differential I/O pairs in I/O Bank 3. Table 48: iCE65P CB284 Chip-scale BGA Pinout Table (with CB132 cross reference) Ball Function GBIN0/PIO0 GBIN1/PIO0 PIO0 () PIO0 () PIO0 () PIO0 () PIO0 PIO0 PIO0 PIO0 () PIO0 () PIO0 () PIO0 () PIO0 () PIO0 PIO0 PIO0 PIO0 PIO0 () PIO0 () PIO0 () PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 (1.31, 22-APR-2011) 60 Ball Number E10 E11 A1 A2 A3 A4 A5 A6 A7 A9 A10 A11 A12 A13 A15 A16 A17 A18 A14 A19 A20 C3 C4 C5 C6 C7 C9 C10 C11 C13 C14 C15 C16 C17 C18 C19 E5 E6 E7 E8 E9 E14 E15 E16 Pin Type by Device iCE65P04 iCE65P08 GBIN GBIN GBIN GBIN N.C. PIO N.C. PIO N.C. PIO N.C. PIO PIO PIO PIO PIO PIO PIO N.C. PIO N.C. PIO N.C. PIO N.C. PIO N.C. PIO PIO PIO PIO PIO PIO PIO PIO PIO N.C. PIO N.C. PIO N.C. PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SiliconBlue Technologies Corporation www.SiliconBlueTech.com SiliconBlue Ball Function PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 VCCIO_0 VCCIO_0 VCCIO_0 VCCIO_0 Ball Number G8 G9 G10 G11 G12 G13 G14 G15 G16 H9 H10 H11 H12 H13 H14 H15 A8 A21 E12 K10 GBIN2/PIO1 GBIN3/PIO1 PIO1 () PIO1 () PIO1 () PIO1 PIO1 () PIO1 PIO1 () PIO1 PIO1 () PIO1 PIO1 PIO1 () PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 () PIO1 PIO1 PIO1 PIO1 () PIO1 PIO1 L18 K18 A22 AA22 B22 C20 C22 D20 D22 E20 E22 F18 F20 F22 G18 G20 G22 H16 H18 H20 J15 J16 J18 J22 K15 K16 K20 K22 L15 L16 SiliconBlue Technologies Corporation www.SiliconBlueTech.com Pin Type by Device iCE65P04 iCE65P08 PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO GBIN GBIN N.C. N.C. N.C. PIO N.C. PIO N.C. PIO N.C. PIO PIO N.C. PIO PIO PIO PIO PIO PIO PIO PIO PIO N.C. PIO PIO PIO N.C. PIO PIO GBIN GBIN PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (1.31, 22-APR-2011) 61 iCE65 P-Series Ultra-Low Power mobileFPGA™ Family Ball Function PIO1 () PIO1 PIO1 PIO1 PIO1 () PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 () PIO1 PIO1 () PIO1 PIO1 () PIO1 () TCK TDI TDO TMS TRST_B VCCIO_1 VCCIO_1 VCCIO_1 VCCIO_1 Ball Number L22 M15 M16 M20 M22 N15 N16 N22 P15 P16 P18 P20 P22 R18 R20 R22 T20 T22 U20 U22 V20 V22 W20 W22 Y22 R16 T16 U18 V18 T18 H22 J20 K13 M18 CDONE CRESET_B GBIN4/PIO2 GBIN5/PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 T14 R14 V12 V11 R8 R9 R10 R11 R12 T7 T8 T10 T11 T12 T13 V6 V7 (1.31, 22-APR-2011) 62 Pin Type by Device iCE65P04 iCE65P08 N.C. PIO PIO PIO PIO PIO PIO PIO N.C. PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO N.C. PIO PIO PIO N.C. PIO PIO PIO N.C. PIO N.C. PIO JTAG JTAG JTAG JTAG JTAG JTAG JTAG JTAG JTAG JTAG VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO CONFIG CONFIG GBIN GBIN PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO CONFIG CONFIG GBIN GBIN PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 SiliconBlue Technologies Corporation www.SiliconBlueTech.com SiliconBlue Pin Type by Device iCE65P04 iCE65P08 PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO N.C. PIO N.C. PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO N.C. PIO N.C. PIO N.C. PIO N.C. PIO N.C. PIO N.C. PIO N.C. PIO PIO PIO PIO PIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO Ball Function PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 () PIO2 () PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 () PIO2 () PIO2 () PIO2 () PIO2 () PIO2 () PIO2 () PIO2/CBSEL0 PIO2/CBSEL1 VCCIO_2 VCCIO_2 VCCIO_2 Ball Number V8 V9 V13 Y4 Y5 Y6 Y7 Y13 Y14 Y15 Y17 Y18 Y19 Y20 AB2 AB3 AB4 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 R13 V14 N13 T9 Y11 PIO3/DP00A PIO3/DP00B PIO3/DP01A PIO3/DP01B F5 G5 G7 H7 DPIO DPIO DPIO DPIO DPIO DPIO DPIO DPIO 3 3 3 3 PIO3/DP02A PIO3/DP02B H8 J8 DPIO DPIO DPIO DPIO 3 3 PIO3/DP03A PIO3/DP03B H5 J5 DPIO DPIO DPIO DPIO 3 3 PIO3/DP04A PIO3/DP04B K8 K7 DPIO DPIO DPIO DPIO 3 3 PIO3/DP05A E3 DPIO DPIO 3 SiliconBlue Technologies Corporation www.SiliconBlueTech.com Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 (1.31, 22-APR-2011) 63 iCE65 P-Series Ultra-Low Power mobileFPGA™ Family Pin Type by Device iCE65P04 iCE65P08 DPIO DPIO Ball Function PIO3/DP05B Ball Number F3 PIO3/DP06A PIO3/DP06B G3 H3 DPIO DPIO DPIO DPIO 3 3 PIO3/DP07A () PIO3/DP07B () B1 C1 N.C. N.C. DPIO DPIO 3 3 PIO3/DP08A () PIO3/DP08B () D1 E1 N.C. N.C. DPIO DPIO 3 3 PIO3/DP09A PIO3/DP09B H1 J1 DPIO DPIO DPIO DPIO 3 3 PIO3/DP10A PIO3/DP10B K1 L1 DPIO DPIO DPIO DPIO 3 3 PIO3/DP11A GBIN7/PIO3/DP11B L3 L5 DPIO GBIN DPIO GBIN 3 3 PIO3/DP12A () PIO3/DP12B () T1 U1 N.C. N.C. DPIO DPIO 3 3 PIO3/DP13A () PIO3/DP13B () W1 Y1 N.C. N.C. DPIO DPIO 3 3 PIO3/DP14A () PIO3/DP14B () AA1 AB1 N.C. N.C. DPIO DPIO 3 3 GBIN6/PIO3/DP15A PIO3/DP15B M5 M3 GBIN DPIO GBIN DPIO 3 3 PIO3/DP16A PIO3/DP16B N3 P3 DPIO DPIO DPIO DPIO 3 3 PIO3/DP17A PIO3/DP17B U3 V3 DPIO DPIO DPIO DPIO 3 3 PIO3/DP18A PIO3/DP18B W3 Y3 DPIO DPIO DPIO DPIO 3 3 PIO3/DP19A PIO3/DP19B L7 L8 DPIO DPIO DPIO DPIO 3 3 PIO3/DP20A PIO3/DP20B M7 M8 DPIO DPIO DPIO DPIO 3 3 PIO3/DP21A PIO3/DP21B N7 N5 DPIO DPIO DPIO DPIO 3 3 PIO3/DP22A PIO3/DP22B P7 P8 DPIO DPIO DPIO DPIO 3 3 PIO3/DP23A PIO3/DP23B R5 T5 DPIO DPIO DPIO DPIO 3 3 PIO3/DP24A PIO3/DP24B U5 V5 DPIO DPIO DPIO DPIO 3 3 VCCIO_3 VCCIO_3 VCCIO_3 VCCIO_3 VCCIO_3 VCCIO_3 VCCIO_3 VREF F1 P1 J7 K3 N10 P5 R3 M1 VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VREF VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VREF 3 3 3 3 3 3 3 3 (1.31, 22-APR-2011) 64 Bank 3 SiliconBlue Technologies Corporation www.SiliconBlueTech.com SiliconBlue Pin Type by Device iCE65P04 iCE65P08 Ball Function Ball Number PIOS/SPI_SO PIOS/SPI_SI PIOS/SPI_SCK PIOS/SPI_SS_B SPI_VCC T15 V15 V16 V17 R15 SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI PLLGND PLLVCC Y9 Y10 PLLGND PLLVCC PLLGND PLLVCC PLL PLL GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND C12 E13 J3 K5 K11 L11 L12 L13 M10 M11 M12 N1 N12 N18 N20 R7 T3 V1 V10 Y12 Y16 AB5 G1 R1 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC VCC VCC VCC VCC VCC VCC VCC VCC C8 D3 K12 L10 L20 M13 N8 N11 Y8 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VPP_2V5 VPP_FAST E18 E17 VPP VPP VPP VPP VPP VPP SiliconBlue Technologies Corporation www.SiliconBlueTech.com Bank (1.31, 22-APR-2011) 65 iCE65 P-Series Ultra-Low Power mobileFPGA™ Family Package Mechanical Drawing Figure 40: CB284 Package Mechanical Drawing 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 CB284: 12 x 12 mm, 284-ball, 0.5 mm ball-pitch, chip-scale ball grid array Mark pin 1 dot Top View Bottom View A B B C C D D e A E E F F G G H H J J M N P R T K i CE65P04F-T EN G CB284C N XXXXXXX YYWW L D1 L D K M N P R T U U V V W Y AA © CCCCCC W Y AA AB AB e E1 A A1 b Side View E Top Marking Format Description Number of Ball Columns X Number of Ball Rows Y Number of Signal Balls X Body Size Y Ball Pitch Ball Diameter X Edge Ball Center to Center Y Package Height Stand Off Symbol n E D e b E1 D1 A A1 Min. Nominal 11.90 11.90 — 0.27 — — — 0.16 22 22 284 12.00 12.00 0.50 — 10.50 10.50 — — Max. Units Columns Rows Balls 12.10 12.10 — 0.37 — — 1.00 0.26 mm Li ne Content 1 Logo i CE65P04F 2 -T ENG 3 CB284C NXXXXXXX 4 YYWW 5 N/A 6 © CCCCCC Des cription Logo Pa rt number Power/Speed Engi neering Pa cka ge type and Lot number Da te Code Bl a nk Country Thermal Resistance Junction-to-Ambient θ (⁰C/W) 0 LFM 200 LFM 35 28 (1.31, 22-APR-2011) 66 SiliconBlue Technologies Corporation www.SiliconBlueTech.com SiliconBlue Die Cross Reference The tables in this section list all the pads on a specific die type and provide a cross reference on how a specific pad connects to a ball or pin in each of the available package offerings. Similarly, the tables provide the pad coordinates for the die-based version of the product (iCE DiCE). These tables also provide a way to prototype with one package option and then later move to a different package or die. As described in “Input and Output Register Control per PIO Pair” on page 14, PIO pairs share register control inputs. Similarly, as described in “Differential Inputs and Outputs” on page 11, a PIO pair can form a differential input or output. PIO pairs in I/O Bank 3 are optionally differential inputs or differential outputs. PIO pairs in all other I/O Banks are optionally differential outputs. In the tables, differential pairs are surrounded by a heavy blue box. iCE65P04 Table 49 lists all the pads on the iCE65P04 die and how these pads connect to the balls or pins in the supported package styles. Most VCC, VCCIO, and GND pads are double-bonded inside the package although the table shows only a single connection. For additional information on the iCE65P04 DiePlus product, please contact your SiliconBlue sales representative.. Table 49: iCE65P04 Die Cross Reference iCE65P04 Pad Name CB196 Available Packages CB284 Pad DiePlus X (µm) PIO3_00/DP00A PIO3_01/DP00B C1 B1 F5 G5 1 2 129.40 231.40 2,687.75 2,642.74 PIO3_02/DP01A PIO3_03/DP01B D3 C3 G7 H7 3 4 129.40 231.40 2,597.75 2,552.74 GND GND VCCIO_3 VCCIO_3 F1 — E3 — K5 — J7 — 5 6 7 8 129.40 231.40 129.40 231.40 2,507.75 2,462.74 2,417.75 2,372.74 PIO3_04/DP02A PIO3_05/DP02B D1 D2 H8 J8 9 10 129.40 231.40 2,327.75 2,292.74 PIO3_06/DP03A PIO3_07/DP03B E1 E2 H5 J5 11 12 129.40 231.40 2,257.75 2,222.74 VCC H9 D3 13 129.40 2,187.75 PIO3_08/DP04A PIO3_09/DP04B D4 E4 K8 K7 14 15 231.40 129.40 2,152.74 2,117.75 PIO3_10/DP05A PIO3_11/DP05B F3 F4 E3 F3 16 17 231.40 129.40 2,082.74 2,047.75 Y (µm) GND A9 M10 18 231.40 2,012.74 PIO3_12/DP06A PIO3_13/DP06B F5 E5 G3 H3 19 20 129.40 231.40 1,977.75 1,942.74 GND GND A9 — J3 — 21 22 129.40 231.40 1,907.75 1,872.74 PIO3_14/DP07A PIO3_15/DP07B — — H1 J1 23 24 129.40 231.40 1,837.75 1,802.74 VCCIO_3 VCC K1 G6 K3 L10 25 26 129.40 231.40 1,767.75 1,732.74 PIO3_16/DP08A PIO3_17/DP08B — — K1 L1 27 28 129.40 231.40 1,697.75 1,662.74 PIO3_18/DP09A GBIN7/PIO3_19/DP09B G2 G1 L3 L5 29 30 129.40 231.40 1,627.75 1,592.74 VCCIO_3 J6 N10 31 129.40 1,557.75 SiliconBlue Technologies Corporation www.SiliconBlueTech.com (1.31, 22-APR-2011) 67 iCE65 P-Series Ultra-Low Power mobileFPGA™ Family iCE65P04 Pad Name Available Packages DiePlus X (µm) CB284 M1 N1 Pad VREF GND CB196 N/A A9 32 33 231.40 129.40 1,522.74 1,487.75 GBIN6/PIO3_20/DP10A PIO3_21/DP10B H1 H2 M5 M3 34 35 231.40 129.40 1,452.74 1,417.75 GND A9 M11 36 231.40 1,382.74 PIO3_22/DP11A PIO3_23/DP11B G3 G4 N3 P3 37 38 129.40 231.40 1,347.75 1,312.74 VCCIO_3 VCCIO_3 GND GND K1 — A9 — R3 — T3 — 39 40 41 42 129.40 231.40 129.40 231.40 1,277.75 1,242.74 1,207.75 1,172.74 PIO3_24/DP12A PIO3_25/DP12B J1 J2 U3 V3 43 44 129.40 231.40 1,137.75 1,102.74 GND A9 V1 45 129.40 1,067.75 PIO3_26/DP13A PIO3_27/DP13B H4 H3 W3 Y3 46 47 231.40 129.40 1,032.74 997.75 PIO3_28/DP14A PIO3_29/DP14B K2 J3 L7 L8 48 49 231.40 129.40 962.74 927.75 PIO3_30/DP15A PIO3_31/DP15B H5 G5 M7 M8 50 51 231.40 129.40 892.74 857.75 VCC F2 N8 52 231.40 822.74 PIO3_32/DP16A PIO3_33/DP16B L1 L2 N7 N5 53 54 129.40 231.40 787.75 752.74 VCCIO_3 VCCIO_3 GND GND K1 — L3 — P5 — R7 — 55 56 57 58 129.40 231.40 129.40 231.40 717.75 682.74 637.75 592.74 PIO3_34/DP17A PIO3_35/DP17B M1 M2 P7 P8 59 60 129.40 231.40 547.75 502.74 PIO3_36/DP18A PIO3_37/DP18B K3 K4 R5 T5 61 62 129.40 231.40 457.75 412.74 PIO3_38/DP19A PIO3_39/DP19B N1 N2 U5 V5 63 64 129.40 231.40 367.75 322.74 PIO2_00 PIO2_01 — L4 AB2 V6 65 66 440.00 490.00 139.20 37.20 PIO2_02 GND PIO2_03 M3 C2 P1 T7 AB5 R8 67 68 69 540.00 590.00 640.00 139.20 37.20 139.20 PIO2_04 PIO2_05 N3 P2 V7 T8 70 71 690.00 740.00 37.20 139.20 PIO2_06 PIO2_07 L5 M4 R9 V8 72 73 790.00 825.00 37.20 139.20 PIO2_08 VCCIO_2 PIO2_09 P3 M5 K5 R10 T9 V9 74 75 76 860.00 895.00 930.00 37.20 139.20 37.20 (1.31, 22-APR-2011) 68 Y (µm) SiliconBlue Technologies Corporation www.SiliconBlueTech.com SiliconBlue iCE65P04 Pad Name CB196 Available Packages CB284 Pad PIO2_10 GND PIO2_11 N4 H7 P4 T10 V10 Y4 77 78 79 965.00 1,000.00 1,035.00 139.20 37.20 139.20 PIO2_12 PIO2_13 L6 — Y5 AB6 80 81 1,070.00 1,105.00 37.20 139.20 PIO2_14 PIO2_15 — — AB7 AB8 82 83 1,140.00 1,175.00 37.20 139.20 PIO2_16 PIO2_17 — — AB9 AB10 84 85 1,210.00 1,245.00 37.20 139.20 PIO2_18 GND PIO2_19 — H8 K6 AB11 N12 Y6 86 87 88 1,280.00 1,315.00 1,350.00 37.20 139.20 37.20 PIO2_20 VCC PIO2_21 N5 J4 — Y7 Y8 — 89 90 91 1,385.00 1,420.00 1,455.00 139.20 37.20 139.20 PIO2_22 PLLGND PLLVCC GBIN5/PIO2_23 — M6 N6 P5 — Y9 Y10 V11 92 93 94 95 1,490.00 1,525.00 1,595.00 1,630.00 37.20 139.20 37.20 139.20 GBIN4/PIO2_24 PIO2_25 L7 — V12 AB12 96 97 1,665.00 1,700.00 37.20 139.20 VCCIO_2 J9 Y11 98 1,735.00 37.20 PIO2_26 PIO2_27 — K7 AB13 AB14 99 100 1,770.00 1,805.00 139.20 37.20 GND J5 Y12 101 1,840.00 139.20 PIO2_28 PIO2_29 K9 M7 AB15 Y13 102 103 1,875.00 1,910.00 37.20 139.20 PIO2_30 PIO2_31 K8 P7 Y14 Y15 104 105 1,945.00 1,980.00 37.20 139.20 PIO2_32 PIO2_33 L8 P8 Y17 Y18 106 107 2,015.00 2,050.00 37.20 139.20 PIO2_34 PIO2_35 N8 M8 Y19 Y20 108 109 2,085.00 2,120.00 37.20 139.20 VCC VCC J7 — N11 — 110 111 2,155.00 2,190.00 37.20 139.20 PIO2_36 PIO2_37 P9 N9 V13 T11 112 113 2,225.00 2,260.00 37.20 139.20 VCCIO_2 N10 N13 114 2,295.00 37.20 PIO2_38 GND PIO2_39 M9 J8 N12 R11 M12 T12 115 116 117 2,330.00 2,365.00 2,400.00 139.20 37.20 139.20 PIO2_40 PIO2_41 N11 N13 R12 T13 118 119 2,435.00 2,470.00 37.20 139.20 PIO2_42/CBSEL0 PIO2_43/CBSEL1 L9 P10 R13 V14 120 121 2,505.00 2,540.00 37.20 139.20 CDONE CRESET_B M10 L10 T14 R14 122 123 2,575.00 2,625.00 37.20 139.20 SiliconBlue Technologies Corporation www.SiliconBlueTech.com DiePlus X (µm) Y (µm) (1.31, 22-APR-2011) 69 iCE65 P-Series Ultra-Low Power mobileFPGA™ Family iCE65P04 Pad Name CB196 CB284 Pad PIOS_00/SPI_SO PIOS_01/SPI_SI M11 P11 T15 V15 124 125 2,690.00 2,740.00 37.20 139.20 GND P6 Y16 126 2,790.00 37.20 PIOS_02/SPI_SCK PIOS_03/SPI_SS_B P12 P13 V16 V17 127 128 2,840.00 2,890.00 139.20 37.20 SPI_VCC L11 R15 129 2,990.00 37.20 TDI TMS TCK TDO TRST_B M12 P14 L12 N14 M14 T16 V18 R16 U18 T18 130 131 132 133 134 3,610.80 3,712.80 3,610.80 3,712.80 3,610.80 342.00 392.00 442.00 492.00 542.00 PIO1_00 PIO1_01 K11 L13 R18 P16 135 136 3,712.80 3,610.80 592.00 642.00 PIO1_02 PIO1_03 K12 M13 P15 P18 137 138 3,712.80 3,610.80 692.00 727.00 GND GND J14 J14 N18 N18 139 140 3,712.80 3,610.80 762.00 797.00 PIO1_04 PIO1_05 J10 L14 N16 N15 141 142 3,712.80 3,610.80 832.00 867.00 VCCIO_1 VCCIO_1 H14 — M18 — 143 144 3,712.80 3,610.80 902.00 937.00 PIO1_06 PIO1_07 J11 K14 M16 M15 145 146 3,712.80 3,610.80 972.00 1,007.00 PIO1_08 PIO1_09 H10 J13 W20 V20 147 148 3,712.80 3,610.80 1,042.00 1,077.00 PIO1_10 VCC VCC PIO1_11 J12 N7 — H13 U20 M13 — T22 149 150 151 152 3,712.80 3,610.80 3,712.80 3,610.80 1,112.00 1,147.00 1,182.00 1,217.00 PIO1_12 PIO1_13 H12 — R22 P22 153 154 3,712.80 3,610.80 1,252.00 1,287.00 PIO1_14 PIO1_15 — G13 N22 T20 155 156 3,712.80 3,610.80 1,322.00 1,357.00 PIO1_16 PIO1_17 H11 G14 R20 P20 157 158 3,712.80 3,610.80 1,392.00 1,427.00 GND GND K10 — N20 — 159 160 3,712.80 3,610.80 1,462.00 1,497.00 PIO1_18 GBIN3/PIO1_19 G10 G12 M20 K18 161 162 3,712.80 3,610.80 1,532.00 1,567.00 GBIN2/PIO1_20 PIO1_21 F10 F14 L18 K20 163 164 3,712.80 3,610.80 1,602.00 1,637.00 VCCIO_1 VCCIO_1 H14 — J20 — 165 166 3,712.80 3,610.80 1,672.00 1,707.00 PIO1_22 PIO1_23 F13 D13 H20 G20 167 168 3,712.80 3,610.80 1,742.00 1,777.00 PIO1_24 G11 F20 169 3,712.80 1,812.00 (1.31, 22-APR-2011) 70 Available Packages DiePlus X (µm) Y (µm) SiliconBlue Technologies Corporation www.SiliconBlueTech.com SiliconBlue iCE65P04 Pad Name Available Packages DiePlus X (µm) CB284 E20 Pad PIO1_25 CB196 F11 170 3,610.80 1,847.00 PIO1_26 PIO1_27 E10 E14 D20 C20 171 172 3,712.80 3,610.80 1,882.00 1,917.00 GND GND G8 — L12 — 173 174 3,712.80 3,610.80 1,952.00 1,987.00 PIO1_28 PIO1_29 F12 D14 G22 L16 175 176 3,712.80 3,610.80 2,022.00 2,057.00 PIO1_30 PIO1_31 E13 C14 L15 K16 177 178 3,712.80 3,610.80 2,092.00 2,127.00 VCC VCC K13 — L20 — 179 180 3,712.80 3,610.80 2,162.00 2,197.00 PIO1_32 PIO1_33 E11 C13 J18 K15 181 182 3,712.80 3,610.80 2,232.00 2,267.00 VCCIO_1 VCCIO_1 F9 — K13 — 183 184 3,712.80 3,610.80 2,302.00 2,337.00 PIO1_34 PIO1_35 E12 B14 J16 H18 185 186 3,712.80 3,610.80 2,377.00 2,427.00 GND G9 L13 187 3,712.80 2,477.00 PIO1_36 PIO1_37 B13 D12 J15 H16 188 189 3,610.80 3,712.80 2,527.00 2,577.00 PIO1_38 PIO1_39 C12 D11 G18 F18 190 191 3,610.80 3,712.80 2,627.00 2,677.00 VPP_2V5 A14 E18 192 3,610.80 2,739.68 VPP_FAST VCC VCC A13 F8 F8 E17 K12 K12 193 194 195 3,096.90 2,997.00 2,947.00 2,962.80 2,860.80 2,962.80 PIO0_00 PIO0_01 C11 — E16 G16 196 197 2,897.00 2,847.00 2,860.80 2,962.80 PIO0_02 PIO0_03 A12 B11 E15 G15 198 199 2,797.00 2,747.00 2,860.80 2,962.80 PIO0_04 PIO0_05 — D10 H15 E14 200 201 2,697.00 2,647.00 2,860.80 2,962.80 PIO0_06 PIO0_07 A11 D9 G14 H14 202 203 2,612.00 2,577.00 2,860.80 2,962.80 GND GND H6 — E13 — 204 205 2,542.00 2,507.00 2,860.80 2,962.80 PIO0_08 PIO0_09 C10 A10 G13 H13 206 207 2,472.00 2,437.00 2,860.80 2,962.80 PIO0_10 PIO0_11 B10 E9 G12 H12 208 209 2,402.00 2,367.00 2,860.80 2,962.80 PIO0_12 PIO0_13 — — A18 A17 210 211 2,332.00 2,297.00 2,860.80 2,962.80 PIO0_14 PIO0_15 — — A16 A15 212 213 2,262.00 2,227.00 2,860.80 2,962.80 VCCIO_0 VCCIO_0 A8 — E12 — 214 215 2,192.00 2,157.00 2,860.80 2,962.80 PIO0_16 — C19 216 2,122.00 2,860.80 SiliconBlue Technologies Corporation www.SiliconBlueTech.com Y (µm) (1.31, 22-APR-2011) 71 iCE65 P-Series Ultra-Low Power mobileFPGA™ Family iCE65P04 Pad Name Available Packages DiePlus X (µm) CB284 C18 Pad PIO0_17 CB196 C9 217 2,087.00 2,962.80 PIO0_18 PIO0_19 B9 D8 C17 C16 218 219 2,052.00 2,017.00 2,860.80 2,962.80 PIO0_20 PIO0_21 C8 E8 C15 C14 220 221 1,982.00 1,947.00 2,860.80 2,962.80 PIO0_22 GBIN1/PIO0_23 B8 E7 C13 E11 222 223 1,912.00 1,877.00 2,860.80 2,962.80 GND GND B12 — C12 — 224 225 1,842.00 1,807.00 2,860.80 2,962.80 GBIN0/PIO0_24 PIO0_25 A7 D7 E10 C11 226 227 1,772.00 1,737.00 2,860.80 2,962.80 PIO0_26 PIO0_27 C7 E6 C10 C9 228 229 1,702.00 1,667.00 2,860.80 2,962.80 VCC VCC B7 — C8 — 230 231 1,632.00 1,597.00 2,860.80 2,962.80 PIO0_28 PIO0_29 A6 B6 C7 C6 232 233 1,562.00 1,527.00 2,860.80 2,962.80 PIO0_30 PIO0_31 A5 D6 C5 C4 234 235 1,492.00 1,457.00 2,860.80 2,962.80 GND GND F7 — K11 — 236 237 1,422.00 1,387.00 2,860.80 2,962.80 PIO0_32 PIO0_33 — — C3 A7 238 239 1,352.00 1,317.00 2,860.80 2,962.80 PIO0_34 PIO0_35 — — A6 A5 240 241 1,282.00 1,247.00 2,860.80 2,962.80 PIO0_36 VCCIO_0 VCCIO_0 PIO0_37 C6 F6 F6 C5 G11 K10 K10 H11 242 243 244 245 1,212.00 1,177.00 1,142.00 1,107.00 2,860.80 2,962.80 2,860.80 2,962.80 PIO0_38 PIO0_39 B5 A4 G10 E9 246 247 1,072.00 1,037.00 2,860.80 2,962.80 PIO0_40 PIO0_41 B4 D5 H10 G9 248 249 1,002.00 967.00 2,860.80 2,962.80 PIO0_42 GND PIO0_43 A3 G7 B3 E8 L11 H9 250 251 252 917.00 867.00 817.00 2,860.80 2,962.80 2,860.80 PIO0_44 PIO0_45 C4 A2 G8 E7 253 254 767.00 717.00 2,962.80 2,860.80 PIO0_46 PIO0_47 A1 B2 E6 E5 255 256 667.00 617.00 2,962.80 2,860.80 (1.31, 22-APR-2011) 72 Y (µm) SiliconBlue Technologies Corporation www.SiliconBlueTech.com SiliconBlue Electrical Characteristics All parameter limits are specified under worst-case supply voltage, junction temperature, and processing conditions. Absolute Maximum Ratings Stresses beyond those listed under Table 50 may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions beyond those listed under the Recommended Operating Conditions is not implied. Exposure to absolute maximum conditions for extended periods of time adversely affects device reliability. Table 50: Absolute Maximum Ratings Symbol VCC VPP_2V5 VPP_FAST VCCIO_0 VCCIO_1 VCCIO_2 SPI_VCC VCCIO_3 VIN_0 VIN_1 VIN_2 VIN_SPI VIN_3 VIN_VREF VCCPLL IOUT TJ TSTG Minimum Maximum Units Core supply Voltage VPP_2V5 NVCM programming and operating supply Optional fast NVCM programming supply I/O bank supply voltage (I/O Banks 0, 1, and 2 plus SPI interface) Description –0.5 1.42 –0.5 4.00 V V V V I/O Bank 3 supply voltage Voltage applied to PIO pin within a specific I/O bank (I/O Banks 0, 1, and 2 plus SPI interface) –0.5 –1.0 3.60 5.5 V V Voltage applied to PIO pin within I/O Bank 3 –0.5 3.60 V Analog voltage supply to the Phase Locked Loop (PLL) DC output current per pin Junction temperature Storage temperature, no bias –0.5 — –55 –65 3.60 20 125 150 V mA °C °C Recommended Operating Conditions Table 51: Recommended Operating Conditions Symbol VCC VPP_2V5 VPP_FAST SPI_VCC VCCIO_0 VCCIO_1 VCCIO_2 VCCIO_3 SPI_VCC VCCIO_3 VCCPLL TA TPROG NOTE: Description Core supply voltage VPP_2V5 NVCM programming and operating supply High Performance, low-power Release from Power-on Reset Configure from NVCM NVCM programming Optional fast NVCM programming supply SPI interface supply voltage I/O standards, all banks LVCMOS33 LVCMOS25, LVDS LVCMOS18, SubLVDS LVCMOS15 I/O standards only available in I/O Bank 3 SSTL2 SSTL18 MDDR Analog voltage supply to the Phase Locked Loop (PLL) Ambient temperature Commercial (C) Industrial (I) NVCM programming temperature Minimum Nominal Maximum Units 1.14 1.20 1.26 V 1.30 — 3.47 V 2.30 — 3.47 V 2.30 — 3.00 V Leave unconnected in application 1.71 — 3.47 V 2.70 3.30 3.47 V 2.38 2.50 2.63 V 1.71 1.80 1.89 V 1.43 1.50 1.58 V 2.38 1.71 1.71 1.71 0 –40 10 2.50 1.80 1.80 2.50 — — 25 2.63 1.89 1.89 2.63 70 85 30 V V V V °C °C °C VPP_FAST is only used for fast production programming. Leave floating or unconnected in application. When the iCE65P device is active, VPP_2V5 must be connected to a valid voltage. SiliconBlue Technologies Corporation www.SiliconBlueTech.com (1.31, 22-APR-2011) 73 iCE65 P-Series Ultra-Low Power mobileFPGA™ Family I/O Characteristics Table 52: PIO Pin Electrical Characteristics Symbol Il IOZ CPIO CGBIN RPULLUP VHYST Description Input pin leakage current Three-state I/O pin (Hi-Z) leakage current PIO pin input capacitance GBIN global buffer pin input capacitance Internal PIO pull-up resistance during configuration Input hysteresis Conditions VIN = VCCIOmax to 0 V VO = VCCIOmax to 0 V Minimum Nominal VCCIO = 3.3V VCCIO = 2.5V VCCIO = 1.8V VCCIO = 1.5V VCCIO = 1.2V VCCIO = 1.5V to 3.3V Maximum ±10 ±10 Units µA µA 6 6 pF pF 40 50 90 kΩ kΩ kΩ kΩ kΩ mV 50 NOTE: All characteristics are characterized and may or may not be tested on each pin on each device. Single-ended I/O Characteristics Table 53: I/O Characteristics (I/O Banks 0, 1, 2 and SPI only) I/O Standard LVCMOS33 LVCMOS25 LVCMOS18 Nominal I/O Bank Supply Voltage 3.3V 2.5V 1.8V LVCMOS15 1.5V Input Voltage (V) VIL 0.80 0.70 Output Voltage (V) VIH VOH 2.40 2.00 1.40 IOL IOH 0.4 0.4 0.4 8 6 4 8 6 4 0.4 1.20 2 2 VOL 2.00 1.70 35% VCCIO 65% VCCIO Not supported: Use I/O Bank 3 and SPI Bank Output Current at Voltage (mA) Table 54: I/O Characteristics (I/O Bank 3 only) I/O Standard LVCMOS33 Supply Voltage 3.3V Input Voltage (V) Max. VIL 0.80 Min. VIH 2.20 Output Voltage (V) Max. VOL 0.4 Min. VOH 2.40 LVCMOS25 2.5V 0.70 1.70 0.4 2.00 LVCMOS18 1.8V 35% VCCIO 65% VCCIO 0.4 VCCIO–0.45 LVCMOS15 1.5V 35% VCCIO 65% VCCIO 25% VCCIO 75% VCCIO MDDR 1.8V 35% VCCIO 65% VCCIO 0.4 VCCIO–0.45 SSTL2 (Class 2) 0.35 VREF–0.180 VREF+0.180 2.5V SSTL2 (Class 1) 0.54 SSTL18 (Full) 0.28 VREF–0.125 VREF+0.125 1.8V SSTL18 (Half) VTT–0.475 NOTES: SSTL2 and SSTL18 I/O standards require the VREF input pin, which is only available products. (1.31, 22-APR-2011) 74 VTT+0.430 VTT+0.280 VTT+0.475 I/O Attribute Name SL_LVCMOS33_8 SB_LVCMOS25_16 SB_LVCMOS25_12 SB_LVCMOS25_8 * SB_LVCMOS25_4 SB_LVCMOS18_10 SB_LVCMOS18_8 SB_LVCMOS18_4 * SB_LVCMOS18_2 SB_LVCMOS15_4 SB_LVCMOS15_2 * SB_MDDR10 SB_MDDR8 SB_MDDR4 * SB_MDDR2 SB_SSTL2_CLASS_2 SB_SSTL2_CLASS_1 SB_SSTL18_FULL SB_SSTL18_HALF mA at Voltage IOL. IOH ±8 ±16 ±12 ±8 ±4 ±10 ±8 ±4 ±2 ±4 ±2 ±10 ±8 ±4 ±2 ±16.2 ±8.1 ±13.4 ±6.7 on the CB284 package and for die-based SiliconBlue Technologies Corporation www.SiliconBlueTech.com SiliconBlue Differential Inputs Figure 41: Differential Input Specifications VCCIO_3 Differential input voltage 50% DPxxB 1% 100Ω Input common mode voltage VIN_B VID VIN_A DPxxA VICM iC65 Differential Input GND Input common mode voltage: VIC = VID =|VIN_B -VIN_A | Differential input voltage: I/O Standard VCCIO_3 2 Table 55: Recommended Operating Conditions for Differential Inputs VCCIO_3 (V) VID (mV) VICM (V) Min Nom Max Min Nom Max Min LVDS 2.38 2.50 2.63 250 350 450 VCCIO 2 SubLVDS 1.71 1.80 1.89 100 150 200 VCCIO 2 Nom Max VCCIO 2 VCCIO 2 VCCIO 2 VCCIO 2 Differential Outputs Figure 42: Differential Output Specifications VCCIO_x RS 1% RS VOUT_B Differential output voltage Output common mode voltage 50% RP VOD VOUT_A VOCM iC65 Differential Output Pair GND Output common mode voltage: Differential output voltage: VOC = VCCIO_x 2 VOD =|VOUT_B -VOUT_A | Table 56: Recommended Operating Conditions for Differential Outputs VCCIO_x (V) VOD (mV) Ω VOCM (V) I/O Standard Min Nom Max RS RP Min Nom Max LVDS 2.38 2.50 2.63 150 140 300 350 400 VCCIO 2 VCCIO 2 VCCIO 2 SubLVDS 1.71 1.80 1.89 270 120 100 150 200 VCCIO 2 VCCIO 2 VCCIO 2 SiliconBlue Technologies Corporation www.SiliconBlueTech.com Min Nom Max (1.31, 22-APR-2011) 75 iCE65 P-Series Ultra-Low Power mobileFPGA™ Family I/O Banks 0, 1, 2 and SPI Bank Characteristic Curves Figure 43: Typical LVCMOS Output Low Characteristics (I/O Banks 0, 1, 2, and SPI) VCCIO = 3.3V 50 IOL ( mA ) 40 30 VCCIO = 2.5V 20 VCCIO = 1.8V 10 VCCIO = 1.5V 0 0.0 0.5 1.0 1.5 VOL ( V ) 2.0 2.5 3.0 Figure 44: Typical LVCMOS Output High Characteristics (I/O Banks 0, 1, 2, and SPI) 0 VCCIO = 1.5V -10 IOH ( mA ) -20 VCCIO = 2.5V -30 VCCIO = 1.8V -40 -50 -60 VCCIO = 3.3V -70 0.0 0.5 1.0 1.5 2.0 2.5 3.0 VOH ( V ) Figure 45: Input with Internal Pull-Up Resistor Enabled (I/O Banks 0, 1, 2, and SPI) 0 -10 VCCIO = 1.8V -20 IIN (µA) -30 -40 VCCIO = 2.5V -50 -60 -70 -80 VCCIO = 3.3V -90 0.0 0.5 1.0 1.5 2.0 2.5 3.0 VIN (Volts) (1.31, 22-APR-2011) 76 SiliconBlue Technologies Corporation www.SiliconBlueTech.com SiliconBlue AC Timing Guidelines The following examples provide some guidelines of device performance. The actual performance depends on the specific application and how it is physically implemented in the iCE65P FPGA using the SiliconBlue iCEcube software. The following guidelines assume typical conditions (VCC = 1.0 V or 1.2 V as specified, temperature = 25 ˚C). Apply derating factors using the iCEcube timing analyzer to adjust to other operating regimes. Programmable Logic Block (PLB) Timing Table 57 provides timing information for the logic in a Programmable Logic Block (PLB), which includes the paths shown in Figure 46 and Figure 47. Figure 46 PLB Sequential Timing Circuit PAD PIO PAD DFF PIO D Q LUT4 GBIN Logic Logic Cell Cell GBUF Figure 47 PLB Combinational Timing Circuit PAD PIO PAD PIO LUT4 Logic Cell Table 57: Typical Programmable Logic Block (PLB) Timing Power/Speed Grade –T Nominal VCC 1.2 V Symbol From To Description Sequential Logic Paths FTOGGLE GBIN GBIN Flip-flop toggle frequency. DFF flip-flop output fed back to LUT4 input with input input 4-input XOR, clocked on same clock edge Logic cell flip-flop (DFF) clock-to-output time, measured from the DFF CLK tCKO DFF PIO clock output input to PIO output, including interconnect delay. input Global Buffer Input (GBIN) delay, though Global Buffer (GBUF) clock network tGBCKLC GBIN DFF input clock to clock input on the logic cell DFF flip-flop. input tSULI PIO GBIN Minimum setup time on PIO input, through LUT4, to DFF flip-flop D-input input input before active clock edge on the GBIN input, including interconnect delay. Minimum hold time on PIO input, through LUT4, to DFF flip-flop D-input tHDLI GBIN PIO input input after active clock edge on the GBIN input, including interconnect delay. Combinational Logic Paths tLUT4IN PIO LUT4 Asynchronous delay from PIO input pad to adjacent PLB interconnect. input input tILO LUT4 LUT4 Logic cell LUT4 combinational logic propagation delay, regardless of logic input output complexity from input to output. Asynchronous delay from adjacent PLB interconnect to PIO output tLUT4IN LUT4 PIO output output pad. SiliconBlue Technologies Corporation www.SiliconBlueTech.com Typ. Units 256 MHz 7.1 ns 2.7 ns 1.2 ns 0 ns 3.3 ns 0.62 ns 6.6 ns (1.31, 22-APR-2011) 77 iCE65 P-Series Ultra-Low Power mobileFPGA™ Family Programmable Input/Output (PIO) Block Table 58 provides timing information for the logic in a Programmable Logic Block (PLB), which includes the paths shown in Figure 48 and Figure 49. The timing shown is for the LVCMOS25 I/O standard in all I/O banks. The iCEcube development software reports timing adjustments for other I/O standards. Figure 48: Programmable I/O (PIO) Pad-to-Pad Timing Circuit PAD PIO PAD PIO Figure 49: Programmable I/O (PIO) Sequential Timing Circuit PAD PIO PIO PAD INFF D Q GBIN OUTFF D Q GBUF Table 58: Typical Programmable Input/Output (PIO) Timing (LVCMOS25) Power/Speed Grad –T Nominal VCC 1.2 V Description Symbol From To Synchronous Output Paths OUTFF Delay from clock input on OUTFF output flip-flop to PIO output tOCKO PIO clock output pad. input OUTFF Global Buffer Input (GBIN) delay, though Global Buffer (GBUF) tGBCKIO GBIN clock clock network to clock input on the PIO OUTFF output flip-flop. input input Synchronous Input Paths Setup time on PIO input pin to INFF input flip-flop before active tSUPDIN PIO GBIN clock edge on GBIN input, including interconnect delay. input input Hold time on PIO input to INFF input flip-flop after active clock tHDPDIN GBIN PIO edge on the GBIN input, including interconnect delay. input input Pad to Pad InterAsynchronous delay from PIO input pad to adjacent tPADIN PIO connect interconnect. input InterAsynchronous delay from adjacent interconnect to PIO output tPADO PIO connect output pad including interconnect delay. (1.31, 22-APR-2011) 78 Typ. Units 5.6 ns 2.6 ns 0 ns 2.8 ns 3.2 ns 6.2 ns SiliconBlue Technologies Corporation www.SiliconBlueTech.com SiliconBlue RAM4K Block Table 59 provides timing information for the logic in a RAM4K block, which includes the paths shown in Figure 50. Figure 50: RAM4K Timing Circuit PAD GBIN PIO WDATA RDATA RAM4K RAM Block (256x16) GBUF WCLK PIO PAD GBUF Table 59: Typical RAM4K Block Timing Power/Speed Grade Nominal VCC Symbol From To Description Write Setup/Hold Time tSUWD PIO GBIN Minimum write data setup time on PIO inputs before active clock input input edge on GBIN input, include interconnect delay. Minimum write data hold time on PIO inputs after active clock edge tHDWD GBIN PIO input input on GBIN input, including interconnect delay. Read Clock-Output-Time Clock-to-output delay from RCLK input pin, through RAM4K RDATA tCKORD RCLK PIO clock output output flip-flop to PIO output pad, including interconnect delay. input tGBCKRM GBIN RCLK Global Buffer Input (GBIN) delay, though Global Buffer (GBUF) input clock clock network to the RCLK clock input. input Write and Read Clock Characteristics WCLK WCLK Write clock High time tRMWCKH RCLK RCLK Write clock Low time tRMWCKL Write clock cycle time tRMWCYC Sustained write clock frequency FWMAX SiliconBlue Technologies Corporation www.SiliconBlueTech.com GBIN RCLK –T 1.2 V Typ. Units 0.8 ns 0 ns 7.3 ns 2.6 ns 0.54 0.63 1.27 256 ns ns ns MHz (1.31, 22-APR-2011) 79 iCE65 P-Series Ultra-Low Power mobileFPGA™ Family Phase-Locked Loop (PLL) Block Table 59 provides timing information for the Phase-Locked Loop (PLL) block shown in Figure 50. Figure 51: Phase-Locked Loop (PLL) PLL LATCHINPUTVALUE DYNAMICDELAY[3:0] EXTFEEDBACK BYPASS RESET REFERENCECLK LOCK PLLOUT Table 60: Phase-Locked Loop (PLL) Block Timing Power/Speed Grade –T Nominal VCC 1.2 V Symbol From Frequency Range FREF FOUT Duty Cycle PLLIJ TwHI TwLOW PLLOJD PLLOJM Fine Delay tFDTAP PLLTAPS PLLFDAM Jitter PLLIPJ PLLOPJ Lock/Reset Time tLOCK twRST To Min. Typical Max. Units Input clock frequency range Output clock frequency range (cannot exceed maximum frequency supported by global buffers) 10 10 — — 133 533 MHz MHz Input duty cycle Input clock high time Input clock low time Output duty cycle (divided frequency) Output duty cycle (undivided frequency) 35 2.5 2.5 45 40 — — — — — 65 — — 55 60 % ns ns % % Fine delay adjustment, per tap Fine delay adjustment settings Maximum delay adjustment 0 165 — 2.5 15 ps taps ns Input clock period jitter PLLOUT output period jitter — — — 1% or ≤ 100 +/- 300 +/- 1.1% output period or ≥ 110 ps ps PLL lock time after receive stable, monotonic REFERENCECLK input Minimum reset pulse width — — 50 μs 20 — — ns Description Notes: 1. Output jitter performance is affected by input jitter. A clean reference clock < 100ps jitter must be used to ensure best jitter performance. 2. The output jitter specification refers to the intrinsic jitter of the PLL. (1.31, 22-APR-2011) 80 SiliconBlue Technologies Corporation www.SiliconBlueTech.com SiliconBlue Internal Configuration Oscillator Frequency Table 61 shows the operating frequency for the iCE65‟s internal configuration oscillator. Table 61: Internal Oscillator Frequency Symbol fOSCD fOSCL fOSCH Frequency (MHz) Min. Max. 4.0 6.8 Oscillator Mode Default Low Frequency High Frequency Off 14 21 Description Default oscillator frequency. Slow enough to safely operate with any SPI serial PROM. Supported by most SPI serial Flash PROMs 21 31 Supported by some high-speed SPI serial Flash PROMs 0 0 Oscillator turned off by default after configuration to save power. Configuration Timing Table 62 shows the maximum time to configure an iCE65P device, by oscillator mode. The calculations use the slowest frequency for a given oscillator mode from Table 61 and the maximum configuration bitstream size from Table 1, which includes full RAM4K block initialization. The configuration bitstream selects the desired oscillator mode based on the performance of the configuration data source. Table 62: Maximum SPI Master or NVCM Configuration Timing by Oscillator Mode Symbol tCONFIGL Description Time from when minimum Power-on Reset (POR) threshold is reached until user application starts. Device Default Low Freq. High Freq. Units iCE65P04 115 55 25 ms Table 63 provides timing for the CRESET_B and CDONE pins. Table 63: General Configuration Timing Symbol tCRESET_B tDONE_IO From To Description CREST_B CREST_B CDONE High PIO pins active Minimum CRESET_B Low pulse width required to restart configuration, from falling edge to rising edge Number of configuration clock cycles after CDONE goes High before the PIO pins are activated. SPI Peripheral Mode (Clock = SPI_SCK, cycles measured rising-edge to rising-edge) NVCM or SPI Master Mode by internal Default oscillator frequency setting (Clock = Low internal oscillator)s High SiliconBlue Technologies Corporation www.SiliconBlueTech.com All Grades Min. Max. 200 — — 49 Units ns Clock cycles Depends on SPI_SCK frequency 7.20 2.34 1.59 12.25 3.50 2.33 µs µs µs (1.31, 22-APR-2011) 81 iCE65 P-Series Ultra-Low Power mobileFPGA™ Family Table 64 provides various timing specifications for the SPI peripheral mode interface. Table 64: SPI Peripheral Mode Timing Symbol tCR_SCK From To Description CRESET_B SPI_SCK Minimum time from a rising edge on CRESET_B until the first SPI write operation, first SPI_SCK. During this time, the iCE65P FPGA is clearing its internal configuration memory SPI_SI SPI_SCK Setup time on SPI_SI before the rising SPI_SCK clock tSUSPISI edge SPI_SCK SPI_SI Hold time on SPI_SI after the rising SPI_SCK clock edge tHDSPISI SPI_SCK SPI_SCK SPI_SCK clock High time tSPISCKH SPI_SCK SPI_SCK SPI_SCK clock Low time tSPISCKL tSPISCKCYC SPI_SCK SPI_SCK SPI_SCK clock period* SPI_SCK SPI_SCK Sustained SPI_SCK clock frequency* FSPI_SCK * = Applies after sending the synchronization pattern. All Grades Min. Max. 300 — Units µs 12 — ns 12 20 20 40 1 — — — 1,000 25 ns ns ns ns MHz Power Consumption Characteristics Core Power Table 65 shows the power consumed on the internal VCC supply rail when the device is filled with 16-bit binary counters, measured with a 32.768 kHz and at 32.0 MHz Table 65: VCC Power Consumption for Device Filled with 16-Bit Binary Counters iCE65P04 Symbol Description Grade VCC Typical ICC0K ICC32K ICC32M f =0 f ≤ 32.768 kHz f = 32.0 MHz –T –T –T 1.2V 1.2V 1.2V 45 52 8 Max. Units µA µA mA I/O Power Table 66 provides the static current by I/O bank. The typical current for I/O Banks 0, 1, 2 and the SPI bank is not measurable within the accuracy of the test environment. The PIOs in I/O Bank 3 use different circuitry and dissipate a small amount of static current. Table 66: I/O Bank Static Current (f = 0 MHz) Symbol ICCO_0 ICCO_1 ICCO_2 ICCO_3 ICCO_SPI Description I/O Bank 0 I/O Bank 1 I/O Bank 2 I/O Bank 3 SPI Bank Static current consumption per I/O bank. f = 0 MHz. No PIO pull-up resistors enabled. All inputs grounded. All outputs driving Low. Typical Maximum «1 «1 «1 1.2 «1 Units uA uA uA uA uA NOTE: The typical static current for I/O Banks 0, 1, 2, and the SPI bank is less than the accuracy of the device tester. Power Estimator To estimate the power consumption for a specific application, please download and use the iCE65P Power Estimator Spreadsheet our use the power estimator built into the iCEcube software. (1.31, 22-APR-2011) 82 SiliconBlue Technologies Corporation www.SiliconBlueTech.com SiliconBlue Notes: SiliconBlue Technologies Corporation www.SiliconBlueTech.com (1.31, 22-APR-2011) 83 iCE65 P-Series Ultra-Low Power mobileFPGA™ Family Revision History Version 1.31 Date 22-APR-2011 1.3 17-DEC-2010 1.2 08-OCT-2010 Description Updated Figure 35: iCE65P04 CB121 Chip-Scale BGA Footprint (Top View) A10 to PIO0 and G1 to PIO3/DP08B. Updated Table 46: iCE65P04 CB121 Chipscale BGA Pinout Table F4 to GBIN6/PIO3/DP06A and G4 to PIO3/DP06B. Updated Table 60: Phase-Locked Loop (PLL) Block Timing duty cycle, jitter and lock/reset time parameters Changed FSPI_SCK from 0.125 MHz to 1 MHz in SPI Peripheral Configuration Process and Table 64. Updated equation: PLLOUT Frequency for FEEDBACK_PATH = SIMPLE 1.1 1.0 06-AUG-2010 15-FEB-2010 Added CB121 package. Removed Programmable Interconnect description Initial Release SiliconBlue Technologies Sales Partner Network For sales information, contact your local business partners listed on the link below or contact www.siliconbluetech.com Optionally, contact sales@siliconbluetech.com via E-mail. Copyright © 2007–2011 by SiliconBlue Technologies LTD. All rights reserved. SiliconBlue is a registered trademark of SiliconBlue Technologies LTD in the United States. Specific device designations, and all other words and logos that are identified as trademarks are, unless noted otherwise, the trademarks of SiliconBlue Technologies LTD. All other product or service names are the property of their respective holders. SiliconBlue products are protected under numerous United States and foreign patents and pending applications, maskwork rights, and copyrights. SiliconBlue warrants performance of its semiconductor products to current specifications in accordance with SiliconBlue's standard warranty, but reserves the right to make changes to any products and services at any time without notice. SiliconBlue assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by SiliconBlue Technologies LTD. SiliconBlue customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. R SiliconBlue SiliconBlue Technologies Corporation cumentati on s ervi ces by Prevail ing Technol ogy, Inc. ( www.pre vai ling-technol ogy.com ) (1.31, 22-APR-2011) 84 3255 Scott Blvd. Building 7, Suite 101 Santa Clara, California 95054 United States of America Tel: +1 408-727-6101 Fax: +1 408-727-6085 www.SiliconBlueTech.com SiliconBlue Technologies Corporation www.SiliconBlueTech.com
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