LeadFree
Package
Options
Available!
Features
®
ispGDX 240VA
In-System Programmable
3.3V Generic Digital Crosspoint
Functional Block Diagram
ISP
Control
I/O Pins A
I/O Pins D
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— 3.3V Core Power Supply
— 4.5ns Input-to-Output/4.0ns Clock-to-Output Delay
— 200MHz Maximum Clock Frequency
— TTL/3.3V/2.5V Compatible Input Thresholds and
Output Levels (Individually Programmable)
— Low-Power: 20.0mA Quiescent Icc
— 24mA IOL Drive with Programmable Slew Rate
Control Option
— PCI Compatible Drive Capability
— Schmitt Trigger Inputs for Noise Immunity
— Electrically Erasable and Reprogrammable
— Non-Volatile E2CMOS Technology
I/O
Cells
Boundary
Scan
Control
Global Routing
Pool
(GRP)
I/O
Cells
I/O Pins C
• IN-SYSTEM PROGRAMMABLE GENERIC DIGITAL
CROSSPOINT FAMILY
— 240 I/O, “Any Input to Any Output” Routing
— Advanced Architecture Addresses Programmable
PCB Interconnect, Bus Interface Integration and
Jumper/Switch Replacement
— Fixed HIGH or LOW Output Option for Jumper/DIP
Switch Emulation
— Space-Saving Fine Pitch BGA Packaging
— Dedicated IEEE 1149.1-Compliant Boundary Scan
Test
I/O Pins B
Description
• ispGDXVA OFFERS THE FOLLOWING ADVANTAGES
— 3.3V In-System Programmable Using Boundary Scan
Test Access Port (TAP)
— Change Interconnects in Seconds
• FLEXIBLE ARCHITECTURE
— Combinatorial/Latched/Registered Inputs or Outputs
— Individual I/O Tri-state Control with Polarity Control
— Dedicated Clock/Clock Enable Input Pins (four) or
Programmable Clocks/Clock Enables from I/O Pins (60)
— Single Level 4:1 Dynamic Path Selection (Tpd = 4.5ns)
— Programmable Wide-MUX Cascade Feature
Supports up to 16:1 MUX
— Programmable Pull-ups, Bus Hold Latch and Open
Drain on I/O Pins
— Outputs Tri-state During Power-up (“Live Insertion”
Friendly)
• LEAD-FREE PACKAGE OPTIONS
The ispGDXVA architecture provides a family of fast,
flexible programmable devices to address a variety of
system-level digital signal routing and interface requirements including:
• Multi-Port Multiprocessor Interfaces
• Wide Data and Address Bus Multiplexing
(e.g. 16:1 High-Speed Bus MUX)
• Programmable Control Signal Routing
(e.g. Interrupts, DMAREQs, etc.)
• Board-Level PCB Signal Routing for Prototyping or
Programmable Bus Interfaces
The ispGDX240VA device features fast operation, with
input-to-output signal delays (Tpd) of 4.5ns and clock-tooutput delays of 4.0ns.
The architecture of the devices consists of a series of
programmable I/O cells interconnected by a Global Routing Pool (GRP). All I/O pin inputs enter the GRP directly
or are registered or latched so they can be routed to the
required I/O outputs. I/O pin inputs are defined as four
sets (A,B,C,D) which have access to the four MUX inputs
Copyright © 2004 Lattice Semiconductor Corporation. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein
are subject to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
gdx240va_06
1
August 2004
Specifications ispGDX240VA
Description (Continued)
found in each I/O cell. Each output has individual, programmable I/O tri-state control (OE), output latch clock
(CLK), clock enable (CLKEN), and two multiplexer control (MUX0 and MUX1) inputs. Polarity for these signals
is programmable for each I/O cell. The MUX0 and MUX1
inputs control a fast 4:1 MUX, allowing dynamic selection
of up to four signal sources for a given output. A wider
16:1 MUX can be implemented with the MUX expander
feature of each I/O and a propagation delay increase of
2.0ns. OE, CLK, CLKEN, and MUX0 and MUX1 inputs
can be driven directly from selected sets of I/O pins.
Optional dedicated clock input pins give minimum clockto-output delays. CLK and CLKEN share the same set of
I/O pins. CLKEN disables the register clock when
CLKEN = 0.
In addition, there are no pin-to-pin routing constraints for
1:1 or 1:n signal routing. That is, any I/O pin configured
as an input can drive one or more I/O pins configured as
outputs.
Through in-system programming, connections between
I/O pins and architectural features (latched or registered
inputs or outputs, output enable control, etc.) can be
defined. In keeping with its data path application focus,
the ispGDXVA devices contain no programmable logic
arrays. All input pins include Schmitt trigger buffers for
noise immunity. These connections are programmed
into the device using non-volatile E2CMOS technology.
Non-volatile technology means the device configuration
is saved even when the power is removed from the
device.
All I/O pins are equipped with IEEE1149.1-compliant
Boundary Scan Test circuitry for enhanced testability. In
addition, in-system programming is supported through
the Test Access Port via a special set of private commands.
The device pins also have the ability to set outputs to
fixed HIGH or LOW logic levels (Jumper or DIP Switch
mode). Device outputs are specified for 24mA sink and
12mA source current (at JEDEC LVTTL levels) and can
be tied together in parallel for greater drive. On the
ispGDXVA, each I/O pin is individually programmable for
3.3V or 2.5V output levels as described later. Programmable output slew rate control can be defined
independently for each I/O pin to reduce overall ground
bounce and switching noise.
The ispGDXVA I/Os are designed to withstand “live
insertion” system environments. The I/O buffers are
disabled during power-up and power-down cycles. When
designing for “live insertion,” absolute maximum rating
conditions for the Vcc and I/O pins must still be met.
Table 1. ispGDXVA Family Members
ispGDXV/VA Device
ispGDX80VA
ispGDX160V/VA
ispGDX240VA
I/O Pins
80
160
240
I/O-OE Inputs*
20
40
60
I/O-CLK / CLKEN Inputs*
20
40
60
I/O-MUXsel1 Inputs*
I/O-MUXsel2 Inputs*
20
20
40
40
60
60
Dedicated Clock Pins**
2
4
4
EPEN
1
1
1
TOE
1
4
1
1
4
1
1
4
1
BSCAN Interface
RESET
Pin Count/Package
100-Pin TQFP
208-Pin PQFP 388-Ball fpBGA
208-Ball fpBGA
272-Ball BGA
* The CLK/CLK_EN, OE, MUX0 and MUX1 terminals on each I/O cell can each be assigned to
25% of the I/Os.
** Global clock pins Y0, Y1, Y2 and Y3 are multiplexed with CLKEN0, CLKEN1, CLKEN2 and
CLKEN3 respectively in all devices.
2
Specifications ispGDX240VA
Architecture
The ispGDXVA architecture is different from traditional
PLD architectures, in keeping with its unique application
focus. The block diagram is shown below. The programmable interconnect consists of a single Global Routing
Pool (GRP). Unlike ispLSI® devices, there are no programmable logic arrays on the device. Control signals for
OEs, Clocks/Clock Enables and MUX Controls must
come from designated sets of I/O pins. The polarity of
these signals can be independently programmed in each
I/O cell.
The various I/O pin sets are also shown in the block
diagram below. The A, B, C, and D I/O pins are grouped
together with one group per side.
I/O Architecture
Each I/O cell contains a 4:1 dynamic MUX controlled by
two select lines as well as a 4x4 crossbar switch controlled by software for increased routing flexiability (Figure
1). The four data inputs to the MUX (called M0, M1, M2,
and M3) come from I/O signals in the GRP and/or
adjacent I/O cells. Each MUX data input can access one
quarter of the total I/Os. For example, in a 240-I/O
ispGDXVA, each data input can connect to one of 60 I/O
pins. MUX0 and MUX1 can be driven by designated I/O
pins called MUXsel1 and MUXsel2. Each MUXsel input
covers 25% of the total I/O pins (e.g. 60 out of 240). MUX0
and MUX1 can be driven from either MUXsel1 or MUXsel2.
Each I/O cell drives a unique pin. The OE control for each
I/O pin is independent and may be driven via the GRP by
one of the designated I/O pins (I/O-OE set). The I/O-OE
set consists of 25% of the total I/O pins. Boundary Scan
test is supported by dedicated registers at each I/O pin.
In-system programming is accomplished through the
standard Boundary Scan protocol.
Figure 1. ispGDXVA I/O Cell and GRP Detail (240 I/O Device)
Logic “0” Logic “1”
240 I/O Inputs
I/OCell 0
I/O Cell 239
I/O Cell 1
I/O Cell 238
••
•
E2CMOS
Programmable
Interconnect
To 2 Adjacent
I/O Cells above
From MUX Outputs
of 2 Adjacent I/O Cells
4-to-1 MUX
N+2
I/O Group A
I/O Group B
I/O Group C
I/O Group D
N+1
N-1
•
•
•
•
•
•
Register
or Latch
M0
M1
M2
M3
MUX0 MUX1
4x4
Crossbar
Switch
N-2
From MUX Outputs
of 2 Adjacent I/O Cells
Prog.
Prog.
Pull-up Bus Hold
Latch
(VCCIO)
Bypass Option
A
B
D
Q
I/O
Pin
C
R
CLK
To 2 Adjacent
I/O Cells below
CLK_EN Reset
Prog. Open Drain
2.5V/3.3V Output
Prog. Slew Rate
Boundary
Scan Cell
I/O Cell N
••
•
I/O Cell 118
I/O Cell 121
••••••
I/O Cell 119
120 I/O Cells
I/O Cell 120
120 I/O Cells
240 Input GRP
Inputs Vertical
Outputs Horizontal
Global
Y0-Y3
Reset
Global
Clocks /
Clock_Enables
ispGDXVA architecture enhancements over ispGDX (5V)
3
Specifications ispGDX240VA
allow adjacent I/O cell outputs to be directly connected
without passing through the global routing pool. The
relationship between the [N+i] adjacent cells and A, B, C
and D inputs will vary depending on where the I/O cell is
located on the physical die. The I/O cells can be grouped
into “normal” and “reflected” I/O cells or I/O “hemispheres.” These are defined as:
I/O MUX Operation
0
0
M0
0
1
M1
1
1
M2
1
0
M3
Device
Flexible mapping of MUXselx to MUXx allows the user to
change the MUX select assignment after the ispGDXVA
device has been soldered to the board. Figure 1 shows
that the I/O cell can accept (by programming the appropriate fuses) inputs from the MUX outputs of four adjacent
I/O cells, two above and two below. This enables cascading of the MUXes to enable wider (up to 16:1) MUX
implementations.
ispGDX80VA
Normal I/O Cells
Reflected I/O Cells
TBA
TBA
ispGDX160V/VA B19-B0, A39-A20,
A19-A0, D39-D20
ispGDX240VA
B20-B39, C0-C19,
C20-C39, D0-D19
TBA
TBA
Table 2 shows the relationship between adjacent I/O
cells as well as their relationship to direct MUX inputs.
Note that the MUX expansion is circular and that I/O cell
B30, for example, draws on I/Os B29 and B28, as well as
B31 and B32, even though they are in different hemispheres of the physical die. Table 2 shows some typical
cases and all boundary cases. All other cells can be
extrapolated from the pattern shown in the table.
The I/O cell also includes a programmable flow-through
latch or register that can be placed in the input or output
path and bypassed for combinatorial outputs. As shown
in Figure 1, when the input control MUX of the register/
latch selects the “A” path, the register/latch gets its inputs
from the 4:1 MUX and drives the I/O output. When
selecting the “B” path, the register/latch is directly driven
by the I/O input while its output feeds the GRP. The
programmable polarity Clock to the latch or register can
be connected to any I/O in the I/O-CLK/CLKEN set (onequarter of total I/Os) or to one of the dedicated clock input
pins (Yx). The programmable polarity Clock Enable input
to the register can be programmed to connect to any of
the I/O-CLK/CLKEN input pin set or to the global clock
enable inputs (CLKENx). Use of the dedicated clock
inputs gives minimum clock-to-output delays and minimizes delay variation with fanout. Combinatorial output
mode may be implemented by a dedicated architecture
bit and bypass MUX. I/O cell output polarity can be
programmed as active high or active low.
Figure 2. I/O Hemisphere Configuration of
ispGDX240VA
MUX Expander Using Adjacent I/O Cells
D59
D30
D29
D0
B0
B29
B30
B59
A59
The ispGDXVA allows adjacent I/O cell MUXes to be
cascaded to form wider input MUXes (up to 16 x 1)
without incurring an additional full Tpd penalty. However,
there are certain dependencies on the locality of the
adjacent MUXes when used along with direct MUX
inputs.
I/O cell 239
A0
I/O cell index increases in this direction
I/O cell 0
I/O cell index increases in this direction
Data Input Selected
C59
MUX0
C0
MUX1
I/O cell 119 I/O cell 120
Adjacent I/O Cells
Direct and Expander Input Routing
Expansion inputs MUXOUT[n-2], MUXOUT[n-1],
MUXOUT[n+1], and MUXOUT[n+2] are fuse-selectable
for each I/O cell MUX. These expansion inputs share the
same path as the standard A, B, C and D MUX inputs, and
Table 2 also illustrates the routing of MUX direct inputs
that are accessible when using adjacent I/O cells as
inputs. Take I/O cell D33 as an example, which is also
shown in Figure 3.
4
Specifications ispGDX240VA
Figure 3. Adjacent I/O Cells vs. Direct Input Path for
ispGDX240VA, I/O D33
Special Features
Slew Rate Control
ispGDX240VA I/O Cell
All output buffers contain a programmable slew rate
control that provides software-selectable slew rate options.
I/O Group A
D31 MUX Out
S1 S0
I/O Group B
.m0
4x4
Crossbar
Switch
D32 MUX Out
I/O Group C
.m1
.m2
Open Drain Control
D33
All output buffers provide a programmable Open-Drain
option which allows the user to drive system level reset,
interrupt and enable/disable lines directly without the
need for an off-chip Open-Drain or Open-Collector buffer.
Wire-OR logic functions can be performed at the printed
circuit board level.
.m3
D34 MUX Out
I/O Group D
D35 MUX Out
It can be seen from Figure 3 that if the D31 adjacent I/O
cell is used, the I/O group “A” input is no longer available
as a direct MUX input.
Pull-up Resistor
All pins have a programmable active pull-up. A typical
resistor value for the pull-up ranges from 50kΩ to 80kΩ.
The ispGDXVA can implement MUXes up to 16 bits wide
in a single level of logic, but care must be taken when
combining adjacent I/O cell outputs with direct MUX
inputs. Any particular combination of adjacent I/O cells as
MUX inputs will dictate what I/O groups (A, B, C or D) can
be routed to the remaining inputs. By properly choosing
the adjacent I/O cells, all of the MUX inputs can be
utilized.
Output Latch (Bus Hold)
All pins have a programmable circuit that weakly holds
the previously driven state when all drivers connected to
the pin (including the pin's output driver as well as any
other devices connected to the pin by external bus) are
tristated.
Table 2. Adjacent I/O Cells (Mapping of
ispGDX240VA)
User-Programmable I/Os
The ispGDX240VA features user-programmable
I/Os supporting either 3.3V or 2.5V output voltage level
options. The ispGDX240VA uses a VCCIO pin to provide
the 2.5V reference voltage when used.
Data A/ Data B/ Data C/ Data D/
MUXOUT MUXOUT MUXOUT MUXOUT
Reflected
I/O Cells
Normal
I/O Cells
B30
B32
B31
B29
B28
B31
B32
B33
B34
B32
B33
B30
B31
B29
B30
B33
B35
B34
B32
B31
D26
D28
D27
D25
D24
D27
D29
D28
D26
D25
D28
D30
D29
D27
D26
D29
D31
D30
D28
D27
D30
D28
D29
D31
D32
D31
D29
D30
D32
D33
D32
D30
D31
D33
D34
D33
D31
D32
D34
D35
B26
B24
B25
B27
B28
B27
B25
B26
B28
B29
B28
B26
B27
B27
B29
B30
B30
B29
B28
PCI Compatible Drive Capability
The ispGDX240VA supports PCI compatible drive capability for all I/Os.
B31
5
Specifications ispGDX240VA
Applications
Programmable Switch Replacement (PSR)
The ispGDXVA Family architecture has been developed
to deliver an in-system programmable signal routing
solution with high speed and high flexibility. The devices
are targeted for three similar but distinct classes of endsystem applications:
Includes solid-state replacement and integration of mechanical DIP Switch and jumper functions. Through
in-system programming, pins of the ispGDXVA devices
can be driven to HIGH or LOW logic levels to emulate the
traditional device outputs. PSR functions do not require
any input pin connections.
Programmable, Random Signal
Interconnect (PRSI)
These applications actually require somewhat different
silicon features. PRSI functions require that the device
support arbitrary signal routing on-chip between any two
pins with no routing restrictions. The routing connections
are static (determined at programming time) and each
input-to-output path operates independently. As a result,
there is little need for dynamic signal controls (OE,
clocks, etc.). Because the ispGDXVA device will interface with control logic outputs from other components
(such as ispLSI or ispMACH™) on the board (which
frequently change late in the design process as control
logic is finalized), there must be no restrictions on pin-topin signal routing for this type of application.
This class includes PCB-level programmable signal routing and may be used to provide arbitrary signal swapping
between chips. It opens up the possibilities of programmable system hardware. It is characterized by the need
to provide a large number of 1:1 pin connections which
are statically configured, i.e., the pin-to-pin paths do not
need to change dynamically in response to control inputs.
Programmable Data Path (PDP)
This application area includes system data path transceiver, MUX and latch functions. With today’s 32- and
64-bit microprocessor buses, but standard data path glue
components still relegated primarily to eight bits, PCBs
are frequently crammed with a dozen or more data path
glue chips that use valuable real estate. Many of these
applications consist of “on-board” bus and memory interfaces that do not require the very high drive of standard
glue functions but can benefit from higher integration.
Therefore, there is a need for a flexible means to integrate these on-board data path functions in an analogous
way to programmable logic’s solution to control logic
integration. Lattice’s CPLDs make an ideal control logic
complement to the ispGDXVA in-system programmable
data path devices as shown below.
PDP functions, on the other hand, require the ability to
dynamically switch signal routing (MUXing) as well as
latch and tri-state output signals. As a result, the programmable interconnect is used to define possible signal
routes that are then selected dynamically by control
signals from an external MPU or control logic. These
functions are usually formulated early in the conceptual
design of a product. The data path requirements are
driven by the microprocessor, bus and memory architecture defined for the system. This part of the design is the
earliest portion of the system design frozen, and will not
usually change late in the design because the result
would be total system and PCB redesign. As a result, the
ability to accommodate arbitrary any pin-to-any pin rerouting is not a strong requirement as long as the designer
has the ability to define his functions with a reasonable
degree of freedom initially.
Figure 4. ispGDXVA Complements Lattice CPLDs
Address
Inputs
(from µP)
Control
Inputs
(from µP)
State Machines
ispLSI/
ispMACH
Device
Decoders
System
Clock(s)
Data Path
Bus #1
Buffers / Registers
Control
Outputs
As a result, the ispGDXVA architecture has been defined
to support PSR and PRSI applications (including bidirectional paths) with no restrictions, while PDP applications
(using dynamic MUXing) are supported with a minimal
number of restrictions as described below. In this way,
speed and cost can be optimized and the devices can still
support the system designer’s needs.
ISP/JTAG
Interface
ispGDXVA
Device
Buffers / Registers
Configuration
(Switch)
Outputs
The following diagrams illustrate several ispGDXVA applications.
Data Path
Bus #2
6
Specifications ispGDX240VA
Applications (Continued)
Figure 5. Address Demultiplex/Data Buffering
Designing with the ispGDXVA
As mentioned earlier, this architecture satisfies the PRSI
class of applications without restrictions: any I/O pin as a
single input or bidirectional can drive any other I/O pin as
output.
Control Bus
MUXed Address Data Bus
XCVR
I/OA
I/OB
OEA
OEB
Buffered
Data
For the case of PDP applications, the designer does have
to take into consideration the limitations on pins that can
be used as control (MUX0, MUX1, OE, CLK) or data
(MUXA-D) inputs. The restrictions on control inputs are
not likely to cause any major design issues because the
input possibilities span 25% of the total pins.
To Memory/
Peripherals
Address
Latch
D
Address
Q
The MUXA-D input partitioning requires that designers
consciously assign pinouts so that MUX inputs are in the
appropriate, disjoint groups. For example, since the
MUXA group includes I/O A0-39 (240 I/O device), it is not
possible to use I/O A0 and I/O A9 in the same MUX
function. As previously discussed, data path functions
will be assigned early in the design process and these
restrictions are reasonable in order to optimize speed
and cost.
CLK
Figure 6. Data Bus Byte Swapper
XCVR
I/OA
D0-7
I/OB
XCVR
Data Bus A
Control Bus
OEA OEB
I/OA
I/OB
OEA OEB
XCVR
D8-15
I/OA
User Electronic Signature
Data Bus B
D0-7
The ispGDXVA Family includes dedicated User Electronic Signature (UES) E2CMOS storage to allow users
to code design-specific information into the devices to
identify particular manufacturing dates, code revisions,
or the like. The UES information is accessible through
the boundary scan programming port via a specific command. This information can be read even when the
security cell is programmed.
D8-15
I/OB
XCVR
OEA OEB
I/OA
I/OB
OEA OEB
Security
The ispGDXVA Family includes a security feature that
prevents reading the device program once set. Even
when set, it does not inhibit reading the UES or device ID
code. It can be erased only via a device bulk erase.
Figure 7. Four-Port Memory Interface
Bus 1
Bus 2
Bus 3
Bus 4
4-to-1
16-Bit MUX
Bidirectional
Port #1
OE1
Memory
Port
Port #2
OE2
OEM
Port #3
OE3
SEL0
Port #4
OE4
SEL1
To
Memory
Note: All OE and SEL lines driven by external arbiter logic (not shown).
7
Specifications ispGDX240VA
Absolute Maximum Ratings 1,2
Supply Voltage Vcc ................................. -0.5 to +5.4V
Input Voltage Applied ............................... -0.5 to +5.6V
Off-State Output Voltage Applied ............ -0.5 to +5.6V
Storage Temperature ................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (TJ) with Power Applied ... 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
2. Compliance with the Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM is a requirement.
DC Recommended Operating Conditions
SYMBOL
MIN.
MAX.
UNITS
Commercial
TA = 0°C to +70°C
3.00
3.60
V
Industrial
TA = -40°C to +85°C
3.00
3.60
V
2.3
3.60
PARAMETER
VCC
Supply Voltage
VCCIO
I/O Reference Voltage
V
Table 2-0005/gdxva
Capacitance (TA=25oC, f=1.0 MHz)
SYMBOL
C1
C2
TYPICAL
UNITS
I/O Capacitance
PARAMETER
PACKAGE TYPE
TQFP
7
pf
VCC = 3.3V, VI/O = 2.0V
TEST CONDITIONS
Dedicated Clock Capacitance
TQFP
8
pf
VCC = 3.3V, VY = 2.0V
Table 2-0006/gdxva
Erase/Reprogram Specifications
PARAMETER
Erase/Reprogram Cycles
8
MINIMUM
MAXIMUM
UNITS
10,000
—
Cycles
Specifications ispGDX240VA
Switching Test Conditions
Figure 8. Test Load
Input Pulse Levels
GND to VCCIO(MIN)
Input Rise and Fall Time
VCCIO
< 1.5ns 10% to 90%
Input Timing Reference Levels
VCCIO(MIN)/2
Output Timing Reference Levels
VCCIO(MIN)/2
Output Load
See Figure 8
R1
Device
Output
3-state levels are measured 0.5V from steady-state active level.
Test
Point
CL*
R2
Output Load Conditions (See Figure 8)
3.3V
R1
R2
R1
153Ω
134Ω
156Ω
144Ω 35pF
Active High
∞
134Ω
∞
144Ω 35pF
Active Low
153Ω
∞
156Ω
∞
35pF
Active High to Z
at VOH -0.5V
∞
134Ω
∞
144Ω
5pF
Active Low to Z
at VOL+0.5V
153Ω
∞
156Ω
∞
5pF
∞
∞
∞
∞
35pF
TEST CONDITION
A
B
C
*CL includes Test Fixture and Probe Capacitance.
2.5V
D
Slow Slew
R2
0213D
CL
Table 2-0004A/gdxva
DC Electrical Characteristics for 3.3V Range
Over Recommended Operating Conditions
SYMBOL
PARAMETER
MIN.
TYP.
–
3.0
–
VCCIO
VIL
VIH
Input Low Voltage
VOH ≤ VOUT or VOUT ≤ VOL (MAX)
-0.3
Input High Voltage
VOH ≤ VOUT or VOUT ≤ VOL(MAX)
2.0
VOL
Output Low Voltage
VCC = VCC (MIN)
IOL = +100µA
VOH
I/O Reference Voltage
Output High Voltage
1
CONDITION
VCC = VCC (MIN)
MAX. UNITS
3.6
V
–
0.8
V
–
5.25
V
–
–
0.2
V
IOL = +24mA
–
–
0.55
V
IOH = -100µA
2.8
–
–
V
IOH = -12mA
2.4
–
–
V
Table 2-0007/gdxva
1. Typical values are at VCC = 3.3V and TA = 25°C.
9
Specifications ispGDX240VA
DC Electrical Characteristics for 2.5V Range
Over Recommended Operating Conditions
SYMBOL
VCCIO
VIL
VIH
I/O Reference Voltage
VOL
Output Low Voltage
VOH
CONDITION
PARAMETER
Input Low Voltage
Input High Voltage
–
TYP.
MAX. UNITS
2.3
–
2.7
V
VOH(MIN) ≤ VOUT or VOUT ≤ VOL(MAX)
-0.3
–
0.7
V
VOH(MIN) ≤ VOUT or VOUT ≤ VOL(MAX)
1.7
–
5.25
V
–
–
0.2
V
VCCIO=MIN, IOL = 100µA
VCCIO=MIN, IOL = 8mA
Output High Voltage
MIN.
–
–
0.6
V
VCCIO=MIN, IOH = -100µA
2.1
–
–
V
VCCIO=MIN, IOH = -8mA
1.8
–
–
V
2.5V/gdxva
DC Electrical Characteristics
Over Recommended Operating Conditions
SYMBOL
IIL
IIH
IPU
IBHLS
IBHHS
IBHLO
IBHHO
IBHT
IOS1
ICCQ4
CONDITION
PARAMETER
MIN.
TYP.2
MAX.
UNITS
0V ≤ VIN ≤ VIL (MAX)
–
–
-10
µA
(VCCIO-0.2) ≤ VIN ≤ VCCIO
–
–
10
µA
VCCIO ≤ VIN ≤ 5.25V
–
–
50
µA
–
–
-200
µA
Bus Hold Low Sustaining Current
0V ≤ VIN ≤ VIL (MAX)
VIN = VIL (MAX)
40
–
–
µA
-40
–
–
µA
–
–
550
µA
Input or I/O Low Leakage Current
Input or I/O High Leakage Current
I/O Active Pullup Current
Bus Hold High Sustaining Current
VIN = VIH (MIN)
Bus Hold Low Overdrive Current
0V ≤ VIN ≤ VCCIO
Bus Hold High Overdrive Current
Bus Hold Trip Points
0V ≤ VIN ≤ VCCIO
Output Short Circuit Current
VCC = 3.3V, VOUT = 0.5V, TA = 25°C
Quiescent Power Supply Current
VIL = 0.5V, VIH = VCC
–
20
–
mA
One input toggling at 50% duty cycle,
outputs open.
–
See
Note 3
–
mA/
MHz
–
–
135
mA
ICC
Dynamic Power Supply Current
per Input Switching
ICONT 5
Maximum Continuous I/O Pin Sink
Current Through Any GND Pin
–
–
–
-550
µA
VIL
–
VIH
V
–
–
-250
mA
DC Char_gdxva
1. One output at a time for a maximum of one second. VOUT = 0.5V was selected to avoid test problems by
tester ground degradation. Characterized, but not 100% tested.
2. Typical values are at VCC = 3.3V and TA = 25°C.
3. ICC / MHz = (0.0025 x I/O cell fanout) + 0.042.
e.g. An input driving four I/O cells at 40MHz results in a dynamic ICC of approximately ((0.0025 x 4) + 0.042) x 40 = 2.08mA.
4. For a typical application with 50% of I/O pins used as inputs, 50% used as outputs or bi-directionals.
5. This parameter limits the total current sinking of I/O pins surrounding the nearest GND pin.
10
Specifications ispGDX240VA
External Timing Parameters
Over Recommended Operating Conditions
TEST1
PARAMETER COND. #
tpd2
tsel2
fmax (Tog.)
fmax (Ext.)
tsu1
tsu2
tsu3
tsu4
tsuce1
tsuce2
tsuce3
th1
th2
th3
th4
thce1
thce2
thce3
tgco12
tgco22
tco12
tco22
ten2
tdis2
ttoeen2
ttoedis2
twh
twl
trst
trw
tsl
tsk
-4
DESCRIPTION
-10
-7
UNITS
MIN. MAX. MIN. MAX. MIN. MAX.
A
1 Data Prop. Delay from Any I/O Pin to Any I/O Pin (4:1 MUX)
–
4.5
–
7.0
–
10.0
ns
A
2 Data Prop. Delay from MUXsel Inputs to Any Output (4:1 MUX)
–
4.5
–
7.0
–
10.0
ns
–
3 Clk. Frequency, Max. Toggle
200.0
–
100.0
–
71.0
–
MHz
–
4 Clk. Frequency with External Feedback (
153.8
–
80.0
–
56.0
–
MHz
–
5 Input Latch or Reg. Setup Time Before Yx
2.5
–
5.5
–
8.0
–
ns
–
6 Input Latch or Reg. Setup Time Before I/O Clk.
1.5
–
4.5
–
6.5
–
ns
–
7 Output Latch or Reg. Setup Time Before Yx
2.5
–
5.5
–
8.0
–
ns
–
8 Output Latch or Reg. Setup Time Before I/O Clk.
1.5
–
4.5
–
6.5
–
ns
–
9 Global Clock Enable Setup Time Before Yx
2.5
–
3.5
–
5.0
–
ns
–
10 Global Clock Enable Setup Time Before I/O Clock
1.5
–
2.5
–
3.5
–
ns
–
11 I/O Clock Enable Setup Time Before Yx
3.0
–
6.5
–
9.0
–
ns
–
12 Input Latch or Reg. Hold Time (Yx)
0.0
–
0.0
–
0.0
–
ns
–
13 Input Latch or Reg. Hold Time (I/O Clock)
1.0
–
2.5
–
3.5
–
ns
–
14 Output Latch or Reg. Hold Time (Yx)
0.0
–
0.0
–
0.0
–
ns
–
15 Output Latch or Reg. Hold Time (I/O Clock)
1.0
–
2.5
–
3.5
–
ns
–
16 Global Clock Enable Hold Time (Yx)
0.0
–
0.0
–
0.0
–
ns
–
17 Global Clock Enable Hold Time (I/O Clock)
1.0
–
2.5
–
3.5
–
ns
–
18 I/O Clock Enable Hold Time (Yx)
0.0
–
0.0
–
0.0
–
ns
A
19 Output Latch or Reg. Clk (from Yx) to Output Delay
–
4.0
–
7.0
–
10.0
ns
A
20 Input Latch or Register Clk (from Yx) to Output Delay
–
7.0
–
11.0
–
15.5
ns
A
21 Output Latch or Reg. Clk. (from I/O pin) to Output Delay
–
5.0
–
9.0
–
12.5
ns
A
22 Input Latch or Reg. Clk. (from I/O pin) to Output Delay
–
8.0
–
13.0
–
18.0
ns
1
tsu3+tgco1
)
B
23 Input to Output Enable
–
5.0
–
8.5
–
12.0
ns
C
24 Input to Output Disable
–
5.0
–
8.5
–
12.0
ns
B
25 Test OE Output Enable
–
6.5
–
8.5
–
12.0
ns
C
26 Test OE Output Disable
–
6.5
–
8.5
–
12.0
ns
–
27 Clk. Pulse Duration, High
2.5
–
5.0
–
7.0
–
ns
–
28 Clk. Pulse Duration, Low
2.5
–
5.0
–
7.0
–
ns
–
29 Reg. Reset Delay from RESET Low
–
12.0
–
18.0
–
25.0
ns
–
30 Reset Pulse Width
7.5
–
14.0
–
18.0
–
ns
D
31 Output Delay Adder for Output Timings Using Slow Slew Rate
–
4.0
–
4.0
–
4.0
ns
A
32 Output Skew (tgco1 Across Chip)
–
0.5
–
0.5
–
ns
1.0
Timing ver. 2.8
1. All timings measured with one output switching, fast output slew rate setting, except tsl.
2. The delay parameters are measured with Vcc as I/O voltage reference. An additional 0.5ns delay is incurred when Vccio is
used as I/O voltage reference.
11
Specifications ispGDX240VA
External Timing Parameters (Continued)
ispGDX240VA timings are specified with a GRP load
(fanout) of four I/O cells. The figure below shows the ∆
GRP Delay with increased GRP loads. These deltas
apply to any signal path traversing the GRP (MUXA-D,
OE, CLK/CLKEN, MUXsel0-1). Global Clock signals
which do not use the GRP have no fanout delay adder.
ispGDX240VA Maximum ∆ GRP Delay vs. I/O Cell Fanout
∆ GRP Delay (ns)
10
8
6
4
2
0 4 10
20
30
40
50
I/O Cell Fanout
12
60
70
Specifications ispGDX240VA
Internal Timing Parameters1
Over Recommended Operating Conditions
-4
PARAMETER
Inputs
tio
GRP
tgrp
MUX
tmuxd
tmuxexp
tmuxs
tmuxsio
tmuxsg
tmuxselexp
Register
tiolat
tiosu
tioh
tioco
tior
tcesu
tceh
Data Path
tfdbk
tiobp
tioob
tmuxcg
tmuxcio
tiodg
tiodio
Outputs
tob
tobs
toeen
toedis
tgoe
ttoe
Clocks
tioclk
tgclk
tgclkeng
tgclkenio
tioclkeng
Global Reset
tgr
DESCRIPTION1
#
-7
-10
MIN. MAX. MIN. MAX. MIN. MAX. UNITS
32
Input Buffer Delay
—
0.8
—
1.4
—
2.1
ns
33
GRP Delay
—
1.1
—
1.1
—
1.1
ns
34
35
36
37
38
I/O Cell MUX A/B/C/D Data Delay
I/O Cell MUX A/B/C/D Expander Delay
I/O Cell Data Select
I/O Cell Data Select (I/O Clock)
I/O Cell Data Select (Yx Clock)
—
—
—
—
—
1.3
1.8
1.3
2.3
2.3
—
—
—
—
—
2.0
2.5
2.0
4.5
2.5
—
—
—
—
—
2.8
3.3
2.8
6.0
5.0
ns
ns
ns
ns
ns
39
I/O Cell MUX Data Select Expander Delay
—
1.8
—
2.5
—
3.3
ns
40
41
42
43
44
45
46
I/O Latch Delay
I/O Register Setup Time Before Clock
I/O Register Hold Time After Clock
I/O Register Clock to Output Delay
I/O Reset to Output Delay
I/O Clock Enable Setup Time Before Clock
I/O Clock Enable Hold Time After Clock
—
—
—
—
—
—
—
1.0
0.3
2.2
0.5
1.5
2.0
0.0
—
—
—
—
—
—
—
1.0
3.2
2.3
0.5
1.5
2.5
1.0
—
—
—
—
—
—
—
1.0
5.0
2.5
0.4
1.5
2.0
3.0
ns
ns
ns
ns
ns
ns
ns
47
48
49
50
51
52
53
I/O Register Feedback Delay
I/O Register Bypass Delay
I/O Register Output Buffer Delay
I/O Register A/B/C/D Data Input MUX Delay (Yx Clock)
I/O Register A/B/C/D Data Input MUX Delay (I/O Clock)
I/O Register I/O MUX Delay (Yx Clock)
I/O Register I/O MUX Delay (I/O Clock)
—
—
—
—
—
—
—
0.8
0.0
0.2
2.3
2.3
4.2
4.2
—
—
—
—
—
—
—
1.2
0.3
0.6
2.5
4.5
5.0
7.0
—
—
—
—
—
—
—
1.5
0.8
0.7
5.0
6.0
8.7
9.7
ns
ns
ns
ns
ns
ns
ns
54
55
56
57
58
59
Output Buffer Delay
Output Buffer Delay (Slow Slew Option)
I/O Cell OE to Output Enable
I/O Cell OE to Output Disable
GRP Output Enable and Disable Delay
Test OE Enable and Disable Delay
—
—
—
—
—
—
1.3
5.3
3.1
3.1
0.0
3.4
—
—
—
—
—
—
2.2
6.2
6.0
6.0
0.0
2.5
—
—
—
—
—
—
3.2
7.2
8.2
8.2
0.6
3.8
ns
ns
ns
ns
ns
ns
60
61
62
63
64
I/O Clock Delay
Global Clock Delay
Global Clock Enable (Yx Clock)
Global Clock Enable (I/O Clock)
I/O Clock Enable (Yx Clock)
—
—
—
—
—
1.1
2.0
2.0
2.0
1.1
—
—
—
—
—
3.2
2.7
3.7
5.7
4.2
—
—
—
—
—
5.0
5.7
8.7
9.7
8.0
ns
ns
ns
ns
ns
65
Global Reset to I/O Register Latch
—
9.0
—
13.7
—
19.6
ns
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to the Timing Model in this data sheet for further details.
13
Timing ver. 2.8
Specifications ispGDX240VA
Switching Waveforms
DATA
(I/O INPUT)
VALID INPUT
MUXSEL (I/O INPUT)
VALID INPUT
tsu
tsel
DATA (I/O INPUT)
VALID INPUT
th
t gco
CLK
tco
tpd
COMBINATORIAL
I/O OUTPUT
REGISTERED
I/O OUTPUT
1/fmax
(external fdbk)
Combinatorial Output
t suce
t ceh
OE (I/O INPUT)
CLKEN
tdis
ten
Registered Output
COMBINATORIAL
I/O OUTPUT
I/O Output Enable/Disable
RESET
trw
twh
trst
twl
REGISTERED
I/O OUTPUT
CLK
(I/O INPUT)
Clock Width
Reset
ispGDXVA Timing Model
tgoe #58
OE
MUX Expander Input
tmuxd #34
tmuxs #36
tmuxio #37
tmuxg #38
tmuxcg #50
tmuxcio #51
TOE
ttoe #59
A
B
C
D
tiobp #48
D
MUX0
GRP
MUX Expander Output
tmuxexp #35
tmuxselexp #39
Q
tioob #49
I/O Pin
CLKEN
MUX1
tob #54
tobs #55
toeen #56
toedis #57
CLK
tgrp #33
tiod #52, #53
tiolat #40
tiosu #41
tioh #42
tioco #43
tior #44
tcesu #45
tceh #46
tgr #65
RESET
tfdbk #47
tio #32
CLKEN
CLK
tioclkeg #64
tioclk #60
Y0,1,2,3
0902/gdx160v/va
tgclk #61
Y0,1,2,3, Enable
tgclkeng #62
tgclkenio #63
14
Specifications ispGDX240VA
are fed into the on-chip programming circuitry where a
state machine controls the programming.
ispLEVER Development System
The ispLEVER Development System supports ispGDX
design using a VHDL or Verilog language syntax. From
creation to in-system programming, the ispLEVER system is an easy-to-use, self-contained design tool.
On-chip programming can be accomplished using an
IEEE 1149.1 boundary scan protocol. The IEEE 1149.1compliant interface signals are Test Data In (TDI), Test
Data Out (TDO), Test Clock (TCK) and Test Mode Select
(TMS) control. The EPEN pin is also used to enable or
disable the JTAG port.
Features
• VHDL and Verilog Synthesis Support Available
The embedded controller port enable pin (EPEN) is used
to enable the JTAG tap controller and in that regard has
similar functionality to a TRST pin. When the pin is driven
high, the JTAG TAP controller is enabled. This is also true
when the pin is left unconnected, in which case the pin is
pulled high by the permanent internal pullup. This allows
ISP programming and BSCAN testing to take place as
specified by the Instruction Table.
• ispGDX Design Compiler
- Design Rule Checker
- I/O Connectivity Checker
- Automatic Compiler Function
• Industry Standard JEDEC File for Programming
• Min/Max Timing Report
• Interfaces To Popular Timing Simulators
• User Electronic Signature (UES) Support
When the pin is driven low, the JTAG TAP controller is
driven to a reset state asynchronously. It stays there
while the pin is held low. After pulling the pin high the
JTAG controller becomes active. The intent of this feature is to allow the JTAG interface to be directly controlled
by the data bus of an embedded controller (hence the
name Embedded Port Enable). The EPEN signal is used
as a “device select” to prevent spurious programming
and/or testing from occurring due to random bit patterns
on the data bus. Figure 5 illustrates the block diagram for
the ispJTAG™ interface.
• Detailed Log and Report Files For Easy Design
Debug
• On-line Help
• Windows® XP, Windows 2000, Windows 98 and
Windows NT® Compatible
• Solaris® and HP-UX Versions Available
In-System Programmability
All necessary programming of the ispGDXVA is done via
four TTL level logic interface signals. These four signals
Figure 5. ispJTAG Device Programming Interface
TDO
TDI
TMS
TCK
ispJTAG
Programming
Interface
EPEN
ispGDX
240VA
Device
ispLSI
Device
ispMACH
Device
15
ispGDX
240VA
Device
ispGDX
240VA
Device
Specifications ispGDX240VA
The ispGDXVA devices are identified by the 32-bit JTAG
IDCODE register. The device ID assignments are listed
in Table 3.
Boundary Scan
The ispGDXVA devices provide IEEE1149.1a test capability and ISP programming through a standard Boundary
Scan Test Access Port (TAP) interface.
The ispJTAG programming is accomplished by executing Lattice private instructions under the Boundary Scan
State Machine.
The boundary scan circuitry on the ispGDXVA Family
operates independently of the programmed pattern. This
allows customers using boundary scan test to have full
test capability with only a single BSDL file.
Contact Lattice Applications to obtain more detailed
programming information.
Table 2. I/O Shift Register Order
I/O SHIFT REGISTER ORDER
DEVICE
ispGDX240VA
TDI, TOE, Y2, Y3, RESET, Y1, Y0, I/O B30 .. B59, I/O C0 .. C59, I/O D0 .. D29, I/O B29 .. B0,
I/O A59.. A0, I/O D59 .. D30, TDO
I/O Shift Reg Order/ispGDX240
Table 3. ispGDX240VA Device ID Codes
DEVICE
ispGDX240VA
32-BIT BOUNDARY SCAN ID CODE
0001, 0000, 0011, 0101, 0100, 0000, 0100, 0011
ID Code/GDX240VA
Figure 7. Boundary Scan I/O Register Cell
SCANIN
(from
previous
cell)
M
U
X
Normal
Function
OE
D
Q
D
Q
TOE
EXTEST
M
U
X
Normal
Function
OE
D
Q
D
Q
Update DR
M
U
X
Shift DR
M
U
X
D
Q
SCANOUT (to next cell)
Clock DR
16
M
U
X
I/O Pin
Specifications ispGDX240VA
Figure 8. Boundary Scan State Machine
1
0
Test-Logic-Reset
0
1
Run-Test/Idle
Select-DR-Scan
0
1
Capture-DR
0
Shift-DR
0
1
Exit1-DR
1
0
Pause-DR
1
1
Select-IR-Scan
0
1
Capture-IR
0
Shift-IR
0
1
Exit1-IR
1
0
Pause-IR
1
0
1
0
0
Exit2-DR
1
Update-DR
1
0
0
Exit2-IR
1
Update-IR
1
0
TCK
t su
th
TMS or
TDI
t co
TDO
tsu = 0.1µs (min.)
th = 0.1µs (min.)
17
tco = 0.1µs (min.)
Specifications ispGDX240VA
Signal Descriptions
Signal Name
Description
I/O
Input/Output Pins – These are the general purpose bidirectional data pins. When used as outputs,
each may be independently latched, registered or tristated. They can also each assume one other
control function (OE, CLK/CLKEN, and MUXsel as described in the text).
TOE
Test Output Enable Pin – This pin tristates all I/O pins when a logic low is driven.
RESET
Active LOW Input Pin – Resets all I/O register outputs when LOW.
Yx/CLKENx
Input Pins –These can be either Global Clocks or Clock Enables.
EPEN
Input Pin – JTAG TAP Controller Enable Pin. When high, JTAG operation is enabled. When low,
JTAG TAP controller is driven to reset.
TDI
Input Pin – Serial data input during ISP programming or Boundary Scan mode.
TCK
Input Pin – Serial data clock during ISP programming or Boundary Scan mode.
TMS
Input Pin – Control input during ISP programming or Boundary Scan mode.
TDO
Output Pin – Serial data output during ISP programming or Boundary Scan mode.
GND
Ground (GND)
VCC
Vcc – Supply voltage (3.3V).
VCCIO
Input – This pin is used if optional 2.5V output is to be used. Every I/O can independently select either
3.3V or the optional voltage as its output level. If the optional output voltage is not required, this pin
must be connected to the VCC supply. Programmable pull-up resistors and bus-hold latches only draw
current from this supply.
NC1
No Connect.
1. NC pins are not to be connected to any active signals, VCC or GND.
Signal Locations: ispGDX240VA
Signal
388-Ball fpBGA
TOE
L22
RESET
L21
Y0/CLKEN0
M4
Y1/CLKEN1
L3
Y2/CLKEN2
M20
Y3/CLKEN3
M21
EPEN
A11
TDI
M1
TCK
L1
TMS
L2
TDO
AB12
GND
A1, A22, B2, B21, C3, C20, D4, D19, H9, H10, H11, H12, H13, H14, J8, J9, J10, J11, J12, J13, J14, J15, K8,
K9, K10, K11, K12, K13, K14, K15, L8, L9, L10, L11, L12, L13, L14, L15, M8, M9, M10, M11, M12, M13,
M14, M15, N8, N9, N10, N11, N12, N13, N14, N15, P8, P9, P10, P11, P12, P13, P14, P15, R9, R10, R11,
R12, R13, R14, W4, W19, Y3, Y20, AA2, AA21, AB1, AB22
VCC
D6, D9, D12, D14, D17, F4, F19, G7, G8, G15, G16, H7, H16, J4, J19, L4, M19, P4, P19, R7, R16, T7, T8,
T15, T16, U4, U19, W6, W9, W11, W14, W17
M22
VCCIO
NC1
G9, G10, G11, G12, G13, G14, H8, H15, J7, J16, K7, K16, L7, L16, M7. M16, N7, N16, P7, P16, R8,
R15, T9, T10, T11, T12, T13, T14
1. NC pins are not to be connected to any active signals, VCC or GND.
18
Specifications ispGDX240VA
388-Ball BGA I/O Locations (Sorted by I/O)
I/O #
VCC
I/O A0
I/O A1
I/O A2
I/O A3
I/O A4
I/O A5
I/O A6
GND
I/O A7
I/O A8
I/O A9
I/O A10
I/O A11
VCC
I/O A12
I/O A13
I/O A14
GND
I/O A15
I/O A16
I/O A17
I/O A18
I/O A19
I/O A20
I/O A21
GND
I/O A22
I/O A23
VCC
I/O A24
I/O A25
I/O A26
I/O A27
I/O A28
GND
I/O A29
I/O A30
I/O A31
I/O A32
I/O A33
I/O A34
I/O A35
VCC
I/O A36
I/O A37
GND
I/O A38
I/O A39
I/O A40
I/O A41
I/O A42
I/O A43
I/O A44
GND
I/O A45
I/O A46
I/O A47
VCC
I/O A48
Control
Signal
Ball
CLK/CLKEN
OE
MUXsel1
MUXsel2
CLK/CLKEN
OE
MUXsel1
A2
B1
C2
D3
C1
D2
D1
MUXsel2
CLK/CLKEN
OE
MUXsel1
MUXsel2
E3
E4
E2
E1
F3
CLK/CLKEN
OE
MUXsel1
F2
F1
G3
MUXsel2
CLK/CLKEN
OE
MUXsel1
MUXsel2
CLK/CLKEN
OE
G4
G2
G1
H3
H4
H2
H1
MUXsel1
MUXsel2
J3
J2
CLK/CLKEN
OE
MUXsel1
MUXsel2
CLK/CLKEN
J1
K3
K2
K4
K1
OE
MUXsel1
MUXsel2
CLK/CLKEN
OE
MUXsel1
MUXsel2
M2
M3
N1
N4
N2
N3
P1
CLK/CLKEN
OE
P2
P3
MUXsel1
MUXsel2
CLK/CLKEN
OE
MUXsel1
MUXsel2
CLK/CLKEN
R1
R2
R4
R3
T1
T2
T4
OE
MUXsel1
MUXsel2
T3
U1
U2
CLK/CLKEN
U3
I/O #
I/O A49
I/O A50
I/O A51
I/O A52
GND
I/O A53
I/O A54
I/O A55
I/O A56
I/O A57
I/O A58
I/O A59
GND
VCC
I/O B0
I/O B1
I/O B2
I/O B3
I/O B4
I/O B5
I/O B6
I/O B7
I/O B8
GND
I/O B9
I/O B10
I/O B11
VCC
I/O B12
I/O B13
I/O B14
I/O B15
I/O B16
GND
I/O B17
I/O B18
I/O B19
I/O B20
I/O B21
I/O B22
I/O B23
VCC
I/O B24
GND
I/O B25
I/O B26
I/O B27
I/O B28
I/O B29
I/O B30
I/O B31
I/O B32
I/O B33
I/O B34
GND
I/O B35
VCC
I/O B36
I/O B37
I/O B38
Control
Signal
Ball
OE
MUXsel1
MUXsel2
CLK/CLKEN
V1
V2
V4
V3
OE
MUXsel1
MUXsel2
CLK/CLKEN
OE
MUXsel1
MUXsel2
W1
W2
Y1
W3
Y2
AA1
AB2
CLK/CLKEN
OE
MUXsel1
MUXsel2
CLK/CLKEN
OE
MUXsel1
MUXsel2
CLK/CLKEN
AA3
W5
AB3
Y4
AB4
AA4
AA5
Y5
W7
OE
MUXsel1
MUXsel2
AB5
Y6
AA6
CLK/CLKEN
OE
MUXsel1
MUXsel2
CLK/CLKEN
AB6
Y7
W8
AA7
AB7
OE
MUXsel1
MUXsel2
CLK/CLKEN
OE
MUXsel1
MUXsel2
Y8
AA8
AB8
Y9
AA9
AB9
W10
CLK/CLKEN
Y10
OE
MUXsel1
MUXsel2
CLK/CLKEN
OE
MUXsel1
MUXsel2
CLK/CLKEN
OE
MUXsel1
AA10
AB10
W12
Y11
AA11
AB11
AA12
Y12
AB13
AA13
MUXsel2
Y13
CLK/CLKEN AB14
OE
AA14
MUXsel1
W13
19
I/O #
I/O B39
I/O B40
I/O B41
I/O B42
GND
I/O B43
I/O B44
I/O B45
I/O B46
I/O B47
VCC
I/O B48
I/O B49
I/O B50
GND
I/O B51
I/O B52
I/O B53
I/O B54
I/O B55
I/O B56
I/O B57
I/O B58
I/O B59
GND
VCC
I/O C0
I/O C1
I/O C2
I/O C3
I/O C4
I/O C5
I/O C6
GND
I/O C7
I/O C8
I/O C9
I/O C10
I/O C11
VCC
I/O C12
I/O C13
I/O C14
GND
I/O C15
I/O C16
I/O C17
I/O C18
I/O C19
I/O C20
I/O C21
GND
I/O C22
I/O C23
VCC
I/O C24
I/O C25
I/O C26
I/O C27
I/O C28
Control
Signal
MUXsel2
CLK/CLKEN
OE
MUXsel1
Ball
Y14
AB15
AA15
Y15
MUXsel2
AB16
CLK/CLKEN AA16
OE
W15
MUXsel1
Y16
MUXsel2
AB17
CLK/CLKEN AA17
OE
Y17
MUXsel1
AB18
MUXsel2
CLK/CLKEN
OE
MUXsel1
MUXsel2
CLK/CLKEN
OE
MUXsel1
MUXsel2
W16
Y18
AA18
AB19
W18
AA20
AB20
Y19
AA19
CLK/CLKEN AB21
OE
AA22
MUXsel1
Y21
MUXsel2
W20
CLK/CLKEN Y22
OE
W21
MUXsel1
W22
MUXsel2
CLK/CLKEN
OE
MUXsel1
MUXsel2
V20
V19
V21
V22
U20
CLK/CLKEN
OE
MUXsel1
U21
U22
T20
MUXsel2
CLK/CLKEN
OE
MUXsel1
MUXsel2
CLK/CLKEN
OE
T19
T21
T22
R20
R19
R21
R22
MUXsel1
MUXsel2
P20
P21
CLK/CLKEN
OE
MUXsel1
MUXsel2
CLK/CLKEN
P22
N20
N21
N19
L19
I/O #
I/O C29
GND
I/O C30
I/O C31
I/O C32
I/O C33
I/O C34
I/O C35
VCC
I/O C36
I/O C37
GND
I/O C38
I/O C39
I/O C40
I/O C41
I/O C42
I/O C43
I/O C44
GND
I/O C45
I/O C46
I/O C47
VCC
I/O C48
I/O C49
I/O C50
I/O C51
I/O C52
GND
I/O C53
I/O C54
I/O C55
I/O C56
I/O C57
I/O C58
I/O C59
GND
VCC
I/O D0
I/O D1
I/O D2
I/O D3
I/O D4
I/O D5
I/O D6
I/O D7
I/O D8
GND
I/O D9
I/O D10
I/O D11
VCC
I/O D12
I/O D13
I/O D14
I/O D15
I/O D16
GND
I/O D17
Control
Signal
Ball
OE
N22
MUXsel1
MUXsel2
CLK/CLKEN
OE
MUXsel1
MUXsel2
L20
K22
K19
K21
K20
J22
CLK/CLKEN
OE
J21
J20
MUXsel1
MUXsel2
CLK/CLKEN
OE
MUXsel1
MUXsel2
CLK/CLKEN
H22
H21
H19
H20
G22
G21
G19
OE
MUXsel1
MUXsel2
G20
F22
F21
CLK/CLKEN
OE
MUXsel1
MUXsel2
CLK/CLKEN
F20
E22
E21
E19
E20
OE
MUXsel1
MUXsel2
CLK/CLKEN
OE
MUXsel1
MUXsel2
D22
D21
C22
D20
C21
B22
A21
CLK/CLKEN
OE
MUXsel1
MUXsel2
CLK/CLKEN
OE
MUXsel1
MUXsel2
CLK/CLKEN
B20
D18
A20
C19
A19
B19
B18
C18
D16
OE
MUXsel1
MUXsel2
A18
C17
B17
CLK/CLKEN
OE
MUXsel1
MUXsel2
CLK/CLKEN
A17
C16
D15
B16
A16
OE
C15
Specifications ispGDX240VA
388-Ball BGA I/O Locations (Sorted by I/O), continued
I/O #
I/O D18
I/O D19
I/O D20
I/O D21
I/O D22
I/O D23
VCC
I/O D24
GND
I/O D25
I/O D26
I/O D27
I/O D28
Control
Signal
Ball
I/O #
MUXsel1
MUXsel2
CLK/CLKEN
OE
MUXsel1
MUXsel2
B15
A15
C14
B14
A14
D13
CLK/CLKEN
C13
OE
MUXsel1
MUXsel2
CLK/CLKEN
B13
A13
D11
C12
I/O D29
I/O D30
I/O D31
I/O D32
I/O D33
I/O D34
GND
I/O D35
VCC
I/O D36
I/O D37
I/O D38
I/O D39
Control
Signal
Ball
I/O #
OE
MUXsel1
MUXsel2
CLK/CLKEN
OE
MUXsel1
B12
A12
B11
C11
A10
B10
MUXsel2
C10
CLK/CLKEN
OE
MUXsel1
MUXsel2
A9
B9
D10
C9
I/O D40
I/O D41
I/O D42
GND
I/O D43
I/O D44
I/O D45
I/O D46
I/O D47
VCC
I/O D48
I/O D49
I/O D50
20
Control
Signal
Ball
CLK/CLKEN
OE
MUXsel1
A8
B8
C8
MUXsel2
CLK/CLKEN
OE
MUXsel1
MUXsel2
A7
B7
D8
C7
A6
CLK/CLKEN
OE
MUXsel1
B6
C6
A5
I/O #
GND
I/O D51
I/O D52
I/O D53
I/O D54
I/O D55
I/O D56
I/O D57
I/O D58
I/O D59
GND
Control
Signal
MUXsel2
CLK/CLKEN
OE
MUXsel1
MUXsel2
CLK/CLKEN
OE
MUXsel1
MUXsel2
Ball
D7
C5
B5
B4
A4
C4
A3
D5
B3
Specifications ispGDX240VA
388-Ball BGA I/O Locations (Sorted by Ball)
I/O #
I/O A0
I/O D57
I/O D55
I/O D50
I/O D47
I/O D43
I/O D40
I/O D36
I/O D33
I/O D30
I/O D26
I/O D22
I/O D19
I/O D16
I/O D12
I/O D9
I/O D4
I/O D2
I/O C59
I/O A1
I/O D59
I/O D54
I/O D53
I/O D48
I/O D44
I/O D41
I/O D37
I/O D34
I/O D31
I/O D29
I/O D25
I/O D21
I/O D18
I/O D15
I/O D11
I/O D6
I/O D5
I/O D0
I/O C58
I/O A4
I/O A2
I/O D56
I/O D52
I/O D49
I/O D46
I/O D42
I/O D39
I/O D35
I/O D32
I/O D28
I/O D24
I/O D20
I/O D17
I/O D13
I/O D10
I/O D7
I/O D3
I/O C57
I/O C55
I/O A6
Control
Signal
Ball
CLK/CLKEN
OE
MUXsel2
MUXsel1
MUXsel2
MUXsel2
CLK/CLKEN
CLK/CLKEN
OE
MUXsel1
MUXsel1
MUXsel1
MUXsel2
CLK/CLKEN
CLK/CLKEN
OE
CLK/CLKEN
MUXsel1
MUXsel2
OE
MUXsel2
MUXsel1
OE
CLK/CLKEN
CLK/CLKEN
OE
OE
MUXsel1
MUXsel2
OE
OE
OE
MUXsel1
MUXsel2
MUXsel2
MUXsel1
OE
CLK/CLKEN
MUXsel1
CLK/CLKEN
MUXsel1
CLK/CLKEN
CLK/CLKEN
OE
MUXsel1
MUXsel1
MUXsel2
MUXsel2
CLK/CLKEN
CLK/CLKEN
CLK/CLKEN
CLK/CLKEN
OE
OE
MUXsel1
MUXsel2
MUXsel2
OE
MUXsel2
MUXsel1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
B1
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B22
C1
C2
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C21
C22
D1
Control
Signal
Ball
OE
MUXsel2
MUXsel1
MUXsel2
OE
MUXsel1
MUXsel2
MUXsel2
MUXsel1
CLK/CLKEN
OE
CLK/CLKEN
MUXsel1
OE
MUXsel1
OE
MUXsel2
CLK/CLKEN
MUXsel2
CLK/CLKEN
MUXsel1
OE
OE
CLK/CLKEN
MUXsel2
CLK/CLKEN
MUXsel2
MUXsel1
OE
CLK/CLKEN
MUXsel1
MUXsel2
CLK/CLKEN
OE
MUXsel2
MUXsel1
OE
CLK/CLKEN
MUXsel1
MUXsel2
CLK/CLKEN
OE
MUXsel2
MUXsel1
CLK/CLKEN
MUXsel2
MUXsel1
OE
CLK/CLKEN
MUXsel2
CLK/CLKEN
MUXsel1
OE
MUXsel2
CLK/CLKEN
MUXsel1
OE
MUXsel2
CLK/CLKEN
MUXsel1
D2
D3
D5
D7
D8
D10
D11
D13
D15
D16
D18
D20
D21
D22
E1
E2
E3
E4
E19
E20
E21
E22
F1
F2
F3
F20
F21
F22
G1
G2
G3
G4
G19
G20
G21
G22
H1
H2
H3
H4
H19
H20
H21
H22
J1
J2
J3
J20
J21
J22
K1
K2
K3
K4
K19
K20
K21
K22
L19
L20
I/O #
I/O A5
I/O A3
I/O D58
I/O D51
I/O D45
I/O D38
I/O D27
I/O D23
I/O D14
I/O D8
I/O D1
I/O C56
I/O C54
I/O C53
I/O A10
I/O A9
I/O A7
I/O A8
I/O C51
I/O C52
I/O C50
I/O C49
I/O A13
I/O A12
I/O A11
I/O C48
I/O C47
I/O C46
I/O A17
I/O A16
I/O A14
I/O A15
I/O C44
I/O C45
I/O C43
I/O C42
I/O A21
I/O A20
I/O A18
I/O A19
I/O C40
I/O C41
I/O C39
I/O C38
I/O A24
I/O A23
I/O A22
I/O C37
I/O C36
I/O C35
I/O A28
I/O A26
I/O A25
I/O A27
I/O C32
I/O C34
I/O C33
I/O C31
I/O C28
I/O C30
I/O #
I/O A29
I/O A30
I/O A31
I/O A33
I/O A34
I/O A32
I/O C27
I/O C25
I/O C26
I/O C29
I/O A35
I/O A36
I/O A37
I/O C22
I/O C23
I/O C24
I/O A38
I/O A39
I/O A41
I/O A40
I/O C19
I/O C18
I/O C20
I/O C21
I/O A42
I/O A43
I/O A45
I/O A44
I/O C15
I/O C14
I/O C16
I/O C17
I/O A46
I/O A47
I/O A48
I/O C11
I/O C12
I/O C13
I/O A49
I/O A50
I/O A52
I/O A51
I/O C8
I/O C7
I/O C9
I/O C10
I/O A53
I/O A54
I/O A56
I/O B1
I/O B8
I/O B14
I/O B23
I/O B27
I/O B38
I/O B45
I/O B51
I/O B55
I/O C3
I/O C5
NOTE: VCC and GND Pads Shown for Reference
21
Control
Signal
Ball
I/O #
Control
Signal
Ball
OE
MUXsel1
MUXsel2
OE
MUXsel1
CLK/CLKEN
MUXsel2
OE
MUXsel1
OE
MUXsel2
CLK/CLKEN
OE
MUXsel1
MUXsel2
CLK/CLKEN
MUXsel1
MUXsel2
OE
CLK/CLKEN
MUXsel2
MUXsel1
CLK/CLKEN
OE
MUXsel1
MUXsel2
OE
CLK/CLKEN
MUXsel2
MUXsel1
CLK/CLKEN
OE
MUXsel1
MUXsel2
CLK/CLKEN
MUXsel2
CLK/CLKEN
OE
OE
MUXsel1
CLK/CLKEN
MUXsel2
CLK/CLKEN
MUXsel2
OE
MUXsel1
OE
MUXsel1
CLK/CLKEN
OE
CLK/CLKEN
MUXsel1
MUXsel2
MUXsel2
MUXsel1
OE
MUXsel2
MUXsel2
MUXsel2
OE
M2
M3
N1
N2
N3
N4
N19
N20
N21
N22
P1
P2
P3
P20
P21
P22
R1
R2
R3
R4
R19
R20
R21
R22
T1
T2
T3
T4
T19
T20
T21
T22
U1
U2
U3
U20
U21
U22
V1
V2
V3
V4
V19
V20
V21
V22
W1
W2
W3
W5
W7
W8
W10
W12
W13
W15
W16
W18
W20
W21
I/O C6
I/O A55
I/O A57
I/O B3
I/O B7
I/O B10
I/O B13
I/O B17
I/O B20
I/O B24
I/O B28
I/O B32
I/O B35
I/O B39
I/O B42
I/O B46
I/O B49
I/O B52
I/O B58
I/O C2
I/O C4
I/O A58
I/O B0
I/O B5
I/O B6
I/O B11
I/O B15
I/O B18
I/O B21
I/O B25
I/O B29
I/O B31
I/O B34
I/O B37
I/O B41
I/O B44
I/O B48
I/O B53
I/O B59
I/O B56
I/O C1
I/O A59
I/O B2
I/O B4
I/O B9
I/O B12
I/O B16
I/O B19
I/O B22
I/O B26
I/O B30
I/O B33
I/O B36
I/O B40
I/O B43
I/O B47
I/O B50
I/O B54
I/O B57
I/O C0
MUXsel1
MUXsel2
OE
MUXsel2
MUXsel2
MUXsel1
OE
OE
CLK/CLKEN
CLK/CLKEN
CLK/CLKEN
CLK/CLKEN
MUXsel2
MUXsel2
MUXsel1
MUXsel1
OE
CLK/CLKEN
MUXsel1
MUXsel1
CLK/CLKEN
MUXsel1
CLK/CLKEN
OE
MUXsel1
MUXsel2
MUXsel2
MUXsel1
OE
OE
OE
MUXsel2
MUXsel1
OE
OE
CLK/CLKEN
CLK/CLKEN
OE
MUXsel2
CLK/CLKEN
OE
MUXsel2
MUXsel1
CLK/CLKEN
OE
CLK/CLKEN
CLK/CLKEN
MUXsel2
MUXsel1
MUXsel1
MUXsel1
OE
CLK/CLKEN
CLK/CLKEN
MUXsel2
MUXsel2
MUXsel1
MUXsel1
OE
CLK/CLKEN
W22
Y1
Y2
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y21
Y22
AA1
AA3
AA4
AA5
AA6
AA7
AA8
AA9
AA10
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA22
AB2
AB3
AB4
AB5
AB6
AB7
AB8
AB9
AB10
AB11
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
Specifications ispGDX240VA
Signal Configuration: ispGDX240VA
ispGDX240VA 388-Ball fpBGA (1.0mm Ball Pitch / 23.0mm x 23.0mm Body Size)
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A
GND
I/O
C59
I/O
D2
I/O
D4
I/O
D9
I/O
D12
I/O
D16
I/O
D19
I/O
D22
I/O
D26
I/O
D30
EPEN
I/O
D33
I/O
D36
I/O
D40
I/O
D43
I/O
D47
I/O
D50
I/O
D55
I/O
D57
I/O
A0
GND
A
B
I/O
C58
GND
I/O
D0
I/O
D5
I/O
D6
I/O
D11
I/O
D15
I/O
D18
I/O
D21
I/O
D25
I/O
D29
I/O
D31
I/O
D34
I/O
D37
I/O
D41
I/O
D44
I/O
D48
I/O
D53
I/O
D54
I/O
D59
GND
I/O
A1
B
C
I/O
C55
I/O
C57
GND
I/O
D3
I/O
D7
I/O
D10
I/O
D13
I/O
D17
I/O
D20
I/O
D24
I/O
D28
I/O
D32
I/O
D35
I/O
D39
I/O
D42
I/O
D46
I/O
D49
I/O
D52
I/O
D56
GND
I/O
A2
I/O
A4
C
D
I/O
C53
I/O
C54
I/O
C56
GND
I/O
D8
I/O
D14
VCC
I/O
D23
VCC
I/O
D27
I/O
D38
VCC
I/O
D45
I/O
VCC
D51
I/O
D58
GND
I/O
A3
I/O
A5
I/O
A6
D
E
I/O
C49
I/O
C50
I/O
C52
I/O
C51
I/O
A8
I/O
A7
I/O
A9
I/O
A10
E
F
I/O
C46
I/O
C47
I/O
C48
VCC
VCC
I/O
A11
I/O
A12
I/O
A13
F
G
I/O
C42
I/O
C43
I/O
C45
I/O
C44
VCC VCC
NC1
NC1
NC1
NC1
NC1
NC1
VCC
VCC
I/O
A15
I/O
A14
I/O
A16
I/O
A17
G
H
I/O
C38
I/O
C39
I/O
C41
I/O
C40
VCC
NC1
GND
GND
GND GND
GND
GND
NC1
VCC
I/O
A19
I/O
A18
I/O
A20
I/O
A21
H
J
I/O
C35
I/O
C36
I/O
C37
VCC
NC1
GND GND
GND
GND GND
GND
GND
GND
NC1
VCC
I/O
A22
I/O
A23
I/O
A24
J
K
I/O
C31
I/O
C33
I/O
C34
I/O
C32
NC1
GND GND
GND
GND GND
GND
GND
GND
NC1
I/O
A27
I/O
A25
I/O
A26
I/O
A28
K
L
TOE RESET
I/O
C30
I/O
C28
NC1
GND GND
GND
GND GND
GND
GND
GND
NC1
VCC
Y1
TMS
TCK
L
Y3
Y2
VCC
NC1
GND GND
GND
GND GND
GND
GND
GND
NC1
Y0
I/O
A30
I/O
A29
TDI
M
M VCCIO
I/O
VCC
D1
N
I/O
C29
I/O
C26
I/O
C25
I/O
C27
NC1
GND GND
GND
GND GND
GND
GND
GND
NC1
I/O
A32
I/O
A34
I/O
A33
I/O
A31
N
P
I/O
C24
I/O
C23
I/O
C22
VCC
NC1
GND GND
GND
GND GND
GND
GND
GND
NC1
VCC
I/O
A37
I/O
A36
I/O
A35
P
R
I/O
C21
I/O
C20
I/O
C18
I/O
C19
VCC
NC1
GND
GND
GND GND
GND
GND
NC1
VCC
I/O
A40
I/O
A41
I/O
A39
I/O
A38
R
T
I/O
C17
I/O
C16
I/O
C14
I/O
C15
VCC VCC
NC1
NC1
NC1
NC1
NC1
VCC
VCC
I/O
A44
I/O
A45
I/O
A43
I/O
A42
T
U
I/O
C13
I/O
C12
I/O
C11
VCC
ispGDX240VA
VCC
I/O
A48
I/O
A47
I/O
A46
U
V
I/O
C10
I/O
C9
I/O
C7
I/O
C8
Bottom View
I/O
A51
I/O
A52
I/O
A50
I/O
A49
V
W
I/O
C6
I/O
C5
I/O
C3
GND
I/O
VCC
B55
I/O
B51
I/O
B45
VCC
I/O
B38
I/O
B27
VCC
I/O
B23
VCC
I/O
B14
I/O
B8
I/O
B1
GND
I/O
A56
I/O
A54
I/O
A53
W
Y
I/O
C4
I/O
C2
GND
I/O
B58
I/O
B52
I/O
B49
I/O
B46
I/O
B42
I/O
B39
I/O
B35
I/O
B32
I/O
B28
I/O
B24
I/O
B20
I/O
B17
I/O
B13
I/O
B10
I/O
B7
I/O
B3
GND
I/O
A57
I/O
A55
Y
AA
I/O
C1
GND
I/O
B56
I/O
B59
I/O
B53
I/O
B48
I/O
B44
I/O
B41
I/O
B37
I/O
B34
I/O
B31
I/O
B29
I/O
B25
I/O
B21
I/O
B18
I/O
B15
I/O
B11
I/O
B6
I/O
B5
I/O
B0
GND
I/O
A58
AA
I/O
C0
I/O
B57
I/O
B54
I/O
B50
I/O
B47
I/O
B43
I/O
B40
I/O
B36
I/O TDO
B33
I/O
B30
I/O
B26
I/O
B22
I/O
B19
I/O
B16
I/O
B12
I/O
B9
I/O
B4
I/O
B2
I/O
A59
GND AB
21
20
19
18
17
16
15
14
13
11
10
9
8
7
6
5
4
3
2
AB GND
22
NC1
12
1. NCs are not to be connected to any active signals, VCC or GND.
Note: Ball A1 indicator dot on top side of package.
22
VCC
1
Specifications ispGDX240VA
Part Number Description
ispGDX 240VA
X XXXXX X
Device Family
Grade
Blank = Commercial
I = Industrial
Device Number
Package
B388 = 388-Ball fpBGA
BN388 = Lead-Free 388-Ball fpBGA
Speed
4 = 4.5ns Tpd
7 = 7.0ns Tpd
10 = 10.0ns Tpd
0212/gdx240va
Ordering Information
Conventional Packaging
COMMERCIAL
FAMILY
ispGDXVA
tpd (ns)
ORDERING NUMBER
PACKAGE
4.5
ispGDX240VA-4B388
388-Ball fpBGA
7
ispGDX240VA-7B388
388-Ball fpBGA
Table 2-0041A/gdx240va
INDUSTRIAL
FAMILY
ispGDXVA
tpd (ns)
7
ORDERING NUMBER
ispGDX240VA-7B388I
PACKAGE
388-Ball fpBGA
10
ispGDX240VA-10B388I
388-Ball fpBGA
Note: The ispGDX240VA devices are dual-marked with both Commercial and Industrial grades.
The Commercial speed grade is faster, e.g. ispGDX240VA-4B388-7I.
Table 2-0041/gdx240va
Lead-Free Packaging
COMMERCIAL
FAMILY
ispGDXVA
tpd (ns)
ORDERING NUMBER
PACKAGE
4.5
ispGDX240VA-4BN388
Lead-Free 388-Ball fpBGA
7
ispGDX240VA-7BN388
Lead-Free 388-Ball fpBGA
INDUSTRIAL
FAMILY
ispGDXVA
tpd (ns)
7
ORDERING NUMBER
ispGDX240VA-7BN388I
PACKAGE
Lead-Free 388-Ball fpBGA
10
ispGDX240VA-10BN388I
Lead-Free 388-Ball fpBGA
Note: The ispGDX240VA devices are dual-marked with both Commercial and Industrial grades.
The Commercial speed grade is faster, e.g. ispGDX240VA-4B388-7I.
23
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