LeadFree
Package
Options
Available!
Features
®
ispGDX 80VA
In-System Programmable
3.3V Generic Digital Crosspoint
Functional Block Diagram
ISP
Control
I/O Pins A
I/O Pins D
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— 3.3V Core Power Supply
— 3.0ns Input-to-Output/3.0ns Clock-to-Output Delay
— 250MHz Maximum Clock Frequency
— TTL/3.3V/2.5V Compatible Input Thresholds and
Output Levels (Individually Programmable)
— Low-Power: 16.5mA Quiescent Icc
— 24mA IOL Drive with Programmable Slew Rate
Control Option
— PCI Compatible Drive Capability
— Schmitt Trigger Inputs for Noise Immunity
— Electrically Erasable and Reprogrammable
— Non-Volatile E2CMOS Technology
I/O
Cells
Boundary
Scan
Control
Global Routing
Pool
(GRP)
I/O
Cells
I/O Pins C
• IN-SYSTEM PROGRAMMABLE GENERIC DIGITAL
CROSSPOINT FAMILY
— Advanced Architecture Addresses Programmable
PCB Interconnect, Bus Interface Integration and
Jumper/Switch Replacement
— “Any Input to Any Output” Routing
— Fixed HIGH or LOW Output Option for Jumper/DIP
Switch Emulation
— Space-Saving PQFP and BGA Packaging
— Dedicated IEEE 1149.1-Compliant Boundary Scan
Test
I/O Pins B
Description
• ispGDXV OFFERS THE FOLLOWING ADVANTAGES
— 3.3V In-System Programmable Using Boundary Scan
Test Access Port (TAP)
— Change Interconnects in Seconds
• FLEXIBLE ARCHITECTURE
— Combinatorial/Latched/Registered Inputs or Outputs
— Individual I/O Tri-state Control with Polarity Control
— Dedicated Clock/Clock Enable Input Pins (two) or
Programmable Clocks/Clock Enables from I/O Pins (20)
— Single Level 4:1 Dynamic Path Selection (Tpd = 3.0ns)
— Programmable Wide-MUX Cascade Feature
Supports up to 16:1 MUX
— Programmable Pull-ups, Bus Hold Latch and Open
Drain on I/O Pins
— Outputs Tri-state During Power-up (“Live Insertion”
Friendly)
• LEAD-FREE PACKAGE OPTIONS
The ispGDXVA architecture provides a family of fast,
flexible programmable devices to address a variety of
system-level digital signal routing and interface requirements including:
• Multi-Port Multiprocessor Interfaces
• Wide Data and Address Bus Multiplexing
(e.g. 16:1 High-Speed Bus MUX)
• Programmable Control Signal Routing
(e.g. Interrupts, DMAREQs, etc.)
• Board-Level PCB Signal Routing for Prototyping or
Programmable Bus Interfaces
The devices feature fast operation, with input-to-output
signal delays (Tpd) of 3.0ns and clock-to-output delays of
3.0ns.
The architecture of the devices consists of a series of
programmable I/O cells interconnected by a Global Routing Pool (GRP). All I/O pin inputs enter the GRP directly
or are registered or latched so they can be routed to the
required I/O outputs. I/O pin inputs are defined as four
sets (A,B,C,D) which have access to the four MUX inputs
Copyright © 2004 Lattice Semiconductor Corporation. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein
are subject to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8037; http://www.latticesemi.com
gdx80va_05
1
August 2004
Specifications ispGDX80VA
Description (Continued)
found in each I/O cell. Each output has individual, programmable I/O tri-state control (OE), output latch clock
(CLK), clock enable (CLKEN), and two multiplexer control (MUX0 and MUX1) inputs. Polarity for these signals
is programmable for each I/O cell. The MUX0 and MUX1
inputs control a fast 4:1 MUX, allowing dynamic selection
of up to four signal sources for a given output. A wider
16:1 MUX can be implemented with the MUX expander
feature of each I/O and a propagation delay increase of
2.0ns. OE, CLK, CLKEN, and MUX0 and MUX1 inputs
can be driven directly from selected sets of I/O pins.
Optional dedicated clock input pins give minimum clockto-output delays. CLK and CLKEN share the same set of
I/O pins. CLKEN disables the register clock when
CLKEN = 0.
In addition, there are no pin-to-pin routing constraints for
1:1 or 1:n signal routing. That is, any I/O pin configured
as an input can drive one or more I/O pins configured as
outputs.
Through in-system programming, connections between
I/O pins and architectural features (latched or registered
inputs or outputs, output enable control, etc.) can be
defined. In keeping with its data path application focus,
the ispGDXVA devices contain no programmable logic
arrays. All input pins include Schmitt trigger buffers for
noise immunity. These connections are programmed
into the device using non-volatile E2CMOS technology.
Non-volatile technology means the device configuration
is saved even when the power is removed from the
device.
All I/O pins are equipped with IEEE1149.1-compliant
Boundary Scan Test circuitry for enhanced testability. In
addition, in-system programming is supported through
the Test Access Port via a special set of private commands.
The device pins also have the ability to set outputs to
fixed HIGH or LOW logic levels (Jumper or DIP Switch
mode). Device outputs are specified for 24mA sink and
12mA source current (at JEDEC LVTTL levels) and can
be tied together in parallel for greater drive. On the
ispGDXVA, each I/O pin is individually programmable for
3.3V or 2.5V output levels as described later. Programmable output slew rate control can be defined
independently for each I/O pin to reduce overall ground
bounce and switching noise.
The ispGDXVA I/Os are designed to withstand “live
insertion” system environments. The I/O buffers are
disabled during power-up and power-down cycles. When
designing for “live insertion,” absolute maximum rating
conditions for the Vcc and I/O pins must still be met.
Table 1. ispGDXVA Family Members
ispGDXV/VA Device
ispGDX80VA
ispGDX160V/VA
ispGDX240VA
I/O Pins
80
160
240
I/O-OE Inputs*
20
40
60
I/O-CLK / CLKEN Inputs*
20
40
60
I/O-MUXsel1 Inputs*
I/O-MUXsel2 Inputs*
20
20
40
40
60
60
Dedicated Clock Pins**
2
4
4
EPEN
1
1
1
TOE
1
4
1
1
4
1
1
4
1
BSCAN Interface
RESET
Pin Count/Package
100-Pin TQFP
208-Pin PQFP 388-Ball fpBGA
208-Ball fpBGA
272-Ball BGA
* The CLK/CLK_EN, OE, MUX0 and MUX1 terminals on each I/O cell can each be assigned to
25% of the I/Os.
** Global clock pins Y0, Y1, Y2 and Y3 are multiplexed with CLKEN0, CLKEN1, CLKEN2 and
CLKEN3 respectively in all devices.
2
Specifications ispGDX80VA
Architecture
The ispGDXVA architecture is different from traditional
PLD architectures, in keeping with its unique application
focus. The block diagram is shown below. The programmable interconnect consists of a single Global Routing
Pool (GRP). Unlike ispLSI® devices, there are no programmable logic arrays on the device. Control signals for
OEs, Clocks/Clock Enables and MUX Controls must
come from designated sets of I/O pins. The polarity of
these signals can be independently programmed in each
I/O cell.
The various I/O pin sets are also shown in the block
diagram below. The A, B, C, and D I/O pins are grouped
together with one group per side.
I/O Architecture
Each I/O cell contains a 4:1 dynamic MUX controlled by
two select lines as well as a 4x4 crossbar switch controlled by software for increased routing flexiability (Figure
1). The four data inputs to the MUX (called M0, M1, M2,
and M3) come from I/O signals in the GRP and/or
adjacent I/O cells. Each MUX data input can access one
quarter of the total I/Os. For example, in an 80-I/O
ispGDXVA, each data input can connect to one of 20 I/O
pins. MUX0 and MUX1 can be driven by designated I/O
pins called MUXsel1 and MUXsel2. Each MUXsel input
covers 25% of the total I/O pins (e.g. 20 out of 80). MUX0
and MUX1 can be driven from either MUXsel1 or MUXsel2.
Each I/O cell drives a unique pin. The OE control for each
I/O pin is independent and may be driven via the GRP by
one of the designated I/O pins (I/O-OE set). The I/O-OE
set consists of 25% of the total I/O pins. Boundary Scan
test is supported by dedicated registers at each I/O pin.
In-system programming is accomplished through the
standard Boundary Scan protocol.
Figure 1. ispGDXVA I/O Cell and GRP Detail (80 I/O Device)
Logic “0” Logic “1”
80 I/O Inputs
I/OCell 0
I/O Cell 79
I/O Cell 1
I/O Cell 78
••
•
E2CMOS
Programmable
Interconnect
To 2 Adjacent
I/O Cells above
From MUX Outputs
of 2 Adjacent I/O Cells
4-to-1 MUX
N+2
I/O Group A
I/O Group B
I/O Group C
I/O Group D
N+1
N-1
•
•
•
•
•
•
Register
or Latch
M0
M1
M2
M3
MUX0 MUX1
4x4
Crossbar
Switch
N-2
From MUX Outputs
of 2 Adjacent I/O Cells
Prog.
Prog.
Pull-up Bus Hold
Latch
(VCCIO)
Bypass Option
A
B
D
Q
I/O
Pin
C
R
CLK
To 2 Adjacent
I/O Cells below
CLK_EN Reset
Prog. Open Drain
2.5V/3.3V Output
Prog. Slew Rate
Boundary
Scan Cell
I/O Cell N
••
•
I/O Cell 38
I/O Cell 41
••••••
I/O Cell 39
40 I/O Cells
I/O Cell 40
40 I/O Cells
80 Input GRP
Inputs Vertical
Outputs Horizontal
Global
Y0-Y3
Reset
Global
Clocks /
Clock_Enables
ispGDXVA architecture enhancements over ispGDX (5V)
3
Specifications ispGDX80VA
allow adjacent I/O cell outputs to be directly connected
without passing through the global routing pool. The
relationship between the [N+i] adjacent cells and A, B, C
and D inputs will vary depending on where the I/O cell is
located on the physical die. The I/O cells can be grouped
into “normal” and “reflected” I/O cells or I/O “hemispheres.” These are defined as:
I/O MUX Operation
0
0
M0
0
1
M1
1
1
M2
1
0
M3
Device
Flexible mapping of MUXselx to MUXx allows the user to
change the MUX select assignment after the ispGDXVA
device has been soldered to the board. Figure 1 shows
that the I/O cell can accept (by programming the appropriate fuses) inputs from the MUX outputs of four adjacent
I/O cells, two above and two below. This enables cascading of the MUXes to enable wider (up to 16:1) MUX
implementations.
Normal I/O Cells
Reflected I/O Cells
ispGDX80VA
B9-B0, A19-A0,
D19-D10
B10-B19, C0-C19,
D0-D9
ispGDX160VA
B19-B0, A39-A0,
D39-D20
B20-B39, C0-C39,
D0-D19
ispGDX240VA
B29-B0, A59-A0,
D59-D30
B30-B59, C0-C59,
D0-D29
Table 2 shows the relationship between adjacent I/O
cells as well as their relationship to direct MUX inputs.
Note that the MUX expansion is circular and that I/O cell
B10, for example, draws on I/Os B9 and B8, as well as
B11 and B12, even though they are in different hemispheres of the physical die. Table 2 shows some typical
cases and all boundary cases. All other cells can be
extrapolated from the pattern shown in the table.
The I/O cell also includes a programmable flow-through
latch or register that can be placed in the input or output
path and bypassed for combinatorial outputs. As shown
in Figure 1, when the input control MUX of the register/
latch selects the “A” path, the register/latch gets its inputs
from the 4:1 MUX and drives the I/O output. When
selecting the “B” path, the register/latch is directly driven
by the I/O input while its output feeds the GRP. The
programmable polarity Clock to the latch or register can
be connected to any I/O in the I/O-CLK/CLKEN set (onequarter of total I/Os) or to one of the dedicated clock input
pins (Yx). The programmable polarity Clock Enable input
to the register can be programmed to connect to any of
the I/O-CLK/CLKEN input pin set or to the global clock
enable inputs (CLKENx). Use of the dedicated clock
inputs gives minimum clock-to-output delays and minimizes delay variation with fanout. Combinatorial output
mode may be implemented by a dedicated architecture
bit and bypass MUX. I/O cell output polarity can be
programmed as active high or active low.
Figure 2. I/O Hemisphere Configuration of
ispGDX80VA
MUX Expander Using Adjacent I/O Cells
D19
D10
D9
D0
B0
B9
B10
B19
A19
The ispGDXVA allows adjacent I/O cell MUXes to be
cascaded to form wider input MUXes (up to 16 x 1)
without incurring an additional full Tpd penalty. However,
there are certain dependencies on the locality of the
adjacent MUXes when used along with direct MUX
inputs.
I/O cell 79
A0
I/O cell index increases in this direction
I/O cell 0
I/O cell 39
I/O cell index increases in this direction
Data Input Selected
C19
MUX0
C0
MUX1
I/O cell 40
Adjacent I/O Cells
Direct and Expander Input Routing
Expansion inputs MUXOUT[n-2], MUXOUT[n-1],
MUXOUT[n+1], and MUXOUT[n+2] are fuse-selectable
for each I/O cell MUX. These expansion inputs share the
same path as the standard A, B, C and D MUX inputs, and
Table 2 also illustrates the routing of MUX direct inputs
that are accessible when using adjacent I/O cells as
inputs. Take I/O cell D13 as an example, which is also
shown in Figure 3.
4
Specifications ispGDX80VA
Figure 3. Adjacent I/O Cells vs. Direct Input Path for
ispGDX80VA, I/O D13
Special Features
Slew Rate Control
ispGDX80VA I/O Cell
All output buffers contain a programmable slew rate
control that provides software-selectable slew rate options.
I/O Group A
D11 MUX Out
S1 S0
I/O Group B
.m0
4x4
Crossbar
Switch
D12 MUX Out
I/O Group C
.m1
.m2
Open Drain Control
D13
All output buffers provide a programmable Open-Drain
option which allows the user to drive system level reset,
interrupt and enable/disable lines directly without the
need for an off-chip Open-Drain or Open-Collector buffer.
Wire-OR logic functions can be performed at the printed
circuit board level.
.m3
D14 MUX Out
I/O Group D
D15 MUX Out
It can be seen from Figure 3 that if the D11 adjacent I/O
cell is used, the I/O group “A” input is no longer available
as a direct MUX input.
Pull-up Resistor
All pins have a programmable active pull-up. A typical
resistor value for the pull-up ranges from 50kΩ to 80kΩ.
The ispGDXVA can implement MUXes up to 16 bits wide
in a single level of logic, but care must be taken when
combining adjacent I/O cell outputs with direct MUX
inputs. Any particular combination of adjacent I/O cells as
MUX inputs will dictate what I/O groups (A, B, C or D) can
be routed to the remaining inputs. By properly choosing
the adjacent I/O cells, all of the MUX inputs can be
utilized.
Output Latch (Bus Hold)
All pins have a programmable circuit that weakly holds
the previously driven state when all drivers connected to
the pin (including the pin's output driver as well as any
other devices connected to the pin by external bus) are
tristated.
Table 2. Adjacent I/O Cells (Mapping of
ispGDX80VA)
User-Programmable I/Os
The ispGDX80VA features user-programmable
I/Os supporting either 3.3V or 2.5V output voltage level
options. The ispGDX80VA uses a VCCIO pin to provide
the 2.5V reference voltage when used.
Data A/ Data B/ Data C/ Data D/
MUXOUT MUXOUT MUXOUT MUXOUT
Reflected
I/O Cells
Normal
I/O Cells
B10
B12
B11
B9
B8
B11
B12
B13
B14
B12
B13
B10
B11
B9
B10
B13
B15
B14
B12
B11
D6
D8
D7
D5
D4
D7
D9
D8
D6
D5
D8
D10
D9
D7
D6
D9
D11
D10
D8
D7
D10
D8
D9
D11
D12
D11
D9
D10
D12
D13
D12
D10
D11
D13
D14
D13
D11
D12
D14
D15
B6
B4
B5
B7
B8
B7
B5
B6
B8
B9
B8
B9
B6
B7
B8
B9
B10
B10
B11
B7
PCI Compatible Drive Capability
The ispGDX80VA supports PCI compatible drive capability for all I/Os.
5
Specifications ispGDX80VA
Applications
Programmable Switch Replacement (PSR)
The ispGDXVA Family architecture has been developed
to deliver an in-system programmable signal routing
solution with high speed and high flexibility. The devices
are targeted for three similar but distinct classes of endsystem applications:
Includes solid-state replacement and integration of mechanical DIP Switch and jumper functions. Through
in-system programming, pins of the ispGDXVA devices
can be driven to HIGH or LOW logic levels to emulate the
traditional device outputs. PSR functions do not require
any input pin connections.
Programmable, Random Signal
Interconnect (PRSI)
These applications actually require somewhat different
silicon features. PRSI functions require that the device
support arbitrary signal routing on-chip between any two
pins with no routing restrictions. The routing connections
are static (determined at programming time) and each
input-to-output path operates independently. As a result,
there is little need for dynamic signal controls (OE,
clocks, etc.). Because the ispGDXVA device will interface with control logic outputs from other components
(such as ispLSI or ispMACH™) on the board (which
frequently change late in the design process as control
logic is finalized), there must be no restrictions on pin-topin signal routing for this type of application.
This class includes PCB-level programmable signal routing and may be used to provide arbitrary signal swapping
between chips. It opens up the possibilities of programmable system hardware. It is characterized by the need
to provide a large number of 1:1 pin connections which
are statically configured, i.e., the pin-to-pin paths do not
need to change dynamically in response to control inputs.
Programmable Data Path (PDP)
This application area includes system data path transceiver, MUX and latch functions. With today’s 32- and
64-bit microprocessor buses, but standard data path glue
components still relegated primarily to eight bits, PCBs
are frequently crammed with a dozen or more data path
glue chips that use valuable real estate. Many of these
applications consist of “on-board” bus and memory interfaces that do not require the very high drive of standard
glue functions but can benefit from higher integration.
Therefore, there is a need for a flexible means to integrate these on-board data path functions in an analogous
way to programmable logic’s solution to control logic
integration. Lattice’s CPLDs make an ideal control logic
complement to the ispGDXVA in-system programmable
data path devices as shown below.
PDP functions, on the other hand, require the ability to
dynamically switch signal routing (MUXing) as well as
latch and tri-state output signals. As a result, the programmable interconnect is used to define possible signal
routes that are then selected dynamically by control
signals from an external MPU or control logic. These
functions are usually formulated early in the conceptual
design of a product. The data path requirements are
driven by the microprocessor, bus and memory architecture defined for the system. This part of the design is the
earliest portion of the system design frozen, and will not
usually change late in the design because the result
would be total system and PCB redesign. As a result, the
ability to accommodate arbitrary any pin-to-any pin rerouting is not a strong requirement as long as the designer
has the ability to define his functions with a reasonable
degree of freedom initially.
Figure 4. ispGDXVA Complements Lattice CPLDs
Address
Inputs
(from µP)
Control
Inputs
(from µP)
State Machines
ispLSI/
ispMACH
Device
Decoders
System
Clock(s)
Data Path
Bus #1
Buffers / Registers
Control
Outputs
As a result, the ispGDXVA architecture has been defined
to support PSR and PRSI applications (including bidirectional paths) with no restrictions, while PDP applications
(using dynamic MUXing) are supported with a minimal
number of restrictions as described below. In this way,
speed and cost can be optimized and the devices can still
support the system designer’s needs.
ISP/JTAG
Interface
ispGDXVA
Device
Buffers / Registers
Configuration
(Switch)
Outputs
The following diagrams illustrate several ispGDXVA applications.
Data Path
Bus #2
6
Specifications ispGDX80VA
Applications (Continued)
Designing with the ispGDXVA
As mentioned earlier, this architecture satisfies the PRSI
class of applications without restrictions: any I/O pin as a
single input or bidirectional can drive any other I/O pin as
output.
XCVR
Muxed Address Data Bus
Control Bus
Figure 5. Address Demultiplex/Data Buffering
I/OA
I/OB
Buffered
Data
For the case of PDP applications, the designer does have
to take into consideration the limitations on pins that can
be used as control (MUX0, MUX1, OE, CLK) or data
(MUXA-D) inputs. The restrictions on control inputs are
not likely to cause any major design issues because the
input possibilities span 25% of the total pins.
OEA OEB
To Memory/
Peripherals
Address
Latch
D
Q
Address
The MUXA-D input partitioning requires that designers
consciously assign pinouts so that MUX inputs are in the
appropriate, disjoint groups. For example, since the
MUXA group includes I/O A0-A19 (80 I/O device), it is not
possible to use I/O A0 and I/O A9 in the same MUX
function. As previously discussed, data path functions
will be assigned early in the design process and these
restrictions are reasonable in order to optimize speed
and cost.
CLK
Figure 6. Data Bus Byte Swapper
XCVR
I/OA
D0-7
I/OB
XCVR
Data Bus A
Control Bus
OEA OEB
I/OA
I/OB
OEA OEB
XCVR
D8-15
I/OA
User Electronic Signature
Data Bus B
D0-7
The ispGDXVA Family includes dedicated User Electronic Signature (UES) E2CMOS storage to allow users
to code design-specific information into the devices to
identify particular manufacturing dates, code revisions,
or the like. The UES information is accessible through
the boundary scan programming port via a specific command. This information can be read even when the
security cell is programmed.
D8-15
I/OB
XCVR
OEA OEB
I/OA
I/OB
OEA OEB
Security
The ispGDXVA Family includes a security feature that
prevents reading the device program once set. Even
when set, it does not inhibit reading the UES or device ID
code. It can be erased only via a device bulk erase.
Figure 7. Four-Port Memory Interface
Bus 1
Bus 2
Bus 3
Bus 4
4-to-1
16-Bit MUX
Bidirectional
Port #1
OE1
Memory
Port
Port #2
OE2
OEM
Port #3
OE3
SEL0
Port #4
OE4
SEL1
To
Memory
Note: All OE and SEL lines driven by external arbiter logic (not shown).
7
Specifications ispGDX80VA
Absolute Maximum Ratings 1,2
Supply Voltage Vcc ................................. -0.5 to +5.4V
Input Voltage Applied ............................... -0.5 to +5.6V
Off-State Output Voltage Applied ............ -0.5 to +5.6V
Storage Temperature ................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (TJ) with Power Applied ... 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
2. Compliance with the Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM is a requirement.
DC Recommended Operating Conditions
SYMBOL
MIN.
MAX.
UNITS
Commercial
TA = 0°C to +70°C
3.00
3.60
V
Industrial
TA = -40°C to +85°C
3.00
3.60
V
2.3
3.60
PARAMETER
VCC
Supply Voltage
VCCIO
I/O Reference Voltage
V
Table 2-0005/gdxva
Capacitance (TA=25oC, f=1.0 MHz)
SYMBOL
C1
C2
TYPICAL
UNITS
I/O Capacitance
PARAMETER
PACKAGE TYPE
TQFP
7
pf
VCC = 3.3V, VI/O = 2.0V
TEST CONDITIONS
Dedicated Clock Capacitance
TQFP
8
pf
VCC = 3.3V, VY = 2.0V
Table 2-0006/gdxva
Erase/Reprogram Specifications
PARAMETER
Erase/Reprogram Cycles
8
MINIMUM
MAXIMUM
UNITS
10,000
—
Cycles
Specifications ispGDX80VA
Switching Test Conditions
Figure 8. Test Load
Input Pulse Levels
GND to VCCIO(MIN)
Input Rise and Fall Time
VCCIO
< 1.5ns 10% to 90%
Input Timing Reference Levels
VCCIO(MIN)/2
Output Timing Reference Levels
VCCIO(MIN)/2
Output Load
See Figure 8
R1
Device
Output
3-state levels are measured 0.5V from steady-state active level.
Test
Point
CL*
R2
Output Load Conditions (See Figure 8)
3.3V
R1
R2
R1
153Ω
134Ω
156Ω
144Ω 35pF
Active High
∞
134Ω
∞
144Ω 35pF
Active Low
153Ω
∞
156Ω
∞
35pF
Active High to Z
at VOH -0.5V
∞
134Ω
∞
144Ω
5pF
Active Low to Z
at VOL+0.5V
153Ω
∞
156Ω
∞
5pF
∞
∞
∞
∞
35pF
TEST CONDITION
A
B
C
*CL includes Test Fixture and Probe Capacitance.
2.5V
D
Slow Slew
R2
CL
0213D
Table 2-0004A/gdxva
DC Electrical Characteristics for 3.3V Range
Over Recommended Operating Conditions
SYMBOL
PARAMETER
MIN.
TYP.
–
3.0
–
VCCIO
VIL
VIH
Input Low Voltage
VOH ≤ VOUT or VOUT ≤ VOL (MAX)
-0.3
Input High Voltage
VOH ≤ VOUT or VOUT ≤ VOL(MAX)
2.0
VOL
Output Low Voltage
VCC = VCC (MIN)
IOL = +100µA
VOH
I/O Reference Voltage
Output High Voltage
1
CONDITION
VCC = VCC (MIN)
MAX. UNITS
3.6
V
–
0.8
V
–
5.25
V
–
–
0.2
V
IOL = +24mA
–
–
0.55
V
IOH = -100µA
2.8
–
–
V
IOH = -12mA
2.4
–
–
V
Table 2-0007/gdxva
1. Typical values are at VCC = 3.3V and TA = 25°C.
9
Specifications ispGDX80VA
DC Electrical Characteristics for 2.5V Range
Over Recommended Operating Conditions
SYMBOL
VCCIO
VIL
VIH
Input Low Voltage
Input High Voltage
VOL
Output Low Voltage
VOH
CONDITION
PARAMETER
I/O Reference Voltage
–
TYP.
MAX. UNITS
2.3
–
2.7
V
VOH(MIN) ≤ VOUT or VOUT ≤ VOL(MAX)
-0.3
–
0.7
V
VOH(MIN) ≤ VOUT or VOUT ≤ VOL(MAX)
1.7
–
5.25
V
–
–
0.2
V
VCCIO=MIN, IOL = 100µA
VCCIO=MIN, IOL = 8mA
Output High Voltage
MIN.
–
–
0.6
V
VCCIO=MIN, IOH = -100µA
2.1
–
–
V
VCCIO=MIN, IOH = -8mA
1.8
–
–
V
2.5V/gdxva
DC Electrical Characteristics
Over Recommended Operating Conditions
SYMBOL
IIL
IIH
MIN.
TYP.2
MAX.
0V ≤ VIN ≤ VIL (MAX)
–
–
-10
µA
(VCCIO-0.2) ≤ VIN ≤ VCCIO
–
–
10
µA
VCCIO ≤ VIN ≤ 5.25V
–
–
50
µA
–
–
-200
µA
Bus Hold Low Sustaining Current
0V ≤ VIN ≤ VIL (MAX)
VIN = VIL (MAX)
40
–
–
µA
Bus Hold High Sustaining Current
VIN = VIH (MIN)
-40
–
–
µA
Bus Hold Low Overdrive Current
0V ≤ VIN ≤ VCCIO
–
–
550
µA
Bus Hold High Overdrive Current
Bus Hold Trip Points
0V ≤ VIN ≤ VCCIO
–
–
-550
µA
VIL
–
VIH
V
–
-250
mA
CONDITION
PARAMETER
Input or I/O Low Leakage Current
Input or I/O High Leakage Current
IPU
IBHLS
IBHHS
IBHLO
IBHHO
IBHT
IOS1
ICCQ4
I/O Active Pullup Current
UNITS
Output Short Circuit Current
VCC = 3.3V, VOUT = 0.5V, TA = 25°C
–
Quiescent Power Supply Current
VIL = 0.5V, VIH = VCC
–
12
–
mA
ICC
Dynamic Power Supply Current
per Input Switching
One input toggling at 50% duty cycle,
outputs open.
–
See
Note 3
–
mA/
MHz
ICONT 5
Maximum Continuous I/O Pin Sink
Current Through Any GND Pin
–
–
160
mA
–
DC Char_gdx80va
1. One output at a time for a maximum of one second. VOUT = 0.5V was selected to avoid test problems by
tester ground degradation. Characterized, but not 100% tested.
2. Typical values are at VCC = 3.3V and TA = 25°C.
3. ICC / MHz = (0.002 x I/O cell fanout) + 0.022.
e.g. An input driving four I/O cells at 40MHz results in a dynamic ICC of approximately ((0.002 x 4) + 0.022) x 40 = 1.20mA.
4. For a typical application with 50% of I/O pins used as inputs, 50% used as outputs or bi-directionals.
5. This parameter limits the total current sinking of I/O pins surrounding the nearest GND pin.
10
Specifications ispGDX80VA
External Timing Parameters
Over Recommended Operating Conditions
TEST1
PARAMETER COND. #
tpd2
tsel2
fmax (Tog.)
fmax (Ext.)
tsu1
tsu2
tsu3
tsu4
tsuce1
tsuce2
tsuce3
th1
th2
th3
th4
thce1
thce2
thce3
tgco12
tgco22
tco12
tco22
ten2
tdis2
ttoeen2
ttoedis2
twh
twl
trst
trw
tsl
tsk
-33
DESCRIPTION
-3
-5
UNITS
MIN. MAX. MIN. MAX. MIN. MAX.
A
1 Data Prop. Delay: Any I/O Pin to Any I/O Pin (4:1 MUX)
–
3.0
–
3.5
–
5.0
ns
A
2 Data Prop. Delay: MUXsel Inputs to Any Output (4:1 MUX)
–
3.2
–
3.5
–
5.0
ns
–
3 Clk. Frequency, Max. Toggle
–
4 Clk. Frequency with External Feedback (
–
250
–
250
–
143
–
MHz
208.3
–
166.7
–
111
–
MHz
5 Input Latch or Reg. Setup Time Before Yx
2.2
–
3.0
–
4.0
–
ns
–
6 Input Latch or Reg. Setup Time Before I/O Clk.
1.8
–
2.5
–
3.0
–
ns
–
7 Output Latch or Reg. Setup Time Before Yx
1.8
–
2.5
–
4.0
–
ns
–
8 Output Latch or Reg. Setup Time Before I/O Clk.
1.5
–
2.0
–
3.0
–
ns
–
9 Global Clk. Enable Setup Time Before Yx
1.8
–
2.5
–
2.5
–
ns
–
10 Global Clk. Enable Setup Time Before I/O Clk.
1.5
–
1.5
–
1.5
–
ns
–
11 I/O Clk. Enable Setup Time Before Yx
2.5
–
3.0
–
4.5
–
ns
–
12 Input Latch or Reg. Hold Time (Yx)
0.0
–
0.0
–
0.0
–
ns
–
13 Input Latch or Reg. Hold Time (I/O Clk.)
0.5
–
0.5
–
1.5
–
ns
–
14 Output Latch or Reg. Hold Time (Yx)
0.0
–
0.0
–
0.0
–
ns
–
15 Output Latch or Reg. Hold Time (I/O Clk.)
0.5
–
1.0
–
1.5
–
ns
–
16 Global Clk. Enable Hold Time (Yx)
0.0
–
0.0
–
0.0
–
ns
–
17 Global Clk. Enable Hold Time (I/O Clk.)
1.0
–
1.0
–
1.5
–
ns
–
18 I/O Clk. Enable Hold Time (Yx)
0.0
–
0.0
–
0.0
–
ns
A
19 Output Latch or Reg. Clk. (from Yx) to Output Delay
–
3.0
–
3.5
–
5.0
ns
A
20 Input Latch or Register Clk. (from Yx) to Output Delay
–
5.5
–
6.0
–
8.5
ns
A
21 Output Latch or Reg. Clk. (from I/O pin) to Output Delay
–
3.5
–
4.0
–
6.0
ns
A
22 Input Latch or Reg. Clk. (from I/O pin) to Output Delay
–
6.0
–
7.0
–
9.5
ns
B
23 Input to Output Enable
–
4.0
–
5.0
–
6.0
ns
C
24 Input to Output Disable
–
4.0
–
5.0
–
6.0
ns
B
25 Test OE Output Enable
–
5.5
–
6.0
–
6.0
ns
C
26 Test OE Output Disable
–
5.5
–
6.0
–
6.0
ns
–
27 Clock Pulse Duration, High
2.0
–
2.0
–
3.5
–
ns
–
28 Clock Pulse Duration, Low
2.0
–
2.0
–
3.5
–
ns
–
29 Register Reset Delay from RESET Low
–
7.0
–
8.0
–
14.0
ns
–
30 Reset Pulse Width
4.5
–
5.0
–
10.0
–
ns
D
31 Output Delay Adder for Output Timings Using Slow Slew Rate
–
3.0
–
3.5
–
5.0
ns
1
tsu3+tgco1
)
ns
0.5
–
0.5
–
0.5
–
A 32 Output Skew (tgco1 Across Chip)
1. All timings measured with one output switching, fast output slew rate setting, except tsl.
2. The delay parameters are measured with Vcc as I/O voltage reference. An additional 0.5ns delay is incurred when Vccio is
used as I/O voltage reference.
3. The new “-3” speed grade (tpd = 3.0ns) will be effective starting with date code A113xxxx. Devices with topside date codes
prior to A113xxxx adhere to the shaded “-3” speed grade (tpd = 3.5ns).
11
Specifications ispGDX80VA
External Timing Parameters
Over Recommended Operating Conditions
TEST1
PARAMETER COND. #
tpd2
tsel2
fmax (Tog.)
fmax (Ext.)
tsu1
tsu2
tsu3
tsu4
tsuce1
tsuce2
tsuce3
th1
th2
th3
th4
thce1
thce2
thce3
tgco12
tgco22
tco12
tco22
ten2
tdis2
ttoeen2
ttoedis2
twh
twl
trst
trw
tsl
tsk
-9
-7
DESCRIPTION
UNITS
MIN. MAX. MIN. MAX.
A
1 Data Prop. Delay: Any I/O pin to Any I/O Pin (4:1 MUX)
–
7.0
–
9.0
ns
A
2 Data Prop. Delay: MUXsel Inputs to Any Output (4:1 MUX)
–
7.0
–
9.0
ns
–
3 Clk. Frequency, Max. Toggle
100
–
83
–
MHz
–
4 Clk. Frequency with External Feedback(
80
–
62.5
–
MHz
–
5 Input Latch or Reg. Setup Time Before Yx
5.5
–
7.0
–
ns
–
6 Input Latch or Reg. Setup Time Before I/O Clock
4.5
–
6.0
–
ns
–
7 Output Latch or Reg. Setup Time Before Yx
5.5
–
7.0
–
ns
–
8 Output Latch or Reg. Setup Time Before I/O Clk.
4.5
–
6.0
–
ns
–
9 Global Clk. Enable Setup Time Before Yx
3.5
–
4.0
–
ns
–
10 Global Clk. Enable Setup Time Before I/O Clk.
2.5
–
3.0
–
ns
–
11 I/O Clk. Enable Setup Time Before Yx
6.5
–
8.5
–
ns
–
12 Input Latch or Reg. Hold Time (Yx)
0.0
–
0.0
–
ns
–
13 Input Latch or Reg. Hold Time (I/O Clk.)
2.5
–
3.0
–
ns
–
14 Output Latch or Reg. Hold Time (Yx)
0.0
–
0.0
–
ns
–
15 Output Latch or Reg. Hold Time (I/O Clk.)
2.5
–
3.0
–
ns
–
16 Global Clk. Enable Hold Time (Yx)
0.0
–
0.0
–
ns
–
17 Global Clk. Enable Hold Time (I/O Clk.)
2.5
–
3.0
–
ns
–
18 I/O Clk. Enable Hold Time (Yx)
0.0
–
0.0
–
ns
A
19 Output Latch or Reg. Clk. (from Yx) to Output Delay
–
7.0
–
9.0
ns
A
20 Input Latch or Reg. Clk. (from Yx) to Output Delay
–
11.0
–
13.5
ns
A
21 Output Latch or Reg. Clk. (from I/O pin) to Output Delay
–
9.0
–
11.5
ns
A
22 Input Latch or Reg. Clock (from I/O pin) to Output Delay
–
13.0
–
15.7
ns
1
tsu3+tgco1
)
B
23 Input to Output Enable
–
8.5
–
10.5
ns
C
24 Input to Output Disable
–
8.5
–
10.5
ns
B
25 Test OE Output Enable
–
8.5
–
10.5
ns
C
26 Test OE Output Disable
–
8.5
–
10.5
ns
–
27 Clk. Pulse Duration, High
5.0
–
6.0
–
ns
–
28 Clk. Pulse Duration, Low
5.0
–
6.0
–
ns
–
29 Reg. Reset Delay from RESET Low
–
18.0
–
22.0
ns
–
30 Reset Pulse Width
14.0
–
18.0
–
ns
D
31 Output Delay Adder for Output Timings Using Slow Slew Rate
–
7.0
–
9.0
ns
ns
1.0
–
A 32 Output Skew (tgco1 Across Chip)
0.5
–
1. All timings measured with one output switching, fast output slew rate setting, except tsl.
2. The delay parameters are measured with Vcc as I/O voltage reference. An additional 0.5ns delay is incurred when Vccio is
used as I/O voltage reference.
12
Specifications ispGDX80VA
External Timing Parameters (Continued)
ispGDX80VA timings are specified with a GRP load
(fanout) of four I/O cells. The figure below shows the ∆
GRP Delay with increased GRP loads. These deltas
apply to any signal path traversing the GRP (MUXA-D,
OE, CLK/CLKEN, MUXsel0-1). Global Clock signals
which do not use the GRP have no fanout delay adder.
ispGDX80VA Maximum ∆ GRP Delay vs. I/O Cell Fanout
∆ GRP Delay (ns)
10
8
6
4
2
0 4 10
20
30
40
50
I/O Cell Fanout
13
60
70
Specifications ispGDX80VA
Internal Timing Parameters
Over Recommended Operating Conditions
-32
PARAMETER
Inputs
tio
GRP
tgrp
MUX
tmuxd
tmuxexp
tmuxs
tmuxsio
tmuxsg
tmuxselexp
Register
tiolat
tiosu
tioh
tioco
tior
tcesu
tceh
Data Path
tfdbk
tiobp
tioob
tmuxcg
tmuxcio
tiodg
tiodio
Outputs
tob
tobs
toeen
toedis
tgoe
ttoe
Clocks
tioclk
tgclk
tgclkeng
tgclkenio
tioclkeng
Global Reset
DESCRIPTION1
#
-3
-5
MIN. MAX. MIN. MAX. MIN. MAX. UNITS
32 Input Buffer Delay
—
0.3
—
0.4
—
0.9
ns
33 GRP Delay
—
1.1
—
1.1
—
1.1
ns
34
35
36
37
38
39
I/O Cell MUX A/B/C/D Data Delay
I/O Cell MUX A/B/C/D Expander Delay
I/O Cell Data Select
I/O Cell Data Select (I/O Clock)
I/O Cell Data Select (Yx Clock)
I/O Cell MUX Data Select Expander Delay
—
—
—
—
—
—
0.8
1.3
1.0
1.5
1.5
1.5
—
—
—
—
—
—
1.0
1.5
1.0
1.5
1.5
1.5
—
—
—
—
—
—
1.5
2.0
1.5
3.0
2.0
2.0
ns
ns
ns
ns
ns
ns
40
41
42
43
44
45
46
I/O Latch Delay
I/O Register Setup Time Before Clock
I/O Register Hold Time After Clock
I/O Register Clock to Output Delay
I/O Reset to Output Delay
I/O Clock Enable Setup Time Before Clock
I/O Clock Enable Hold Time After Clock
—
—
—
—
—
—
—
1.0
0.4
1.4
0.9
1.0
0.6
1.2
—
—
—
—
—
—
—
1.0
0.8
1.7
1.2
1.0
1.3
1.2
—
—
—
—
—
—
—
1.0
2.0
1.5
0.5
1.5
2.0
0.5
ns
ns
ns
ns
ns
ns
ns
47
48
49
50
51
52
53
I/O Register Feedback Delay
I/O Register Bypass Delay
I/O Register Output Buffer Delay
I/O Register A/B/C/D Data Input MUX Delay (Yx Clock)
I/O Register A/B/C/D Data Input MUX Delay (I/O Clock)
I/O Register I/O MUX Delay (Yx Clock)
I/O Register I/O MUX Delay (I/O Clock)
—
—
—
—
—
—
—
0.4
0.0
0.0
1.3
1.3
3.1
3.1
—
—
—
—
—
—
—
0.4
0.0
0.0
1.5
1.5
3.5
3.5
—
—
—
—
—
—
—
0.9
0.0
0.0
2.0
3.0
4.0
5.0
ns
ns
ns
ns
ns
ns
ns
54
55
56
57
58
59
Output Buffer Delay
Output Buffer Delay (Slow Slew Option)
I/O Cell OE to Output Enable
I/O Cell OE to Output Disable
GRP Output Enable and Disable Delay
Test OE Enable and Disable Delay
—
—
—
—
—
—
0.8
3.8
2.6
2.6
0.0
2.5
—
—
—
—
—
—
1.0
4.5
3.5
3.5
0.0
2.5
—
—
—
—
—
—
1.5
6.5
4.0
4.0
0.0
2.0
ns
ns
ns
ns
ns
ns
60
61
62
63
64
I/O Clock Delay
Global Clock Delay
Global Clock Enable (Yx Clock)
Global Clock Enable (I/O Clock)
I/O Clock Enable (Yx Clock)
—
—
—
—
—
0.3
1.3
2.5
2.0
1.5
—
—
—
—
—
0.3
1.3
2.5
2.0
1.5
—
—
—
—
—
2.0
2.0
2.5
3.5
2.5
ns
ns
ns
ns
ns
tgr
65 Global Reset to I/O Register Latch
—
5.2
—
6.0
— 11.0
ns
1. Internal Timing Parameters are not tested and are for reference only.
Timing Rev. 2.9
2. The new “-3” speed grade (tpd = 3.0ns) will be effective starting with date code A113xxxx. Devices with topside date codes prior to
A113xxxx adhere to the shaded “-3” speed grade (tpd = 3.5ns).
14
Specifications ispGDX80VA
Internal Timing Parameters1
Over Recommended Operating Conditions
-7
PARAMETER
Inputs
tio
GRP
tgrp
MUX
tmuxd
tmuxexp
tmuxs
tmuxsio
tmuxsg
tmuxselexp
Register
tiolat
tiosu
tioh
tioco
tior
tcesu
tceh
Data Path
tfdbk
tiobp
tioob
tmuxcg
tmuxcio
tiodg
tiodio
Outputs
tob
tobs
toeen
toedis
tgoe
ttoe
Clocks
tioclk
tgclk
tgclkeng
tgclkenio
tioclkeng
Global Reset
tgr
DESCRIPTION1
#
-9
MIN. MAX. MIN. MAX. UNITS
32
Input Buffer Delay
—
1.4
—
1.9
ns
33
GRP Delay
—
1.1
—
1.1
ns
34
35
36
37
38
I/O Cell MUX A/B/C/D Data Delay
I/O Cell MUX A/B/C/D Expander Delay
I/O Cell Data Select
I/O Cell Data Select (I/O Clock)
I/O Cell Data Select (Yx Clock)
—
—
—
—
—
2.0
2.5
2.0
4.5
2.5
—
—
—
—
—
2.5
3.0
2.5
6.0
3.0
ns
ns
ns
ns
ns
39
I/O Cell MUX Data Select Expander Delay
—
2.5
—
3.0
ns
40
41
42
43
44
45
46
I/O Latch Delay
I/O Register Setup Time Before Clock
I/O Register Hold Time After Clock
I/O Register Clock to Output Delay
I/O Reset to Output Delay
I/O Clock Enable Setup Time Before Clock
I/O Clock Enable Hold Time After Clock
—
—
—
—
—
—
—
1.0
3.2
2.3
0.5
1.5
2.5
1.0
—
—
—
—
—
—
—
1.0
4.4
2.6
0.5
1.5
2.0
2.0
ns
ns
ns
ns
ns
ns
ns
47
48
49
50
51
52
53
I/O Register Feedback Delay
I/O Register Bypass Delay
I/O Register Output Buffer Delay
I/O Register A/B/C/D Data Input MUX Delay (Yx Clock)
I/O Register A/B/C/D Data Input MUX Delay (I/O Clock)
I/O Register I/O MUX Delay (Yx Clock)
I/O Register I/O MUX Delay (I/O Clock)
—
—
—
—
—
—
—
1.2
0.3
0.6
2.5
4.5
5.0
7.0
—
—
—
—
—
—
—
1.3
0.6
0.7
3.0
6.0
6.0
9.0
ns
ns
ns
ns
ns
ns
ns
54
55
56
57
58
59
Output Buffer Delay
Output Buffer Delay (Slow Slew Option)
I/O Cell OE to Output Enable
I/O Cell OE to Output Disable
GRP Output Enable and Disable Delay
Test OE Enable and Disable Delay
—
—
—
—
—
—
2.2
9.2
6.0
6.0
0.0
2.5
—
—
—
—
—
—
2.9
11.9
7.5
7.5
0.0
3.0
ns
ns
ns
ns
ns
ns
60
61
62
63
64
I/O Clock Delay
Global Clock Delay
Global Clock Enable (Yx Clock)
Global Clock Enable (I/O Clock)
I/O Clock Enable (Yx Clock)
—
—
—
—
—
3.2
2.7
3.7
5.7
4.2
—
—
—
—
—
4.4
3.4
5.4
8.4
6.4
ns
ns
ns
ns
ns
65
Global Reset to I/O Register Latch
—
13.7
—
16.4
ns
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to the Timing Model in this data sheet for further details.
15
Timing Rev. 2.9
Specifications ispGDX80VA
Switching Waveforms
DATA
(I/O INPUT)
VALID INPUT
MUXSEL (I/O INPUT)
VALID INPUT
tsu
tsel
DATA (I/O INPUT)
VALID INPUT
th
t gco
CLK
tco
tpd
COMBINATORIAL
I/O OUTPUT
REGISTERED
I/O OUTPUT
1/fmax
(external fdbk)
Combinatorial Output
t suce
t ceh
OE (I/O INPUT)
CLKEN
tdis
ten
Registered Output
COMBINATORIAL
I/O OUTPUT
I/O Output Enable/Disable
RESET
trw
twh
trst
twl
REGISTERED
I/O OUTPUT
CLK
(I/O INPUT)
Clock Width
Reset
ispGDXVA Timing Model
tgoe #58
OE
MUX Expander Input
tmuxd #34
tmuxs #36
tmuxio #37
tmuxg #38
tmuxcg #50
tmuxcio #51
TOE
ttoe #59
A
B
C
D
tiobp #48
D
MUX0
GRP
MUX Expander Output
tmuxexp #35
tmuxselexp #39
Q
tioob #49
I/O Pin
CLKEN
MUX1
tob #54
tobs #55
toeen #56
toedis #57
CLK
tgrp #33
tiod #52, #53
tiolat #40
tiosu #41
tioh #42
tioco #43
tior #44
tcesu #45
tceh #46
tgr #65
RESET
tfdbk #47
tio #32
CLKEN
CLK
tioclkeg #64
tioclk #60
Y0,1,2,3
0902/gdxv/va
tgclk #61
Y0,1,2,3, Enable
tgclkeng #62
tgclkenio #63
16
Specifications ispGDX80VA
are fed into the on-chip programming circuitry where a
state machine controls the programming.
ispLEVER Development System
The ispLEVER Development System supports ispGDX
design using a VHDL or Verilog language syntax. From
creation to in-system programming, the ispLEVER system is an easy-to-use, self-contained design tool.
On-chip programming can be accomplished using an
IEEE 1149.1 boundary scan protocol. The IEEE 1149.1compliant interface signals are Test Data In (TDI), Test
Data Out (TDO), Test Clock (TCK) and Test Mode Select
(TMS) control. The EPEN pin is also used to enable or
disable the JTAG port.
Features
• VHDL and Verilog Synthesis Support Available
The embedded controller port enable pin (EPEN) is used
to enable the JTAG tap controller and in that regard has
similar functionality to a TRST pin. When the pin is driven
high, the JTAG TAP controller is enabled. This is also true
when the pin is left unconnected, in which case the pin is
pulled high by the permanent internal pullup. This allows
ISP programming and BSCAN testing to take place as
specified by the Instruction Table.
• ispGDX Design Compiler
- Design Rule Checker
- I/O Connectivity Checker
- Automatic Compiler Function
• Industry Standard JEDEC File for Programming
• Min/Max Timing Report
• Interfaces To Popular Timing Simulators
• User Electronic Signature (UES) Support
When the pin is driven low, the JTAG TAP controller is
driven to a reset state asynchronously. It stays there
while the pin is held low. After pulling the pin high the
JTAG controller becomes active. The intent of this feature is to allow the JTAG interface to be directly controlled
by the data bus of an embedded controller (hence the
name Embedded Port Enable). The EPEN signal is used
as a “device select” to prevent spurious programming
and/or testing from occuring due to random bit patterns
on the data bus. Figure 9 illustrates the block diagram for
the ispJTAG™ interface.
• Detailed Log and Report Files For Easy Design
Debug
• On-line Help
• Windows® XP, Windows 2000, Windows 98 and
Windows NT® Compatible
• Solaris® and HP-UX Versions Available
In-System Programmability
All necessary programming of the ispGDXVA is done via
four TTL level logic interface signals. These four signals
Figure 9. ispJTAG Device Programming Interface
TDO
TDI
TMS
TCK
ispJTAG
Programming
Interface
EPEN
ispGDX
80VA
Device
ispLSI
Device
ispMACH
Device
17
ispGDX
80VA
Device
ispGDX
80VA
Device
Specifications ispGDX80VA
Boundary Scan
The ispGDXVA devices provide IEEE1149.1a test capability and ISP programming through a standard Boundary
Scan Test Access Port (TAP) interface.
allows customers using boundary scan test to have full
test capability with only a single BSDL file.
The ispGDXVA devices are identified by the 32-bit JTAG
IDCODE register. The device ID assignments are listed
in Table 4.
The boundary scan circuitry on the ispGDXVA Family
operates independently of the programmed pattern. This
Figure 10. Boundary Scan Register Circuit for I/O Pins
HIGHZ
EXTEST
SCANIN
(from previous
cell
TOE
BSCAN
Registers
D
Q
BSCAN
Latches
D
Normal
Function
OE
Q
0
1
EXTEST
PROG_MODE
Normal
Function
Shift DR
D
Q
D
Q
Clock DR
D
Q
0
I/O Pin
1
SCANOUT
(to next cell)
Update DR
Reset
Table 3. I/O Shift Register Order
I/O SHIFT REGISTER ORDER
DEVICE
ispGDX80VA
TDI, TOE, RESET, Y1, Y0, I/O B10 .. B19, I/O C0 .. C19, I/O D0 .. D9, I/O B9 .. B0, I/O A19.. A0,
I/O D19 .. D10, TDO
I/O Shift Reg Order/ispGDXVA
Table 4. ispGDX80VA Device ID Codes
DEVICE
ispGDX80VA
32-BIT BOUNDARY SCAN ID CODE
0001, 0000, 0011, 0101, 0000, 0000, 0100, 0011
ID Code/GDX80VA
18
Specifications ispGDX80VA
Boundary Scan (Continued)
The ispJTAG programming is accomplished by executing Lattice private instructions under the Boundary Scan
State Machine.
Downlowad software, ispCODE ‘C’ routines or any thirdparty programmers. Contact Lattice Technical Support to
obtain more detailed programming information.
Details of the programming sequence are transparent to
the user and are handled by Lattice ISP Daisy Chain
Figure 11. Boundary Scan Register Circuit for Input-Only Pins
Input Pin
SCANIN
(from previous
cell
D
SCANOUT
(to next cell)
Q
Shift DR
Clock DR
Figure 12. Boundary Scan State Machine
1
0
Test-Logic-Reset
0
1
Run-Test/Idle
Select-DR-Scan
0
1
Capture-DR
0
Shift-DR
0
1
Exit1-DR
1
0
Pause-DR
1
1
Select-IR-Scan
0
1
Capture-IR
0
Shift-IR
0
1
Exit1-IR
1
0
Pause-IR
1
0
1
0
0
Exit2-DR
1
Update-DR
1
0
19
0
Exit2-IR
1
Update-IR
1
0
Specifications ispGDX80VA
Boundary Scan (Continued)
Figure 13. Boundary Scan Waveforms and Timing Specifications
TMS
TDI
Tbtsu
Tbtch
Tbth
Tbtcl
Tbtcp
TCK
Tbtvo
Tbtco
TDO
Valid Data
Tbtcsu
Data to be
captured
Valid Data
Tbtch
Data Captured
Tbtuov
Tbtuco
Data to be
driven out
Symbol
Tbtoz
Valid Data
Parameter
Tbtuoz
Valid Data
Min
Max
Units
tbtcp
TCK [BSCAN test] clock pulse width
100
–
ns
tbtch
TCK [BSCAN test] pulse width high
50
–
ns
tbtcl
tbtsu
TCK [BSCAN test] pulse width low
50
–
ns
TCK [BSCAN test] setup time
20
–
ns
tbth
trf
TCK [BSCAN test] hold time
25
–
ns
TCK [BSCAN test] rise and fall time
50
–
mV/ns
tbtco
tbtoz
TAP controller falling edge of clock to valid output
–
25
ns
TAP controller falling edge of clock to data output disable
–
25
ns
tbtvo
tbtcpsu
TAP controller falling edge of clock to data output enable
–
25
ns
BSCAN test Capture register setup time
20
–
ns
tbtcph
tbtuco
BSCAN test Capture register hold time
25
–
ns
BSCAN test Update reg, falling edge of clock to valid output
–
50
ns
tbtuoz
tbtuov
BSCAN test Update reg, falling edge of clock to output disable
–
50
ns
BSCAN test Update reg, falling edge of clock to output enable
–
50
ns
20
Specifications ispGDX80VA
Signal Descriptions
Signal Name
Description
I/O
Input/Output Pins – These are the general purpose bidirectional data pins. When used as outputs,
each may be independently latched, registered or tristated. They can also each assume one other
control function (OE, CLK/CLKEN, and MUXsel as described in the text).
RESET / I/O D10
This pin can be configured by the user through software to act as a RESET pin or as an I/O (I/O D10)
The default is RESET. If programmed to act as RESET, this pin is an active LOW Input Pin and resets
all I/O Register outputs when LOW.
Y1/CLKEN1/TOE,
Y0/CLKEN0
Input Pins – These can be either Global Clocks or Clock Enables. In addition, Y1 is multiplexed with
TOE. Each pin can drive any or all I/O cell registers. The Test Output Enable (TOE) pin tristates all I/O
pins when LOW
EPEN
Input Pin – JTAG TAP Controller Enable Pin. When high, JTAG operation is enabled. When low,
JTAG TAP controller is driven to reset.
TDI
Input Pin – Serial data input during ISP programming or Boundary Scan mode.
TCK
Input Pin – Serial data clock during ISP programming or Boundary Scan mode.
TMS
Input Pin – Control input during ISP programming or Boundary Scan mode.
TDO
Output Pin – Serial data output during ISP programming or Boundary Scan mode.
GND
Ground (GND)
VCC
Vcc – Supply voltage (3.3V).
VCCIO
Input – This pin is used if optional 2.5V output is to be used. Every I/O can independently select either
3.3V or the optional voltage as its output level. If the optional output voltage is not required, this pin
must be connected to the VCC supply. Programmable pull-up resistors and bus-hold latches only draw
current from this supply.
21
Specifications ispGDX80VA
Signal Locations: ispGDX80VA
Signal
100-Pin TQFP
RESET /I/O D10
90
Y0/CLKEN0
38
Y1/CLKEN1/TOE 87
EPEN
35
TDI
39
TCK
36
TMS
86
TDO
85
GND
6, 18, 29, 45, 56, 68, 79, 95
VCC
12, 37, 62, 88
VCCIO
89
I/O Locations: ispGDX80VA
I/O
Signal
Control
Signal
100
TQFP
I/O
Signal
Control
Signal
100
TQFP
I/O
Signal
Control
Signal
I/O A0
I/O A1
I/O A2
I/O A3
I/O A4
GND
I/O A5
I/O A6
I/O A7
I/O A8
I/O A9
VCC
I/O A10
I/O A11
I/O A12
I/O A13
I/O A14
GND
I/O A15
I/O A16
I/O A17
I/O A18
I/O A19
I/O B0
CLK
OE
MUXsel1
MUXsel2
CLK
1
2
3
4
5
OE
MUXsel1
MUXsel2
CLK
25
26
27
28
53
54
55
7
8
9
10
11
I/O C2
I/O C3
I/O C4
GND
I/O C5
I/O C6
I/O C7
I/O C8
I/O C9
VCC
I/O C10
I/O C11
I/O C12
I/O C13
I/O C14
GND
I/O C15
I/O C16
I/O C17
I/O C18
I/O C19
I/O D0
I/O D1
I/O D2
MUXsel1
MUXsel2
CLK
OE
MUXsel1
MUXsel2
CLK
OE
I/O B1
I/O B2
I/O B3
I/O B4
GND
I/O B5
I/O B6
I/O B7
I/O B8
I/O B9
VCC
I/O B10
I/O B11
I/O B12
I/O B13
I/O B14
GND
I/O B15
I/O B16
I/O B17
I/O B18
I/O B19
I/O C0
I/O C1
OE
MUXsel1
MUXsel2
CLK
OE
57
58
59
60
61
MUXsel1
MUXsel2
CLK
OE
MUXsel1
63
64
65
66
67
MUXsel2
CLK
OE
MUXsel1
MUXsel2
CLK
OE
MUXsel1
69
70
71
72
73
74
75
76
MUXsel1
MUXsel2
CLK
OE
MUXsel1
MUXsel2
CLK
OE
MUXsel1
MUXsel2
CLK
13
14
15
16
17
19
20
21
22
23
24
OE
MUXsel1
MUXsel2
CLK
OE
30
31
32
33
34
MUXsel1
MUXsel2
CLK
OE
MUXsel1
40
41
42
43
44
MUXsel2
CLK
OE
MUXsel1
MUXsel2
CLK
OE
46
47
48
49
50
51
52
100
I/O
TQFP Signal
*I/O D10 is multiplexed with RESET. The functionality is programmable and selected through software.
Note: VCC and GND Pads Shown for Reference
22
I/O D3
I/O D4
GND
I/O D5
I/O D6
I/O D7
I/O D8
I/O D9
VCC
VCCIO
I/O D10*
I/O D11
I/O D12
I/O D13
I/O D14
GND
I/O D15
I/O D16
I/O D17
I/O D18
I/O D19
Control
Signal
100
TQFP
MUXsel2
CLK
77
78
OE
MUXsel1
MUXsel2
CLK
OE
80
81
82
83
84
MUXsel1
MUXsel2
CLK
OE
MUXsel1
90
91
92
93
94
MUXsel2
CLK
OE
MUXsel1
MUXsel2
96
97
98
99
100
Specifications ispGDX80VA
Pin Configuration: ispGDX80VA
MUXsel2
CLK
OE
MUXsel1
MUXsel2
CLK
OE
CLK
MUXsel2
MUXsel1
OE
CLK
MUXsel2
MUXsel1
OE
MUXsel1
OE
CLK
MUXsel2
MUXsel1
MUXsel2
MUXsel1
OE
CLK
MUXsel2
I/O D19
I/O D18
I/O D17
I/O D16
I/O D15
GND
I/O D14
I/O D13
I/O D12
I/O D11
RESET/I/O D10
VCCIO
VCC
Y1/CLKEN1/TOE
TMS
TDO
I/O D9
I/O D8
I/O D7
I/O D6
I/O D5
GND
I/O D4
I/O D3
I/O D2
ispGDX80VA
Top View
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
MUXsel1
MUXsel2
CLK
OE
MUXsel1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Data
I/O B2
I/O B3
I/O B4
GND
I/O B5
OE
I/O B6
MUXsel1
I/O B7
MUXsel2
I/O B8
CLK
I/O B9
OE
EPEN
TCK
VCC
Y0/CLKEN0
TDI
I/O B10
MUXsel1
I/O B11
MUXsel2
I/O B12
CLK
I/O B13
OE
I/O B14
MUXsel1
GND
I/O B15
MUXsel2
I/O B16
CLK
I/O B17
OE
I/O B18
MUXsel1
I/O B19
MUXsel2
OE
MUXsel1
MUXsel2
CLK
OE
Data
I/O A0
I/O A1
I/O A2
I/O A3
I/O A4
GND
I/O A5
I/O A6
I/O A7
I/O A8
I/O A9
VCC
I/O A10
I/O A11
I/O A12
I/O A13
I/O A14
GND
I/O A15
I/O A16
I/O A17
I/O A18
I/O A19
I/O B0
I/O B1
Control
MUXsel1
MUXsel2
CLK
Control
CLK
OE
MUXsel1
MUXsel2
CLK
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
Data
Control
ispGDX80VA 100-Pin TQFP Pinout Diagram
23
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
Data
Control
I/O D1
I/O D0
I/O C19
I/O C18
I/O C17
I/O C16
I/O C15
GND
I/O C14
I/O C13
I/O C12
I/O C11
I/O C10
VCC
I/O C9
I/O C8
I/O C7
I/O C6
I/O C5
GND
I/O C4
I/O C3
I/O C2
I/O C1
I/O C0
OE
CLK
MUXsel2
MUXsel1
OE
CLK
MUXsel2
MUXsel1
OE
CLK
MUXsel2
MUXsel1
OE
CLK
MUXsel2
MUXsel1
OE
CLK
MUXsel2
MUXsel1
OE
CLK
Specifications ispGDX80VA
Part Number Description
ispGDX 80VA
X XXXXX X
Device Family
Grade
Blank = Commercial
I = Industrial
Device Number
Package
T100 = 100-Pin TQFP
TN100 = Lead-Free 100-Pin TQFP
Speed
3 = 3.0ns Tpd*
5 = 5.0ns Tpd
7 = 7.0ns Tpd
9 = 9.0ns Tpd
0212/gdx80va
Ordering Information
Conventional Packaging
COMMERCIAL
FAMILY
ispGDXVA
tpd (ns)
ORDERING NUMBER
PACKAGE
3.0*
ispGDX80VA-3T100
100-Pin TQFP
5.0
ispGDX80VA-5T100
100-Pin TQFP
7.0
ispGDX80VA-7T100
100-Pin TQFP
INDUSTRIAL
FAMILY
ispGDXVA
tpd (ns)
ORDERING NUMBER
PACKAGE
5.0
ispGDX80VA-5T100I
100-Pin TQFP
7.0
ispGDX80VA-7T100I
100-Pin TQFP
9.0
ispGDX80VA-9T100I
100-Pin TQFP
Note: The ispGDX80VA devices are dual-marked with both Commercial and Industrial grades. The Commercial speed grade is faster,
e.g. ispGDX80VA-3T100-5I.
*The new “-3” speed grade (tpd = 3.0ns) will be effective starting with date code A113xxxx.
Lead-Free Packaging
COMMERCIAL
FAMILY
ispGDXVA
tpd (ns)
ORDERING NUMBER
PACKAGE
3.0*
ispGDX80VA-3TN100
Lead-Free 100-Pin TQFP
5.0
ispGDX80VA-5TN100
Lead-Free 100-Pin TQFP
7.0
ispGDX80VA-7TN100
Lead-Free 100-Pin TQFP
INDUSTRIAL
FAMILY
ispGDXVA
tpd (ns)
ORDERING NUMBER
PACKAGE
5.0
ispGDX80VA-5TN100I
Lead- Free 100-Pin TQFP
7.0
ispGDX80VA-7TN100I
Lead- Free 100-Pin TQFP
9.0
ispGDX80VA-9TN100I
Lead- Free 100-Pin TQFP
Note: The ispGDX80VA devices are dual-marked with both Commercial and Industrial grades. The Commercial speed grade is faster,
e.g. ispGDX80VA-3T100-5I.
*The new “-3” speed grade (tPD = 3.0ns) will be effective starting with date code A113xxxx.
24
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