ISPLSI2096VE-135LT128I

LeadFree a P ckage Options Available! 3.3V In-System Programmable SuperFAST™ High Density PLD Functional Block Diagram • SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC — 4000 PLD Gates — 96 I/O Pins, Six Dedicated Inputs — 96 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic — 100% Functional, JEDEC and Pinout Compatible with ispLSI 2096V Devices — Pinout Compatible with ispLSI 2192VE Output Routing Pool (ORP) Output Routing Pool (ORP) C7 C5 C4 C2 C1 C0 B7 D Q A1 A2 GLB Logic Array B6 D Q Global Routing Pool (GRP) D Q B5 D Q B4 A3 A5 A6 A7 Output Routing Pool (ORP) • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 250MHz Maximum Operating Frequency — tpd = 4.0ns Propagation Delay — Electrically Erasable and Reprogrammable — Non-Volatile — 100% Tested at Time of Manufacture — Unused Product Term Shutdown Saves Power Output Routing Pool (ORP) C3 A0 A4 • 3.3V LOW VOLTAGE 2096 ARCHITECTURE — Interfaces with Standard 5V TTL Devices C6 B0 B1 B2 Output Routing Pool (ORP) Features ® ispLSI 2096VE B3 Output Routing Pool (ORP) 0919/2096VE Description The ispLSI 2096VE is a High Density Programmable Logic Device containing 96 Registers, six Dedicated Input pins, three Dedicated Clock Input pins, two dedicated Global OE input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2096VE features in-system programmability through the Boundary Scan Test Access Port (TAP) and is 100% IEEE 1149.1 Boundary Scan Testable. The ispLSI 2096VE offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. • IN-SYSTEM PROGRAMMABLE — 3.3V In-System Programmability (ISP™) Using Boundary Scan Test Access Port (TAP) — Open-Drain Output Option for Flexible Bus Interface Capability, Allowing Easy Implementation of Wired-OR or Bus Arbitration Logic — Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality — Reprogram Soldered Devices for Faster Prototyping • 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE The basic unit of logic on the ispLSI 2096VE device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1 .. C7 (see Figure 1). There are a total of 24 GLBs in the ispLSI 2096VE device. Each GLB is made up of four macrocells. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device. • THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS — Enhanced Pin Locking Capability — Three Dedicated Clock Input Pins — Synchronous and Asynchronous Clocks — Programmable Output Slew Rate Control — Flexible Pin Placement — Optimized Global Routing Pool Provides Global Interconnectivity • LEAD-FREE PACKAGE OPTIONS The devices also have 96 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be individually programmed to be a combinatorial input, output or bi-directional I/O pin with 3-state control. The signal levels are TTL compatible voltages and the output drivers can source 4 mA or sink 8 mA. Each output can Copyright © 2004 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com 2096ve_08 1 August 2004 Specifications ispLSI 2096VE Functional Block Diagram Megablock Generic Logic Blocks (GLBs) TDI/IN 0 TMS/IN 1 C4 C1 C2 C3 IN 5 IN 4 I/O 67 I/O 66 I/O 65 I/O 64 I/O 71 I/O 70 I/O 69 I/O 68 I/O 75 I/O 74 I/O 73 I/O 72 I/O 79 I/O 78 I/O 77 I/O 76 I/O 83 I/O 82 I/O 81 I/O 80 I/O 87 I/O 86 I/O 85 I/O 84 C5 C6 C7 C0 I/O 63 I/O 62 I/O 61 I/O 60 Global Routing Pool (GRP) A1 A2 B6 B5 A3 Input Bus B7 A6 A5 A7 Output Routing Pool (ORP) RESET B2 B1 B0 I/O 55 I/O 54 I/O 53 I/O 52 I/O 51 I/O 50 I/O 49 I/O 48 B4 A4 I/O 59 I/O 58 I/O 57 I/O 56 B3 Output Routing Pool (ORP) CLK 0 CLK 1 CLK 2 I/O 12 I/O 13 I/O 14 I/O 15 Output Routing Pool (ORP) I/O 8 I/O 9 I/O 10 I/O 11 Input Bus Output Routing Pool (ORP) A0 Input Bus I/O 4 I/O 5 I/O 6 I/O 7 Input Bus Output Routing Pool (ORP) Output Routing Pool (ORP) I/O 0 I/O 1 I/O 2 I/O 3 I/O 91 I/O 90 I/O 89 I/O 88 I/O 95 I/O 94 I/O 93 I/O 92 GOE 1 GOE 0 Figure 1. ispLSI 2096VE Functional Block Diagram Input Bus Input Bus be programmed independently for fast or slow output slew rate to minimize overall output switching noise. Device pins can be safely driven to 5V signal levels to support mixed-voltage systems. 0917/2096VE Y0 Y1 Y2 I/O 44 I/O 45 I/O 46 I/O 47 I/O 40 I/O 41 I/O 42 I/O 43 I/O 36 I/O 37 I/O 38 I/O 39 I/O 32 I/O 33 I/O 34 I/O 35 TDO/IN 2 TCK/IN 3 I/O 28 I/O 29 I/O 30 I/O 31 I/O 24 I/O 25 I/O 26 I/O 27 I/O 20 I/O 21 I/O 22 I/O 23 I/O 16 I/O 17 I/O 18 I/O 19 BSCAN Programmable Open-Drain Outputs In addition to the standard output configuration, the outputs of the ispLSI 2096VE are individually programmable, either as a standard totem-pole output or an open-drain output. The totem-pole output drives the specified Voh and Vol levels, whereas the open-drain output drives only the specified Vol. The Voh level on the open-drain output depends on the external loading and pull-up. This output configuration is controlled by a programmable fuse. The default configuration when the device is in bulk erased state is totem-pole configuration. The open-drain/totem-pole option is selectable through the ispLEVER software tools. Eight GLBs, 32 I/O cells, two dedicated inputs and two ORPs are connected together to make a Megablock (see Figure 1). The outputs of the eight GLBs are connected to a set of 32 universal I/O cells by the two ORPs. Each ispLSI 2096VE device contains three Megablocks. The GRP has as its inputs, the outputs from all of the GLBs and all of the inputs from the bi-directional I/O cells. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew. Clocks in the ispLSI 2096VE device are selected using the dedicated clock pins. Three dedicated clock pins (Y0, Y1, Y2) or an asynchronous clock can be selected on a GLB basis. The asynchronous or Product Term clock can be generated in any GLB for its own clock. 2 Specifications ispLSI 2096VE Absolute Maximum Ratings 1 Supply Voltage Vcc .................................. -0.5 to +5.4V Input Voltage Applied ............................... -0.5 to +5.6V Off-State Output Voltage Applied ............ -0.5 to +5.6V Storage Temperature ................................ -65 to 150°C Case Temp. with Power Applied .............. -55 to 125°C Max. Junction Temp. (TJ) with Power Applied ... 150°C 1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). DC Recommended Operating Condition SYMBOL PARAMETER VCC Supply Voltage VIL VIH Input Low Voltage MIN. MAX. UNITS Commercial TA = 0°C to + 70°C 3.0 3.6 V Industrial TA = -40°C to + 85°C 3.0 3.6 V 0.8 V 5.25 V VSS – 0.5 Input High Voltage 2.0 Table 2-0005/2096VE Capacitance (TA=25°C, f=1.0 MHz) TYPICAL UNITS Dedicated Input Capacitance 8 pf VCC = 3.3V, VIN = 0.0V I/O Capacitance 6 pf VCC = 3.3V, VI/O = 0.0V Clock and Global Output Enable Capacitance 10 pf VCC = 3.3V, VY = 0.0V SYMBOL C1 C2 C3 PARAMETER TEST CONDITIONS Table 2-0006/2096VE Erase Reprogram Specifications PARAMETER MINIMUM MAXIMUM UNITS 10000 – Cycles Erase/Reprogram Cycles Table 2-0008/2096VE 3 Specifications ispLSI 2096VE Switching Test Conditions Input Pulse Levels Figure 2. Test Load GND to 3.0V Input Rise and Fall Time ≤ 1.5ns 10% to 90% Input Timing Reference Levels 1.5V Output Timing Reference Levels 1.5V Output Load + 3.3V R1 See Figure 2 3-state levels are measured 0.5V from steady-state active level. Device Output Table 2-0003/2096VE Test Point CL* R2 Output Load Conditions (see Figure 2) TEST CONDITION R1 R2 CL 316Ω 348Ω 35pF Active High ∞ 348Ω 35pF Active Low 316Ω 348Ω 35pF Active High to Z at VOH -0.5V ∞ 348Ω 5pF Active Low to Z at VOL +0.5V 316Ω 348Ω 5pF A B C *CL includes Test Fixture and Probe Capacitance. 0213A/2096VE Table 2-0004/2096VE DC Electrical Characteristics Over Recommended Operating Conditions SYMBOL VOL VOH IIL PARAMETER CONDITION 3 MIN. TYP. MAX. UNITS Output Low Voltage IOL= 8 mA – – 0.4 V Output High Voltage IOH = -4 mA 2.4 – – V 0V ≤ VIN ≤ VIL (Max.) – – -10 µA (VCC – 0.2)V ≤ VIN ≤ VCC – – 10 µA VCC ≤ VIN ≤ 5.25V – – 10 µA 0V ≤ VIN ≤ VIL – – -150 µA I/O Active Pull-Up Current Input or I/O Low Leakage Current IIH Input or I/O High Leakage Current IIL-isp IIL-PU IOS1 BSCAN Input Low Leakage Current 0V ≤ VIN ≤ VIL – – -150 µA Output Short Circuit Current VCC = 3.3V, VOUT = 0.5V – – -100 mA ICC2, 4 Operating Power Supply Current VIL = 0.0V, VIH = 3.0V – 125 – mA fCLOCK = 1 MHz Table 2-0007A/2096VE 1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test problems by tester ground degradation. Characterized but not 100% tested. 2. Measured using six 16-bit counters. 3. Typical values are at VCC = 3.3V and TA= 25°C. 4. Maximum I CC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum ICC . 4 Specifications ispLSI 2096VE External Timing Parameters Over Recommended Operating Conditions 3 tpd1 tpd2 fmax fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 tco2 th2 tr1 trw1 tptoeen tptoedis tgoeen tgoedis twh twl -200 -250 TEST COND. # A 1 Data Propagation Delay, 4PT Bypass, ORP Bypass – 4.0 – 4.5 ns A 2 Data Propagation Delay – 6.0 – 7.0 ns DESCRIPTION 1 MIN. MAX. MIN. MAX. 2 A 3 Clock Frequency with Internal Feedback 250 – – 4 Clock Frequency with External Feedback ( tsu2 + tco1) 158 – – 5 Clock Frequency, Max. Toggle 277 – 1 – 6 GLB Reg. Setup Time before Clock, 4 PT Bypass 2.5 – A 7 GLB Reg. Clock to Output Delay, ORP Bypass – 3.0 – 8 GLB Reg. Hold Time after Clock, 4 PT Bypass 0.0 – – 9 GLB Reg. Setup Time before Clock 3.3 – A 10 GLB Reg. Clock to Output Delay – 3.7 0.0 – – 6.0 – 11 GLB Reg. Hold Time after Clock A 12 Ext. Reset Pin to Output Delay, ORP Bypass USE ispLSI 209 6VE-250 FOR NEW DES IGNS PARAMETER UNITS 200 – MHz 133 – MHz 200 – MHz 3.0 – ns – 3.5 ns 0.0 – ns 4.0 – ns – 4.5 ns 0.0 – ns – 6.0 ns 4.0 – ns – 8.0 ns – 8.0 ns – 5.0 ns – 13 Ext. Reset Pulse Duration 3.5 – B 14 Input to Output Enable – 6.0 C 15 Input to Output Disable – 6.0 B 16 Global OE Output Enable – 4.0 C 17 Global OE Output Disable – 4.0 – 5.0 ns – 18 External Synchronous Clock Pulse Duration, High 1.8 – 2.5 – ns – 19 External Synchronous Clock Pulse Duration, Low 1.8 – 2.5 – ns 1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock. 2. Standard 16-bit counter using GRP feedback. 3. Reference Switching Test Conditions section. 5 Table 2-0030A/2096VE v.1.0 Specifications ispLSI 2096VE External Timing Parameters Over Recommended Operating Conditions 3 PARAMETER tpd1 tpd2 fmax fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 tco2 th2 tr1 trw1 tptoeen tptoedis tgoeen tgoedis twh twl -135 TEST COND. # A 1 Data Propagation Delay, 4PT Bypass, ORP Bypass A 2 Data Propagation Delay A 3 Clock Frequency with Internal Feedback – 4 – – DESCRIPTION 1 -100 MIN. MAX. MIN. MAX. – 7.5 – 10.0 UNITS ns – 10.0 – 13.0 ns 135 – 100 – MHz Clock Frequency with External Feedback ( tsu2 + tco1) 100 – 77 – MHz 5 Clock Frequency, Max. Toggle 143 – 100 – MHz 6 GLB Reg. Setup Time before Clock, 4 PT Bypass 5.0 – 6.5 – ns A 7 GLB Reg. Clock to Output Delay, ORP Bypass – 4.0 – 5.0 ns – 8 GLB Reg. Hold Time after Clock, 4 PT Bypass 0.0 – 0.0 – ns GLB Reg. Setup Time before Clock 2 1 – 9 6.0 – 8.0 – ns A 10 GLB Reg. Clock to Output Delay – 5.0 – 6.0 ns – 11 GLB Reg. Hold Time after Clock 0.0 – 0.0 – ns A 12 Ext. Reset Pin to Output Delay, ORP Bypass – 13 Ext. Reset Pulse Duration – 9.0 – 12.5 ns 5.0 – 6.5 – ns B 14 Input to Output Enable – 12.0 – 15.0 ns C 15 Input to Output Disable – 12.0 – 15.0 ns B 16 Global OE Output Enable – 7.0 – 9.0 ns C 17 Global OE Output Disable – 7.0 – 9.0 ns – 18 External Synchronous Clock Pulse Duration, High 3.5 – 5.0 – ns – 19 External Synchronous Clock Pulse Duration, Low 3.5 – 5.0 – ns 1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock. 2. Standard 16-bit counter using GRP feedback. 3. Reference Switching Test Conditions section. 6 Table 2-0030B/2096VE v.1.0 Specifications ispLSI 2096VE Internal Timing Parameters1 Over Recommended Operating Conditions PARAMETER 2 # DESCRIPTION -200 -250 MIN. MAX. MIN. MAX. UNITS Inputs – 0.5 – 0.5 ns 21 Dedicated Input Delay – 0.7 – 1.1 ns 22 GRP Delay – 0.2 – 23 4 Product Term Bypass Path Delay (Combinatorial) – 1.5 – 24 4 Product Term Bypass Path Delay (Registered) – 2.0 – 25 1 Product Term/XOR Path Delay – 2.8 – 26 20 Product Term/XOR Path Delay – 2.8 – – 2.8 – – 0.0 – 29 GLB Register Setup Time before Clock 0.8 – 30 GLB Register Hold Time after Clock 1.7 31 GLB Register Clock to Output Delay EW DESIGNS 20 Input Buffer Delay 1.4 ns 1.9 ns 2.9 ns 2.9 ns 2.9 ns 0.0 ns 1.2 – ns – 1.8 – ns – 0.2 – 0.3 ns 32 GLB Register Reset to Output Delay – 0.3 – 0.4 ns 33 GLB Product Term Reset to Register Delay – 3.7 – 4.3 ns 34 GLB Product Term Output Enable to I/O Cell Delay – 2.9 – 3.9 ns 0.8 3.6 1.0 4.0 ns 36 ORP Delay – 1.1 – 1.5 ns 37 ORP Bypass Delay – 0.4 – 0.5 ns 38 Output Buffer Delay – 1.4 – 1.5 ns 39 Output Slew Limited Delay Adder – 2.0 – 2.0 ns 40 I/O Cell OE to Output Enabled – 2.4 – 3.0 ns 41 I/O Cell OE to Output Disabled – 2.4 – 3.0 ns 42 Global Output Enable – 1.6 USE ispLSI 209 tio tdin – 2.0 ns 43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) 1.0 1.0 1.2 1.2 ns 44 Clock Delay, Y1 or Y2 to Global GLB Clock Line 1.2 1.2 1.4 1.4 ns – 3.9 – 3.6 ns GRP tgrp t4ptbpc t4ptbpr t1ptxor t20ptxor txoradj tgbp tgsu tgh tgco tgro tptre tptoe tptck 27 XOR Adjacent Path Delay 3 28 GLB Register Bypass Delay 35 GLB Product Term Clock Delay ORP torp torpbp Outputs tob tsl toen todis tgoe Clocks tgy0 tgy1/2 6VE-250 FOR N GLB 0.6 ns Global Reset tgr 45 Global Reset to GLB 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros. 7 Table 2-0036A/2096VE v.1.0 Specifications ispLSI 2096VE Internal Timing Parameters1 Over Recommended Operating Conditions PARAMETER 2 # DESCRIPTION -100 -135 MIN. MAX. MIN. MAX. UNITS Inputs tio tdin 20 Input Buffer Delay – 0.5 – 0.7 ns 21 Dedicated Input Delay – 1.7 – 2.5 ns 22 GRP Delay – 1.2 – 1.8 ns 23 4 Product Term Bypass Path Delay (Combinatorial) – 3.7 – 5.2 ns 24 4 Product Term Bypass Path Delay (Registered) – 3.7 – 4.7 ns 25 1 Product Term/XOR Path Delay – 4.7 – 6.2 ns 26 20 Product Term/XOR Path Delay – 4.7 – 6.2 ns – 4.7 – 6.2 ns – 0.5 – 1.0 ns 29 GLB Register Setup Time before Clock 1.2 – 1.7 – ns 30 GLB Register Hold Time after Clock 3.8 – 4.8 – ns 31 GLB Register Clock to Output Delay – 0.3 – 0.3 ns 32 GLB Register Reset to Output Delay – 1.1 – 3.1 ns 33 GLB Product Term Reset to Register Delay – 6.1 – 7.1 ns 34 GLB Product Term Output Enable to I/O Cell Delay – 6.9 – 9.1 ns 1.6 5.0 2.6 5.6 ns 36 ORP Delay – 1.5 – 1.7 ns 37 ORP Bypass Delay – 0.5 – 0.7 ns 38 Output Buffer Delay – 1.6 – 1.6 ns 39 Output Slew Limited Delay Adder – 2.0 – 2.0 ns 40 I/O Cell OE to Output Enabled – 3.4 – 3.4 ns 41 I/O Cell OE to Output Disabled – 3.4 – 3.4 ns 42 Global Output Enable – 3.6 – 5.6 ns 43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) 1.6 1.6 2.4 2.4 ns 44 Clock Delay, Y1 or Y2 to Global GLB Clock Line 1.8 1.8 2.6 2.6 ns – 5.8 – 7.1 ns GRP tgrp GLB t4ptbpc t4ptbpr t1ptxor t20ptxor txoradj tgbp tgsu tgh tgco tgro tptre tptoe tptck 27 XOR Adjacent Path Delay 3 28 GLB Register Bypass Delay 35 GLB Product Term Clock Delay ORP torp torpbp Outputs tob tsl toen todis tgoe Clocks tgy0 tgy1/2 Global Reset tgr 45 Global Reset to GLB 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros. 8 Table 2-0036B/2096VE v.1.0 Specifications ispLSI 2096VE ispLSI 2096VE Timing Model I/O Cell GRP GLB ORP I/O Cell Feedback Ded. In I/O Pin (Input) Comb 4 PT Bypass #23 #21 I/O Delay GRP Reg 4 PT Bypass GLB Reg Bypass ORP Bypass #20 #22 #24 #28 #37 20 PT XOR Delays GLB Reg Delay ORP Delay #25, 26, 27 D Q #38, 39 #36 RST Reset #45 #29, 30, 31, 32 Control RE PTs OE #33, 34, CK 35 Y0,1,2 GOE 0 #40, 41 #43, 44 #42 0491/2032 Derivations of tsu, th and tco from the Product Term Clock tsu = = = 2.8ns = Logic + Reg su - Clock (min) (tio + tgrp + t20ptxor) + (tgsu) - (tio + tgrp + tptck(min)) (#20 + #22 + #26) + (#29) - (#20 + #22 + #35) (0.5 + 0.2 + 2.8) + (0.8) - (0.5 + 0.2 + 0.8) th = = = 2.5ns = Clock (max) + Reg h - Logic (tio + tgrp + tptck(max)) + (tgh) - (tio + tgrp + t20ptxor) (#20 + #22 + #35) + (#30) - (#20 + #22 + #26) (0.5 + 0.2 + 3.6) + (1.7) - (0.5 + 0.2 + 2.8) tco = = = 7.0ns = Clock (max) + Reg co + Output (tio + tgrp + tptck(max)) + (tgco) + (torp + tob) (#20 + #22 + #35) + (#31) + (#36 + #38) (0.5 + 0.2 + 3.6) + (0.2) + (1.1 + 1.4) Note: Calculations are based upon timing specifications for the ispLSI 2096VE-250L. Table 2-0042/2096VE 9 I/O Pin (Output) Specifications ispLSI 2096VE Power Consumption used. Figure 3 shows the relationship between power and operating speed. Power consumption in the ispLSI 2096VE device depends on two primary factors: the speed at which the device is operating and the number of Product Terms Figure 3. Typical Device Power Consumption vs fmax 260 ispLSI 2096VE 240 220 ICC (mA) 200 180 160 140 120 0 50 100 150 200 250 fmax (MHz) Notes: Configuration of six 16-bit counters Typical current at 3.3V, 25° C ICC can be estimated for the ispLSI 2096VE using the following equation: ICC (mA) = 8.0 + (# of PTs * 0.63) + (# of Nets * Fmax * 0.005) Where: # of PTs = Number of Product Terms used in design # of nets = Number of Signals used in device Max freq = Highest Clock Frequency to the device (in MHz) The ICC estimate is based on typical conditions (VCC = 3.3V, room temperature) and an assumption of two GLB loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the program in the device, the actual ICC should be verified. 0127/2096VE 10 Specifications ispLSI 2096VE Pin Description NAME TQFP PIN NUMBERS 23, 29, 37, 43, 53, 59, 67, 73, 87, 93, 101, 107, 117, 123, 3, 9, 24, 30, 38, 44, 54, 60, 68, 74, 88, 94, 102, 108, 118, 124, 4, 10, 25, 32, 39, 45, 55, 61, 69, 75, 89, 96, 103, 109, 119, 125, 5, 11, DESCRIPTION 26 33 40 46 56 62 70 76 90 97 104 110 120 126 6 12 Input/Output Pins - These are the general purpose I/O pins used by the logic array. I/O 0 - I/O 5 I/O 6 - I/O 11 I/O 12 - I/O 17 I/O 18 - I/O 23 I/O 24 - I/O 29 I/O 30 - I/O 35 I/O 36 - I/O 41 I/O 42 - I/O 47 I/O 48 - I/O 53 I/O 54 - I/O 59 I/O 60 - I/O 65 I/O 66 - I/O 71 I/O 72 - I/O 77 I/O 78 - I/O 83 I/O 84 - I/O 89 I/O 90 - I/O 95 21, 27, 35, 41, 51, 57, 64, 71, 85, 91, 99, 105, 115, 121, 128, 7, 22, 28, 36, 42, 52, 58, 65, 72, 86, 92, 100, 106, 116, 122, 1, 8, GOE 0, GOE 1 80, 17 Global Output Enables input pins. IN 4, IN 5 84, 113 Dedicated input pins to the device. BSCAN 19 Input — Dedicated in-system programming Boundary Scan enable input pin. This pin is brought low to enable the programming mode. The TMS, TDI, TDO and TCK controls become active. TDI/IN 0 20 TMS/IN 1 48 TDO/IN 2 112 TCK/IN 3 77 Input — This pin performs two functions. When BSCAN is logic low, it functions as a serial data input pin to load programming data into the device. When BSCAN is high, it functions as a dedicated input pin. Input — This pin performs two functions. When BSCAN is logic low, it functions as a mode control pin for the Boundary Scan state machine. When BSCAN is high, it functions as a dedicated input pin. Output/Input — This pin performs two functions. When BSCAN is logic low, it functions as an output pin to read serial shift register data. When BSCAN is high, it functions as a dedicated input pin. Input — This pin performs two functions. When BSCAN is logic low, it functions as a clock pin for the Boundary Scan state machine. When BSCAN is high, it functions as a dedicated input pin. RESET 15 Y0, Y1, Y2 14 83, 78 GND 18, 111, 34, 127 50, 63, 79, 98, Ground (GND) VCC 2, 95, 16, 114 31, 47, 66, 81, VCC NC1 13, 49, 82 Active Low (0) Reset pin which resets all of the registers in the device. Dedicated Clock input. This clock input is connected to one of the clock inputs of all the GLBs on the device. No Connect. 1. NC pins are not to be connected to any active signal, VCC or GND. 11 Table 2-0002-2096VE Specifications ispLSI 2096VE Pin Configuration 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 I/O 84 GND I/O 83 I/O 82 I/O 81 I/O 80 I/O 79 I/O 78 I/O 77 I/O 76 I/O 75 I/O 74 I/O 73 I/O 72 VCC IN 5 TDO/IN 2 GND I/O 71 I/O 70 I/O 69 I/O 68 I/O 67 I/O 66 I/O 65 I/O 64 I/O 63 I/O 62 I/O 61 I/O 60 GND I/O 59 ispLSI 2096VE 128-Pin TQFP Pinout Diagram (0.4mm Lead Pitch/14.0 x 14.0mm Body Size) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ispLSI 2096VE Top View 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 I/O 58 VCC I/O 57 I/O 56 I/O 55 I/O 54 I/O 53 I/O 52 I/O 51 I/O 50 I/O 49 I/O 48 IN 4 Y1 NC1 VCC GOE 0 GND Y2 TCK/IN 3 I/O 47 I/O 46 I/O 45 I/O 44 I/O 43 I/O 42 I/O 41 I/O 40 I/O 39 I/O 38 VCC I/O 37 I/O 11 GND I/O 12 I/O 13 I/O 14 I/O 15 I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 VCC TMS/IN 1 1NC GND I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 I/O 32 I/O 33 I/O 34 I/O 35 GND I/O 36 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 I/O 85 VCC I/O 86 I/O 87 I/O 88 I/O 89 I/O 90 I/O 91 I/O 92 I/O 93 I/O 94 I/O 95 1NC Y0 RESET VCC GOE 1 GND BSCAN TDI/IN 0 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 VCC I/O 10 1. NC pins are not to be connected to any active signals, VCC or GND. 12 0124-2096VE Specifications ispLSI 2096VE Part Number Description ispLSI 2096VE – XX X XXXXX X Device Family Grade Blank = Commercial I = Industrial Package T128 = 128-Pin TQFP TN128 = Lead-Free 128-Pin TQFP Power L = Low Device Number Speed 250 = 250 MHz fmax 200 = 200 MHz fmax* 135 = 135 MHz fmax 100 = 100 MHz fmax 0212/2096VE *Use ispLSI 2096VE-250 for new designs ispLSI 2096VE Ordering Information Conventional Packaging COMMERCIAL FAMILY ispLSI fmax (MHz) tpd (ns) ORDERING NUMBER PACKAGE 250 4.0 ispLSI 2096VE-250LT128 128-Pin TQFP 200 4.5 ispLSI 2096VE-200LT128* 128-Pin TQFP 135 7.5 ispLSI 2096VE-135LT128 128-Pin TQFP 100 10 ispLSI 2096VE-100LT128 128-Pin TQFP Table 2-0041A/2096VE *Use ispLSI 2096VE-250 for new designs INDUSTRIAL FAMILY fmax (MHz) tpd (ns) ORDERING NUMBER PACKAGE ispLSI 135 7.5 ispLSI 2096VE-135LT128I 128-Pin TQFP Table 2-0041B/2096VE Lead-Free Packaging COMMERCIAL FAMILY ispLSI fmax (MHz) tpd (ns) ORDERING NUMBER PACKAGE 250 135 4.0 ispLSI 2096VE-250LTN128 Lead-Free 128-Pin TQFP 7.5 ispLSI 2096VE-135LTN128 Lead-Free 128-Pin TQFP 100 10 ispLSI 2096VE-100LTN128 Lead-Free 128-Pin TQFP INDUSTRIAL FAMILY fmax (MHz) tpd (ns) ORDERING NUMBER PACKAGE ispLSI 135 7.5 ispLSI 2096VE-135LTN128I Lead-Free 128-Pin TQFP 13