ISPLSI2192VE-180LT128

LeadFree Package Options Available! 3.3V In-System Programmable SuperFAST™ High Density PLD Functional Block Diagram Output Routing Pool Output Routing Pool F7 F6 F5 F4 F3 F2 F1 F0 E7 E6 E5 E4 E3 E2 E1 E0 D7 Output Routing Pool A0 D Q A1 A2 A3 A4 Logic Global Routing Pool (GRP) Array D6 D5 D Q D Q GLB 2 D3 D2 A5 D Q A6 D1 A7 • 3.3V LOW VOLTAGE ARCHITECTURE — Interfaces with Standard 5V TTL Devices D4 Output Routing Pool • SuperFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC — 8000 PLD Gates — 96 I/O Pins, Nine or Twelve Dedicated Inputs — 192 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic — Pinout Compatible with ispLSI 2096V and 2096VE D0 B0 B1 B2 B3 B4 B5 B6 B7 C0 C1 C2 C3 C4 C5 C6 C7 Output Routing Pool Output Routing Pool CLK0 CLK1 CLK2 Features ® ispLSI 2192VE ® • HIGH PERFORMANCE E CMOS TECHNOLOGY — fmax = 225MHz Maximum Operating Frequency — tpd = 4.0ns Propagation Delay — Electrically Erasable and Reprogrammable — Non-Volatile — 100% Tested at Time of Manufacture — Unused Product Term Shutdown Saves Power 0139/2192VE Description The ispLSI 2192VE is a High Density Programmable Logic Device containing 192 Registers, nine or twelve Dedicated Input pins, three Dedicated Clock Input pins, two dedicated Global OE input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2192VE features in-system programmability through the Boundary Scan Test Access Port (TAP) and is 100% IEEE 1149.1 Boundary Scan Testable. The ispLSI 2192VE offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. • IN-SYSTEM PROGRAMMABLE — 3.3V In-System Programmability (ISP™) Using Boundary Scan Test Access Port (TAP) — Open-Drain Output Option for Flexible Bus Interface Capability, Allowing Easy Implementation of WiredOR Bus Arbitration Logic — Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality — Reprogram Soldered Devices for Faster Prototyping • 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE The basic unit of logic on the ispLSI 2192VE device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1 .. F7 (see Figure 1). There are a total of 48 GLBs in the ispLSI 2192VE device. Each GLB is made up of four macrocells. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device. • THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS — Enhanced Pin Locking Capability — Three Dedicated Clock Input Pins — Synchronous and Asynchronous Clocks — Programmable Output Slew Rate Control — Flexible Pin Placement — Optimized Global Routing Pool Provides Global Interconnectivity • LEAD-FREE PACKAGE OPTIONS Copyright © 2004 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com 2192ve_10 1 August 2004 Specifications ispLSI 2192VE Functional Block Diagram Figure 1. ispLSI 2192VE Functional Block Diagram I/O I/O I/O I/O 95 94 93 92 I/O I/O I/O I/O 91 90 89 88 I/O I/O I/O I/O 87 86 85 84 IN IN 11* 10 I/O I/O I/O I/O 83 82 81 80 I/O I/O I/O I/O 79 78 77 76 I/O I/O I/O I/O 75 74 73 72 I/O I/O I/O I/O 71 70 69 68 I/O I/O I/O I/O 67 66 65 64 IN 9 IN 8 RESET Input Bus Input Bus Output Routing Pool (ORP) Output Routing Pool (ORP) GOE 0 Generic Logic Blocks (GLBs) GOE 1 F7 F6 F5 F4 F3 F2 F1 F0 E7 E6 E5 E4 E3 E2 E1 IN 7/TCK IN 6/TDO E0 I/O 63 I/O 62 I/O 61 D7 I/O 12 I/O 13 I/O 14 I/O 15 I/O 60 D5 Global Routing Pool (GRP) A2 A3 A4 D4 D3 D2 A5 D1 A6 D0 I/O 59 I/O 58 I/O 57 lnput Bus Input Bus I/O 56 I/O 55 I/O 54 I/O 53 I/O 52 I/O 51 I/O 50 I/O 49 I/O 48 B0 B1 B2 B3 B4 B5 B6 B7 C0 C1 C2 C3 C4 C5 Output Routing Pool (ORP) Output Routing Pool (ORP) Input Bus Input Bus C6 C7 CLK 2 TDI/IN 0 TMS/IN 1 CLK 1 A7 CLK 0 I/O 8 I/O 9 I/O 10 I/O 11 D6 A1 Output Routing Pool (ORP) I/O 4 I/O 5 I/O 6 I/O 7 A0 Output Routing Pool (ORP) I/O 0 I/O 1 I/O 2 I/O 3 Megablock BSCAN IN 2* IN 3 I/O I/O I/O I/O 16 17 18 19 I/O I/O I/O I/O 20 21 22 23 I/O I/O I/O I/O 24 25 26 27 I/O I/O I/O I/O 28 29 30 31 IN4 IN 5* I/O I/O I/O I/O 32 33 34 35 I/O I/O I/O I/O 36 37 38 39 I/O I/O I/O I/O 40 41 42 43 I/O I/O I/O I/O 44 45 46 47 *Note: Dedicated Inputs 2, 5 and 11 are not available with 128-pin packages. Y0 Y1 Y2 2192VE Block.eps The 2192VE contains 96 I/O cells. Each I/O cell is directly connected to an I/O pin and can be individually programmed to be a combinatorial input, output or bi-directional I/O pin with 3-state control. The signal levels are TTL compatible voltages and the output drivers can source 4mA or sink 8mA. Each output can be programmed independently for fast or slow output slew rate to minimize overall output switching noise. Device pins can be safely driven to 5V signal levels to support mixed-voltage systems. Clocks in the ispLSI 2192VE device are selected using the dedicated clock pins. Three dedicated clock pins (Y0, Y1, Y2) or an asynchronous clock can be selected on a GLB basis. The asynchronous or Product Term clock can be generated in any GLB for its own clock. Programmable Open-Drain Outputs In addition to the standard output configuration, the outputs of the ispLSI 2192VE are individually programmable, either as a standard totem-pole output or an open-drain output. The totem-pole output drives the specified Voh and Vol levels, whereas the open-drain output drives only the specified Vol. The Voh level on the open-drain output depends on the external loading and pull-up. This output configuration is controlled by a programmable fuse. The default configuration when the device is in bulk erased state is totem-pole configuration. The open-drain/totem-pole option is selectable through the Lattice software tools. Eight GLBs, 16 I/O cells, two dedicated inputs and an ORP are connected together to make a Megablock (see Figure 1). The outputs of the eight GLBs are connected to a set of 16 universal I/O cells by the ORP. Each ispLSI 2192VE device contains six Megablocks. The GRP has as its inputs, the outputs from all of the GLBs and all of the inputs from the bi-directional I/O cells. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew. 2 Specifications ispLSI 2192VE Absolute Maximum Ratings 1 Supply Voltage Vcc .................................. -0.5 to +5.4V Input Voltage Applied ............................... -0.5 to +5.6V Off-State Output Voltage Applied ............ -0.5 to +5.6V Storage Temperature ................................ -65 to 150°C Case Temp. with Power Applied .............. -55 to 125°C Max. Junction Temp. (TJ) with Power Applied ... 150°C 1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). DC Recommended Operating Condition PARAMETER SYMBOL VCC VIL VIH Supply Voltage Commercial TA = 0°C to + 70°C Input Low Voltage MIN. MAX. UNITS 3.0 3.6 V 0.8 V 5.25 V VSS – 0.5 Input High Voltage 2.0 Table 2-0005/2192VE Capacitance (TA=25°C, f=1.0 MHz) TYPICAL UNITS Dedicated Input Capacitance 8 pf VCC = 3.3V, VIN = 0.0V I/O Capacitance 8 pf VCC = 3.3V, VI/O = 0.0V Clock and Global Output Enable Capacitance 12 pf VCC = 3.3V, VY = 0.0V SYMBOL C1 C2 C3 PARAMETER TEST CONDITIONS Table 2-0006/2192VE Erase Reprogram Specifications PARAMETER MINIMUM MAXIMUM UNITS 10,000 — Cycles Erase/Reprogram Cycles Table 2-0008/2192VE 3 Specifications ispLSI 2192VE Switching Test Conditions Input Pulse Levels Figure 2. Test Load GND to 3.0V Input Rise and Fall Time ≤ 1.5ns 10% to 90% Input Timing Reference Levels 1.5V Output Timing Reference Levels 1.5V Output Load + 3.3V R1 See Figure 2 Device Output 3-state levels are measured 0.5V from steady-state active level. Test Point Table 2-0003/2192VE R2 CL* Output Load Conditions (see Figure 2) TEST CONDITION A B C R1 R2 CL 316Ω 348Ω 35pF Active High ∞ 348Ω 35pF Active Low 316Ω 348Ω 35pF Active High to Z at VOH -0.5V ∞ 348Ω 5pF Active Low to Z at VOL +0.5V 316Ω 348Ω 5pF *CL includes Test Fixture and Probe Capacitance. 0213A/2192VE Table 2-0004/2192VE DC Electrical Characteristics Over Recommended Operating Conditions SYMBOL PARAMETER CONDITION 3 MIN. TYP. MAX. UNITS VOL VOH IIL Output Low Voltage IOL= 8 mA – – 0.4 V Output High Voltage IOH = -4 mA 2.4 – – V Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (Max.) – – -10 µA IIH Input or I/O High Leakage Current (VCC - 0.2)V ≤ VIN ≤ VCC – – 10 µA VCC ≤ VIN ≤ 5.25V – – 10 µA IIL-isp IIL-PU IOS1 BSCAN Input Low Leakage Current 0V ≤ VIN ≤ VIL – – -150 µA I/O Active Pull-Up Current 0V ≤ VIN ≤ VIL – – -150 µA Output Short Circuit Current VCC = 3.3V, VOUT = 0.5V – – -100 mA ICC2, 4 Operating Power Supply Current VIL = 0.0V, VIH = 3.0V – 275 – mA fCLOCK = 1 MHz Table 2-0007/2192VE 1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test problems by tester ground degradation. Characterized but not 100% tested. 2. Measured using twelve 16-bit counters. 3. Typical values are at VCC = 3.3V and TA= 25°C. 4. Maximum I CC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum ICC . 4 Specifications ispLSI 2192VE External Timing Parameters Over Recommended Operating Conditions 3 tpd1 tpd2 fmax fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 tco2 th2 tr1 trw1 tptoeen tptoedis tgoeen tgoedis twh twl -225 TEST COND. # A 1 Data Propagation Delay, 4PT Bypass, ORP Bypass A 2 Data Propagation Delay A 3 Clock Frequency with Internal Feedback – 4 – – DESCRIPTION 1 -180 MIN. MAX. MIN. MAX. – 4.0 – 6.2 225 – Clock Frequency with External Feedback ( tsu2 + tco1) 150 – 5 Clock Frequency, Max. Toggle 250 – 6 GLB Reg. Setup Time before Clock, 4 PT Bypass 2.5 – A 7 GLB Reg. Clock to Output Delay, ORP Bypass – 3.2 – 8 GLB Reg. Hold Time after Clock, 4 PT Bypass 0.0 – – 9 GLB Reg. Setup Time before Clock 3.5 – A 10 GLB Reg. Clock to Output Delay – 3.7 – 11 GLB Reg. Hold Time after Clock 0.0 – A 12 Ext. Reset Pin to Output Delay, ORP Bypass – 13 Ext. Reset Pulse Duration 2 1 – 6.0 3.5 – B 14 Input to Output Enable – 6.0 C 15 Input to Output Disable – 6.0 B 16 Global OE Output Enable – 4.5 – 5.0 UNITS ns – 7.5 ns 180 – MHz 125 – MHz 200 – MHz 3.5 – ns USE 2192VE-2 25 FOR NEW DESIGNS PARAMETER – 3.5 ns 0.0 – ns 4.5 – ns – 4.5 ns 0.0 – ns – 7.0 ns 4.0 – ns – 10.0 ns – 10.0 ns – 5.0 ns C 17 Global OE Output Disable – 4.5 – 5.0 ns – 18 External Synchronous Clock Pulse Duration, High 2.0 – 2.5 – ns – 19 External Synchronous Clock Pulse Duration, Low 2.0 – 2.5 – ns 1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock. 2. Standard 16-bit counter using GRP feedback. 3. Reference Switching Test Conditions section. 5 Table 2-0030A/2192VE Specifications ispLSI 2192VE External Timing Parameters Over Recommended Operating Conditions 3 PARAMETER tpd1 tpd2 fmax fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 tco2 th2 tr1 trw1 tptoeen tptoedis tgoeen tgoedis twh twl -135 TEST COND. # A 1 Data Propagation Delay, 4PT Bypass, ORP Bypass A 2 Data Propagation Delay A 3 Clock Frequency with Internal Feedback – 4 – – DESCRIPTION 1 -100 MIN. MAX. MIN. MAX. – 7.5 – 10.0 UNITS ns – 10.0 – 13.0 ns 135 – 100 – MHz Clock Frequency with External Feedback ( tsu2 + tco1) 100 – 77 – MHz 5 Clock Frequency, Max. Toggle 143 – 100 – MHz 6 GLB Reg. Setup Time before Clock, 4 PT Bypass 5.0 – 6.5 – ns A 7 GLB Reg. Clock to Output Delay, ORP Bypass – 4.0 – 5.0 ns – 8 GLB Reg. Hold Time after Clock, 4 PT Bypass 0.0 – 0.0 – ns – 9 GLB Reg. Setup Time before Clock 6.0 – 8.0 – ns A 10 GLB Reg. Clock to Output Delay – 5.0 – 6.0 ns – 11 GLB Reg. Hold Time after Clock 0.0 – 0.0 – ns A 12 Ext. Reset Pin to Output Delay, ORP Bypass – 13 Ext. Reset Pulse Duration 2 1 – 9.0 – 12.5 ns 5.0 – 6.5 – ns B 14 Input to Output Enable – 12.0 – 15.0 ns C 15 Input to Output Disable – 12.0 – 15.0 ns B 16 Global OE Output Enable – 7.0 – 9.0 ns C 17 Global OE Output Disable – 7.0 – 9.0 ns – 18 External Synchronous Clock Pulse Duration, High 3.5 – 5.0 – ns – 19 External Synchronous Clock Pulse Duration, Low 3.5 – 5.0 – ns 1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock. 2. Standard 16-bit counter using GRP feedback. 3. Reference Switching Test Conditions section. 6 Table 2-0030B/2192VE Specifications ispLSI 2192VE Internal Timing Parameters1 Over Recommended Operating Conditions PARAMETER 2 # -180 -225 DESCRIPTION MIN. MAX. MIN. MAX. UNITS Inputs tio tdin 20 Input Buffer Delay – 0.3 – 0.5 ns 21 Dedicated Input Delay – 0.5 – 1.1 ns 22 GRP Delay – 0.2 – 0.6 ns 23 4 Product Term Bypass Path Delay (Combinatorial) – 1.5 – 1.9 24 4 Product Term Bypass Path Delay (Registered) – 2.2 – 2.4 ns 25 1 Product Term/XOR Path Delay – 3.2 – 3.4 ns tgrp ns 3.4 ns 0.0 ns – 3.2 – 27 XOR Adjacent Path Delay 3 – 3.2 – 28 GLB Register Bypass Delay – 0.0 – 29 GLB Register Setup Time before Clock 0.7 – 1.2 – ns 30 GLB Register Hold Time after Clock 1.8 – 2.3 – ns 31 GLB Register Clock to Output Delay – 0.3 – 0.3 ns 32 GLB Register Reset to Output Delay – 0.3 – 0.6 ns 33 GLB Product Term Reset to Register Delay – 4.0 – 4.3 ns – 5.9 ns – 2.9 0.8 3.2 1.0 4.0 ns 36 ORP Delay – 0.9 – 1.4 ns 37 ORP Bypass Delay – 0.4 – 0.4 ns 38 Output Buffer Delay – 1.6 – 1.6 ns 39 Output Slew Limited Delay Adder – 2.0 – 2.0 ns 40 I/O Cell OE to Output Enabled – 2.6 – 3.0 ns 41 I/O Cell OE to Output Disabled – 2.6 – 3.0 ns 42 Global Output Enable – 1.9 – 2.0 ns 43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) 0.9 0.9 1.2 1.2 ns 44 Clock Delay, Y1 or Y2 to Global GLB Clock Line 1.1 1.1 1.4 1.4 ns – 3.7 – 4.4 ns 34 GLB Product Term Output Enable to I/O Cell Delay 35 GLB Product Term Clock Delay Outputs tob tsl toen todis tgoe 3.4 26 20 Product Term/XOR Path Delay ORP torp torpbp ns USE 2192VE-2 t4ptbpc t4ptbpr t1ptxor t20ptxor txoradj tgbp tgsu tgh tgco tgro tptre tptoe tptck 25 FOR NEW D GLB ESIGNS GRP Clocks tgy0 tgy1/2 Global Reset tgr 45 Global Reset to GLB 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros. 7 Table 2-0036E/2192VE v0.1 Specifications ispLSI 2192VE Internal Timing Parameters1 Over Recommended Operating Conditions PARAMETER 2 # -100 -135 DESCRIPTION MIN. MAX. MIN. MAX. UNITS Inputs tio tdin 20 Input Buffer Delay – 0.5 – 0.7 ns 21 Dedicated Input Delay – 1.7 – 2.5 ns 22 GRP Delay – 1.2 – 1.8 ns 23 4 Product Term Bypass Path Delay (Combinatorial) – 3.7 – 5.2 ns 24 4 Product Term Bypass Path Delay (Registered) – 3.7 – 4.7 ns 25 1 Product Term/XOR Path Delay – 4.7 – 6.2 ns 26 20 Product Term/XOR Path Delay – 4.7 – 6.2 ns – 4.7 – 6.2 ns – 0.5 – 1.0 ns 29 GLB Register Setup Time before Clock 1.2 – 1.7 – ns 30 GLB Register Hold Time after Clock 3.8 – 4.8 – ns 31 GLB Register Clock to Output Delay – 0.3 – 0.3 ns 32 GLB Register Reset to Output Delay – 1.1 – 3.1 ns 33 GLB Product Term Reset to Register Delay – 6.1 – 7.1 ns 34 GLB Product Term Output Enable to I/O Cell Delay – 6.9 – 9.1 ns 1.6 4.6 2.6 5.6 ns 36 ORP Delay – 1.5 – 1.7 ns 37 ORP Bypass Delay – 0.5 – 0.7 ns 38 Output Buffer Delay – 1.6 – 1.6 ns 39 Output Slew Limited Delay Adder – 2.0 – 2.0 ns 40 I/O Cell OE to Output Enabled – 3.4 – 3.4 ns 41 I/O Cell OE to Output Disabled – 3.4 – 3.4 ns 42 Global Output Enable – 3.6 – 5.6 ns 43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) 1.6 1.6 2.4 2.4 ns 44 Clock Delay, Y1 or Y2 to Global GLB Clock Line 1.8 1.8 2.6 2.6 ns – 5.8 – 7.1 ns GRP tgrp GLB t4ptbpc t4ptbpr t1ptxor t20ptxor txoradj tgbp tgsu tgh tgco tgro tptre tptoe tptck 27 XOR Adjacent Path Delay 3 28 GLB Register Bypass Delay 35 GLB Product Term Clock Delay ORP torp torpbp Outputs tob tsl toen todis tgoe Clocks tgy0 tgy1/2 Global Reset tgr 45 Global Reset to GLB 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros. 8 Table 2-0036D/2192VE v0.1 Specifications ispLSI 2192VE ispLSI 2192VE Timing Model I/O Cell GRP GLB ORP I/O Cell Feedback Ded. In I/O Pin (Input) Comb 4 PT Bypass #23 #21 I/O Delay GRP Reg 4 PT Bypass GLB Reg Bypass ORP Bypass #20 #22 #24 #28 #37 20 PT XOR Delays GLB Reg Delay ORP Delay #25, 26, 27 D Q #38, 39 #36 RST Reset #45 #29, 30, 31, 32 Control RE PTs OE #33, 34, CK 35 Y0,1,2 GOE 0 #40, 41 #43, 44 #42 0491/2192VE Derivations of tsu, th and tco from the Product Term Clock tsu = = = 3.1ns = Logic + Reg su - Clock (min) (tio + tgrp + t20ptxor) + (tgsu) - (tio + tgrp + tptck(min)) (#20 + #22 + #26) + (#29) - (#20 + #22 + #35) (0.3 + 0.2 + 3.2) + (0.7) - (0.3 + 0.2 + 0.8) th = = = 1.8ns = Clock (max) + Reg h - Logic (tio + tgrp + tptck(max)) + (tgh) - (tio + tgrp + t20ptxor) (#20 + #22 + #35) + (#30) - (#20 + #22 + #26) (0.3 + 0.2 + 3.2) + (1.8) - (0.3 + 0.2 + 3.2) tco = = = 6.5ns = Clock (max) + Reg co + Output (tio + tgrp + tptck(max)) + (tgco) + (torp + tob) (#20 + #22 + #35) + (#31) + (#36 + #38) (0.3 + 0.2 + 3.2) + (0.3) + (0.9 + 1.6) Note: Calculations are based upon timing specifications for the ispLSI 2192VE-225L. Table 2-0042A/2192VE v0.1 9 I/O Pin (Output) Specifications ispLSI 2192VE Power Consumption used. Figure 3 shows the relationship between power and operating speed. Power consumption in the ispLSI 2192VE device depends on two primary factors: the speed at which the device is operating and the number of Product Terms Figure 3. Typical Device Power Consumption vs fmax 500 ispLSI 2192VE ICC (mA) 450 400 350 300 250 0 40 80 120 160 200 240 fmax (MHz) Notes: Configuration of twelve 16-bit counters Typical current at 3.3V, 25° C ICC can be estimated for the ispLSI 2192VE using the following equation: ICC = 25 + (# of PTs * 0.670) + (# of nets * max freq * 0.0051) Where: # of PTs = Number of Product Terms used in design # of nets = Number of Signals used in device Max freq = Highest Clock Frequency to the device (in MHz) The ICC estimate is based on typical conditions (VCC = 3.3V, room temperature) and an assumption of two GLB loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the program in the device, the actual ICC should be verified. 0127/2192VE 10 Specifications ispLSI 2192VE Signal Descriptions Signal Name Description RESET Active Low (0) Reset pin resets all the registers in the device. GOE 0, GOE1 Global Output Enable input pins. Y0, Y1, Y2 Dedicated Clock Input – These clock inputs are connected to one of the clock inputs of all the GLBs in the device. BSCAN Input – Dedicated in-system programming Boundary Scan enable input pin. This pin is brought low to enable the programming mode. The TMS, TDI, TDO and TCK controls become active. TDI/IN 0 Input – This pin performs two functions. When BSCAN is logic low, it functions as a serial data input pin to load programming data into the device. When BSCAN is high, it functions as a dedicated input pin. TCK/IN 7 Input – This pin performs two functions. When BSCAN is logic low, it functions as a clock pin for the Boundary Scan state machine. When BSCAN is high, it functions as a dedicated input pin. TMS/IN 1 Input – This pin performs two functions. When BSCAN is logic low, it functions as a mode control pin for the Boundary Scan state machine. When BSCAN is high, it functions as a dedicated input pin. TDO/IN 6 Output/Input – This pin performs two functions. When BSCAN is logic low, it functions as an output pin to read serial shift register data. When BSCAN is high, it functions as a dedicated input pin. IN 2-5, IN 8-11 Dedicated Input Pins to the device. GND Ground (GND) VCC Vcc NC1 No Connect I/O Input/Output Pins – These are the general purpose I/O pins used by the logic array. 1. NC pins are not to be connected to any active signals, VCC or GND. Signal Locations Signal Name 128-Pin TQFP 144-Ball fpBGA RESET 15 G4 GOE 0, GOE 1 80, 17 F12, G2 Y0, Y1, Y2 14, 83, 78 F3, F10, G11 BSCAN 19 F1 TDI/IN 0 20 G3 TMS/IN 1 48 J6 TDO/IN 6 112 C7 TCK/IN 7 77 G12 IN 2-5, IN 8-11 —, 49, 82, —, 84, 113, 13, — M7, J7, F9, G10, E12, B6, F2, E1 GND 18, 34, 50, 63, 79, 98, 111, 127 A1, A12, D4, D9, E5, E8, F6, F7, G6, G7, H5, H8, J4, J9, M1, M12 VCC 2, 16, 31, 47, 66, 81, 95, 114 B1, B12, E6, E7, F5, F8, G5, G8, H6, H7, L1, L12 NC1 — K2 1. NC pins are not to be connected to any active signals, VCC or GND. 11 Specifications ispLSI 2192VE I/O Locations Signal 128 TQFP 144 fpBGA Signal 128 TQFP 144 fpBGA I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 I/O 32 I/O 33 I/O 34 I/O 35 I/O 36 I/O 37 I/O 38 I/O 39 I/O 40 I/O 41 I/O 42 I/O 43 I/O 44 I/O 45 I/O 46 I/O 47 21 22 23 24 25 26 27 28 29 30 32 33 35 36 37 38 39 40 41 42 43 44 45 46 51 52 53 54 55 56 57 58 59 60 61 62 64 65 67 68 69 70 71 72 73 74 75 76 H4 G1 H2 H1 H3 J1 J3 K1 J2 M2 L2 L3 K3 M3 L4 K4 M4 J5 M5 K5 L5 M6 L6 K6 L7 K7 J8 M8 L8 K8 M9 L9 K9 M10 L10 M11 K10 K11 L11 K12 J11 J12 J10 H9 H11 H12 H10 G9 I/O 48 I/O 49 I/O 50 I/O 51 I/O 52 I/O 53 I/O 54 I/O 55 I/O 56 I/O 57 I/O 58 I/O 59 I/O 60 I/O 61 I/O 62 I/O 63 I/O 64 I/O 65 I/O 66 I/O 67 I/O 68 I/O 69 I/O 70 I/O 71 I/O 72 I/O 73 I/O 74 I/O 75 I/O 76 I/O 77 I/O 78 I/O 79 I/O 80 I/O 81 I/O 82 I/O 83 I/O 84 I/O 85 I/O 86 I/O 87 I/O 88 I/O 89 I/O 90 I/O 91 I/O 92 I/O 93 I/O 94 I/O 95 85 86 87 88 89 90 91 92 93 94 96 97 99 100 101 102 103 104 105 106 107 108 109 110 115 116 117 118 119 120 121 122 123 124 125 126 128 1 3 4 5 6 7 8 9 10 11 12 F11 D12 E9 E10 E11 C12 D10 D11 B11 C11 C10 A11 B10 A10 C9 B9 A9 D8 B8 C8 A8 B7 A7 D7 C6 A6 D6 B5 C5 A5 D5 C4 B4 A4 C3 B3 A3 C2 B2 D2 A2 D3 E2 C1 E3 E4 D1 F4 12 Specifications ispLSI 2192VE Pin Configuration 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 I/O 84 GND I/O 83 I/O 82 I/O 81 I/O 80 I/O 79 I/O 78 I/O 77 I/O 76 I/O 75 I/O 74 I/O 73 I/O 72 VCC IN 9 TDO/IN 6 GND I/O 71 I/O 70 I/O 69 I/O 68 I/O 67 I/O 66 I/O 65 I/O 64 I/O 63 I/O 62 I/O 61 I/O 60 GND I/O 59 ispLSI 2192VE 128-Pin TQFP Pinout Diagram ispLSI 2192VE Top View 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 I/O 58 VCC I/O 57 I/O 56 I/O 55 I/O 54 I/O 53 I/O 52 I/O 51 I/O 50 I/O 49 I/O 48 IN 8 Y1 IN4 VCC GOE 0 GND Y2 TCK/IN 7 I/O 47 I/O 46 I/O 45 I/O 44 I/O 43 I/O 42 I/O 41 I/O 40 I/O 39 I/O 38 VCC I/O 37 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 I/O 11 GND I/O 12 I/O 13 I/O 14 I/O 15 I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 VCC TMS/IN 1 IN3 GND I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 I/O 32 I/O 33 I/O 34 I/O 35 GND I/O 36 I/O 85 VCC I/O 86 I/O 87 I/O 88 I/O 89 I/O 90 I/O 91 I/O 92 I/O 93 I/O 94 I/O 95 IN10 Y0 RESET VCC GOE 1 GND BSCAN TDI/IN 0 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 VCC I/O 10 0124-2192VE 13 Specifications ispLSI 2192VE Signal Configuration ispLSI 2192VE 144-Ball fpBGA Signal Diagram 12 11 10 9 8 7 6 5 4 3 2 1 A GND I/O 59 I/O 61 I/O 64 I/O 68 I/O 70 I/O 73 I/O 77 I/O 81 I/O 84 I/O 88 GND A B VCC I/O 56 I/O 60 I/O 63 I/O 66 I/O 69 IN 9 I/O 75 I/O 80 I/O 83 I/O 86 VCC B C I/O 53 I/O 57 I/O 58 I/O 62 I/O 67 TDO/ IN 6 I/O 72 I/O 76 I/O 79 I/O 82 I/O 85 I/O 91 C D I/O 49 I/O 55 I/O 54 GND I/O 65 I/O 71 I/O 74 I/O 78 GND I/O 89 I/O 87 I/O 94 D E IN 8 I/O 52 I/O 51 I/O 50 GND VCC VCC GND I/O 93 I/O 92 I/O 90 IN 11 E F GOE 0 I/O 48 Y1 IN 4 VCC GND GND VCC I/O 95 Y0 G TCK/ IN 7 Y2 IN 5 I/O 47 VCC GND GND VCC RESET TDI/ IN 0 GOE 1 I/O 1 G H I/O 45 I/O 44 I/O 46 I/O 43 GND VCC VCC GND I/O 0 I/O 4 I/O 2 I/O 3 H J I/O 41 I/O 40 I/O 42 GND I/O 26 IN 3 TMS/ IN 1 I/O 17 GND I/O 6 I/O 8 I/O 5 J K I/O 39 I/O 37 I/O 36 I/O 32 I/O 29 I/O 25 I/O 23 I/O 19 I/O 15 I/O 12 NC1 I/O 7 K L VCC I/O 38 I/O 34 I/O 31 I/O 28 I/O 24 I/O 22 I/O 20 I/O 14 I/O 11 I/O 10 VCC L M GND I/O 35 I/O 33 I/O 30 I/O 27 IN 2 I/O 21 I/O 18 I/O 16 I/O 13 I/O 9 GND M 12 11 10 9 8 7 6 5 4 3 2 IN 10 BSCAN 1 144-BGA/2192VE ispLSI 2192VE Bottom View 1NCs are not to be connected to any active signals, VCC or GND. Note: Ball A1 indicator dot on top side of package. 14 F Specifications ispLSI 2192VE Part Number Description ispLSI 2192VE - XXX X XXXXX X Device Family Grade Blank = Commercial I = Industrial Device Number Package T128 = 128-Pin TQFP TN128 = Lead-Free 128-Pin TQFP B144 = 144-Ball fpBGA Speed 225 = 225 MHz fmax 180 = 180 MHz fmax* 135 = 135 MHz fmax 100 = 100 MHz fmax Power L = Low *ispLSI 2192VE-225 recommended for new designs. 0212B/2192VE ispLSI 2192VE Ordering Information Conventional Packaging COMMERCIAL FAMILY ispLSI fmax (MHz) tpd (ns) ORDERING NUMBER PACKAGE 225 4.0 ispLSI 2192VE-225LT128 128-Pin TQFP 225 4.0 ispLSI 2192VE-225LB144 144-Ball fpBGA 180 5.0 ispLSI 2192VE-180LT128* 128-Pin TQFP 180 5.0 ispLSI 2192VE-180LB144* 144-Ball fpBGA 135 7.5 ispLSI 2192VE-135LT128 128-Pin TQFP 135 7.5 ispLSI 2192VE-135LB144 144-Ball fpBGA 100 10 ispLSI 2192VE-100LT128 128-Pin TQFP 100 10 ispLSI 2192VE-100LB144 144-Ball fpBGA Table 2-0041D/2192VE *ispLSI 2192VE-225 recommended for new designs. INDUSTRIAL FAMILY fmax (MHz) tpd (ns) ORDERING NUMBER PACKAGE ispLSI 180 5.0 ispLSI 2192VE-180LT128I 128-Pin TQFP Table 2-0041A/2192VE Lead-Free Packaging COMMERCIAL FAMILY fmax (MHz) tpd (ns) ORDERING NUMBER PACKAGE 225 4.0 ispLSI 2192VE-225LTN128 Lead-Free 128-Pin TQFP ispLSI 135 7.5 ispLSI 2192VE-135LTN128 Lead-Free 128-Pin TQFP 100 10 ispLSI 2192VE-100LTN128 Lead-Free 128-Pin TQFP INDUSTRIAL FAMILY fmax (MHz) tpd (ns) ORDERING NUMBER PACKAGE ispLSI 180 7.5 ispLSI 2192VE-180LTN128I Lead-Free 128-Pin TQFP 15