ISPPAC-CLK5406D-01SN48C

ispClock 5400D Family ™ In-System Programmable, Ultra-Low Jitter Zero Delay and Fan-Out Buffer, Differential December 2011 Preliminary Data Sheet DS1025  Up to 10 Programmable Fan-out Buffers Features • Programmable differential output standards and individual enable controls - LVDS, LVPECL, HSTL, SSTL, HCSL, MLVDS • Up to 10 banks with individual VCCO and GND - 1.5V, 1.8V, 2.5V, 3.3V CleanClock™ PLL  Ultra Low Period Jitter 2.5ps  Ultra Low Phase Jitter 6.5ps  Fully Integrated High-Performance PLL • • • • •  All I/Os are Hot Socket Compliant  Operating Modes Programmable lock detect Four output dividers Programmable on-chip loop filter Compatible with Spread Spectrum clocks Internal/external feedback • Fan-out buffer with programmable output skew control • Zero delay buffer with dual programmable skew controls  Flexible Clock Reference and External Feedback Inputs  Dynamic Reconfiguration through I2C  Full JTAG Boundary Scan Test In-System Programming Support  Exceptional Power Supply Noise Immunity  Commercial (0° to 70°C) and Industrial (-40° to 85°C) Temperature Ranges  48-Pin and 64-pin QFNS Packages  Applications • Programmable differential input reference/feedback standards - LVDS, LVPECL, HSTL, SSTL, HCSL, MLVDS • Programmable termination • Clock A/B selection multiplexer FlexiClock™ I/O  40 MHz to 400 MHz Input/Output Operation  Dual Programmable Skew Per Output • • • • Low-cost clock source for SERDES ATCA, MicroTCA, AMC, PCI Express Differential Clock Distribution Generic Source Synchronous Clock  Management • Zero-delay clock buffer • Programmable phase adjustment - 16 settings; minimum step size 156 ps - Up to +/- 9.4 ns skew range - Coarse and fine adjustment modes • Programmable time delay adjustment - 16 settings; 18 ps  Dynamic Skew Control Through I2C  Low Output-to-Output Skew (