ISPPAC-POWR605-01SN24I

TM ProcessorPM-POWR605 In-System Programmable Power Supply Supervisor, Reset Generator and Watchdog Timer April 2015 Data Sheet DS1034 Features Application Block Diagram  Precision Programmable Threshold Monitors, Threshold Accuracy 0.7% Input Power Supply • Simultaneously monitors up to six power supplies • Programmable analog trip points (1% step size; 192 steps) • Programmable glitch filter • Power-off detection (75 mV) DC-DC #1 DC-DC #2 DC-DC #n Manual Reset In Power Supply Bus  Embedded Programmable Timers • Four independent timers • 32 µs to 2 second intervals for timing sequences Voltage Supervisor  Embedded PLD for Logical Control • Rugged 16-macrocell CPLD architecture • 81 product terms / 28 inputs • Implements state machines and combinatorial functions Reset Generator Watchdog Timer  Power-Down Mode ICC < 10 µA  Digital I/O Interrupt – Power Fail CPU_Reset_in WDT Trigger Interrupt – WDT Power Down • Two dedicated digital inputs • Five programmable digital I/O pins ProcessorPMPOWR605  Wide Supply Range (2.64 V to 3.96 V) CPU / uProcessor Power Up/Down Control • In-system programmable through JTAG • Industrial temperature range: –40 °C to +105 °C • 24-pin QFN package, lead-free option The diagram above shows how a ProcessorPMPOWR605 is used in a typical application. It controls power to the microprocessor system, generates the CPU reset and monitors critical power supply voltages, generating interrupts whenever faults are detected. It also provides a watchdog timer function to detect CPU operating and bus timeout errors. Description Lattice’s Power Manager II ProcessorPM-POWR605 is a general-purpose power-supply monitor, reset generator and watchdog timer, incorporating both in-system programmable logic and analog functions implemented in non-volatile E2CMOS® technology. The ProcessorPM-POWR605 device provides six independent analog input channels to monitor power supply voltages. Two general-purpose digital inputs are also provided for miscellaneous control functions. The ProcessorPM-POWR605 incorporates a 16-macrocell CPLD. Figure 1 shows the analog input comparators and digital inputs used as inputs to the CPLD array. The digital output pins providing the external control signals are driven by the CPLD. Four independently programmable timers also interface with the CPLD and can create delays and time-outs ranging from 32 µs to 2 seconds. The CPLD is programmed using LogiBuilder™, an easy-to-learn language integrated into the PAC-Designer® software. Control sequences are written to monitor the status of any of the analog input channel comparators or the digital inputs. The ProcessorPM-POWR605 provides up to five open drain digital outputs that can be used for controlling DCDC converters, low-drop-out regulators (LDOs) and optocouplers, as well as for supervisory and general-purpose logic interface functions. The five digital, open drain outputs can optionally be configured as digital inputs to sense more input signals as needed, such as manual reset, etc. © 2015 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1 DS1034_2.0 ProcessorPM-POWR605 Data Sheet Figure 1. ProcessorPM-POWR605 Block Diagram VCC ProcessorPM-POWR605 Power Down Logic IN1_PWRDN IN2 IN_OUT1 PLD 6 Analog Voltage Monitor Inputs VMON1 16 Macrocells 4 Timers JTAG Interface VMON2 VMON3 VMON4 VMON5 VMON6 28 Inputs IN_OUT2 IN_OUT3 IN_OUT4 IN_OUT5 TMS TCK TDI TDO VCCJ GND Pin Descriptions Number Name 8, 9 GND 20 IN_OUT1 19 IN_OUT2 18 IN_OUT3 17 IN_OUT4 15 IN_OUT5 22 IN1_PWRDN Digital Input10 0 V to 5.5 V3 PLD Logic Input 1.4, 5 When not used, this pin should be pulled down with a 10k resistor. IN2 Digital Input10 0 V to 5.5 V3 PLD Logic Input 2. When not used, this pin should be tied to GND. 21 Pin Type Ground Digital Input9, 10 Open Drain Output2 Digital Input9, 10 Open Drain Output2 Digital Input9, 10 Open Drain Output2 Digital Input9, 10 Open Drain Output2 Digital Input9, 10 Open Drain Output2 Voltage Range Ground 0 V to 5.5 V 0 V to 5.5 V 0 V to 5.5 V 0 V to 5.5 V 0 V to 5.5 V Description Ground1 PLD Input 3 Open Drain Output 3 PLD Input 4 Open Drain Output 4 PLD Input 5 Open Drain Output 5 PLD Input 6 Open Drain Output 6 PLD Input 7 Open Drain Output 7 12 TCK Digital Input 0 V to 5.5 V JTAG Test Clock Input 13 TDI Digital Input 0 V to 5.5 V JTAG Test Data In - Internal Pull-up 11 TDO Digital Output 0 V to 5.5 V JTAG Test Data Out 14 TMS Digital Input 0 V to 5.5 V JTAG Test Mode Select - Internal Pull-up 3, 16 VCC Power 2.64 V to 3.96 V Power Supply6 10 VCCJ Power 2.25 V to 3.6 V VCC for JTAG Logic Interface Pins7 1 VMON1 Analog Input Voltage Monitor Input 1 2 VMON2 Analog Input –0.3 V to 5.9 V8 –0.3 V to 5.9 V8 2 Voltage Monitor Input 2 ProcessorPM-POWR605 Data Sheet Pin Descriptions (Cont.) Number Name 4 VMON3 Analog Input Pin Type 5 VMON4 Analog Input 6 VMON5 Analog Input 7 VMON6 23, 24 Die Pad Voltage Range Description Voltage Monitor Input 3 Analog Input –0.3 V to 5.9 V8 –0.3 V to 5.9 V8 –0.3 V to 5.9 V8 –0.3 V to 5.9 V8 NC No Connection Not applicable No internal connection NC No Connection Not applicable No internal connection Voltage Monitor Input 4 Voltage Monitor Input 5 Voltage Monitor Input 6 1. 2. 3. 4. GND pins must be connected together on the circuit board. Open-drain outputs require an external pull-up resistor to a supply. IN1_PWRDN and IN2 are inputs to the PLD. The thresholds for these pins are referenced by the voltage on VCC. The power-down function is E2CMOS programmable and when enabled is input level sensitive (enter power-down mode = low; exit powerdown mode = high). 5. Source of the power-down initiation can be assigned to either the IN1_PWRDN pin or to an internally generated PLD output signal called PLD_PWRDN. When generated internally by the PLD, the IN1_PWRDN pin is only used to exit power-down mode (IN1_PWRDN pin = high). 6. VCC pins must be connected together on the circuit board. 7. In power-down mode, VCCJ is internally pulled to GND to turn off the JTAG I/O pins. It is important, therefore, that the VCCJ pin be open whenever power-down mode is initiated. If connected to a power supply during power-down mode, VCCJ will draw approximately 2.2 mA. 8. The VMON inputs can be biased independently from VCC. Connect unused VMONs to 3.3 V rail. 9. Thresholds of IN_OUT1...IN_OUT5 in the input mode are referenced by the voltage on VCC. 10. IN1_PWRDN, IN2 and IN_OUT1...INOUT5 pins configured as inputs are clocked by the internal MCLK signal. Figure 2. Reset Generator Programmable Pulse Stretch and Watchdog Timer Programmable Up to  One Minute (Initial Factory Configuration)1 WDT_Trig Manual_reset IN1_PWRDN [22] 1V8_Rail2 ADJ12 VMON4 [5] R23 ADJ22 ADJ32 VMON5 [6] R63 ProcessorPM WDT_int [19] IN_OUT2 [17] [18] WDT Sel0 [15] WDT Sel1 R43 Processor/DSP VMON6 [7] IN_OUT5 2.5 V 1.8 V 1.1 V 0.9 V R53 Reset_CPU VMON3 [4] R13 R33 5V 3.3 V [20] IN_OUT1 VMON2 [2] Stretch_ 200 ms IN_OUT3 2V5_Rail2 IN2 [21] VMON1 [1] IN_OUT4 3V3_Rail2 0 – No Reset Pulse Stretch 1 – 200 ms Reset Pulse Stretch 00 – 500 ms 01 – 2 Sec. 10 – 10 Sec. 11 –1 Min. 1. Pin numbers shown in brackets. 2. Connect unused VMONs to 3.3 V rail. 3. R1..R6 required to externally adjust fault threshold when using factory default configuration. For supply rails 2.7 V 350 3000 300 2500 Frequency 1500 200 150 1000 100 500 50 Trip Point Error (%) Trip Point Error (%) Threshold setting accuracy histogram for all trip points ≤2.7V. Threshold setting accuracy histogram for all trip points >2.7V. 5 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 -1.0 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 0 -0.9 0 -1.0 Frequency 250 2000 ProcessorPM-POWR605 Data Sheet Power-On Reset (Internal) Max. Units TRST Symbol Delay from VTH to start-up state Parameter Conditions 100 µs TSTART Duration of start-up state 300 µs TBRO Minimum duration brown out required to enter reset state 5 µs TPOR Delay from brown out to reset state 7 µs Typ. 2.2 V 1 1 VTL Threshold below which POR is LOW VTH Threshold above which POR is HIGH1 VT Min. 1 Threshold above which POR is valid 2.5 V 0.8 V 1. Corresponds to VCC supply voltage. Figure 3. Internal Power-On Reset VTH TBRO VTL VT VCC T RST Reset State TPOR POR (Internal) Start Up State PLDCLK (Internal) T START Analog Calibration VMONs Ready (Internal) 6 ProcessorPM-POWR605 Data Sheet AC/Transient Characteristics Over Recommended Operating Conditions Symbol Parameter Conditions Min. Typ. Max. Units Voltage Monitors tPD12 Propagation delay input to output glitch filter OFF 12 µs tPD48 Propagation delay input to output glitch filter ON 48 µs Oscillators fMCLK MCLK timing fPLDCLK PLDCLK frequency = MCLK  32 7.6 8.0 8.4 250 MHz kHz Timers Timeout Range Range of programmable timers (128 steps) Resolution Spacing between available adjacent timer intervals Accuracy Timer accuracy 0.032 fMCLK = 8.0 MHz –6.67 1966 ms 13 % –12.5 % Power-Down Mode TPWRDN Time to enter power-down mode TPWRDN_HOLD Device previously on 100 µs Minimum required time in powerdown mode before power-up can occur 100 µs TPWRUP Time to exit power-down mode 300 µs TPWRDN_UP Total time to enter and then exit power-down mode 500 µs Figure 4. Power-Down Mode Timing VCC T PWRDN_UP IN1_PWRDN (low = power-down) ICC (nominal) TPWRDN_HOLD ICC I CC_PWRDN TPWRUP T PWRDN 7 ProcessorPM-POWR605 Data Sheet Digital Specifications Over Recommended Operating Conditions Symbol Parameter Conditions IIL,IIH Input leakage, no pull-up/pull-down IPU Input pull-up current (TMS, TDI) VIL VIH Voltage input, logic low1 Voltage input, logic high1 Typ. Max. Units +/-10 µA 70 µA TDI, TMS, TCK, IN[1:2], IN_OUT[1:5]2, VCCJ = 3.3 V supply 0.8 TDI, TMS, TCK, VCCJ = 2.5 V supply 0.7 V TDI, TMS, TCK, IN[1:2], IN_OUT[1:5]2, VCCJ = 3.3 V supply 2.0 TDI, TMS, TCK, VCCJ = 2.5 V supply 1.7 V ISINK = 20 mA 0.8 TDO ISINK = 4 mA 0.4 VOH TDO ISRC = 4 mA VCC - 0.4 V VOL < 0.8 V Output sink current per digital output Chip powered down, outIN_OUT[1:5] puts pulled up to 3.6 V 20 mA ISINK VOL IN_OUT[1:5] 3 Min.