L-ASC10
In-System Programmable
Hardware Management Expander
June 2017
Data Sheet DS1042
Features
Ten Rail Voltage Monitoring and
Measurement
Four Precision Trim and Margin Channels
• Closed Loop Operation
• Voltage Scaling and VID Support
• UV/OV Fault Detection Accuracy - 0.2% Typ.
• Fault Detection Speed 0.650 V
0.3
0.9
%
8
0.075
pF
VMON HYST
Hysteresis of any trip-point (relative
to setting)
1
%
VMON CMR
Differential VMON Common mode
rejection ratio
60
dB
VZ Sense
Low Voltage Sense Trip Point Error
– Differential VMON1-4
Low Voltage Sense Trip Point Error
– Single-Ended VMON5-9
Trip Point = 0.075 V
–5
+5
mV
Trip Point = 0.150 V
–5
+5
mV
Trip Point = 0.300 V
–10
+10
mV
Trip Point = 0.545 V
–15
+15
mV
Trip Point = 0.080 V
–10
+10
mV
Trip Point = 0.155 V
–15
+15
mV
Trip Point = 0.310 V
–25
+25
mV
Trip Point = 0.565 V
–55
+55
mV
0.3
13.2
Volts
1.0
%
High Voltage Monitor
HVMON Range
High Voltage VMON programmable
trip-point range
HVMON Accuracy HVMON Absolute accuracy of any
trip-point
VZ Sense
Low Voltage Sense Trip Point Error HVMON pin
HVMON voltage > 1.8 V
0.4
Trip Point = 0.220 V
–20
+20
mV
Trip Point = 0.425 V
–35
+35
mV
Trip Point = 0.810 V
–75
+75
mV
Trip Point = 1.280 V
–130
+130
mV
1. VMON accuracy may degrade based on SSO conditions of hardware management controller ASC-I/F. See the System Connections section
for more details.
6
L-ASC10
In-System Programmable
Hardware Management Expander
Current Monitors
Symbol
Parameter
IIMONPleak
IMON1P input leakage
IMON1N input leakage
IIMONNleak
IHIMONPleak
HIMONP input leakage
2
IMONA/B Accuracy HIMON, IMON1A/B Comparator
Trip Point accuracy
IMONA/B Gain
tIMONF
Min
Max
Units
–2
Typ
250
µA
Low Side Sense Enabled
Fast Trip Point Vsns =
500 mV
–2
40
µA
Low Side Sense Disabled
Fast Trip Point Vsns =
500 mV
–2
2
µA
Low Side Sense Enabled
Fast Trip Point Vsns =
500 mV
–200
2
µA
550
µA
350
µA
Fast Trip Point Vsns =
500 mV
HIMONN_HVMON input leakage
IHIMONNleak
IMONF Accuracy
Conditions
Low Side Sense Disabled
Fast Trip Point Vsns =
500 mV
Programmable Gain Setting
2
Gain = 100x
8
%
Gain = 50x
5
%
Gain = 25x
3
%
Gain = 10x
2
%
Four settings in software
10
V/V
25
V/V
50
V/V
100
V/V
8
%
Vsns = 200 mV, 250 mV,
or 300 mV
5
%
Vsns = 400 mV or
500 mV
3
%
1
Fast comparator trip-point accuracy Vsns = 50 mV, 100 mV, or
150 mV
Fast comparator response time
1
µs
1. Vsns is the differential voltage between IMON1P and IMON1N (or HIMONP and HIMONN).
2. IMON accuracy may degrade based on SSO conditions of hardware management controller ASC-I/F. See the System Connections section
for more details.
7
L-ASC10
In-System Programmable
Hardware Management Expander
ADC Characteristics
Symbol
Parameter
Conditions
Min
Resolution
tCONVERT
Typ
Max
10
2
Conversion Time from I C Request
Units
Bits
200
µs
V
Voltage Monitors
VVMON-IN
LSB
EVMON-attenuator
Input Range Full scale
ADC Step Size
Error due to attenuator
Programmable
Attenuator = 1
0
2.048
Programmable
Attenuator = 3
0
5.91
Programmable
Attenuator = 1
2
Programmable
Attenuator = 3
6
Programmable
Attenuator = 3
+/– 0.1
mV
%
High Voltage Monitor
VHVMON-IN
LSB
EHVMON-attenuator
Input Range Full scale
ADC Step Size
Error due to attenuator
Programmable
Attenuator = 4
0
8.192
Programmable
Attenuator = 8
0
13.21
V
Programmable
Attenuator = 4
8
Programmable
Attenuator = 8
16
Programmable
Attenuator = 4
+/–0.2
%
Programmable
Attenuator = 8
+/–0.4
%
1
ms
mV
Current Monitors
tIMON-sample
Sample period of HIMON and
IMON1 conversions for averaged
value
4 Settings via I2C
command
2
4
8
VIMON-IN
LSB
1
Input Range Full scale
ADC Step Size
Programmable Gain 10x
0
200
Programmable Gain 25x
0
80
Programmable Gain 50x
0
40
Programmable Gain 100x
0
20
Programmable Gain 10x
0.2
Programmable Gain 25x
0.08
Programmable Gain 50x
0.04
Programmable Gain 100x
0.02
1. Differential voltage applied across HIMONP/IMON1P and HIMONN/IMON1N before programmable gain amplification.
8
mV
mV
L-ASC10
In-System Programmable
Hardware Management Expander
ADC Error Budget Across Entire Operating Temperature Range
Symbol
TADC Error
Parameter
Conditions
Total ADC Measurement Error Measurement Range 600 mV - 2.048 V,
at Any Voltage (Differential
VMONxGS > –100 mV, Attenuator =1
Analog Inputs)1, 3
Measurement Range 600 mV - 2.048 V,
VMONxGS > –200 mV, Attenuator =1
Min
Typ
Max
Units
8
+/– 4
8
mV
Measurement Range 0 - 2.048 V,
VMONxGS > –200 mV, Attenuator =1
Total Measurement Error at
Any Voltage (Single-Ended
Analog Inputs including
IMON)1, 2, 3
Measurement Range 600 mV - 2.048 V,
Attenuator =1
–8
+/– 6
mV
+/– 10
mV
+/– 4
8
mV
1. Total error, guaranteed by characterization, includes INL, DNL, Gain, Offset, and PSR specs of the ADC.
2. Programmable gain error on IMON not included.
3. ADC accuracy may degrade based on SSO conditions of hardware management controller ASC-I/F. See the System Connections section
for more details
Temperature Monitors
Symbol
Parameter
Conditions
Min
Typ
Max
Units
TMON_REMOTE
Accuracy1, 7
Temp Error – Remote Sensor
Ta=–40 to +85 ºC
Td=–64 to 150 ºC
1
ºC
TMON_INT
Accuracy7
Internal Sensor – Relative to
ambient6
Ta=–40 to +85 ºC
1
ºC
TMON
Resolution
Measurement Resolution
0.25
ºC
TMON Range
Programmable threshold
range
–64
155
ºC
TMON Offset
Temperature offset
Programmable in software
–64
63.75
ºC
TMON
Hysteresis
Hysteresis of trip points
Programmable in software
0
63
ºC
tTMON_settle2
Temperature measurement
settling time3
Measurement Averaging Coefficient = 1
15
ms
Measurement Averaging Coefficient = 8
120
ms
Measurement Averaging Coefficient = 16
240
ms
Tn
Ideality Factor n
Tlimit
Temperature measurement
limit4
160
ºC
CTMON
Maximum capacitance
between TMONP and TMONN
pins
200
pF
RTMONSeries
Equivalent external resistance
to sensor5
200
ohms
Programmable in software
0.9
2
1. Accuracy number is valid for the use of a grounded collector pnp configuration, programmed with proper ideality factor, and 16x measurement filter enabled. Any other device or configuration can have additional errors, including beta, series resistance and ideality factor accuracy. See the Temperature Monitors section for more details.
2. Settling time based on one TMON enabled. For multiple TMONs, settling time can be multiplied by the number of enabled TMON channels.
3. Settling time is defined as the time it takes a step change to settle to 1% of the measured value.
4. All values above Tlimit read as 0x3FF over I2C. There is no cold temperature limiting reading, although performance is not specified below
–64 oC.
5. This is the maximum series resistance which the TMON circuit can compensate out. Equivalent series resistance includes all board trace
wiring (TMONP and TMONN) as well as parasitic base and emitter resistances. Re=1/gm should not be included as part of series resistance.
6. Internal sensor is subject to self-heating, dependent on PCB design and device configuration. Self-heating not included in published accuracy.
7. TMON accuracy may degrade based on SSO conditions of hardware management controller ASC-I/F. See the System Connections section
for more details.
9
L-ASC10
In-System Programmable
Hardware Management Expander
Digital Specifications
Symbol
Parameter
Conditions
Min
Typ
Max
Units
+/– 10
µA
IIL,IIH
Input Leakage, no pull-up,
pull-down2
IPD
Active Pull-Down Current2
GPIO[1:10] configured as Inputs, Internal Pull-Down enabled
200
µA
IPD-ASCIF
Input Leakage (WDAT and
WRCLK)3
Internal Pull-Down
175
µA
IOH-HVOUT
Output Leakage Current
HVOUT[1:4] in open drain mode and
pulled up to 12 V
35
IPU-RESETb
Input Pull-Up Current
(RESETb)
VIL
Voltage input, logic low
Voltage input, logic high
VIH
VOL
ISINKTOTAL
1
100
–50
µA
GPIO[1:10]
0.8
SCL, SDA
30%
VCCA
GPIO[1:10]
2.0
SCL, SDA
70%
VCCA
HVOUT[1:4] (open drain
mode)
ISINK = 10 mA
GPIO[1:6], GPIO[8:10]
ISINK = 20 mA
µA
V
V
All digital outputs
0.8
V
130
mA
1. Sum of maximum current sink from all digital outputs combined. Reliable operation is not guaranteed if this value is exceeded.
2. During safe-state, all GPIO default to output, see the Safe State of Digital Outputs section for more details. GPIO[1:6] and GPIO[10] default
to active low output. This will result in a leakage current dependent on the input voltage which can exceed the specified input leakage
3. WRCLK and WDAT pins may see transients above 1 mA in hot socket conditions. DC levels will remain below 1 mA.
High Voltage FET Drivers
Symbol
VPP
Parameter
Gate driver output voltage
Conditions
Min
Four settings in software
Typ
Max
12
Units
Volts
10
8
6
IOUTSRC
Gate driver source current
(HIGH state)
Four settings in software
12.5
µA
25
50
100
IOUTSINK
Gate driver sink current
(LOW state)
Four settings in software
100
µA
250
500
3000
Frequency
Switched Mode Frequency
Two settings in software
15.625
kHz
31.25
Duty Cycle
Switched Mode Programmable Duty Cycle Range
Programmable in software
Duty Cycle step size
6.25
93.75
6.25
10
%
%
L-ASC10
In-System Programmable
Hardware Management Expander
Margin/Trim DAC Output Characteristics
Symbol
Parameter
Conditions
Min
Resolution
FSR
Full scale range
LSB
LSB step size
IOUT
Output source/sink current
ITRIM_Hi-Z
Tri-state mode leakage
BPZ
Bipolar zero output voltage
(code=80h)
Typ.
Max.
Bits
+/– 320
mV
2.5
–200
Four settings in software
Units
8 (7 +
sign)
mV
200
µA
0.1
µA
0.6
V
0.8
1.0
1.25
tS
TrimCell output voltage settling DAC code changed from 80H to FFH or
time1
80H to 00H
2.5
Single DAC code change
C_LOAD
Maximum load capacitance
TOSE
Total open loop supply voltage Full scale DAC corresponds to +/– 5%
error2
supply voltage variation
256
–1%
ms
µs
50
pF
+1%
V/V
1. To 1% of set value with 50 pF load connected to trim pins.
2. Total resultant error in the trimmed power supply output voltage referred to any DAC code due to DAC’s INL, DNL, gain, output impedance,
offset error and bipolar offset error across the temperature, and VCCA ranges of the device.
Fault Log
Symbol
Parameter
Records
Number of available fault log
records in EEPROM
tfaultTrigger
Minimum active time of trigger
signal to start fault recording
tfaultRecord
Time to copy fault record to
EEPROM
Conditions
Min
Typ.
Max.
16
Units
Records
64
µs
5
ms
Oscillator
Min
Typ.
Max.
Units
CLKASC
Symbol
Internal ASC0 Clock
Parameter
Conditions
7.6
8
8.4
MHz
CLKext
Externally Applied Clock
7.6
8
8.4
MHz
11
L-ASC10
In-System Programmable
Hardware Management Expander
Propagation Delays
Symbol
Parameter
Conditions
Min
Typ.
Max.
Units
Voltage Monitors
tVMONtoFPGA
tVMONtoOCB
2
Propagation delay VMON
Glitch Filter Off
input to signal update at FPGA Glitch Filter ON
48
µs
96
µs
Propagation delay VMON
Glitch Filter Off
input to output update at OCB Glitch Filter ON
16
µs
64
µs
Current Monitors
tIMONtoFPGA
Propagation delay IMON input Glitch Filter Off
to signal update at FPGA
Glitch Filter ON
tIMONtoOCB2
Propagation delay IMON input Glitch Filter Off
to output update at OCB
Glitch Filter ON
tIMONFtoOCB2
Propagation delay IMONF
input to output update at OCB
48
µs
96
µs
16
µs
64
µs
1
µs
Temperature Monitors
tTMONtoFPGA
Propagation delay TMON
input to signal update at
FPGA1
Monitor Alarm Filter Depth = 1
15
ms
Monitor Alarm Filter Depth = 16
240
ms
32
µs
GPIO – Inputs
tGPIOtoFPGA
Propagation delay GPIO input
to signal update at FPGA
tGPIOtoOCB2
Propagation delay GPIO input
to output update at OCB
50
ns
GPIO – Outputs
tFPGAtoGPIO
Propagation delay FPGA signal update to GPIO output
tOCBtoGPIO3
Propagation delay OCB input
to output update at GPIO
32
µs
50
ns
HVOUT
tFPGAtoHVOUT
Propagation delay FPGA signal update to HVOUT output
tOCBtoHVOUT3, 4
Propagation delay OCB input
to output update at HVOUT
32
µs
110
ns
TRIM DAC
tFPGAtoTrimOE
Propagation delay FPGA signal update to TRIM_OE
update
32
µs
1. Propagation delay based on one TMON enabled. For multiple TMONs, propagation delay can be multiplied by the number of enabled TMON
channels.
2. OCB output propagation delays measured using time delay to GPIO output from OCB. Propagation delay is measured on falling GPIO outputs. Rising output propagation time will be dependent on external pull-up resistor.
3. OCB input propagation delays measured using time delay from GPIO input to OCB. Propagation delay is measured on falling GPIO outputs.
Rising output propagation time will be dependent on external pull-up resistor.
4. HVOUT propagation delay measured with HVOUT in open-drain mode, with switched mode disabled. Propagation delay in charge pump
mode is dependent on external load and HVOUT settings.
12
L-ASC10
In-System Programmable
Hardware Management Expander
ASC Interface (ASC-I/F) Timing Specifications1
Symbol
Parameter
Conditions
Min
Typ
Max
8
Units
fwrclk
WRCLK frequency
tASC_HLD
Hold time between WRCLK
falling edge and WDAT transition
0
MHz
ns
tASC_SU
Setup time between WDAT
transition and WRCLK rising
edge
25
ns
tASC_OUT
Delay from WRCLK falling
edge to RDAT transition
50
ns
1. All timing conditions valid for VCCIO = 3.3 V at FPGA ASC-I/F and ASC VCCA range of 2.8 V to 3.6 V.
Figure 4. ASC Interface (ASC-I/F) Timing Diagram
WRCLK
t ASC _ HLD
WDAT
t ASC_SU
RDAT
t ASC_OUT
I2C Port Timing Specifications
Symbol
fMAX
Parameter
Min.
Maximum SCL clock frequency
1. ASC supports the following modes:
a. Standard-mode (Sm), with a bit rate up to 100 kbit/s (user and configuration mode)
b. Fast-mode (Fm), with a bit rate up to 400 kbit/s (user and configuration mode)
2. Refer to the I2C specification for timing requirements.
13
Max.
Units
400
kHz
L-ASC10
In-System Programmable
Hardware Management Expander
Theory of Operation
Hardware Management System
The ASC Hardware Management Expander is designed to seamlessly increase the number of analog sense and
control channels in the hardware management section of a circuit board. The device functions as a hardware management expander in systems with the Lattice Platform Manager 2, MachXO2, MachXO3, or ECP5 FPGAs. The
functional blocks for analog voltage, current and temperature monitoring, measurement, and control are built into
the ASC. The ASC depends on the Platform Manager 2, MachXO2, MachXO3, or ECP5 FPGA to interpret the analog monitor status signals and provide control commands.
The Platform Manager 2, MachXO2, MachXO3, or ECP5 FPGA includes the hardware management control logic
and other plug-in IP components to support functions like Fan Control, or Voltage by Identification (VID). ASC
devices can be added to the hardware management system to scale with application requirements and are connected to the same Platform Manager 2, MachXO2, MachXO3, or ECP5 FPGA. This architecture supports a single
centralized hardware management logic design, with up to eight distributed ASC devices. The basic system concept is shown in Figure 5. The connections are described in detail in the System Connections section.
Figure 5. Hardware Management System with ASC Hardware Management Expander
To Additional
ASC Devices
ASC Hardware Management Expander
Platform Manager 2 / MachXO2 /
MachXO3 / ECP5 FPGA
MOSFET & Digital I / O Drive
(HVOUTs & GPIO)
Output Control
Block
Analog Monitors, Inputs
Current
Sense
ASC
Interface
(ASC-I/F)
Outputs, Trim Controls
ASC-I/F
Logic
Hardware
Management
Control Logic
FPGA I/ Os
Temperat ure
Sense
Voltage
Sense
ADC
Non Volatile
Fault Log
I2 C
Interface
ADC
Programming,
Trim Targets
Analog Measurements
I2 C
Interface
IP Components
(Fan Control, VID, etc.)
Trim & Margin
Control
To Additional
ASC Devices
The Hardware Management System is configured using Platform Designer, a part of Lattice Diamond software.
Platform Designer provides an easy to use graphical and spreadsheet based interface. Platform Designer automatically generates the device memory configuration based on the options selected in the software. See the For Further Information section for more details.
14
L-ASC10
In-System Programmable
Hardware Management Expander
Voltage Monitor Inputs
The ASC provides ten independently programmable voltage monitor input circuits. There are nine standard voltage
channels and one high voltage channel. The standard voltage channels are shown in Figure 6, while the high voltage channel is described in the High Voltage Current Monitor section. Two individually programmable trip-point
comparators are connected to each voltage monitoring input. Each comparator reference has programmable trip
points over the range of 0.075 V to 5.734 V. The 75 mV ‘zero-detect’ threshold allows the voltage monitors to determine if a monitored signal has dropped to ground level. This feature is especially useful for determining if a power
supply’s output has decayed to a substantially inactive condition after it has been switched off.
Figure 6. ASC Voltage Monitors
To ADC
Differential
Input Buffer X*
CompA/Window
Select
Comp A
VMONx
VMONx_A
Logic Signal
Trip Point A
MUX
VMONxGS*
Glitch
Filter
Comp B
VMONx_B
Logic Signal
Glitch
Filter
Trip Point B
Analog Input
TO
ASC-I/F
& OCB
Window Control
Filtering
VMONx Status
2
I C Interface Unit
*Differential Input Buffer X and VMONxGS pins are not present for single-ended VMON x inputs.
Figure 6 shows the functional block diagram of one of the nine voltage monitor inputs - ‘x’ (where x = 1...9). Each
voltage monitor can be divided into three sections: Analog Input, Window Control, and Filtering. The first section
provides a differential input buffer to monitor the power supply voltage through VMONx (to sense the positive terminal of the supply) and VMONxGS (to sense the power supply ground). Differential voltage sensing minimizes inaccuracies in voltage measurement with ADC and monitor thresholds due to the potential difference between the
ASC device ground and the ground potential at the sensed node on the circuit board.
The voltage output of the differential input buffer is monitored by two individually programmable trip-point comparators, shown as Comp A and Comp B. The differential input buffer shown above is not present for any of the singleended VMON inputs. VMON1-4 are differential inputs, while VMON5-10 are single-ended.
Each comparator outputs a HIGH signal to the ASC-I/F if the voltage at its positive terminal is greater than its programmed trip point setting; otherwise it outputs a LOW signal. The VMON4A and VMON9A comparators also output their status signals to the OCB.
Hysteresis is provided by the comparators to reduce false triggering as a result of input noise. The hysteresis provided by the voltage monitor is a function of the input divider setting. Table 1 lists the typical hysteresis versus voltage monitor trip-point.
AGOOD Logic Signal
All the VMON, IMON and TMON comparators auto-calibrate following a power-on reset event. During this time, the
digital glitch filters are also initialized. This process completion is signaled by an internally generated logic signal:
AGOOD. The ASC-I/F will not begin communicating valid VMON status bits or receiving GPIO control signals until
the AGOOD signal is initialized.
15
L-ASC10
In-System Programmable
Hardware Management Expander
Programmable Over-Voltage and Under-Voltage Thresholds
Figure 7 shows the power supply ramp-up and ramp-down voltage waveforms. Because of hysteresis, the comparator outputs change state at different thresholds depending on the direction of excursion of the monitored power
supply.
Monitored Power Supply Voltage
Figure 7. Power Supply Voltage Ramp-up and Ramp-down Waveform and the Resulting Comparator Output
(a) and Corresponding to Upper and Lower Trip Points (b)
UTP
LTP
(a)
(b)
Comparator Logic Output
During power supply ramp-up the comparator output changes from logic zero to one when the power supply voltage crosses the upper trip point (UTP). During ramp down the comparator output changes from logic state one to
zero when the power supply voltage crosses the lower trip point (LTP). To monitor for over voltage fault conditions,
the UTP should be used. To monitor under-voltage fault conditions, the LTP should be used. The upper and lower
trip points are automatically selected in software depending on whether the user is monitoring for an over-voltage
condition or an under-voltage condition. Table 1 shows the comparator hysteresis versus the trip-point range.
Table 1. Voltage Monitor Comparator Hysteresis vs. Trip-Point
Trip-point Range (V)
Hysteresis (mV)
Low Limit
High Limit
0.66
0.79
8
0.79
0.9
10
0.94
1.12
12
1.12
1.33
14
1.33
1.58
17
1.58
1.88
20
1.88
2.24
24
2.24
2.66
28
2.66
3.16
34
3.16
3.76
40
4.05
4.82
51
4.82
5.73
61
0.075
0.57
0 (Disabled)
16
L-ASC10
In-System Programmable
Hardware Management Expander
The window control section of the voltage monitor circuit is an AND gate (with inputs: an inverted COMPA “ANDed”
with COMPB signal) and a multiplexer that supports the ability to develop a ‘window’ function in hardware. Through
the use of the multiplexer, voltage monitor’s ‘A’ output may be set to report either the status of the ‘A’ comparator, or
the window function of both comparator outputs. The voltage monitor’s ‘A’ output indicates whether the input signal
is between or outside the two comparator thresholds. Important: This windowing function is only valid in cases
where the threshold of the ‘A’ comparator is set to a value higher than that of the ‘B’ comparator. Table 2 shows the
operation of window function logic.
Table 2. Voltage Monitoring Window Logic
Comp A
Comp B
Window
(B and Not A)
Comment
VIN < Trip-Point B < Trip-Point A
0
0
0
Outside window, low
Trip-Point B
