LA-ISPPAC-POWR1014A-01TN48E

® LA-ispPAC-POWR1014/A Automotive Family In-System Programmable Power Supply Supervisor, Reset Generator and Sequencing Controller September 2013 Data Sheet DS1018 Features Application Block Diagram  Monitor and Control Multiple Power Supplies • Simultaneously monitors up to 10 power  supplies • Provides up to 14 output control signals • Programmable digital and analog circuitry Primary Supply 3.3V Primary Supply  AEC-Q100 Tested and Qualified  Embedded PLD for Sequence Control 1.8V Primary Supply POL#1 • Four independent timers • 32µs to 2 second intervals for timing sequences Primary Supply Enables  Embedded Programmable Timers POL#N  Analog Input Monitoring Other Control/Supervisory Signals  High-Voltage FET Drivers  2-Wire (I C/SMBus™ Compatible) Interface 2 • • • • • Comparator status monitor ADC readout Direct control of inputs and outputs Power sequence control Only available with LA-ispPAC-POWR1014A  3.3V Operation, Wide Supply Range 2.8V to 3.96V • Automotive temperature range: -40°C to +105°C • 48-pin TQFP package, lead-free option  Multi-Function JTAG Interface • In-system programming • Access to all I2C registers • Direct input control 12 Digital Outputs 2 MOSFET Drivers Digital Monitoring 10 Analog Inputs and Voltage Monitors • 10 independent analog monitor inputs • Two programmable threshold comparators per analog input • Hardware window comparison • 10-bit ADC for I2C monitoring (LA-ispPACPOWR1014A only) • Power supply ramp up/down control • Programmable current and voltage output • Independently configurable for FET control or digital output Voltage Monitoring • 24-macrocell CPLD implements both state machines and combinatorial logic functions Other Board Circuitry 2.5V Primary Supply CPLD 24 Macrocells 53 Inputs ADC* 4 Timers 4 Digital Inputs I2C Interface I2C Bus* CPU LA-ispPAC-POWR1014A *LA-ispPAC-POWR1014A only. Description Lattice’s Power Manager II LA-ispPAC-POWR1014/A is a general-purpose power-supply monitor and sequence controller, incorporating both in-system programmable logic and in-system programmable analog functions implemented in non-volatile E2CMOS® technology. The LA-ispPAC-POWR1014/A device provides 10 independent analog input channels to monitor up to 10 power supply test points. Each of these input channels has two independently programmable comparators to support both high/low and in-bounds/out-of-bounds (window-compare) monitor functions. Four general-purpose digital inputs are also provided for miscellaneous control functions. The LA-ispPAC-POWR1014/A provides 14 open-drain digital outputs that can be used for controlling DC-DC converters, low-drop-out regulators (LDOs) and optocouplers, as well as for supervisory and general-purpose logic interface functions. Two of these outputs (HVOUT1-HVOUT2) may be configured as high-voltage © 2013 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 5-1 DS1018_01.3 LA-ispPAC-POWR1014/A Automotive Family Data Sheet MOSFET drivers. In high-voltage mode these outputs can provide up to 8V for driving the gates of n-channel MOSFETs so that they can be used as high-side power switches controlling the supplies with a programmable ramp rate for both ramp up and ramp down. The LA-ispPAC-POWR1014/A incorporates a 24-macrocell CPLD that can be used to implement complex state machine sequencing for the control of multiple power supplies as well as combinatorial logic functions. The status of all of the comparators on the analog input channels as well as the general purpose digital inputs are used as inputs by the CPLD array, and all digital outputs may be controlled by the CPLD. Four independently programmable timers can create delays and time-outs ranging from 32µs to 2 seconds. The CPLD is programmed using LogiBuilder™, an easy-to-learn language integrated into the PAC-Designer® software. Control sequences are written to monitor the status of any of the analog input channel comparators or the digital inputs. The on-chip 10-bit A/D converter is used to monitor the VMON voltage through the I2C bus or JTAG interface of the LA-ispPAC-POWR1014A device. The I2C bus/SMBus interface allows an external microcontroller to measure the voltages connected to the VMON inputs, read back the status of each of the VMON comparator and PLD outputs, control logic signals IN2 to IN4 and control the output pins (LA-ispPAC-POWR1014A only). The JTAG interface can be used to read out all I2C registers during manufacturing. Figure 5-1. LA-ispPAC-POWR1014/A Block Diagram MEASUREMENT ADC* CONTROL LOGIC* 53 INPUTS 4 DIGITAL INPUTS IN1 IN2 IN3 IN4 JTAG LOGIC CLOCK OSCILLATOR TIMERS (4) GNDD (2) GNDA SDA (POWR1014A only) 5-2 OUT3/(SMBA*) OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 OUT10 OUT11 OUT12 OUT13 OUT14 I 2C INTERFACE SCL (POWR1014A only) RESETb PLDCLK MCLK ATDI TDI TDISEL TCK TMS TDO VCCJ APS VCCA VCCD (2) VCCINP *LA-ispPAC-POWR1014A only. HVOUT1 HVOUT2 12 OPEN-DRAIN DIGITAL OUTPUTS 24 MACROCELLS 2 FET DRIVERS CPLD OUTPUT ROUTING POOL 10 ANALOG INPUTS AND VOLTAGE MONITORS VMON1 VMON2 VMON3 VMON4 VMON5 VMON6 VMON7 VMON8 VMON9 VMON10 LA-ispPAC-POWR1014/A Automotive Family Data Sheet Pin Descriptions Number Name Pin Type Voltage Range Description 44 IN1 Digital Input VCCINP1, 2 PLD Logic Input 1 Registered by MCLK 46 IN2 Digital Input VCCINP1, 3 PLD Logic Input 2 Registered by MCLK 47 IN3 Digital Input VCCINP1, 3 PLD Logic Input 3 Registered by MCLK 1, 3 48 IN4 Digital Input VCCINP PLD Logic Input 4 Registered by MCLK 25 VMON1 Analog Input -0.3V to 5.87V4 Voltage Monitor 1 Input 26 VMON2 Analog Input -0.3V to 5.87V4 Voltage Monitor 2 Input 4 Voltage Monitor 3 Input 27 VMON3 Analog Input -0.3V to 5.87V 28 VMON4 Analog Input -0.3V to 5.87V4 Voltage Monitor 4 Input 32 VMON5 Analog Input -0.3V to 5.87V4 Voltage Monitor 5 Input 4 Voltage Monitor 6 Input 33 VMON6 Analog Input -0.3V to 5.87V 34 VMON7 Analog Input -0.3V to 5.87V4 Voltage Monitor 7 Input 35 VMON8 Analog Input -0.3V to 5.87V4 Voltage Monitor 8 Input 4 Voltage Monitor 9 Input 36 VMON9 Analog Input -0.3V to 5.87V 37 VMON10 Analog Input -0.3V to 5.87V4 Voltage Monitor 10 Input 7, 31 GNDD5 Ground Ground Digital Ground 30 GNDA5 Analog Ground Ground Ground 41, 23 VCCD6 Power 2.8V to 3.96V Core VCC, Main Power Supply 29 VCCA6 Power 2.8V to 3.96V Analog Power Supply 45 VCCINP Power 2.25V to 5.5V VCC for IN[1:4] Inputs 20 VCCJ Power 2.25V to 3.6V VCC for JTAG Logic Interface Pins 24 APS10 Alternate Programming 3.0V to 3.6V Supply Alternate E2 Programming Supply; use only when the Device is Not Powered by VCCD and VCCA Open Drain Output7 0V to 8V Open-Drain Output 1 15 HVOUT1 Current Source/Sink 12.5µA to 100µA Source High-voltage FET Gate Driver 1 100µA to 3000µA Sink Open Drain Output7 0V to 8V Current Source/Sink 12.5µA to 100µA Source High-voltage FET Gate Driver 2 100µA to 3000µA Sink Open-Drain Output 2 14 HVOUT2 13 SMBA_OUT3 Open Drain Output7 0V to 5.5V Open-Drain Output 3, (SMBUS Alert Active Low, LA-ispPAC-POWR1014A only). 12 OUT4 Open Drain Output7 0V to 5.5V Open-Drain Output 4 OUT5 Open Drain Output 7 0V to 5.5V Open-Drain Output 5 7 11 10 OUT6 Open Drain Output 0V to 5.5V Open-Drain Output 6 9 OUT7 Open Drain Output7 0V to 5.5V Open-Drain Output 7 8 OUT8 Open Drain Output7 0V to 5.5V Open-Drain Output 8 6 OUT9 Open Drain Output 7 0V to 5.5V Open-Drain Output 9 5 OUT10 Open Drain Output7 0V to 5.5V Open-Drain Output 10 4 OUT11 Open Drain Output7 0V to 5.5V Open-Drain Output 11 3 OUT12 Open Drain Output 7 0V to 5.5V Open-Drain Output 12 2 OUT13 Open Drain Output7 0V to 5.5V Open-Drain Output 13 7 1 OUT14 Open Drain Output 0V to 5.5V Open-Drain Output 14 40 RESETb8 Digital I/O 0V to 3.96V Device Reset (Active Low) - Internal pull-up 42 PLDCLK Digital Output 0V to 3.96V 250kHz PLD Clock Output (Tristate), CMOS  Output - Internal pull-up 5-3 LA-ispPAC-POWR1014/A Automotive Family Data Sheet Pin Descriptions (Cont.) Number Name Pin Type Voltage Range Description 43 MCLK Digital I/O 0V to 3.96V 8MHz Clock I/O (Tristate), CMOS Drive - Internal Pull-up 21 TDO Digital Output 0V to 5.5V JTAG Test Data Out 22 TCK Digital Input 0V to 5.5V JTAG Test Clock Input 16 TMS Digital Input 0V to 5.5V JTAG Test Mode Select - Internal Pull-up 18 TDI Digital Input 0V to 5.5V JTAG Test Data In, TDISEL pin = 1 - Internal  Pull-up 17 ATDI Digital Input 0V to 5.5V JTAG Test Data In (Alternate), TDISEL Pin = 0 Internal Pull-up 19 TDISEL Digital Input 0V to 5.5V Select TDI/ATDI Input - Internal Pull-up 39 SCL9, 11 Digital Input 0V to 5.5V I2C Serial Clock Input (LA-ispPAC-POWR1014A Only) 38 SDA9, 11 Digital I/O 0V to 5.5V I2C Serial Data, Bi-directional Pin, Open Drain  (LA-ispPAC-POWR1014A Only) 1. [IN1...IN4] are inputs to the PLD. The thresholds for these pins are referenced by the voltage on VCCINP. Unused INx inputs should be tied to GNDD. 2. IN1 pin can also be controlled through JTAG interface. 3. [IN2..IN4] can also be controlled through I2C/SMBus interface (LA-ispPAC-POWR1014A only). 4. The VMON inputs can be biased independently from VCCA. Unused VMON inputs should be tied to GNDD. 5. GNDA and GNDD pins must be connected together on the circuit board. 6. VCCD and VCCA pins must be connected together on the circuit board. 7. Open-drain outputs require an external pull-up resistor to a supply. 8. The RESETb pin should only be used for cascading two or more LA-ispPAC-POWR1014/A devices. 9. These pins should be connected to GNDD (LA-ispPAC-POWR1014 device only). 10. The APS pin MUST be left floating when VCCD and VCCA are powered. 11. SCL should be tied high and SDA is don’t care when I2C registers are accessed through the JTAG interface. 5-4 LA-ispPAC-POWR1014/A Automotive Family Data Sheet Absolute Maximum Ratings Absolute maximum ratings are shown in the table below. Stresses beyond those listed may cause permanent damage to the device. Functional operation of the device at these or any other conditions beyond those indicated in the recommended operating conditions of this specification is not implied. Symbol Parameter Conditions Min. Max. Units VCCD Core supply -0.5 4.5 V VCCA Analog supply -0.5 4.5 V VCCINP Digital input supply (IN[1:4]) -0.5 6 V VCCJ JTAG logic supply -0.5 6 V APS Alternate E2 programming supply -0.5 4 V VIN Digital input voltage (all digital I/O pins) -0.5 6 V VMON VMON input voltage VTRI Voltage applied to tri-stated pins ISINKMAXTOTAL Maximum sink current on any output TS Storage temperature TA -0.5 6 V HVOUT[1:2] -0.5 13.3 V OUT[3:14] -0.5 V mA 150 o -65 125 o Min. Max. Units 2.8 3.96 V -65 Ambient temperature 6 23 C C Recommended Operating Conditions Symbol Parameter Conditions VCCD, VCCA Core supply voltage at pin VCCINP Digital input supply for IN[1:4] at pin 2.25 5.5 V VCCJ JTAG logic supply voltage at pin 2.25 3.6 V APS Alternate E2 programming supply at pin VIN Input voltage at digital input pins VMON Input voltage at VMON pins VCCD and VCCA powered VCCD and VCCA not powered No connect Must be left floating V 3.0 3.6 V -0.3 5.5 V -0.3 5.9 V OUT[3:14] pins -0.3 5.5 V HVOUT[1:2] pins in open-drain mode -0.3 13.0 V -40 85 o VOUT Open-drain output voltage TAPROG Ambient temperature during  programming TA1 Ambient temperature Power applied -40 105 o TJ Junction temperature Power applied -40 110 o Typ. Max. Units C C C 1. Device functionality guaranteed up to 125°C. Analog Specifications Symbol ICC 1 Parameter Conditions Min. Core and analog supply current 20 mA ICCINP VCCINP supply current 5 mA ICCJ JTAG supply current ICCPROG Core and analog supply current During programming cycle 1. Includes currents on VCCD and VCCA supplies. 5-5 1 mA 20 mA LA-ispPAC-POWR1014/A Automotive Family Data Sheet Voltage Monitors Symbol Parameter RIN Input resistance Conditions Min. Typ. Max. Units 55 65 75 k CIN Input capacitance VMON Range Programmable trip-point range 0.075 8 VZ Sense Near-ground sense threshold 70 VMON Accuracy Absolute accuracy of any trip-point1 HYST Hysteresis of any trip-point (relative to setting) -40