ECP5™ Automotive Family
Data Sheet
FPGA-DS-02014 -1.1
June 2018
ECP5™ Automotive Family
Data Sheet
Contents
Acronyms in This Document .................................................................................................................................................7
1. General Description ......................................................................................................................................................8
1.1.
Features ...............................................................................................................................................................8
2. Architecture ................................................................................................................................................................10
2.1.
Overview ...........................................................................................................................................................10
2.2.
PFU Blocks .........................................................................................................................................................11
2.2.1. Slice ...............................................................................................................................................................12
2.2.2. Modes of Operation ......................................................................................................................................15
2.3.
Routing ..............................................................................................................................................................16
2.4.
Clocking Structure .............................................................................................................................................16
2.5.
sysCLOCK PLL .....................................................................................................................................................16
2.6.
Clock Distribution Network ...............................................................................................................................18
2.7.
Primary Clocks ...................................................................................................................................................18
2.8.
Dynamic Clock Control ......................................................................................................................................19
2.9.
Dynamic Clock Select.........................................................................................................................................19
2.10. Edge Clock .........................................................................................................................................................19
2.11. Clock Dividers ....................................................................................................................................................20
2.12. DDRDLL ..............................................................................................................................................................21
2.13. sysMEM Memory ..............................................................................................................................................22
2.13.1.
sysMEM Memory Block ............................................................................................................................22
2.13.2.
Bus Size Matching .....................................................................................................................................23
2.13.3.
RAM Initialization and ROM Operation ....................................................................................................23
2.13.4.
Memory Cascading ...................................................................................................................................23
2.13.5.
Single, Dual and Pseudo-Dual Port Modes ...............................................................................................23
2.13.6.
Memory Core Reset ..................................................................................................................................24
2.14. sysDSP™ Slice ....................................................................................................................................................25
2.14.1.
sysDSP Slice Approach Compared to General DSP ...................................................................................25
2.15. ECP5 Automotive sysDSP Slice Architecture Features ......................................................................................26
2.16. Programmable I/O Cells ....................................................................................................................................29
2.17. PIO .....................................................................................................................................................................31
2.17.1.
Input Register Block ..................................................................................................................................31
2.17.2.
Output Register Block ...............................................................................................................................32
2.18. Tri-state Register Block......................................................................................................................................33
2.19. DDR Memory Support .......................................................................................................................................34
2.19.1.
DQS Grouping for DDR Memory ...............................................................................................................34
2.19.2.
DLL Calibrated DQS Delay and Control Block (DQSBUF) ...........................................................................35
2.20. sysI/O Buffer ......................................................................................................................................................37
2.20.1.
sysI/O Buffer Banks...................................................................................................................................37
2.20.2.
Typical sysI/O I/O Behavior during Power-up...........................................................................................38
2.20.3.
Supported sysI/O Standards .....................................................................................................................38
2.20.4.
On-Chip Programmable Termination .......................................................................................................39
2.20.5.
Hot Socketing............................................................................................................................................39
2.21. SERDES and Physical Coding Sublayer ...............................................................................................................40
2.21.1.
SERDES Block ............................................................................................................................................41
2.21.2.
PCS ............................................................................................................................................................42
2.21.3.
SERDES Client Interface Bus .....................................................................................................................42
2.22. Flexible Dual SERDES Architecture ....................................................................................................................42
2.23. IEEE 1149.1-Compliant Boundary Scan Testability ............................................................................................43
2.24. Device Configuration .........................................................................................................................................43
2.24.1.
Enhanced Configuration Options..............................................................................................................43
2.24.2.
Single Event Upset (SEU) Support.............................................................................................................44
2.24.3.
On-Chip Oscillator.....................................................................................................................................44
© 2016-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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FPGA-DS-02014-1.1
ECP5™ Automotive Family
Data Sheet
2.25. Density Shifting ................................................................................................................................................. 45
DC and Switching Characteristics ............................................................................................................................... 46
3.1.
Absolute Maximum Ratings .............................................................................................................................. 46
3.2.
Recommended Operating Conditions ............................................................................................................... 46
3.3.
Power Supply Ramp Rates ................................................................................................................................ 47
3.4.
Power-On-Reset Voltage Levels ........................................................................................................................ 47
3.5.
Power up Sequence .......................................................................................................................................... 47
3.6.
Hot Socketing Specifications ............................................................................................................................. 47
3.7.
Hot Socketing Requirements............................................................................................................................. 48
3.8.
ESD Performance .............................................................................................................................................. 48
3.9.
DC Electrical Characteristics .............................................................................................................................. 48
3.10. Standby ECP5 Automotive Supply Current ....................................................................................................... 49
3.11. SERDES Power Supply Requirements ................................................................................................................ 50
3.12. sysI/O Recommended Operating Conditions .................................................................................................... 51
3.13. sysI/O Single-Ended DC Electrical Characteristics ............................................................................................. 52
3.14. sysI/O Differential Electrical Characteristics ..................................................................................................... 53
3.14.1.
LVDS.......................................................................................................................................................... 53
3.14.2.
SSTLD ........................................................................................................................................................ 53
3.14.3.
LVCMOS33D ............................................................................................................................................. 53
3.14.4.
LVDS25E .................................................................................................................................................... 54
3.14.5.
BLVDS25 ................................................................................................................................................... 55
3.14.6.
LVPECL33 .................................................................................................................................................. 56
3.14.7.
MLVDS25 .................................................................................................................................................. 57
3.14.8.
SLVS .......................................................................................................................................................... 58
3.15. Typical Building Block Function Performance ................................................................................................... 59
3.16. Derating Timing Tables...................................................................................................................................... 60
3.17. ECP5 Automotive Maximum I/O Buffer Speed ................................................................................................. 61
3.18. ECP5 Automotive External Switching Characteristics ....................................................................................... 62
3.19. sysCLOCK PLL Timing ......................................................................................................................................... 69
3.20. SERDES High-Speed Data Transmitter ............................................................................................................... 70
3.21. SERDES/PCS Block Latency ................................................................................................................................ 71
3.22. SERDES High-Speed Data Receiver .................................................................................................................... 72
3.23. Input Data Jitter Tolerance................................................................................................................................ 72
3.24. SERDES External Reference Clock ..................................................................................................................... 73
3.25. PCI Express Electrical and Timing Characteristics ............................................................................................. 74
3.25.1.
2.5 Gb/s PCIe AC and DC Characteristics .................................................................................................. 74
3.26. CPRI LV2 E.48 Electrical and Timing Characteristics – Preliminary ................................................................... 75
3.27. XAUI/CPRI LV E.30 Electrical and Timing Characteristics .................................................................................. 76
3.27.1.
AC and DC Characteristics ........................................................................................................................ 76
3.28. CPRI LV E.24 Electrical and Timing Characteristics ............................................................................................ 76
3.28.1.
AC and DC Characteristics ........................................................................................................................ 76
3.29. Gigabit Ethernet/SGMII/CPRI LV E.12 Electrical and Timing Characteristics .................................................... 77
3.29.1.
AC and DC Characteristics ........................................................................................................................ 77
3.30. SMPTE SD/HD-SDI/3G-SDI (Serial Digital Interface) Electrical and Timing Characteristics ............................... 78
3.30.1.
AC and DC Characteristics ........................................................................................................................ 78
3.31. ECP5 Automotive sysCONFIG Port Timing Specifications ................................................................................. 79
3.32. JTAG Port Timing Specifications ........................................................................................................................ 84
3.33. Switching Test Conditions ................................................................................................................................. 85
4. Pinout Information ..................................................................................................................................................... 87
4.1.
Signal Descriptions ............................................................................................................................................ 87
4.2.
PICs and DDR Data (DQ) Pins Associated with the DDR Strobe (DQS) Pin ........................................................ 90
4.3.
Pin Information Summary ................................................................................................................................. 91
4.3.1. LAE5UM ........................................................................................................................................................ 91
3.
© 2016-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02014-1.1
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ECP5™ Automotive Family
Data Sheet
4.3.2. LAE5U ............................................................................................................................................................92
Ordering Information ..................................................................................................................................................94
5.1.
ECP5 Automotive Part Number Description .....................................................................................................94
5.2.
Ordering Part Numbers .....................................................................................................................................94
5.2.1. Automotive ...................................................................................................................................................94
Supplemental Information ..................................................................................................................................................95
Revision History ..................................................................................................................................................................96
5.
Figures
Figure 2.1. Simplified Block Diagram of LAE5UM-45 Device (Top Level) ............................................................................11
Figure 2.2. PFU Diagram .....................................................................................................................................................11
Figure 2.3. Slice Diagram ....................................................................................................................................................13
Figure 2.4. Connectivity Supporting LUT5, LUT6, LUT7, and LUT8 .....................................................................................14
Figure 2.5. General Purpose PLL Diagram ...........................................................................................................................17
Figure 2.6. LAE5UM-45 Clocking .........................................................................................................................................18
Figure 2.7. DCS Waveforms ................................................................................................................................................19
Figure 2.8. Edge Clock Sources per Bank ............................................................................................................................20
Figure 2.9. ECP5 Automotive Clock Divider Sources ...........................................................................................................20
Figure 2.10. DDRDLL Functional Diagram ...........................................................................................................................21
Figure 2.11. ECP5 Automotive DLL Top Level View for LAE-45 ...........................................................................................22
Figure 2.12. Memory Core Reset ........................................................................................................................................24
Figure 2.13. Comparison of General DSP and ECP5 Automotive Approaches ....................................................................25
Figure 2.14. Simplified sysDSP Slice Block Diagram ............................................................................................................27
Figure 2.15. Detailed sysDSP Slice Diagram ........................................................................................................................28
Figure 2.16. Group of Four Programmable I/O Cells on Left/Right Side .............................................................................30
Figure 2.17. Input Register Block for PIO on Top Side of the Device ..................................................................................31
Figure 2.18. Input Register Block for PIO on Left or Right Side of the Device ....................................................................31
Figure 2.19. Output Register Block on Top Side .................................................................................................................32
Figure 2.20. Output Register Block on Left or Right Side ....................................................................................................33
Figure 2.21. Tri-state Register Block on Top Side ...............................................................................................................33
Figure 2.22. Tri-state Register Block on Left or Right Side ..................................................................................................34
Figure 2.23. DQS Grouping on the Left and Right Edges ....................................................................................................35
Figure 2.24. DQS Control and Delay Block (DQSBUF) .........................................................................................................36
Figure 2.25. ECP5 Automotive Device Family Banks ...........................................................................................................37
Figure 2.26. On-chip Termination .......................................................................................................................................39
Figure 2.27. SERDES/PCS Duals (LAE5UM-45) ....................................................................................................................40
Figure 2.28. Simplified Channel Block Diagram for SERDES/PCS Block ..............................................................................41
Figure 3.1. LVDS25E Output Termination Example ............................................................................................................54
Figure 3.2. BLVDS25 Multi-point Output Example ..............................................................................................................55
Figure 3.3. Differential LVPECL33 .......................................................................................................................................56
Figure 3.4. MLVDS25 (Multipoint Low Voltage Differential Signaling) ...............................................................................57
Figure 3.5. SLVS Interface ...................................................................................................................................................58
Figure 3.6. Receiver RX.CLK. Centered Waveforms ............................................................................................................66
Figure 3.7. Receiver RX.CLK. Aligned and DDR Memory Input Waveforms ........................................................................66
Figure 3.8. Transmit TX.CLK. Centered and DDR Memory Output Waveforms ..................................................................66
Figure 3.9. Transmit TX.CLK. Aligned Waveforms ...............................................................................................................67
Figure 3.10. DDRX71 Video Timing Waveforms ..................................................................................................................67
Figure 3.11. Receiver DDRX71_RX Waveforms ...................................................................................................................68
Figure 3.12. Transmitter DDRX71_TX Waveforms ..............................................................................................................68
Figure 3.13. Transmitter and Receiver Latency Block Diagram ..........................................................................................71
Figure 3.14. SERDES External Reference Clock Waveforms ................................................................................................73
Figure 3.15. sysCONFIG Parallel Port Read Cycle ................................................................................................................80
© 2016-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
4
FPGA-DS-02014-1.1
ECP5™ Automotive Family
Data Sheet
Figure 3.16. sysCONFIG Parallel Port Write Cycle............................................................................................................... 81
Figure 3.17. sysCONFIG Slave Serial Port Timing ................................................................................................................ 81
Figure 3.18. Power-On-Reset (POR) Timing ........................................................................................................................ 82
Figure 3.19. sysCONFIG Port Timing ................................................................................................................................... 82
Figure 3.20. Configuration from PROGRAMN Timing ......................................................................................................... 83
Figure 3.21. Wake-Up Timing ............................................................................................................................................. 83
Figure 3.22. Master SPI Configuration Waveforms ............................................................................................................ 84
Figure 3.23. JTAG Port Timing Waveforms ......................................................................................................................... 85
Figure 3.24. Output Test Load, LVTTL and LVCMOS Standards .......................................................................................... 85
Tables
Table 1.1. ECP5 Automotive Family Selection Guide ............................................................................................................ 9
Table 2.1. Resources and Modes Available per Slice .......................................................................................................... 12
Table 2.2. Slice Signal Descriptions ..................................................................................................................................... 14
Table 2.3. Number of Slices Required to Implement Distributed RAM .............................................................................. 15
Table 2.4. PLL Blocks Signal Descriptions............................................................................................................................ 17
Table 2.5. DDRDLL Ports List ............................................................................................................................................... 21
Table 2.6. sysMEM Block Configurations ............................................................................................................................ 23
Table 2.7. Maximum Number of Elements in a Slice .......................................................................................................... 29
Table 2.8. Input Block Port ................................................................................................................................................. 32
Table 2.9. Output Block Port Description ........................................................................................................................... 33
Table 2.10. Tri-state Block Port .......................................................................................................................................... 34
Table 2.11. DQSBUF Port Description ................................................................................................................................. 36
Table 2.12. On-Chip Termination Options for Input Modes ............................................................................................... 39
Table 2.13. LAE5UM SERDES Standard Support ................................................................................................................. 41
Table 2.14. Available SERDES Duals per LAE5UM Device ................................................................................................... 41
Table 2.15. LAE5UM Mixed Protocol Support .................................................................................................................... 42
Table 2.16. Selectable Master Clock (MCLK) Frequencies during Configuration (Nominal) ............................................... 44
Table 3.1. Absolute Maximum Ratings ............................................................................................................................... 46
Table 3.2. Recommended Operating Conditions ................................................................................................................ 46
Table 3.3. Power Supply Ramp Rates ................................................................................................................................. 47
Table 3.4. Power-On-Reset Voltage Levels ......................................................................................................................... 47
Table 3.5. Hot Socketing Specifications .............................................................................................................................. 47
Table 3.6. Hot Socketing Requirements ............................................................................................................................. 48
Table 3.7. DC Electrical Characteristics ............................................................................................................................... 48
Table 3.8. Standby ECP5 Automotive Supply Current ........................................................................................................ 49
Table 3.9. ECP5UM Automotive ......................................................................................................................................... 50
Table 3.10. sysI/O Recommended Operating Conditions ................................................................................................... 51
Table 3.11. LVDS ................................................................................................................................................................. 53
Table 3.12. LVDS25E DC Conditions.................................................................................................................................... 54
Table 3.13. BLVDS25 DC Conditions ................................................................................................................................... 55
Table 3.14. LVPECL33 DC Conditions .................................................................................................................................. 56
Table 3.15. MLVDS25 DC Conditions .................................................................................................................................. 57
Table 3.16. Input to SLVS .................................................................................................................................................... 58
Table 3.17. Pin-to-Pin Performance.................................................................................................................................... 59
Table 3.18. Register-to-Register Performance ................................................................................................................... 60
Table 3.19. ECP5 Automotive Maximum I/O Buffer Speed ................................................................................................ 61
Table 3.20. ECP5 Automotive External Switching Characteristics ...................................................................................... 62
Table 3.21. sysCLOCK PLL Timing ........................................................................................................................................ 69
Table 3.22. Serial Output Timing and Levels ...................................................................................................................... 70
Table 3.23. Channel Output Jitter ....................................................................................................................................... 70
© 2016-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02014-1.1
5
ECP5™ Automotive Family
Data Sheet
Table 3.24. SERDES/PCS Latency Breakdown .....................................................................................................................71
Table 3.25. Serial Input Data Specifications ........................................................................................................................72
Table 3.26. Receiver Total Jitter Tolerance Specification ...................................................................................................72
Table 3.27. External Reference Clock Specification (refclkp/refclkn) .................................................................................73
Table 3.28. 2.5 Gb/s PCIe ....................................................................................................................................................74
Table 3.29. CPRI LV2 E.48 Electrical and Timing Characteristics .........................................................................................75
Table 3.30. Transmit ...........................................................................................................................................................76
Table 3.31. Receive and Jitter Tolerance ............................................................................................................................76
Table 3.32. Transmit ...........................................................................................................................................................76
Table 3.33. Receive and Jitter Tolerance ............................................................................................................................77
Table 3.34. Transmit ...........................................................................................................................................................77
Table 3.35. Receive and Jitter Tolerance ............................................................................................................................77
Table 3.36. Transmit ...........................................................................................................................................................78
Table 3.37. Receive .............................................................................................................................................................78
Table 3.38. Reference Clock ...............................................................................................................................................78
Table 3.39. ECP5 Automotive sysCONFIG Port Timing Specifications ................................................................................79
Table 3.40. JTAG Port Timing Specifications .......................................................................................................................84
Table 3.41. Test Fixture Required Components, Non-Terminated Interfaces ....................................................................86
© 2016-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
6
FPGA-DS-02014-1.1
ECP5™ Automotive Family
Data Sheet
Acronyms in This Document
A list of acronyms used in this document.
Acronym
Definition
ALU
Arithmetic Logic Unit
BGA
Ball Grid Array
CDR
Clock and Data Recovery
CRC
Cycle Redundancy Code
DCC
Dynamic Clock Control
DCS
Dynamic Clock Select
DDR
Double Data Rate
DLL
Delay Locked Loops
DSP
Digital Signal Processing
EBR
Embedded Block RAM
ECLK
Edge Clock
FFT
Fast Fourier Transforms
FIFO
First In First Out
FIR
Finite Impulse Response
LVCMOS
Low-Voltage Complementary Metal Oxide Semiconductor
LVDS
Low-Voltage Differential Signaling
LVPECL
Low Voltage Positive Emitter Coupled Logic
LVTTL
Low Voltage Transistor-Transistor Logic
LUT
Look Up Table
MLVDS
Multipoint Low-Voltage Differential Signaling
PCI
Peripheral Component Interconnect
PCS
Physical Coding Sublayer
PCLK
Primary Clock
PDPR
Pseudo Dual Port RAM
PFU
Programmable Functional Unit
PIC
Programmable I/O Cells
PIO
Programmable I/O
PLL
Phase Locked Loops
POR
Power On Reset
SCI
SERDES Client Interface
SCM
Serial Configuration Mode
SEU
Single Event Upset
SLVS
Scalable Low-Voltage Signaling
SPI
Serial Peripheral Interface
SPR
Single Port RAM
SRAM
Static Random-Access Memory
TAP
Test Access Port
TDM
Time Division Multiplexing
© 2016-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02014-1.1
7
ECP5™ Automotive Family
Data Sheet
1. General Description
extract the timing from the routing and back-annotate
it into the design for timing verification.
The ECP5 Automotive family of FPGA devices is
optimized to deliver high performance features such as
an enhanced DSP architecture, high speed SERDES and
high speed source synchronous interfaces in an
economical FPGA fabric. This combination is achieved
through advances in device architecture and the use of
40 nm technology making the devices suitable for
high-volume, high-speed, and low-cost applications.
Lattice Semiconductor provides many pre-engineered
IP (Intellectual Property) modules for the ECP5
Automotive family. By using these configurable soft
core IPs as standardized blocks, designers are free to
concentrate on the unique aspects of the design,
increasing their productivity.
The ECP5 Automotive device family covers
look-up-table (LUT) capacity to 44K logic elements and
supports up to 203 user I/Os. The ECP5 Automotive
device family also offers up to 72 18 x 18 multipliers
and a wide range of parallel I/O standards.
The ECP5 Automotive FPGA fabric is optimized to reach
high performance with low power and low cost in
mind. The ECP5 Automotive devices utilize
reconfigurable SRAM logic technology and provide
popular building blocks such as LUT-based logic,
distributed and embedded memory, Phase Locked
Loops (PLLs), Delay Locked Loops (DLLs),
pre-engineered source synchronous I/O support,
enhanced sysDSP slices and advanced configuration
support, including encryption and dual-boot
capabilities.
1.1. Features
The pre-engineered source synchronous logic
implemented in the ECP5 Automotive device family
supports a broad range of interface standards,
including DDR2/3, LPDDR2/3, XGMII and 7:1 LVDS.
The ECP5 Automotive device family also features high
speed SERDES with dedicated Physical Coding Sublayer
(PCS) functions. High jitter tolerance and low transmit
jitter allow the SERDES plus PCS blocks to be
configured to support an array of popular data
protocols including PCI Express, Ethernet (1GbE, XAUI,
and SGMII), and CPRI. Transmit De-emphasis with
pre- and post-cursors, and Receive Equalization
settings make the SERDES suitable for transmission and
reception over various forms of media.
The ECP5 Automotive devices also provide flexible,
reliable and secure configuration options, such as
dual-boot capability, bit-stream encryption, and
TransFR field upgrade features.
The Lattice Diamond® design software allows large
complex designs to be efficiently implemented using
the ECP5 Automotive FPGA family. Synthesis library
support for ECP5 Automotive devices is available for
popular logic synthesis tools. The Diamond tools use
the synthesis tool output along with the constraints
from its floor planning tools to place and route the
design in the ECP5 Automotive device. The tools
Higher Logic Density for Increased System
Integration
12K to 44K LUTs
197 to 203 user programmable I/Os
Embedded SERDES
270 Mb/s, up to 3.2 Gb/s, SERDES interface
(ECP5UM Automotive)
Supports eDP in RDR (1.62 Gb/s) and HDR
(2.7 Gb/s)
Up to four channels per device: PCI Express,
Ethernet (1GbE, XAUI, and SGMII,), and CPRI
sysDSP™
Fully cascadable slice architecture
12 to 160 slices for high performance multiply
and accumulate
Powerful 54-bit ALU operations
Time Division Multiplexing MAC Sharing
Rounding and truncation
Each slice supports
Half 36 x 36, two 18 x 18 or four
9 x 9 multipliers
Advanced 18 x 36 MAC and
18 x 18 Multiply-Multiply-Accumulate
(MMAC) operations
Flexible Memory Resources
Up to 1.944 Mb sysMEM™ Embedded Block
RAM (EBR)
194K to 351K bits distributed RAM
sysCLOCK Analog PLLs and DLLs
Four DLLs and four PLLs in LAE5-45; two DLLs
and two PLLs in LAE5-25 and LAE5-12
Pre-engineered Source Synchronous I/O
DDR registers in I/O cells
Dedicated read/write levelling functionality
Dedicated gearing logic
Source synchronous standards support
ADC/DAC, 7:1 LVDS, XGMII
High Speed ADC/DAC devices
© 2016-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
8
FPGA-DS-02014-1.1
ECP5™ Automotive Family
Data Sheet
Dedicated DDR2/DDR3 and LPDDR2/LPDDR3
memory support with DQS logic, up to
800 Mb/s data-rate
Programmable sysI/O™ Buffer Supports Wide
Range of Interfaces
On-chip termination
LVTTL and LVCMOS 33/25/18/15/12
SSTL 18/15 I, II
HSUL12
LVDS, Bus-LVDS, LVPECL, RSDS, MLVDS
subLVDS and SLVS, MIPI D-PHY input
interfaces
Flexible Device Configuration
Shared bank for configuration I/Os
SPI boot flash interface
Dual-boot images supported
Slave SPI
TransFR™ I/O for simple field updates
Single Event Upset (SEU) Mitigation Support
Soft Error Detect – Embedded hard macro
Soft Error Correction – Without stopping user
operation
Soft Error Injection – Emulate SEU event to
debug system error handling
System Level Support
IEEE 1149.1 and IEEE 1532 compliant
Reveal Logic Analyzer
On-chip oscillator for initialization and general
use
1.1 V core power supply
Table 1.1. ECP5 Automotive Family Selection Guide
Device
LAE5UM-25
LAE5UM-45
LAE5U-12
LUTs (K)
24
44
12
sysMEM Blocks (18 Kb)
56
108
32
Embedded Memory (Kb)
1,008
1944
576
Distributed RAM Bits (Kb)
194
351
97
18 X 18 Multipliers
28
72
28
SERDES (Dual/Channels)
1/2
2/4
0
PLLs/DLLs
2/2
4/4
2/2
2/197
4/203
0/197
Packages and SERDES Channels / I/O Combinations
381 caBGA (17 x 17 mm2)
© 2016-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02014-1.1
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ECP5™ Automotive Family
Data Sheet
2. Architecture
2.1. Overview
Each ECP5 Automotive device contains an array of logic blocks surrounded by Programmable I/O Cells (PIC).
Interspersed between the rows of logic blocks are rows of sysMEM™ Embedded Block RAM (EBR) and rows of sysDSP™
Digital Signal Processing slices, as shown in Figure 2.1. LAE5-45 devices have two rows. Both LAE5-25 and LAE5-12
devices have one row. In addition, the LAE5UM devices contain SERDES Duals on the bottom of the device.
The Programmable Functional Unit (PFU) contains the building blocks for logic, arithmetic, RAM, and ROM functions.
The PFU block is optimized for flexibility, allowing complex designs to be implemented quickly and efficiently. Logic
Blocks are arranged in a two-dimensional array.
The ECP5 Automotive devices contain one or more rows of sysMEM EBR blocks. sysMEM EBRs are large, dedicated
18 Kb fast memory blocks. Each sysMEM block can be configured in a variety of depths and widths as RAM or ROM. In
addition, ECP5 Automotive devices contain up to three rows of DSP slices. Each DSP slice has multipliers and
adder/accumulators, which are the building blocks for complex signal processing capabilities.
The ECP5 Automotive devices feature up to four embedded 3.2 Gb/s SERDES (Serializer/Deserializer) channels. Each
SERDES channel contains independent 8b/10b encoding/decoding, polarity adjust and elastic buffer logic. Each group
of two SERDES channels, along with its Physical Coding Sublayer (PCS) block, creates a dual DCU (Dual Channel Unit).
The functionality of the SERDES/PCS duals can be controlled by SRAM cell settings during device configuration or by
registers that are addressable during device operation. The registers in every dual can be programmed via the SERDES
Client Interface (SCI). These DCUs (up to two) are located at the bottom of the devices.
Each PIC block encompasses two PIOs, PIO pair, with their respective sysI/O buffers. The sysI/O buffers of the ECP5
Automotive devices are arranged in seven banks allowing the implementation of a wide variety of I/O standards. One
of these banks (Bank 8) is shared with the programming interfaces. 50% of the PIO pairs on the left and right edges of
the device can be configured as LVDS transmit pairs, and all pairs on left and right can be configured as LVDS receive
pairs. The PIC logic in the left and right banks also includes pre-engineered support to aid in the implementation of high
speed source synchronous standards such as XGMII, 7:1 LVDS, along with memory interfaces including DDR3 and
LPDDR3.
The ECP5 Automotive registers in PFU and sysI/O can be configured to be SET or RESET. After power up, the device is
configured and then enters into user mode with these registers SET/RESET according to the configuration setting,
allowing the device entering to a known state for predictable system function.
Other blocks provided PLLs, DLLs, and configuration functions. The ECP5 Automotive architecture provides up to four
Delay Locked Loops (DLLs) and up to four Phase Locked Loops (PLLs). The PLL and DLL blocks are located at the corners
of each device.
The configuration block that supports features such as configuration bit-stream decryption, transparent updates, and
dual-boot support is located at the bottom of each device, to the left of the SERDES blocks. Every device in the ECP5
Automotive family supports a sysCONFIG™ port located in that same corner, powered by VCCIO8, allowing for serial or
parallel device configuration.
In addition, every device in the family has a JTAG port. This family also provides an on-chip oscillator and soft error
detect capability. The ECP5 Automotive devices use 1.1 V as their core voltage.
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10
FPGA-DS-02014-1.1
ECP5™ Automotive Family
Data Sheet
Figure 2.1. Simplified Block Diagram of LAE5UM-45 Device (Top Level)
2.2. PFU Blocks
The core of the ECP5 Automotive device consists of PFU blocks. Each PFU block consists of four interconnected slices
numbered 0 – 3 as shown in Figure 2.2. Each slice contains two LUTs. All the interconnections to and from PFU blocks
are from routing. There are 50 inputs and 23 outputs associated with each PFU block.
The PFU block can be used in Distributed RAM or ROM function, or used to perform Logic, Arithmetic, or ROM
functions. Table 2.1 shows the functions each slice can perform in different modes.
From
Routing
LUT4 &
CARRY
LUT4 &
CARRY
LUT4 &
CARRY
Slice 0
LUT4 &
CARRY
Slice 1
D
FF
LUT4 &
CARRY
D
FF
LUT4 &
CARRY
D
D
FF
FF
LUT4 &
CARRY
Slice 3
Slice 2
D
FF
LUT4 &
CARRY
D
D
FF
FF
D
FF
To
Routing
Figure 2.2. PFU Diagram
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All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02014-1.1
11
ECP5™ Automotive Family
Data Sheet
2.2.1. Slice
Each slice contains two LUT4s feeding two registers. In Distributed SRAM mode, Slice 0 through Slice 2 are configured
as distributed memory, and Slice 3 is used as Logic or ROM. Table 2.1 shows the capability of the slices along with the
operation modes they enable. In addition, each PFU contains logic that allows the LUTs to be combined to perform
functions such as LUT5, LUT6, LUT7, and LUT8. There is control logic to perform set/reset functions, which can be
programmed as synchronous/asynchronous, clock select, chip-select, and wider RAM/ROM functions.
Table 2.1. Resources and Modes Available per Slice
Slice
PFU (Used in Distributed SRAM)
PFU (Not used as Distributed SRAM)
Resources
Modes
Resources
Modes
Slice 0
2 LUT4s and 2 Registers
RAM
2 LUT4s and 2 Registers
Logic, Ripple, ROM
Slice 1
2 LUT4s and 2 Registers
RAM
2 LUT4s and 2 Registers
Logic, Ripple, ROM
Slice 2
2 LUT4s and 2 Registers
RAM
2 LUT4s and 2 Registers
Logic, Ripple, ROM
Slice 3
2 LUT4s and 2 Registers
Logic, Ripple, ROM
2 LUT4s and 2 Registers
Logic, Ripple, ROM
Figure 2.3 shows an overview of the internal logic of the slice. The registers in the slice can be configured for
positive/negative and edge triggered or level sensitive clocks.
Each slice has 14 input signals: 13 signals from routing and 1 signal from the carry-chain routed from the adjacent slice
or PFU. There are five outputs: four to routing and one to carry-chain (to the adjacent PFU). There are two inter
slice/PFU output signals that are used to support wider LUT functions, such as LUT6, LUT7, and LUT8. Table 2.2 and
Figure 2.3 list the signals associated with all the slices. Figure 2.4 shows the connectivity of the inter-slice/PFU signals
that support LUT5, LUT6, LUT7, and LUT8.
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12
FPGA-DS-02014-1.1
ECP5™ Automotive Family
Data Sheet
FCO
FXA
FXB
M1
M0
A1
B1
C1
D1
LUT4 &
CARRY*
F1
F1
FF
Q1
A0
B0
C0
D0
LUT4 &
CARRY*
F0
F0
FF
Q0
CE
CLK
LSR
FCI
From Different Slice/PFU
Notes: For Slices 0 and 1, memory control signals are generated from Slice 2 as follows:
WCK is CLK
WRE is from LSR
DI[3:2] for Slice 1 and DI[1:0] for Slice 0 data from Slice 2
WAD [A:D] is a 4-bit address from slice 2 LUT input
Figure 2.3. Slice Diagram
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FPGA-DS-02014-1.1
13
ECP5™ Automotive Family
Data Sheet
A1
B1
C1
D1
A0
B0
C0
D0
FXB
FXA
Q1
F0
LUT5
Q0
F1
LUT6
Q1
LUT5
F0
Q0
Q1
F0
LUT5
Q0
A1
B1
C1
D1
A0
B0
C0
D0
FXB
FXA
A1
B1
C1
D1
A0
B0
C0
D0
FXB
FXA
F1
LUT7
Q1
LUT5
F0
Q0
F1
LUT6
Q1
LUT5
F0
Q0
A1
B1
C1
D1
A0
B0
C0
D0
FXB
FXA
A1
B1
C1
D1
A0
B0
C0
D0
FXB
FXA
3
SLICE
F0
LUT5
Q0
LUT7 Output
From Previous PFU
F1
LUT6
2
A1
B1
C1
D1
A0
B0
C0
D0
FXB
FXA
Q1
Q1
SLICE
3
SLICE
2
LUT6
LUT8
F0
LUT5
Q0
F1
LUT7
1
LUT7
1
F1
F1
F1
Q1
SLICE
Q0
SLICE
A1
B1
C1
D1
A0
B0
C0
D0
FXB
FXA
F0
LUT5
A1
B1
C1
D1
A0
B0
C0
D0
FXB
FXA
A1
B1
C1
D1
A0
B0
C0
D0
FXB
FXA
F0
LUT5
Q0
F1
LUT6
0
SLICE
Q1
F0
LUT5
Q0
SLICE
LUT6
2
F1
Q1
1
Q0
F1
SLICE
F0
LUT5
PFU Col(n+1)
LUT8
0
SLICE
Q1
A1
B1
C1
D1
A0
B0
C0
D0
FXB
FXA
SLICE
3
LUT8
0
A1
B1
C1
D1
A0
B0
C0
D0
FXB
FXA
PFU Col(n)
F1
SLICE
LUT7 Output
To Next PFU
A1
B1
C1
D1
A0
B0
C0
D0
FXB
FXA
Q1
SLICE
PFU Col(n-1)
LUT5
F0
Q0
Figure 2.4. Connectivity Supporting LUT5, LUT6, LUT7, and LUT8
Table 2.2. Slice Signal Descriptions
Function
Type
Signal Names
Description
Input
Data signal
A0, B0, C0, D0
Inputs to LUT4
Input
Data signal
A1, B1, C1, D1
Inputs to LUT4
Input
Multi-purpose
M0
Multipurpose Input
Input
Multi-purpose
M1
Multipurpose Input
Input
Control signal
CE
Clock Enable
Input
Control signal
LSR
Local Set/Reset
Input
Control signal
CLK
System Clock
Input
Inter-PFU signal
FCI
Fast Carry-in1
Input
Inter-slice signal
FXA
Intermediate signal to generate LUT6, LUT7 and LUT82
Input
Inter-slice signal
FXB
Intermediate signal to generate LUT6, LUT7 and LUT82
Output
Data signals
F0, F1
LUT4 output register bypass signals
Output
Data signals
Q0, Q1
Register outputs
Output
Inter-PFU signal
FCO
Fast carry chain output1
Notes:
1. See Figure 2.3 for connection details.
2. Requires two adjacent PFUs.
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14
FPGA-DS-02014-1.1
ECP5™ Automotive Family
Data Sheet
2.2.2. Modes of Operation
Slices 0 – 2 have up to four potential modes of operation: Logic, Ripple, RAM, and ROM. Slice 3 is not needed for RAM
mode, it can be used in Logic, Ripple, or ROM modes.
Logic Mode
In this mode, the LUTs in each slice are configured as 4-input combinatorial lookup tables. A LUT4 can have 16 possible
input combinations. Any four input logic functions can be generated by programming this lookup table. Since there are
two LUT4s per slice, a LUT5 can be constructed within one slice. Larger look-up tables such as LUT6, LUT7, and LUT8
can be constructed by concatenating other slices. Note that LUT8 requires more than four slices.
Ripple Mode
Ripple mode supports the efficient implementation of small arithmetic functions. In ripple mode, the following
functions can be implemented by each slice:
Addition 2-bit
Subtraction 2-bit
Add/Subtract 2-bit using dynamic control
Up counter 2-bit
Down counter 2-bit
Up/Down counter with asynchronous clear
Up/Down counter with synchronous preload
Ripple mode multiplier building block
Multiplier support
Comparator functions of A and B inputs
A greater-than-or-equal-to B
A not-equal-to B
A less-than-or-equal-to B
Ripple Mode includes an optional configuration that performs arithmetic using fast carry chain methods. In this
configuration, also referred to as CCU2 mode, two additional signals, Carry Generate and Carry Propagate, are
generated on a per slice basis to allow fast arithmetic functions to be constructed by concatenating Slices.
RAM Mode
In this mode, a 16x4-bit distributed single port RAM (SPR) can be constructed in one PFU using each LUT block in Slice 0
and Slice 1 as a 16 x 2-bit memory in each slice. Slice 2 is used to provide memory address and control signals.
A 16 x 2-bit pseudo dual port RAM (PDPR) memory is created in one PFU by using one Slice as the read-write port and
the other companion slice as the read-only port. The slice with the read-write port updates the SRAM data contents in
both slices at the same write cycle.
ECP5 Automotive devices support distributed memory initialization.
The Lattice Semiconductor design tools support the creation of a variety of different size memories. Where
appropriate, the software will construct memories using distributed memory primitives that represent the capabilities
of the PFU. Table 2.3 lists the number of slices required to implement different distributed RAM primitives. For more
information about using RAM in ECP5 Automotive devices, refer to ECP5 and ECP5-5G Memory Usage Guide (TN1264).
Table 2.3. Number of Slices Required to Implement Distributed RAM
Number of slices
SPR 16 X 4
PDPR 16 X 4
3
6
Note: SPR = Single Port RAM, PDPR = Pseudo Dual Port RAM
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FPGA-DS-02014-1.1
15
ECP5™ Automotive Family
Data Sheet
ROM Mode
ROM mode uses the LUT logic; hence, Slices 0 through 3 can be used in ROM mode. Preloading is accomplished
through the programming interface during PFU configuration.
For more information, refer to ECP5 and ECP5-5G Memory Usage Guide (TN1264).
2.3. Routing
There are many resources provided in the ECP5 Automotive devices to route signals individually or as busses with
related control signals. The routing resources consist of switching circuitry, buffers, and metal interconnect segments.
The ECP5 Automotive family has an enhanced routing architecture that produces a compact design. Lattice Diamond
design software tool suites take the output of the synthesis tool and places and routes the design.
2.4. Clocking Structure
ECP5 Automotive clocking structure consists of:
Clock synthesis blocks and sysCLOCK PLL;
Balanced clock tress networks, PCLK, and ECLK trees;
Efficient clock logic modules, CLOCK DIVIDER and Dynamic Clock Select (DCS), Dynamic Clock Control (DCC), and
DLL.
Each of these functions is described as follows.
2.5. sysCLOCK PLL
The sysCLOCK PLLs provide the ability to synthesize clock frequencies. The devices in the ECP5 Automotive family
support two to four full-featured General Purpose PLLs. The sysCLOCK PLLs provide the ability to synthesize clock
frequencies.
The architecture of the PLL is shown in Figure 2.5. Following is the description of the PLL functionality.
CLKI is the reference frequency input to the PLL and its source can come from two different external CLK inputs or
from internal routing. A non-glitchless 2-to-1 input multiplexor is provided to dynamically select between two
different external reference clock sources. The CLKI input feeds into the input Clock Divider block.
CLKFB is the feedback signal to the PLL that can come from internal feedback path, routing or an external I/O pin.
The feedback divider is used to multiply the reference frequency and thus synthesize a higher frequency clock
output.
The PLL has four clock outputs CLKOP, CLKOS, CLKOS2, and CLKOS3. Each output has its own output divider, thus
allowing the PLL to generate different frequencies for each output. The output dividers can have a value from 1 to
128. The CLKOP, CLKOS, CLKOS2, and CLKOS3 outputs can all be used to drive the primary clock network. Only
CLKOP and CLKOS outputs can go to the edge clock network.
The setup and hold times of the device can be improved by programming a phase shift into the CLKOS, CLKOS2,
and CLKOS3 output clocks which will advance or delay the output clock with reference to the CLKOP output clock.
This phase shift can be either programmed during configuration or can be adjusted dynamically using the
PHASESEL, PHASEDIR, PHASESTEP, and PHASELOADREG ports.
The LOCK signal is asserted when the PLL determines it has achieved lock and de-asserted if a loss of lock is
detected.
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16
FPGA-DS-02014-1.1
ECP5™ Automotive Family
Data Sheet
PHASESEL[1:0]
PHASEDIR
PHASESTEP
PHASELOADREG
PLLREFCS
Dynamic
Phase
Adjust
SEL
CLKOP
Divider
(1-128 )
CLKOP
CLKOS
Divider
(1-128 )
CLKOS
VCO
CLKOS2
Divider
(1-128 )
CLKOS2
VCO
CLKOS3
Divider
(1-128 )
CLKOS3
VCO
Refclk
CLK0
PLLCSOUT
CLKI
CLKI2
CLK1
Refclk Divider M
CLKI
Phase
Detector,
VCO, and
Loop Filter
FBKSEL
CLKFB
Feedback
Clock Divider
VCO
Internal Feedback
CLKOP, CLKOS, CLKOS2, CLKOS3
ENCLKOP
ENCLKOS
ENCLKOS2
ENCLKOS3
RST
STDBY
Lock
Detect
LOCK
Figure 2.5. General Purpose PLL Diagram
Table 2.4 provides a description of the signals in the PLL blocks.
Table 2.4. PLL Blocks Signal Descriptions
Signal
Type
Description
CLKI
Input
Clock Input to PLL from external pin or routing
CLKI2
Input
Muxed clock input to PLL
SEL
Input
Input Clock select, selecting from CLKI and CLKI2 inputs
CLKFB
Input
PLL Feedback Clock
PHASESEL[1:0]
Input
Select which output to be adjusted on Phase by PHASEDIR, PHASESTEP, PHASELODREG
PHASEDIR
Input
Dynamic Phase adjustment direction
PHASESTEP
Input
Dynamic Phase adjustment step
PHASELOADREG
Input
Load dynamic phase adjustment values into PLL
CLKOP
Output
Primary PLL output clock with phase shift adjustment
CLKOS
Output
Secondary PLL output clock with phase shift adjust
CLKOS2
Output
Secondary PLL output clock2 with phase shift adjust
CLKOS3
Output
Secondary PLL output clock3 with phase shift adjust
LOCK
Output
PLL LOCK to CLKI, Asynchronous signal. Active high indicates PLL lock.
STDBY
Input
Standby signal to power down the PLL
RST
Input
Resets the PLL
ENCLKOP
Input
Enable PLL output CLKOP
ENCLKOS
Input
Enable PLL output CLKOS
ENCLKOS2
Input
Enable PLL output CLKOS2
ENCLKOS3
Input
Enable PLL output CLKOS3
For more details on the PLL, you can refer to ECP5 and ECP5-5G sysClock PLL/DLL Design and Usage Guide (TN1263).
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FPGA-DS-02014-1.1
17
ECP5™ Automotive Family
Data Sheet
2.6. Clock Distribution Network
There are two main clock distribution networks for any member of the ECP5 Automotive product family, namely
Primary Clock (PCLK) and Edge Clock (ECLK). These clock networks have the clock sources come from many different
sources, such as Clock Pins, PLL outputs, DLLDEL outputs, Clock divider outputs, SERDES/PCS clocks and some on chip
generated clock signal. There are clock dividers (CLKDIV) blocks to provide the slower clock from these clock sources.
ECP5 Automotive also supports glitchless dynamic enable function (DCC) for the PCLK Clock to save dynamic power.
There are also some logics to allow dynamic glitchless selection between two clocks for the PCLK network (DCS).
Overview of Clocking Network is shown in Figure 2.6, for LAE5UM-45 device.
PIO
PLL
12 DCC
Bank 7
Edge Clocks
PLL
Quadrant TL
Primary
Clocks
12 Primary Sources
16
PIO
PIO
DLL
14 DCC
14 Primary Sources
14 Primary Sources
Fabric
Entry
Fabric
Entry
16
14
Primary
Clocks
PCSCLKDIV
PCSCLKDIV
SERDES DCU0
CLK
DIV
CLK
DIV
PLL
Mid
MUX
Bank 8
Mid
MUX
Quadrant BR
16 DCC
PLL
DLL
14 DCC
Center MUX
16 Primary Sources
Quadrant BL
Quadrant TR
Edge Clocks
Bank 6
16
Primary
Clocks
Bank 3
Primary
Clocks
16
PIO
PIO
14
Fabric
Entry
PIO
Mid
MUX
Fabric
Entry
PIO
PIO
Bank 1
PIO
Edge Clocks
PIO
Bank 2
CLK
DIV
PIO
Mid
MUX
Edge Clocks
CLK
DIV
PIO
Bank 0
DLL
SERDES DCU1
Bank 4
DLL
Figure 2.6. LAE5UM-45 Clocking
2.7. Primary Clocks
The ECP5 Automotive device family provides low-skew, high fanout clock distribution to all synchronous elements in
the FPGA fabric through the Primary Clock Network.
The primary clock network is divided into four clocking quadrants: Top Left (TL), Bottom Left (BL), Top Right (TR), and
Bottom Right (BR). Each of these quadrants has 16 clocks that can be distributed to the fabric in the quadrant.
The Lattice Diamond software can automatically route each clock to one of the four quadrants up to a maximum of 16
clocks per quadrant. The user can change how the clocks are routed by specifying a preference in Lattice Diamond
software to locate the clock to specific quadrant. The ECP5 Automotive device provides the user with a maximum of 64
unique clock input sources that can be routed to the primary Clock network.
Primary clock sources are:
Dedicated clock input pins
PLL outputs
CLKDIV outputs
Internal FPGA fabric entries with minimum general routing
SERDES/PCS/PCSDIV clocks
OSC clock
These sources are routed to one of the four clock switches called the Mid MUX. The outputs of the Mid MUX are
routed to the center of the FPGA where another clock switch, called the Center MUX, is used to route the primary clock
sources to primary clock distribution to the ECP5 Automotive fabric. These routing muxes are shown in Figure 2.6. Since
there is a maximum of 60 unique clock input sources to the clocking quadrants, there are potentially 64 unique clock
domains that can be used in the ECP5 Automotive device. For more information about the primary clock tree and
connections, refer to ECP5 and ECP5-5G sysClock PLL/DLL Design and Usage Guide (TN1263).
© 2016-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
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18
FPGA-DS-02014-1.1
ECP5™ Automotive Family
Data Sheet
2.8. Dynamic Clock Control
The Dynamic Clock Control (DCC), Quadrant Clock enable/disable feature allows internal logic control of the quadrant
primary clock network. When a clock network is disabled, the clock signal is static and not toggle. All the logic fed by
that clock will not toggle, reducing the overall power consumption of the device. The disable function will not create
glitch and increase the clock latency to the primary clock network.
This DCC controls the clock sources from the Primary CLOCK MIDMUX before they are fed to the Primary Center MUXs
that drive the quadrant clock network. For more information about the DCC, refer to ECP5 and ECP5-5G sysCLOCK
PLL/DLL Design and Usage Guide (TN1263).
2.9. Dynamic Clock Select
The Dynamic Clock Select (DCS) is a smart multiplexer function available in the primary clock routing. It switches
between two independent input clock sources. Depending on the operation modes, it switches between two
independent input clock sources either with or without any glitches. This is achieved regardless of when the selected
signal is toggled. Both input clocks must be running to achieve functioning glitch-less DCS output clock, but it does not
require running clocks when being used as non-glitch-less normal clock multiplexer.
There are two DCS blocks per device that are fed to all quadrants. The inputs to the DCS block come from all the output
of MIDMUXs and Clock from CIB located at the center of the PLC array core. The output of the DCS is connected to one
of the inputs of Primary Clock Center MUX.
Figure 2.7 shows the timing waveforms of the default DCS operating mode. The DCS block can be programmed to other
modes. For more information about the DCS, refer to ECP5 and ECP5-5G sysCLOCK PLL/DLL Design and Usage Guide
(TN1263).
CLK0
CLK1
SEL
CLKO
Figure 2.7. DCS Waveforms
2.10. Edge Clock
ECP5 Automotive devices have a number of high-speed edge clocks that are intended for use with the PIOs in the
implementation of high-speed interfaces. There are two ECLK networks per bank IO on the Left and Right sides of the
devices.
Each Edge Clock can be sourced from the following:
Dedicated Clock input pins (PCLK)
DLLDEL output (Clock delayed by 90°)
PLL outputs (CLKOP and CLKOS)
ECLKBRIDGE
Internal Nodes
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FPGA-DS-02014-1.1
19
ECP5™ Automotive Family
Data Sheet
Top Left / Right PCLK Pin
From ECLK of
other bank on
same side
Top Left / Right DLLDEL Output
Top Right / Left PLL CLKOP
From
ECLKBRIDGE
Top Right / Left PLL CLKOS
ECLK Tree
ECLKSYNC
Bottom Right / Left PLL CLKOP
Bottom Right / Left PLL CLKOS
Bottom Left / Right PCLK Pin
To ECLK of other
bank on same side
Bottom Left / Right DLLDEL Output
To ECLKBRIDGE
to go to other side
From Routing
Figure 2.8. Edge Clock Sources per Bank
The edge clocks have low injection delay and low skew. They are used for DDR Memory or Generic DDR interfaces. For
detailed information on Edge Clock connections, refer to ECP5 and ECP5-5G sysCLOCK PLL/DLL Design and Usage Guide
(TN1263).
2.11. Clock Dividers
ECP5 Automotive devices have two clock dividers, one on the left side and the other on the right side of the device.
These are intended to generate a slower-speed system clock from a high-speed edge clock. The block operates in a ÷2,
÷3.5 mode and maintains a known phase relationship between the divided down clock and the high-speed clock based
on the release of its reset signal.
The clock dividers can be fed from selected PLL outputs, external primary clock pins multiplexed with the DDRDEL Slave
Delay or from routing. The clock divider outputs serve as primary clock sources and feed into the clock distribution
network. The Reset (RST) control signal resets input and asynchronously forces all outputs to low. The SLIP signal slips
the outputs one cycle relative to the input clock. For further information on clock dividers, refer to ECP5 and ECP5-5G
sysCLOCK PLL/DLL Design and Usage Guide (TN1263). Figure 2.9 shows the clock divider connections.
Primary Clock Pin OR
DLLDEL output clock
PLL clock output
(CLKOP/CLKOS)
Primary
Clock Tree
OR Routing
CLKDIV
(/2 or /3.5)
To Primary Clock Tree
OR Routing
RST
SLIP
Figure 2.9. ECP5 Automotive Clock Divider Sources
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Data Sheet
2.12. DDRDLL
Every DDRDLL (master DLL block) can generate phase shift code representing the amount of delay in a delay block that
corresponding to 90-degree phase of the reference clock input. The reference clock can be either from PLL, or input
pin. This code is used in the DQSBUF block that controls a set of DQS pin groups to interface with DDR memory (slave
DLL). There are two DDRDLLs that supply two sets of codes (for two different reference clock frequencies) to each side
of the I/Os (at each of the corners). The DQSBUF uses this code to controls the DQS input of the DDR memory to
90-degree shift to clock DQs at the center of the data eye for DDR memory interface.
The code is also sent to another slave DLL and DLLDEL, which takes a clock input, and generates a 90-degree shift clock
output to drive the clocking structure. This is useful to interface edge-aligned Generic DDR, where 90-degree clocking
needs to be created. Figure 2.10 shows DDRDLL functional diagram.
DDRDLL
CLK
DDRDEL
RST
LOCK
UDDCNTLN
DCNTL[7:0]
FREEZE
Figure 2.10. DDRDLL Functional Diagram
Table 2.5. DDRDLL Ports List
Port Name
Type
Description
CLK
Input
Reference clock input to the DDRDLL. Should run at the same frequency as the clock to the
delayed.
RST
Input
Reset Input to the DDRDLL.
UDDCNTLN
Input
FREEZE
Input
DDRDEL
Output
Update Control to update the delay code. When UDDCNTLN goes LOW, the delay code out the
DDRDLL is updated. Should not be active during a read or a write cycle.
FREEZE goes HIGH and, without a glitch, turns off the DLL internal clock and the ring oscillator
output clock. When FREEZE goes LOW, it turns them back on.
The delay codes from the DDRDLL to be used in DQSBUF or DLLDEL.
LOCK
Output
Lock output to indicate the DDRDLL has valid delay output.
DCNTL [7:0]
Output
The delay codes from the DDRDLL available for the user IP.
There are identical DDRDLLs, four in each corner in LAE5-45 device and two in upper corners in both LAE5-25 and
LAE5-12 devices. Each DDRDLL can generate delay code based on the reference frequency. The slave DLL, DQSBUF, and
DLLDEL use the code to delay the signal, to create the phase shifted signal used for either DDR memory, or to create
90-degree shift clock. Figure 2.11 shows the DDRDLL and the slave DLLs on the top level view.
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FPGA-DS-02014-1.1
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Data Sheet
ASICIO
Buffer
ASICIO
Buffer
DDR DLL
DDR DLL
PIC
PIC
PIC
PIC
PIC
PIC
PIC
PIC
DLLDEL
LFE5 Device
DQSBUF
sysIO Buffer
DLLDEL
DDR DLL
sysIO Buffer
DLLDEL
sysIO Buffer
DLLDEL
DQSBUF
PIC
DQSBUF
DQSBUF
sysIO Buffer
PIC
DLLDEL
DLLDEL
PIC
PIC
PIC
PIC
PIC
PIC
Config IO
SERDES Block
DDR DLL
Figure 2.11. ECP5 Automotive DLL Top Level View for LAE-45
2.13. sysMEM Memory
ECP5 Automotive devices contain a number of sysMEM Embedded Block RAM (EBR). The EBR consists of an 18 Kb RAM
with memory core, dedicated input registers and output registers with separate clock and clock enable. Each EBR
includes functionality to support true dual-port, pseudo dual-port, single-port RAM, ROM, and FIFO buffers via external
PFUs.
2.13.1. sysMEM Memory Block
The sysMEM block can implement single port, dual port or pseudo dual port memories. Each block can be used in a
variety of depths and widths as listed in Table 2.6. FIFOs can be implemented in sysMEM EBR blocks by implementing
support logic with PFUs. The EBR block facilitates parity checking by supporting an optional parity bit for each data
byte. EBR blocks provide byte-enable support for configurations with 18-bit and 36-bit data widths. For more
information, refer to ECP5 and ECP5-5G Memory Usage Guide (TN1264).
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Data Sheet
Table 2.6. sysMEM Block Configurations
Memory Mode
Configurations
16,384 x 1
8,192 x 2
Single Port
4,096 x 4
2,048 x 9
1,024 x 18
512 x 36
16,384 x 1
8,192 x 2
True Dual Port
4,096 x 4
2,048 x 9
1,024 x 18
16,384 x 1
8,192 x 2
Pseudo Dual Port
4,096 x 4
2,048 x 9
1,024 x 18
512 x 36
2.13.2. Bus Size Matching
All of the multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB word
0 to MSB word 0, LSB word 1 to MSB word 1, and so on. Although the word size and number of words for each port
varies, this mapping scheme applies to each port.
2.13.3. RAM Initialization and ROM Operation
If desired, the contents of the RAM can be pre-loaded during device configuration. By preloading the RAM block during
the chip configuration cycle and disabling the write controls, the sysMEM block can also be utilized as a ROM.
2.13.4. Memory Cascading
Larger and deeper blocks of RAM can be created using EBR sysMEM Blocks. Typically, the Lattice Semiconductor design
tools cascade memory transparently, based on specific design inputs.
2.13.5. Single, Dual and Pseudo-Dual Port Modes
In all the sysMEM RAM modes the input data and address for the ports are registered at the input of the memory
array. The output data of the memory is optionally registered at the output.
EBR memory supports the following forms of write behavior for single port or dual port operation:
Normal – Data on the output appears only during a read cycle. During a write cycle, the data at the current address
does not appear on the output. This mode is supported for all data widths.
Write Through – A copy of the input data appears at the output of the same port during a write cycle. This mode is
supported for all data widths.
Read-Before-Write – When new data is written, the old content of the address appears at the output. This mode is
supported for x9, x18, and x36 data widths.
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Data Sheet
2.13.6. Memory Core Reset
The memory array in the EBR utilizes latches at the A and B output ports. These latches can be reset asynchronously or
synchronously. RSTA and RSTB are local signals, which reset the output latches associated with Port A and Port B,
respectively. The Global Reset (GSRN) signal can reset both ports. The output data latches and associated resets for
both ports are as shown in Figure 2.12.
Memory Core
D
SET
Q
Port A[17:0]
LCLR
Output Data
Latches
D
SET
Q
Port B[17:0]
LCLR
RSTA
RSTB
GSRN
Programmable Disable
Figure 2.12. Memory Core Reset
For further information on the sysMEM EBR block, see the list of technical documentation in the Supplemental
Information section.
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Data Sheet
2.14. sysDSP™ Slice
The ECP5 Automotive family provides an enhanced sysDSP architecture, making it ideally suited for low-cost,
high-performance Digital Signal Processing (DSP) applications. Typical functions used in these applications are Finite
Impulse Response (FIR) filters, Fast Fourier Transforms (FFT) functions, Correlators, Reed-Solomon/Turbo/Convolution
encoders and decoders. These complex signal processing functions use similar building blocks such as multiply-adders
and multiply-accumulators.
2.14.1. sysDSP Slice Approach Compared to General DSP
Conventional general-purpose DSP chips typically contain one to four (Multiply and Accumulate) MAC units with fixed
data-width multipliers; this leads to limited parallelism and limited throughput. Their throughput is increased by higher
clock speeds. In the ECP5 Automotive device family, there are many DSP slices that can be used to support different
data widths. This allows designers to use highly parallel implementations of DSP functions. Designers can optimize DSP
performance vs. area by choosing appropriate levels of parallelism. Figure 2.13 compares the fully serial
implementation to the mixed parallel and serial implementation.
Operand
A
Operand
A
Operand
B
Operand
A
Single
Multiplier
Operand
A
Operand
B
Operand
B
Operand
B
x
M loops
x
Multiplier
0
x
x
Multiplier
1
m/k
loops
Multiplier
k
Accumulator
Function Implemented in
General Purpose DSP
(k adds)
+
m/k
accumulate
Output
Function Implemented in ECP5 Automative
Figure 2.13. Comparison of General DSP and ECP5 Automotive Approaches
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FPGA-DS-02014-1.1
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ECP5™ Automotive Family
Data Sheet
2.15. ECP5 Automotive sysDSP Slice Architecture Features
The ECP5 Automotive sysDSP Slice is significantly enhanced to provide functions needed for advanced processing
applications. These enhancements provide improved flexibility and resource utilization.
The ECP5 Automotive sysDSP Slice supports many functions that include the following:
Fully double data rate support. Higher operation frequency (throughput of up to 370 Mb/s) is achieved by double
input and output interfaces that enable twice the fabric operation throughput for most of the operation modes.
Symmetry support. The primary target application is wireless. 1D Symmetry is useful for many applications that
use FIR filters when their coefficients have symmetry or asymmetry characteristics. The main motivation for using
1D symmetry is cost/size optimization. The expected size reduction is up to 2x.
Odd mode – Filter with Odd number of taps
Even mode – Filter with Even number of taps
Two dimensional (2D) symmetry mode – Supports 2D filters for mainly video applications
Dual-multiplier architecture. Lower accumulator overhead to half and the latency to half compared to single
multiplier architecture.
Fully cascadable DSP across slices. Support for symmetric, asymmetric, and non-symmetric filters.
Multiply function supports one 18x36, two 18x18, or four 9x9 multipliers per slice.
Multiply function with the 36x36 multiplier uses two sysDSP slices.
Multiply Accumulate supports one 18x36 multiplier result accumulation or two 18x18 multiplier result
accumulation
Two multipliers feeding one Accumulate per cycle for increased processing with lower latency (two 18x18
multipliers feed into an accumulator that can accumulate up to 52 bits)
Pipeline registers
1D Symmetry support. The coefficients of FIR filters have symmetry or negative symmetry characteristics.
Odd mode – Filter with Odd number of taps
Even mode – Filter with Even number of taps
2D Symmetry support. The coefficients of 2D FIR filters have symmetry or negative symmetry characteristics.
3*3 and 3*5 – Internal DSP Slice support
5*5 and larger size 2D blocks – Semi-internal DSP Slice support
Flexible saturation and rounding options to satisfy a diverse set of applications situations
Flexible cascading across DSP slices
Minimizes fabric use for common DSP and ALU functions
Enables implementation of FIR Filter or similar structures using dedicated sysDSP slice resources only
Provides matching pipeline registers
Can be configured to continue cascading from one row of sysDSP slices to another for longer cascade chains
Flexible and Powerful Arithmetic Logic Unit (ALU) supports:
Dynamically selectable ALU OPCODE
Ternary arithmetic addition/subtraction of three inputs
Bit-wise two-input logic operations such as AND, OR, NAND, NOR, XOR, and XNOR
Eight flexible and programmable ALU flags that can be used for multiple pattern detection scenarios, such as
overflow, underflow and convergent rounding.
Flexible cascading across slices to get larger functions
RTL Synthesis friendly synchronous reset on all registers, while still supporting asynchronous reset for legacy users
Dynamic MUX selection to allow Time Division Multiplexing (TDM) of resources for applications that require
processor-like flexibility that enables different functions for each clock cycle
For most cases, as shown in Figure 2.14, the ECP5 Automotive sysDSP slice is backwards-compatible with the
LatticeECP2™ and LatticeECP3™ sysDSP block, such that, legacy applications can be targeted to the ECP5 Automotive
sysDSP slice. Figure 2.14 shows the diagram of sysDSP. Figure 2.15 shows the detailed diagram.
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Data Sheet
ALU24
ALU24
ALU24
PR0 (36)
PR1 (36)
PR2 (36)
PR3 (36)
9x9
9x9
Mult18-1
9x9
Mult18-2
9x9
9x9
One of these
Mult18-0
9x9
Mult18-1
36x36 (Mult36)
In Reg B 1
9+/-9
9+/-9
9+/-9
In Reg A 1
In Reg B 0
In Reg B 1
9+/-9
18+/-18
MUA1[17:0]
MUB0[17:0]
MUA0[17:0]
C0[53:0]
18+/-18
9+/-9
In Reg A 0
9+/-9
9+/-9
18+/-18
Casc
A1
9+/-9
18+/-18
MUB3[17:0]
In Reg B 0
Casc
A0
MUA3[17:0]
In Reg A 1
MUA2[17:0]
18
In Reg A 0
SIGNEDA[3:0]
SIGNEDB[3:0]
SOURCEA[3:0]
SOURCEB[3:0]
GSR
MUB2[17:0]
18
Flags[7:0]
18
18
SROA[17:0]
SROB[17:0]
One of these
9x9
COUT[53:0] (hardwired
cascade to right DSP)
To DSP
Block on
Right and to
CIB Outputs
C0[53:0]
9x9
One of these
OutB3 (18)
OutA3 (18)
MUP3[17:0]
MUP2[35:18]
OutB2 (18)
OutA2 (18)
MUP2[17:0]
MUP1[35:18]
OutB1 (18)
OutA1 (18)
Accumulator/ALU (54)
ALU24
MUB1[17:0]
SRIA[17:0]
SRIB[17:0]
Hardwired from DSP
Block on Left
OutB0 (18)
Accumulator/ALU (54)
CLK[3:0]
CE[3:0]
RST[3:0]
DYNOP0[10:0],
DYNOP1[10:0]
MUP1[17:0]
MUP0[35:18]
MUP0[17:0]
OutA0 (18)
CIN[53:0] (hardwired
cascade from left DSP)
MUP3[35:18]
SLICE 1
SLICE 0
Figure 2.14. Simplified sysDSP Slice Block Diagram
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FPGA-DS-02014-1.1
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Data Sheet
MUIA0
MUIB0
INT_A
OPCODE_PA
MUIA1 MUIB1
INT_B
IR
INT_B
SRIBK_PA
IR
IR
IR
IR
+/=
DYNOP
OPA1
SROA
SRIA
IR
IR
IR
IR
SRIB
IR
MULTA
SROB
MULTB
IR
IR
PR
PR
PR
B ALU
A ALU
0
0
AMUX
Shift 18L
BMUX
R= A ± B ± C
R = Logic (B, C)
CMUX
C_ALU
CIN
DSP
PreAdder
Logic
+/-
OPA0
C
INT_A
COUT
ALU
==
OR
OR
FR
OR
DSP
Core
Logic
MUOP0
R
FLAGS
MUOP1
DSP SLICE
Figure 2.15. Detailed sysDSP Slice Diagram
In Figure 2.15, note that A_ALU, B_ALU and C_ALU are internal signals generated by combining bits from AA, AB, BA BB
and C inputs. For further information, refer to ECP5 and ECP5-5G sysDSP Usage Guide (TN1267).
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Data Sheet
The ECP5 Automotive sysDSP block supports the following basic elements:
MULT (Multiply)
MAC (Multiply, Accumulate)
MULTADDSUB (Multiply, Addition/Subtraction)
MULTADDSUBSUM (Multiply, Addition/Subtraction, Summation)
Table 2.7 shows the capabilities of each of the ECP5 Automotive slices versus the above functions.
Table 2.7. Maximum Number of Elements in a Slice
Width of Multiply
x9
x18
x36
MULT
4
2
1/2
MAC
1
1
—
MULTADDSUB
2
1
—
MULTADDSUBSUM
1*
1/2
—
*Note: One slice can implement 1/2 9x9 m9x9addsubsum and two m9x9addsubsum with two slices.
Some options are available in the above four elements. The input register in all the elements can be directly loaded or
can be loaded as a shift register from previous operand registers. By selecting “dynamic operation”, the following
operations are possible:
In the Add/Sub option, the Accumulator can be switched between addition and subtraction on every cycle.
The loading of operands can switch between parallel and serial operations.
For further information, refer to ECP5 and ECP5-5G sysDSP Usage Guide (TN1267).
2.16. Programmable I/O Cells
The programmable logic associated with an I/O is called a PIO. The individual PIO is connected to their respective sysIO
buffers and pads. On the ECP5 Automotive devices, the Programmable I/O cells (PIC) are assembled into groups of four
PIO cells that are called a Programmable I/O Cell or PIC. The PICs are placed on all four sides of the device.
On all the ECP5 Automotive devices, two adjacent PIOs can be combined to provide a complementary output driver
pair. All PIO pairs can implement differential receivers. Half of the PIO pairs on the left and right edges of these devices
can be configured as true LVDS transmit pairs.
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FPGA-DS-02014-1.1
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Data Sheet
1 PIC
PIO A
Input
Register
Block
Output and
Tristate
Register
Block
Pin A
PIO B
Input
Register
Block
Input
Gearbox
Core
Logic /
Routing
Output
Gearbox
Output and
Tristate
Register
Block
Pin B
PIO C
Input
Register
Block
Output and
Tristate
Register
Block
Pin C
PIO D
Input
Register
Block
Output and
Tristate
Register
Block
Pin D
Figure 2.16. Group of Four Programmable I/O Cells on Left/Right Side
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Data Sheet
2.17. PIO
The PIO contains three blocks: an input register block, an output register block, and a tri-state register block. These
blocks contain registers for operating in a variety of modes along with the necessary clock and selection logic.
2.17.1. Input Register Block
The input register blocks for the PIOs on all edges contain delay elements and registers that can be used to condition
high-speed interface signals before they are passed to the device core. In addition, the input register blocks for the
PIOs on the left and right edges include built-in FIFO logic to interface to DDR and LPDDR memory.
The Input register block on the right and left sides includes gearing logic and registers to implement IDDRX1 and
IDDRX2 functions. With two PICs sharing the DDR register path, it can also implement IDDRX71 function used for 7:1
LVDS interfaces. It uses three sets of registers – shift, update, and transfer to implement gearing and the clock domain
transfer. The first stage registers sample the high-speed input data by the high-speed edge clock on its rising and falling
edges. The second stage registers perform data alignment based on the control signals. The third stage pipeline
registers pass the data to the device core synchronized to the low-speed system clock. The Top side of the device will
support IDDRX1 gearing function. For more information on gearing function, refer to ECP5 and ECP5-5G High-Speed I/O
Interface (TN1265) Technical Note.
Figure 2.17 shows the input register block for the PIOs on the top edge.
INCK
INFF
Programmable
Delay Cell
D
Q
INFF
IDDRX1
SCLK
RST
Q[1:0]
Figure 2.17. Input Register Block for PIO on Top Side of the Device
Figure 2.18 shows the input register block for the PIOs located on the left and right edges.
INCK
INFF
Programmable
Delay Cell
D
INFF
Q
FIFO
Delayed DQS
ECLK
SCLK
RST
ALIGNWD
ECLK
Generic
IDDRX1
IDDRX2
IDDRX71*
Q[1:0]/
Q[3:0]/
Q[6:0]*
Memory
IDDRX2
*Note: For 7:1 LVDS interface only. It is required to use PIO pair pins (PIOA/B or PIOC/D).
Figure 2.18. Input Register Block for PIO on Left or Right Side of the Device
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Data Sheet
2.17.1.1. Input FIFO
The ECP5 Automotive PIO has dedicated input FIFO per single-ended pin for input data register for DDR Memory
interfaces. The FIFO resides before the gearing logic. It transfers data from DQS domain to continuous ECLK domain. On
the Write side of the FIFO, it is clocked by DQS clock which is the delayed version of the DQS Strobe signal from DDR
memory. On the Read side of FIFO, it is clocked by ECLK. ECLK may be any high speed clock with identical frequency as
DQS (the frequency of the memory chip). Each DQS group has one FIFO control block. It distributes FIFO read/write
pointer to every PIC in same DQS group. DQS Grouping and DQS Control Block is described in DDR Memory Support
section.
Table 2.8. Input Block Port
Name
Type
Description
D
Input
High speed data input
Q[1:0]/Q[3:0]/Q[6:0]
Output
Low speed data to the device core
RST
Input
Reset to the output block
SCLK
Input
Slow speed system clock
ECLK
Input
High speed edge clock
DQS
Input
Clock from DQS control block used to clock DDR memory data
ALIGNWD
Input
Data alignment signal from device core
2.17.2. Output Register Block
The output register block registers signals from the core of the device before they are passed to the sysIO buffers.
ECP5 Automotive output data path has output programmable flip flops and output gearing logic. On the left and right
sides the output register block can support 1x, 2x and 7:1 gearing enabling high speed DDR interfaces and DDR memory
interfaces. On the top side, the banks will support 1x gearing. ECP5 Automotive output data path diagram is shown in
Figure 2.19. The programmable delay cells are also available in the output data path.
For detailed description of the output register block modes and usage, refer to ECP5 and ECP5-5G High-Speed I/O
Interface (TN1265) Technical Note.
Programmable
Delay Cell
D
OUTFF
RST
SCLK
D[1:0]
Q
Generic
ODDRX1
Figure 2.19. Output Register Block on Top Side
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FPGA-DS-02014-1.1
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Data Sheet
Programmable
Delay Cell
D
OUTFF
RST
SCLK
Q
Generic
ODDRX1/
ODDRX2/
ODDR71*
ECLK
DQSW
DQSW270
Memory
ODDRX2
OSHX2
D[1:0]/
D[3:0]/
D[6:0]*
*Note: For 7:1 LVDS interf ace only. It is required to use PIO pair pins PIOA/B.
Figure 2.20. Output Register Block on Left or Right Side
Table 2.9. Output Block Port Description
Name
Type
Description
Q
Output
High Speed Data Output
D
Input
Data from core to output SDR register
D[1:0]/D[3:0]/ D[6:0]
Input
Low Speed Data from device core to output DDR register
RST
Input
Reset to the Output Block
SCLK
Input
Slow Speed System Clock
ECLK
Input
High Speed Edge Clock
DQSW
Input
Clock from DQS control Block used to generate DDR memory DQS output
DQSW270
Input
Clock from DQS control Block used to generate DDR memory DQ output
2.18. Tri-state Register Block
The tri-state register block registers tri-state control signals from the core of the device before they are passed to the
sysIO buffers. The block contains a register for SDR operation. In SDR, TD input feeds one of the flip-flops, which feeds
the output. DDR memory interface can be implemented on the left and right sides of the device. Here two inputs feed
the tri-state registers clocked by both ECLK and SCLK.
Figure 2.21 and Figure 2.22 show the Tri-state Register Block functions on the device. For detailed description of the
tri-state register block modes and usage, refer to ECP5 and ECP5-5G High-Speed I/O Interface (TN1265) Technical Note.
TQ
TD
RST
SCLK
TSFF
Figure 2.21. Tri-state Register Block on Top Side
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FPGA-DS-02014-1.1
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ECP5™ Automotive Family
Data Sheet
TQ
TD
TSFF
RST
SCLK
ECLK
THSX2
DQSW
DQSW270
T[1:0]
Figure 2.22. Tri-state Register Block on Left or Right Side
Table 2.10. Tri-state Block Port
Name
Type
Description
TD
Input
Tri-state Input to Tri-state SDR register
RST
Input
Reset to the Tristate block
TD[1:0]
Input
Tri-state input to TSHX2 function
SCLK
Input
Slow Speed system clock
ECLK
Input
High speed edge clock
DQSW
Input
Clock from DQS control block used to generate DDR memory DQS output
Input
Clock from DQS control block used to generate DDR memory DQ output
DQSW270
TQ
Output
Output of the Tri-state block
2.19. DDR Memory Support
2.19.1. DQS Grouping for DDR Memory
Some PICs have additional circuitry to allow the implementation of high-speed source synchronous and DDR2, DDR3,
LPDDR2 or LPDDR3 memory interfaces. The support varies by the edge of the device as detailed below.
The left and right sides of the PIC have fully functional elements supporting DDR2, DDR3, LPDDR2 or LPDDR3 memory
interfaces. Every 16 PIOs on the left and right sides are grouped into one DQS group, as shown in Figure 2.23. Within
each DQS group, there are two pre-placed pins for DQS and DQS# signals. The rest of the pins in the DQS group can be
used as DQ signals and DM signal. The number of pins in each DQS group bonded out is package dependent. DQS
groups with less than 11 pins bonded out can only be used for LPDDR2/3 Command/ Address busses. For DQS groups
with more than 11 pins bonded out, two pre-defined pins can be assigned as "virtual" VCCIO by driving these pins to
HIGH. These pins are required to be connected to VCCIO power supply. These connections create "soft" connections to
VCCIO through these output pins, and make better connections on VCCIO to help to reduce SSO noise. For details, refer
to ECP5 and ECP5-5G High-Speed I/O Interface (TN1265) Technical Note.
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34
FPGA-DS-02014-1.1
ECP5™ Automotive Family
Data Sheet
DQS
PIO A
sysIO Buffer
Pad A (T)
PIO B
sysIO Buffer
Pad B (C)
PIO C
sysIO Buffer
Pad C
PIO D
sysIO Buffer
Pad D
PIO A
sysIO Buffer
Pad A (T)
PIO B
sysIO Buffer
Pad B (C)
PIO C
sysIO Buffer
Pad C
PIO D
sysIO Buffer
Pad D
DQSBUF
Delay
PIO A
sysIO Buffer
Pad A (T)
PIO B
sysIO Buffer
Pad B (C)
PIO C
sysIO Buffer
Pad C
PIO D
sysIO Buffer
Pad D
PIO A
sysIO Buffer
Pad A (T)
PIO B
sysIO Buffer
Pad B (C)
PIO C
sysIO Buffer
Pad C
PIO D
sysIO Buffer
Pad D
Figure 2.23. DQS Grouping on the Left and Right Edges
2.19.2. DLL Calibrated DQS Delay and Control Block (DQSBUF)
To support DDR memory interfaces, DDR2/3, LPDDR2/3, the DQS strobe signal from the memory must be used to
capture the data DQ in the PIC registers during memory reads. This signal is output from the DDR memory device
aligned to data transitions and must be time shifted before it can be used to capture data in the PIC. This time shifting
is achieved by using DQSDEL programmable delay line in the DQS Delay Block. The DQSDEL is implemented as a slave
delay line and works in conjunction with a master DDRDLL.
This block also includes slave delay line to generate delayed clocks used in the write side to generate DQ and DQS with
correct phases within one DQS group. There is a third delay line inside this block used to provide write leveling feature
for DDR write if needed.
Each of the read or write side delays can be dynamically shifted using margin control signals that can be controlled by
the core logic.
FIFO Control Block included here generates the Read and Write Pointers for the FIFO block inside the Input Register
Block. These pointers are generated to control the DQS to ECLK domain crossing using the FIFO module.
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FPGA-DS-02014-1.1
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ECP5™ Automotive Family
Data Sheet
Preamble/Postamble Management
&
Burst Detect
DQS
READ[1:0]
BURSTDET
DATAVALID
READCLKSEL[1:0]
FIFO Control & Datavalid
Generation
ECLK
SCLK
RDPNTR[2:0]
WRPNTR[2:0]
DQSDEL
(90 Deg. Delay Code
from DDRDLL)
Read Side Slave Delay with
Dynamic Margin Control
RDLOADN, RDMOVE, RDDIRECTION
(Read Side Dynamic Margin Control)
DQSR90 (Read Side)
DQSW (Write Side)
WRLOADN, WRMOVE, WRDIRECTION
(Write Side Dynamic Margin Control)
Write Side Slave Delay with
Dynamic Margin Control
DQSW270 (Write Side)
RDCFLAG
WRCFLAG
PAUSE
DYNDELAY[7:0]
(Write Leveling delay)
Write
Leveling
Figure 2.24. DQS Control and Delay Block (DQSBUF)
Table 2.11. DQSBUF Port Description
Name
Type
Description
DQS
Input
DDR memory DQS strobe
READ[1:0]
Input
Read Input from DDR controller
READCLKSEL[1:0]
Input
Read pulse selection
SCLK
Input
Slow system clock
ECLK
Input
DQSDEL
Input
High speed edge clock with the same frequency as that of the DDR
memory)
90-degree delay code from DDRDLL
RDLOADN, RDMOVE, RDDIRECTION
Input
Dynamic margin control ports for Read delay
WRLOADN, WRMOVE, WRDIRECTION
Input
Dynamic margin control ports for Write delay
PAUSE
Input
DYNDELAY[7:0]
Input
Used by DDR controller to pause write side signals during DDRDLL
code update or Write leveling
Dynamic Write leveling delay control
DQSR90
Output
90-degree delay DQS used for Read
DQSW270
Output
90-degree delay clock used for DQ Write
DQSW
Output
Clock used for DQS Write
RDPNTR[2:0]
Output
Read pointer for IFIFO module
WRPNTR[2:0]
Output
Write pointer for IFIFO module
DATAVALID
Output
Signal indicating start of valid data
BURSTDET
Output
Burst detect indicator
RDFLAG
Output
Read dynamic margin control output to indicate max value
WRFLAG
Output
Write dynamic margin control output to indicate max value
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36
FPGA-DS-02014-1.1
ECP5™ Automotive Family
Data Sheet
2.20. sysI/O Buffer
Each I/O is associated with a flexible buffer referred to as a sysI/O buffer. These buffers are arranged around the
periphery of the device in groups referred to as banks. The sysI/O buffers allow users to implement the wide variety of
standards that are found in today’s systems including LVDS, HSUL, BLVDS, SSTL Class I and II, LVCMOS, LVTTL, LVPECL,
and MIPI.
2.20.1. sysI/O Buffer Banks
ECP5 Automotive devices have seven sysI/O buffer banks, two banks per side at Top, Left and Right, plus one at the
bottom left side. The bottom left side bank, Bank 8, is a shared I/O bank. The I/Os in that bank contains both dedicated
and shared I/O for sysConfig function. When a shared pin is not used for configuration, it is available as a user I/O.
In ECP5 Automotive devices, the Left and Right sides are tailored to support high performance interfaces, such as
DDR2, DDR3, LPDDR2, LPDDR3 and other high speed source synchronous standards. The banks on the Left and Right
sides of the devices feature LVDS input and output buffers, data-width gearing, and DQSBUF block to support DDR2/3
and LPDDR2/3 interfaces. The I/Os on the top and bottom banks do not have LVDS input and output buffer, and
gearing logic, but can use LVCMOS to emulate most of differential output signaling.
Each sysIO bank has its own I/O supply voltage VCCIO. In addition, the banks on the Left or Right side of the device, have
voltage reference input, VREF1 per bank, which allow it to be completely independent of each other. This voltage
reference input is a shared I/O pin. The VREF voltage is used to set the threshold for the referenced input buffers, such
as SSTL. Figure 2.25 shows the seven banks and their associated supplies.
In ECP5 Automotive devices, single-ended output buffers and ratioed input buffers, LVTTL, and LVCMOS, are powered
using VCCIO. LVTTL, LVCMOS33, LVCMOS25, and LVCMOS12 can also be set as fixed threshold inputs independent of
VCCIO.
TOP
VREF1(1)V
VCCIO1
GND
VREF1(0)V
VCCIO0
GND
Bank 0
Bank 1
VREF1(7)
GND
Bank 7
Bank 2
V CCIO7
V REF1(2)
GND
RIGHT
LEFT
V CCIO2
V REF1(6)
GND
Bank 6
Bank 3
V CCIO6
GND
V CCIO3
V REF1(3)
Bank 8
CONFIG BANK
Bank 4*
SERDES
GND
V CCIO4
GND
V CCIO8
BOTTOM
*Note: Only 85K device has this bank.
Figure 2.25. ECP5 Automotive Device Family Banks
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FPGA-DS-02014-1.1
37
ECP5™ Automotive Family
Data Sheet
ECP5 Automotive devices contain two types of sysI/O buffer pairs:
Top, Bank 0 and Bank 1, and Bottom, Bank 8 and Bank 4, single-ended sysIO Buffer Pairs
The sysI/O buffers in the Banks at top and bottom of the device consist of ratioed single-ended output drivers and
single-ended input buffers. The I/Os in these banks are not usually used as a pair, except when used as emulated
differential output pair. They are used as individual I/Os and are configured as different I/O modes, as long as they
are compatible with the VCCIO voltage in the bank. When used as emulated differential outputs, the pair can be
used together.
The top or bottom side IOs also support hot socketing. They support IO standards from 3.3 V to 1.2 V. They are
ideal for general purpose I/Os, or as ADDR/CMD bus for DDR2/DDR3 applications, or for being used as emulated
differential signaling.
Bank 8 is a bottom bank that shares with sysConfig I/Os. During configuration, these I/Os are used for programming
the device. Once the configuration is completed, these I/Os can be released and user can use these I/Os for
functional signals in his design.
The top and bottom side pads can be identified by the Lattice Semiconductor Diamond tool.
Left and right banks have 50% differential sysI/O buffer pairs and 100% single-ended outputs.
The sysI/O buffer pairs in the left and right banks of the device consist of two single-ended output drivers, two
single-ended input buffers, both ratioed and referenced, and half of the sysI/O buffer pairs, PIOA/B pairs. Also has a
high-speed differential output driver. One of the referenced input buffers can also be configured as a differential
input. In these banks the two pads in the pair are described as “true” and “comp”, where the true pad is associated
with the positive side of the differential I/O, and the comp (complementary) pad is associated with the negative
side of the differential I/O.
In addition, programmable on-chip input termination (parallel or differential, static or dynamic) is supported on
these sides, which is required for DDR3 interface. However, there is no support for hot-socketing for the I/O pins
located on the left and right side of the device as the PCI clamp is always enabled on these pins.
LVDS differential output drivers are available on 50% of the buffer pairs on the left and right banks.
2.20.2. Typical sysI/O I/O Behavior during Power-up
The internal Power-On-Reset (POR) signal is deactivated when VCC, VCCIO8 and VCCAUX have reached satisfactory levels.
After the POR signal is deactivated, the FPGA core logic becomes active. It is the user’s responsibility to ensure that all
other VCCIO banks are active with valid input logic levels to properly control the output logic states of all the I/O banks
that are critical to the application. For more information about controlling the output logic state with valid input logic
levels during power-up in ECP5 Automotive devices, see the list of technical documentation in the Supplemental
Information section.
The VCC and VCCAUX supply the power to the FPGA core fabric, whereas the VCCIO supplies power to the I/O buffers. In
order to simplify system design while providing consistent and predictable I/O behavior, it is recommended that the I/O
buffers be powered-up prior to the FPGA core fabric. VCCIO supplies should be powered-up before or together with the
VCC and VCCAUX supplies.
2.20.3. Supported sysI/O Standards
The ECP5 Automotive sysI/O buffer supports both single-ended and differential standards. Single-ended standards can
be further subdivided into LVCMOS, LVTTL and other standards. The buffers support the LVTTL, LVCMOS 1.2 V, 1.5 V,
1.8 V, 2.5 V, and 3.3 V standards. In the LVCMOS and LVTTL modes, the buffer has individual configuration options for
drive strength, slew rates, bus maintenance (weak pull-up, weak pull-down, or a bus-keeper latch) and open drain.
Other single-ended standards supported include SSTL and HSUL. Differential standards supported include LVDS,
differential SSTL and differential HSUL. For further information on utilizing the sysI/O buffer to support a variety of
standards, refer to ECP5 and ECP5-5G sysIO Usage Guide (TN1262).
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38
FPGA-DS-02014-1.1
ECP5™ Automotive Family
Data Sheet
2.20.4. On-Chip Programmable Termination
The ECP5 Automotive devices support a variety of programmable on-chip terminations options including:
Dynamically switchable Single-ended Termination with programmable resistor values of 50 Ω, 75 Ω, or 150 Ω.
Common mode termination of 100 Ω for differential inputs.
Zo = 50
V CCIO
Zo = 50 Ω, 75 Ω, or 150 Ω
to V CCIO /2
TERM
control
Zo
Zo
2Zo
Zo
+
-
VREF
OFF-chip
+
-
Zo
OFF-chip
ON-chip
Parallel Single-Ended Input
ON-chip
Differential Input
Figure 2.26. On-chip Termination
See Table 2.12 for termination options for input modes.
Table 2.12. On-Chip Termination Options for Input Modes
IO_TYPE
Terminate to VCCIO/2*
Differential Termination Resistor*
LVDS25
—
100
BLVDS25
—
100
MLVDS
—
100
LVPECL33
—
100
subLVDS
—
100
SLVS
HSUL12
HSUL12D
SSTL135_I / II
SSTL135D_I / II
SSTL15_I / II
SSTL15D_I / II
SSTL18_I / II
SSTL18D_I / II
—
100
50, 75, 150
—
—
100
50, 75, 150
—
—
100
50, 75, 150
—
—
100
50, 75, 150
—
—
100
*Notes:
TERMINATE to single-ended VCCIO/2 and DIFFRENTIAL TERMINATION RESISTOR when turned on can only have one setting per bank.
Only left and right banks have this feature.
Use of TERMINATE to VCCIO/2 and DIFFRENTIAL TERMINATION RESISTOR are mutually exclusive in an I/O bank. On-chip termination
tolerance ±20%.
Refer to ECP5 and ECP5-5G sysIO Usage Guide (TN1262) for on-chip termination usage and value ranges.
2.20.5. Hot Socketing
ECP5 Automotive devices have been carefully designed to ensure predictable behavior during power-up and
power-down. During power-up and power-down sequences, the I/Os remain in tri-state until the power supply voltage
is high enough to ensure reliable operation. In addition, leakage into I/O pins is controlled within specified limits. See
the Hot Socketing Specifications section.
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FPGA-DS-02014-1.1
39
ECP5™ Automotive Family
Data Sheet
2.21. SERDES and Physical Coding Sublayer
LAE5UM devices feature up to 4 channels of embedded SERDES/PCS arranged in dual-channel blocks at the bottom of
the devices. Each channel supports up to 3.2 Gb/s data rate. Figure 2.27 shows the position of the dual blocks for the
LAE5-45. Table 2.13 shows the location of available SERDES Duals for all devices. The LAE5UM SERDES/PCS supports a
range of popular serial protocols, including:
PCI Express Gen1 and Gen2 (2.5 Gb/s)
Ethernet (XAUI, GbE – 1000 Base CS/SX/LX and SGMII)
SMPTE SDI (3G-SDI, HD-SDI, SD-SDI)
CPRI (E.6.LV: 614.4 Mb/s, E.12.LV: 1228.8 Mb/s, E.24.LV: 2457.6 Mb/s, E.30.LV: 3072 Mb/s)
JESD204A/B – ADC and DAC converter interface: 312.5 Mb/s to 3.125 Gb/s
Each dual contains two dedicated SERDES for high speed, full duplex serial data transfer. Each dual also has a PCS
block that interfaces to the SERDES channels and contains protocol specific digital logic to support the standards
listed above. The PCS block also contains interface logic to the FPGA fabric. All PCS logic for dedicated protocol
support can also be bypassed to allow raw 8b/10b interfaces to the FPGA fabric.
Even though the SERDES/PCS blocks are arranged in duals, multiple baud rates can be supported within a dual with the
use of dedicated, per channel /1, /2 and /11 rate dividers. Additionally, two duals can be arranged together to form x4
channel link.
When a SERDES Dual in a 2-Dual device is not used, the power VCCA power supply for that Dual should be connected. It
is advised to connect the VCCA of unused channel to core if the user knows he will not use the Dual at all. Or, it should
be connected to a different regulated supply, if that Dual may be used in the future.
For an unused channel in a Dual, it is advised to connect the V CCHTX to VCCA. User can leave VCCHRX unconnected.
For information on how to use the SERDES/PCS blocks to support specific protocols, as well as on how to combine
multiple protocols and baud rates within a device, refer to ECP5 and ECP5-5G SERDES/PCS Usage Guide (TN1261).
Figure 2.27. SERDES/PCS Duals (LAE5UM-45)
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40
FPGA-DS-02014-1.1
ECP5™ Automotive Family
Data Sheet
Table 2.13. LAE5UM SERDES Standard Support
Standard
Data Rate (Mb/s)
Number of General/Link Width
Encoding Style
2500
x1, x2, x4
8b10b
1250
x1
8b10b
1250
x1
8b10b
2500
x1
8b10b
3125
x4
8b10b
x1
8b10b
x1
NRZI/Scrambled
x1
NRZI/Scrambled
x1
NRZI/Scrambled
x1
8b/10b
PCI Express 1.1 and 2.0
2.02
Gigabit Ethernet
SGMII
XAUI
CPRI-1
CPRI-2
CPRI-3
CPRI-4
SD-SDI (259M, 344M)*
614.4
1228.8
2457.6
3072.0
270
1483.5
1485
2967
2970
3125
HD-SDI (292M)
3G-SDI (424M)
JESD204A/B
*Note:
For slower rates, the SERDES are bypassed and CML signals are directly connected to the FPGA routing.
Table 2.14. Available SERDES Duals per LAE5UM Device
Package
LAE5UM -25
LAE5UM -45
1
2
381 caBGA
2.21.1. SERDES Block
A SERDES receiver channel may receive serial differential data stream, equalize the signal, perform Clock and Data
Recovery (CDR), and de-serialize the data stream before passing the 8b/10b data to the PCS logic. The SERDES
transmitter channel may receive the parallel 8b/10b data, serialize the data, and transmit the serial bit stream through
the differential drivers. Figure 2.28 shows a single-channel SERDES/PCS block. Each SERDES channel provides a
recovered clock and a SERDES transmit clock to the PCS block and to the FPGA core logic.
Each transmit channel, receiver channel, and SERDES PLL shares the same power supply V CCA. The output and input
buffers of each channel have their own independent power supplies, VCCHTX and VCCHRX.
SERDES
PCS
FPGA Core
Recovered Clock*
RX_REFCLK
HDINP
Recovered Clock
Equalizer
HDINN
Clock/Data
Recovery
Receiver
TX REFCLK
Deserializer
1:8/1:10
Polarity
Adjust
Bypass
CTC
FIFO
Word Alignment
8b/10b Decoder
Downsample
FIFO
Bypass
Bypass
Receive Clock
TX PLL
(Per Dual)
SERDES Tx Clock
De-emphasis
Tx Driver
HDOUTP
Serializer
8:1/10:1
HDOUTN
Receive Data
Polarity
Adjust
8b/10b
Encoder
Upsample
FIFO
Bypass
Bypass
Transmit Data
Transmit Clock
* 1/8 or 1/10 line rate
Figure 2.28. Simplified Channel Block Diagram for SERDES/PCS Block
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FPGA-DS-02014-1.1
41
ECP5™ Automotive Family
Data Sheet
2.21.2. PCS
As shown in Figure 2.28, the PCS receives the parallel digital data from the deserializer and selects the polarity,
performs word alignment, decodes 8b/10b, provides Clock Tolerance Compensation and transfers the clock domain
from the recovered clock to the FPGA clock via the Down Sample FIFO.
For the transmit channel, the PCS block receives the parallel data from the FPGA core, encodes it with 8b/10b, selects
the polarity and passes the 8b/10b data to the transmit SERDES channel.
The PCS also provides bypass modes that allow a direct 8b/10b interface from the SERDES to the FPGA logic. The PCS
interface to the FPGA can also be programmed to run at 1/2 speed for a 16-bit or 20-bit interface to the FPGA logic.
Some of the enhancements in LAE5UM SERDES/PCS include:
Higher clock/channel granularity: Dual channel architecture provides more clock resource per channel.
Enhanced TX de-emphasis: Programmable pre- and post-cursors improves TX output signaling.
Bit-slip function in PCS: Improves logic needed to perform Word Alignment function.
Refer to ECP5 and ECP5-5G SERDES/PCS Usage Guide (TN1261) for more information.
2.21.3. SERDES Client Interface Bus
The SERDES Client Interface (SCI) is an IP interface that allows the user to change the configuration through this
interface. This is useful when the user needs to fine-tune some settings, such as input and output buffer that need to
be optimized based on the channel characteristics. It is a simple register configuration interface that allows
SERDES/PCS configuration without power cycling the device.
The Diamond design tools support all modes of the PCS. Most modes are dedicated to applications associated with a
specific industry standard data protocol. Other more general purpose modes allow users to define their own operation.
With these tools, the user can define the mode for each dual in a design.
Popular standards such as 10 Gb Ethernet, x4 PCI Express, and 4x Serial RapidIO can be implemented using IP that is
available through Lattice Semiconductor), with two duals which is four SERDES channels with PCS and some additional
logic from the core.
The LAE5UM devices support a wide range of protocols. Within the same dual, the LAE5UM devices support mixed
protocols with semi-independent clocking as long as the required clock frequencies are integer x1, x2, or x11 multiples
of each other. Table 2.15 lists the allowable combination of primary and secondary protocol combinations.
2.22. Flexible Dual SERDES Architecture
The LAE5UM SERDES architecture is a dual channel-based architecture. For most SERDES settings and standards, the
whole dual, consisting of two SERDES channels, is treated as a unit. This helps in silicon area savings, better utilization,
higher granularity on clock/SERDES channel and overall lower cost.
However, for some specific standards, the LAE5UM dual-channel architecture provides flexibility. More than one
standard can be supported within the same dual.
Table 2.15 lists the standards that can be mixed and matched within the same dual. In general, the SERDES standards
whose nominal data rates are either the same or a defined subset of each other, can be supported within the same
dual. The two Protocol columns of the table define the different combinations of protocols that can be implemented
together within a Dual.
Table 2.15. LAE5UM Mixed Protocol Support
Protocol
Mixed With
Protocol
PCI Express 1.1
with
SGMII
PCI Express 1.1
with
Gigabit Ethernet
CPRI-3
with
CPRI-2 and CPRI-1
3G-SDI
with
HD-SDI and SD-SDI
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42
FPGA-DS-02014-1.1
ECP5™ Automotive Family
Data Sheet
There are some restrictions to be aware of when using spread spectrum clocking. When a dual shares a PCI Express x1
channel with a non-PCI Express channel, ensure that the reference clock for the dual is compatible with all protocols
within the dual. For example, a PCI Express spread spectrum reference clock is not compatible with most Gigabit
Ethernet applications because of tight CTC ppm requirements.
While the LAE5UM architecture will allow the mixing of a PCI Express channel and a Gigabit Ethernet, or SGMII channel
within the same dual, using a PCI Express spread spectrum clocking as the transmit reference clock will cause a
violation of the Gigabit Ethernet, and SGMII transmit jitter specifications.
For further information on SERDES, refer to ECP5 and ECP5-5G SERDES/PCS Usage Guide (TN1261).
2.23. IEEE 1149.1-Compliant Boundary Scan Testability
All ECP5 Automotive devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant Test Access
Port (TAP). This allows functional testing of the circuit board on which the device is mounted through a serial scan path
that can access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in and
loaded directly onto test nodes, or test data to be captured and shifted out for verification. The test access port
consists of dedicated I/Os: TDI, TDO, TCK and TMS. The test access port uses VCCIO8 for power supply.
For more information, refer to ECP5 and ECP5-5G sysCONFIG Usage Guide (TN1260).
2.24. Device Configuration
All ECP5 Automotive devices contain two ports that can be used for device configuration. The Test Access Port (TAP),
which supports bit-wide configuration and the sysCONFIG port, support dual-byte, byte, and serial configuration. The
TAP supports both the IEEE Standard 1149.1 Boundary Scan specification and the IEEE Standard 1532 In-System
Configuration specification. There are dedicated pins for TAP and sysConfig support, which are TDI, TDO, TCK, TMS,
CFG[2:0], PROGRAMN, DONE, INITN, and CCLK. The remaining sysCONFIG pins are used as dual function pins. Refer to
ECP5 and ECP5-5G sysCONFIG Usage Guide (TN1260) for more information about using the dual-use pins as general
purpose I/Os.
There are various ways to configure an ECP5 Automotive device:
JTAG
Standard Serial Peripheral Interface (SPI) to boot PROM Support x1, x2, x4 wide SPI memory interfaces.
System microprocessor to drive a x8 CPU port in Slave Parallel Configuration Mode (SPCM) mode.
System microprocessor to drive a serial slave SPI port (SSPI mode).
Slave Serial Configuration Mode (SCM)
On power-up, the FPGA SRAM is ready to be configured using the selected sysCONFIG port. Once a configuration port is
selected, it will remain active throughout that configuration cycle. The IEEE 1149.1 port can be activated any time after
power-up by sending the appropriate command through the TAP port.
ECP5 Automotive devices also support the Slave SPI Interface. In this mode, the FPGA behaves like a SPI Flash device
(slave mode) with the SPI port of the FPGA to perform read-write operations.
2.24.1. Enhanced Configuration Options
ECP5 Automotive devices have enhanced configuration features such as: decryption support, decompression support,
TransFR™ I/O, and dual-boot and multi-boot image support.
TransFR (Transparent Field Reconfiguration)
TransFR I/O (TFR) is a unique Lattice Semiconductor technology that allows users to update their logic in the field
without interrupting system operation using a single ispVM command. TransFR I/O allows I/O states to be frozen
during device configuration. This allows the device to be field updated with a minimum of system disruption and
downtime. Refer to Minimizing System Interruption During Configuration Using TransFR Technology (TN1087) Technical
Note for details.
© 2016-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02014-1.1
43
ECP5™ Automotive Family
Data Sheet
Dual-Boot and Multi-Boot Image Support
Dual-boot and multi-boot images are supported for applications requiring reliable remote updates of configuration
data for the system FPGA. After the system is running with a basic configuration, a new boot image can be downloaded
remotely and stored in a separate location in the configuration storage device. Any time after the update, the ECP5
Automotive devices can be re-booted from this new configuration file. If there is a problem, such as corrupt data during
download or incorrect version number with this new boot image, the ECP5 Automotive device can revert back to the
original backup golden configuration and try again. This all can be done without power cycling the system. For more
information, refer to ECP5 and ECP5-5G sysCONFIG Usage Guide (TN1260).
2.24.2. Single Event Upset (SEU) Support
ECP5 Automotive devices support SEU mitigation with three supporting functions:
SED – Soft Error Detect
SEC – Soft Error Correction
SEI – Soft Error Injection
ECP5 Automotive devices have dedicated logic to perform Cycle Redundancy Code (CRC) checks. During configuration,
the configuration data bitstream can be checked with the CRC logic block. In addition, the ECP5 Automotive device can
also be programmed to utilize a Soft Error Detect (SED) mode that checks for soft errors in configuration SRAM. The
SED operation can be run in the background during user mode. If a soft error occurs, during user mode, normal
operation, the device can be programmed to generate an error signal.
When an error is detected, and the user's error handling software determines the error did not create any risk to the
system operation, the SEC tool allows the device to be re-configured in the background to correct the affected bit. This
operation allows the user functions to continue to operate without stopping the system function.
Additional SEI tool is also available in the Diamond Software, by creating a frame of data to be programmed into the
device in the background with one bit changed, without stopping the user functions on the device. This emulates an
SEU situation, allowing the user to test and monitor its error handling software.
For further information on SED support, refer to LatticeECP3, ECP5 and ECP5-5G Soft Error Detection (SED)/Correction
(SEC) Usage Guide (TN1184).
2.24.3. On-Chip Oscillator
Every ECP5 Automotive device has an internal CMOS oscillator which is used to derive a Master Clock (MCLK) for
configuration. The oscillator and the MCLK run continuously and are available to user logic after configuration is
completed. The software default value of the MCLK is nominally 2.4 MHz. Table 2.16 lists all the available MCLK
frequencies. When a different Master Clock is selected during the design process, the following sequence takes place:
1.
Device powers up with a nominal Master Clock frequency of 2.4 MHz.
2.
During configuration, users select a different master clock frequency.
3.
The Master Clock frequency changes to the selected frequency once the clock configuration bits are received.
4.
If the user does not select a master clock frequency, then the configuration bitstream defaults to the MCLK
frequency of 2.4 MHz.
This internal oscillator is available to the user by routing it as an input clock to the clock tree. For further information on
the use of this oscillator for configuration or user mode, refer to ECP5 and ECP5-5G sysCONFIG Usage Guide (TN1260).
Table 2.16. Selectable Master Clock (MCLK) Frequencies during Configuration (Nominal)
MCLK Frequency (MHz)
2.4
4.8
9.7
19.4
38.8
62
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44
FPGA-DS-02014-1.1
ECP5™ Automotive Family
Data Sheet
2.25. Density Shifting
The ECP5 Automotive family is designed to ensure that different density devices in the same family and in the same
package have the same pinout. Furthermore, the architecture ensures a high success rate when performing design
migration from lower density devices to higher density devices. In many cases, it is also possible to shift a lower
utilization design targeted for a high-density device to a lower density device. However, the exact details of the final
resource utilization will impact the likelihood of success in each case. An example is that some user I/Os may become
No Connects in smaller devices in the same package. Refer to the ECP5 Automotive Pin Migration Tables. Go to the
Lattice Semiconductor website. Enter ECP5 in the search field. In the Document Type navigation pane, click Pin &
Package. The web page displays information on the Pin Migration.
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FPGA-DS-02014-1.1
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ECP5™ Automotive Family
Data Sheet
3. DC and Switching Characteristics
3.1. Absolute Maximum Ratings
Table 3.1. Absolute Maximum Ratings
Symbol
VCC
Parameter
Supply Voltage
Min
–0.5
Max
1.32
Unit
V
VCCA
VCCAUX, VCCAUXA
VCCIO
Supply Voltage
Supply Voltage
Supply Voltage
–0.5
–0.5
–0.5
1.32
2.75
3.63
V
V
V
—
VCCHRX, VCCHTX
—
Input or I/O Transient Voltage Applied
SERDES RX/TX Buffer Supply Voltages
Voltage Applied on SERDES Pins
–0.5
–0.5
–0.5
3.63
1.32
1.80
V
V
V
TA
TJ
Storage Temperature (Ambient)
Junction Temperature
–65
—
150
+125
°C
°C
Notes:
1. Stress above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. Functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is
not implied.
2. Compliance with the Lattice Semiconductor Thermal Management document is required.
3. All voltages referenced to GND.
3.2. Recommended Operating Conditions
Table 3.2. Recommended Operating Conditions
Symbol
Parameter
Device
Min
Max
Unit
VCC2
Core Supply Voltage
All
1.045
1.155
V
Auxiliary Supply Voltage
All
2.375
2.625
V
I/O Driver Supply Voltage
All
1.14
3.465
V
Input Reference Voltage
All
0.5
1.0
V
Junction Temperature, Industrial Operation
All
–40
125
°C
VCCAUX
2, 4
VCCIO2, 3
VREF
1
tJAUTO
SERDES External Power Supply5
VCCA
SERDES Analog Power Supply
ECP5UM
1.045
1.155
V
VCCAUXA
SERDES Auxiliary Supply Voltage
ECP5UM
2.374
2.625
V
VCCHRX6
SERDES Input Buffer Power Supply
ECP5UM
0.30
1.155
V
VCCHTX
SERDES Output Buffer Power Supply
ECP5UM
1.045
1.155
V
Notes:
1. For correct operation, all supplies except VREF must be held in their valid operation range. This is true independent of feature
usage.
2. All supplies with same voltage, except SERDES Power Supplies, should be connected together.
3. See recommended voltages by I/O standard in Table 3.4 .
4. VCCAUX ramp rate must not exceed 30 mV/µs during power-up when transitioning between 0 V and 3 V.
5. Refer to ECP5 and ECP5-5G SERDES/PCS Usage Guide (TN1261) for information on board considerations for SERDES power
supplies.
6. VCCHRX is used for Rx termination. It can be biased to Vcm if external AC coupling is used. This voltage needs to meet all the HDin
input voltage level requirements specified in the SERDES High-Speed Data Receiver section of this Data Sheet.
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46
FPGA-DS-02014-1.1
ECP5™ Automotive Family
Data Sheet
3.3. Power Supply Ramp Rates
Table 3.3. Power Supply Ramp Rates
Symbol
Parameter
Min
Typ
Max
Unit
tRAMP
Power Supply ramp rates for all supplies
0.01
—
10
V/ms
Note: Assumes monotonic ramp rates.
3.4. Power-On-Reset Voltage Levels
Table 3.4. Power-On-Reset Voltage Levels
Symbol
Parameter
VPORUP
All Devices
VPORDN
All Devices
Min
Typ
Max
Unit
Power-On-Reset ramp-up trip point
(Monitoring VCC, VCCAUX, and VCCIO8)
VCC
VCCAUX
VCCIO8
0.90
2.00
0.95
—
—
—
1.02
2.20
1.06
V
V
V
Power-On-Reset ramp-down trip
point (Monitoring VCC, and VCCAUX)
VCC
VCCAUX
0.77
1.80
—
—
0.87
2.00
V
V
Notes:
These POR trip points are only provided for guidance. Device operation is only characterized for power supply voltages specified
under recommended operating conditions.
Only VCCIO8 has a Power-On-Reset ramp up trip point. All other VCCIOs do not have Power-On-Reset ramp up detection.
VCCIO8 does not have a Power-On-Reset ramp down detection. VCCIO8 must remain within the Recommended Operating
Conditions to ensure proper operation.
3.5. Power up Sequence
Power-On-Reset (POR) puts the ECP5 Automotive device in a reset state. POR is released when VCC, VCCAUX, and VCCIO8
are ramped above the VPORUP voltage, as specified above.
VCCIO8 controls the voltage on the configuration I/O pins. If the ECP5 Automotive device is using Master SPI mode to
download configuration data from external SPI Flash, it is required to ramp V CCIO8 above VIH of the external SPI Flash,
before at least one of the other two supplies, VCC and/or VCCAUX, is ramped to VPORUP voltage level. If the system
cannot meet this power up sequence requirement, and requires the VCCIO8 to be ramped last, the system must keep
either PROGRAMN or INITN pin LOW during power up until VCCIO8 reaches VIH of the external SPI Flash. This ensures
the signals driven out on the configuration pins to the external SPI Flash meeting the VIH voltage requirement of the SPI
Flash.
For LAE5UM devices, it is required to power up VCCA before VCCAUXA is powered up.
3.6. Hot Socketing Specifications
Table 3.5. Hot Socketing Specifications
Symbol
Parameter
Condition
IDK_HS
Input or I/O Leakage Current
for Top and Bottom Banks Only
Min
Typ
Max
Unit
0 VIN VIH (Max)
—
—
±1
mA
IDK
Input or I/O Leakage Current
for Left and Right Banks Only
0 VIN < VCCIO
—
—
±1
mA
VCCIO VIN VCCIO + 0.5 V
—
18
—
mA
Notes:
1. VCC, VCCAUX and VCCIO should rise/fall monotonically.
2. IDK is additive to IPU, IPW, or IBH.
3. LVCMOS and LVTTL only.
4. Hot socket specification defines when the hot socketed device's junction temperature is at 85 oC or below. When the hot
socketed device's junction temperature is above 85 oC, the IDK current can exceed ±1 mA.
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FPGA-DS-02014-1.1
47
ECP5™ Automotive Family
Data Sheet
3.7. Hot Socketing Requirements
Table 3.6. Hot Socketing Requirements
Description
Min
Typ
Max
Unit
Input current per SERDES I/O pin when device is powered down and inputs driven.
Input current per HDIN pin when device power supply is off, inputs driven1, 2
—
—
—
—
8
15
mA
mA
Current per HDIN pin when device power ramps up, input driven3
—
—
50
mA
—
—
30
mA
Current per HDOUT pin when device power supply is off, outputs pulled
up4
Notes:
1. Device is powered down with all supplies grounded, both HDINP and HDINN inputs driven by a CML driver with maximum
allowed output VCCHTX, 8b/10b data, no external AC coupling.
2. Each P and N input must have less than the specified maximum input current during hot plug. For a device with 2 DCU, the total
input current would be 15 mA * 4 channels * 2 input pins per channel = 120 mA.
3. Device power supplies are ramping up to VCCA and VCCAUX. Both HDINP and HDINN inputs are driven by a CML driver with
maximum allowed output VCCHTX, 8b/10b data, internal AC coupling.
4. Device is powered down with all supplies grounded. Both HDOUTP and HDOUN outputs are pulled up to V CCHTX by the far end
receiver termination of 50 Ω single ended.
3.8. ESD Performance
Refer to the ECP5 Product Family Qualification Summary for complete qualification data, including ESD performance.
3.9. DC Electrical Characteristics
Over Recommended Operating Conditions
Table 3.7. DC Electrical Characteristics
Symbol
Parameter
Condition
IIL, IIH1, 4
Input or I/O Low Leakage
IIH
1, 3
IPU
IPD
Min
Typ
Max
Unit
0 VIN VCCIO
—
Input or I/O High Leakage
VCCIO < VIN VIH(MAX)
—
—
10
µA
—
100
µA
I/O Active Pull-up Current,
sustaining logic HIGH state
I/O Active Pull-up Current, pulling
down from logic HIGH state
I/O Active Pull-down Current,
sustaining logic LOW state
I/O Active Pull-down Current,
pulling up from logic LOW state
0.7 VCCIO VIN VCCIO
–30
—
—
µA
0 VIN 0.7 VCCIO
—
—
–150
µA
0 VIN VIL (MAX)
30
—
—
µA
0 VIN VCCIO
—
—
150
µA
C1
I/O Capacitance2
VCCIO = 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V,
VCC = 1.1 V, VIO = 0 to VIH (MAX)
—
5
8
pf
C2
Dedicated Input Capacitance2
VCCIO = 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V,
VCC = 1.1 V, VIO = 0 to VIH (MAX)
—
5
7
pf
VHYST
Hysteresis for Single-Ended
Inputs
VCCIO = 3.3 V
—
300
—
mV
VCCIO = 2.5 V
—
250
—
mV
Notes:
1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tri-stated. It is
not measured with the output driver active. Bus maintenance circuits are disabled.
2. TA 25 oC, f = 1.0 MHz.
3. Applicable to general purpose I/Os in top and bottom banks.
4. When used as VREF, maximum leakage= 25 µA.
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48
FPGA-DS-02014-1.1
ECP5™ Automotive Family
Data Sheet
3.10. Standby ECP5 Automotive Supply Current
Over recommended operating conditions.
Table 3.8. Standby ECP5 Automotive Supply Current
Symbol
Parameter
Device
Typical
Unit
ICC
Core Power Supply Current
LAE5U-12F/LAE5UM-25F
LAE5UM-45F
77
116
mA
mA
ICCAUX
Auxiliary Power Supply Current
LAE5U-12F/ LAE5UM-25F
LAE5UM-45F
16
17
mA
mA
ICCIO
Bank Power Supply Current (Per Bank)
LAE5U-12F/ LAE5UM-25F
LAE5UM-45F
0.5
0.5
mA
mA
ICCA
SERDES Power Supply Current (Per Dual)
LAE5UM-25F
11
mA
LAE5UM-45F
9.5
mA
Notes:
For further information on supply current, see the list of technical documentation in the Supplemental Information section.
Assumes all outputs are tri-stated, all inputs are configured as LVCMOS and held at the VCCIO or GND.
Frequency 0 Hz.
Pattern represents a “blank” configuration data file.
TJ = 85 °C, power supplies at nominal voltage. For TJ = 125 °C, use the Power Calculator tool in the Lattice Diamond design
software.
To determine the ECP5 Automotive peak start-up current, use the Power Calculator tool in the Lattice Diamond design
software.
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FPGA-DS-02014-1.1
49
ECP5™ Automotive Family
Data Sheet
3.11. SERDES Power Supply Requirements
Over recommended operating conditions.
Table 3.9. ECP5UM Automotive
Symbol
Description
Typ
Max
Unit
Standby (Power Down)
ICCA-SB
VCCA, Power Supply Current per Channel
4
—
mA
ICCHRX-SB1
VCCHRX, Input Buffer Current per Channel
—
—
mA
ICCHTX-SB
VCCHTX, Output Buffer Current per Channel
—
—
mA
Operating (Data Rate = 3.125 Gb/s)
ICCA-OP
VCCA, Power Supply Current per Channel
43
—
mA
ICCHRX-OP2
VCCHRX, Input Buffer Current per Channel
0.4
—
mA
ICCHTX-OP
VCCHTX, Output Buffer Current per Channel
10
—
mA
Operating (Data Rate = 2.5 Gb/s)
ICCA-OP
VCCA, Power Supply Current per Channel
40
—
mA
ICCHRX-OP2
VCCHRX, Input Buffer Current per Channel
0.4
—
mA
ICCHTX-OP
VCCHTX, Output Buffer Current per Channel
10
—
mA
Operating (Data Rate = 1.25 Gb/s)
ICCA-OP
VCCA, Power Supply Current per Channel
34
—
mA
ICCHRX-OP2
VCCHRX, Input Buffer Current per Channel
0.4
—
mA
ICCHTX-OP
VCCHTX, Output Buffer Current per Channel
10
—
mA
VCCA, Power Supply Current per Channel
28
—
mA
VCCHRX, Input Buffer Current per Channel
0.4
—
mA
8
—
mA
Operating (Data Rate = 270 Mb/s)
ICCA-OP
ICCHRX-OP
ICCHTX-OP
2
VCCHTX, Output Buffer Current per Channel
Notes:
1. Rx Equalization enabled, Tx De-emphasis (pre-cursor and post-cursor) disabled
2. Per Channel current is calculated with both channels on in a Dual, and divide current by two. If only one channel is on, current is
higher.
3. To calculate with Tx De-emphasis enabled, use the Diamond Power Calculator tool.
4. For ICCHRX-SB, during Standby, input termination on Rx are disabled.
5. For ICCHRX-OP, during operational, the max specified when external AC coupling is used. If externally DC coupled, the power is
based on current pulled down by external driver when the input is driven to LOW.
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50
FPGA-DS-02014-1.1
ECP5™ Automotive Family
Data Sheet
3.12. sysI/O Recommended Operating Conditions
Table 3.10. sysI/O Recommended Operating Conditions
VCCIO (V)
Standard
VREF (V)
Min
Typ
Max
Min
Typ
Max
3.135
3.3
3.465
—
—
—
3.135
3.3
3.465
—
—
—
2.375
2.5
2.625
—
—
—
LVCMOS18
1.71
1.8
1.89
—
—
—
LVCMOS15
1.425
1.5
1.575
—
—
—
LVCMOS121
1.14
1.2
1.26
—
—
—
LVTTL331
3.135
3.3
3.465
—
—
—
_II2
1.43
1.5
1.57
0.68
0.75
0.9
SSTL18_I, _II2
1.71
1.8
1.89
0.833
0.9
0.969
SSTL135_I, _II2
1.28
1.35
1.42
0.6
0.675
0.75
HSUL122
1.14
1.2
1.26
0.588
0.6
0.612
MIPI D-PHY LP Input3
1.425
1.5
1.575
—
—
—
LVDS251, 3 Output
2.375
2.5
2.625
—
—
—
LVCMOS331
LVCMOS33D3
Output
LVCMOS251
SSTL15_I,
subLVS3 (Input
—
—
—
—
—
—
SLVS3 (Input only)
—
—
—
—
—
—
LVDS25E3 Output
2.375
2.5
2.625
—
—
—
MLVDS3 Output
2.375
2.5
2.625
—
—
—
LVPECL331, 3 Output
3.135
3.3
3.465
—
—
—
BLVDS251, 3 Output
2.375
2.5
2.625
—
—
—
HSULD12D2, 3
1.14
1.2
1.26
—
—
—
SSTL135D_I, II2, 3
1.28
1.35
1.42
—
—
—
II2, 3
1.43
1.5
1.57
—
—
—
1.71
1.8
1.89
—
—
—
SSTL15D_I,
only)
SSTL18D_I1, 2, 3, II1, 2, 3
Notes:
1. For input voltage compatibility, refer to ECP5 and ECP5-5G sysIO Usage Guide (TN1262).
2. VREF is required when using Differential SSTL and HSUL to interface to DDR/LPDDR memories.
3. These differential inputs use LVDS input comparator, which uses VCCAUX power.
4. All differential inputs and LVDS25 output are supported in the Left and Right banks only. Refer to ECP5 and ECP5-5G sysIO
Usage Guide (TN1262) for details.
5. MIPI D-PHY LP input can be implemented by powering VCCIO to 1.5 V, and select MIPI LP primitive to meet MIPI Alliance spec
on VIH and VIL. It can also be implemented as LVCMOS12 with VCCIO at 1.2 V, which would meet VIH/VIL spec on LVCOM12.
© 2016-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
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FPGA-DS-02014-1.1
51
ECP5™ Automotive Family
Data Sheet
3.13. sysI/O Single-Ended DC Electrical Characteristics
Input/Output
Standard
VIL
VIH
Min (V)
Max (V)
Min (V)
Max (V)
VOL Max
(V)
VOH Min
(V)
IOL1 (mA)
LVCMOS33
–0.3
0.8
2.0
3.465
0.4
VCCIO – 0.4
16, 12, 8, 4
LVCMOS25
–0.3
0.7
1.7
3.465
0.4
VCCIO – 0.4
12, 8, 4
–16, –12,
–8, –4
–12, –8, –4
LVCMOS18
–0.3
0.35 VCCIO
0.65 VCCIO
3.465
0.4
VCCIO – 0.4
12, 8, 4
–12, –8, –4
LVCMOS15
–0.3
0.35 VCCIO
0.65 VCCIO
3.465
0.4
VCCIO – 0.4
8, 4
–8, –4
LVCMOS12
–0.3
0.35 VCCIO
0.65 VCCIO
3.465
0.4
VCCIO – 0.4
8, 4
–8, –4
LVTTL33
SSTL18_I
(DDR2 Memory)
SSTL18_II
–0.3
–0.3
–0.3
0.8
VREF –
0.125
VREF –
0.125
VREF – 0.1
IOH1 (mA)
2.0
3.465
0.4
VCCIO – 0.4
16, 12, 8, 4
–16, –12,
–8, –4
VREF + 0.125
3.465
0.4
VCCIO – 0.4
6.7
–6.7
VREF + 0.125
3.465
0.28
VCCIO – 0.28
13.4
–13.4
SSTL15 _I
VREF + 0.1
VCCIO – 0.31
–0.3
3.465
0.31
7.5
–7.5
(DDR3 Memory)
SSTL15_II
VREF – 0.1
VREF + 0.1
VCCIO – 0.31
–0.3
3.465
0.31
8.8
–8.8
(DDR3 Memory)
SSTL135_I
VREF – 0.09
VREF + 0.09
VCCIO – 0.27
–0.3
3.465
0.27
7
–7
(DDR3L Memory)
SSTL135_II
VREF – 0.09
VREF + 0.09
VCCIO – 0.27
–0.3
3.465
0.27
8
–8
(DDR3L Memory)
MIPI D-PHY (LP)
–0.3
0.55
0.88
3.465
—
—
—
—
HSUL12
VREF – 0.1
VREF + 0.1
VCCIO – 0.3
(LPDDR2/3
–0.3
3.465
0.3
4
–4
Memory)
Notes:
1. For electromigration, the average DC current drawn by the I/O pads within a bank of I/Os shall not exceed 10 mA per I/O (All
I/Os used in the same VCCIO).
2. Not all IO types are supported in all banks. Refer to ECP5 and ECP5-5G sysIO Usage Guide (TN1262) for details.
3. MIPI D-PHY LP input can be implemented by powering VCCIO to 1.5 V, and select MIPI LP primitive to meet MIPI Alliance spec
on VIH and VIL. It can also be implemented as LVCMOS12 with VCCIO at 1.2 V, which would meet VIH/VIL spec on LVCOM12.
© 2016-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
52
FPGA-DS-02014-1.1
ECP5™ Automotive Family
Data Sheet
3.14. sysI/O Differential Electrical Characteristics
3.14.1. LVDS
Over recommended operating conditions.
Table 3.11. LVDS
Parameter
Description
Test Conditions
VINP, VINM
Input Voltage
—
Min
Typ
Max
Unit
0
—
2.4
V
VCM
Input Common Mode Voltage
VTHD
Differential Input Threshold
Half the sum of the two Inputs
0.05
—
2.35
V
±100
—
—
mV
Input Current
Difference between the two
Inputs
Power On or Power Off
IIN
VOH
—
—
±10
µA
Output High Voltage for VOP or VOM
RT = 100 Ω
—
1.38
1.60
V
VOL
Output Low Voltage for VOP or VOM
RT = 100 Ω
0.9 V
1.03
—
V
VOD
Output Voltage Differential
(VOP - VOM), RT = 100 Ω
250
350
450
mV
VOD
Change in VOD Between High and Low
—
—
—
50
mV
VOS
Output Voltage Offset
(VOP + VOM)/2, RT = 100 Ω
1.125
1.20
1.375
V
VOS
Change in VOS Between H and L
—
—
—
50
mV
—
12
mA
VOD = 0 V Driver outputs shorted
—
to each other
Note: On the left and right sides of the device, this specification is valid only for VCCIO = 2.5 V or 3.3 V.
ISAB
Output Short Circuit Current
3.14.2. SSTLD
All differential SSTL outputs are implemented as a pair of complementary single-ended outputs. All allowable
single-ended output classes, class I and class II, are supported in this mode.
3.14.3. LVCMOS33D
All I/O banks support emulated differential I/O using the LVCMOS33D I/O type. This option, along with the external
resistor network, provides the system designer the flexibility to place differential outputs on an I/O bank with 3.3 V
VCCIO. The default drive current for LVCMOS33D output is 12 mA with the option to change the device strength to
4 mA, 8 mA, 12 mA or 16 mA. Follow the LVCMOS33 specifications for the DC characteristics of the LVCMOS33D.
© 2016-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
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FPGA-DS-02014-1.1
53
ECP5™ Automotive Family
Data Sheet
3.14.4. LVDS25E
The top and bottom sides of ECP5 Automotive devices support LVDS outputs via emulated complementary LVCMOS
outputs in conjunction with a parallel resistor across the driver outputs. The scheme shown in Figure 3.1 is one possible
solution for point-to-point signals.
VCCIO = 2.5 V (±5%)`
RS=158 Ω
(±1%)
8 mA
RP = 140 Ω
(±1%)
VCCIO = 2.5 V (±5%)
RT = 100 Ω
(±1%)
+
–
RS=158 Ω
(±1%)
8 mA
Transmission line, Zo = 100 Ω differential
ON-chip
OFF-chip
OFF-chip
ON-chip
Figure 3.1. LVDS25E Output Termination Example
Table 3.12. LVDS25E DC Conditions
Parameter
Description
VCCIO
Output Driver Supply (±5%)
Typical
Unit
2.50
V
ZOUT
RS
Driver Impedance
20
Driver Series Resistor (±1%)
158
RP
Driver Parallel Resistor (±1%)
140
RT
Receiver Termination (±1%)
100
VOH
Output High Voltage
1.43
V
VOL
Output Low Voltage
1.07
V
VOD
Output Differential Voltage
0.35
V
VCM
Output Common Mode Voltage
1.25
V
ZBACK
Back Impedance
100.5
IDC
DC Output Current
6.03
mA
© 2016-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
54
FPGA-DS-02014-1.1
ECP5™ Automotive Family
Data Sheet
3.14.5. BLVDS25
The ECP5 Automotive devices support the BLVDS standard. This standard is emulated using complementary LVCMOS
outputs in conjunction with a parallel external resistor across the driver outputs. BLVDS is intended for use when
multi-drop and bi-directional multi-point differential signaling is required. The scheme shown in Figure 3.2 is one
possible solution for bi-directional multi-point differential signals.
Heavily loaded backplane, effective Zo ~ 45 Ω to 90 Ω differential
2.5 V
R S = 90 Ω
2.5 V
R S = 90 Ω
16 mA
16 mA
45 Ω – 90 Ω
R TL
2.5 V
R TR
45 Ω – 90 Ω
2.5 V
16 mA
16 mA
. R. =.90 Ω
R S = 90 Ω
S
2.5 V
+
+
–
2.5 V
16 mA
16 mA
–
R S = 90 Ω
R S = 90 Ω
2.5 V
+
–
+
R S = 90 Ω
R S = 90 Ω
2.5 V
16 mA
–
16 mA
Figure 3.2. BLVDS25 Multi-point Output Example
Over recommended operating conditions.
Table 3.13. BLVDS25 DC Conditions
Parameter
Description
VCCIO
Typical
Unit
Zo = 45
Zo = 90
Output Driver Supply (±5%)
2.50
2.50
V
ZOUT
Driver Impedance
10.00
10.00
RS
Driver Series Resistor (±1%)
90.00
90.00
RTL
Driver Parallel Resistor (±1%)
45.00
90.00
RTR
Receiver Termination (±1%)
45.00
90.00
VOH
Output High Voltage
1.38
1.48
V
VOL
Output Low Voltage
1.12
1.02
V
VOD
Output Differential Voltage
0.25
0.46
V
VCM
Output Common Mode Voltage
1.25
1.25
V
IDC
DC Output Current
11.24
10.20
mA
Note: For input buffer, see LVDS Table 3.11.
© 2016-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02014-1.1
55
ECP5™ Automotive Family
Data Sheet
3.14.6. LVPECL33
The ECP5 Automotive devices support the differential LVPECL standard. This standard is emulated using
complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The LVPECL input
standard is supported by the LVDS differential input buffer. The scheme shown in Figure 3.3 is one possible solution for
point-to-point signals.
VCCIO = 3.3 V
(±5%)
RS = 93.1 Ω
(±1%)
16 mA
VCCIO = 3.3 V
(±5%)
RP = 196 Ω
(±1%)
RS = 93.1 Ω
(±1%)
16 mA
+
RT = 100 Ω
(±1%)
–
Transmission line,
Zo = 100 Ω differential
On-chip
Off-chip
Off-chip
On-chip
Figure 3.3. Differential LVPECL33
Over recommended operating conditions.
Table 3.14. LVPECL33 DC Conditions
Parameter
Description
VCCIO
Output Driver Supply (±5%)
Typical
Unit
3.30
V
ZOUT
RS
Driver Impedance
10
Driver Series Resistor (±1%)
93
RP
Driver Parallel Resistor (±1%)
196
RT
Receiver Termination (±1%)
100
VOH
Output High Voltage
2.05
V
VOL
Output Low Voltage
1.25
V
VOD
Output Differential Voltage
0.80
V
VCM
Output Common Mode Voltage
1.65
V
ZBACK
Back Impedance
100.5
IDC
DC Output Current
12.11
mA
Note: For input buffer, see LVDS Table 3.11.
© 2016-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
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56
FPGA-DS-02014-1.1
ECP5™ Automotive Family
Data Sheet
3.14.7. MLVDS25
The ECP5 Automotive devices support the differential MLVDS standard. This standard is emulated using
complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The MLVDS input
standard is supported by the LVDS differential input buffer. The scheme shown in Figure 3.4 is one possible solution for
MLVDS standard implementation. Resistor values in the figure are industry standard values for 1% resistors.
Heavily loaded backplace, effective Zo~50 Ω to 70 Ω differential
2.5 V
2.5 V
R S = 35 Ω
R S = 35 Ω
16 mA
16 mA
OE
R TL
50 Ω to 70 Ω ±1%
50 Ω to 70 Ω ±1%
OE
R TR
2.5 V
2.5 V
16 mA
16 mA
OE
R S = 35 Ω
R S = 35 Ω
R S = 35 Ω
R S = 35 Ω
R S = 35 Ω
OE
R S = 35 Ω
+
–-
OE
16 mA
2.5 V
OE
OE
2.5 V
–
2.5 V
+
OE
16 mA
+
2.5 V
–
+
–
1 6 mA
16 mA
Figure 3.4. MLVDS25 (Multipoint Low Voltage Differential Signaling)
Table 3.15. MLVDS25 DC Conditions
Typical
Parameter
Description
VCCIO
Output Driver Supply (±5%)
2.50
2.50
V
ZOUT
Driver Impedance
10.00
10.00
RS
Driver Series Resistor (±1%)
35.00
35.00
RTL
Driver Parallel Resistor (±1%)
50.00
70.00
RTR
Receiver Termination (±1%)
50.00
70.00
VOH
Output High Voltage
1.52
1.60
V
VOL
Output Low Voltage
0.98
0.90
V
VOD
Output Differential Voltage
0.54
0.70
V
VCM
Output Common Mode Voltage
1.25
1.25
V
IDC
DC Output Current
21.74
20.00
mA
Zo=50
Zo=70
Unit
Note: For input buffer, see LVDS Table 3.11.
© 2016-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
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FPGA-DS-02014-1.1
57
ECP5™ Automotive Family
Data Sheet
3.14.8. SLVS
Scalable Low-Voltage Signaling (SLVS) is based on a point-to-point signaling method defined in the JEDEC JESD8-13 for
SLVS-400 standard. This standard evolved from the traditional LVDS standard relies on the advantage of its use of
smaller voltage swings and a lower common-mode voltage. The 200 mV, or 400 mV p-p, SLVS swing contributes to a
reduction in power.
The ECP5 Automotive devices can receive differential input up to 800 Mb/s with its LVDS input buffer. This LVDS input
buffer is used to meet the SLVS input standard specified by the JEDEC standard. The SLVS output parameters are
compared to ECP5 Automotive LVDS input parameters, as listed in Table 3.16.
Table 3.16. Input to SLVS
Parameter
ECP5 Automotive LVDS Input
SLVS Output
Unit
Vcm (min)
50
150
mV
Vcm (max)
2350
250
mV
Differential Voltage (min)
100
140
mV
Differential Voltage (max)
—
270
mV
ECP5 Automotive does not support SLVS output. However, SLVS output can be created using ECP5 Automotive LVDS
outputs by level shift to meet the low Vcm/Vod levels required by SLVS. Figure 3.5 shows how the LVDS output can be
shifted externally to meet SLVS levels.
2.5 V Typical
R3=15
R1=220
R2=47
LVDS
+
-
SLVDS
100 Ω Diff
+
Z0=50
–
R2=47
R1=220
ECP5/ECP5-5G
2.5 V Typical
On Chip
R3=15
On Chip
SLVDS Peer
LVDS
+
–-
Z0=50
+
–-
Figure 3.5. SLVS Interface
© 2016-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
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58
FPGA-DS-02014-1.1
ECP5™ Automotive Family
Data Sheet
3.15. Typical Building Block Function Performance
Table 3.17. Pin-to-Pin Performance
Function
Timing
Unit
16-Bit Decoder
5.06
ns
32-Bit Decoder
6.08
ns
64-Bit Decoder
5.06
ns
4:1 Mux
4.45
ns
8:1 Mux
4.63
ns
16:1 Mux
4.81
ns
32:1 Mux
4.85
ns
Basic Functions
Notes:
1. I/Os are configured with LVCMOS25 with VCCIO=2.5, 12 mA drive.
2. These functions were generated using Lattice Diamond design software tool. Exact performance may vary with the device and
the design software tool version. The design software tool uses internal parameters that have been characterized but are not
tested on every device.
3. Non-automotive device timing numbers are shown. Automotive device numbers are slower and can be extracted from Lattice
Diamond design software tool.
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All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02014-1.1
59
ECP5™ Automotive Family
Data Sheet
Table 3.18. Register-to-Register Performance
Function
Timing
Unit
16-Bit Decoder
441
MHz
32-Bit Decoder
441
MHz
64-Bit Decoder
332
MHz
4:1 Mux
441
MHz
8:1 Mux
441
MHz
16:1 Mux
441
MHz
32:1 Mux
441
MHz
8-Bit Adder
441
MHz
16-Bit Adder
441
MHz
64-Bit Adder
441
MHz
16-Bit Counter
384
MHz
32-Bit Counter
317
MHz
64-Bit Counter
263
MHz
64-Bit Accumulator
288
MHz
1024x18 True-Dual Port RAM (Write Through or Normal), with EBR Output Registers
272
MHz
1024x18 True-Dual Port RAM (Read-Before-Write), with EBR Output Registers
214
MHz
16 x 2 Pseudo-Dual Port or 16 x 4 Single Port RAM (One PFU)
441
MHz
16 x 4 Pseudo-Dual Port (Two PFUs)
441
MHz
9 x 9 Multiplier (All Registers)
225
MHz
18 x 18 Multiplier (All Registers)
225
MHz
36 x 36 Multiplier (All Registers)
225
MHz
18 x 18 Multiply-Add/Sub (All Registers)
225
MHz
18 x 18 Multiply/Accumulate (Input and Output Registers)
225
MHz
Basic Functions
Embedded Memory Functions
Distributed Memory Functions
DSP Functions
Notes:
1. These functions were generated using Lattice Diamond design software tool. Exact performance may vary with the device and
the design software tool version. The design software tool uses internal parameters that have been characterized but are not
tested on every device.
2. Non-automotive device timing numbers are shown. Automotive device numbers are slower and can be extracted from Lattice
Diamond design software tool.
3.16. Derating Timing Tables
Logic timing provided in the following sections of this data sheet and the Diamond design tools are worst case numbers
in the operating range. Actual delays at nominal temperature and voltage for best case process, can be much better
than the values given in the tables. The Diamond design tool can provide logic timing numbers at a particular
temperature and voltage.
© 2016-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
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60
FPGA-DS-02014-1.1
ECP5™ Automotive Family
Data Sheet
3.17. ECP5 Automotive Maximum I/O Buffer Speed
Over recommended operating conditions.
Table 3.19. ECP5 Automotive Maximum I/O Buffer Speed
Buffer
Description
Max
Unit
LVDS25
LVDS, VCCIO = 2.5 V
400
MHz
MLVDS25
MLVDS, Emulated, VCCIO = 2.5 V
400
MHz
BLVDS25
BLVDS, Emulated, VCCIO = 2.5 V
400
MHz
MIPI D-PHY (HS Mode)
MIPI Video
400
MHz
SLVS
SLVS similar to MIPI
400
MHz
Mini LVDS
Mini LVDS
400
MHz
LVPECL33
LVPECL, Emulated, VCCIO = 3.3 V
400
MHz
SSTL18 (all supported classes)
SSTL_18 class I, II, VCCIO = 1.8 V
400
MHz
SSTL15 (all supported classes)
SSTL_15 class I, II, VCCIO = 1.5 V
400
MHz
SSTL135 (all supported classes)
SSTL_135 class I, II, VCCIO = 1.35 V
400
MHz
HSUL12 (all supported classes)
HSUL_12 class I, II, VCCIO = 1.2 V
400
MHz
LVTTL33
LVTTL, VCCIO = 3.3 V
200
MHz
LVCMOS33
LVCMOS, VCCIO = 3.3 V
200
MHz
LVCMOS25
LVCMOS, VCCIO = 2.5 V
200
MHz
LVCMOS18
LVCMOS, VCCIO = 1.8 V
200
MHz
LVCMOS15
LVCMOS 1.5, VCCIO = 1.5 V
200
MHz
LVCMOS12
LVCMOS 1.2, VCCIO = 1.2 V
200
MHz
LVDS25E
LVDS, Emulated, VCCIO = 2.5 V
300
MHz
LVDS25
LVDS, VCCIO = 2.5 V
400
MHz
MLVDS25
MLVDS, Emulated, VCCIO = 2.5 V
300
MHz
BLVDS25
BLVDS, Emulated, VCCIO = 2.5 V
300
MHz
LVPECL33
LVPECL, Emulated, VCCIO = 3.3 V
300
MHz
SSTL18 (all supported classes)
SSTL_18 class I, II, VCCIO = 1.8 V
400
MHz
SSTL15 (all supported classes)
SSTL_15 class I, II, VCCIO = 1.5 V
400
MHz
SSTL135 (all supported classes)
SSTL_135 class I, II, VCCIO = 1.35 V
400
MHz
HSUL12 (all supported classes)
HSUL12 class I, II, VCCIO = 1.2 V
400
MHz
LVTTL33
LVTTL, VCCIO = 3.3 V
150
MHz
LVCMOS33 (For all drives)
LVCMOS, 3.3 V
150
MHz
LVCMOS25 (For all drives)
LVCMOS, 2.5 V
150
MHz
LVCMOS18 (For all drives)
LVCMOS, 1.8 V
150
MHz
LVCMOS15 (For all drives)
LVCMOS, 1.5 V
150
MHz
LVCMOS12 (For all drives)
LVCMOS, 1.2 V
150
MHz
Maximum Input Frequency
Maximum Output Frequency
Notes:
1. These maximum speeds are characterized but not tested on every device.
2. Maximum I/O speed for differential output standards emulated with resistors depends on the layout.
3. LVCMOS timing is measured with the load specified in Switching Test Conditions, Table 3.41.
4. All speeds are measured at fast slew.
5. Actual system operation may vary depending on user logic implementation.
6. Maximum data rate equals 2 times the clock rate when utilizing DDR.
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FPGA-DS-02014-1.1
61
ECP5™ Automotive Family
Data Sheet
3.18. ECP5 Automotive External Switching Characteristics
Over recommended commercial operating conditions.
Table 3.20. ECP5 Automotive External Switching Characteristics
Device
–7
Min –7 Min
Parameter
Description
Clocks
Primary Clock
fMAX_PRI
Frequency for Primary Clock Tree
—
—
tW_PRI
Clock Pulse Width for Primary Clock
—
tSKEW_PRI
Primary Clock Skew Within a Device
Edge Clock
fMAX_EDGE
tW_EDGE
tSKEW_EDGE
Frequency for Edge Clock Tree
Clock Pulse Width for Edge Clock
Edge Clock Skew Within a Bank
–6
Unit
Min
Max
303
—
257
MHz
0.9
—
1.0
—
ns
—
—
462
—
505
ps
—
—
—
—
1.344
—
350
—
180
—
1.50
—
312
—
200
MHz
ns
ps
Generic SDR Input
General I/O Pin Parameters Using Dedicated Primary Clock Input without PLL
tCO
Clock to Output - PIO Output Register
All Devices
—
6.1
—
6.8
ns
tSU
Clock to Data Setup - PIO Input Register
All Devices
0
—
0
—
ns
tH
Clock to Data Hold - PIO Input Register
All Devices
3
—
3.3
—
ns
All Devices
1.33
—
1.46
—
ns
All Devices
0
—
0
—
ns
All Devices
—
350
—
312
MHz
tSU_DEL
tH_DEL
fMAX_IO
Clock to Data Setup - PIO Input Register
with Data Input Delay
Clock to Data Hold - PIO Input Register
with Data Input Delay
Clock Frequency of I/O and PFU Register
General I/O Pin Parameters Using Dedicated Primary Clock Input with PLL
tCOPLL
Clock to Output - PIO Output Register
All Devices
—
3.8
—
4.1
ns
tSUPLL
Clock to Data Setup - PIO Input Register
All Devices
0.78
—
0.85
—
ns
tHPLL
Clock to Data Hold - PIO Input Register
All Devices
0.89
—
0.98
—
ns
All Devices
1.78
—
1.95
—
ns
All Devices
0
—
0
—
ns
tSU_DELPLL
tH_DELPLL
Clock to Data Setup - PIO Input Register
with Data Input Delay
Clock to Data Hold - PIO Input Register
with Data Input Delay
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62
FPGA-DS-02014-1.1
ECP5™ Automotive Family
Data Sheet
Table 3.20. ECP5 Automotive External Switching Characteristics (Continued)
Parameter
Description
Device
–7
Min –7 Max
–6
Min
Max
Unit
Generic DDR Input
Generic DDRX1 Inputs with Clock and Data Centered at Pin (GDDRX1_RX.SCLK.Centered) Using PCLK Clock Input - Figure 3.6
tSU_GDDRX1_centered
Data Setup Before CLK Input
All Devices
0.52
—
0.52
—
ns
tHD_GDDRX1_centered Data Hold After CLK Input
All Devices
0.52
—
0.52
—
ns
fDATA_GDDRX1_center GDDRX1 Data Rate
All Devices
—
500
—
500
Mb/s
ed
fMAX_GDDRX1_centere GDDRX1 CLK Frequency (SCLK)
All Devices
—
250
—
250
MHz
d
Generic DDRX1 Inputs with Clock and Data Aligned at Pin (GDDRX1_RX.SCLK.Aligned) Using PCLK Clock Input - Figure 3.7
ns + 1/2
tSU_GDDRX1_aligned
Data Setup from CLK Input
All Devices
—
–0.55
—
–0.55
UI
ns + 1/2
tHD_GDDRX1_aligned
Data Hold from CLK Input
All Devices
0.55
—
0.55
—
UI
fDATA_GDDRX1_aligne
GDDRX1 Data Rate
All Devices
—
500
—
500
Mb/s
d
fMAX_GDDRX1_aligned GDDRX1 CLK Frequency (SCLK)
All Devices
—
250
—
250
MHz
Generic DDRX2 Inputs with Clock and Data Centered at Pin (GDDRX2_RX.ECLK.Centered) Using PCLK Clock Input, Left and Right
Sides Only - Figure 3.6
tSU_GDDRX2_centered
Data Setup before CLK Input
All Devices
0.403
—
0.471
—
ns
tHD_GDDRX2_centered Data Hold after CLK Input
All Devices
0.403
—
0.471
—
ns
fDATA_GDDRX2_center GDDRX2 Data Rate
All Devices
—
700
—
624
Mb/s
ed
fMAX_GDDRX2_centere GDDRX2 CLK Frequency (ECLK)
All Devices
—
350
—
312
MHz
d
Generic DDRX2 Inputs with Clock and Data Aligned at Pin (GDDRX2_RX.ECLK.Aligned) Using PCLK Clock Input, Left and Right
Sides Only - Figure 3.7
tSU_GDDRX2_align
Data Setup from CLK Input
All Devices
—
–0.42
—
–0.495 ns + 1/2 UI
ed
tHD_GDDRX2_alig
Data Hold from CLK Input
All Devices
0.42
—
0.495
—
ns + 1/2 UI
GDDRX2 Data Rate
All Devices
—
700
—
624
Mb/s
ned
fDATA_GDDRX2_al
igned
fMAX_GDDRX2_ali
GDDRX2 CLK Frequency (ECLK)
All Devices
—
350
—
312
MHz
gned
Video DDRX71 Inputs With Clock and Data Aligned at Pin (GDDRX71_RX.ECLK) Using PLL Clock Input, Left and Right sides Only Figure 3.11
Data Setup from CLK Input
ns+(1/2+i)
tSU_LVDS71_i
All Devices
—
–0.39
—
–0.41
(bit i)
UI
Data Hold from CLK Input
ns+(1/2+i)
tHD_LVDS71_i
All Devices
0.39
—
0.41
—
(bit i)
UI
fDATA_LVDS71
DDR71 Data Rate
All Devices
—
620
—
525
Mb/s
fMAX_LVDS71
DDR71 CLK Frequency (ECLK)
All Devices
—
310
—
262.5
MHz
© 2016-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02014-1.1
63
ECP5™ Automotive Family
Data Sheet
Table 3.20. ECP5 Automotive External Switching Characteristics (Continued)
Parameter
Description
Device
–7
Min
–6
Max
Min
Max
Unit
Generic DDR Output
Generic DDRX1 Outputs With Clock and Data Centered at Pin (GDDRX1_TX.SCLK.Centered) Using PCLK Clock Input - Figure 3.8
tDVB_GDDRX1_cent
Data Output Valid before CLK Output
All Devices
–0.67
—
–0.67
—
ns + 1/2 UI
ered
tDVA_GDDRX1_cent
Data Output Valid after CLK Output
All Devices
–0.67
—
–0.67
—
ns + 1/2 UI
ered
fDATA_GDDRX1_cen GDDRX1 Data Rate
All Devices
—
500
—
500
Mb/s
tered
fMAX_GDDRX1_cent GDDRX1 CLK Frequency (SCLK)
All Devices
—
250
—
250
MHz
ered
Generic DDRX1 Outputs With Clock and Data Aligned at Pin (GDDRX1_TX.SCLK.Aligned) Using PCLK Clock Input - Figure 3.9
tDIB_GDDRX1_align
Data Output Invalid before CLK Output
All Devices
–0.3
—
–0.3
—
ns
ed
tDIA_GDDRX1_align
Data Output Invalid after CLK Output
All Devices
—
0.3
—
0.3
ns
ed
fDATA_GDDRX1_alig GDDRX1 Data Rate
All Devices
—
500
—
500
Mb/s
ned
fMAX_GDDRX1_alig GDDRX1 CLK Frequency (SCLK)
All Devices
—
250
—
250
MHz
ned
Generic DDRX2 Outputs With Clock and Data Centered at Pin (GDDRX2_TX.ECLK.Centered) Using PCLK Clock Input, Left and
Right sides Only - Figure 3.8
tDVB_GDDRX2_cent
Data Output Valid Before CLK Output
All Devices
–0.56
—
–0.676
—
ns + 1/2 UI
ered
tDVA_GDDRX2_cent
Data Output Valid After CLK Output
All Devices
—
0.56
—
0.676
ns + 1/2 UI
ered
fDATA_GDDRX2_cen GDDRX2 Data Rate
All Devices
—
700
—
624
Mb/s
tered
fMAX_GDDRX2_cent GDDRX2 CLK Frequency (ECLK)
All Devices
—
350
—
312
MHz
ered
Generic DDRX2 Outputs With Clock and Data Aligned at Pin (GDDRX2_TX.ECLK.Aligned) Using PCLK Clock Input, Left and Right
sides Only - Figure 3.9
tDIB_GDDRX2_align
Data Output Invalid before CLK Output
All Devices
–0.18
—
–0.2
—
ns
ed
tDIA_GDDRX2_align
Data Output Invalid after CLK Output
All Devices
—
0.18
—
0.2
ns
ed
fDATA_GDDRX2_alig GDDRX2 Data Rate
All Devices
—
700
—
624
Mb/s
ned
fMAX_GDDRX2_alig GDDRX2 CLK Frequency (ECLK)
All Devices
—
350
—
312
MHz
ned
Video DDRX71 Outputs With Clock and Data Aligned at Pin (GDDRX71_TX.ECLK) Using PLL Clock Input, Left and Right sides Only
- Figure 3.12
tDIB_LVDS71_i
Data Output Invalid before CLK Output
All Devices
–0.18
—
–0.2
—
ns + (i) UI
tDIA_LVDS71_i
Data Output Invalid after CLK Output
All Devices
—
0.18
—
0.2
ns + (i) UI
fDATA_LVDS71
DDR71 Data Rate
All Devices
—
fMAX_LVDS71
DDR71 CLK Frequency (ECLK)
All Devices
—
Memory Interface
DDR2/DDR3/DDR3L/LPDDR2/LPDDR3 READ (DQ Input Data are Aligned to DQS)
tDVBDQ_DDR2
tDVBDQ_DDR3
tDVBDQ_DDR3L
Data Output Valid before DQS Input
All Devices
—
tDVBDQ_LPDDR2
tDVBDQ_LPDDR3
620
310
—
—
525
262.5
Mb/s
MHz
–0.317
—
–0.374
ns + 1/2 UI
—
0.374
—
ns + 1/2 UI
tDVADQ_DDR2
tDVADQ_DDR3
tDVADQ_DDR3L
tDVADQ_LPDDR2
tDVADQ_LPDDR3
Data Output Valid after DQS Input
All Devices
0.317
© 2016-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
64
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Data Sheet
Table 3.20. ECP5 Automotive External Switching Characteristics (Continued)
Parameter
Description
fDATA_DDR2
fDATA_DDR3
fDATA_DDR3L
fDATA_LPDDR2
fDATA_LPDDR3
DDR Memory Data Rate
fMAX_DDR2
fMAX_DDR3
fMAX_DDR3L
fMAX_LPDDR2
fMAX_LPDDR3
DDR Memory CLK Frequency (ECLK)
Device
–7
–6
Unit
Min
Max
Min
Max
All Devices
—
700
—
624
Mb/s
All Devices
—
350
—
312
MHz
–0.25
—
-0.25
UI
DDR2/DDR3/DDR3L/LPDDR2/LPDDR3 WRITE (DQ Output Data are Centered to DQS)
tDQVBS_DDR2
tDQVBS_DDR3
tDQVBS_DDR3L
Data Output Valid before DQS Output
All Devices
—
tDQVBS_LPDDR2
tDQVBS_LPDDR3
tDQVAS_DDR2
tDQVAS_DDR3
tDQVAS_DDR3L
tDQVAS_LPDDR2
tDQVAS_LPDDR3
Data Output Valid after DQS Output
All Devices
0.25
—
0.25
—
UI
fDATA_DDR2
fDATA_DDR3
fDATA_DDR3L
fDATA_LPDDR2
fDATA_LPDDR3
DDR Memory Data Rate
All Devices
—
700
—
624
Mb/s
fMAX_DDR2
fMAX_DDR3
fMAX_DDR3L
fMAX_LPDDR2
fMAX_LPDDR3
DDR Memory CLK Frequency (ECLK)
All Devices
—
350
—
312
MHz
Notes:
1. Commercial timing numbers are shown. Industrial numbers are typically slower and can be extracted from the Diamond
software.
2. General I/O timing numbers are based on LVCMOS 2.5, 12 mA, Fast Slew Rate, 0pf load.
Generic DDR timing are numbers based on LVDS I/O.
DDR2 timing numbers are based on SSTL18.
DDR3 timing numbers are based on SSTL15.
LPDDR2 and LPDDR3 timing numbers are based on HSUL12.
3. Uses LVDS I/O standard for measurements.
4. Maximum clock frequencies are tested under best case conditions. System performance may vary upon the user environment.
5. All numbers are generated with the Lattice Diamond software.
© 2016-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02014-1.1
65
ECP5™ Automotive Family
Data Sheet
Rx CLK (in)
Rx DATA (in)
tSU/tDVBDQ
tSU/tDVBDQ
tHD/tDVADQ
tHD/tDVADQ
Figure 3.6. Receiver RX.CLK. Centered Waveforms
1/2 UI
Rx CLK (in)
or DQS Input
1/2 UI
1 UI
Rx DATA (in)
or DQ Input
tSU
tSU
tHD
tHD
Figure 3.7. Receiver RX.CLK. Aligned and DDR Memory Input Waveforms
1/2 UI
1/2 UI
1/2 UI
1/2 UI
Tx CLK (out)
or DQS Output
Tx DATA (out)
or DQ Output
tDVB/tDQVBS
tDVB/tDQVBS
tDVA/tDQVA
tDVA/tDQVAS
Figure 3.8. Transmit TX.CLK. Centered and DDR Memory Output Waveforms
© 2016-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
66
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Data Sheet
1 UI
Tx CLK (out)
Tx DATA (out)
tDIB
tDIB
tDIA
tDIA
Figure 3.9. Transmit TX.CLK. Aligned Waveforms
Receiver – Shown for one LVD S channel
# of B its
Data In
756 Mb/s
Cl ock In
108 MHz
Bi t #
10 – 1
11 – 2
12 – 3
13 – 4
14 – 5
15 – 6
16 – 7
0x
0x
For each channel:
0x
7-bit Output Words 0x
to FPGA Fabric
0x
0x
0x
Bi t #
20 – 8
21 – 9
22 – 10
23 – 11
24 – 12
25 – 13
26 – 14
Bi t #
30 – 15
31 – 16
32 – 17
33 – 18
34 – 19
35 – 20
36 – 21
Bi t #
40 – 22
41 – 23
42 – 24
43 – 25
44 – 26
45 – 27
46 – 28
Transmitter – Shown for one LVD S channel
# of B its
Data Out
756 Mb/s
Cl ock Out
108 MHz
For each channel:
7-bit Output Words
to FPGA Fabric
Bi t #
00 – 1
00 – 2
00 – 3
00 – 4
00 – 5
00 – 6
00 – 7
Bi t #
10 – 8
11 – 9
12 – 10
13 – 11
14 – 12
15 – 13
16 – 14
Bi t #
20 – 15
21 – 16
22 – 17
23 – 18
24 – 19
25 – 20
26 – 21
Bi t #
30 – 22
31 – 23
32 – 24
33 – 25
34 – 26
35 – 27
36 – 28
Figure 3.10. DDRX71 Video Timing Waveforms
© 2016-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02014-1.1
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ECP5™ Automotive Family
Data Sheet
Bit 0
1/2 UI
Bit i
1/2 UI
Bit 1
1 UI
CLK (in)
DATA (in)
tSU_0
tHD_0
tSU_i
tHD_i
Figure 3.11. Receiver DDRX71_RX Waveforms
Bit 0
Bit i
Bit 1
1 UI
CLK (out)
DATA (out)
tDIB_0
tDIA_0
tDIB_i
tDIA_i
Figure 3.12. Transmitter DDRX71_TX Waveforms
© 2016-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
68
FPGA-DS-02014-1.1
ECP5™ Automotive Family
Data Sheet
3.19. sysCLOCK PLL Timing
Over recommended operating conditions.
Table 3.21. sysCLOCK PLL Timing
Parameter
Descriptions
Conditions
Min
Max
Units
fIN
Input Clock Frequency (CLKI, CLKFB)
—
8
400
MHz
fOUT
Output Clock Frequency (CLKOP, CLKOS)
—
3.125
400
MHz
fVCO
PLL VCO Frequency
—
400
800
MHz
Phase Detector Input Frequency
—
10
400
MHz
tDT
Output Clock Duty Cycle
—
45
55
%
tPH4
Output Phase Accuracy
—
–5
5
%
fOUT ≥ 100 MHz
—
100
ps p-p
fOUT < 100 MHz
—
0.025
UIPP
fOUT ≥ 100 MHz
—
200
ps p-p
fOUT < 100 MHz
—
0.050
UIPP
fPFD > 100 MHz
—
200
ps p-p
fPFD < 100 MHz
—
0.011
UIPP
Divider ratio =
integer
At 90%
or 10%
—
400
ps p-p
0.9
—
ns
—
—
15
ms
—
—
50
ns
fPFD ≥ 20 MHz
—
1,000
ps p-p
fPFD
3
AC Characteristics
Output Clock Period Jitter
tOPJIT1
Output Clock Cycle-to-Cycle Jitter
Output Clock Phase Jitter
tSPO
Static Phase Offset
tW
Output Clock Pulse Width
tLOCK2
PLL Lock-in Time
tUNLOCK
PLL Unlock Time
tIPJIT
Input Clock Period Jitter
fPFD < 20 MHz
—
0.02
UIPP
tHI
Input Clock High Time
90% to 90%
0.5
—
ns
tLO
Input Clock Low Time
10% to 10%
0.5
—
ns
tRST
RST/ Pulse Width
—
1
—
ms
tRSTREC
RST Recovery Time
—
1
—
ns
tLOAD_REG
Min Pulse for CIB_LOAD_REG
—
10
—
ns
—
5
—
ns
tROTATE-SETUP
Min time for CIB dynamic phase controls to be stable
fore CIB_ROTATE
Min pulse width for CIB_ROTATE to maintain “0” or
“1”
tROTATE-WD
—
4
—
VCO cycles
Notes:
1. Jitter sample is taken over 10,000 samples for Periodic jitter, and 2,000 samples for Cycle-to-Cycle jitter of the primary PLL
output with clean reference clock with no additional I/O toggling.
2. Output clock is valid after tLOCK for PLL reset and dynamic delay adjustment.
3. Period jitter and cycle-to-cycle jitter numbers are guaranteed for fPFD > 10 MHz. For fPFD < 10 MHz, the jitter numbers may not
be met in certain conditions.
© 2016-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02014-1.1
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ECP5™ Automotive Family
Data Sheet
3.20. SERDES High-Speed Data Transmitter
Table 3.22. Serial Output Timing and Levels
Symbol
Description
Min
amplitude1, 2
Typ
Max
Unit
VTX-DIFF-PP
Peak-Peak Differential voltage on selected
–25%
—
25%
mV, p-p
VTX-CM-DC
Output common mode voltage
—
VCCHTX / 2
—
mV, p-p
TTX-R
Rise time (20% to 80%)
50
—
—
ps
TTX-F
Fall time (80% to 20%)
50
—
—
ps
TTX-CM-AC-P
RMS AC peak common-mode output voltage
—
—
20
mV
Single ended output impedance for 50/75 Ω
–20%
50/75
20%
Ω
Single ended output impedance for 6K Ω
ZTX_SE
–25%
6K
25%
Ω
RLTX_DIFF
Differential return loss with package included 3
—
—
–10
dB
RLTX_COM
Common mode return loss with package included 3
—
—
–6
dB
Notes:
1. Measured with 50 Ω Tx Driver impedance at VCCHTX±5%.
2. Refer to ECP5 and ECP5-5G SERDES/PCS Usage Guide (TN1261) for settings of Tx amplitude.
3. Return los = −10 dB (differential), –6 dB (common mode) for 100 MHz ≤ f 11 pins in group)
Total DQS Groups
4.3.2. LAE5U
Pin Information Summary
LAE5U-12
Pin Type
381 caBGA
General Purpose Inputs/Outputs per Bank
Bank 0
24
Bank 1
32
Bank 2
32
Bank 3
32
Bank 4
0
Bank 6
32
Bank 7
32
Bank 8
13
Total Single-Ended User I/O
197
VCC
20
VCCAUX (Core)
VCCIO
TAP
4
Bank 0
2
Bank 1
2
Bank 2
3
Bank 3
3
Bank 4
0
Bank 6
3
Bank 7
3
Bank 8
2
4
Miscellaneous Dedicated Pins
7
GND
99
NC
26
Reserved
6
Total Balls
381
© 2016-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
92
FPGA-DS-02014-1.1
ECP5™ Automotive Family
Data Sheet
LAE5U (Continued)
LAE5U-12
Pin Information Summary
Pin Type
381 caBGA
Bank 0
High Speed Differential Input / Output Pairs
Bank 1
0
Bank 2
16/8
Bank 3
16/8
Bank 4
0
Bank 6
16/8
Bank 7
16/8
Bank 8
Total DQS Groups
0
64/32
Total High Speed Differential I/O Pairs
DQS Groups (> 11 pins in group)
0
Bank 0
0
Bank 1
0
Bank 2
2
Bank 3
2
Bank 4
0
Bank 6
2
Bank 7
2
Bank 8
0
8
© 2016-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02014-1.1
93
ECP5™ Automotive Family
Data Sheet
5. Ordering Information
5.1. ECP5 Automotive Part Number Description
LAE5U - XX - X XXXXX X
Grade
E = Automotive
Device Family
LAE5U (ECP5 FPGA)
Logic Capacity
12F = 12K LUTs
Package
BG381 = 381-ball caBGA
Speed
6 = Slowest
7 = Fastest
LAE5UM - XX - X XXXXX X
Device Family
LAE5UM (ECP5 FPGA with SERDES)
Grade
E = Automotive
Logic Capacity
25F = 25K LUTs
45F = 45K LUTs
Package
BG381 = 381-ball caBGA
Speed
6 = Slowest
7 = Fastest
5.2. Ordering Part Numbers
5.2.1. Automotive
Part number
Grade
Package
Pins
Temp.
LUTs (K)
SERDES
LAE5U-12F-6BG381E
–6
Lead free caBGA
381
Automotive
12
No
LAE5U-12F-7BG381E
–7
Lead free caBGA
381
Automotive
12
No
LAE5UM-25F-6BG381E
–6
Lead free caBGA
381
Automotive
24
Yes
LAE5UM-25F-7BG381E
–7
Lead free caBGA
381
Automotive
24
Yes
LAE5UM-45F-6BG381E
–6
Lead free caBGA
381
Automotive
44
Yes
LAE5UM-45F-7BG381E
–7
Lead free caBGA
381
Automotive
44
Yes
© 2016-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
94
FPGA-DS-02014-1.1
ECP5™ Automotive Family
Data Sheet
Supplemental Information
A variety of technical notes for the ECP5 Automotive family are available.
High-Speed PCB Design Considerations (TN1033)
Transmission of High-Speed Serial Signals Over Common Cable Media (TN1066)
PCB Layout Recommendations for BGA Packages (TN1074)
Minimizing System Interruption During Configuration Using TransFR Technology (TN1087)
Electrical Recommendations for Lattice SERDES (FPGA-TN-02077)
LatticeECP3, ECP-5 and ECP5-5G Soft Error Detection (SED)/Correction (SEC) Usage Guide (TN1184)
Using TraceID (TN1207)
Sub-LVDS Signaling Using Lattice Devices (TN1210)
Advanced Security Encryption Key Programming Guide for ECP5, ECP5-5G, LatticeECP3, and LatticeECP2/MS
Devices (TN1215)
LatticeECP3, LatticeECP2/M, ECP5 and ECP5-5G Dual Boot and Multiple Boot Feature (TN1216)
ECP5 and ECP5-5G sysCONFIG Usage Guide (FPGA-TN-02039)
ECP5 and ECP5-5G SERDES/PCS Usage Guide (TN1261)
ECP5 and ECP5-5G sysIO Usage Guide (TN1262)
ECP5 and ECP5-5G sysClock PLL/DLL Design and Usage Guide (TN1263)
ECP5 and ECP5-5G Memory Usage Guide (TN1264)
ECP5 and ECP5-5G High-Speed I/O Interface (TN1265)
Power Consumption and Management for ECP5 and ECP5-5G Devices (TN1266)
ECP5 and ECP5-5G sysDSP Usage Guide (TN1267)
ECP5 and ECP5-5G Hardware Checklist (FPGA-TN-02038)
Solder Reflow Guide for Surface Mount Devices (FPGA-TN-02041)
ECP5 and ECP5-5G PCI Express Soft IP Ease of Use Guidelines (FPGA-TN-02045)
Programming External SPI Flash through JTAG for ECP5/ECP5-5G (FPGA-TN-02050)
Adding Scalable Power and Thermal Management to ECP5 Using L-ASC10 (AN6095)
For further information on interface standards, refer to the following websites:
JEDEC Standards (LVTTL, LVCMOS, SSTL): www.jedec.org
PCI: www.pcisig.com
© 2016-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02014-1.1
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ECP5™ Automotive Family
Data Sheet
Revision History
Revision 1.1, June 2018
Section
All
Change Summary
Removed preliminary.
Features
Architecture
Changed ECP5 to ECP5UM Automotive.
Changed figure caption for Figure 2.11.
Changed description in the SERDES and Physical Coding Sublayer section.
Added data to SGMII standard in Table 2.13. LAE5UM SERDES Standard Support.
DC and Switching Characteristics
Updated the maximum value for VCC symbol in Table 3.1. Absolute Maximum Ratings.
Updated device support for VCCAUXA symbol, and contents of Note 6 for Table 3.2.
Recommended Operating Conditions.
Updated maximum value for the VPORUP symbol in Table 3.4. Power-On-Reset Voltage
Levels.
Updated Table 3.7. DC Electrical Characteristics.
Changed table caption for Table 3.9.
Updated note contents for Table 3.8. Standby ECP5 Automotive Supply Current, Table
3.9. ECP5UM Automotive, Table 3.10. sysI/O Recommended Operating Conditions,
Table 3.25. Serial Input Data Specifications, Table 3.27. External Reference Clock
Specification (refclkp/refclkn), and the sysI/O Single-Ended DC Electrical Characteristics
section.
Changed table note contents in the sysI/O Single-Ended DC Electrical Characteristics
section.
Updated timing value and note contents in Table 3.17. Pin-to-Pin Performance and
Table 3.18. Register-to-Register Performance.
Added values for –7 speed grade in Table 3.20. ECP5 Automotive External Switching
Characteristics.
Pinout Information
Updated table in the Signal Descriptions section by:
removing “for ECP5” from the VCCAx signal in the SERDES Function area;
changing “ECP5” to “ECP5UM Automotive” for VCCHRX_D[dual_num]CH[chan_num]
and VCCHRX_D[dual_num]CH[chan_num] signals in the SERDES Function area.
Ordering Information
Supplemental Information
Updated the documents list.
Updated speed in the ECP5 Automotive Part Number Description section.
Updated table in the Ordering Part Numbers section.
Revision 1.0, September 2016
Section
All
Change Summary
Initial preliminary release.
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All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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