LA-LatticeXP2 Family Data Sheet
DS1024 Version 1.5, February 2015
LA-LatticeXP2 Family Data Sheet
Introduction
February 2015
Data Sheet DS1024
Flexible I/O Buffer
Features
• sysIO™ buffer supports:
– LVCMOS 33/25/18/15/12; LVTTL
– SSTL 33/25/18 class I, II
– HSTL15 class I; HSTL18 class I, II
– PCI
– LVDS, Bus-LVDS, MLVDS, LVPECL, RSDS
flexiFLASH™ Architecture
•
•
•
•
•
•
Instant-on
Infinitely reconfigurable
Single chip
FlashBAK™ technology
Serial TAG memory
Design security
Pre-engineered Source Synchronous
Interfaces
AEC-Q100 Tested and Qualified
Live Update Technology
• TransFR™ technology
• Secure updates with 128 bit AES encryption
• Dual-boot with external SPI
• DDR / DDR2 interfaces up to 200 MHz
• 7:1 LVDS interfaces support display applications
• XGMII
Density And Package Options
• 5k to 17k LUT4s, 86 to 358 I/Os
• csBGA, ftBGA, TQFP and PQFP packages
• Density migration supported
sysDSP™ Block
• Three to five blocks for high performance
Multiply and Accumulate
• 12 to 20 18 x 18 multipliers
• Each block supports one 36 x 36 multiplier or
four 18 x 18 or eight 9 x 9 multipliers
Embedded and Distributed Memory
Flexible Device Configuration
• SPI (master and slave) Boot Flash Interface
• Dual Boot Image supported
• Soft Error Detect (SED) macro embedded
System Level Support
• Up to 276 kbits sysMEM™ EBR
• Up to 35 kbits Distributed RAM
• IEEE 1149.1 and IEEE 1532 Compliant
• On-chip oscillator for initialization & general use
• Devices operate with 1.2 V power supply
sysCLOCK™ PLLs
• Up to four analog PLLs per device
• Clock multiply, divide and phase shifting
Table 1-1. LA-LatticeXP2 Family Selection Guide
Device
LA-XP2-5
LA-XP2-8
LA-XP2-17
LUTs (K)
5
8
17
Distributed RAM (kbits)
10
18
35
EBR SRAM (kbits)
166
221
276
EBR SRAM Blocks
9
12
15
sysDSP Blocks
3
4
5
18 x 18 Multipliers
12
16
20
VCC Voltage
1.2
1.2
1.2
2
2
4
172
201
201
GPLL
Max Available I/O
Packages and I/O Combinations
132-Ball csBGA (8 x 8 mm)
86
86
144-Pin TQFP (20 x 20 mm)
100
100
208-Pin PQFP (28 x 28 mm)
146
146
146
256-Ball ftBGA (17 x17 mm)
172
201
201
© 2015 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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1-1
DS1024 Introduction_01.4
Introduction
LatticeXP2 Family Data Sheet
Introduction
LA-LatticeXP2 devices combine a Look-up Table (LUT) based FPGA fabric with non-volatile Flash cells in an architecture referred to as flexiFLASH.
The flexiFLASH approach provides benefits including instant-on, infinite reconfigurability, on chip storage with
FlashBAK embedded block memory and Serial TAG memory and design security. The parts also support Live
Update technology with TransFR, 128-bit AES Encryption and Dual-boot technologies.
The LA-LatticeXP2 FPGA fabric was optimized for the new technology from the outset with high performance and
low cost in mind. LA-LatticeXP2 devices include LUT-based logic, distributed and embedded memory, Phase
Locked Loops (PLLs), pre-engineered source synchronous I/O support and enhanced sysDSP blocks.
Lattice Diamond® design software allows large and complex designs to be efficiently implemented using the LALatticeXP2 family of FPGA devices. Synthesis library support for LA-LatticeXP2 is available for popular logic synthesis tools. The Diamond software uses the synthesis tool output along with the constraints from its floor planning
tools to place and route the design in the LA-LatticeXP2 device. The Diamond design tool extracts the timing from
the routing and back-annotates it into the design for timing verification.
Lattice provides many pre-designed Intellectual Property (IP) LatticeCORE™ modules for the LA-LatticeXP2 family. By using these IPs as standardized blocks, designers are free to concentrate on the unique aspects of their
design, increasing their productivity.
1-2
LA-LatticeXP2 Family Data Sheet
Architecture
February 2015
Data Sheet DS1024
Architecture Overview
Each LA-LatticeXP2 device contains an array of logic blocks surrounded by Programmable I/O Cells (PIC). Interspersed between the rows of logic blocks are rows of sysMEM™ Embedded Block RAM (EBR) and a row of sysDSP™ Digital Signal Processing blocks as shown in Figure 2-1.
On the left and right sides of the Programmable Functional Unit (PFU) array, there are Non-volatile Memory Blocks.
In configuration mode the nonvolatile memory is programmed via the IEEE 1149.1 TAP port or the sysCONFIG™
peripheral port. On power up, the configuration data is transferred from the Non-volatile Memory Blocks to the configuration SRAM. With this technology, expensive external configuration memory is not required, and designs are
secured from unauthorized read-back. This transfer of data from non-volatile memory to configuration SRAM via
wide busses happens in microseconds, providing an “instant-on” capability that allows easy interfacing in many
applications. LA-LatticeXP2 devices can also transfer data from the sysMEM EBR blocks to the Non-volatile Memory Blocks at user request.
There are two kinds of logic blocks, the PFU and the PFU without RAM (PFF). The PFU contains the building
blocks for logic, arithmetic, RAM and ROM functions. The PFF block contains building blocks for logic, arithmetic
and ROM functions. Both PFU and PFF blocks are optimized for flexibility allowing complex designs to be implemented quickly and efficiently. Logic Blocks are arranged in a two-dimensional array. Only one type of block is used
per row.
LA-LatticeXP2 devices contain one or more rows of sysMEM EBR blocks. sysMEM EBRs are large dedicated 18 kbit
memory blocks. Each sysMEM block can be configured in a variety of depths and widths of RAM or ROM. In addition,
LA-LatticeXP2 devices contain up to two rows of DSP Blocks. Each DSP block has multipliers and adder/accumulators, which are the building blocks for complex signal processing capabilities.
Each PIC block encompasses two PIOs (PIO pairs) with their respective sysIO buffers. The sysIO buffers of the LALatticeXP2 devices are arranged into eight banks, allowing the implementation of a wide variety of I/O standards.
PIO pairs on the left and right edges of the device can be configured as LVDS transmit/receive pairs. The PIC logic
also includes pre-engineered support to aid in the implementation of high speed source synchronous standards
such as 7:1 LVDS interfaces, found in many display applications, and memory interfaces including DDR and DDR2.
Other blocks provided include PLLs and configuration functions. The LA-LatticeXP2 architecture provides up to
four General Purpose PLLs (GPLL) per device. The GPLL blocks are located in the corners of the device.
The configuration block that supports features such as configuration bit-stream de-encryption, transparent updates
and dual boot support is located between banks two and three. Every device in the LA-LatticeXP2 family supports
a sysCONFIG port, muxed with bank seven I/Os, which supports serial device configuration. A JTAG port is provided between banks two and three.
This family also provides an on-chip oscillator. LA-LatticeXP2 devices use 1.2 V as their core voltage.
© 2015 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
2-1
DS1024 Introduction_01.4
Architecture
LatticeXP2 Family Data Sheet
Figure 2-1. Simplified Block Diagram, LA-LatticeXP2-17 Device (Top Level)
sysIO Buffers,
Pre-Engineered Source
Synchronous Support
On-chip
Oscillator
Programmable
Function Units
(PFUs)
SPI Port
sysMEM Block
RAM
JTAG Port
DSP Blocks
Flash
sysCLOCK PLLs
Flexible Routing
PFU Blocks
The core of the LA-LatticeXP2 device is made up of logic blocks in two forms, PFUs and PFFs. PFUs can be programmed to perform logic, arithmetic, distributed RAM and distributed ROM functions. PFF blocks can be programmed to perform logic, arithmetic and ROM functions. Except where necessary, the remainder of this data
sheet will use the term PFU to refer to both PFU and PFF blocks.
Each PFU block consists of four interconnected slices, numbered Slice 0 through Slice 3, as shown in Figure 2-2.
All the interconnections to and from PFU blocks are from routing. There are 50 inputs and 23 outputs associated
with each PFU block.
2-2
Architecture
LatticeXP2 Family Data Sheet
Figure 2-2. PFU Diagram
From
Routing
LUT4 &
CARRY
LUT4 &
CARRY
LUT4 &
CARRY
Slice 0
LUT4 &
CARRY
Slice 1
D
FF
LUT4 &
CARRY
D
D
FF
LUT4
D
FF
FF
LUT4
Slice 3
Slice 2
D
FF
LUT4 &
CARRY
D
FF
To
Routing
Slice
Slice 0 through Slice 2 contain two 4-input combinatorial Look-Up Tables (LUT4), which feed two registers. Slice 3
contains two LUT4s and no registers. For PFUs, Slice 0 and Slice 2 can also be configured as distributed memory,
a capability not available in PFF blocks. Table 2-1 shows the capability of the slices in both PFF and PFU blocks
along with the operation modes they enable. In addition, each PFU contains logic that allows the LUTs to be combined to perform functions such as LUT5, LUT6, LUT7 and LUT8. There is control logic to perform set/reset functions (programmable as synchronous/asynchronous), clock select, chip-select and wider RAM/ROM functions.
Figure 2-3 shows an overview of the internal logic of the slice. The registers in the slice can be configured as positive/negative edge triggered or level sensitive clocks.
Table 2-1. Resources and Modes Available per Slice
PFU BLock
Slice
Resources
PFF Block
Modes
Resources
Modes
Slice 0
2 LUT4s and 2 Registers Logic, Ripple, RAM, ROM 2 LUT4s and 2 Registers
Logic, Ripple, ROM
Slice 1
2 LUT4s and 2 Registers
2 LUT4s and 2 Registers
Logic, Ripple, ROM
Slice 2
2 LUT4s and 2 Registers Logic, Ripple, RAM, ROM 2 LUT4s and 2 Registers
Logic, Ripple, ROM
Slice 3
2 LUT4s
Logic, Ripple, ROM
Logic, ROM
2 LUT4s
Logic, ROM
Slice 0 through Slice 2 have 14 input signals: 13 signals from routing and one from the carry-chain (from the adjacent slice or PFU). There are seven outputs: six to routing and one to carry-chain (to the adjacent PFU). Slice 3 has
13 input signals from routing and four signals to routing. Table 2-2 lists the signals associated with Slice 0 to Slice
2.
2-3
Architecture
LatticeXP2 Family Data Sheet
Figure 2-3. Slice Diagram
FCO from Slice/PFU, FCI into Different Slice/PFU
SLICE
FXB
FXA
OFX1
A1
B1
C1
D1
CO
F1
F/SUM
D
LUT4 &
CARRY*
Q1
FF*
To
Routing
CI
M1
M0
LUT5
Mux
From
Routing
OFX0
A0
B0
C0
D0
CO
LUT4 &
CARRY*
F0
F/SUM
Q0
D
FF*
CI
CE
CLK
LSR
* Not in Slice 3
FCI into Slice/PFU, FCO from Different Slice/PFU
For Slices 0 and 2, memory control signals are generated from Slice 1 as follows:
WCK is CLK
WRE is from LSR
DI[3:2] for Slice 2 and DI[1:0] for Slice 0 data
WAD [A:D] is a 4bit address from Slice 1 LUT input
Table 2-2. Slice Signal Descriptions
Function
Type
Signal Names
Input
Data signal
A0, B0, C0, D0
Inputs to LUT4
Description
Input
Data signal
A1, B1, C1, D1
Inputs to LUT4
Input
Multi-purpose
M0
Multipurpose Input
Input
Multi-purpose
M1
Multipurpose Input
Input
Control signal
CE
Clock Enable
Input
Control signal
LSR
Local Set/Reset
Input
Control signal
CLK
System Clock
Input
Inter-PFU signal
FCI
Fast Carry-In1
Input
Inter-slice signal
FXA
Intermediate signal to generate LUT6 and LUT7
Input
Inter-slice signal
FXB
Intermediate signal to generate LUT6 and LUT7
Output
Data signals
F0, F1
LUT4 output register bypass signals
Output
Data signals
Q0, Q1
Register outputs
Output
Data signals
OFX0
Output of a LUT5 MUX
Output
Data signals
OFX1
Output of a LUT6, LUT7, LUT82 MUX depending on the slice
Output
Inter-PFU signal
FCO
Slice 2 of each PFU is the fast carry chain output1
1. See Figure 2-3 for connection details.
2. Requires two PFUs.
2-4
Architecture
LatticeXP2 Family Data Sheet
Modes of Operation
Each slice has up to four potential modes of operation: Logic, Ripple, RAM and ROM.
Logic Mode
In this mode, the LUTs in each slice are configured as LUT4s. A LUT4 has 16 possible input combinations. Fourinput logic functions are generated by programming the LUT4. Since there are two LUT4s per slice, a LUT5 can be
constructed within one slice. Larger LUTs such as LUT6, LUT7 and LUT8, can be constructed by concatenating
two or more slices. Note that a LUT8 requires more than four slices.
Ripple Mode
Ripple mode allows efficient implementation of small arithmetic functions. In ripple mode, the following functions
can be implemented by each slice:
• Addition 2-bit
• Subtraction 2-bit
• Add/Subtract 2-bit using dynamic control
• Up counter 2-bit
• Down counter 2-bit
• Up/Down counter with async clear
• Up/Down counter with preload (sync)
• Ripple mode multiplier building block
• Multiplier support
• Comparator functions of A and B inputs
– A greater-than-or-equal-to B
– A not-equal-to B
– A less-than-or-equal-to B
Two carry signals, FCI and FCO, are generated per slice in this mode, allowing fast arithmetic functions to be constructed by concatenating slices.
RAM Mode
In this mode, a 16x4-bit distributed Single Port RAM (SPR) can be constructed using each LUT block in Slice 0 and
Slice 2 as a 16x1-bit memory. Slice 1 is used to provide memory address and control signals. A 16x2-bit Pseudo
Dual Port RAM (PDPR) memory is created by using one slice as the read-write port and the other companion slice
as the read-only port.
The Lattice design tools support the creation of a variety of different size memories. Where appropriate, the software will construct these using distributed memory primitives that represent the capabilities of the PFU. Table 2-3
shows the number of slices required to implement different distributed RAM primitives. For more information on
using RAM in LA-LatticeXP2 devices, see TN1137, LatticeXP2 Memory Usage Guide.
Table 2-3. Number of Slices Required For Implementing Distributed RAM
Number of slices
SPR 16x4
PDPR 16x4
3
3
Note: SPR = Single Port RAM, PDPR = Pseudo Dual Port RAM
ROM Mode
ROM mode uses the LUT logic; hence, Slices 0 through 3 can be used in the ROM mode. Preloading is accomplished through the programming interface during PFU configuration.
2-5
Architecture
LatticeXP2 Family Data Sheet
Routing
There are many resources provided in the LA-LatticeXP2 devices to route signals individually or as busses with
related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing)
segments.
The inter-PFU connections are made with x1 (spans two PFU), x2 (spans three PFU) or x6 (spans seven PFU)
connections. The x1 and x2 connections provide fast and efficient connections in horizontal and vertical directions.
The x2 and x6 resources are buffered to allow both short and long connections routing between PFUs.
The LA-LatticeXP2 family has an enhanced routing architecture to produce a compact design. The Diamond
design tool takes the output of the synthesis tool and places and routes the design. Generally, the place and route
tool is completely automatic, although an interactive routing editor is available to optimize the design.
sysCLOCK Phase Locked Loops (PLL)
The sysCLOCK PLLs provide the ability to synthesize clock frequencies. The LA-LatticeXP2 family supports
between two and four full featured General Purpose PLLs (GPLL). The architecture of the GPLL is shown in
Figure 2-4.
CLKI, the PLL reference frequency, is provided either from the pin or from routing; it feeds into the Input Clock
Divider block. CLKFB, the feedback signal, is generated from CLKOP (the primary clock output) or from a user
clock pin/logic. CLKFB feeds into the Feedback Divider and is used to multiply the reference frequency.
Both the input path and feedback signals enter the Voltage Controlled Oscillator (VCO) block. The phase and frequency of the VCO are determined from the input path and feedback signals. A LOCK signal is generated by the
VCO to indicate that the VCO is locked with the input clock signal.
The output of the VCO feeds into the CLKOP Divider, a post-scalar divider. The duty cycle of the CLKOP Divider
output can be fine tuned using the Duty Trim block, which creates the CLKOP signal. By allowing the VCO to operate at higher frequencies than CLKOP, the frequency range of the GPLL is expanded. The output of the CLKOP
Divider is passed through the CLKOK Divider, a secondary clock divider, to generate lower frequencies for the
CLKOK output. For applications that require even lower frequencies, the CLKOP signal is passed through a divideby-three divider to produce the CLKOK2 output. The CLKOK2 output is provided for applications that use source
synchronous logic. The Phase/Duty Cycle/Duty Trim block is used to adjust the phase and duty cycle of the CLKOP
Divider output to generate the CLKOS signal. The phase/duty cycle setting can be pre-programmed or dynamically
adjusted.
The clock outputs from the GPLL; CLKOP, CLKOK, CLKOK2 and CLKOS, are fed to the clock distribution network.
For further information on the GPLL see TN1126, LatticeXP2 sysCLOCK PLL Design and Usage Guide.
2-6
Architecture
LatticeXP2 Family Data Sheet
Figure 2-4. General Purpose PLL (GPLL) Diagram
WRDEL
DDUTY
DPHASE
3
Phase/
Duty Cycle/
Duty Trim
CLKI
Divider
CLKI
PFD
CLKFB
VCO/
LOOP FILTER
CLKOP
Divider
CLKFB
Divider
CLKOK2
CLKOS
CLKOP
Duty Trim
CLKOK
CLKOK
Divider
Internal Feedback
RSTK
RST
Lock
Detect
LOCK
Table 2-4 provides a description of the signals in the GPLL blocks.
Table 2-4. GPLL Block Signal Descriptions
Signal
I/O
Description
CLKI
I
Clock input from external pin or routing
CLKFB
I
PLL feedback input from CLKOP (PLL internal), from clock net (CLKOP) or from a user clock
(PIN or logic)
RST
I
“1” to reset PLL counters, VCO, charge pumps and M-dividers
RSTK
I
“1” to reset K-divider
DPHASE [3:0]
I
DPA Phase Adjust input
DDDUTY [3:0]
I
DPA Duty Cycle Select input
WRDEL
I
DPA Fine Delay Adjust input
CLKOS
O
PLL output clock to clock tree (phase shifted/duty cycle changed)
CLKOP
O
PLL output clock to clock tree (no phase shift)
CLKOK
O
PLL output to clock tree through secondary clock divider
CLKOK2
O
PLL output to clock tree (CLKOP divided by 3)
LOCK
O
“1” indicates PLL LOCK to CLKI
Clock Dividers
LA-LatticeXP2 devices have two clock dividers, one on the left side and one on the right side of the device. These
are intended to generate a slower-speed system clock from a high-speed edge clock. The block operates in a ÷2,
÷4 or ÷8 mode and maintains a known phase relationship between the divided down clock and the high-speed
clock based on the release of its reset signal. The clock dividers can be fed from the CLKOP output from the
GPLLs or from the Edge Clocks (ECLK). The clock divider outputs serve as primary clock sources and feed into the
clock distribution network. The Reset (RST) control signal resets the input and forces all outputs to low. The
RELEASE signal releases outputs to the input clock. For further information on clock dividers, see TN1126,
LatticeXP2 sysCLOCK PLL Design and Usage Guide. Figure 2-5 shows the clock divider connections.
2-7
Architecture
LatticeXP2 Family Data Sheet
Figure 2-5. Clock Divider Connections
ECLK
÷1
CLKOP (GPLL)
÷2
CLKDIV
÷4
RST
÷8
RELEASE
Clock Distribution Network
LA-LatticeXP2 devices have eight quadrant-based primary clocks and between six and eight flexible region-based
secondary clocks/control signals. Two high performance edge clocks are available on each edge of the device to
support high speed interfaces. The clock inputs are selected from external I/Os, the sysCLOCK PLLs, or routing.
Clock inputs are fed throughout the chip via the primary, secondary and edge clock networks.
Primary Clock Sources
LA-LatticeXP2 devices derive primary clocks from four sources: PLL outputs, CLKDIV outputs, dedicated clock
inputs and routing. LA-LatticeXP2 devices have two to four sysCLOCK PLLs, located in the four corners of the
device. There are eight dedicated clock inputs, two on each side of the device. Figure 2-6 shows the primary clock
sources.
2-8
Architecture
LatticeXP2 Family Data Sheet
Figure 2-6. Primary Clock Sources for LatticeXP2-17
Clock Input
Clock Input
From Routing
PLL Input
GPLL
GPLL
CLK
DIV
CLK
DIV
Clock
Input
Clock
Input
Primary Clock Sources
to Eight Quadrant Clock Selection
Clock
Input
PLL Input
PLL Input
Clock
Input
GPLL
GPLL
From Routing
Clock Input
Clock Input
Note: This diagram shows sources for the LA-LatticeXP2-17 device. Smaller LA-LatticeXP2 devices have two GPLLs.
2-9
PLL Input
Architecture
LatticeXP2 Family Data Sheet
Secondary Clock/Control Sources
LA-LatticeXP2 devices derive secondary clocks (SC0 through SC7) from eight dedicated clock input pads and the
rest from routing. Figure 2-7 shows the secondary clock sources.
Figure 2-7. Secondary Clock Sources
Clock
Input
From
Routing
Clock
Input
From
Routing
From
Routing
From
Routing
From Routing
From Routing
From Routing
From Routing
Clock Input
Clock Input
Secondary Clock Sources
Clock Input
Clock Input
From Routing
From Routing
From Routing
From Routing
From
Routing
From
Routing
From
Routing
Clock
Input
Clock
Input
2-10
From
Routing
Architecture
LatticeXP2 Family Data Sheet
Edge Clock Sources
Edge clock resources can be driven from a variety of sources at the same edge. Edge clock resources can be
driven from adjacent edge clock PIOs, primary clock PIOs, PLLs and clock dividers as shown in Figure 2-8.
Figure 2-8. Edge Clock Sources
Clock Input
Clock Input
From
Routing
From
Routing
Sources for top
edge clocks
PLL
Input
GPLL
CLKOP
CLKOP
CLKOS
CLKOS GPLL
From Routing
From Routing
Clock
Input
Clock
Input
Eight Edge Clocks (ECLK)
Two Clocks per Edge
Clock
Input
Clock
Input
From Routing
PLL
Input
PLL
Input
From Routing
GPLL
CLKOP
CLKOP
CLKOS
CLKOS GPLL
PLL
Input
Sources for right edge clocks
Sources for left edge clocks
Sources for
bottom edge
clocks
From
Routing
From
Routing
Clock Input
Clock Input
Note: This diagram shows sources for the LA-LatticeXP2-17 device. Smaller LA-LatticeXP2 devices have two GPLLs.
2-11
Architecture
LatticeXP2 Family Data Sheet
Primary Clock Routing
The clock routing structure in LA-LatticeXP2 devices consists of a network of eight primary clock lines (CLK0
through CLK7) per quadrant. The primary clocks of each quadrant are generated from muxes located in the center
of the device. All the clock sources are connected to these muxes. Figure 2-9 shows the clock routing for one quadrant. Each quadrant mux is identical. If desired, any clock can be routed globally.
Figure 2-9. Per Quadrant Primary Clock Selection
Primary Clock Sources: PLLs + CLKDIVs + PIOs + Routing
30:1
30:1
30:1
30:1
30:1
30:1
29:1
29:1
DCS
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
29:1
29:1
DCS
CLK7
8 Primary Clocks (CLK0 to CLK7) per Quadrant
Dynamic Clock Select (DCS)
The DCS is a smart multiplexer function available in the primary clock routing. It switches between two independent
input clock sources without any glitches or runt pulses. This is achieved irrespective of when the select signal is
toggled. There are two DCS blocks per quadrant; in total, eight DCS blocks per device. The inputs to the DCS block
come from the center muxes. The output of the DCS is connected to primary clocks CLK6 and CLK7 (see Figure 29).
Figure 2-10 shows the timing waveforms of the default DCS operating mode. The DCS block can be programmed
to other modes. For more information on the DCS, see TN1126, LatticeXP2 sysCLOCK PLL Design and Usage
Guide.
Figure 2-10. DCS Waveforms
CLK0
CLK1
SEL
DCSOUT
Secondary Clock/Control Routing
Secondary clocks in the LA-LatticeXP2 devices are region-based resources. The benefit of region-based
resources is the relatively low injection delay and skew within the region, as compared to primary clocks. EBR
rows, DSP rows and a special vertical routing channel bound the secondary clock regions. This special vertical
routing channel aligns with either the left edge of the center DSP block in the DSP row or the center of the DSP
row. Figure 2-11 shows this special vertical routing channel and the six secondary clock regions for the LA-
2-12
Architecture
LatticeXP2 Family Data Sheet
LatticeXP2-17. All LA-LatticeXP2 devices have six secondary clock regions and four secondary clocks (SC0 to
SC3) which are distributed to every region.
The secondary clock muxes are located in the center of the device. Figure 2-12 shows the mux structure of the
secondary clock routing. Secondary clocks SC0 to SC3 are used for clock and control and SC4 to SC7 are used for
high fan-out signals.
Figure 2-11. Secondary Clock Regions LatticeXP2-17
I/O Bank 1
Secondary Clock
Region 6
Secondary Clock
Region 2
Secondary Clock
Region 5
Secondary Clock
Region 3
Secondary Clock
Region 4
I/O Bank 5
I/O Bank 4
I/O Bank 2
Secondary Clock
Region 1
Vertical Routing
Channel Regional
Boundary
EBR Row
Regional
Boundary
I/O Bank 3
I/O Bank 6
I/O Bank 7
I/O Bank 0
DSP Row
Regional
Boundary
Figure 2-12. Secondary Clock Selection
Secondary Clock Feedlines: 8 PIOs + 16 Routing
24:1
SC0
24:1
SC1
24:1
SC2
24:1
SC3
24:1
SC4
24:1
SC5
24:1
SC6
24:1
SC7
4 Secondary Clocks/CE/LSR (SC0 to SC3) per Region
Clock/Control
4 High Fan-out Data Signals (SC4 to SC7) per Region
High Fan-Out Data
2-13
Architecture
LatticeXP2 Family Data Sheet
Slice Clock Selection
Figure 2-13 shows the clock selections and Figure 2-14 shows the control selections for Slice 0 through Slice 2. All
the primary clocks and the four secondary clocks are routed to this clock selection mux. Other signals, via routing,
can be used as clock inputs to the slices. Slice controls are generated from the secondary clocks or other signals
connected via routing.
If none of the signals are selected for both clock and control, then the default value of the mux output is 1. Slice 3
does not have any registers; therefore it does not have the clock or control muxes.
Figure 2-13. Slice 0 through Slice 2 Clock Selection
Primary Clock
8
Secondary Clock
Clock to Slice
4
25:1
Routing
12
Vcc
1
Figure 2-14. Slice 0 through Slice 2 Control Selection
Secondary Clock
3
Slice Control
Routing
16:1
12
Vcc
1
Edge Clock Routing
LA-LatticeXP2 devices have eight high-speed edge clocks that are intended for use with the PIOs in the implementation of high-speed interfaces. Each device has two edge clocks per edge. Figure 2-15 shows the selection muxes
for these clocks.
2-14
Architecture
LatticeXP2 Family Data Sheet
Figure 2-15. Edge Clock Mux Connections
Top and Bottom
Edge Clocks
ECLK1/ ECLK2
Clock Input Pad
(Both Muxes)
Routing
Left and Right
Edge Clocks
ECLK1
Input Pad
GPLL Input Pad
GPLL Output CLKOP
Routing
Left and Right
Edge Clocks
ECLK2
Input Pad
GPLL Input Pad
GPLL Output CLKOS
Routing
sysMEM Memory
LA-LatticeXP2 devices contains a number of sysMEM Embedded Block RAM (EBR). The EBR consists of 18 Kbit
RAM with dedicated input and output registers.
sysMEM Memory Block
The sysMEM block can implement single port, dual port or pseudo dual port memories. Each block can be used in
a variety of depths and widths as shown in Table 2-5. FIFOs can be implemented in sysMEM EBR blocks by using
support logic with PFUs. The EBR block supports an optional parity bit for each data byte to facilitate parity checking. EBR blocks provide byte-enable support for configurations with18-bit and 36-bit data widths.
2-15
Architecture
LatticeXP2 Family Data Sheet
Table 2-5. sysMEM Block Con• gurations
Memory Mode
Configurations
Single Port
16,384 x 1
8,192 x 2
4,096 x 4
2,048 x 9
1,024 x 18
512 x 36
True Dual Port
16,384 x 1
8,192 x 2
4,096 x 4
2,048 x 9
1,024 x 18
Pseudo Dual Port
16,384 x 1
8,192 x 2
4,096 x 4
2,048 x 9
1,024 x 18
512 x 36
Bus Size Matching
All of the multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB
word 0 to MSB word 0, LSB word 1 to MSB word 1, and so on. Although the word size and number of words for
each port varies, this mapping scheme applies to each port.
FlashBAK EBR Content Storage
All the EBR memory in the LA-LatticeXP2 is shadowed by Flash memory. Optionally, initialization values for the
memory blocks can be defined using the Lattice Diamond design tool. The initialization values are loaded into the
Flash memory during device programming and into the SRAM at power up or whenever the device is reconfigured.
This feature is ideal for the storage of a variety of information such as look-up tables and microprocessor code. It is
also possible to write the current contents of the EBR memory back to Flash memory. This capability is useful for
the storage of data such as error codes and calibration information. For additional information on the FlashBAK
capability see TN1137, LatticeXP2 Memory Usage Guide.
Figure 2-16. FlashBAK Technology
Write to Flash During
Programming
Make Infinite Reads and
Writes to EBR
Flash
FPGA Logic
JTAG / SPI Port
EBR
Write From Flash to
EBR During Configuration /
Write From EBR to Flash
on User Command
Memory Cascading
Larger and deeper blocks of RAMs can be created using EBR sysMEM Blocks. Typically, the Lattice design tools
cascade memory transparently, based on speci• c design inputs.
Single, Dual and Pseudo-Dual Port Modes
In all the sysMEM RAM modes the input data and address for the ports are registered at the input of the memory
array. The output data of the memory is optionally registered at the output.
2-16
Architecture
LatticeXP2 Family Data Sheet
EBR memory supports two forms of write behavior for single port or dual port operation:
1. Normal – Data on the output appears only during a read cycle. During a write cycle, the data (at the current
address) does not appear on the output. This mode is supported for all data widths.
2. Write Through – A copy of the input data appears at the output of the same port during a write cycle. This
mode is supported for all data widths.
Memory Core Reset
The memory array in the EBR utilizes latches at the A and B output ports. These latches can be reset asynchronously or synchronously. RSTA and RSTB are local signals, which reset the output latches associated with Port A
and Port B respectively. GSRN, the global reset signal, resets both ports. The output data latches and associated
resets for both ports are as shown in Figure 2-17.
Figure 2-17. Memory Core Reset
Memory Core
D
SET
Q
Port A[17:0]
LCLR
Output Data
Latches
D
SET
Q
Port B[17:0]
LCLR
RSTA
RSTB
GSRN
Programmable Disable
For further information on the sysMEM EBR block, see TN1137, LatticeXP2 Memory Usage Guide.
EBR Asynchronous Reset
EBR asynchronous reset or GSR (if used) can only be applied if all clock enables are low for a clock cycle before the
reset is applied and released a clock cycle after the low-to-high transition of the reset signal, as shown in Figure 2-18.
The GSR input to the EBR is always asynchronous.
Figure 2-18. EBR Asynchronous Reset (Including GSR) Timing Diagram
Reset
Clock
Clock
Enable
2-17
Architecture
LatticeXP2 Family Data Sheet
If all clock enables remain enabled, the EBR asynchronous reset or GSR may only be applied and released after
the EBR read and write clock inputs are in a steady state condition for a minimum of 1/fMAX (EBR clock). The reset
release must adhere to the EBR synchronous reset setup time before the next active read or write clock edge.
If an EBR is pre-loaded during configuration, the GSR input must be disabled or the release of the GSR during
device Wake Up must occur before the release of the device I/Os becoming active.
These instructions apply to all EBR RAM and ROM implementations.
Note that there are no reset restrictions if the EBR synchronous reset is used and the EBR GSR input is disabled.
sysDSP™ Block
The LA-LatticeXP2 family provides a sysDSP block making it ideally suited for low cost, high performance Digital
Signal Processing (DSP) applications. Typical functions used in these applications include Bit Correlators, Fast
Fourier Transform (FFT) functions, Finite Impulse Response (FIR) Filter, Reed-Solomon Encoder/Decoder, Turbo
Encoder/Decoder and Convolutional Encoder/Decoder. These complex signal processing functions use similar
building blocks such as multiply-adders and multiply-accumulators.
sysDSP Block Approach Compare to General DSP
Conventional general-purpose DSP chips typically contain one to four (Multiply and Accumulate) MAC units with
• xed data-width multipliers; this leads to limited parallelism and limited throughput. Their throughput is increased by
higher clock speeds. The LA-LatticeXP2 family, on the other hand, has many DSP blocks that support different
data-widths. This allows the designer to use highly parallel implementations of DSP functions. The designer can
optimize the DSP performance vs. area by choosing appropriate levels of parallelism. Figure 2-19 compares the
fully serial and the mixed parallel and serial implementations.
Figure 2-19. Comparison of General DSP and LA-LatticeXP2 Approaches
Operand
A
Operand
A
Operand
A
Operand
B
Operand
A
Single
Multiplier
Operand
B
Operand
B
Operand
B
x
M loops
x
Multiplier 0
Multiplier 1
x
Accumulator
(k adds)
Function implemented in
General purpose DSP
x
m/k
loops
Multiplier k
+
m/k
accumulate
Output
Function implemented
in LA-LatticeXP2
sysDSP Block Capabilities
The sysDSP block in the LA-LatticeXP2 family supports four functional elements in three 9, 18 and 36 data path
widths. The user selects a function element for a DSP block and then selects the width and type (signed/unsigned)
of its operands. The operands in the LA-LatticeXP2 family sysDSP Blocks can be either signed or unsigned but not
2-18
Architecture
LatticeXP2 Family Data Sheet
mixed within a function element. Similarly, the operand widths cannot be mixed within a block. DSP elements can
be concatenated.
The resources in each sysDSP block can be con• gured to support the following four elements:
• MULT (Multiply)
• MAC (Multiply, Accumulate)
• MULTADDSUB (Multiply, Addition/Subtraction)
• MULTADDSUBSUM (Multiply, Addition/Subtraction, Accumulate)
The number of elements available in each block depends on the width selected from the three available options: x9,
x18, and x36. A number of these elements are concatenated for highly parallel implementations of DSP functions.
Table 2-6 shows the capabilities of the block.
Table 2-6. Maximum Number of Elements in a Block
x9
x18
x36
MULT
Width of Multiply
8
4
1
MAC
2
2
—
MULTADDSUB
4
2
—
MULTADDSUBSUM
2
1
—
Some options are available in four elements. The input register in all the elements can be directly loaded or can be
loaded as shift register from previous operand registers. By selecting ‘dynamic operation’ the following operations
are possible:
• In the ‘Signed/Unsigned’ options the operands can be switched between signed and unsigned on every cycle.
• In the ‘Add/Sub’ option the Accumulator can be switched between addition and subtraction on every cycle.
• The loading of operands can switch between parallel and serial operations.
MULT sysDSP Element
This multiplier element implements a multiply with no addition or accumulator nodes. The two operands, A and B,
are multiplied and the result is available at the output. The user can enable the input/output and pipeline registers.
Figure 2-20 shows the MULT sysDSP element.
2-19
Architecture
LatticeXP2 Family Data Sheet
Figure 2-20. MULT sysDSP Element
Shift Register B In
Shift Register A In
Multiplier
m
m
n
n
m
Input Data
Register A
n
m
Multiplier
n
Input Data
Register B
x
m+n
(default)
Output
Register
Multiplicand
Pipeline
Register
m
n
Signed A
Input
Register
To
Multiplier
Signed B
Input
Register
To
Multiplier
CLK (CLK0,CLK1,CLK2,CLK3)
CE (CE0,CE1,CE2,CE3)
RST(RST0,RST1,RST2,RST3)
Shift Register B Out
Shift Register A Out
2-20
m+n
Output
Architecture
LatticeXP2 Family Data Sheet
MAC sysDSP Element
In this case, the two operands, A and B, are multiplied and the result is added with the previous accumulated value.
This accumulated value is available at the output. The user can enable the input and pipeline registers but the output register is always enabled. The output register is used to store the accumulated value. The Accumulators in the
DSP blocks in LA-LatticeXP2 family can be initialized dynamically. A registered overflow signal is also available.
The over• ow conditions are provided later in this document. Figure 2-21 shows the MAC sysDSP element.
Figure 2-21. MAC sysDSP
Serial Register B in
Serial Register A in
Multiplicand
m
Preload
m
Accumulator
Input Data
Register A
n
Input Data
Register B
m
Multiplier
n
x
m+n
(default)
Pipeline
Register
n
n
Signed A
Input
Register
Pipeline
Register
To Accumulator
Signed B
Input
Register
Pipeline
Register
To Accumulator
Addn
Input
Register
Pipeline
Register
To Accumulator
Accumsload
Input
Register
Pipeline
Register
To Accumulator
m+n+16
(default)
Output
Register
m
n
n
m+n+16
(default)
Output
Register
Multiplier
CLK (CLK0,CLK1,CLK2,CLK3)
CE (CE0,CE1,CE2,CE3)
RST(RST0,RST1,RST2,RST3)
SROB
SROA
2-21
Output
Overflow
signal
Architecture
LatticeXP2 Family Data Sheet
MULTADDSUB sysDSP Element
In this case, the operands A0 and B0 are multiplied and the result is added/subtracted with the result of the multiplier operation of operands A1 and B1. The user can enable the input, output and pipeline registers. Figure 2-22
shows the MULTADDSUB sysDSP element.
Figure 2-22. MULTADDSUB
Shift Register B In
Shift Register A In
Multiplicand A0
m
CLK (CLK0,CLK1,CLK2,CLK3)
m
CE (CE0,CE1,CE2,CE3)
Multiplier B0
m
n
n
RST (RST0,RST1,RST2,RST3)
Input Data
Register A
n
Multiplier
m
x
n
Input Data
Register B
Pipeline
Register
m
m+n
(default)
Add/Sub
Multiplicand A1
Multiplier B1
m
m+n+1
(default)
m
n
Input Data
Register A
n
Signed B
Addn
Shift Register B Out
n
x
n
Input Data
Register B
Signed A
Multiplier
m
Pipeline
Register
m
Input
Register
Pipeline
Pipe
Register
Reg
To Add/Sub
Input
Register
Pipeline
Pipe
Register
Reg
To Add/Sub
Input
Register
Pipeline
Pipe
Register
Reg
To Add/Sub
Shift Register A Out
2-22
m+n
(default)
Output
Register
n
Output
m+n+1
(default)
Architecture
LatticeXP2 Family Data Sheet
MULTADDSUBSUM sysDSP Element
In this case, the operands A0 and B0 are multiplied and the result is added/subtracted with the result of the multiplier operation of operands A1 and B1. Additionally the operands A2 and B2 are multiplied and the result is added/
subtracted with the result of the multiplier operation of operands A3 and B3. The result of both addition/subtraction
are added in a summation block. The user can enable the input, output and pipeline registers. Figure 2-23 shows
the MULTADDSUBSUM sysDSP element.
Figure 2-23. MULTADDSUBSUM
Shift Register B In
Shift Register A In
Multiplicand A0
m
m
CLK (CLK0,CLK1,CLK2,CLK3)
m
n
n
CE (CE0,CE1,CE2,CE3)
Input Data
Register A
n
n
Input Data
Register B
Multiplier
x
m+n
(default)
Pipeline
Register
m
RST(RST0,RST1,RST2,RST3)
Add/Sub0
n
Multiplicand A1
Multiplier B1
m
m
m+n
(default)
m
n
Input Data
Register A
n
n
Input Data
Register B
Multiplicand A2
n
Multiplier
m+n+1
x
SUM
Pipeline
Register
m
m
m+n+2
Multiplier B2
m
n
n
Input Data
Register A
n
n
Input Data
Register B
Multiplier
x
m+n+2
m+n
(default)
m+n+1
Pipeline
Register
m
Output
Add/Sub1
n
Multiplicand A3
Multiplier B3
m
Output
Register
Multiplier B0
m
n
Input Data
Register A
n
Input Data
Register B
Signed A
Signed B
Addn0
Addn1
Shift Register B Out
m+n
(default)
m
n
m
n
Multiplier
x
Pipeline
Register
m
Input
Register
Pipeline
Register
To Add/Sub0, Add/Sub1
Input
Register
Pipeline
Register
To Add/Sub0, Add/Sub1
Input
Register
Pipeline
Register
To Add/Sub0
Input
Register
Pipeline
Register
To Add/Sub1
Shift Register A Out
Clock, Clock Enable and Reset Resources
Global Clock, Clock Enable (CE) and Reset (RST) signals from routing are available to every DSP block. From four
clock sources (CLK0, CLK1, CLK2, CLK3) one clock is selected for each input register, pipeline register and output
2-23
Architecture
LatticeXP2 Family Data Sheet
register. Similarly, CE and RST are selected from their four respective sources (CE0, CE1, CE2, CE3 and RST0,
RST1, RST2, RST3) at each input register, pipeline register and output register.
Signed and Unsigned with Different Widths
The DSP block supports other widths, in addition to x9, x18 and x36 widths, of signed and unsigned multipliers. For
unsigned operands, unused upper data bits should be • lled to create a valid x9, x18 or x36 operand. For signed
two’s complement operands, sign extension of the most signi• cant bit should be performed until x9, x18 or x36
width is reached. Table 2-7 provides an example of this.
Table 2-7. Sign Extension Example
Number
Unsigned
Unsigned
9-bit
Unsigned
18-bit
Signed
Two’s Complement
Signed 9 Bits
Two’s Complement
Signed 18 Bits
+5
0101
000000101
000000000000000101
0101
000000101
000000000000000101
–6
N/A
N/A
N/A
1010
111111010
111111111111111010
OVERFLOW Flag from MAC
The sysDSP block provides an overflow output to indicate that the accumulator has overflowed. “Roll-over” occurs
and an overflow signal is indicated when any of the following is true: two unsigned numbers are added and the
result is a smaller number than the accumulator, two positive numbers are added with a negative sum or two negative numbers are added with a positive sum. Note that when overflow occurs the overflow flag is present for only
one cycle. By counting these overflow pulses in FPGA logic, larger accumulators can be constructed. The conditions for the overflow signal for signed and unsigned operands are listed in Figure 2-24.
Figure 2-24. Accumulator Over• ow/Under• ow
011111100
011111101
011111110
011111111
100000000
100000001
100000010
252
253
254
255
256
257
258
000000011
000000010
000000001
000000000
3
2
1
0
111111111
111111110
111111101
511
510
509
Unsigned Operation
Overflow signal is generated
for one cycle when this
boundary is crossed
011111100
011111101
011111110
011111111
100000000
100000001
100000010
000000011
000000010
000000001
000000000
111111111
111111110
111111101
252
253
254
255
-256
-255
-254
Signed Operation
2-24
+3
+2
+1
0
-1
-2
-3
Carry signal is generated for
one cycle when this
boundary is crossed
Architecture
LatticeXP2 Family Data Sheet
IPexpress™
The user can access the sysDSP block via the Lattice IPexpress tool, which provides the option to configure each
DSP module (or group of modules), or by direct HDL instantiation. In addition, Lattice has partnered with The MathWorks® to support instantiation in the Simulink® tool, a graphical simulation environment. Simulink works with Diamond to dramatically shorten the DSP design cycle in Lattice FPGAs.
Optimized DSP Functions
Lattice provides a library of optimized DSP IP functions. Some of the IP cores planned for the LA-LatticeXP2 DSP
include the Bit Correlator, FFT functions, FIR Filter, Reed-Solomon Encoder/Decoder, Turbo Encoder/Decoder and
Convolutional Encoder/Decoder. Please contact Lattice to obtain the latest list of available DSP IP cores.
Resources Available in the LA-LatticeXP2 Family
Table 2-8 shows the maximum number of multipliers for each member of the LA-LatticeXP2 family. Table 2-9 shows
the maximum available EBR RAM Blocks and Serial TAG Memory bits in each LA-LatticeXP2 device. EBR blocks,
together with Distributed RAM can be used to store variables locally for fast DSP operations.
Table 2-8. Maximum Number of DSP Blocks in the LA-LatticeXP2 Family
Device
DSP Block
9 x 9 Multiplier
18 x 18 Multiplier
36 x 36 Multiplier
LA-XP2-5
3
24
12
3
LA-XP2-8
4
32
16
4
LA-XP2-17
5
40
20
5
Table 2-9. Embedded SRAM/TAG Memory in the LA-LatticeXP2 Family
Device
EBR SRAM Block
Total EBR SRAM
(kbits)
TAG Memory
(Bits)
LA-XP2-5
9
166
632
LA-XP2-8
12
221
768
LA-XP2-17
15
276
2184
LA-LatticeXP2 DSP Performance
Table 2-10 lists the maximum performance in Millions of MAC (MMAC) operations per second for each member of
the LA-LatticeXP2 family.
Table 2-10. DSP Performance
Device
DSP Block
DSP Performance
MMAC
LA-XP2-5
3
3,900
LA-XP2-8
4
5,200
LA-XP2-17
5
6,500
For further information on the sysDSP block, see TN1140, LatticeXP2 sysDSP Usage Guide.
Programmable I/O Cells (PIC)
Each PIC contains two PIOs connected to their respective sysIO buffers as shown in Figure 2-25. The PIO Block
supplies the output data (DO) and the tri-state control signal (TO) to the sysIO buffer and receives input from the
buffer. Table 2-11 provides the PIO signal list.
2-25
Architecture
LatticeXP2 Family Data Sheet
Figure 2-25. PIC Diagram
PIOA
TD
OPOS1
ONEG1
IOLT0
Tristate
Register
Block
OPOS0
OPOS21
ONEG0
ONEG21
PADA
“T”
IOLD0
Output
Register
Block
sysIO
Buffer
QNEG01
QNEG11
QPOS01
QPOS11
INCK2
INDD
INFF
IPOS0
IPOS1
CLK
CE
LSR
GSRN
ECLK1
ECLK2
DDRCLKPOL1
DQSXFER1
DQS
DEL
Control
Muxes
CLK1
CEO
LSR
GSR
CLK0
CEI
Input
Register
Block
DI
PADB
“C”
PIOB
1. Signals are available on left/right/bottom edges only.
2. Selected blocks.
Two adjacent PIOs can be joined to provide a differential I/O pair (labeled as “T” and “C”) as shown in Figure 2-25.
The PAD Labels “T” and “C” distinguish the two PIOs. Approximately 50% of the PIO pairs on the left and right
edges of the device can be configured as true LVDS outputs. All I/O pairs can operate as inputs.
2-26
Architecture
LatticeXP2 Family Data Sheet
Table 2-11. PIO Signal List
Name
Type
Description
CE
Control from the core
Clock enables for input and output block flip-flops
CLK
Control from the core
System clocks for input and output blocks
ECLK1, ECLK2
Control from the core
Fast edge clocks
LSR
Control from the core
Local Set/Reset
GSRN
Control from routing
Global Set/Reset (active low)
INCK2
Input to the core
Input to Primary Clock Network or PLL reference inputs
DQS
Input to PIO
DQS signal from logic (routing) to PIO
INDD
Input to the core
Unregistered data input to core
INFF
Input to the core
Registered input on positive edge of the clock (CLK0)
IPOS0, IPOS1
Input to the core
Double data rate registered inputs to the core
1
Input to the core
Gearbox pipelined inputs to the core
QNEG01, QNEG11
Input to the core
Gearbox pipelined inputs to the core
OPOS0, ONEG0,
OPOS2, ONEG2
Output data from the core
Output signals from the core for SDR and DDR operation
OPOS1 ONEG1
Tristate control from the core
Signals to Tristate Register block for DDR operation
DEL[3:0]
Control from the core
Dynamic input delay control bits
TD
Tristate control from the core
Tristate signal from the core used in SDR operation
DDRCLKPOL
Control from clock polarity bus Controls the polarity of the clock (CLK0) that feed the DDR input block
DQSXFER
Control from core
1
QPOS0 , QPOS1
Controls signal to the Output block
1. Signals available on left/right/bottom only.
2. Selected I/O.
PIO
The PIO contains four blocks: an input register block, output register block, tristate register block and a control logic
block. These blocks contain registers for operating in a variety of modes along with necessary clock and selection
logic.
Input Register Block
The input register blocks for PIOs contain delay elements and registers that can be used to condition high-speed
interface signals, such as DDR memory interfaces and source synchronous interfaces, before they are passed to
the device core. Figure 2-26 shows the diagram of the input register block.
Input signals are fed from the sysIO buffer to the input register block (as signal DI). If desired, the input signal can
bypass the register and delay elements and be used directly as a combinatorial signal (INDD), a clock (INCK) and,
in selected blocks, the input to the DQS delay block. If an input delay is desired, designers can select either a fixed
delay or a dynamic delay DEL[3:0]. The delay, if selected, reduces input register hold time requirements when
using a global clock.
The input block allows three modes of operation. In the Single Data Rate (SDR) mode, the data is registered, by
one of the registers in the SDR Sync register block, with the system clock. In DDR mode two registers are used to
sample the data on the positive and negative edges of the DQS signal which creates two data streams, D0 and D2.
D0 and D2 are synchronized with the system clock before entering the core. Further information on this topic can
be found in the DDR Memory Support section of this data sheet.
By combining input blocks of the complementary PIOs and sharing registers from output blocks, a gearbox function
can be implemented, that takes a double data rate signal applied to PIOA and converts it as four data streams,
IPOS0A, IPOS1A, IPOS0B and IPOS1B. Figure 2-26 shows the diagram using this gearbox function. For more
information on this topic, see TN1138, LatticeXP2 High Speed I/O Interface.
2-27
Architecture
LatticeXP2 Family Data Sheet
The signal DDRCLKPOL controls the polarity of the clock used in the synchronization registers. It ensures adequate timing when data is transferred from the DQS to system clock domain. For further discussion on this topic,
see the DDR Memory section of this data sheet.
Figure 2-26. Input Register Block
INCK2
To DQS Delay Block 2
DI
(From sysIO
Buffer)
INDD
SDR & Sync
Registers
DDR Registers
Fixed Delay
0
Dynamic Delay
1
0
D
DEL [3:0]
D0
D
IPOS0A
Q
D-Type
/LATCH
1
Q
Clock Transfer Registers
D
Q
QPOS0A
D-Type1
D-Type
From
Routing
IPOS1A
D
Delayed
DQS
0
Q
D1
D
D-Type
D2
Q
D
Q
D-Type
/LATCH
D-Type
D
Q
QPOS1A
D-Type1
To
Routing
1
CLK0 (of PIO A)
DDRCLKPOL
CLKA
True PIO (A) in LVDS I/O Pair
Comp PIO (B) in LVDS I/O Pair
DI
(From sysIO
Buffer)
INCK2
To DQS Delay Block 2
INDD
DDRSRC
Fixed Delay
Dynamic Delay
0
0
D0
1
D
DEL [3:0]
SDR & Sync
Registers
DDR Registers
0
1
Q
1
D-Type
From
Routing
D
Q
D-Type
/LATCH
Clock Transfer Registers
D
Q
IPOS0B
QPOS0B
D-Type1
IPOS1B
D
Delayed
DQS
0
Q
D-Type
D1
0
D
Q
D2
D-Type
1
D
Q
D-Type
/LATCH
D
Q
QPOS1B
D-Type1
1
To
Routing
CLK0 (of PIO B)
Gearbox Configuration Bit
DDRCLKPOL
CLKB
Note: Simplified version does not
show CE and SET/RESET details
1. Shared with output register
2. Selected PIO.
Output Register Block
The output register block provides the ability to register signals from the core of the device before they are passed
to the sysIO buffers. The blocks on the PIOs on the left, right and bottom contain registers for SDR operation that
are combined with an additional latch for DDR operation. Figure 2-27 shows the diagram of the Output Register
Block for PIOs.
In SDR mode, ONEG0 feeds one of the flip-flops that then feeds the output. The flip-flop can be configured as a Dtype or latch. In DDR mode, ONEG0 and OPOS0 are fed into registers on the positive edge of the clock. At the next
clock cycle the registered OPOS0 is latched. A multiplexer running off the same clock cycle selects the correct register to feed the output (D0).
By combining output blocks of the complementary PIOs and sharing some registers from input blocks, a gearbox
function can be implemented, to take four data streams ONEG0A, ONEG1A, ONEG1B and ONEG1B. Figure 2-27
2-28
Architecture
LatticeXP2 Family Data Sheet
shows the diagram using this gearbox function. For more information on this topic, see TN1138, LatticeXP2 High
Speed I/O Interface.
Figure 2-27. Output and Tristate Block
TD
Tristate Logic
D
Q
D-Type
/LATCH
ONEG1
0
1
0
0
D
OPOS1
Q
D
1
Q
Latch
From Routing
To sysIO Buffer
D-Type
TO
1
0
ONEG0
D
Q
0
D-Type*
1
1
D
Q
D-Type
/LATCH
DDR Output
Registers
DO
0
OPOS0
0
Q
D
D-Type*
CLKA
0
Q
D
Latch
D
0
1
1
Q
D
D-Type
1
1
Q
Latch
Clock Transfer
Registers
ECLK1
ECLK2
CLK1
(CLKA)
DQSXFER
Programmable
Control
0
1
0
1
Output Logic
True PIO (A) in LVDS I/O Pair
Comp PIO (B) in LVDS I/O Pair
TD
Tristate Logic
Q
D
D-Type
/LATCH
ONEG1
0
1
0
0
D
OPOS1
Q
D-Type
1
Q
D
TO
1
Latch
From Routing
To sysIO Buffer
ONEG0
D
Q
D
D-Type
/LATCH
Q
D-Type*
DDR Output
Registers
DO
0
OPOS0
0
D
Q
D-Type*
CLKB
ECLK1
ECLK2
CLK1
(CLKB)
DQSXFER
D
D
Q
Latch
Q
D-Type
D
Q
1
1
Latch
Clock Transfer
Registers
0
1
0
1
* Shared with input register
Programmable
Control
Output Logic
Note: Simplified version does not show CE and SET/RESET details
2-29
Architecture
LatticeXP2 Family Data Sheet
Tristate Register Block
The tristate register block provides the ability to register tri-state control signals from the core of the device before
they are passed to the sysIO buffers. The block contains a register for SDR operation and an additional latch for
DDR operation. Figure 2-27 shows the Tristate Register Block with the Output Block
In SDR mode, ONEG1 feeds one of the flip-flops that then feeds the output. The flip-flop can be configured as Dtype or latch. In DDR mode, ONEG1 and OPOS1 are fed into registers on the positive edge of the clock. Then in
the next clock the registered OPOS1 is latched. A multiplexer running off the same clock cycle selects the correct
register for feeding to the output (D0).
Control Logic Block
The control logic block allows the selection and modification of control signals for use in the PIO block. A clock signal is selected from general purpose routing, ECLK1, ECLK2 or a DQS signal (from the programmable DQS pin)
and is provided to the input register block. The clock can optionally be inverted.
DDR Memory Support
PICs have additional circuitry to allow implementation of high speed source synchronous and DDR memory interfaces.
PICs have registered elements that support DDR memory interfaces. Interfaces on the left and right edges are
designed for DDR memories that support 16 bits of data, whereas interfaces on the top and bottom are designed
for memories that support 18 bits of data. One of every 16 PIOs on the left and right and one of every 18 PIOs on
the top and bottom contain delay elements to facilitate the generation of DQS signals. The DQS signals feed the
DQS buses which span the set of 16 or 18 PIOs. Figure 2-28 and Figure 2-29 show the DQS pin assignments in
each set of PIOs.
The exact DQS pins are shown in a dual function in the Logic Signal Connections table in this data sheet. Additional detail is provided in the Signal Descriptions table. The DQS signal from the bus is used to strobe the DDR
data from the memory into input register blocks. For additional information on using DDR memory support, see
TN1138, LatticeXP2 High Speed I/O Interface.
2-30
Architecture
LatticeXP2 Family Data Sheet
Figure 2-28. DQS Input Routing (Left and Right)
PIO A
PADA "T"
PIO B
PADB "C"
PIO A
PADA "T"
PIO B
PADB "C"
LVDS Pair
LVDS Pair
PIO A
PADA "T"
PIO B
PADB "C"
PIO A
PADA "T"
PIO B
PADB "C"
LVDS Pair
LVDS Pair
PIO A
DQS
sysIO
Buffer
Delay
Assigned
DQS Pin
PADA "T"
LVDS Pair
PADB "C"
PIO B
PIO A
PADA "T"
PIO B
PADB "C"
PIO A
PADA "T"
PIO B
PADB "C"
PIO A
PADA "T"
PIO B
PADB "C"
LVDS Pair
LVDS Pair
LVDS Pair
Figure 2-29. DQS Input Routing (Top and Bottom)
PIO A
PADA "T"
PIO B
PADB "C"
PIO A
PADA "T"
PIO B
PADB "C"
LVDS Pair
LVDS Pair
PIO A
PADA "T"
PIO B
PADB "C"
PIO A
PADA "T"
PIO B
PADB "C"
LVDS Pair
LVDS Pair
PIO A
DQS
sysIO
Buffer
Delay
PIO B
Assigned
DQS Pin
PADA "T"
LVDS Pair
PADB "C"
PIO A
PADA "T"
PIO B
PADB "C"
PIO A
PADA "T"
PIO B
PADB "C"
PIO A
PADA "T"
PIO B
PADB "C"
LVDS Pair
LVDS Pair
LVDS Pair
PIO A
PIO B
2-31
PADA "T"
LVDS Pair
PADB "C"
Architecture
LatticeXP2 Family Data Sheet
DLL Calibrated DQS Delay Block
Source synchronous interfaces generally require the input clock to be adjusted in order to correctly capture data at
the input register. For most interfaces a PLL is used for this adjustment. However, in DDR memories the clock,
referred to as DQS, is not free-running, and this approach cannot be used. The DQS Delay block provides the
required clock alignment for DDR memory interfaces.
The DQS signal (selected PIOs only, as shown in Figure 2-30) feeds from the PAD through a DQS delay element to
a dedicated DQS routing resource. The DQS signal also feeds polarity control logic which controls the polarity of
the clock to the sync registers in the input register blocks. Figure 2-30 and Figure 2-31 show how the DQS transition signals are routed to the PIOs.
The temperature, voltage and process variations of the DQS delay block are compensated by a set of 6-bit bus calibration signals from two dedicated DLLs (DDR_DLL) on opposite sides of the device. Each DLL compensates
DQS delays in its half of the device as shown in Figure 2-30. The DLL loop is compensated for temperature, voltage and process variations by the system clock and feedback loop.
Figure 2-30. Edge Clock, DLL Calibration and DQS Local Bus Distribution
I/O Bank 0
Spans 16 PIOs
Left & Right Sides
I/O Bank 1
ECLK1
ECLK2
I/O Bank 7
I/O Bank 2
DQS Input
Delayed
DQS
DDR_DLL
(Right)
DDR_DLL
(Left)
Polarity Control
I/O Bank 6
I/O Bank 3
Spans 18 PIOs
Top & Bottom
Sides
I/O Bank 5
I/O Bank 4
2-32
DQSXFER
DQS Delay
Control Bus
Architecture
LatticeXP2 Family Data Sheet
DQS
Polarity control
DCNTL[6:0]
DQSXFER
CLK1
ECLK2
ECLK1
Figure 2-31. DQS Local Bus
PIO
Output
Register Block
DQSXFER
Input
Register Block
GSR
CEI
DQS
DDR
Datain
PAD
sysIO
Buffer
DI
To Sync
Reg.
CLK1
DQS
To DDR
Reg.
DQS
Strobe
PAD
sysIO
Buffer
PIO
Polarity Control
Logic
DI
DQS
DQSDEL
Calibration bus
from DLL
DCNTL[6:0]
ECLK1
DQSXFER
DQSXFERDEL*
DCNTL[6:0]
*DQSXFERDEL shifts ECLK1 by 90% and is not associated with a particular PIO.
Polarity Control Logic
In a typical DDR memory interface design, the phase relationship between the incoming delayed DQS strobe and
the internal system clock (during the READ cycle) is unknown. The LA-LatticeXP2 family contains dedicated circuits to transfer data between these domains. To prevent set-up and hold violations, at the domain transfer between
DQS (delayed) and the system clock, a clock polarity selector is used. This changes the edge on which the data is
registered in the synchronizing registers in the input register block and requires evaluation at the start of each
READ cycle for the correct clock polarity.
Prior to the READ operation in DDR memories, DQS is in tristate (pulled by termination). The DDR memory device
drives DQS low at the start of the preamble state. A dedicated circuit detects this transition. This signal is used to
control the polarity of the clock to the synchronizing registers.
2-33
Architecture
LatticeXP2 Family Data Sheet
DQSXFER
LA-LatticeXP2 devices provide a DQSXFER signal to the output buffer to assist it in data transfer to DDR memories
that require DQS strobe be shifted 90o. This shifted DQS strobe is generated by the DQSDEL block. The
DQSXFER signal runs the span of the data bus.
sysIO Buffer
Each I/O is associated with a • exible buffer referred to as a sysIO buffer. These buffers are arranged around the
periphery of the device in groups referred to as banks. The sysIO buffers allow users to implement the wide variety
of standards that are found in today’s systems including LVCMOS, SSTL, HSTL, LVDS and LVPECL.
sysIO Buffer Banks
LA-LatticeXP2 devices have eight sysIO buffer banks for user I/Os arranged two per side. Each bank is capable of
supporting multiple I/O standards. Each sysIO bank has its own I/O supply voltage (VCCIO). In addition, each bank
has voltage references, VREF1 and VREF2, that allow it to be completely independent from the others. Figure 2-32
shows the eight banks and their associated supplies.
In LA-LatticeXP2 devices, single-ended output buffers and ratioed input buffers (LVTTL, LVCMOS and PCI) are
powered using VCCIO. LVTTL, LVCMOS33, LVCMOS25 and LVCMOS12 can also be set as fixed threshold inputs
independent of VCCIO.
Each bank can support up to two separate VREF voltages, VREF1 and VREF2, that set the threshold for the referenced input buffers. Some dedicated I/O pins in a bank can be configured to be a reference voltage supply pin.
Each I/O is individually configurable based on the bank’s supply and reference voltages.
Figure 2-32. LA-LatticeXP2 Banks
TOP
GND
V
REF2(1)
Bank 1
V CCIO2
CCIO7
V REF2(7)
Bank 2
V REF1(7)
Bank 7
V
V
REF1(1)
V
CCIO1
GND
V
REF2(0)
V
REF1(0)
V
CCIO0
Bank 0
V REF1(2)
V REF2(2)
GND
GND
LEFT
RIGHT
V CCIO3
V REF1(6)
V REF1(3)
Bank 3
V REF2(6)
Bank 6
V CCIO6
V REF2(3)
GND
GND
BOTTOM
2-34
GND
V
REF2(4)
V
CCIO4
V
REF1(4)
Bank 4
GND
V
REF2(5)
V
CCIO5
VREF1(5)
Bank 5
Architecture
LatticeXP2 Family Data Sheet
LA-LatticeXP2 devices contain two types of sysIO buffer pairs.
1. Top and Bottom (Banks 0, 1, 4 and 5) sysIO Buffer Pairs (Single-Ended Outputs Only)
The sysIO buffer pairs in the top banks of the device consist of two single-ended output drivers and two sets of
single-ended input buffers (both ratioed and referenced). One of the referenced input buffers can also be configured as a differential input.
The two pads in the pair are described as “true” and “comp”, where the true pad is associated with the positive
side of the differential input buffer and the comp (complementary) pad is associated with the negative side of
the differential input buffer.
Only the I/Os on the top and bottom banks have programmable PCI clamps.
2. Left and Right (Banks 2, 3, 6 and 7) sysIO Buffer Pairs (50% Differential and 100% Single-Ended Outputs)
The sysIO buffer pairs in the left and right banks of the device consist of two single-ended output drivers, two
sets of single-ended input buffers (both ratioed and referenced) and one differential output driver. One of the referenced input buffers can also be configured as a differential input.
The two pads in the pair are described as “true” and “comp”, where the true pad is associated with the positive
side of the differential I/O, and the comp pad is associated with the negative side of the differential I/O.
LVDS differential output drivers are available on 50% of the buffer pairs on the left and right banks.
Typical sysIO I/O Behavior During Power-up
The internal power-on-reset (POR) signal is deactivated when VCC and VCCAUX have reached satisfactory levels.
After the POR signal is deactivated, the FPGA core logic becomes active. It is the user’s responsibility to ensure
that all other VCCIO banks are active with valid input logic levels to properly control the output logic states of all the
I/O banks that are critical to the application. During power up and before the FPGA core logic becomes active, all
user I/Os will be high-impedance with weak pull-up. Please refer to TN1136, LatticeXP2 sysIO Usage Guide for
additional information.
The VCC and VCCAUX supply the power to the FPGA core fabric, whereas the VCCIO supplies power to the I/O buffers. In order to simplify system design while providing consistent and predictable I/O behavior, it is recommended
that the I/O buffers be powered-up prior to the FPGA core fabric. VCCIO supplies should be powered-up before or
together with the VCC and VCCAUX supplies.
Supported sysIO Standards
The LA-LatticeXP2 sysIO buffer supports both single-ended and differential standards. Single-ended standards
can be further subdivided into LVCMOS, LVTTL and other standards. The buffers support the LVTTL, LVCMOS
1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V standards. In the LVCMOS and LVTTL modes, the buffer has individual configuration options for drive strength, bus maintenance (weak pull-up, weak pull-down, or a bus-keeper latch) and
open drain. Other single-ended standards supported include SSTL and HSTL. Differential standards supported
include LVDS, MLVDS, BLVDS, LVPECL, RSDS, differential SSTL and differential HSTL. Table 2-12 and Table 213 show the I/O standards (together with their supply and reference voltages) supported by LA-LatticeXP2
devices. For further information on utilizing the sysIO buffer to support a variety of standards, see TN1136,
LatticeXP2 sysIO Usage Guide.
2-35
Architecture
LatticeXP2 Family Data Sheet
Table 2-12. Supported Input Standards
VREF (Nom.)
VCCIO1 (Nom.)
LVTTL
—
—
LVCMOS33
—
—
LVCMOS25
—
—
LVCMOS18
—
1.8
LVCMOS15
—
1.5
Input Standard
Single Ended Interfaces
LVCMOS12
—
—
PCI33
—
—
HSTL18 Class I, II
0.9
—
HSTL15 Class I
0.75
—
SSTL33 Class I, II
1.5
—
SSTL25 Class I, II
1.25
—
SSTL18 Class I, II
0.9
—
Differential SSTL18 Class I, II
—
—
Differential SSTL25 Class I, II
—
—
Differential Interfaces
Differential SSTL33 Class I, II
—
—
Differential HSTL15 Class I
—
—
Differential HSTL18 Class I, II
—
—
LVDS, MLVDS, LVPECL, BLVDS, RSDS
—
—
1. When not specified, VCCIO can be set anywhere in the valid operating range (page 3-1).
2-36
Architecture
LatticeXP2 Family Data Sheet
Table 2-13. Supported Output Standards
Output Standard
Drive
VCCIO (Nom.)
4 mA, 8 mA, 12 mA, 16 mA, 20 mA
3.3
Single-ended Interfaces
LVTTL
LVCMOS33
4 mA, 8 mA, 12 mA 16 mA, 20 mA
3.3
LVCMOS25
4 mA, 8 mA, 12 mA, 16 mA, 20 mA
2.5
LVCMOS18
4 mA, 8 mA, 12 mA, 16 mA
1.8
LVCMOS15
4 mA, 8 mA
1.5
LVCMOS12
2 mA, 6 mA
1.2
LVCMOS33, Open Drain
4 mA, 8 mA, 12 mA 16 mA, 20 mA
—
LVCMOS25, Open Drain
4 mA, 8 mA, 12 mA 16 mA, 20 mA
—
LVCMOS18, Open Drain
4 mA, 8 mA, 12 mA 16 mA
—
LVCMOS15, Open Drain
4mA, 8mA
—
LVCMOS12, Open Drain
2mA, 6mA
—
PCI33
N/A
3.3
HSTL18 Class I, II
N/A
1.8
HSTL15 Class I
N/A
1.5
SSTL33 Class I, II
N/A
3.3
SSTL25 Class I, II
N/A
2.5
SSTL18 Class I, II
N/A
1.8
N/A
3.3
Differential Interfaces
Differential SSTL33, Class I, II
Differential SSTL25, Class I, II
N/A
2.5
Differential SSTL18, Class I, II
N/A
1.8
Differential HSTL18, Class I, II
N/A
1.8
Differential HSTL15, Class I
N/A
1.5
1, 2
LVDS
N/A
2.5
MLVDS1
N/A
2.5
1
BLVDS
N/A
2.5
LVPECL1
N/A
3.3
1
RSDS
LVCMOS33D1
N/A
2.5
4 mA, 8 mA, 12 mA, 16 mA, 20 mA
3.3
1. Emulated with external resistors. For more detail, see TN1138, LatticeXP2 High Speed I/O Interface.
2. On the left and right edges, LVDS outputs are supported with a dedicated differential output driver on 50% of the I/Os. This
solution does not require external resistors at the driver.
Hot Socketing
LA-LatticeXP2 devices have been carefully designed to ensure predictable behavior during power-up and powerdown. Power supplies can be sequenced in any order. During power-up and power-down sequences, the I/Os
remain in tri-state until the power supply voltage is high enough to ensure reliable operation. In addition, leakage
into I/O pins is controlled to within specified limits. This allows for easy integration with the rest of the system.
These capabilities make the LA-LatticeXP2 ideal for many multiple power supply and hot-swap applications.
IEEE 1149.1-Compliant Boundary Scan Testability
All LA-LatticeXP2 devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant Test
Access Port (TAP). This allows functional testing of the circuit board, on which the device is mounted, through a
serial scan path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to
2-37
Architecture
LatticeXP2 Family Data Sheet
be shifted in and loaded directly onto test nodes, or test data to be captured and shifted out for veri• cation. The test
access port consists of dedicated I/Os: TDI, TDO, TCK and TMS. The test access port has its own supply voltage
VCCJ and can operate with LVCMOS3.3, 2.5, 1.8, 1.5 and 1.2 standards. For more information, see TN1141,
LatticeXP2 sysCONFIG Usage Guide.
flexiFLASH Device Configuration
The LA-LatticeXP2 devices combine Flash and SRAM on a single chip to provide users with flexibility in device programming and configuration. Figure 2-33 provides an overview of the arrangement of Flash and SRAM configuration cells within the device. The remainder of this section provides an overview of these capabilities. See TN1141,
LatticeXP2 sysCONFIG Usage Guide for a more detailed description.
Figure 2-33. Overview of Flash and SRAM Configuration Cells Within LA-LatticeXP2 Devices
Massively Parallel
Data Transfer
Instant-ON
EBR Blocks
Flash Memory
Flash for
Single-Chip
Solution
SRAM
Configuration
Bits
FlashBAK
for EBR
Storage
EBR Blocks
TAG
Memory
Decryption
and Device
Lock
Device Lock
for Design
Security
SPI and JTAG
At power-up, or on user command, data is transferred from the on-chip Flash memory to the SRAM configuration
cells that control the operation of the device. This is done with massively parallel buses enabling the parts to operate within microseconds of the power supplies reaching valid levels; this capability is referred to as Instant-On.
The on-chip Flash enables a single-chip solution eliminating the need for external boot memory. This Flash can be
programmed through either the JTAG or Slave SPI ports of the device. The SRAM configuration space can also be
infinitely reconfigured through the JTAG and Master SPI ports. The JTAG port is IEEE 1149.1 and IEEE 1532 compliant.
As described in the EBR section of the data sheet, the FlashBAK capability of the parts enables the contents of the
EBR blocks to be written back into the Flash storage area without erasing or reprogramming other aspects of the
device configuration. Serial TAG memory is also available to allow the storage of small amounts of data such as
calibration coefficients and error codes.
For applications where security is important, the lack of an external bitstream provides a solution that is inherently
more secure than SRAM only FPGAs. This is further enhanced by device locking. The device can be in one of
three modes:
2-38
Architecture
LatticeXP2 Family Data Sheet
1. Unlocked
2. Key Locked – Presenting the key through the programming interface allows the device to be unlocked.
3. Permanently Locked – The device is permanently locked.
To further complement the security of the device a One Time Programmable (OTP) mode is available. Once the
device is set in this mode it is not possible to erase or re-program the Flash portion of the device.
Serial TAG Memory
LA-LatticeXP2 devices offer 0.6 to 3.3kbits of Flash memory in the form of Serial TAG memory. The TAG memory is
an area of the on-chip Flash that can be used for non-volatile storage including electronic ID codes, version codes,
date stamps, asset IDs and calibration settings. A block diagram of the TAG memory is shown in Figure 2-34. The
TAG memory is accessed in the same way as external SPI Flash and it can be read or programmed either through
JTAG, an external Slave SPI Port, or directly from FPGA logic. To read the TAG memory, a start address is specified and the entire TAG memory contents are read sequentially in a first-in-first-out manner. The TAG memory is
independent of the Flash used for device configuration and given its use for general-purpose storage functions is
always accessible regardless of the device security settings. For more information, see TN1137, LatticeXP2 Memory Usage Guide and TN1141, LatticeXP2 sysCONFIG Usage Guide.
Figure 2-34. Serial TAG Memory Diagram
External Slave
SPI Port
External Slave
SPI Port
TDI
JTAG
TDO
Data Shift Register
FPGA Logic
JTAG
FPGA Logic
Sequential
Address
Counter
Flash
Flash Memory Array
Live Update Technology
Many applications require field updates of the FPGA. LA-LatticeXP2 devices provide three features that enable this
configuration to be done in a secure and failsafe manner while minimizing impact on system operation.
1. Decryption Support
LA-LatticeXP2 devices provide on-chip, non-volatile key storage to support decryption of a 128-bit AES
encrypted bitstream, securing designs and deterring design piracy.
2. TransFR (Transparent Field Reconfiguration)
TransFR I/O (TFR) is a unique Lattice technology that allows users to update their logic in the field without
interrupting system operation using a single ispVM command. TransFR I/O allows I/O states to be frozen during device configuration. This allows the device to be field updated with a minimum of system disruption and
downtime. For more information please see TN1143, LatticeXP2 TransFR I/O.
3. Dual Boot Image Support
Dual boot images are supported for applications requiring reliable remote updates of configuration data for the
system FPGA. After the system is running with a basic configuration, a new boot image can be downloaded
remotely and stored in a separate location in the configuration storage device. Any time after the update the
LA-LatticeXP2 can be re-booted from this new configuration file. If there is a problem such as corrupt data during download or incorrect version number with this new boot image, the LA-LatticeXP2 device can revert back
2-39
Architecture
LatticeXP2 Family Data Sheet
to the original backup configuration and try again. This all can be done without power cycling the system. For
more information please see TN1220, LatticeXP2 Dual Boot Feature.
4. For more information on device configuration, see TN1141, LatticeXP2 sysCONFIG Usage Guide.
Soft Error Detect (SED) Support
LA-LatticeXP2 devices have dedicated logic to perform Cyclic Redundancy Code (CRC) checks. During configuration, the configuration data bitstream can be checked with the CRC logic block. In addition, LA-LatticeXP2 devices
can be programmed for checking soft errors in SRAM. SED can be run on a programmed device when the user
logic is not active. In the event a soft error occurs, the device can be programmed to either reload from a known
good boot image (from internal Flash or external SPI memory) or generate an error signal.
For further information on SED support, see TN1130, LatticeXP2 Soft Error Detection (SED) Usage Guide.
On-Chip Oscillator
Every LA-LatticeXP2 device has an internal CMOS oscillator that is used to derive a Master Clock (CCLK) for configuration. The oscillator and CCLK run continuously and are available to user logic after configuration is complete.
The available CCLK frequencies are listed in Table 2-14. When a different CCLK frequency is selected during the
design process, the following sequence takes place:
1. Device powers up with the default CCLK frequency.
2. During configuration, users select a different CCLK frequency.
3. CCLK frequency changes to the selected frequency after clock configuration bits are received.
This internal CMOS oscillator is available to the user by routing it as an input clock to the clock tree. For further
information on the use of this oscillator for configuration or user mode, see TN1141, LatticeXP2 sysCONFIG Usage
Guide.
Table 2-14. Selectable CCLKs and Oscillator Frequencies During Configuration and User Mode
CCLK/Oscillator (MHz)
2.51
3.12
4.3
5.4
6.9
8.1
9.2
10
13
15
20
26
32
40
54
803
1633
1. Software default oscillator frequency.
2. Software default CCLK frequency.
3. Frequency not valid for CCLK.
2-40
Architecture
LatticeXP2 Family Data Sheet
Density Shifting
The LA-LatticeXP2 family is designed to ensure that different density devices in the same family and in the same
package have the same pinout. Furthermore, the architecture ensures a high success rate when performing design
migration from lower density devices to higher density devices. In many cases, it is also possible to shift a lower utilization design targeted for a high-density device to a lower density device. However, the exact details of the final
resource utilization will impact the likely success in each case.
2-41
LA-LatticeXP2 Family Data Sheet
DC and Switching Characteristics
February 2015
Data Sheet DS1024
Absolute Maximum Ratings1, 2, 3
Supply Voltage VCC . . . . . . . . . . . . . . . . –0.5 V to 1.32 V
Supply Voltage VCCAUX . . . . . . . . . . . . . –0.5 V to 3.75 V
Supply Voltage VCCJ . . . . . . . . . . . . . . . –0.5 V to 3.75 V
Supply Voltage VCCPLL4 . . . . . . . . . . . . . –0.5 V to 3.75 V
Output Supply Voltage VCCIO . . . . . . . . –0.5 V to 3.75 V
Input or I/O Tristate Voltage Applied5 . . . –0.5 V to 3.75 V
Storage Temperature (Ambient) . . . . . . –65 °C to 150 °C
Junction Temperature Under Bias (Tj) . . . . . . . . . +125 °C
1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
2. Compliance with the Lattice Thermal Management document is required.
3. All voltages referenced to GND.
4. VCCPLL only available on csBGA, PQFP and TQFP packages.
5. Overshoot and undershoot of –2 V to (VIHMAX + 2) volts is permitted for a duration of 400 MHz
tOPJIT1
Output Clock Period Jitter
-5
0
5
%
—
—
±50
ps
100 MHz < fOUT < 400 MHz
—
—
±125
ps
fOUT < 100 MHz
—
—
0.025
UIPP
tSK
Input Clock to Output Clock Skew
N/M = integer
—
—
±240
ps
tOPW
Output Clock Pulse Width
At 90% or 10%
1
—
—
ns
tLOCK2
PLL Lock-in Time
tIPJIT
Input Clock Period Jitter
tFBKDLY
External Feedback Delay
tHI
Input Clock High Time
90% to 90%
tLO
Input Clock Low Time
10% to 10%
tR / tF
Input Clock Rise/Fall Time
10% to 90%
—
—
1
ns
tRSTKW
Reset Signal Pulse Width (RSTK)
10
—
—
ns
tRSTW
Reset Signal Pulse Width (RST)
500
—
—
ns
25 to 435MHz
—
—
50
µs
10 to 25MHz
—
—
100
µs
—
—
±200
ps
—
—
10
ns
0.5
—
—
ns
0.5
—
—
ns
1. Jitter sample is taken over 10,000 samples of the primary PLL output with clean reference clock.
2. Output clock is valid after tLOCK for PLL reset and dynamic delay adjustment.
3. Using LVDS output buffers.
4. Relative to CLKOP.
Timing v. A 0.12
3-25
DC and Switching Characteristics
LatticeXP2 Family Data Sheet
LA-LatticeXP2 sysCONFIG Port Timing Specifications
Over Recommended Operating Conditions
Parameter
Description
Min
Max
Units
50
ms
sysCONFIG POR, Initialization and Wake Up
tICFG
Minimum Vcc to INITN High
—
tVMC
Time from tICFG to valid Master CCLK
—
2
µs
tPRGMRJ
PROGRAMN Pin Pulse Rejection
—
12
ns
tPRGM
PROGRAMN Low Time to Start Con• guration
50
—
ns
tDINIT
PROGRAMN High to INITN High Delay
—
1
ms
tDPPINIT
Delay Time from PROGRAMN Low to INITN Low
—
50
ns
tDPPDONE
Delay Time from PROGRAMN Low to DONE Low
—
50
ns
tIODISS
User I/O Disable from PROGRAMN Low
—
35
ns
tIOENSS
User I/O Enabled Time from CCLK Edge During Wake-up Sequence
—
25
ns
tMWC
Additional Wake Master Clock Signals after DONE Pin High
0
—
cycles
sysCONFIG SPI Port (Master)
tCFGX
INITN High to CCLK Low
—
1
µs
tCSSPI
INITN High to CSSPIN Low
—
2
µs
tCSCCLK
CCLK Low before CSSPIN Low
0
—
ns
tSOCDO
CCLK Low to Output Valid
—
15
ns
tCSPID
CSSPIN[0:1] Low to First CCLK Edge Setup Time
2cyc
600+6cyc
ns
fMAXSPI
Max CCLK Frequency
—
20
MHz
tSUSPI
SOSPI Data Setup Time Before CCLK
7
—
ns
tHSPI
SOSPI Data Hold Time After CCLK
10
—
ns
25
MHz
mV/ns
sysCONFIG SPI Port (Slave)
fMAXSPIS
Slave CCLK Frequency
—
tRF
Rise and Fall Time
50
—
tSTCO
Falling Edge of CCLK to SOSPI Active
—
20
ns
tSTOZ
Falling Edge of CCLK to SOSPI Disable
—
20
ns
tSTSU
Data Setup Time (SISPI)
8
—
ns
tSTH
Data Hold Time (SISPI)
10
—
ns
tSTCKH
CCLK Clock Pulse Width, High
0.02
200
µs
tSTCKL
CCLK Clock Pulse Width, Low
0.02
200
µs
tSTVO
Falling Edge of CCLK to Valid SOSPI Output
—
20
ns
tSCS
CSSPISN High Time
25
—
ns
tSCSS
CSSPISN Setup Time
25
—
ns
tSCSH
CSSPISN Hold Time
25
—
ns
3-26
DC and Switching Characteristics
LatticeXP2 Family Data Sheet
On-Chip Oscillator and Configuration Master Clock Characteristics
Over Recommended Operating Conditions
Parameter
Master Clock Frequency
Duty Cycle
Min.
Max.
Units
Selected value –30%
Selected value +30%
MHz
40
60
%
Timing v. A 0.12
Figure 3-9. Master SPI Configuration Waveforms
Capture CR0
Capture CFGx
VCC
PROGRAMN
DONE
INITN
CSSPIN
0
1
2
3
…
7
8
9 10
… 31 32 33 34
… 127 128
CCLK
SISPI
Opcode
Address
Ignore
SOSPI
3-27
Valid Bitstream
DC and Switching Characteristics
LatticeXP2 Family Data Sheet
Flash Download Time (from On-Chip Flash to SRAM)
Over Recommended Operating Conditions
Symbol
Parameter
Min.
Typ.
Max.
Units
PROGRAMN Low-toHigh. Transition to Done LA-XP2-8
High.
LA-XP2-17
—
1.8
2.1
ms
—
1.9
2.3
ms
—
1.7
2.0
ms
Power-up refresh when
PROGRAMN is pulled
up to VCC
(VCC=VCC Min)
LA-XP2-5
—
1.8
2.1
ms
LA-XP2-8
—
1.9
2.3
ms
LA-XP2-17
—
1.7
2.0
ms
LA-XP2-5
tREFRESH
Flash Program Time
Over Recommended Operating Conditions
Program Time
Device
LA-XP2-5
LA-XP2-8
LA-XP2-17
Flash Density
1.2 M
2.0 M
3.6 M
TAG
Typ.
Units
1.0
ms
Main Array
1.1
s
TAG
1.0
ms
Main Array
1.4
s
TAG
1.0
ms
Main Array
1.8
s
Flash Erase Time
Over Recommended Operating Conditions
Erase Time
Device
LA-XP2-5
Flash Density
1.2 M
LA-XP2-8
2.0 M
LA-XP2-17
3.6 M
TAG
Typ.
Units
1.0
s
Main Array
3.0
s
TAG
1.0
s
Main Array
4.0
s
TAG
1.0
s
Main Array
5.0
s
FlashBAK Time (from EBR to Flash)
Over Recommended Operating Conditions
EBR Density (Bits)
Time (Typ.)
Units
LA-XP2-5
Device
166 K
1.5
s
LA-XP2-8
221 K
1.5
s
LA-XP2-17
276 K
1.5
s
3-28
DC and Switching Characteristics
LatticeXP2 Family Data Sheet
JTAG Port Timing Specifications
Over Recommended Operating Conditions
Symbol
Parameter
Min.
Max.
Units
—
25
MHz
TCK [BSCAN] clock pulse width
40
—
ns
TCK [BSCAN] clock pulse width high
20
—
ns
tBTCPL
TCK [BSCAN] clock pulse width low
20
—
ns
tBTS
TCK [BSCAN] setup time
8
—
ns
tBTH
TCK [BSCAN] hold time
10
—
ns
tBTRF
TCK [BSCAN] rise/fall time
50
—
mV/ns
tBTCO
TAP controller falling edge of clock to valid output
—
10
ns
tBTCODIS
TAP controller falling edge of clock to valid disable
—
10
ns
tBTCOEN
TAP controller falling edge of clock to valid enable
—
10
ns
tBTCRS
BSCAN test capture register setup time
8
—
ns
tBTCRH
BSCAN test capture register hold time
25
—
ns
tBUTCO
BSCAN test update register, falling edge of clock to valid output
—
25
ns
tBTUODIS
BSCAN test update register, falling edge of clock to valid disable
—
25
ns
tBTUPOEN
BSCAN test update register, falling edge of clock to valid enable
—
25
ns
fMAX
TCK Clock Frequency
tBTCP
tBTCPH
Timing v. A 0.12
Figure 3-10. JTAG Port Timing Waveforms
TMS
TDI
tBTS
tBTCPH
tBTH
tBTCP
tBTCPL
TCK
tBTCO
tBTCOEN
TDO
Valid Data
tBTCRS
Data to be
captured
from I/O
tBTCODIS
Valid Data
tBTCRH
Data Captured
tBTUPOEN
tBUTCO
Data to be
driven out
to I/O
Valid Data
3-29
tBTUODIS
Valid Data
DC and Switching Characteristics
LatticeXP2 Family Data Sheet
Switching Test Conditions
Figure 3-11 shows the output test load that is used for AC testing. The speci• c values for resistance, capacitance,
voltage, and other test conditions are shown in Table 3-6.
Figure 3-11. Output Test Load, LVTTL and LVCMOS Standards
VT
R1
DUT
Test Poi nt
CL*
*CL Includes Test Fixture and Probe Capacitance
Table 3-6. Test Fixture Required Components, Non-Terminated Interfaces
Test Condition
LVTTL and other LVCMOS settings (L -> H, H -> L)
R1
R2
CL
0pF
Timing Ref.
VT
LVCMOS 3.3 = 1.5 V
—
LVCMOS 2.5 = VCCIO/2
—
LVCMOS 1.8 = VCCIO/2
—
LVCMOS 1.5 = VCCIO/2
—
LVCMOS 1.2 = VCCIO/2
—
VCCIO/2
—
VCCIO/2
VCCIO
LVCMOS 2.5 I/O (Z -> H)
1M
LVCMOS 2.5 I/O (Z -> L)
1M
LVCMOS 2.5 I/O (H -> Z)
100
VOH – 0.10
—
LVCMOS 2.5 I/O (L -> Z)
100
VOL + 0.10
VCCIO
Note: Output test conditions for all other interfaces are determined by the respective standards.
3-30
LA-LatticeXP2 Family Data Sheet
Pinout Information
August 2014
Data Sheet DS1024
Signal Descriptions
Signal Name
I/O
Description
General Purpose
[Edge] indicates the edge of the device on which the pad is located. Valid
edge designations are L (Left), B (Bottom), R (Right), T (Top).
[Row/Column Number] indicates the PFU row or the column of the device on
which the PIC exists. When Edge is T (Top) or B (Bottom), only need to specify Row Number. When Edge is L (Left) or R (Right), only need to specify Column Number.
P[Edge] [Row/Column Number*]_[A/B]
I/O
[A/B] indicates the PIO within the PIC to which the pad is connected. Some of
these user-programmable pins are shared with special function pins. These
pins, when not used as special purpose pins, can be programmed as I/Os for
user logic. During configuration the user-programmable I/Os are tri-stated
with an internal pull-up resistor enabled. If any pin is not used (or not bonded
to a package pin), it is also tri-stated with an internal pull-up resistor enabled
after configuration.
GSRN
I
Global RESET signal (active low). Any I/O pin can be GSRN.
NC
—
No connect.
GND
—
Ground. Dedicated pins.
VCC
—
Power supply pins for core logic. Dedicated pins.
VCCAUX
—
Auxiliary power supply pin. This dedicated pin powers all the differential and
referenced input buffers.
VCCPLL
—
PLL supply pins. csBGA, PQFP and TQFP packages only.
VCCIOx
—
Dedicated power supply pins for I/O bank x.
VREF1_x, VREF2_x
—
Reference supply pins for I/O bank x. Pre-determined pins in each bank are
assigned as VREF inputs. When not used, they may be used as I/O pins.
PLL and Clock Functions (Used as user programmable I/O pins when not in use for PLL or clock pins)
[LOC][num]_VCCPLL
—
Power supply pin for PLL: LLC, LRC, URC, ULC, num = row from center.
[LOC][num]_GPLL[T, C]_IN_A
I
General Purpose PLL (GPLL) input pads: LLC, LRC, URC, ULC, num = row
from center, T = true and C = complement, index A,B,C...at each side.
[LOC][num]_GPLL[T, C]_FB_A
I
Optional feedback GPLL input pads: LLC, LRC, URC, ULC, num = row from
center, T = true and C = complement, index A,B,C...at each side.
PCLK[T, C]_[n:0]_[3:0]
I
Primary Clock pads, T = true and C = complement, n per side, indexed by
bank and 0,1,2,3 within bank.
[LOC]DQS[num]
I
DQS input pads: T (Top), R (Right), B (Bottom), L (Left), DQS, num = ball
function number. Any pad can be configured to be output.
TMS
I
Test Mode Select input, used to control the 1149.1 state machine. Pull-up is
enabled during configuration.
TCK
I
Test Clock input pin, used to clock the 1149.1 state machine. No pull-up
enabled.
I
Test Data in pin. Used to load data into device using 1149.1 state machine.
After power-up, this TAP port can be activated for configuration by sending
appropriate command. (Note: once a configuration port is selected it is
locked. Another configuration port cannot be selected until the power-up
sequence). Pull-up is enabled during configuration.
Test and Programming (Dedicated Pins)
TDI
© 2014 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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4-1
DS1024 Introduction_01.3
Pinout Information
LatticeXP2 Family Data Sheet
Signal Descriptions (Continued)
I/O
Description
TDO
Signal Name
O
Output pin. Test Data Out pin used to shift data out of a device using 1149.1.
VCCJ
—
Power supply pin for JTAG Test Access Port.
Configuration Pads (Used during sysCONFIG)
CFG[1:0]
INITN1
I
Mode pins used to specify configuration mode values latched on rising edge
of INITN. During configuration, an internal pull-up is enabled.
I/O
Open Drain pin. Indicates the FPGA is ready to be configured. During configuration, a pull-up is enabled.
I
Initiates configuration sequence when asserted low. This pin always has an
active pull-up.
DONE
I/O
Open Drain pin. Indicates that the configuration sequence is complete, and
the startup sequence is in progress.
CCLK
I/O
Configuration Clock for configuring an FPGA in sysCONFIG mode.
I/O
Input data pin in slave SPI mode and Output data pin in Master SPI mode.
I/O
Output data pin in slave SPI mode and Input data pin in Master SPI mode.
CSSPIN
O
Chip select for external SPI Flash memory in Master SPI mode. This pin has
a weak internal pull-up.
CSSPISN
I
Chip select in Slave SPI mode. This pin has a weak internal pull-up.
TOE
I
Test Output Enable tristates all I/O pins when driven low. This pin has a weak
internal pull-up, but when not used an external pull-up to VCC is recommended.
PROGRAMN
SISPI
2
SOSPI2
2
1. If not actively driven, the internal pull-up may not be sufficient. An external pull-up resistor of 4.7k to 10k ohms is recommended.
2. When using the device in Master SPI mode, it must be mutually exclusive from JTAG operations (i.e. TCK tied to GND) or the JTAG TCK
must be free-running when used in a system JTAG test environment. If Master SPI mode is used in conjunction with a JTAG download
cable, the device power cycle is required after the cable is unplugged.
1-2
Pinout Information
LatticeXP2 Family Data Sheet
PICs and DDR Data (DQ) Pins Associated with the DDR Strobe (DQS) Pin
PICs Associated with
DQS Strobe
PIO Within PIC
DDR Strobe (DQS) and
Data (DQ) Pins
For Left and Right Edges of the Device
P[Edge] [n-4]
P[Edge] [n-3]
P[Edge] [n-2]
P[Edge] [n-1]
P[Edge] [n]
P[Edge] [n+1]
P[Edge] [n+2]
P[Edge] [n+3]
A
DQ
B
DQ
A
DQ
B
DQ
A
DQ
B
DQ
A
DQ
B
DQ
A
[Edge]DQSn
B
DQ
A
DQ
B
DQ
A
DQ
B
DQ
A
DQ
B
DQ
For Top and Bottom Edges of the Device
P[Edge] [n-4]
P[Edge] [n-3]
P[Edge] [n-2]
P[Edge] [n-1]
P[Edge] [n]
P[Edge] [n+1]
P[Edge] [n+2]
P[Edge] [n+3]
P[Edge] [n+4]
A
DQ
B
DQ
A
DQ
B
DQ
A
DQ
B
DQ
A
DQ
B
DQ
A
[Edge]DQSn
B
DQ
A
DQ
B
DQ
A
DQ
B
DQ
A
DQ
B
DQ
A
DQ
B
DQ
Notes:
1. “n” is a row PIC number.
2. The DDR interface is designed for memories that support one DQS strobe up to 16 bits
of data for the left and right edges and up to 18 bits of data for the top and bottom
edges. In some packages, all the potential DDR data (DQ) pins may not be available.
PIC numbering definitions are provided in the “Signal Names” column of the Signal
Descriptions table.
1-3
Pinout Information
LatticeXP2 Family Data Sheet
Pin Information Summary
LA-XP2-5
132
144
csBGA TQFP
Pin Type
Single Ended User I/O
Differential Pair User I/O
Configuration
86
100
208
PQFP
LA-XP2-8
256
132
144
ftBGA csBGA TQFP
LA-XP2-17
208
PQFP
256
ftBGA
208
PQFP
256
ftBGA
146
172
86
100
146
201
146
201
Normal
35
39
57
66
35
39
57
77
57
77
Highspeed
8
11
16
20
8
11
16
23
16
23
TAP
5
5
5
5
5
5
5
5
5
5
Muxed
9
9
9
9
9
9
9
9
9
9
Dedicated
1
1
1
1
1
1
1
1
1
1
Muxed
5
5
7
7
7
7
9
9
11
11
Dedicated
1
1
1
1
1
1
1
1
1
1
Vcc
6
4
9
6
6
4
9
6
9
6
Vccaux
4
4
4
4
4
4
4
4
4
4
VCCPLL
2
2
2
-
2
2
2
-
4
-
Bank0
2
2
2
2
2
2
2
2
2
2
Bank1
1
1
2
2
1
1
2
2
2
2
Bank2
2
2
2
2
2
2
2
2
2
2
Bank3
1
1
2
2
1
1
2
2
2
2
Bank4
1
1
2
2
1
1
2
2
2
2
Bank5
2
2
2
2
2
2
2
2
2
2
Bank6
1
1
2
2
1
1
2
2
2
2
Non Configuration
VCCIO
2
2
2
2
2
2
2
2
2
2
GND, GND0-GND7
Bank7
15
15
20
20
15
15
22
20
22
20
NC
—
—
4
31
—
—
2
2
—
2
Bank0
18/9
20/10
20/10
26/13
18/9
20/10
20/10
28/14
20/10
28/14
Bank1
4/2
6/3
18/9
18/9
4/2
6/3
18/9
22/11
18/9
22/11
Bank2
16/8
18/9
18/9
22/11
16/8
18/9
18/9
26/13
18/9
26/13
Bank3
4/2
4/2
16/8
20/10
4/2
4/2
16/8
24/12
16/8
24/12
Bank4
8/4
8/4
18/9
18/9
8/4
8/4
18/9
26/13
18/9
26/13
Bank5
14/7
18/9
20/10
24/12
14/7
18/9
20/10
24/12
20/10
24/12
Single Ended/
Differential I/O per Bank
True LVDS Pairs
Bonding Out per Bank
Bank6
6/3
8/4
18/9
22/11
6/3
8/4
18/9
27/13
18/9
27/13
Bank7
16/8
18/9
18/9
22/11
16/8
18/9
18/9
24/12
18/9
24/12
Bank0
0
0
0
0
0
0
0
0
0
0
Bank1
0
0
0
0
0
0
0
0
0
0
Bank2
3
4
4
5
3
4
4
6
4
6
Bank3
1
1
4
5
1
1
4
6
4
6
Bank4
0
0
0
0
0
0
0
0
0
0
Bank5
0
0
0
0
0
0
0
0
0
0
Bank6
1
2
4
5
1
2
4
6
4
6
Bank7
3
4
4
5
3
4
4
5
4
5
1-4
Pinout Information
LatticeXP2 Family Data Sheet
Pin Information Summary (Continued)
LA-XP2-5
132
144
csBGA TQFP
Pin Type
208
PQFP
LA-XP2-8
256
132
144
ftBGA csBGA TQFP
LA-XP2-17
208
PQFP
256
ftBGA
208
PQFP
256
ftBGA
Bank0
1
1
1
1
1
1
1
1
1
1
Bank1
0
0
1
1
0
0
1
1
1
1
Bank2
1
1
1
1
1
1
1
1
1
1
DDR Banks Bonding Out Bank3
per I/O Bank1
Bank4
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
0
1
1
1
1
Bank5
1
1
1
1
1
1
1
1
1
1
Bank6
0
0
1
1
0
0
1
1
1
1
Bank7
1
1
1
1
1
1
1
1
1
1
Bank0
18
20
20
26
18
20
20
28
20
28
Bank1
4
6
18
18
4
6
18
22
18
22
Bank2
0
0
0
0
0
0
0
0
0
0
Bank3
0
0
0
0
0
0
0
0
0
0
PCI capable I/Os
Bonding Out per Bank
Bank4
8
8
18
18
8
8
18
26
18
26
Bank5
14
18
20
24
14
18
20
24
20
24
Bank6
0
0
0
0
0
0
0
0
0
0
Bank7
0
0
0
0
0
0
0
0
0
0
1. Minimum requirement to implement a fully functional 8-bit wide DDR bus. Available DDR interface consists of at least 12 I/Os
(1 DQS + 1 DQSB + 8 DQs + 1 DM + Bank VREF1).
Logic Signal Connections
Package pinout information can be found on the LatticeXP2 product pages on the Lattice website at www.latticesemi.com/products/fpga/xp2 and in the Lattice Diamond design software.
Thermal Management
Thermal management is recommended as part of any sound FPGA design methodology. To assess the thermal
characteristics of a system, Lattice specifies a maximum allowable junction temperature in all device data sheets.
Designers must complete a thermal analysis of their specific design to ensure that the device and package do not
exceed the junction temperature limits. Refer to the Thermal Management document to find the device/packagespecific thermal values.
For Further Information
• TN1139 - Power Estimation and Management for LatticeXP2 Devices
• Power Calculator tool included with Lattice Diamond design software or as a standalone download from
www.latticesemi.com/software
1-5
LA-LatticeXP2 Family Data Sheet
Ordering Information
August 2014
Data Sheet DS1024
Part Number Description
LAXP2 – XX E – 5 XXXXX X
Device Family
LA-XP2 Automotive FPGA
Grade
E = Automotive
Logic Capacity
5 = 5K LUTs
8 = 8K LUTs
17 = 17K LUTs
Package
MN132 = 132-ball Lead-Free csBGA
TN144 = 144-pin Lead-Free TQFP
QN208 = 208-pin Lead-Free PQFP
FTN256 = 256-ball Lead-Free ftBGA
Supply Voltage
E = 1.2V
Speed
Ordering Information
The LA-LatticeXP2 devices are marked with a single automotive temperature grade, as shown below.
XP2
LAXP2-17E
5FT256E
Datecode
Automotive Disclaimer
Products are not designed, intended or warranted to be fail-safe and are not designed, intended or warranted for
use in applications related to the deployment of airbags. Further, products are not intended to be used, designed or
warranted for use in applications that affect the control of the vehicle unless there is a fail-safe or redundancy feature and also a warning signal to the operator of the vehicle upon failure. Use of products in such applications is
fully at the risk of the customer, subject to applicable laws and regulations governing limitations on product liability.
© 2014 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
5-1
DS1024 Introduction_01.2
Ordering Information
LatticeXP2 Family Data Sheet
Lead-Free Packaging
Voltage
Grade
Package
Pins
Temp.
LUTs (k)
LAXP2-5E-5MN132E
Part Number
1.2V
-5
Lead-Free csBGA
132
AUTO
5
LAXP2-5E-5TN144E
1.2V
-5
Lead-Free TQFP
144
AUTO
5
LAXP2-5E-5QN208E
1.2V
-5
Lead-Free PQFP
208
AUTO
5
LAXP2-5E-5FTN256E
1.2V
-5
Lead-Free ftBGA
256
AUTO
5
Voltage
Grade
Package
Pins
Temp.
LUTs (k)
LAXP2-8E-5MN132E
Part Number
1.2V
-5
Lead-Free csBGA
132
AUTO
8
LAXP2-8E-5TN144E
1.2V
-5
Lead-Free TQFP
144
AUTO
8
LAXP2-8E-5QN208E
1.2V
-5
Lead-Free PQFP
208
AUTO
8
LAXP2-8E-5FTN256E
1.2V
-5
Lead-Free ftBGA
256
AUTO
8
Voltage
Grade
Package
Pins
Temp.
LUTs (k)
Part Number
LAXP2-17E-5QN208E
1.2V
-5
Lead-Free PQFP
208
AUTO
17
LAXP2-17E-5FTN256E
1.2V
-5
Lead-Free ftBGA
256
AUTO
17
5-2
LA-LatticeXP2 Family Data Sheet
Supplemental Information
August 2014
Data Sheet DS1024
For Further Information
A variety of technical notes for the LA-LatticeXP2 FPGA family are available on the Lattice website.
• TN1136, LatticeXP2 sysIO Usage Guide
• TN1137, LatticeXP2 Memory Usage Guide
• TN1138, LatticeXP2 High Speed I/O Interface
• TN1126, LatticeXP2 sysCLOCK PLL Design and Usage Guide
• TN1139, Power Estimation and Management for LatticeXP2 Devices
• TN1140, LatticeXP2 sysDSP Usage Guide
• TN1141, LatticeXP2 sysCONFIG Usage Guide
• TN1142, LatticeXP2 Configuration Encryption and Security Usage Guide
• TN1143, LatticeXP2 TransFR I/O
• TN1087, Minimizing System Interruption During Configuration Using TransFR Technology
• TN1220, LatticeXP2 Dual Boot Feature
• TN1130, LatticeXP2 Soft Error Detection (SED) Usage Guide
For further information on interface standards refer to the following web sites:
• JEDEC Standards (LVTTL, LVCMOS, SSTL, HSTL): www.jedec.org
• PCI: www.pcisig.com
© 2014 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
6-1
DS1024 Introduction_01.1
LA-LatticeXP2 Family Data Sheet
Revision History
February 2015
Data Sheet DS1024
Revision History
Date
Version
Section
February 2015
1.5
Multiple
August 2014
1.4
All
Architecture
January 2012
01.3
01.2
Multiple
Updated for Lattice Diamond design software.
Corrected information regarding SED support.
Introduction
Pinout Information
Ordering Information
August 2008
01.1
Updated for Lattice corporate logo.
Updated Typical sysIO I/O Behavior During Power-up section.
Described user I/Os during power up and before FPGA core logic is
active.
Architecture
DC and Switching
Characteristics
May 2009
Change Summary
Corrected formatting; fixed page, table and figure numbers.
—
Added reference to ESD Performance Qualification Summary information.
Added support for 132 csBGA to Features list and Family Selection
Guide table.
Added support for 132 csBGA to Pin Information Summary table.
Added support for 132 csBGA to Part Number Description diagram and
Ordering Information tables.
Data sheet status changed from preliminary to final.
Architecture
Clarification of the operation of the secondary clock regions.
DC and Switching
Characteristics
Updated Typical Building Block Function Performance table.
Updated External Switching Characteristics table.
Updated Internal Switching Characteristics table.
Updated Family Timing Adders table.
June 2008
01.0
—
Initial release.
© 2015 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
7-1
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