LC4032C

ispMACH 4000V/B/C/Z Family July 2003 Industry’s Lowest Power CP LDs! ispMACH 4000Z TM NEW! 3.3V/2.5V/1.8V In-System Programmable SuperFAST TM High Density PLDs Data Sheet Features ■ High Performance • fMAX = 400MHz maximum operating frequency • tPD = 2.5ns propagation delay • Up to four global clock pins with programmable clock polarity control • Up to 80 PTs per output ■ Broad Device Offering • Multiple temperature range support – Commercial: 0 to 90°C junction (Tj) – Industrial: -40 to 105°C junction (Tj) – Automotive: -40 to 130°C junction (Tj) ■ Easy System Integration • Operation with 3.3V, 2.5V or 1.8V LVCMOS I/O • Operation with 3.3V (4000V), 2.5V (4000B) or 1.8V (4000C/Z) supplies • 5V tolerant I/O for LVCMOS 3.3, LVTTL, and PCI interfaces • Hot-socketing • Open-drain capability • Input pull-up, pull-down or bus-keeper • Programmable output slew rate • 3.3V PCI compatible • IEEE 1149.1 boundary scan testable • 3.3V/2.5V/1.8V In-System Programmable (ISP™) using IEEE 1532 compliant interface • I/O pins with fast setup path ■ Ease of Design • Enhanced macrocells with individual clock, reset, preset and clock enable controls • Up to four global OE controls • Individual local OE control per I/O pin • Excellent First-Time-FitTM and refit • Fast path, SpeedLockingTM Path, and wide-PT path • Wide input gating (36 input logic blocks) for fast counters, state machines and address decoders ■ Zero Power (ispMACH 4000Z) and Low Power (ispMACH 4000V/B/C) • Typical static current 10µA (4032Z) • Typical static current 1.8mA (4000C) • 1.8V core low dynamic power Table 1. ispMACH 4000V/B/C Family Selection Guide ispMACH 4032V/B/C Macrocells User I/O Options tPD (ns) tS (ns) tCO (ns) fMAX (MHz) Supply Voltages (V) Pins/Package 32 30/32 2.5 1.8 2.2 400 3.3/2.5/1.8V 44 TQFP 48 TQFP ispMACH 4064V/B/C 64 30/32/64 2.5 1.8 2.2 400 3.3/2.5/1.8V 44 TQFP 48 TQFP 100 TQFP ispMACH 4128V/B/C 128 64/92/96 2.7 1.8 2.7 333 3.3/2.5/1.8V ispMACH 4256V/B/C 256 64/96/128/160 3.0 2.0 2.7 322 3.3/2.5/1.8V ispMACH 4384V/B/C 384 128/192 3.5 2.0 2.7 322 3.3/2.5/1.8V ispMACH 4512V/B/C 512 128/208 3.5 2.0 2.7 322 3.3/2.5/1.8V 100 TQFP 128 TQFP 144 TQFP1 100 TQFP 144 TQFP1 176 TQFP 256 fpBGA2 176 TQFP 256 fpBGA 176 TQFP 256 fpBGA 1. 3.3V (4000V) only. 2. 128-I/O and 160-I/O configurations. Note: ispMACH 4032Z information is preliminary. ispMACH 4064Z/4128Z information is advance. © 2003 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1 ispm4k_15z Lattice Semiconductor Table 2. ispMACH 4000Z Family Selection Guide ispMACH 4032ZC1 Macrocells User I/O Options tPD (ns) tS (ns) tCO (ns) fMAX (MHz) Supply Voltage (V) Standby Icc (µA) Pins/Package 32 32 3.5 2.2 3.0 267 1.8 20 48 TQFP 56 csBGA ispMACH 4000V/B/C/Z Family Data Sheet ispMACH 4064ZC2 64 32/64 4.0 2.8 3.3 250 1.8 25 48 TQFP 56 csBGA 100 TQFP 132 csBGA ispMACH 4128ZC2 128 64/96 4.5 2.9 3.9 220 1.8 30 ispMACH 4256ZC2 256 64/96/128 5.0 3.0 3.9 200 1.8 40 100 TQFP 132csBGA 100 TQFP 132 csBGA 176 TQFP 1. Preliminary information. 2. Advance information. ispMACH 4000 Introduction The high performance ispMACH 4000 family from Lattice offers a SuperFAST CPLD solution. The family is a blend of Lattice’s two most popular architectures: the ispLSI® 2000 and ispMACH 4A. Retaining the best of both families, the ispMACH 4000 architecture focuses on significant innovations to combine the highest performance with low power in a flexible CPLD family. The ispMACH 4000 combines high speed and low power with the flexibility needed for ease of design. With its robust Global Routing Pool and Output Routing Pool, this family delivers excellent First-Time-Fit, timing predictability, routing, pin-out retention and density migration. The ispMACH 4000 family offers densities ranging from 32 to 512 macrocells. There are multiple density-I/O combinations in Thin Quad Flat Pack (TQFP) and Fine Pitch BGA (fpBGA) packages ranging from 44 to 256 pins/balls. Table 1 shows the macrocell, package and I/O options, along with other key parameters. The ispMACH 4000 family has enhanced system integration capabilities. It supports 3.3V (4000V), 2.5V (4000B) and 1.8V (4000C/Z) supply voltages and 3.3V, 2.5V and 1.8V interface voltages. Additionally, inputs can be safely driven up to 5.5V when an I/O bank is configured for 3.3V operation, making this family 5V tolerant. The ispMACH 4000 also offers enhanced I/O features such as slew rate control, PCI compatibility, bus-keeper latches, pull-up resistors, pull-down resistors, open drain outputs and hot socketing. The ispMACH 4000 family members are 3.3V/ 2.5V/1.8V in-system programmable through the IEEE Standard 1532 interface. IEEE Standard 1149.1 boundary scan testing capability also allows product testing on automated test equipment. Overview The ispMACH 4000 devices consist of multiple 36-input, 16-macrocell Generic Logic Blocks (GLBs) interconnected by a Global Routing Pool (GRP). Output Routing Pools (ORPs) connect the GLBs to the I/O Blocks (IOBs), which contain multiple I/O cells. This architecture is shown in Figure 1. 2 Lattice Semiconductor Figure 1. Functional Block Diagram CLK0/I CLK1/I CLK2/I CLK3/I VCCO0 GND ispMACH 4000V/B/C/Z Family Data Sheet I/O Block ORP I/O Bank 0 16 Global Routing Pool Generic Logic Block 16 36 16 36 Generic 16 Logic Block I/O Block ORP I/O Bank 1 I/O Block ORP 16 Generic Logic Block 16 36 16 36 Generic 16 Logic Block I/O Block ORP The I/Os in the ispMACH 4000 are split into two banks. Each bank has a separate I/O power supply. Inputs can support a variety of standards independent of the chip or bank power supply. Outputs support the standards compatible with the power supply provided to the bank. Support for a variety of standards helps designers implement designs in mixed voltage environments. In addition, 5V tolerant inputs are specified within an I/O bank that is connected to VCCO of 3.0V to 3.6V for LVCMOS 3.3, LVTTL and PCI interfaces. ispMACH 4000 Architecture There are a total of two GLBs in the ispMACH 4032, increasing to 32 GLBs in the ispMACH 4512. Each GLB has 36 inputs. All GLB inputs come from the GRP and all outputs from the GLB are brought back into the GRP to be connected to the inputs of any other GLB on the device. Even if feedback signals return to the same GLB, they still must go through the GRP. This mechanism ensures that GLBs communicate with each other with consistent and predictable delays. The outputs from the GLB are also sent to the ORP. The ORP then sends them to the associated I/O cells in the I/O block. Generic Logic Block The ispMACH 4000 GLB consists of a programmable AND array, logic allocator, 16 macrocells and a GLB clock generator. Macrocells are decoupled from the product terms through the logic allocator and the I/O pins are decoupled from macrocells through the ORP. Figure 2 illustrates the GLB. 3 VCCO1 GND GOE0 GOE1 VCC GND TCK TMS TDI TDO Lattice Semiconductor Figure 2. Generic Logic Block CLK0 CLK1 CLK2 CLK3 ispMACH 4000V/B/C/Z Family Data Sheet To GRP Clock Generator 1+OE 16 MC Feedback Signals 1+OE 1+OE 1+OE 1+OE 1+OE 1+OE 1+OE To ORP To Product Term Output Enable Sharing Logic Allocator 36 Inputs from GRP AND Array The programmable AND Array consists of 36 inputs and 83 output product terms. The 36 inputs from the GRP are used to form 72 lines in the AND Array (true and complement of the inputs). Each line in the array can be connected to any of the 83 output product terms via a wired-AND. Each of the 80 logic product terms feed the logic allocator with the remaining three control product terms feeding the Shared PT Clock, Shared PT Initialization and Shared PT OE. The Shared PT Clock and Shared PT Initialization signals can optionally be inverted before being fed to the macrocells. Every set of five product terms from the 80 logic product terms forms a product term cluster starting with PT0. There is one product term cluster for every macrocell in the GLB. Figure 3 is a graphical representation of the AND Array. AND Array 36 Inputs, 83 Product Terms 4 16 Macrocells Lattice Semiconductor Figure 3. AND Array In[0] In[34] In[35] ispMACH 4000V/B/C/Z Family Data Sheet PT0 PT1 PT2 PT3 PT4 Cluster 0 PT75 PT76 PT77 Cluster 15 PT78 PT79 PT80 Shared PT Clock PT81 Shared PT Initialization PT82 Shared PTOE Note: Indicates programmable fuse. Enhanced Logic Allocator Within the logic allocator, product terms are allocated to macrocells in product term clusters. Each product term cluster is associated with a macrocell. The cluster size for the ispMACH 4000 family is 4+1 (total 5) product terms. The software automatically considers the availability and distribution of product term clusters as it fits the functions within a GLB. The logic allocator is designed to provide three speed paths: 5-PT fast bypass path, 20-PT Speed Locking path and an up to 80-PT path. The availability of these three paths lets designers trade timing variability for increased performance. The enhanced Logic Allocator of the ispMACH 4000 family consists of the following blocks: • Product Term Allocator • Cluster Allocator • Wide Steering Logic Figure 4 shows a macrocell slice of the Logic Allocator. There are 16 such slices in the GLB. Figure 4. Macrocell Slice to to n-1 n-2 from from n-1 n-4 Fast 5-PT Path 1-80 PTs To XOR (MC) From n-4 n 5-PT Cluster to n+1 Individual Product Term Allocator from n+2 Cluster Allocator from n+1 To n+4 SuperWIDE™ Steering Logic 5 Lattice Semiconductor Product Term Allocator ispMACH 4000V/B/C/Z Family Data Sheet The product term allocator assigns product terms from a cluster to either logic or control applications as required by the design being implemented. Product terms that are used as logic are steered into a 5-input OR gate associated with the cluster. Product terms that used for control are steered either to the macrocell or I/O cell associated with the cluster. Table 3 shows the available functions for each of the five product terms in the cluster. The OR gate output connects to the associated I/O cell, providing a fast path for narrow combinatorial functions, and to the logic allocator. Table 3. Individual PT Steering Product Term PTn PTn+1 PTn+2 PTn+3 PTn+4 Logic Logic PT Logic PT Logic PT Logic PT Logic PT Single PT for XOR/OR Individual Clock (PT Clock) Individual Initialization or Individual Clock Enable (PT Initialization/CE) Individual Initialization (PT Initialization) Individual OE (PTOE) Control Cluster Allocator The cluster allocator allows clusters to be steered to neighboring macrocells, thus allowing the creation of functions with more product terms. Table 4 shows which clusters can be steered to which macrocells. Used in this manner, the cluster allocator can be used to form functions of up to 20 product terms. Additionally, the cluster allocator accepts inputs from the wide steering logic. Using these inputs, functions up to 80 product terms can be created. Table 4. Available Clusters for Each Macrocell Macrocell M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 — C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 Available Clusters C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 — C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 — — Wide Steering Logic The wide steering logic allows the output of the cluster allocator n to be connected to the input of the cluster allocator n+4. Thus, cluster chains can be formed with up to 80 product terms, supporting wide product term functions and allowing performance to be increased through a single GLB implementation. Table 5 shows the product term chains. 6 Lattice Semiconductor Table 5. Product Term Expansion Capability Expansion Chains Chain-0 Chain-1 Chain-2 Chain-3 ispMACH 4000V/B/C/Z Family Data Sheet Macrocells Associated with Expansion Chain (with Wrap Around) M0 → M4 → M8 → M12 → M0 M1 → M5 → M9 → M13 → M1 M2 → M6 → M10 → M14 → M2 M3 → M7 → M11 → M15 → M3 Max PT/ Macrocell 75 80 75 70 Every time the super cluster allocator is used, there is an incremental delay of tEXP . When the super cluster allocator is used, all destinations other than the one being steered to, are given the value of ground (i.e., if the super cluster is steered to M (n+4), then M (n) is ground). Macrocell The 16 macrocells in the GLB are driven by the 16 outputs from the logic allocator. Each macrocell contains a programmable XOR gate, a programmable register/latch, along with routing for the logic and control functions. Figure 5 shows a graphical representation of the macrocell. The macrocells feed the ORP and GRP. A direct input from the I/O cell allows designers to use the macrocell to construct high-speed input registers. A programmable delay in this path allows designers to choose between the fastest possible set-up time and zero hold time. Figure 5. Macrocell Power-up Initialization Shared PT Initialization PT Initialization (optional) PT Initialization/CE (optional) Delay From I/O Cell From Logic Allocator R D/T/L P Q To ORP To GRP CE Single PT Block CLK0 Block CLK1 Block CLK2 Block CLK3 PT Clock (optional) Shared PT Clock Enhanced Clock Multiplexer The clock input to the flip-flop can select any of the four block clocks along with the shared PT clock, and true and complement forms of the optional individual term clock. An 8:1 multiplexer structure is used to select the clock. The eight sources for the clock multiplexer are as follows: • Block CLK0 • Block CLK1 7 Lattice Semiconductor • • • • • • Block CLK2 Block CLK3 PT Clock PT Clock Inverted Shared PT Clock Ground ispMACH 4000V/B/C/Z Family Data Sheet Clock Enable Multiplexer Each macrocell has a 4:1 clock enable multiplexer. This allows the clock enable signal to be selected from the following four sources: • PT Initialization/CE • PT Initialization/CE Inverted • Shared PT Clock • Logic High Initialization Control The ispMACH 4000 family architecture accommodates both block-level and macrocell-level set and reset capability. There is one block-level initialization term that is distributed to all macrocell registers in a GLB. At the macrocell level, two product terms can be “stolen” from the cluster associated with a macrocell to be used for set/reset functionality. A reset/preset swapping feature in each macrocell allows for reset and preset to be exchanged, providing flexibility. Note that the reset/preset swapping selection feature affects power-up reset as well. All flip-flops power up to a known state for predictable system initialization. If a macrocell is configured to SET on a signal from the block-level initialization, then that macrocell will be SET during device power-up. If a macrocell is configured to RESET on a signal from the block-level initialization or is not configured for set/reset, then that macrocell will RESET on powerup. To guarantee initialization values, the VCC rise must be monotonic, and the clock must be inactive until the reset delay time has elapsed. GLB Clock Generator Each ispMACH 4000 device has up to four clock pins that are also routed to the GRP to be used as inputs. These pins drive a clock generator in each GLB, as shown in Figure 6. The clock generator provides four clock signals that can be used anywhere in the GLB. These four GLB clock signals can consist of a number of combinations of the true and complement edges of the global clock signals. Figure 6. GLB Clock Generator CLK0 Block CLK0 CLK1 Block CLK1 CLK2 Block CLK2 CLK3 Block CLK3 8 Lattice Semiconductor Output Routing Pool (ORP) ispMACH 4000V/B/C/Z Family Data Sheet The Output Routing Pool allows macrocell outputs to be connected to any of several I/O cells within an I/O block. This provides greater flexibility in determining the pinout and allows design changes to occur without affecting the pinout. The output routing pool also provides a parallel capability for routing macrocell-level OE product terms. This allows the OE product term to follow the macrocell output as it is switched between I/O cells. Additionally, the output routing pool allows the macrocell output or true and complement forms of the 5-PT bypass signal to bypass the output routing multipliers and feed the I/O cell directly. The enhanced ORP of the ispMACH 4000 family consists of the following elements: • Output Routing Multiplexers • OE Routing Multiplexers • Output Routing Pool Bypass Multiplexers Figure 7 shows the structure of the ORP from the I/O cell perspective. This is referred to as an ORP slice. Each ORP has as many ORP slices as there are I/O cells in the corresponding I/O block. Figure 7. ORP Slice OE Routing Multiplexer From PTOE To I/O Cell OE 5-PT Fast Path From Macrocell ORP Bypass Multiplexer To I/O Cell Output Output Routing Multiplexer Output Routing Multiplexers The details of connections between the macrocells and the I/O cells vary across devices and within a device dependent on the maximum number of I/Os available. Tables 5-9 provide the connection details. Table 6. ORP Combinations for I/O Blocks with 8 I/Os I/O Cell I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 M0, M1, M2, M3, M4, M5, M6, M7 M2, M3, M4, M5, M6, M7, M8, M9 M4, M5, M6, M7, M8, M9, M10, M11 M6, M7, M8, M9, M10, M11, M12, M13 M8, M9, M10, M11, M12, M13, M14, M15 M10, M11, M12, M13, M14, M15, M0, M1 M12, M13, M14, M15, M0, M1, M2, M3 M14, M15, M0, M1, M2, M3, M4, M5 Available Macrocells 9 Lattice Semiconductor Table 7. ORP Combinations for I/O Blocks with 16 I/Os I/O Cell I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 M0, M1, M2, M3, M4, M5, M6, M7 M1, M2, M3, M4, M5, M6, M7, M8 M2, M3, M4, M5, M6, M7, M8, M9 M3, M4, M5, M6, M7, M8, M9, M10 M4, M5, M6, M7, M8, M9, M10, M11 M5, M6, M7, M8, M9, M10, M11, M12 M6, M7, M8, M9, M10, M11, M12, M13 M7, M8, M9, M10, M11, M12, M13, M14 M8, M9, M10, M11, M12, M13, M14, M15 M9, M10, M11, M12, M13, M14, M15, M0 M10, M11, M12, M13, M14, M15, M0, M1 M11, M12, M13, M14, M15, M0, M1, M2 M12, M13, M14, M15, M0, M1, M2, M3 M13, M14, M15, M0, M1, M2, M3, M4 M14, M15, M0, M1, M2, M3, M4, M5 M15, M0, M1, M2, M3, M4, M5, M6 ispMACH 4000V/B/C/Z Family Data Sheet Available Macrocells Table 8. ORP Combinations for I/O Blocks with 4 I/Os I/O Cell I/O 0 I/O 1 I/O 2 I/O 3 M0, M1, M2, M3, M4, M5, M6, M7 M4, M5, M6, M7, M8, M9, M10, M11 M8, M9, M10, M11, M12, M13, M14, M15 M12, M13, M14, M15, M0, M1, M2, M3 Available Macrocells Table 9. ORP Combinations for I/O Blocks with 10 I/Os I/O Cell I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 M0, M1, M2, M3, M4, M5, M6, M7 M2, M3, M4, M5, M6, M7, M8, M9 M4, M5, M6, M7, M8, M9, M10, M11 M6, M7, M8, M9, M10, M11, M12, M13 M8, M9, M10, M11, M12, M13, M14, M15 M10, M11, M12, M13, M14, M15, M0, M1 M12, M13, M14, M15, M0, M1, M2, M3 M14, M15, M0, M1, M2, M3, M4, M5 M2, M3, M4, M5, M6, M7, M8, M9 M10, M11, M12, M13, M14, M15, M0, M1 Available Macrocells 10 Lattice Semiconductor Table 10. ORP Combinations for I/O Blocks with 12 I/Os I/O Cell I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 M0, M1, M2, M3, M4, M5, M6, M7 M1, M2, M3, M4, M5, M6, M7, M8 M2, M3, M4, M5, M6, M7, M8, M9 M4, M5, M6, M7, M8, M9, M10, M11 M5, M6, M7, M8, M9, M10, M11, M12 M6, M7, M8, M9, M10, M11, M12, M13 M8, M9, M10, M11, M12, M13, M14, M15 M9, M10, M11, M12, M13, M14, M15, M0 M10, M11, M12, M13, M14, M15, M0, M1 M12, M13, M14, M15, M0, M1, M2, M3 M13, M14, M15, M0, M1, M2, M3, M4 M14, M15, M0, M1, M2, M3, M4, M5 ispMACH 4000V/B/C/Z Family Data Sheet Available Macrocells ORP Bypass and Fast Output Multiplexers The ORP bypass and fast-path output multiplexer is a 4:1 multiplexer and allows the 5-PT fast path to bypass the ORP and be connected directly to the pin with either the regular output or the inverted output. This multiplexer also allows the register output to bypass the ORP to achieve faster tCO. Output Enable Routing Multiplexers The OE Routing Pool provides the corresponding local output enable (OE) product term to the I/O cell. I/O Cell The I/O cell contains the following programmable elements: output buffer, input buffer, OE multiplexer and bus maintenance circuitry. Figure 8 details the I/O cell. Figure 8. I/O Cell GOE 0 GOE 1 GOE 2 GOE 3 From ORP VCC VCCO VCCO From ORP To Macrocell To GRP *Global fuses * * * Each output supports a variety of output standards dependent on the VCCO supplied to its I/O bank. Outputs can also be configured for open drain operation. Each input can be programmed to support a variety of standards, independent of the VCCO supplied to its I/O bank. The I/O standards supported are: 11 Lattice Semiconductor • LVTTL • LVCMOS 3.3 • LVCMOS 2.5 • LVCMOS 1.8 • 3.3V PCI Compatible ispMACH 4000V/B/C/Z Family Data Sheet All of the I/Os and dedicated inputs have the capability to provide a bus-keeper latch, Pull-up Resistor or Pull-down Resistor. A fourth option is to provide none of these. The selection is done on a global basis. The default in both hardware and software is such that when the device is erased or if the user does not specify, the input structure is configured to be a Pull-up Resistor. Each ispMACH 4000 device I/O has an individually programmable output slew rate control bit. Each output can be individually configured for the higher speed transition (~3V/ns) or for the lower noise transition (~1V/ns). For highspeed designs with long, unterminated traces, the slow-slew rate will introduce fewer reflections, less noise and keep ground bounce to a minimum. For designs with short traces or well terminated lines, the fast slew rate can be used to achieve the highest speed. The slew rate is adjusted independent of power. Global OE Generation Most ispMACH 4000 family devices have a 4-bit wide Global OE Bus, except the ispMACH 4032 device that has a 2-bit wide Global OE Bus. This bus is derived from a 4-bit internal global OE PT bus and two dual purpose I/O or GOE pins. Each signal that drives the bus can optionally be inverted. Each GLB has a block-level OE PT that connects to all bits of the Global OE PT bus with four fuses. Hence, for a 256-macrocell device (with 16 blocks), each line of the bus is driven from 16 OE product terms. Figures 9 and 10 show a graphical representation of the global OE generation. Figure 9. Global OE Generation for All Devices Except ispMACH 4032 Internal Global OE PT Bus (4 lines) Global OE 4-Bit Global OE Bus Shared PTOE (Block 0) Shared PTOE (Block n) Global Fuses Fuse connection Hard wired GOE (0:3) to I/O cells 12 Lattice Semiconductor Figure 10. Global OE Generation for ispMACH 4032 Internal Global OE PT Bus (2 lines) ispMACH 4000V/B/C/Z Family Data Sheet Global OE 4-Bit Global OE Bus Shared PTOE (Block 0) Shared PTOE (Block 1) Global Fuses Fuse connection Hard wired GOE (3:0) to I/O cells Zero Power/Low Power and Power Management The ispMACH 4000 family is designed with high speed low power design techniques to offer both high speed and low power. With an advanced E2 low power cell and non sense-amplifier design approach (full CMOS logic approach), the ispMACH 4000 family offers SuperFAST pin-to-pin speeds, while simultaneously delivering low standby power without needing any “turbo bits” or other power management schemes associated with a traditional sense-amplifier approach. The zero power ispMACH 4000Z is based on the 1.8V ispMACH 4000C family. With innovative circuit design changes, the ispMACH 4000Z family is able to achieve the industry’s “lowest static power”. IEEE 1149.1-Compliant Boundary Scan Testability All ispMACH 4000 devices have boundary scan cells and are compliant to the IEEE 1149.1 standard. This allows functional testing of the circuit board on which the device is mounted through a serial scan path that can access all critical logic notes. Internal registers are linked internally, allowing test data to be shifted in and loaded directly onto test nodes, or test node data to be captured and shifted out for verification. In addition, these devices can be linked into a board-level serial scan path for more board-level testing. The test access port operates with an LVCMOS interface that corresponds to the power supply voltage. I/O Quick Configuration To facilitate the most efficient board test, the physical nature of the I/O cells must be set before running any continuity tests. As these tests are fast, by nature, the overhead and time that is required for configuration of the I/Os’ physical nature should be minimal so that board test time is minimized. The ispMACH 4000 family of devices allows this by offering the user the ability to quickly configure the physical nature of the I/O cells. This quick configuration takes milliseconds to complete, whereas it takes seconds for the entire device to be programmed. Lattice's ispVM™ System programming software can either perform the quick configuration through the PC parallel port, or can generate the ATE or test vectors necessary for a third-party test system. 13 Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet IEEE 1532-Compliant In-System Programming Programming devices in-system provides a number of significant benefits including: rapid prototyping, lower inventory levels, higher quality and the ability to make in-field modifications. All ispMACH 4000 devices provide In-System Programming (ISP™) capability through the Boundary Scan Test Access Port. This capability has been implemented in a manner that ensures that the port remains complaint to the IEEE 1149.1 standard. By using IEEE 1149.1 as the communication interface through which ISP is achieved, users get the benefit of a standard, welldefined interface. All ispMACH 4000 devices are also compliant with the IEEE 1532 standard. The ispMACH 4000 devices can be programmed across the commercial temperature and voltage range. The PCbased Lattice software facilitates in-system programming of ispMACH 4000 devices. The software takes the JEDEC file output produced by the design implementation software, along with information about the scan chain, and creates a set of vectors used to drive the scan chain. The software can use these vectors to drive a scan chain via the parallel port of a PC. Alternatively, the software can output files in formats understood by common automated test equipment. This equipment can then be used to program ispMACH 4000 devices during the testing of a circuit board. Security Bit A programmable security bit is provided on the ispMACH 4000 devices as a deterrent to unauthorized copying of the array configuration patterns. Once programmed, this bit defeats readback of the programmed pattern by a device programmer, securing proprietary designs from competitors. Programming and verification are also defeated by the security bit. The bit can only be reset by erasing the entire device. Hot Socketing The ispMACH 4000 devices are well-suited for applications that require hot socketing capability. Hot socketing a device requires that the device, during power-up and down, can tolerate active signals on the I/Os and inputs without being damaged. Additionally, it requires that the effects of I/O pin loading be minimal on active signals. The ispMACH 4000 devices provide this capability for input voltages in the range 0V to 3.0V. Density Migration The ispMACH 4000 family has been designed to ensure that different density devices in the same package have the same pin-out. Furthermore, the architecture ensures a high success rate when performing design migration from lower density parts to higher density parts. In many cases, it is possible to shift a lower utilization design targeted for a high density device to a lower density device. However, the exact details of the final resource utilization will impact the likely success in each case. 14 Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet Absolute Maximum Ratings1, 2, 3 ispMACH 4000C/Z ispMACH 4000B ispMACH 4000V (1.8V) (2.5V) (3.3V) Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . -0.5 to 2.5V . . . . . . . . . .-0.5 to 5.5V . . . . . . . . . . -0.5 to 5.5V . Output Supply Voltage (VCCO) . . . . . . . . . . . . . . . -0.5 to 4.5V . . . . . . . . . .-0.5 to 4.5V . . . . . . . . . . -0.5 to 4.5V . . Input or I/O Tristate Voltage Applied4, 5 . . . . . . . . . -0.5 to 5.5V . . . . . . . . . .-0.5 to 5.5V . . . . . . . . . . -0.5 to 5.5V Storage Temperature . . . . . . . . . . . . . . . . . . . . . . -65 to 150°C . . . . . . . . . -65 to 150°C. . . . . . . . . .-65 to 150°C Junction Temperature (Tj) with Power Applied . . . -55 to 150°C. . . . . . . . . -55 to 150°C. . . . . . . . . .-55 to 150°C 1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. 2. Compliance with Lattice Thermal Management document is required. 3. All voltages referenced to GND. 4. Undershoot of -2V and overshoot of (VIH (MAX) + 2V), up to a total pin voltage of 6.0V, is permitted for a duration of < 20ns. 5. Maximum of 64 I/Os per device with VIN > 3.6V is allowed. Recommended Operating Conditions Symbol Supply Voltage for 1.8V Devices VCC Supply Voltage for 2.5V Devices Supply Voltage for 3.3V Devices Junction Temperature (Commercial) Tj Junction Temperature (Industrial) Junction Temperature (Automotive) Parameter ispMACH 4000C ispMACH 4000Z Min. 1.65 1.7 2.3 3.0 0 -40 -40 Max. 1.95 1.9 2.7 3.6 90 105 130 Units V V V V C C C Erase Reprogram Specifications Parameter Erase/Reprogram Cycle Note: Valid over commercial temperature range. Min. 1,000 Max. — Units Cycles Hot Socketing Characteristics1,2,3 Symbol IDK Parameter Input or I/O Leakage Current Condition 0 ≤ VIN ≤ 3.0V, Tj = 105°C 0 ≤ VIN ≤ 3.0V, Tj = 130°C Min. — — Typ. ±30 ±30 Max. ±150 ±200 Units µA µA 1. Insensitive to sequence of VCC or VCCO. However, assumes monotonic rise/fall rates for VCC and VCCO, provided (VIN - VCCO) ≤ 3.0V. 2. 0 < VCC < VCC (MAX), 0 < VCCO < VCCO (MAX). 3. IDK is additive to IPU, IPD or IBH. Device defaults to pull-up until fuse circuitry is active. 15 Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet I/O Recommended Operating Conditions VCCO (V)1 Standard LVTTL LVCMOS 3.3 Extended LVCMOS 3.32 LVCMOS 2.5 LVCMOS 1.8 PCI 3.3 Min. 3.0 3.0 2.7 2.3 1.65 3.0 Max. 3.6 3.6 3.6 2.7 1.95 3.6 1. Typical values for VCCO are the average of the min. and max. values. 2. ispMACH 4000Z only. DC Electrical Characteristics Over Recommended Operating Conditions Symbol IIL, IIH1 Parameter Input Leakage Current Condition 0 < VIN ≤ 3.6V, Tj = 105°C 0 < VIN ≤ 3.6V, Tj = 130°C 3.6V < VIN ≤ 5.5V, Tj = 105°C 3.0V ≤ VCCO ≤ 3.6V 3.6V < VIN ≤ 5.5V, Tj = 130°C 3.0V ≤ VCCO ≤ 3.6V 0 ≤ VIN ≤ 0.7VCCO VIN = VIL (MAX) VIN = 0.7 VCCO 0V ≤ VIN ≤ VBHT VBHT ≤ VIN ≤ VCCO — VCCO = 3.3V, 2.5V, 1.8V VCC = 1.8V, VIO = 0 to VIH (MAX) VCCO = 3.3V, 2.5V, 1.8V VCC = 1.8V, VIO = 0 to VIH (MAX) VCCO = 3.3V, 2.5V, 1.8V VCC = 1.8V, VIO = 0 to VIH (MAX) Min. — — — — -30 30 30 -30 — — VCCO * 0.35 — — — — — — Typ. — — — — — — — — — — — 8 6 6 Max. 10 15 20 50 -150 150 — — 150 -150 VCCO * 0.65 — — — — — — Units µA µA µA µA µA µA µA µA µA µA V pf pf pf IIH2 IPU IPD IBHLS IBHHS IBHLO IBHHO VBHT C1 C2 C3 Input High Leakage Current I/O Weak Pull-up Resistor Current Bus Hold Low Sustaining Current Bus Hold High Sustaining Current Bus Hold Low Overdrive Current Bus Hold High Overdrive Current Bus Hold Trip Points I/O Capacitance3 Clock Capacitance3 Global Input Capacitance3 I/O Weak Pull-down Resistor Current VIL (MAX) ≤ VIN ≤ VIH (MIN) 1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tristated. It is not measured with the output driver active. Bus maintenance circuits are disabled. 2. 5V tolerant inputs and I/O should only be placed in banks where 3.0V ≤ VCCO ≤ 3.6V. 3. TA = 25°C, f = 1.0MHz 16 Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet Supply Current, ispMACH 4000V/B/C Over Recommended Operating Conditions Symbol ispMACH 4032V/B/C Vcc = 3.3V ICC 1,2,3 Parameter Condition Min. — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Typ. 11.8 11.8 1.8 11.3 11.3 1.3 12 12 2 11.5 11.5 1.5 12 12 2 11.5 11.5 1.5 12.5 12.5 2.5 12 12 2 13.5 13.5 3.5 12.5 12.5 2.5 14 14 4 Max. — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Units mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA Operating Power Supply Current Vcc = 2.5V Vcc = 1.8V Vcc = 3.3V ICC4 Standby Power Supply Current Vcc = 2.5V Vcc = 1.8V ispMACH 4064V/B/C Vcc = 3.3V ICC1,2,3 Operating Power Supply Current Vcc = 2.5V Vcc = 1.8V Vcc = 3.3V ICC 5 Standby Power Supply Current Vcc = 2.5V Vcc = 1.8V ispMACH 4128V/B/C Vcc = 3.3V ICC 1,2,3 Operating Power Supply Current Vcc = 2.5V Vcc = 1.8V Vcc = 3.3V ICC4 Standby Power Supply Current Vcc = 2.5V Vcc = 1.8V ispMACH 4256V/B/C Vcc = 3.3V ICC1,2,3 Operating Power Supply Current Vcc = 2.5V Vcc = 1.8V Vcc = 3.3V ICC 4 Standby Power Supply Current Vcc = 2.5V Vcc = 1.8V ispMACH 4384V/B/C Vcc = 3.3V ICC 1,2,3 Operating Power Supply Current Vcc = 2.5V Vcc = 1.8V Vcc = 3.3V ICC4 Standby Power Supply Current Vcc = 2.5V Vcc = 1.8V ispMACH 4512V/B/C Vcc = 3.3V ICC1,2,3 Operating Power Supply Current Vcc = 2.5V Vcc = 1.8V 17 Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet Supply Current, ispMACH 4000V/B/C (Cont.) Over Recommended Operating Conditions Symbol ICC 1. 2. 3. 4. 4 Parameter Standby Power Supply Current Condition Vcc = 3.3V Vcc = 2.5V Vcc = 1.8V Min. — — — Typ. 13 13 3 Max. — — — Units mA mA mA TA = 25°C, frequency = 1.0 MHz. Device configured with 16-bit counters. ICC varies with specific device configuration and operating frequency. TA = 25°C Supply Current, ispMACH 4000Z Over Recommended Operating Conditions Symbol ispMACH 4032ZC 1 Parameter Condition Vcc = 1.8V, TA = 25°C Min. — — — — — — — — — — — — — — — — — — — — — — — — Typ. 50 58 60 70 10 16 18 22 Max. Units — — — — — 20 22 — — — — — — — — — — — — — — — — — µA µA µA µA µA µA µA µA µA µA µA µA µA µA µA µA µA µA µA µA µA µA µA µA ICC3, 4, 5, 7 Operating Power Supply Current Vcc = 1.9V, TA = 70°C Vcc = 1.9V, TA = 85°C Vcc = 1.9V, TA = 125°C Vcc = 1.8V, TA = 25°C Vcc = 1.9V, TA = 70°C Vcc = 1.9V, TA = 85°C Vcc = 1.9V, TA = 125°C ICC6, 7 Standby Power Supply Current ispMACH 4064ZC2 Vcc = 1.8V, TA = 25°C ICC3, 4, 5, 7 Operating Power Supply Current Vcc = 1.9V, TA = 70°C Vcc = 1.9V, TA = 85°C Vcc = 1.9V, TA = 125°C Vcc = 1.8V, TA = 25°C ICC6, 7 Standby Power Supply Current Vcc = 1.9V, TA = 70°C Vcc = 1.9V, TA = 85°C Vcc = 1.9V, TA = 125°C ispMACH 4128ZC2 Vcc = 1.8V, TA = 25°C ICC3, 4, 5, 7 Operating Power Supply Current Vcc = 1.9V, TA = 70°C Vcc = 1.9V, TA = 85°C Vcc = 1.9V, TA = 125°C Vcc = 1.8V, TA = 25°C ICC6, 7 Standby Power Supply Current Vcc = 1.9V, TA = 70°C Vcc = 1.9V, TA = 85°C Vcc = 1.9V, TA = 125°C 18 Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet Supply Current, ispMACH 4000Z (Cont.) Over Recommended Operating Conditions Symbol ispMACH 4256ZC 2 Parameter Condition Vcc = 1.8V, TA = 25°C Min. — — — — — — — — Typ. Max. Units — — — — — — — — µA µA µA µA µA µA µA µA ICC3, 4, 5, 7 Operating Power Supply Current Vcc = 1.9V, TA = 70°C Vcc = 1.9V, TA = 85°C Vcc = 1.9V, TA = 125°C Vcc = 1.8V, TA = 25°C Vcc = 1.9V, TA = 70°C Vcc = 1.9V, TA = 85°C Vcc = 1.9V, TA = 125°C ICC6, 7 Standby Power Supply Current 1. 2. 3. 4. 5. 6. 7. Preliminary information. Advance information. TA = 25°C, frequency = 1.0 MHz. Device configured with 16-bit counters. ICC varies with specific device configuration and operating frequency. VCCO = 3.6V, VIN = 0V or VCCO, bus maintenance turned off. VIN above VCCO will add transient current above the specified standby ICC. Includes VCCO current without output loading. 19 Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet I/O DC Electrical Characteristics Over Recommended Operating Conditions VIL Standard LVTTL LVCMOS 3.3 LVCMOS 2.5 LVCMOS 1.8 (4000V/B) LVCMOS 1.8 (4000C/Z) PCI 3.3 (4000V/B) PCI 3.3 (4000C/Z) Min (V) -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 Max (V) 0.80 0.80 0.70 0.63 0.35 * VCC 1.08 VIH Min (V) 2.0 2.0 1.70 1.17 0.65 * VCC 1.5 Max (V) 5.5 5.5 3.6 3.6 3.6 5.5 5.5 VOL Max (V) 0.40 0.20 0.40 0.20 0.40 0.20 0.40 0.20 0.40 0.20 0.1 VCCO 0.1 VCCO VOH Min (V) VCCO - 0.40 VCCO - 0.20 VCCO - 0.40 VCCO - 0.20 VCCO - 0.40 VCCO - 0.20 VCCO - 0.45 VCCO - 0.20 VCCO - 0.45 VCCO - 0.20 0.9 VCCO 0.9 VCCO IOL1 (mA) 8.0 0.1 8.0 0.1 8.0 0.1 2.0 0.1 2.0 0.1 1.5 1.5 IOH1 (mA) -4.0 -0.1 -4.0 -0.1 -4.0 -0.1 -2.0 -0.1 -2.0 -0.1 -0.5 -0.5 0.3 * 3.3 * (VCC / 1.8) 0.5 * 3.3 * (VCC / 1.8) 1. The average DC current drawn by I/Os between adjacent bank GND connections, or between the last GND in an I/O bank and the end of the I/O bank, as shown in the logic signals connection table, shall not exceed n*8mA. Where n is the number of I/Os between bank GND connections or between the last GND in a bank and the end of a bank. 20 Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet 100 3.3V VCCO Typical I/O Output Current (mA) IOL IOH 70 60 50 40 30 20 10 0 0 0.5 2.5V VCCO Typical I/O Output Current (mA) 80 60 40 20 0 IOL IOH 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 1.0 1.5 2.0 2.5 VO Output Voltage (V) VO Output Voltage (V) 60 1.8V VCCO Typical I/O Output Current (mA) 50 40 30 20 10 0 0 0.5 1.0 1.5 2.0 IOL IOH VO Output Voltage (V) 21 Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet ispMACH 4000V/B/C External Switching Characteristics Over Recommended Operating Conditions -25 Parameter tPD tPD_MC tS tST tSIR tSIRZ tH tHT tHIR tHIRZ tCO tR tRW tPTOE/DIS tGPTOE/DIS tGOE/DIS tCW tGW tWIR fMAX4 fMAX (Ext.) 1. 2. 3. 4. -27 Min. — — 1.8 2.0 1.0 2.0 0.0 0.0 1.0 0.0 — — 1.5 — — — 1.3 1.3 1.3 333 222 Max. 2.7 3.5 — — — — — — — — 2.7 4.0 — 4.5 6.5 3.5 — — — — — Min. — — 2.0 2.2 1.0 2.0 0.0 0.0 1.0 0.0 — — 1.5 — — — 1.3 1.3 1.3 322 212 -3 Max. 3.0 3.8 — — — — — — — — 2.7 4.4 — 5.0 8.0 4.0 — — — — — Min. — — 2.0 2.2 1.0 2.0 0.0 0.0 1.0 0.0 — — 1.5 — — — 1.3 1.3 1.3 322 212 -35 Max. 3.5 4.2 — — — — — — — — 2.7 4.5 5.5 8.0 4.5 — — — — — Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz Timing v.3.1 Description 1, 2, 3 Min. — — 1.8 2.0 0.7 1.7 0.0 0.0 0.9 0.0 — — 1.5 — — — 1.1 1.1 1.1 400 250 Max. 2.5 3.2 — — — — — — — — 2.2 3.5 — 4.0 5.0 3.0 — — — — — 5-PT bypass combinatorial propagation delay 20-PT combinatorial propagation delay through macrocell GLB register setup time before clock GLB register setup time before clock with T-type register GLB register setup time before clock, input register path GLB register setup time before clock with zero hold GLB register hold time after clock GLB register hold time after clock with T-type register GLB register hold time after clock, input register path GLB register hold time after clock, input register path with zero hold GLB register clock-to-output delay External reset pin to output delay External reset pulse duration Input to output local product term output enable/disable Input to output global product term output enable/disable Global OE input to output enable/disable Global clock width, high or low Global gate width low (for low transparent) or high (for high transparent) Input register clock width, high or low Clock frequency with internal feedback Clock frequency with external feedback, [1/ (tS + tCO)] Timing numbers are based on default LVCMOS 1.8 I/O buffers. Use timing adjusters provided to calculate other standards. Measured using standard switching circuit, assuming GRP loading of 1 and 1 output switching. Pulse widths and clock widths less than minimum will cause unknown behavior. Standard 16-bit counter using GRP feedback. 22 Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet ispMACH 4000V/B/C External Switching Characteristics (Cont.) Over Recommended Operating Conditions -5 Parameter tPD tPD_MC tS tST tSIR tSIRZ tH tHT tHIR tHIRZ tCO tR tRW tPTOE/DIS tGOE/DIS tCW tGW tWIR fMAX 1. 2. 3. 4. 4 -75 Max. 5.0 5.5 — — — — — — — — 3.40 6.30 — 7.00 9.00 5.00 — — — — — Min. — — 4.5 4.7 1.7 2.7 0.0 0.0 1.0 0.0 — — 4.0 — — — 3.3 3.3 3.3 168 111 Max. 7.5 8.0 — — — — — — — — 4.5 9.0 — 9.0 10.3 7.0 — — — — — Min. — — 5.5 5.5 1.7 2.7 0.0 0.0 1.0 0.0 — — 4.0 — — — 4.0 4.0 4.0 125 86 -10 Max. 10.0 10.5 — — — — — — — — 6.0 10.5 — 10.5 12.0 8.0 — — — — — Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz Timing v.3.1 Description 1, 2, 3 Min. — — 3.0 3.2 1.2 2.2 0.0 0.0 1.0 0.0 — — 2.0 — — — 2.2 2.2 2.2 227 156 5-PT bypass combinatorial propagation delay 20-PT combinatorial propagation delay through macrocell GLB register setup time before clock GLB register setup time before clock with T-type register GLB register setup time before clock, input register path GLB register setup time before clock with zero hold GLB register hold time after clock GLB register hold time after clock with T-type register GLB register hold time after clock, input register path GLB register hold time after clock, input register path with zero hold GLB register clock-to-output delay External reset pin to output delay External reset pulse duration Input to output local product term output enable/disable Global OE input to output enable/disable Global clock width, high or low Global gate width low (for low transparent) or high (for high transparent) Input register clock width, high or low Clock frequency with internal feedback tGPTOE/DIS Input to output global product term output enable/disable fMAX (Ext.) Clock frequency with external feedback, [1/ (tS + tCO)] Timing numbers are based on default LVCMOS 1.8 I/O buffers. Use timing adjusters provided to calculate other standards. Measured using standard switching circuit, assuming GRP loading of 1 and 1 output switching. Pulse widths and clock widths less than minimum will cause unknown behavior. Standard 16-bit counter using GRP feedback. 23 Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet ispMACH 4032Z External Switching Characteristics1 Over Recommended Operating Conditions -35 Parameter tPD tPD_MC tS tST tSIR tSIRZ tH tHT tHIR tHIRZ tCO tR tRW tPTOE/DIS tGPTOE/DIS tGOE/DIS tCW tGW tWIR fMAX 5 -5 Min. — — 3.0 3.2 1.2 2.2 0.0 0.0 1.0 0.0 — — 2.0 — — — 2.2 2.2 2.2 200 156 Max. 5.0 5.5 — — — — — — — — 3.4 6.3 — 8.0 8.0 5.0 — — — — — 3.5 4.4 — — — — — — — — 3.0 5.0 — 7.0 6.5 4.5 — — — — — — — 4.5 4.7 1.7 2.7 0.0 0.0 1.0 0.0 — — 4.0 — — — 3.3 3.3 3.3 150 111 -75 Min. Max. Units 7.5 8.0 — — — — — — — — 4.5 9.0 — 9.0 9.0 7.0 — — — — — ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz Timing v.1.2 Description 2, 3, 4 Min. — — 2.2 2.5 1.0 2.0 0.0 0.0 1.0 0.0 — — 1.5 — — — 1.0 1.0 1.0 267 192 Max. 5-PT bypass combinatorial propagation delay 20-PT combinatorial propagation delay through macrocell GLB register setup time before clock GLB register setup time before clock with T-type register GLB register setup time before clock, input register path GLB register setup time before clock with zeto hold GLB register hold time after clock GLB register hold time after clock with T-type register GLB register hold time after clock, input register path GLB register hold time after clock, input register path with zero hold GLB register clock-to-output delay External reset pin to output delay External reset pulse duration Input to output local product term output enable/disable Input to output global product term output enable/disable Global OE input to output enable/disable Global clock width, high or low Global gate width low (for low transparent) or high (for high transparent) Input register clock width, high or low Clock frequency with internal feedback clock frequency with external feedback, [1/(tS + tCO)] tMAX (Ext.) 1. Preliminary information. 2. Timing numbers are based on default LVCMOS 1.8 I/O buffers. Use timing adjusters provided to calculate other standards. 3. Measured using standard switching GRP loading of 1 and 1 output switching. 4. Pulse widths and clock widths less than minimum will cause unknown behavior. 5. Standard 16-bit counter using GRP feedback. 24 Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet Timing Model The task of determining the timing through the ispMACH 4000 family, like any CPLD, is relatively simple. The timing model provided in Figure 11 shows the specific delay paths. Once the implementation of a given function is determined either conceptually or from the software report file, the delay path of the function can easily be determined from the timing model. The Lattice design tools report the timing delays based on the same timing model for a particular design. Note that the internal timing parameters are given for reference only, and are not tested. The external timing parameters are tested and guaranteed for every device. For more information on the timing model and usage, please refer to Technical Note TN1004: ispMACH 4000 Timing Model Design and Usage Guidelines. Figure 11. ispMACH 4000 Timing Model Routing/GLB Delays From Feedback tPDb tPDi IN tIN tIOI tROUTE tBLA tINREG tINDIO tMCELL tEXP DATA Q tFBK tBUF tIOO tEN tDIS In/Out Delays Feedback tORP Out SCLK tGCLK_IN tIOI tPTCLK tBCLK tPTSR tBSR C.E. S/R MC Reg. Register/Latch Delays Control Delays OE tGOE tIOI In/Out Delays tGPTOE tPTOE Note: Italicized items are optional delay adders. 25 Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet ispMACH 4000V/B/C Internal Timing Parameters Over Recommended Operating Conditions Parameter In/Out Delays tIN tGOE tGCLK_IN tBUF tEN tDIS tROUTE tMCELL tINREG tFBK tPDb tPDi Input Buffer Delay Global OE Pin Delay Global Clock Input Buffer Delay Delay through Output Buffer Output Enable Time Output Disable Time Delay through GRP Macrocell Delay Input Buffer to Macrocell Register Delay Internal Feedback Delay 5-PT Bypass Propagation Delay Macrocell Propagation Delay D-Register Setup Time (Global Clock) D-Register Setup Time (Product Term Clock) T-Register Setup Time (Global Clock) T-Register Setup Time (Product Term Clock) D-Register Hold Time T-Register Hold Time D-Input Register Setup Time (Global Clock) D-Input Register Setup Time (Product Term Clock) D-Input Register Hold Time (Global Clock) D-Input Register Hold Time (Product Term Clock) Register Clock to Output/Feedback MUX Time Clock Enable Setup Time Clock Enable Hold Time Latch Setup Time (Global Clock) Latch Setup Time (Product Term Clock) Latch Hold Time Latch Gate to Output/Feedback MUX Time — — — — — — — — — — — — 0.60 2.04 0.78 0.85 0.96 0.96 0.61 0.45 0.11 0.00 0.44 0.64 — — — — — — — — — — — — 0.60 2.54 1.28 0.85 0.96 0.96 0.81 0.55 0.31 0.00 0.44 0.64 — — — — — — — — — — — — 0.70 3.04 1.28 0.85 0.96 0.96 1.01 0.55 0.31 0.00 0.44 0.64 — — — — — — — — — — — — 0.70 3.54 1.28 0.85 0.96 0.96 1.01 0.65 0.31 0.00 0.94 0.94 ns ns ns ns ns ns ns ns ns ns ns ns Description -2.5 -2.7 -3 -3.5 Units Routing/GLB Delays Register/Latch Delays tS tS_PT tST tST_PT tH tHT tSIR tSIR_PT tHIR tHIR_PT tCOi tCES tCEH tSL tSL_PT tHL tGOi 0.92 1.42 1.12 1.42 0.88 0.88 0.82 1.45 0.88 0.88 — 2.25 1.88 0.92 1.42 1.17 — — — — — — — — — — — 0.52 — — — — — 0.33 1.12 1.32 1.32 1.32 0.68 0.68 1.37 1.45 0.63 0.63 — 2.25 1.88 1.12 1.32 1.17 — — — — — — — — — — — 0.52 — — — — — 0.33 1.02 1.32 1.22 1.32 0.98 0.98 1.27 1.45 0.73 0.73 — 2.25 1.88 1.02 1.32 1.17 — — — — — — — — — — — 0.52 — — — — — 0.33 0.92 1.32 1.12 1.32 1.08 1.08 1.27 1.45 0.73 0.73 — 2.25 1.88 0.92 1.32 1.17 — — — — — — — — — — — 0.52 — — — — — 0.33 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 26 Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet ispMACH 4000V/B/C Internal Timing Parameters (Cont.) Over Recommended Operating Conditions Parameter tPDLi tSRi tSRR Description Propagation Delay through Transparent Latch to Output/ Feedback MUX Asynchronous Reset or Set to Output/Feedback MUX Delay Asynchronous Reset or Set Recovery Time GLB PT Clock Delay Macrocell PT Clock Delay Block PT Set/Reset Delay Macrocell PT Set/Reset Delay Global PT OE Delay Macrocell PT OE Delay — 0.28 1.67 -2.5 0.25 — — — 0.28 1.67 -2.7 0.25 — — — 0.28 1.67 -3 0.25 — — — 0.28 1.67 -3.5 0.25 — — Units ns ns ns Control Delays tBCLK tPTCLK tBSR tPTSR tGPTOE tPTOE — — — — — — 1.12 0.87 1.83 1.11 2.83 1.83 — — — — — — 1.12 0.87 1.83 1.41 4.13 2.13 — — — — — — 1.12 0.87 1.83 1.51 5.33 2.33 — — — — — — 1.12 0.87 1.83 1.61 5.33 2.83 ns ns ns ns ns ns Timing v.3.1 Note: Internal Timing Parameters are not tested and are for reference only. Refer to Timing Model in this data sheet for further details. 27 Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet ispMACH 4000V/B/C Internal Timing Parameters Over Recommended Operating Conditions -5 Parameter In/Out Delays tIN tGOE tGCLK_IN tBUF tEN tDIS tROUTE tMCELL tINREG tFBK tPDb tPDi tS tS_PT tST tST_PT tH tHT tSIR tSIR_PT tHIR tHIR_PT tCOi tCES tCEH tSL tSL_PT tHL tGOi tPDLi tSRi tSRR tBCLK tPTCLK tBSR tPTSR Input Buffer Delay Global OE Pin Delay Global Clock Input Buffer Delay Delay through Output Buffer Output Enable Time Output Disable Time Delay through GRP Macrocell Delay Input Buffer to Macrocell Register Delay Internal Feedback Delay 5-PT Bypass Propagation Delay Macrocell Propagation Delay D-Register Setup Time (Global Clock) D-Register Setup Time (Product Term Clock) T-Register Setup Time (Global Clock) T-Register Setup Time (Product Term Clock) D-Register Hold Time T-Register Hold Time D-Input Register Setup Time (Global Clock) D-Input Register Setup Time (Product Term Clock) D-Input Register Hold Time (Global Clock) D-Input Register Hold Time (Product Term Clock) Register Clock to Output/Feedback MUX Time Clock Enable Setup Time Clock Enable Hold Time Latch Setup Time (Global Clock) Latch Setup Time (Product Term Clock) Latch Hold Time Latch Gate to Output/Feedback MUX Time Propagation Delay through Transparent Latch to Output/ Feedback MUX Asynchronous Reset or Set to Output/Feedback MUX Delay Asynchronous Reset or Set Recovery Time GLB PT Clock Delay Macrocell PT Clock Delay GLB PT Set/Reset Delay Macrocell PT Set/Reset Delay — — — — — — — — — — — — 1.32 1.32 1.52 1.32 1.68 1.68 1.52 1.45 0.68 0.68 — 2.25 1.88 1.32 1.32 1.17 — — 0.28 1.67 — — — — 0.95 4.04 1.83 1.00 0.96 0.96 1.51 1.05 0.56 0.00 1.54 0.94 — — — — — — — — — — 0.52 — — — — — 0.33 0.25 — — 1.12 0.87 1.83 2.51 — — — — — — — — — — — — 1.57 1.32 1.77 1.32 2.93 2.93 1.57 1.45 1.18 1.18 — 2.25 1.88 1.57 1.32 1.17 — — 0.28 1.67 — — — — 1.50 6.04 2.28 1.50 0.96 0.96 2.26 1.45 0.96 0.00 2.24 1.24 — — — — — — — — — — 0.67 — — — — — 0.33 0.25 — — 1.12 0.87 1.83 3.41 — — — — — — — — — — — — 1.57 1.32 1.77 1.32 3.93 3.93 1.57 1.45 1.18 1.18 — 2.25 1.88 1.57 1.32 1.17 — — 0.28 1.67 — — — — 2.00 7.04 3.28 1.50 0.96 0.96 3.26 1.95 1.46 0.00 3.24 1.74 — — — — — — — — — — 1.17 — — — — — 0.33 0.25 — — 0.62 0.87 1.83 3.41 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. -75 Min. Max. -10 Min. Max. Units Routing/GLB Delays Register/Latch Delays Control Delays 28 Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet ispMACH 4000V/B/C Internal Timing Parameters (Cont.) Over Recommended Operating Conditions -5 Parameter tGPTOE tPTOE Global PT OE Delay Macrocell PT OE Delay Description Min. — — Max. 5.58 3.58 — — -75 Min. Max. 5.58 4.28 — — -10 Min. Max. 5.78 4.28 Units ns ns Timing v.3.1 Note: Internal Timing Parameters are not tested and are for reference only. Refer to Timing Model in this data sheet for further details. 29 Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet ispMACH 4032Z Internal Timing Parameters1 Over Recommended Operating Conditions -35 Parameter In/Out Delays tIN tGOE tGCLK_IN tBUF tEN tDIS tROUTE tMCELL tINREG tFBK tPDb tPDi tS tS_PT tST tST_PT tH tHT tSIR tSIR_PT tHIR tHIR_PT tCOi tCES tCEH tSL tSL_PT tHL tGOi tPDLi tSRi tSRR tBCLK tPTCLK tBSR tPTSR tGPTOE Input Buffer Delay Global OE Pin Delay Global Clock Input Buffer Delay Delay through Output Buffer Output Enable Time Output Disable Time Delay through GRP Macrocell Delay Input Buffer to Macrocell Register Delay Internal Feedback Delay 5-PT Bypass Propagation Delay Macrocell Propagation Delay D-Register Setup Time (Global Clock) D-Register Setup Time (Product Term Clock) T-Register Setup Time (Global Clock) T-register Setup Time (Product Term Clock) D-Register Hold Time T-Resister Hold Time D-Input Register Setup Time (Global Clock) D-Input Register Setup Time (Product Term Clock) D-Input Register Hold Time (Global Clock) D-Input Register Hold Time (Product Term Clock) Register Clock to Output/Feedback MUX Time Clock Enable Setup Time Clock Enable Hold Time Latch Setup Time (Global Clock) Latch Setup Time (Product Term Clock) Latch Hold Time Latch Gate to Output/Feedback MUX Time Propagation Delay through Transparent Latch to Output/Feedback MUX Asynchronous Reset or Set to Output/Feedback MUX Delay Asynchronous Reset or Set Recovery Delay GLB PT Clock Delay Macrocell PT Clock Delay GLB PT Set/Reset Delay Macrocell PT Set/Reset Delay Global PT OE Delay — — — — — — — — — — — — 0.60 1.55 0.90 1.75 1.60 1.60 0.84 1.45 1.16 0.88 — 1.00 0.00 0.65 1.75 1.40 — — — — — — — — — 0.75 2.90 1.50 0.65 1.60 1.35 1.70 0.65 0.91 0.35 0.40 0.25 — — — — — — — — — — 0.45 — — — — — 0.40 0.30 1.00 2.00 1.50 1.70 1.10 0.50 2.45 — — — — — — — — — — — — 0.70 1.50 0.90 1.50 2.30 2.30 1.40 1.45 0.80 1.00 — 1.40 0.00 1.02 1.32 1.17 — — — — — — — — — 0.95 3.20 1.90 0.90 1.80 1.60 2.25 1.00 0.75 0.50 0.90 0.35 — — — — — — — — — — 0.55 — — — — — 0.33 0.25 0.28 1.67 1.12 0.87 1.83 1.87 3.00 — — — — — — — — — — — — 1.57 1.65 1.77 1.32 2.93 2.93 1.83 1.45 0.87 1.18 — 2.00 0.00 1.57 1.32 1.17 — — — — — — — — — 1.50 4.96 2.28 1.50 2.04 2.96 2.26 1.45 0.65 0.70 2.24 1.24 — — — — — — — — — — 0.67 — — — — — 0.33 0.25 0.28 1.67 1.12 0.87 1.83 3.41 3.20 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. Min. -5 Max. -75 Min. Max. Units Routing/GLB Delays Register/Latch Delays Control Delays 30 Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet ispMACH 4032Z Internal Timing Parameters1 (Cont.) Over Recommended Operating Conditions -35 Parameter tPTOE Macrocell PT OE Delay Description Min. — Max. 2.95 Min. — -5 Max. 3.00 — -75 Min. Max. Units 3.20 ns Timing v.1.2 1. Preliminary information. Note: Internal Timing Parameters are not tested and are for reference only. Refer to Timing Model in this data sheet for further details. 31 Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet ispMACH 4000V/B/C Timing Adders1 Adder Type tINDIO tEXP tORP tBLA Base Parameter tINREG tMCELL — tROUTE -25 Description Input register delay Product term expander delay Output routing pool delay Additional block loading adder Min. — — — — Max. 0.95 0.33 0.05 0.03 -27 Min. — — — — Max. 1.00 0.33 0.05 0.05 Min. — — — — -3 Max. 1.00 0.33 0.05 0.05 Min. — — — — -35 Max. Units 1.00 0.33 0.05 0.05 ns ns ns ns Optional Delay Adders tIOI Input Adjusters LVTTL_in LVCMOS33_in LVCMOS25_in LVCMOS18_in PCI_in tIN, tGCLK_IN, tGOE tIN, tGCLK_IN, tGOE tIN, tGCLK_IN, tGOE tIN, tGCLK_IN, tGOE tIN, tGCLK_IN, tGOE Using LVTTL standard Using LVCMOS 3.3 standard Using LVCMOS 2.5 standard Using LVCMOS 1.8 standard Using PCI compatible input Output configured as TTL buffer — — — — — 0.60 0.60 0.60 0.00 0.60 — — — — — 0.60 0.60 0.60 0.00 0.60 — — — — — 0.60 0.60 0.60 0.00 0.60 — — — — — 0.60 0.60 0.60 0.00 0.60 ns ns ns ns ns tIOO Output Adjusters LVTTL_out tBUF, tEN, tDIS — — — — — — 0.20 0.20 0.10 0.00 0.20 1.00 — — — — — — 0.20 0.20 0.10 0.00 0.20 1.00 — — — — — — 0.20 0.20 0.10 0.00 0.20 1.00 — — — — — — 0.20 0.20 0.10 0.00 0.20 1.00 ns ns ns ns ns ns Output configured as LVCMOS33_out tBUF, tEN, tDIS 3.3V buffer Output configured as LVCMOS25_out tBUF, tEN, tDIS 2.5V buffer Output configured as LVCMOS18_out tBUF, tEN, tDIS 1.8V buffer PCI_out Slow Slew tBUF, tEN, tDIS tBUF, tEN Output configured as PCI compatible buffer Output configured for slow slew rate Note: Open drain timing is the same as corresponding LVCMOS timing. Timing v.3.1 1. Refer to Technical Note TN1004: ispMACH 4000 Timing Model Design and Usage Guidelines for information regarding use of these adders. 32 Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet ispMACH 4000V/B/C Timing Adders1 Adder Type tINDIO tEXP tORP tBLA tIOI Input Adjusters LVTTL_in LVCMOS33_in LVCMOS25_in LVCMOS18_in PCI_in tIN, tGCLK_IN, tGOE tIN, tGCLK_IN, tGOE tIN, tGCLK_IN, tGOE tIN, tGCLK_IN, tGOE tIN, tGCLK_IN, tGOE Using LVTTL standard Using LVCMOS 3.3 standard Using LVCMOS 2.5 standard Using LVCMOS 1.8 standard Using PCI compatible input — — — — — 0.60 0.60 0.60 0.00 0.60 — — — — — 0.60 0.60 0.60 0.00 0.60 — — — — — 0.60 0.60 0.60 0.00 0.60 ns ns ns ns ns Base Parameter tINREG tMCELL — tROUTE -5 Description Input register delay Product term expander delay Output routing pool delay Additional block loading adder Min. — — — — Max. 1.00 0.33 0.05 0.05 -75 Min. — — — — Max. 1.00 0.33 0.05 0.05 -10 Min. — — — — Max. Units 1.00 0.33 0.05 0.05 ns ns ns ns Optional Delay Adders tIOO Output Adjusters LVTTL_out tBUF, tEN, tDIS Output configured as TTL buffer — — — — — — 0.20 0.20 0.10 0.00 0.20 1.00 — — — — — — 0.20 0.20 0.10 0.00 0.20 1.00 — — — — — — 0.20 0.20 0.10 0.00 0.20 1.00 ns ns ns ns ns ns LVCMOS33_out tBUF, tEN, tDIS Output configured as 3.3V buffer LVCMOS25_out tBUF, tEN, tDIS Output configured as 2.5V buffer LVCMOS18_out tBUF, tEN, tDIS Output configured as 1.8V buffer PCI_out Slow Slew Output configured as PCI compatible tBUF, tEN, tDIS buffer tBUF, tEN Output configured for slow slew rate Note: Open drain timing is the same as corresponding LVCMOS timing. Timing v.3.1 1. Refer to Technical Note TN1004: ispMACH 4000 Timing Model Design and Usage Guidelines for information regarding use of these adders. 33 Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet ispMACH 4032Z Timing Adders1, 2 Adder Type tINDIO tEXP tORP tBLA LVTTL_in LVCMOS33_in LVCMOS25_in LVCMOS18_in PCI_in LVTTL_out Base Parameter tINREG tMCELL — tROUTE -35 Description Input register delay Product term expander delay Output routing pool delay Additional block loading adder Min. — — — — — — — — — — — — — — — Max. 1.00 0.40 0.40 0.04 0.70 0.70 0.40 0.00 0.70 0.70 0.70 0.40 0.00 0.70 1.00 Min. — — — — — — — — — — — — — — — -5 Max. 1.00 0.50 0.05 0.05 0.70 0.70 0.40 0.00 0.70 0.70 0.70 0.40 0.00 0.70 1.00 Min. — — — — — — — — — — — — — — — -7 Max. 1.00 0.50 0.05 0.05 0.70 0.70 0.40 0.00 0.70 0.70 0.70 0.40 0.00 0.70 1.00 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Timing v.1.2 Optional Delay Adders tIOI Input Adjusters tIN, tGCLK_IN, tGOE Using LVTTL standard tIN, tGCLK_IN, tGOE Using LVCMOS 3.3 standard tIN, tGCLK_IN, tGOE Using LVCMOS 2.5 standard tIN, tGCLK_IN, tGOE Using LVCMOS 1.8 standard tIN, tGCLK_IN, tGOE Using PCI compatible input tBUF, tEN, tDIS Output configured as TTL buffer Output configured as 3.3V buffer Output configured as 2.5V buffer Output configured as 1.8V buffer Output configured as PCI compatible buffer Output configured for slow slew rate tIOO Output Adjusters LVCMOS33_out tBUF, tEN, tDIS LVCMOS25_out tBUF, tEN, tDIS LVCMOS18_out tBUF, tEN, tDIS PCI_out Slow Slew tBUF, tEN, tDIS tBUF, tEN 1. Preliminary information. 2. Refer to Technical Note TN 1004: ispMACH 4000 Timing Model Design and Usage Guidelines for information regarding use of these adders. Note: Open drain timing is the same as corresponding LVCMOS timing. 34 Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet Boundary Scan Waveforms and Timing Specifications Symbol tBTCP tBTCH tBTCL tBTSU tBTH tBRF tBTCO tBTOZ tBTVO tBTCPSU tBTCPH tBTUCO tBTUOZ tBTUOV TCK [BSCAN test] clock cycle TCK [BSCAN test] pulse width high TCK [BSCAN test] pulse width low TCK [BSCAN test] setup time TCK [BSCAN test] hold time TCK [BSCAN test] rise and fall time TAP controller falling edge of clock to valid output TAP controller falling edge of clock to data output disable TAP controller falling edge of clock to data output enable BSCAN test Capture register setup time BSCAN test Capture register hold time BSCAN test Update reg, falling edge of clock to valid output BSCAN test Update reg, falling edge of clock to output disable BSCAN test Update reg, falling edge of clock to output enable Parameter Min. 40 20 20 8 10 50 — — — 8 10 — — — Max. — — — — — — 10 10 10 — — 25 25 25 Units ns ns ns ns ns mV/ns ns ns ns ns ns ns ns ns 35 Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet Power Consumption ispMACH 4000Z Typical ICC vs. Frequency (Preliminary Information) 100 300 300 ispMACH 4000C Typical ICC vs. Frequency ispMACH 4000V/B Typical ICC vs. Frequency 4512V/B 4512C 80 250 250 4384V/B 4384C ICC (mA) ICC (mA) ICC (mA) 60 200 200 4256V/B 150 150 4256C 40 100 20 100 4128V/B 4128C 4032ZC 0 0 50 4064C 4032C 50 4064V/B 4032V/B 50 100 150 200 250 300 0 0 50 100 150 200 250 300 350 400 0 0 50 100 150 200 250 300 350 400 Frequency (MHz) Note: The devices are configured with maximum number of 16-bit counters, typical current at 1.8V, 25°C. Frequency (MHz) Note: The devices are configured with maximum number of 16-bit counters, typical current at 1.8V, 25°C. Frequency (MHz) Note: The devices are configured with maximum number of 16-bit counters, typical current at 3.3V, 2.5V, 25°C. Power Estimation Coefficients1 Device ispMACH 4032V/B ispMACH 4032C ispMACH 4064V/B ispMACH 4064C ispMACH 4128V/B ispMACH 4128C ispMACH 4256V/B ispMACH 4256C ispMACH 4384V/B ispMACH 4384C ispMACH 4512V/B ispMACH 4512C ispMACH 4032ZC2 ispMACH 4064ZC3 ispMACH 4128ZC3 ispMACH 4256ZC3 1. For further information about the use of these coefficients, refer to Technical Note TN1005, Power Estimation in ispMACH 4000V/B/C Devices. 2. Preliminary information. 3. Advance information. A 11.3 1.3 11.5 1.5 11.5 1.5 12 2 12.5 2.5 13 3 0.020 B 0.010 0.010 0.010 0.010 0.011 0.011 0.011 0.011 0.013 0.013 0.013 0.013 0.010 36 Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet Switching Test Conditions Figure 12 shows the output test load that is used for AC testing. The specific values for resistance, capacitance, voltage, and other test conditions are shown in Table 11. Figure 12. Output Test Load, LVTTL and LVCMOS Standards VCCO R1 DUT R2 CL Test Point 0213A/ispm4k Table 11. Test Fixture Required Components Test Condition LVCMOS I/O, (L -> H, H -> L) LVCMOS I/O (Z -> H) LVCMOS I/O (Z -> L) LVCMOS I/O (H -> Z) LVCMOS I/O (L -> Z) 1. CL includes test fixtures and probe capacitance. R1 R2 CL1 35pF 35pF 35pF 5pF 5pF Timing Ref. LVCMOS 3.3 = 1.5V LVCMOS 2.5 = VCCO/2 LVCMOS 1.8 = VCCO/2 1.5V 1.5V VOH - 0.3 VOL + 0.3 VCCO LVCMOS 3.3 = 3.0V LVCMOS 2.5 = 2.3V LVCMOS 1.8 = 1.65V 3.0V 3.0V 3.0V 3.0V 106Ω 106Ω ∞ 106Ω ∞ 106Ω 106Ω ∞ 106Ω ∞ 37 Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet Signal Descriptions Signal Names TMS TCK TDI TDO GOE0/IO, GOE1/IO GND NC VCC CLK0/I, CLK1/I, CLK2/I, CLK3/I VCCO0, VCCO1 Description Input – This pin is the IEEE 1149.1 Test Mode Select input, which is used to control the state machine Input – This pin is the IEEE 1149.1 Test Clock input pin, used to clock through the state machine Input – This pin is the IEEE 1149.1 Test Data In pin, used to load data Output – This pin is the IEEE 1149.1 Test Data Out pin used to shift data out These pins are configured to be either Global Output Enable Input or as general I/O pins Ground Not Connected The power supply pins for logic core These pins are configured to be either CLK input or as an input The power supply pins for each I/O bank Input/Output1 – These are the general purpose I/O used by the logic array. y is GLB reference (alpha) and z is macrocell reference (numeric). z: 0-15 ispMACH 4032 ispMACH 4064 yzz ispMACH 4128 ispMACH 4256 ispMACH 4384 ispMACH 4512 y: A-B y: A-D y: A-H y: A-P y: A-P, AX-HX y: A-P, AX-PX 1. In some packages, certain I/O are only available for use as inputs. See the signal connections table for details. 38 Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet ispMACH 4000V/B/C/Z Power Supply and NC Connections1 Signal VCC 48 44 TQFP4 TQFP4 11, 33 56 csBGA7 100 TQFP4 25, 40, 75, 90 13, 33, 95 45, 63, 83 1, 26, 51, 76 7, 18, 32, 96 46, 57, 68, 82 — 128 TQFP4 32, 51, 96, 115 144 TQFP4 176 TQFP4 256 fpBGA2, 3, 7 12, 36 K2, A9 36, 57, 108, 42, 69, 88, B2, B15, G8, G9, K8, K9, R2, R15 129 130, 157, 176 4, 22, 40, 56, 166 78, 92, 110, 128, 144 2, 465, 65, 90, 134, 153 D6, F4, H7, J7, L4, N6 D11, F13, H10, J10, L13, N11 VCCO0 VCCO1 6 28 6 30 F3 E8 3, 17, 30, 3, 19, 34, 41, 122 47, 136 58, 67, 81, 94, 105 64, 75, 91, 106, 119 GND 12, 34 13, 37 H3, C8 1, 33, 65, 1, 37, 73, 97 109 10, 24, 40, 113, 123 49, 59, 74, 88, 104 — A1, A16, C6, C11, F3, F14, G7, G10, H8, H9, J8, J9, K7, K10, L3, L14, P6, P11, T1, T16 GND (Bank 0) GND (Bank 1) NC 5 5 D3 10, 186, 27, 13, 31, 55, 46, 127, 137 155, 167 55, 65, 82, 67, 79, 906, 99, 118 101, 119, 143 4128V: 17, 20, 38, 45, 72, 89, 92, 110, 117, 144 4256V: 18, 90 1, 43, 44, 45, 89, 131, 132, 133 4256V/B/C, 128 I/O: A4, A5, A6, A11, A12, A13, A15, B5, B6, B11, B12, B14, C7, D1, D4, D5, D10, D12, D16, E1, E2, E4, E5, E7, E10, E13, E14, E15, E16, F1, F2, F15, F16, G1, G4, G5, G6, G12, G13, G14, J11, K3, K4, K15, L1, L2, L12, L15, L16, M1, M2, M3, M4, M5, M12, M13, M15, M16, N1, N2, N7, N10, N12, N14, P5, P12, R4, R5, R6, R11, R12, R16, T2, T4, T5, T6, T11, T12, T13, T15 4256V/B/C, 160 I/O: A5, A12, A15, B5, B6, B11, B12, B14, D4, D5, D12, E1, E4, E5, E13, E15, E16, F1, F2, F15, G1, G5, G12, G14, L1, L2, L12, L15, L16, M1, M2, M3, M12, M16, N1, N12, N14, P5, R4, R5, R6, R11, R12, R16, T4, T5, T12, T15 4384V/B/C: B5, B12, D5, D12, E1, E15, E16, F2, L12, M1, M2, M16, N12, R5, R12, T4 4512V/B/C: None 27 29 G8 — — 4032Z: A8, B10, E1, E3, F8, F10, J1, K3 1. All grounds must be electrically connected at the board level. However, for the purposes of I/O current loading, grounds are associated with the bank shown. 2. Internal GNDs and I/O GNDs (Bank 0/1) are connected inside package. 3. VCCO balls connect to two power planes within the package, one for VCCO0 and one for VCCO1. 4. Pin orientation follows the conventional order from pin 1 marking of the top side view and counter-clockwise. 5. ispMACH 4384V/B/C pin 46 is tied to GND (Bank 0). 6. ispMACH 4128V only. 7. Pin orientation A1 starts from the upper left corner of the top side view with alphabetical order ascending vertically and numerical order ascending horizontally. 39 Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet ispMACH 4032V/B/C and 4064V/B/C Logic Signal Connections: 44-Pin TQFP ispMACH 4032V/B/C Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 Bank Number 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 GLB/MC/Pad TDI A5 A6 A7 GND (Bank 0) VCCO (Bank 0) A8 A9 A10 TCK VCC GND A12 A13 A14 A15 CLK2/I B0 B1 B2 B3 B4 TMS B5 B6 B7 GND (Bank 1) VCCO (Bank 1) B8 B9 B10 TDO VCC GND B12 B13 B14 B15/GOE1 CLK0/I A0/GOE0 A1 ORP A^5 A^6 A^7 A^8 A^9 A^10 A^12 A^13 A^14 A^15 B^0 B^1 B^2 B^3 B^4 B^5 B^6 B^7 B^8 B^9 B^10 B^12 B^13 B^14 B^15 A^0 A^1 ispMACH 4064V/B/C GLB/MC/Pad TDI A10 A12 A14 GND (Bank 0) VCCO (Bank 0) B0 B2 B4 TCK VCC GND B8 B10 B12 B14 CLK2/I C0 C2 C4 C6 C8 TMS C10 C12 C14 GND (Bank 1) VCCO (Bank 1) D0 D2 D4 TDO VCC GND D8 D10 D12 D14/GOE1 CLK0/I A0/GOE0 A2 ORP A^5 A^6 A^7 B^0 B^1 B^2 B^4 B^5 B^6 B^7 C^0 C^1 C^2 C^3 C^4 C^5 C^6 C^7 D^0 D^1 D^2 D^4 D^5 D^6 D^7 A^0 A^1 40 Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet ispMACH 4032V/B/C and 4064V/B/C Logic Signal Connections: 44-Pin TQFP (Cont.) ispMACH 4032V/B/C Pin Number 42 43 44 Bank Number 0 0 0 GLB/MC/Pad A2 A3 A4 ORP A^2 A^3 A^4 ispMACH 4064V/B/C GLB/MC/Pad A4 A6 A8 ORP A^2 A^3 A^4 ispMACH 4032V/B/C/Z and 4064V/B/C/Z Logic Signal Connections: 48-Pin TQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Bank Number 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 ispMACH 4032V/B/C GLB/MC/Pad TDI A5 A6 A7 GND (Bank 0) VCCO (Bank 0) A8 A9 A10 A11 TCK VCC GND A12 A13 A14 A15 CLK1/I CLK2/I B0 B1 B2 B3 B4 TMS B5 B6 B7 GND (Bank 1) VCCO (Bank 1) B8 B9 ORP A^5 A^6 A^7 A^8 A^9 A^10 A^11 A^12 A^13 A^14 A^15 B^0 B^1 B^2 B^3 B^4 B^5 B^6 B^7 B^8 B^9 ispMACH 4064V/B/C GLB/MC/Pad TDI A10 A12 A14 GND (Bank 0) VCCO (Bank 0) B0 B2 B4 B6 TCK VCC GND B8 B10 B12 B14 CLK1/I CLK2/I C0 C2 C4 C6 C8 TMS C10 C12 C14 GND (Bank 1) VCCO (Bank 1) D0 D2 ORP A^5 A^6 A^7 B^0 B^1 B^2 B^6 B^4 B^5 B^6 B^7 C^0 C^1 C^2 C^3 C^4 C^5 C^6 C^7 D^0 D^1 ispMACH 4064Z GLB/MC/Pad TDI A8 A10 A11 GND (Bank 0) VCCO (Bank 0) B15 B12 B10 B8 TCK VCC GND B6 B4 B2 B0 CLK1/I CLK2/I C0 C1 C2 C4 C6 TMS C8 C10 C11 GND (Bank 1) VCCO (Bank 1) D15 D12 ORP A^8 A^10 A^11 B^15 B^12 B^10 B^8 B^6 B^4 B^2 B^0 C^0 C^1 C^2 C^4 C^6 C^8 C^10 C^11 D^15 D^12 41 Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet ispMACH 4032V/B/C/Z and 4064V/B/C/Z Logic Signal Connections: 48-Pin TQFP (Cont.) Pin Number 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Bank Number 1 1 1 1 1 1 1 0 0 0 0 0 0 ispMACH 4032V/B/C GLB/MC/Pad B10 B11 TDO VCC GND B12 B13 B14 B15/GOE1 CLK3/I CLK0/I A0/GOE0 A1 A2 A3 A4 ORP B^10 B^11 B^12 B^13 B^14 B^15 A^0 A^1 A^2 A^3 A^4 ispMACH 4064V/B/C GLB/MC/Pad D4 D6 TDO VCC GND D8 D10 D12 D14/GOE1 CLK3/I CLK0/I A0/GOE0 A2 A4 A6 A8 ORP D^2 D^3 D^4 D^5 D^6 D^7 A^0 A^1 A^2 A^3 A^4 ispMACH 4064Z GLB/MC/Pad D10 D8 TDO VCC GND D6 D4 D2 D0/GOE1 CLK3/I CLK0/I A0/GOE0 A1 A2 A4 A6 ORP D^10 D^8 D^6 D^4 D^2 D^0 A^0 A^1 A^2 A^4 A^6 ispMACH 4032Z and 4064Z Logic Signal Connections: 56-Ball csBGA ispMACH 4032Z Ball Number B1 C3 C1 D1 D3 E3 E1 F3 F1 G3 G1 H1 J1 K1 K2 H3 K3 K4 H4 H5 Bank Number 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A12 A13 A14 A^12 A^13 A^14 GLB/MC/Pad TDI A5 A6 A7 GND (Bank 0) NC NC VCCO (Bank 0) A8 A9 A10 A11 NC TCK VCC GND ORP A^5 A^6 A^7 A^8 A^9 A^10 A^11 TDI A8 A10 A11 GND (Bank 0) A15/I I VCCO (Bank 0) B15 B12 B10 B8 I TCK VCC GND I B6 B4 B2 ispMACH 4064Z GLB/MC/Pad ORP A^8 A^10 A^11 A^15 B^15 B^12 B^10 B^8 B^6 B^4 B^2 42 Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet ispMACH 4032Z and 4064Z Logic Signal Connections: 56-Ball csBGA (Cont.) ispMACH 4032Z Ball Number K5 H6 K6 H7 K7 K8 K9 K10 J10 H8 H10 G10 G8 F8 F10 E8 E10 D8 D10 C10 B10 A10 A9 C8 A8 A7 C7 C6 A6 C5 A5 C4 A4 A3 A2 A1 Bank Number 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 GLB/MC/Pad A15 CLK1/I CLK2/I B0 B1 B2 B3 B4 TMS B5 B6 B7 GND (Bank 1) NC NC VCCO (Bank 1) B8 B9 B10 B11 NC TDO VCC GND NC B12 B13 B14 B15/GOE1 CLK3/I CLK0/I A0/GOE0 A1 A2 A3 A4 ORP A^15 B^0 B^1 B^2 B^3 B^4 B^5 B^6 B^7 B^8 B^9 B^10 B^11 B^12 B^13 B^14 B^15 A^0 A^1 A^2 A^3 A^4 B0 CLK1/I CLK2/I C0 C1 C2 C4 C6 TMS C8 C10 C11 GND (Bank 1) C12/I I VCCO (Bank 1) D15 D12 D10 D8 I TDO VCC GND I D6 D4 D2 D0/GOE1 CLK3/I CLK0/I A0/GOE0 A1 A2 A4 A6 ispMACH 4064Z GLB/MC/Pad ORP B^0 C^0 C^1 C^2 C^4 C^6 C^8 C^10 C^11 C12 D^15 D^12 D^10 D^8 D^6 D^4 D^2 D^0 A^0 A^1 A^2 A^4 A^6 43 Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet ispMACH 4064V/B/C/Z, 4128V/B/C/Z, 4256V/B/C Logic Signal Connections: 100-Pin TQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12* 13 14 15 16 17 18 19 20 21 22 23* 24 25 26 27* 28 29 30 31 32 33 34 35 36 37 38 39 40 41 Bank Number 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 ispMACH 4064V/B/C/Z GLB/MC/Pad GND TDI A8 A9 A10 A11 GND (Bank 0) A12 A13 A14 A15 I VCCO (Bank 0) B15 B14 B13 B12 GND (Bank 0) B11 B10 B9 B8 I TCK VCC GND I B7 B6 B5 B4 GND (Bank 0) VCCO (Bank 0) B3 B2 B1 B0 CLK1/I CLK2/I VCC C0 ORP A^8 A^9 A^10 A^11 A^12 A^13 A^14 A^15 B^15 B^14 B^13 B^12 B^11 B^10 B^9 B^8 B^7 B^6 B^5 B^4 B^3 B^2 B^1 B^0 C^0 ispMACH 4128V/B/C/Z GLB/MC/Pad GND TDI B0 B2 B4 B6 GND (Bank 0) B8 B10 B12 B13 I VCCO (Bank 0) C14 C12 C10 C8 GND (Bank 0) C6 C5 C4 C2 I TCK VCC GND I D13 D12 D10 D8 GND (Bank 0) VCCO (Bank 0) D6 D4 D2 D0 CLK1/I CLK2/I VCC E0 ORP B^0 B^2 B^4 B^6 B^8 B^10 B^12 B^13 C^14 C^12 C^10 C^8 C^6 C^5 C^4 C^2 D^13 D^12 D^10 D^8 D^6 D^4 D^2 D^0 E^0 ispMACH 4256V/B/C GLB/MC/Pad GND TDI C12 C10 C6 C2 GND (Bank 0) D12 D10 D6 D4 I VCCO (Bank 0) E4 E6 E10 E12 GND (Bank 0) F2 F6 F10 F12 I TCK VCC GND I G12 G10 G6 G2 GND (Bank 0) VCCO (Bank 0) H12 H10 H6 H2 CLK1/I CLK2/I VCC I2 ORP C^6 C^5 C^3 C^1 D^6 D^5 D^3 D^2 E^2 E^3 E^5 E^6 F^1 F^3 F^5 F^6 G^6 G^5 G^3 G^1 H^6 H^5 H^3 H^1 I^1 44 Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet ispMACH 4064V/B/C/Z, 4128V/B/C/Z, 4256V/B/C Logic Signal Connections: 100-Pin TQFP (Cont.) Pin Number 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62* 63 64 65 66 67 68 69 70 71 72 73* 74 75 76 77* 78 79 80 81 82 Bank Number 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ispMACH 4064V/B/C/Z GLB/MC/Pad C1 C2 C3 VCCO (Bank 1) GND (Bank 1) C4 C5 C6 C7 GND TMS C8 C9 C10 C11 GND (Bank 1) C12 C13 C14 C15 I VCCO (Bank 1) D15 D14 D13 D12 GND (Bank 1) D11 D10 D9 D8 I TDO VCC GND I D7 D6 D5 D4 GND (Bank 1) ORP C^1 C^2 C^3 C^4 C^5 C^6 C^7 C^8 C^9 C^10 C^11 C^12 C^13 C^14 C^15 D^15 D^14 D^13 D^12 D^11 D^10 D^9 D^8 D^7 D^6 D^5 D^4 ispMACH 4128V/B/C/Z GLB/MC/Pad E2 E4 E6 VCCO (Bank 1) GND (Bank 1) E8 E10 E12 E14 GND TMS F0 F2 F4 F6 GND (Bank 1) F8 F10 F12 F13 I VCCO (Bank 1) G14 G12 G10 G8 GND (Bank 1) G6 G5 G4 G2 I TDO VCC GND I H13 H12 H10 H8 GND (Bank 1) ORP E^2 E^4 E^6 E^8 E^10 E^12 E^14 F^0 F^2 F^4 F^6 F^8 F^10 F^12 F^13 G^14 G^12 G^10 G^8 G^6 G^5 G^4 G^2 H^13 H^12 H^10 H^8 ispMACH 4256V/B/C GLB/MC/Pad I6 I10 I12 VCCO (Bank 1) GND (Bank 1) J2 J6 J10 J12 GND TMS K12 K10 K6 K2 GND (Bank 1) L12 L10 L6 L4 I VCCO (Bank 1) M4 M6 M10 M12 GND (Bank 1) N2 N6 N10 N12 I TDO VCC GND I O12 O10 O6 O2 GND (Bank 1) ORP I^3 I^5 I^6 J^1 J^3 J^5 J^6 K^6 K^5 K^3 K^1 L^6 L^5 L^3 L^2 M^2 M^3 M^5 M^6 N^1 N^3 N^5 N^6 O^6 O^5 O^3 O^1 - 45 Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet ispMACH 4064V/B/C/Z, 4128V/B/C/Z, 4256V/B/C Logic Signal Connections: 100-Pin TQFP (Cont.) Pin Number 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 *This pin is input only. Bank Number 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 ispMACH 4064V/B/C/Z GLB/MC/Pad VCCO (Bank 1) D3 D2 D1 D0/GOE1 CLK3/I CLK0/I VCC A0/GOE0 A1 A2 A3 VCCO (Bank 0) GND (Bank 0) A4 A5 A6 A7 ORP D^3 D^2 D^1 D^0 A^0 A^1 A^2 A^3 A^4 A^5 A^6 A^7 ispMACH 4128V/B/C/Z GLB/MC/Pad VCCO (Bank 1) H6 H4 H2 H0/GOE1 CLK3/I CLK0/I VCC A0/GOE0 A2 A4 A6 VCCO (Bank 0) GND (Bank 0) A8 A10 A12 A14 ORP H^6 H^4 H^2 H^0 A^0 A^2 A^4 A^6 A^8 A^10 A^12 A^14 ispMACH 4256V/B/C GLB/MC/Pad VCCO (Bank 1) P12 P10 P6 P2/OE1 CLK3/I CLK0/I VCC A2/GOE0 A6 A10 A12 VCCO (Bank 0) GND (Bank 0) B2 B6 B10 B12 ORP P^6 P^5 P^3 P^1 A^1 A^3 A^5 A^6 B^1 B^3 B^5 B^6 ispMACH 4128V/B/C Logic Signal Connections: 128-Pin TQFP ispMACH 4128V/B/C Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Bank Number 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GLB/MC/Pad GND TDI VCCO (Bank 0) B0 B1 B2 B4 B5 B6 GND (Bank 0) B8 B9 B10 B12 B13 B14 VCCO (Bank 0) C14 ORP B^0 B^1 B^2 B^4 B^5 B^6 B^8 B^9 B^10 B^12 B^13 B^14 C^14 46 Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet ispMACH 4128V/B/C Logic Signal Connections: 128-Pin TQFP (Cont.) ispMACH 4128V/B/C Pin Number 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 Bank Number 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 GLB/MC/Pad C13 C12 C10 C9 C8 GND (Bank 0) C6 C5 C4 C2 C0 VCCO (Bank 0) TCK VCC GND D14 D13 D12 D10 D9 D8 GND (Bank 0) VCCO (Bank 0) D6 D5 D4 D2 D1 D0 CLK1/I GND (Bank 1) CLK2/I VCC E0 E1 E2 E4 E5 E6 VCCO (Bank 1) GND (Bank 1) E8 E9 ORP C^13 C^12 C^10 C^9 C^8 C^6 C^5 C^4 C^2 C^0 D^14 D^13 D^12 D^10 D^9 D^8 D^6 D^5 D^4 D^2 D^1 D^0 E^0 E^1 E^2 E^4 E^5 E^6 E^8 E^9 47 Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet ispMACH 4128V/B/C Logic Signal Connections: 128-Pin TQFP (Cont.) ispMACH 4128V/B/C Pin Number 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 Bank Number 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 GLB/MC/Pad E10 E12 E14 GND TMS VCCO (Bank 1) F0 F1 F2 F4 F5 F6 GND (Bank 1) F8 F9 F10 F12 F13 F14 VCCO (Bank 1) G14 G13 G12 G10 G9 G8 GND (Bank 1) G6 G5 G4 G2 G0 VCCO (Bank 1) TDO VCC GND H14 H13 H12 H10 H9 H8 GND (Bank 1) ORP E^10 E^12 E^14 F^0 F^1 F^2 F^4 F^5 F^6 F^8 F^9 F^10 F^12 F^13 F^14 G^14 G^13 G^12 G^10 G^9 G^8 G^6 G^5 G^4 G^2 G^0 H^14 H^13 H^12 H^10 H^9 H^8 - 48 Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet ispMACH 4128V/B/C Logic Signal Connections: 128-Pin TQFP (Cont.) ispMACH 4128V/B/C Pin Number 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Bank Number 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GLB/MC/Pad VCCO (Bank 1) H6 H5 H4 H2 H1 H0/GOE1 CLK3/I GND (Bank 0) CLK0/I VCC A0/GOE0 A1 A2 A4 A5 A6 VCCO (Bank 0) GND (Bank 0) A8 A9 A10 A12 A14 ORP H^6 H^5 H^4 H^2 H^1 H^0 A^0 A^1 A^2 A^4 A^5 A^6 A^8 A^9 A^10 A^12 A^14 ispMACH 4128V and 4256V Logic Signal Connections: 144-Pin TQFP ispMACH 4128V Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 Bank Number 0 0 0 0 0 0 0 0 0 0 0 GLB/MC/Pad GND TDI VCCO (Bank 0) B0 B1 B2 B4 B5 B6 GND (Bank 0) B8 B9 B10 ORP B^0 B^1 B^2 B^4 B^5 B^6 B^8 B^9 B^10 ispMACH 4256V GLB/MC/Pad GND TDI VCCO (Bank 0) C12 C10 C8 C6 C4 C2 GND (Bank 0) D14 D12 D10 ORP C^6 C^5 C^4 C^3 C^2 C^1 D^7 D^6 D^5 49 Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet ispMACH 4128V and 4256V Logic Signal Connections: 144-Pin TQFP (Cont.) ispMACH 4128V Pin Number 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 Bank Number 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 GLB/MC/Pad B12 B13 B14 NC2 GND (Bank 0) NC 2 1 ispMACH 4256V GLB/MC/Pad D8 D6 D4 I2 NC I 2 1 ORP B^12 B^13 B^14 C^14 C^13 C^12 C^10 C^9 C^8 C^6 C^5 C^4 C^2 C^1 C^0 D^14 D^13 D^12 D^10 D^9 D^8 D^6 D^5 D^4 D^2 D^1 D^0 - ORP D^4 D^3 D^2 E^1 E^2 E^3 E^4 E^5 E^6 F^1 F^2 F^3 F^4 F^5 F^6 G^6 G^5 G^4 G^3 G^2 G^1 H^6 H^5 H^4 H^3 H^2 H^1 - VCCO (Bank 0) C14 C13 C12 C10 C9 C8 GND (Bank 0) C6 C5 C4 C2 C1 C0 VCCO (Bank 0) TCK VCC GND NC 2 VCCO (Bank 0) E2 E4 E6 E8 E10 E12 GND (Bank 0) F2 F4 F6 F8 F10 F12 VCCO (Bank 0) TCK VCC GND I 2 D14 D13 D12 D10 D9 D8 NC2 GND (Bank 0) VCCO (Bank 0) D6 D5 D4 D2 D1 D0 CLK1/I GND (Bank 1) CLK2/I G12 G10 G8 G6 G4 G2 I2 GND (Bank 0) VCCO (Bank 0) H12 H10 H8 H6 H4 H2 CLK1/I GND (Bank 1) CLK2/I 50 Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet ispMACH 4128V and 4256V Logic Signal Connections: 144-Pin TQFP (Cont.) ispMACH 4128V Pin Number 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 Bank Number 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 GLB/MC/Pad VCC E0 E1 E2 E4 E5 E6 VCCO (Bank 1) GND (Bank 1) E8 E9 E10 E12 E13 E14 NC2 GND TMS VCCO (Bank 1) F0 F1 F2 F4 F5 F6 GND (Bank 1) F8 F9 F10 F12 F13 F14 NC 2 ispMACH 4256V GLB/MC/Pad VCC I2 I4 I6 I8 I10 I12 VCCO (Bank 1) GND (Bank 1) J2 J4 J6 J8 J10 J12 I2 GND TMS VCCO (Bank 1) K12 K10 K8 K6 K4 K2 GND (Bank 1) L14 L12 L10 L8 L6 L4 I 2 ORP E^0 E^1 E^2 E^4 E^5 E^6 E^8 E^9 E^10 E^12 E^13 E^14 F^0 F^1 F^2 F^4 F^5 F^6 F^8 F^9 F^10 F^12 F^13 F^14 G^14 G^13 G^12 G^10 G^9 G^8 - ORP I^1 I^2 I^3 I^4 I^5 I^6 J^1 J^2 J^3 J^4 J^5 J^6 K^6 K^5 K^4 K^3 K^2 K^1 L^7 L^6 L^5 L^4 L^3 L^2 M^1 M^2 M^3 M^4 M^5 M^6 - GND (Bank 1)1 VCCO (Bank 1) NC2 G14 G13 G12 G10 G9 G8 GND (Bank 1) NC1 VCCO (Bank 1) I2 M2 M4 M6 M8 M10 M12 GND (Bank 1) 51 Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet ispMACH 4128V and 4256V Logic Signal Connections: 144-Pin TQFP (Cont.) ispMACH 4128V Pin Number 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 Bank Number 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GLB/MC/Pad G6 G5 G4 G2 G1 G0 VCCO (Bank 1) TDO VCC GND NC 2 ispMACH 4256V GLB/MC/Pad N2 N4 N6 N8 N10 N12 VCCO (Bank 1) TDO VCC GND I 2 ORP G^6 G^5 G^4 G^2 G^1 G^0 H^14 H^13 H^12 H^10 H^9 H^8 H^6 H^5 H^4 H^2 H^1 H^0 A^0 A^1 A^2 A^4 A^5 A^6 A^8 A^9 A^10 A^12 A^13 ORP N^1 N^2 N^3 N^4 N^5 N^6 O^6 O^5 O^4 O^3 O^2 O^1 P^6 P^5 P^4 P^3 P^2 P^1 A^1 A^2 A^3 A^4 A^5 A^6 B^1 B^2 B^3 B^4 B^5 H14 H13 H12 H10 H9 H8 NC2 GND (Bank 1) VCCO (Bank 1) H6 H5 H4 H2 H1 H0/GOE1 CLK3/I GND (Bank 0) CLK0/I VCC A0/GOE0 A1 A2 A4 A5 A6 VCCO (Bank 0) GND (Bank 0) A8 A9 A10 A12 A13 O12 O10 O8 O6 O4 O2 I2 GND (Bank 1) VCCO (Bank 1) P12 P10 P8 P6 P4 P2/GOE1 CLK3/I GND (Bank 0) CLK0/1 VCC A2/GOE0 A4 A6 A8 A10 A12 VCCO (Bank 0) GND (Bank 0) B2 B4 B6 B8 B10 52 Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet ispMACH 4128V and 4256V Logic Signal Connections: 144-Pin TQFP (Cont.) ispMACH 4128V Pin Number 143 144 Bank Number 0 GLB/MC/Pad A14 NC2 ORP A^14 ispMACH 4256V GLB/MC/Pad B12 I2 ORP B^6 - 1. For device migration considerations, these NC pins are GND pins for I/O banks in ispMACH 4128V devices. 2. For device migration considerations, these NC pins are input signal pins in ispMACH 4256V devices. ispMACH 4256V/B/C, 4384V/B/C, 4512V/B/C, Logic Signal Connections: 176-Pin TQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Bank Number 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ispMACH 4256V/B/C GLB/MC/Pad NC GND TDI VCCO (Bank 0) C14 C12 C10 C8 C6 C4 C2 C0 GND (Bank 0) D14 D12 D10 D8 D6 D4 D2 D0 VCCO (Bank 0) E0 E2 E4 E6 E8 E10 E12 E14 GND (Bank 0) F0 ORP C^7 C^6 C^5 C^4 C^3 C^2 C^1 C^0 D^7 D^6 D^5 D^4 D^3 D^2 D^1 D^0 E^0 E^1 E^2 E^3 E^4 E^5 E^6 E^7 F^0 ispMACH 4384V/B/C GLB/MC/Pad NC GND TDI VCCO (Bank 0) C14 C12 C10 C8 C6 C4 C2 C0 GND (Bank 0) E14 E12 E10 E8 E6 E4 E2 E0 VCCO (Bank 0) H0 H2 H4 H6 H8 H10 H12 H14 GND (Bank 0) J0 ORP C^7 C^6 C^5 C^4 C^3 C^2 C^1 C^0 E^7 E^6 E^5 E^4 E^3 E^2 E^1 E^0 H^0 H^1 H^2 H^3 H^4 H^5 H^6 H^7 J^0 ispMACH 4512V/B/C GLB/MC/Pad NC GND TDI VCCO (Bank 0) C14 C12 C10 C8 C6 C4 C2 C0 GND (Bank 0) G14 G12 G10 G8 G6 G4 G2 G0 VCCO (Bank 0) J0 J2 J4 J6 J8 J10 J12 J14 GND (Bank 0) N0 ORP C^7 C^6 C^5 C^4 C^3 C^2 C^1 C^0 G^7 G^6 G^5 G^4 G^3 G^2 G^1 G^0 J^0 J^1 J^2 J^3 J^4 J^5 J^6 J^7 N^0 53 Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet ispMACH 4256V/B/C, 4384V/B/C, 4512V/B/C, Logic Signal Connections: 176-Pin TQFP (Cont.) Pin Number 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 Bank Number 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 ispMACH 4256V/B/C GLB/MC/Pad F2 F4 F6 F8 F10 F12 F14 VCCO (Bank 0) TCK VCC NC NC NC GND G14 G12 G10 G8 G6 G4 G2 G0 GND (Bank 0) VCCO (Bank 0) H14 H12 H10 H8 H6 H4 H2 H0 GND CLK1/I GND (Bank 1) CLK2/I VCC I0 I2 I4 I6 ORP F^1 F^2 F^3 F^4 F^5 F^6 F^7 G^7 G^6 G^5 G^4 G^3 G^2 G^1 G^0 H^7 H^6 H^5 H^4 H^3 H^2 H^1 H^0 I^0 I^1 I^2 I^3 ispMACH 4384V/B/C GLB/MC/Pad J2 J4 J6 J8 J10 J12 J14 VCCO (Bank 0) TCK VCC NC NC NC GND (Bank 0) K14 K12 K10 K8 K6 K4 K2 K0 GND (Bank 0) VCCO (Bank 0) L14 L12 L10 L8 L6 L4 L2 L0 GND CLK1/I GND (Bank 1) CLK2/I VCC M0 M2 M4 M6 ORP J^1 J^2 J^3 J^4 J^5 J^6 J^7 K^7 K^6 K^5 K^4 K^3 K^2 K^1 K^0 L^7 L^6 L^5 L^4 L^3 L^2 L^1 L^0 M^0 M^1 M^2 M^3 ispMACH 4512V/B/C GLB/MC/Pad N2 N4 N6 N8 N10 N12 N14 VCCO (Bank 0) TCK VCC NC NC NC GND O14 O12 O10 O8 O6 O4 O2 O0 GND (Bank 0) VCCO (Bank 0) P14 P12 P10 P8 P6 P4 P2 P0 GND CLK1/I GND (Bank 1) CLK2/I VCC AX0 AX2 AX4 AX6 ORP N^1 N^2 N^3 N^4 N^5 N^6 N^7 O^7 O^6 O^5 O^4 O^3 O^2 O^1 O^0 P^7 P^6 P^5 P^4 P^3 P^2 P^1 P^0 AX^0 AX^1 AX^2 AX^3 54 Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet ispMACH 4256V/B/C, 4384V/B/C, 4512V/B/C, Logic Signal Connections: 176-Pin TQFP (Cont.) Pin Number 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 Bank Number 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ispMACH 4256V/B/C GLB/MC/Pad I8 I10 I12 I14 VCCO (Bank 1) GND (Bank 1) J0 J2 J4 J6 J8 J10 J12 J14 VCC NC GND TMS VCCO (Bank 1) K14 K12 K10 K8 K6 K4 K2 K0 GND (Bank 1) L14 L12 L10 L8 L6 L4 L2 L0 VCCO (Bank 1) M0 M2 M4 M6 ORP I^4 I^5 I^6 I^7 J^0 J^1 J^2 J^3 J^4 J^5 J^6 J^7 K^7 K^6 K^5 K^4 K^3 K^2 K^1 K^0 L^7 L^6 L^5 L^4 L^3 L^2 L^1 L^0 M^0 M^1 M^2 M^3 ispMACH 4384V/B/C GLB/MC/Pad M8 M10 M12 M14 VCCO (Bank 1) GND (Bank 1) N0 N2 N4 N6 N8 N10 N12 N14 VCC NC GND TMS VCCO (Bank 1) O14 O12 O10 O8 O6 O4 O2 O0 GND (Bank 1) AX14 AX12 AX10 AX8 AX6 AX4 AX2 AX0 VCCO (Bank 1) DX0 DX2 DX4 DX6 ORP M^4 M^5 M^6 M^7 N^0 N^1 N^2 N^3 N^4 N^5 N^6 N^7 O^7 O^6 O^5 O^4 O^3 O^2 O^1 O^0 AX^7 AX^6 AX^5 AX^4 AX^3 AX^2 AX^1 AX^0 DX^0 DX^1 DX^2 DX^3 ispMACH 4512V/B/C GLB/MC/Pad AX8 AX10 AX12 AX14 VCCO (Bank 1) GND (Bank 1) BX0 BX2 BX4 BX6 BX8 BX10 BX12 BX14 VCC NC GND TMS VCCO (Bank 1) CX14 CX12 CX10 CX8 CX6 CX4 CX2 CX0 GND (Bank 1) GX14 GX12 GX10 GX8 GX6 GX4 GX2 GX0 VCCO (Bank 1) JX0 JX2 JX4 JX6 ORP AX^4 AX^5 AX^6 AX^7 BX^0 BX^1 BX^2 BX^3 BX^4 BX^5 BX^6 BX^7 CX^7 CX^6 CX^5 CX^4 CX^3 CX^2 CX^1 CX^0 GX^7 GX^6 GX^5 GX^4 GX^3 GX^2 GX^1 GX^0 JX^0 JX^1 JX^2 JX^3 55 Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet ispMACH 4256V/B/C, 4384V/B/C, 4512V/B/C, Logic Signal Connections: 176-Pin TQFP (Cont.) Pin Number 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 Bank Number 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 ispMACH 4256V/B/C GLB/MC/Pad M8 M10 M12 M14 GND (Bank 1) N0 N2 N4 N6 N8 N10 N12 N14 VCCO (Bank 1) TDO VCC NC NC NC GND O14 O12 O10 O8 O6 O4 O2 O0 GND (Bank 1) VCCO (Bank 1) P14 P12 P10 P8 P6 P4 P2/GOE1 P0 GND CLK3/I GND (Bank 0) ORP M^4 M^5 M^6 M^7 N^0 N^1 N^2 N^3 N^4 N^5 N^6 N^7 O^7 O^6 O^5 O^4 O^3 O^2 O^1 O^0 P^7 P^6 P^5 P^4 P^3 P^2 P^1 P^0 ispMACH 4384V/B/C GLB/MC/Pad DX8 DX10 DX12 DX14 GND (Bank 1) FX0 FX2 FX4 FX6 FX8 FX10 FX12 FX14 VCCO (Bank 1) TDO VCC NC NC NC GND GX14 GX12 GX10 GX8 GX6 GX4 GX2 GX0 GND (Bank 1) VCCO (Bank 1) HX14 HX12 HX10 HX8 HX6 HX4 HX2/GOE1 HX0 GND CLK3/I GND (Bank 0) ORP DX^4 DX^5 DX^6 DX^7 FX^0 FX^1 FX^2 FX^3 FX^4 FX^5 FX^6 FX^7 GX^7 GX^6 GX^5 GX^4 GX^3 GX^2 GX^1 GX^0 HX^7 HX^6 HX^5 HX^4 HX^3 HX^2 HX^1 HX^0 ispMACH 4512V/B/C GLB/MC/Pad JX8 JX10 JX12 JX14 GND (Bank 1) NX0 NX2 NX4 NX6 NX8 NX10 NX12 NX14 VCCO (Bank 1) TDO VCC NC NC NC GND OX14 OX12 OX10 OX8 OX6 OX4 OX2 OX0 GND (Bank 1) VCCO (Bank 1) PX14 PX12 PX10 PX8 PX6 PX4 PX2/GOE1 PX0 GND CLK3/I GND (Bank 0) ORP JX^4 JX^5 JX^6 JX^7 NX^0 NX^1 NX^2 NX^3 NX^4 NX^5 NX^6 NX^7 OX^7 OX^6 OX^5 OX^4 OX^3 OX^2 OX^1 OX^0 PX^7 PX^6 PX^5 PX^4 PX^3 PX^2 PX^1 PX^0 - 56 Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet ispMACH 4256V/B/C, 4384V/B/C, 4512V/B/C, Logic Signal Connections: 176-Pin TQFP (Cont.) Pin Number 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 Bank Number 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ispMACH 4256V/B/C GLB/MC/Pad CLK0/I VCC A0 A2/GOE0 A4 A6 A8 A10 A12 A14 VCCO (Bank 0) GND (Bank 0) B0 B2 B4 B6 B8 B10 B12 B14 VCC ORP A^0 A^1 A^2 A^3 A^4 A^5 A^6 A^7 B^0 B^1 B^2 B^3 B^4 B^5 B^6 B^7 ispMACH 4384V/B/C GLB/MC/Pad CLK0/I VCC A0 A2/GOE0 A4 A6 A8 A10 A12 A14 VCCO (Bank 0) GND (Bank 0) B0 B2 B4 B6 B8 B10 B12 B14 VCC ORP A^0 A^1 A^2 A^3 A^4 A^5 A^6 A^7 B^0 B^1 B^2 B^3 B^4 B^5 B^6 B^7 ispMACH 4512V/B/C GLB/MC/Pad CLK0/I VCC A0 A2//GOE0 A4 A6 A8 A10 A12 A14 VCCO (Bank 0) GND (Bank 0) B0 B2 B4 B6 B8 B10 B12 B14 VCC ORP A^0 A^1 A^2 A^3 A^4 A^5 A^6 A^7 B^0 B^1 B^2 B^3 B^4 B^5 B^6 B^7 - ispMACH 4256V/B/C, 4384V/B/C, 4512V/B/C Logic Signal Connections: 256-Ball fpBGA Ball Number C3 B1 F5 D3 C1 C2 E3 D2 F6 D1 I/O Bank 0 0 0 0 0 0 0 0 0 0 ispMACH 4256V/B/C 128-I/O GLB/MC/Pad GND TDI VCCO (Bank 0) C14 C12 C10 C8 C6 C4 C2 C0 NC ORP C^7 C^6 C^5 C^4 C^3 C^2 C^1 C^0 ispMACH 4256V/B/C 160-I/O GLB/MC/Pad GND TDI VCCO (Bank 0) C9 C8 C7 C6 C5 C4 C3 C2 C1 ORP C^9 C^8 C^7 C^6 C^5 C^4 C^3 C^2 C^1 ispMACH 4384V/B/C GLB/MC/Pad VCC GND TDI VCCO (Bank 0) C14 C12 C10 C8 C6 C4 C2 C0 F6 ORP C^7 C^6 C^5 C^4 C^3 C^2 C^1 C^0 F^3 ispMACH 4512V/B/C GLB/MC/Pad VCC GND TDI VCCO (Bank 0) C14 C12 C10 C8 C6 C4 C2 C0 H0 ORP C^7 C^6 C^5 C^4 C^3 C^2 C^1 C^0 H^0 57 Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet ispMACH 4256V/B/C, 4384V/B/C, 4512V/B/C Logic Signal Connections: 256-Ball fpBGA (Cont.) Ball Number E2 E4 G5 E1 F2 F1 G1 G6 G4 H6 G3 H5 G2 H1 H2 H3 H4 J4 J3 J2 J1 K1 J5 K2 J6 K3 K4 L1 L2 M1 M2 N1 M3 M4 N2 I/O Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ispMACH 4256V/B/C 128-I/O GLB/MC/Pad NC NC NC NC GND (Bank 0) NC NC NC NC NC D14 D12 D10 D8 D6 D4 D2 D0 VCCO (Bank 0) E0 E2 E4 E6 E8 E10 E12 E14 NC NC NC NC NC GND (Bank 0) NC NC NC NC NC ORP D^7 D^6 D^5 D^4 D^3 D^2 D^1 D^0 E^0 E^1 E^2 E^3 E^4 E^5 E^6 E^7 ispMACH 4256V/B/C 160-I/O GLB/MC/Pad C0 NC NC NC VCCO (Bank 0) GND (Bank 0) NC NC NC D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 VCCO (Bank 0) GND (Bank 0) E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 NC NC NC GND (Bank 0) VCCO (Bank 0) NC NC NC F0 F1 ORP C^0 D^9 D^8 D^7 D^6 D^5 D^4 D^3 D^2 D^1 D^0 E^0 E^1 E^2 E^3 E^4 E^5 E^6 E^7 E^8 E^9 F^0 F^1 ispMACH 4384V/B/C GLB/MC/Pad F4 D6 D4 NC VCCO (Bank 0) GND (Bank 0) NC D2 D0 F2 F0 E14 E12 E10 E8 E6 E4 E2 E0 VCCO (Bank 0) GND (Bank 0) H0 H2 H4 H6 H8 H10 H12 H14 G0 G2 I14 I12 NC GND (Bank 0) VCCO (Bank 0) NC I10 I8 G4 G6 ORP F^2 D^3 D^2 D^1 D^0 F^1 F^0 E^7 E^6 E^5 E^4 E^3 E^2 E^1 E^0 H^0 H^1 H^2 H^3 H^4 H^5 H^6 H^7 G^0 G^1 I^7 I^6 I^5 I^4 G^2 G^3 ispMACH 4512V/B/C GLB/MC/Pad H4 F4 F6 F8 VCCO (Bank 0) GND (Bank 0) F10 F12 F14 H8 H12 G14 G12 G10 G8 G6 G4 G2 G0 VCCO (Bank 0) GND (Bank 0) J0 J2 J4 J6 J8 J10 J12 J14 I0 I4 K0 K2 K4 GND (Bank 0) VCCO (Bank 0) K6 K8 K10 I8 I12 ORP H^2 F^2 F^3 F^4 F^5 F^6 F^7 H^4 H^6 G^7 G^6 G^5 G^4 G^3 G^2 G^1 G^0 J^0 J^1 J^2 J^3 J^4 J^5 J^6 J^7 I^0 I^2 K^0 K^1 K^2 K^3 K^4 K^5 I^4 I^6 58 Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet ispMACH 4256V/B/C, 4384V/B/C, 4512V/B/C Logic Signal Connections: 256-Ball fpBGA (Cont.) Ball Number K5 P1 K6 N3 L5 P2 L6 R1 P3 T2 M5 N4 T3 R3 M6 P4 L7 N5 M7 P5 R4 T4 R5 T5 R6 T6 N7 P7 R7 L8 T7 M8 N8 R8 P8 I/O Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ispMACH 4256V/B/C 128-I/O GLB/MC/Pad F0 F2 F4 F6 F8 F10 F12 F14 VCCO (Bank 0) TCK VCC GND NC NC G14 G12 G10 G8 G6 G4 G2 G0 NC NC NC GND (Bank 0) VCCO (Bank 0) NC NC NC NC NC H14 H12 H10 H8 H6 H4 H2 H0 ORP F^0 F^1 F^2 F^3 F^4 F^5 F^6 F^7 G^7 G^6 G^5 G^4 G^3 G^2 G^1 G^0 H^7 H^6 H^5 H^4 H^3 H^2 H^1 H^0 ispMACH 4256V/B/C 160-I/O GLB/MC/Pad F2 F3 F4 F5 F6 F7 F8 F9 VCCO (Bank 0) TCK VCC GND GND (Bank 0) G9 G8 G7 G6 G5 G4 G3 G2 G1 G0 NC NC NC GND (Bank 0) VCCO (Bank 0) NC NC NC H9 H8 H7 H6 H5 H4 H3 H2 H1 H0 ORP F^2 F^3 F^4 F^5 F^6 F^7 F^8 F^9 G^9 G^8 G^7 G^6 G^5 G^4 G^3 G^2 G^1 G^0 H^9 H^8 H^7 H^6 H^5 H^4 H^3 H^2 H^1 H^0 ispMACH 4384V/B/C GLB/MC/Pad J0 J2 J4 J6 J8 J10 J12 J14 VCCO (Bank 0) TCK VCC GND GND (Bank 0) I6 I4 K14 K12 K10 K8 K6 K4 K2 K0 G8 G10 NC GND (Bank 0) VCCO (Bank 0) NC I2 I0 G12 G14 L14 L12 L10 L8 L6 L4 L2 L0 ORP J^0 J^1 J^2 J^3 J^4 J^5 J^6 J^7 I^3 I^2 K^7 K^6 K^5 K^4 K^3 K^2 K^1 K^0 G^4 G^5 I^1 I^0 G^6 G^7 L^7 L^6 L^5 L^4 L^3 L^2 L^1 L^0 ispMACH 4512V/B/C GLB/MC/Pad N0 N2 N4 N6 N8 N10 N12 N14 VCCO (Bank 0) TCK VCC GND GND (Bank 0) K12 K14 O14 O12 O10 O8 O6 O4 O2 O0 M0 M4 L0 GND (Bank 0) VCCO (Bank 0) L4 L8 L12 M8 M12 P14 P12 P10 P8 P6 P4 P2 P0 ORP N^0 N^1 N^2 N^3 N^4 N^5 N^6 N^7 K^6 K^7 O^7 O^6 O^5 O^4 O^3 O^2 O^1 O^0 M^0 M^2 L^0 L^2 L^4 L^6 M^4 M^6 P^7 P^6 P^5 P^4 P^3 P^2 P^1 P^0 59 Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet ispMACH 4256V/B/C, 4384V/B/C, 4512V/B/C Logic Signal Connections: 256-Ball fpBGA (Cont.) Ball Number T8 N9 P9 R9 T9 T10 R10 M9 P10 L9 N10 T11 R11 T12 N12 R12 T13 P12 M10 R13 L10 T14 M11 R14 P13 N13 M12 T15 P14 L12 R16 N14 I/O Bank 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ispMACH 4256V/B/C 128-I/O GLB/MC/Pad GND CLK1/I GND (Bank 1) CLK2/I VCC I0 I2 I4 I6 I8 I10 I12 I14 NC NC NC NC NC VCCO (Bank 1) GND (Bank 1) NC NC NC J0 J2 J4 J6 J8 J10 J12 J14 NC NC VCC GND TMS VCCO (Bank 1) NC NC NC ORP I^0 I^1 I^2 I^3 I^4 I^5 I^6 I^7 J^0 J^1 J^2 J^3 J^4 J^5 J^6 J^7 ispMACH 4256V/B/C 160-I/O GLB/MC/Pad GND CLK1/I GND (Bank 1) CLK2/I VCC I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 NC NC NC VCCO (Bank 1) GND (Bank 1) NC J0 J1 J2 J3 J4 J5 J6 J7 J8 J9 NC NC VCC GND GND (Bank 1) TMS VCCO (Bank 1) NC NC NC ORP I^0 I^1 I^2 I^3 I^4 I^5 I^6 I^7 I^8 I^9 J^0 J^1 J^2 J^3 J^4 J^5 J^6 J^7 J^8 J^9 ispMACH 4384V/B/C GLB/MC/Pad GND CLK1/I GND (Bank 1) CLK2/I VCC M0 M2 M4 M6 M8 M10 M12 M14 BX14 BX12 P0 P2 NC VCCO (Bank 1) GND (Bank 1) NC BX10 BX8 N0 N2 N4 N6 N8 N10 N12 N14 P4 P6 VCC GND GND (Bank 1) TMS VCCO (Bank 1) NC P8 P10 ORP M^0 M^1 M^2 M^3 M^4 M^5 M^6 M^7 BX^7 BX^6 P^0 P^1 BX^5 BX^4 N^0 N^1 N^2 N^3 N^4 N^5 N^6 N^7 P^2 P^3 P^4 P^5 ispMACH 4512V/B/C GLB/MC/Pad GND CLK1/I GND (Bank 1) CLK2/I VCC AX0 AX2 AX4 AX6 AX8 AX10 AX12 AX14 DX0 DX4 EX0 EX4 EX8 VCCO (Bank 1) GND (Bank 1) EX12 DX8 DX12 BX0 BX2 BX4 BX6 BX8 BX10 BX12 BX14 FX0 FX2 VCC GND GND (Bank 1) TMS VCCO (Bank 1) FX4 FX6 FX8 ORP AX^0 AX^1 AX^2 AX^3 AX^4 AX^5 AX^6 AX^7 DX^0 DX^2 EX^0 EX^2 EX^4 EX^6 DX^4 DX^6 BX^0 BX^1 BX^2 BX^3 BX^4 BX^5 BX^6 BX^7 FX^0 FX^1 FX^2 FX^3 FX^4 60 Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet ispMACH 4256V/B/C, 4384V/B/C, 4512V/B/C Logic Signal Connections: 256-Ball fpBGA (Cont.) Ball Number P15 L11 P16 K11 M14 K12 N15 N16 M15 M13 M16 L15 L16 J11 K15 J12 K13 K14 K16 J16 J15 H16 J13 J14 H15 H14 H13 G16 H12 G15 H11 F16 G13 G14 F15 E16 I/O Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ispMACH 4256V/B/C 128-I/O GLB/MC/Pad K14 K12 K10 K8 K6 K4 K2 K0 NC NC GND (Bank 1) NC NC NC NC NC L14 L12 L10 L8 L6 L4 L2 L0 VCCO (Bank 1) M0 M2 M4 M6 M8 M10 M12 M14 NC NC NC NC NC GND (Bank 1) ORP K^7 K^6 K^5 K^4 K^3 K^2 K^1 K^0 L^7 L^6 L^5 L^4 L^3 L^2 L^1 L^0 M^0 M^1 M^2 M^3 M^4 M^5 M^6 M^7 ispMACH 4256V/B/C 160-I/O GLB/MC/Pad K9 K8 K7 K6 K5 K4 K3 K2 K1 K0 VCCO (Bank 1) GND (Bank 1) NC NC NC L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 VCCO (Bank 1) GND (Bank 1) M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 NC NC NC GND (Bank 1) ORP K^9 K^8 K^7 K^6 K^5 K^4 K^3 K^2 K^1 K^0 L^9 L^8 L^7 L^6 L^5 L^4 L^3 L^2 L^1 L^0 M^0 M^1 M^2 M^3 M^4 M^5 M^6 M^7 M^8 M^9 ispMACH 4384V/B/C GLB/MC/Pad O14 O12 O10 O8 O6 O4 O2 O0 BX6 BX4 VCCO (Bank 1) GND (Bank 1) NC P12 P14 BX2 BX0 AX14 AX12 AX10 AX8 AX6 AX4 AX2 AX0 VCCO (Bank 1) GND (Bank 1) DX0 DX2 DX4 DX6 DX8 DX10 DX12 DX14 CX0 CX2 EX14 EX12 NC GND (Bank 1) ORP O^7 O^6 O^5 O^4 O^3 O^2 O^1 O^0 BX^3 BX^2 P^6 P^7 BX^1 BX^0 AX^7 AX^6 AX^5 AX^4 AX^3 AX^2 AX^1 AX^0 DX^0 DX^1 DX^2 DX^3 DX^4 DX^5 DX^6 DX^7 CX^0 CX^1 EX^7 EX^6 ispMACH 4512V/B/C GLB/MC/Pad CX14 CX12 CX10 CX8 CX6 CX4 CX2 CX0 HX0 HX4 VCCO (Bank 1) GND (Bank 1) FX10 FX12 FX14 HX8 HX12 GX14 GX12 GX10 GX8 GX6 GX4 GX2 GX0 VCCO (Bank 1) GND (Bank 1) JX0 JX2 JX4 JX6 JX8 JX10 JX12 JX14 IX0 IX4 KX0 KX2 KX4 GND (Bank 1) ORP CX^7 CX^6 CX^5 CX^4 CX^3 CX^2 CX^1 CX^0 HX^0 HX^2 FX^5 FX^6 FX^7 HX^4 HX^6 GX^7 GX^6 GX^5 GX^4 GX^3 GX^2 GX^1 GX^0 JX^0 JX^1 JX^2 JX^3 JX^4 JX^5 JX^6 JX^7 IX^0 IX^2 KX^0 KX^1 KX^2 - 61 Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet ispMACH 4256V/B/C, 4384V/B/C, 4512V/B/C Logic Signal Connections: 256-Ball fpBGA (Cont.) Ball Number E15 G12 E13 D16 E14 G11 D15 F11 C16 F12 D14 C15 B16 C14 A15 B14 E12 A14 C13 D13 E11 B13 F10 C12 E10 A13 D12 B12 A12 B11 A11 D10 C10 B10 I/O Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ispMACH 4256V/B/C 128-I/O GLB/MC/Pad NC NC NC NC NC N0 N2 N4 N6 N8 N10 N12 N14 VCCO (Bank 1) TDO VCC GND NC NC O14 O12 O10 O8 O6 O4 O2 O0 NC NC NC GND (Bank 1) VCCO (Bank 1) NC NC NC NC NC P14 P12 ORP N^0 N^1 N^2 N^3 N^4 N^5 N^6 N^7 O^7 O^6 O^5 O^4 O^3 O^2 O^1 O^0 P^7 P^6 ispMACH 4256V/B/C 160-I/O GLB/MC/Pad VCCO (Bank 1) NC NC NC N0 N1 N2 N3 N4 N5 N6 N7 N8 N9 VCCO (Bank 1) TDO VCC GND GND (Bank 1) NC NC O9 O8 O7 O6 O5 O4 O3 O2 O1 O0 NC GND (Bank 1) VCCO (Bank 1) NC NC NC P9 P8 P7 P6 ORP N^0 N^1 N^2 N^3 N^4 N^5 N^6 N^7 N^8 N^9 O^9 O^8 O^7 O^6 O^5 O^4 O^3 O^2 O^1 O^0 P^9 P^8 P^7 P6 ispMACH 4384V/B/C GLB/MC/Pad VCCO (Bank 1) NC EX10 EX8 CX4 CX6 FX0 FX2 FX4 FX6 FX8 FX10 FX12 FX14 VCCO (Bank 1) TDO VCC GND GND (Bank 1) EX6 EX4 GX14 GX12 GX10 GX8 GX6 GX4 GX2 GX0 CX8 CX10 NC GND (Bank 1) VCCO (Bank 1) NC EX2 EX0 CX12 CX14 HX14 HX12 ORP EX^5 EX^4 CX^2 CX^3 FX^0 FX^1 FX^2 FX^3 FX^4 FX^5 FX^6 FX^7 EX^3 EX^2 GX^7 GX^6 GX^5 GX^4 GX^3 GX^2 GX^1 GX^0 CX^4 CX^5 EX^1 EX^0 CX^6 CX^7 HX^7 HX^6 ispMACH 4512V/B/C GLB/MC/Pad VCCO (Bank 1) KX6 KX8 KX10 IX8 IX12 NX0 NX2 NX4 NX6 NX8 NX10 NX12 NX14 VCCO (Bank 1) TDO VCC GND GND (Bank 1) KX12 KX14 OX14 OX12 OX10 OX8 OX6 OX4 OX2 OX0 MX0 MX4 LX0 GND (Bank 1) VCCO (Bank 1) LX4 LX8 LX12 MX8 MX12 PX14 PX12 ORP KX^3 KX^4 KX^5 IX^4 IX^6 NX^0 NX^1 NX^2 NX^3 NX^4 NX^5 NX^6 NX^7 KX^6 KX^7 OX^7 OX^6 OX^5 OX^4 OX^3 OX^2 OX^1 OX^0 MX^0 MX^2 LX^0 LX^2 LX^4 LX^6 MX^4 MX^6 PX^7 PX^6 62 Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet ispMACH 4256V/B/C, 4384V/B/C, 4512V/B/C Logic Signal Connections: 256-Ball fpBGA (Cont.) Ball Number A10 A9 F9 B9 E9 C9 D9 B8 D8 C8 A8 A7 B7 E8 D7 F8 C7 A6 B6 A5 B5 D5 A4 E7 A3 F7 B4 C5 A2 E6 B3 C4 D4 E5 I/O Bank 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ispMACH 4256V/B/C 128-I/O GLB/MC/Pad P10 P8 P6 P4 P2/GOE1 P0 GND CLK3/I GND (Bank 0) CLK0/I VCC A0 A2/GOE0 A4 A6 A8 A10 A12 A14 NC NC NC NC NC VCCO (Bank 0) GND (Bank 0) NC NC NC B0 B2 B4 B6 B8 B10 B12 B14 NC NC VCC ORP P^5 P^4 P^3 P^2 P^1 P^0 A^0 A^1 A^2 A^3 A^4 A^5 A^6 A^7 B^0 B^1 B^2 B^3 B^4 B^5 B^6 B^7 ispMACH 4256V/B/C 160-I/O GLB/MC/Pad P5 P4 P3 P2 P1/GOE1 P0 GND CLK3/I GND (Bank 0) CLK0/I VCC A0 A1/GOE0 A2 A3 A4 A5 A6 A7 A8 A9 NC NC NC VCCO (Bank 0) GND (Bank 0) NC B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 NC NC VCC A^0 A^1 A^2 A^3 A^4 A^5 A^6 A^7 A^8 A^9 B^0 B^1 B^2 B^3 B^4 B^5 B^6 B^7 B^8 B^9 ORP P^5 P^4 P^3 P^2 P^1 P^0 ispMACH 4384V/B/C GLB/MC/Pad HX10 HX8 HX6 HX4 HX2/GOE1 HX0 GND CLK3/I GND (Bank 0) CLK0/I VCC A0 A2/GOE0 A4 A6 A8 A10 A12 A14 F14 F12 D14 D12 NC VCCO (Bank 0) GND (Bank 0) NC F10 F8 B0 B2 B4 B6 B8 B10 B12 B14 D10 D8 VCC GND ORP HX^5 HX^4 HX^3 HX^2 HX^1 HX^0 A^0 A^1 A^2 A^3 A^4 A^5 A^6 A^7 F^7 F^6 D^7 D^6 F^5 F^4 B^0 B^1 B^2 B^3 B^4 B^5 B^6 B^7 D^5 D^4 ispMACH 4512V/B/C GLB/MC/Pad PX10 PX8 PX6 PX4 PX2/GOE1 PX0 GND CLK3/I GND (Bank 0) CLK0/I VCC A0 A2/GOE0 A4 A6 A8 A10 A12 A14 D0 D4 E0 E4 E8 VCCO (Bank 0) GND (Bank 0) E12 D8 D12 B0 B2 B4 B6 B8 B10 B12 B14 F0 F2 VCC GND ORP PX^5 PX^4 PX^3 PX^2 PX^1 PX^0 A^0 A^1 A^2 A^3 A^4 A^5 A^6 A^7 D^0 D^2 E^0 E^2 E^4 E^6 D^4 D^6 B^0 B^1 B^2 B^3 B^4 B^5 B^6 B^7 F^0 F^1 - 63 Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet ispMACH 4256V/B/C, 4384V/B/C, 4512V/B/C Logic Signal Connections: 256-Ball fpBGA (Cont.) Ball Number I/O Bank 0 ispMACH 4256V/B/C 128-I/O GLB/MC/Pad ORP ispMACH 4256V/B/C 160-I/O GLB/MC/Pad ORP ispMACH 4384V/B/C GLB/MC/Pad GND (Bank 0) ORP ispMACH 4512V/B/C GLB/MC/Pad GND (Bank 0) ORP - Note: VCC, VCCO and GND are tied together to their respective common signal on the package substrate. See Power Supply and NC Connections table for VCC/ VCCO/GND pin definitions. 64 Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet Part Number Description LC XXXX X X – XX X XXX X X XX Device Family Device Number 4032 = 32 Macrocells 4064 = 64 Macrocells 4128 = 128 Macrocells 4256 = 256 Macrocells 4384 = 384 Macrocells 4512 = 512 Macrocells Power Z = Zero Power Blank = Low Power Supply Voltage V = 3.3V B = 2.5V C = 1.8V Speed 25 = 2.5ns 27 = 2.7ns 3 = 3.0ns 35 = 3.5ns 4 = 4.0ns 45 = 4.5ns 5 = 5.0ns 75 = 7.5ns 10 = 10.0ns Production Status Blank = Final production ES = Engineering Samples Grade C = Commercial I = Industrial E = Automotive I/O Designator (if applicable) A = 128 I/Os B = 160 I/Os Pin/Ball Count 44 (1.0mm thickness) 48 (1.0mm thickness) 56 100 128 132 144 176 256 Package T = TQFP F = fpBGA M = csBGA Ordering Information Note: ispMACH 4000 devices are all dual marked except the slowest commercial speed grade ispMACH 4000Z devices. For example, the commercial speed grade LC4128C-5T100C is also marked with the industrial grade -75I. The commercial grade is always one speed grade faster than the associated dual mark industrial grade. The slowest commercial speed grade ispMACH 4000Z devices are marked as commercial grade only. ispMACH 4000C (1.8V) Commercial Devices1 Device Part Number LC4032C-25T48C LC4032C-5T48C LC4032C LC4032C-75T48C LC4032C-25T44C LC4032C-5T44C LC4032C-75T44C Macrocells 32 32 32 32 32 32 Voltage 1.8 1.8 1.8 1.8 1.8 1.8 tPD 2.5 5 7.5 2.5 5 7.5 Package TQFP TQFP TQFP TQFP TQFP TQFP Pin/Ball Count 48 48 48 44 44 44 I/O 32 32 32 30 30 30 Grade C C C C C C 65 Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet ispMACH 4000C (1.8V) Commercial Devices1 (Cont.) Device Part Number LC4064C-25T100C LC4064C-5T100C LC4064C-75T100C LC4064C-25T48C Macrocells 64 64 64 64 64 64 64 64 64 128 128 128 128 128 128 256 256 256 256 256 256 256 256 256 256 256 256 384 384 384 384 384 384 512 512 512 512 512 512 Voltage 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 tPD 2.5 5 7.5 2.5 5 7.5 2.5 5 7.5 2.7 5 7.5 2.7 5 7.5 3 5 7.5 3 5 7.5 3 5 7.5 3 5 7.5 3.5 5 7.5 3.5 5 7.5 3.5 5 7.5 3.5 5 7.5 Package TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA TQFP TQFP TQFP TQFP TQFP TQFP fpBGA fpBGA fpBGA TQFP TQFP TQFP fpBGA fpBGA fpBGA TQFP TQFP TQFP Pin/Ball Count 100 100 100 48 48 48 44 44 44 128 128 128 100 100 100 256 256 256 256 256 256 176 176 176 100 100 100 256 256 256 176 176 176 256 256 256 176 176 176 I/O 64 64 64 32 32 32 30 30 30 92 92 92 64 64 64 128 128 128 160 160 160 128 128 128 64 64 64 192 192 192 128 128 128 208 208 208 128 128 128 Grade C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C LC4064C LC4064C-5T48C LC4064C-75T48C LC4064C-25T44C LC4064C-5T44C LC4064C-75T44C LC4128C-27T128C LC4128C-5T128C LC4128C-75T128C LC4128C-27T100C LC4128C-5T100C LC4128C-75T100C LC4256C-3F256AC LC4256C-5F256AC LC4256C-75F256AC LC4256C-3F256BC LC4256C-5F256BC LC4256C-75F256BC LC4256C-3T176C LC4256C-5T176C LC4256C-75T176C LC4256C-3T100C LC4256C-5T100C LC4256C-75T100C LC4384C-35F256C LC4384C-5F256C LC4384C-75F256C LC4384C-35T176C LC4384C-5T176C LC4384C-75T176C LC4512C-35F256C LC4512C-5F256C LC4512C-75F256C LC4512C-35T176C LC4512C-5T176C LC4512C-75T176C LC4128C LC4256C LC4384C LC4512C 66 Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet ispMACH 4000B (2.5V) Commercial Devices Device Part Number LC4032B-25T48C LC4032B-5T48C LC4032B-75T48C LC4032B-25T44C LC4032B-5T44C LC4032B-75T44C LC4064B-25T100C LC4064B-5T100C LC4064B-75T100C LC4064B-25T48C Macrocells 32 32 32 32 32 32 64 64 64 64 64 64 64 64 64 128 128 128 128 128 128 256 256 256 256 256 256 256 256 256 256 256 256 384 384 384 384 384 384 Voltage 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 tPD 2.5 5 7.5 2.5 5 7.5 2.5 5 7.5 2.5 5 7.5 2.5 5 7.5 2.7 5 7.5 2.7 5 7.5 3 5 7.5 3 5 7.5 3 5 7.5 3 5 7.5 3.5 5 7.5 3.5 5 7.5 Package TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA TQFP TQFP TQFP TQFP TQFP TQFP fpBGA fpBGA fpBGA TQFP TQFP TQFP Pin/Ball Count 48 48 48 44 44 44 100 100 100 48 48 48 44 44 44 128 128 128 100 100 100 256 256 256 256 256 256 176 176 176 100 100 100 256 256 256 176 176 176 I/O 32 32 32 30 30 30 64 64 64 32 32 32 30 30 30 92 92 92 64 64 64 128 128 128 160 160 160 128 128 128 64 64 64 192 192 192 128 128 128 Grade C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C LC4032B LC4064B LC4064B-5T48C LC4064B-75T48C LC4064B-25T44C LC4064B-5T44C LC4064B-75T44C LC4128B-27T128C LC4128B-5T128C LC4128B-75T128C LC4128B-27T100C LC4128B-5T100C LC4128B-75T100C LC4256B-3F256AC LC4256B-5F256AC LC4256B-75F256AC LC4256B-3F256BC LC4256B-5F256BC LC4256B-75F256BC LC4256B-3T176C LC4256B-5T176C LC4256B-75T176C LC4256B-3T100C LC4256B-5T100C LC4256B-75T100C LC4384B-35F256C LC4384B-5F256C LC4384B-75F256C LC4384B-35T176C LC4384B-5T176C LC4384B-75T176C LC4128B LC4256B LC4384B 67 Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet ispMACH 4000B (2.5V) Commercial Devices (Cont.) Device Part Number LC4512B-35F256C LC4512B-5F256C LC4512B-75F256C LC4512B-35T176C LC4512B-5T176C LC4512B-75T176C Macrocells 512 512 512 512 512 512 Voltage 2.5 2.5 2.5 2.5 2.5 2.5 tPD 3.5 5 7.5 3.5 5 7.5 Package fpBGA fpBGA fpBGA TQFP TQFP TQFP Pin/Ball Count 256 256 256 176 176 176 I/O 208 208 208 128 128 128 Grade C C C C C C LC4512B ispMACH 4000V (3.3V) Commercial Devices Device Part Number LC4032V-25T48C LC4032V-5T48C LC4032V LC4032V-75T48C LC4032V-25T44C LC4032V-5T44C LC4032V-75T44C LC4064V-25T100C LC4064V-5T100C LC4064V-75T100C LC4064V-25T48C LC4064V LC4064V-5T48C LC4064V-75T48C LC4064V-25T44C LC4064V-5T44C LC4064V-75T44C LC4128V-27T144C LC4128V-5T144C LC4128V-75T144C LC4128V-27T128C LC4128V LC4128V-5T128C LC4128V-75T128C LC4128V-27T100C LC4128V-5T100C LC4128V-75T100C Macrocells 32 32 32 32 32 32 64 64 64 64 64 64 64 64 64 128 128 128 128 128 128 128 128 128 Voltage 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 tPD 2.5 5 7.5 2.5 5 7.5 2.5 5 7.5 2.5 5 7.5 2.5 5 7.5 2.7 5 7.5 2.7 5 7.5 2.7 5 7.5 Package TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP Pin/Ball Count 48 48 48 44 44 44 100 100 100 48 48 48 44 44 44 144 144 144 128 128 128 100 100 100 I/O 32 32 32 30 30 30 64 64 64 32 32 32 30 30 30 96 96 96 92 92 92 64 64 64 Grade C C C C C C C C C C C C C C C C C C C C C C C C 68 Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet ispMACH 4000V (3.3V) Commercial Devices (Cont.) Device Part Number LC4256V-3F256AC LC4256V-5F256AC LC4256V-75F256AC LC4256V-3F256BC LC4256V-5F256BC LC4256V-75F256BC LC4256V-3T176C Macrocells 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 384 384 384 384 384 384 512 512 512 512 512 512 Voltage 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 tPD 3 5 7.5 3 5 7.5 3 5 7.5 3 5 7.5 3 5 7.5 3.5 5 7.5 3.5 5 7.5 3.5 5 7.5 3.5 5 7.5 Package fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP fpBGA fpBGA fpBGA TQFP TQFP TQFP fpBGA fpBGA fpBGA TQFP TQFP TQFP Pin/Ball Count 256 256 256 256 256 256 176 176 176 144 144 144 100 100 100 256 256 256 176 176 176 256 256 256 176 176 176 I/O 128 128 128 160 160 160 128 128 128 96 96 96 64 64 64 192 192 192 128 128 128 208 208 208 128 128 128 Grade C C C C C C C C C C C C C C C C C C C C C C C C C C C LC4256V LC4256V-5T176C LC4256V-75T176C LC4256V-3T144C LC4256V-5T144C LC4256V-75T144C LC4256V-3T100C LC4256V-5T100C LC4256V-75T100C LC4384V-35F256C LC4384V-5F256C LC4384V-75F256C LC4384V-35T176C LC4384V-5T176C LC4384V-75T176C LC4512V-35F256C LC4512V-5F256C LC4512V-75F256C LC4512V-35T176C LC4512V-5T176C LC4512V-75T176C LC4384V LC4512V ispMACH 4000ZC (Zero Power, 1.8V) Commercial Devices1 Device LC4032ZC Part Number LC4032ZC-35T48C LC4032ZC-5T48C LC4032ZC-75T48C 1. Preliminary information. Macrocells 32 32 32 Voltage 1.8 1.8 1.8 tPD 3.5 5 7.5 Package TQFP TQFP TQFP Pin/Ball Count 48 48 48 I/O 32 32 32 Grade C C C ispMACH 4000C (1.8V) Industrial Devices Family Part Number LC4032C-5T48I LC4032C-75T48I LC4032C LC4032C-10T48I LC4032C-5T44I LC4032C-75T44I LC4032C-10T44I Macrocells 32 32 32 32 32 32 Voltage 1.8 1.8 1.8 1.8 1.8 1.8 tPD 5 7.5 10 5 7.5 10 Package TQFP TQFP TQFP TQFP TQFP TQFP Pin/Ball Count 48 48 48 44 44 44 I/O 32 32 32 30 30 30 Grade I I I I I I 69 Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet ispMACH 4000C (1.8V) Industrial Devices (Cont.) Family Part Number LC4064C-5T100I LC4064C-75T100I LC4064C-10T100I LC4064C-5T48I Macrocells 64 64 64 64 64 64 64 64 64 128 128 128 128 128 128 256 256 256 256 256 256 256 256 256 256 256 256 384 384 384 384 384 384 512 512 512 512 512 512 Voltage 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 tPD 5 7.5 10 5 7.5 10 5 7.5 10 5 7.5 10 5 7.5 10 5 7.5 10 5 7.5 10 5 7.5 10 5 7.5 10 5 7.5 10 5 7.5 10 5 7.5 10 5 7.5 10 Package TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA TQFP TQFP TQFP TQFP TQFP TQFP fpBGA fpBGA fpBGA TQFP TQFP TQFP fpBGA fpBGA fpBGA TQFP TQFP TQFP Pin/Ball Count 100 100 100 48 48 48 44 44 44 128 128 128 100 100 100 256 256 256 256 256 256 176 176 176 100 100 100 256 256 256 176 176 176 256 256 256 176 176 176 I/O 64 64 64 32 32 32 30 30 30 92 92 92 64 64 64 128 128 128 160 160 160 128 128 128 64 64 64 192 192 192 128 128 128 208 208 208 128 128 128 Grade I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I LC4064C LC4064C-75T48I LC4064C-10T48I LC4064C-5T44I LC4064C-75T44I LC4064C-10T44I LC4128C-5T128I LC4128C-75T128I LC4128C-10T128I LC4128C-5T100I LC4128C-75T100I LC4128C-10T100I LC4256C-5F256AI LC4256C-75F256AI LC4256C-10F256AI LC4256C-5F256BI LC4256C-75F256BI LC4256C-10F256BI LC4256C-5T176I LC4256C-75T176I LC4256C-10T176I LC4256C-5T100I LC4256C-75T100I LC4256C-10T100I LC4384C-5F256I LC4384C-75F256I LC4384C-10F256I LC4384C-5T176I LC4384C-75T176I LC4384C-10T176I LC4512C-5F256I LC4512C-75F256I LC4512C-10F256I LC4512C-5T176I LC4512C-75T176I LC4512C-10T176I LC4128C LC4256C LC4384C LC4512C 70 Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet ispMACH 4000B (2.5V) Industrial Devices Family Part Number LC4032B-5T48I LC4032B-75T48I LC4032B-10T48I LC4032B-5T44I LC4032B-75T44I LC4032B-10T44I LC4064B-5T100I LC4064B-75T100I LC4064B-10T100I LC4064B-5T48I Macrocells 32 32 32 32 32 32 64 64 64 64 64 64 64 64 64 128 128 128 128 128 128 256 256 256 256 256 256 256 256 256 256 256 256 384 384 384 384 384 384 Voltage 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 tPD 5 7.5 10 5 7.5 10 5 7.5 10 5 7.5 10 5 7.5 10 5 7.5 10 5 7.5 10 5 7.5 10 5 7.5 10 5 7.5 10 5 7.5 10 5 7.5 10 5 7.5 10 Package TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA TQFP TQFP TQFP TQFP TQFP TQFP fpBGA fpBGA fpBGA TQFP TQFP TQFP Pin/Ball Count 48 48 48 44 44 44 100 100 100 48 48 48 44 44 44 128 128 128 100 100 100 256 256 256 256 256 256 176 176 176 100 100 100 256 256 256 176 176 176 I/O 32 32 32 30 30 30 64 64 64 32 32 32 30 30 30 92 92 92 64 64 64 128 128 128 160 160 160 128 128 128 64 64 64 192 192 192 128 128 128 Grade I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I LC4032B LC4064B LC4064B-75T48I LC4064B-10T48I LC4064B-5T44I LC4064B-75T44I LC4064B-10T44I LC4128B-5T128I LC4128B-75T128I LC4128B-10T128I LC4128B-5T100I LC4128B-75T100I LC4128B-10T100I LC4256B-5F256AI LC4256B-75F256AI LC4256B-10F256AI LC4256B-5F256BI LC4256B-75F256BI LC4256B-10F256BI LC4256B-5T176I LC4256B-75T176I LC4256B-10T176I LC4256B-5T100I LC4256B-75T100I LC4256B-10T100I LC4384B-5F256I LC4384B-75F256I LC4384B-10F256I LC4384B-5T176I LC4384B-75T176I LC4384B-10T176I LC4128B LC4256B LC4384B 71 Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet ispMACH 4000B (2.5V) Industrial Devices (Cont.) Family Part Number LC4512B-5F256I LC4512B-75F256I LC4512B-10F256I LC4512B-5T176I LC4512B-75T176I LC4512B-10T176I Macrocells 512 512 512 512 512 512 Voltage 2.5 2.5 2.5 2.5 2.5 2.5 tPD 5 7.5 10 5 7.5 10 Package fpBGA fpBGA fpBGA TQFP TQFP TQFP Pin/Ball Count 256 256 256 176 176 176 I/O 208 208 208 128 128 128 Grade I I I I I I LC4512B ispMACH 4000V (3.3V) Industrial Devices Family Part Number LC4032V-5T48I LC4032V-75T48I LC4032V LC4032V-10T48I LC4032V-5T44I LC4032V-75T44I LC4032V-10T44I LC4064V-5T100I LC4064V-75T100I LC4064V-10T100I LC4064V-5T48I LC4064V LC4064V-75T48I LC4064V-10T48I LC4064V-5T44I LC4064V-75T44I LC4064V-10T44I LC4128V-5T144I LC4128V-75T144I LC4128V-10T144I LC4128V-5T128I LC4128V LC4128V-75T128I LC4128V-10T128I LC4128V-5T100I LC4128V-75T100I LC4128V-10T100I Macrocells 32 32 32 32 32 32 64 64 64 64 64 64 64 64 64 128 128 128 128 128 128 128 128 128 Voltage 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 tPD 5 7.5 10 5 7.5 10 5 7.5 10 5 7.5 10 5 7.5 10 5 7.5 10 5 7.5 10 5 7.5 10 Package TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP Pin/Ball Count 48 48 48 44 44 44 100 100 100 48 48 48 44 44 44 144 144 144 128 128 128 100 100 100 I/O 32 32 32 30 30 30 64 64 64 32 32 32 30 30 30 96 96 96 92 92 92 64 64 64 Grade I I I I I I I I I I I I I I I I I I I I I I I I 72 Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet ispMACH 4000V (3.3V) Industrial Devices (Cont.) Family Part Number LC4256V-5F256AI LC4256V-75F256AI LC4256V-10F256AI LC4256V-5F256BI LC4256V-75F256BI LC4256V-10F256BI LC4256V-5T176I Macrocells 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 384 384 384 384 384 384 512 512 512 512 512 512 Voltage 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 tPD 5 7.5 10 5 7.5 10 5 7.5 10 5 7.5 10 5 7.5 10 5 7.5 10 5 7.5 10 5 7.5 10 5 7.5 10 Package fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP fpBGA fpBGA fpBGA TQFP TQFP TQFP fpBGA fpBGA fpBGA TQFP TQFP TQFP Pin/Ball Count 256 256 256 256 256 256 176 176 176 144 144 144 100 100 100 256 256 256 176 176 176 256 256 256 176 176 176 I/O 128 128 128 160 160 160 128 128 128 96 96 96 64 64 64 192 192 192 128 128 128 208 208 208 128 128 128 Grade I I I I I I I I I I I I I I I I I I I I I I I I I I I LC4256V LC4256V-75T176I LC4256V-10T176I LC4256V-5T144I LC4256V-75T144I LC4256V-10T144I LC4256V-5T100I LC4256V-75T100I LC4256V-10T100I LC4384V-5F256I LC4384V-75F256I LC4384V-10F256I LC4384V-5T176I LC4384V-75T176I LC4384V-10T176I LC4512V-5F256I LC4512V-75F256I LC4512V-10F256I LC4512V-5T176I LC4512V-75T176I LC4512V-10T176I LC4384V LC4512V ispMACH 4000V (3.3V) Automotive Devices Device LC4032V Part Number LC4032V-75T48E LC4032V-75T44E LC4064V-75T100E LC4064V LC4064V-75T48E LC4064V-75T44E LC4128V-75T144E LC4128V LC4128V-75T128E LC4128V-75T100E LC4256V-75T176E LC4256V LC4256V-75T144E LC4256V-75T100E Macrocells 32 32 64 64 64 128 128 128 256 256 256 Voltage 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 tPD 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 Package TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP Pin/Ball Count 48 44 100 48 44 144 128 100 176 144 100 I/O 32 30 64 32 30 96 92 64 128 96 64 Grade E E E E E E E E E E E 73 Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet For Further Information In addition to this data sheet, the following technical notes may be helpful when designing with the ispMACH 4000V/B/C/Z family: • ispMACH 4000 Timing Model Design and Usage Guidelines (TN1004) • ispMACH 4000V/B/C Power Consumption (TN1005) • Low Power Design Guide (TN1042) 74