ispMACH 4000ZE Pico Development Kit
User’s Guide
September 2009
Revision: EB47_01.0
ispMACH 4000ZE Pico Development Kit
User’s Guide
Lattice Semiconductor
Introduction
Thank you for choosing the Lattice Semiconductor ispMACH® 4000ZE Pico Development Kit!
This user’s guide describes how to start using the ispMACH 4000ZE Pico Development Kit, an easy-to-use platform for evaluating and designing with the LC4256ZE CPLD. Along with the evaluation board and accessories, this
kit includes a pre-loaded Pico Power demonstration design. You may also reprogram the on-board LC4256ZE and
ispPAC®-POWR6AT6 devices to review your own custom designs.
Note: Static electricity can severely shorten the lifespan of electronic components. See the ispMACH 4000ZE Pico
Development Kit QuickSTART Guide for handling and storage tips.
Features
The ispMACH 4000ZE Pico Development Kit includes:
• ispMACH 4000ZE Pico Evaluation Board - The Pico board is a 2.5” x 2” form factor that features the following
on-board components and circuits:
– ispMACH 4256ZE CPLD (LC4256ZE-5MN144C)
– Power Manager II ispPAC-POWR6AT6 mixed-signal PLD (ispPAC-POWR6AT6-01NN32I)
– High-side current sensor circuits
– Battery or USB power
– LCD panel
– USB B-mini connector for power and programming
– 15x2 expansion header landing for general IO, I2C, and JTAG
– Keyboard-style DIP switch bank
– Push-button input
– 3.3V and 1.8V supply rails
– Optional battery recharge circuit
• Pre-loaded Pico Power Demo – The kit includes a pre-loaded demo design that highlights key CPLD applications and power-saving design methods that maximize battery life.
• USB Connector Cable – The Pico board is powered from the mini B USB socket when connected to a host PC.
The USB channel also provides a programming interface to the LC4256ZE and POWR6AT6 JTAG ports.
• QuickSTART Guide – Provides information on connecting the Pico board, running the pre-loaded Pico Power
demo.
• ispMACH 4000ZE Pico Development Kit Web Page – The ispMACH 4000ZE Pico Development Kit web page
(www.latticesemi.com/4000ze-pico-kit) provides access to the latest documentation (including this guide), demo
designs, and drivers for the kit.
The contents of this user’s guide include demo operation, programming instructions, top-level functional descriptions of the evaluation board, descriptions of the on-board connectors, switches and a complete set of schematics
of the Pico board.
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Figure 1. Pico Evaluation Board, Top Side
Figure 2. Pico Evaluation Board, Bottom Side
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Software Requirements
Install the following software before you begin developing designs for the evaluation board:
• ispLEVER® Classic 1.3 (ispMACH 4000ZE CPLD support)
• PAC-Designer® 5.1 (ispPAC-POWR6AT6 mixed-signal PLD support)
• ispVM™ System 17.5 (Required for re-programming on-board PLDs)
• PicoView 1.04 (Required for the I2C GPIO Expansion Demo)
ispMACH 4000ZE Device
This board features the ispMACH 4000ZE CPLD which is ideal for ultra low-power, high-volume portable applications. The on-board LC4256ZE is the highest capacity of the family with 256 macrocells. The 144-pin csBGA package provides 108 user I/Os and four dedicated inputs in a 7mm x 7mm package. The LC4256ZE consumes
standby current as low as 15µA. A complete description of this device can be found in the ispMACH 4000ZE Family
Data Sheet.
Demonstration Designs
Lattice provides two demos that illustrate key applications of the ispMACH 4000ZE CPLD device in the context of a
consumer electronics application:
• Pico Power – Integrates an up/down counter, a right/left shift register, voltage/current meter display, and an I2C
bus master controller that communicates with the on-board POWR6AT6 Power Manager II device. The
POWR6AT6 provides analog power supply monitoring and a 2-wire I2C interface to measure various voltage supplies of the board. An LCD panel displays demo output using three characters. You can select demo features
with the keyboard-style 4-bit DIP switch bank. The Pico Power demo is designed for battery operation but if one
isn’t available you can power the board by connecting the USB cable provided to a PC USB port.
• GPIO I2C Expansion – Shows an application of the LC4256ZE device as an I2C slave processing instructions
issued by a CPU/MPU. CPLDs are ideal GPIO “expanders” for processors. Control registers of the CPLD’s I2C
module allow the processor to access counter and shift registers, I/O, and power measurements. An I2C software
interface utility, PicoView, emulates the CPU/MPU component of the system. Visit www.latticesemi.com/4000zepico-kit to download PicoView.
Note: It is possible that you will obtain your Pico board after it has been reprogrammed. To restore the factory
default demo and program it with other Lattice-supplied examples, see the Download Demo Designs section of this
document.
Pico Power Demo
The Pico Power design highlights low-power features of the LC4256ZE CPLD along with inexpensive PCB design
techniques that help extend battery life, such as low-speed CPLD clocking, efficient use of the CPLD I/O cell’s I/O
bus maintenance feature, and gated supply rails. The demo design integrates an I2C master reference design
(www.latticesemi.com/products/intellectualproperty) with LCD controller logic, an up/down counter and left/right
shift register modules. You may switch the LCD display between a current/voltage meter and counter/shifter operation using the DIP switch bank. The demo shows a clock generator based on the LC4256ZE on-chip oscillator and
timer (OSCTIMER) hardware feature. The counter and shift register modules can be clocked at either Scan Chain. The New Scan Configuration Setup window appears. The LC4256ZE and
POWR6AT6 device(s) appear in the device list.
5. Right-click the LC4256ZE or ispPAC-POWR6AT6 entry and choose Edit Device… The Device Information
dialog appears.
6. From the Data File section, click the Browse button. The Open Data File dialog appears.
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7. Browse to the \project folder, select .jed, and click Open. From the Operation list choose
Erase, Program, Verify and click OK.
Optional: Choose the Bypass operation for devices in the scan chain that don’t require re-programming.
8. Choose Project > Download. ispVM reprograms the evaluation board.
Programming requires about 20-40 seconds. A small, timer window will appear to show elapsed programming time.
At the end of programming, the configuration setup window should show a PASS in the Status column.
PicoView Software
This section describes the features of the PicoView for Windows software program.
Concepts
PicoView provides an easy-to-use interface to the I2C control and status registers within the GPIO I2C Expansion
demo design. PicoView communicates between a Windows PC and the Pico board using an I2C-over-USB connection.
PicoView issues I2C commands just as would an I2C master controller. You can view, and in many cases preload,
control registers prior to issuing a read or write command. To help understand the register set of the demo, see the
I2C GPIO Expansion Demo section and Figure 5 for more information.
Procedures
This section describes how to navigate the PicoView user interface.
Running PicoView
To run PicoView:
1. See the connection and programming procedure for the GPIO I2C Expansion demo to prepare the Pico board.
2. Download PicoView from www.latticesemi.com/4000ze-pico-kit and unzip the archive file. Picoview.exe is
unpacked.
3. From a Windows command prompt run: \Picoview.exe.
Setup
By default, PicoView is set to communicate between a PC and the Pico board over a USB cable. PicoView can also
be set up to operate in a demo mode without hardware. See the PicoView I2C Settings dialog for more information.
I2C Command Execution
To execute an I2C command:
1. From the PicoView Window, click a Control Register Button. A control register dialog box appears. A variety
of dialog styles are available depending on the register. See the User Interface section below for details.
2. Set the register options and click OK. The PicoView user interface will refresh with the updated register command in hex format.
3. Click the R (read) and W (write) buttons to update the register of the related I2C slave/peripheral register. The
PicoView user interface will refresh the status registers. In some cases the Pico board’s LCD operation will
change.
See the Run the I2C GPIO Expansion Demo section of this document for a PicoView operation example.
User Interface
This section describes elements contained within the PicoView graphical user interface. These elements include
windows, menus, toolbars, and dialog boxes.
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PicoView Window
The PicoView window provides access to control and status registers and a series or read or write actions that can
be issued by the I2C bus master module emulated by PicoView.
Figure 7. PicoView Window
Table 3. PicoView Window Buttons and Command Descriptions
Control Buttons
Button or I2C Master Command Description
I2C Address (ispMACH 4256ZE)
Open the PicoView Hex Entry dialog. Specify the hexadecimal value of the LC4256ZE
CPLD I2C bus address.
Control Register [R|W]
Open the PicoView Control Register dialog.
R – Read the current control register value and update the Control Register button display.
W – Write the current control register commands to the I2C slave peripherals.
Counter Register [R|W]
Open the PicoView Hex Entry dialog.
R – Read the counter value from the CPLD and update the Counter Register button display.
W – Write the counter pre-load value to the CPLD. The counter will begin counting up or
down from the preload value if it is not held in the Stop state. For more information about
counter controls, see the Pico View Control Register dialog.
Shift Register [R|W]
Open the PicoView Shift Register dialog.
R – Read the 21-bit shift register value from the CPLD and update the Shift Register button display.
W – Write the shift register pre-load value to the right-most 7-segment digit of the CPLD.
The shift register will shift the pattern left or right from the pre-load value if it is not held in
the Stop state. For more information about shift register controls, see the Pico View Control Register dialog.
General Purpose I/O
Open the PicoView General Purpose I/O Register
R – Read the 8-bit register value from the CPLD prototype GPIOs connected to the 15x2
expansion header landing.
W – Write the 8-bit register value specified to the CPLD prototype GPIOs.
POWR6AT6 Register
Display the current or voltage monitored by the POWR6AT6.
W – Issue a write command to display the POWR6AT6 register value to the LCD panel of
the Pico board.
DIP Switch
Display the value of the 4-bit DIP switch input as a hexadecimal value.
R – Read the DIP switch input.
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Table 3. PicoView Window Buttons and Command Descriptions (Continued)
I2C Address (ispPAC-POWR6AT6)
Open the PicoView Hex Entry dialog. Specify the hexadecimal value of the POWR6AT6
I2C bus address.
VMON1 – VMON6 radio buttons
Select the voltage monitor (VMON) to be read from the POWR6AT6 slave I2C peripheral.
Read (ispPAC-POWR6AT6)
Read the VMON specified and update the POWR6AT6 Register display.
About PicoView Dialog
Function: Report the PicoView version.
From the LCD Display section, specify which CPLD register the LCD will display.
PicoView Control Register Dialog
Function: Specify Counter/Shift Control mode and LCD Display.
Counter / Shift Control Option
Count Up/Shift Left
Count Down/Shift Right
Stop
Description
Specify the counter or shift register direction.
Pause the counter or shift register.
From the LCD Display section, specify which CPLD register the LCD will display.
PicoView General Purpose I/O Register dialog
Function: Specify the output value registered on the LC4256ZE Bank 1 GPIOs connected to the 15x2 expansion
header landing. See Figure 10 for details.
PicoView Hex Entry Dialog
Function: User interface keypad to enter a hexadecimal value. Appears when the Counter Register button is
pressed. Allows you to specify the pre-load value for the CPLD’s counter module.
PicoView I2C Settings Dialog
Function: Controls the I2C interface between the PC and Pico board.
Option
Description
Bypass Hardware Checking
Ignore USB connections. Used for demonstrations when a Windows PC with a USB port and Pico board is not available.
Enable Address Change of LC4245ZE
Enable to update how PicoView addresses the LC4256ZE.
Requires an updated LC4256ZE programming file.
I2C Clock Frequency
Select between I2C fast mode transfer rate at 400 kbit/s or 100
kbit/s.
PicoView Shift Register Dialog
Function: Specify the initial shift-register load pattern for the right-most 7-segment digit of the LCD panel.
ispMACH 4000ZE Pico Evaluation Board
This section describes the features of the ispMACH 4000ZE Pico evaluation board in detail.
Overview
The Pico board is a complete development platform for the LC4256ZE CPLD. The board includes a high-side current sensor circuit, a Power Manager II ispPAC-POWR6AT6 mixed-signal PLD, a USB program/power port, and an
expansion header landing to support test connections. The board is powered by a 3V battery or a PC’s USB port.
You may create or modify PLD program files using ispLEVER and PAC-Designer and reprogram the board using
ispVM software.
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Figure 8. ispMACH 4000ZE Pico Evaluation Board Block Diagram
10 GPIO
2X16
Header
Current
Sense Circuit
ispPACPOWR6AT6
2
4-bit DIP
Switch
14
3-char 7-seg
LCD
I2C
2
A/Mini-B
USB Cable
USB Mini-B
Socket
4
USB
Controller
I2C
ispMACH4256ZEMN144
JTAG
Programming
Table 4 describes the components on the board and the interfaces it supports.
Table 4. Pico Evaluation Board Components and Interfaces
Component/Interface
Type
Schematic Reference
Description
Circuits
Power Circuit
Circuit
Figure 11
5V USB, 3V battery, and optional lithium-ion
20mA charge circuit.
High-Side Current Sense
Circuit
Circuit
Figure 13
Resistive current sensor circuit to produce a
voltage level proportional to the current level
(see AN6049, High-side Current Sensing
Techniques for Power Manager Devices).
USB Controller
Circuit
U4:FT2232D
USB-to-JTAG interface and dual USB
UART/FIFO IC.
USB Mini B Socket
I/O
J1:USB_MINI_B
Programming and debug interface.
LC4256ZE
CPLD
U1: Lattice_4kZE
256-macrocell CPLD packaged in a 7 x 7mm,
144-ball chip-scale BGA.
POWR6AT6
Mixed Signal PLD
U6: ispPAC-POWR6AT6
Integrates analog DC-to-DC trim outputs,
analog monitor, power supply margin/trim
control, ADC, and I2C interface in a 32-ball
QFNS package.
LCD Panel
Output
U2: LUMEX-LCD2
3-character, 7-segment LCD panel.
15x2 Header Landing
I/O
J2:HEADER 15X2
User-definable I/O.
4-Bit DIP Switch
Input
SW2: SWDIP-4
General purpose 4-bit DIP switch.
Push-button Switch
Input
SW1:GlobalReset
General purpose push-button.
Components
Interfaces
Subsystems
This section describes the principle subsystems for the Pico board in alphabetical order.
Battery
A CR2032 watch cell battery provides a 3V supply rail for a portion of the Pico board and covers the LC4256ZE,
current sensor circuit, and LCD power requirements. As a power saving measure a power MOSFET circuit enables
the sensor circuit only upon measurement requests by the CPLD.
The Pico board can be populated by the user with a 20mA charger circuit for use with Li-Ion rechargable batteries
only. Do not try to recharge a standard CR2032 battery.
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Clock Sources
All clocks for the Pico Power and GPIO I2C demonstration designs originate from the LC4256ZE CPLD on-chip
oscillator and timer (OSCTIMER) block. You may use the expansion header landing to drive a CPLD input with an
external clock source.
Current Sensor Circuits
The board is populated with current sensor circuits connected to the VCC core and VCC I/O supply rails of the
LC4256ZE CPLD. For more information see AN6049, High-side Current Sensing Techniques for Power Manager
Devices.
DIP Switch
The evaluation board includes a 4-bit input piano button style switch located on the bottom-right corner of the
board. All four are available as general purpose inputs for the LC4256ZE.
Table 5. DIP Switch Reference
Item
Description
Reference Designators
SW2
Part Number
193-4MS
Manufacturer
CTS
Web Site
www.ctscorp.com
Table 6. DIP Switch Pin Information
SW2
Description
LC4256ZE Pin
1
SW0 Input
K11
2
SW1 Input
J12
3
SW2 Input
J11
4
SW3 Input
H10
Expansion Header Landing
The expansion header provides user GPIOs connected to the LC4256ZE, VMON and TRIM analog I/Os connected
to the POWR6AT6, and the on-board I2C/SMBus. The remaining pins serve as power supplies for external connections. The expansion connector is con• gured as one 2x15 100mil centered pin header.
Table 7. Expansion Connector Reference
Item
Description
Reference Designators
J2
Part Number
HEADER 15X2
Manufacturer
Molex/Waldom Electronics
Web Site
www.molex.com
Table 8. Expansion Header Pin Information
Pin
Number
Function
LC4256ZE
Pin
1
+3.1V
N/A
2
VCCIO_EXT
N/A
3
4K_TDI
TDI
4
USB_TDI
N/A
5
6AT6_TDO
N/A
6
USB_TDO
N/A
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7
4K_TCK
TCK
8
USB_TCK
N/A
9
4K_TMS
TMS
10
USB_TMS
N/A
11
PROTO_K7
K7
12
USB_SDA
N/A
13
PROTO_M7
M7
14
USB_SCL
n/a
15
PROTO_K4
K4
16
PROTO_L7
L7
17
PROTO_M3
M3
18
PROTO_L8
L8
19
PROTO_L4
L4
20
PROTO_M8
M8
21
PROTO_M4
M4
22
PROTO_M9
M9
23
PROTO_K3
K3
24
PROTO_L9
L9
25
CLK0_MACH
CLK0
26
PROTO_K8
K8
27
VMON_3
N/A
28
VMON_4
N/A
29
GND
N/A
30
GND
N/A
ispMACH4256ZE-MN144 CPLD
The ispMACH4256ZE-MN144 is a 144-ball csBGA package CPLD device which provides 108 I/Os and 4 dedicated
inputs in a 7 x 7mm package.
Table 9. LC4256ZE CPLD Interface Reference
Item
Description
Reference Designators
U1
Part Number
LC4256ZE
Manufacturer
Lattice Semiconductor
Web Site
www.latticesemi.com
JTAG Interface Circuits
For power and programming an FTDI USB UART/FIFO IC converter provides a communication interface between a
PC host and the JTAG programming chain of the Pico board. The USB 5V supply is also used as a source for the
3.3V and 1.8V supply rails. A USB B-type mini socket is provided for the USB connector cable.
Table 10. JTAG Interface Reference
Item
Description
Reference Designators
U4
Part Number
FT2232D
Manufacturer
FTDI (Future)
Web Site
www.ftdichip.com
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Table 11. JTAG Programming Pin Information
Description
LC4256ZE Pin
Test Data Output
B11:TDO / 4K_TDO
4:TDI / 6AT6_TDI
POWR6AT6 Pin/Net
Test Data Output
-
1:TDO / 6AT6_TDO
Test Data Input
A1:TDI / 4K_TDI
-
Test Mode Select
M12:TMS / 4K_TMS
5:TMS / 6AT6_TMS
Test Clock
L2:TCK / 4K_TCK
3:TCK / 6AT6_TCK
LCD
A 3-character, 7-segment LCD panel is provided for CPLD outputs.
Table 12. LCD Reference
Item
Description
Reference Designators
U2
Part Number
LCD-S301C31TR
Manufacturer
Lumex
Web Site
www.lumex.com
LED
A blue LED (POWR - D1) is used to indicate USB 5V power.
Table 13. User LEDs Reference
Item
Description
Reference Designators
D1
Part Number
LTST-C190CKT
Manufacturer
Lite-On
Web Site
www.liteonit.com
Power Manager II ispPAC-POWR6AT6
The ispPAC-POWR6AT6-01-SN32 Power Manager II device is a 32-ball QFNS package programmable mixed-signal PLD which provides an interface between the on-board current sensor circuit and the I2C interface bus. The
POWR6AT6 provides analog voltage monitors (VMON) and a 10-bit ADC to provide voltage measurements and an
I2C interface to the LC4256ZE CPLD. The 15x2 External Header Landing provides access to VMON3 and VMON4
inputs for experiments with external circuit monitoring.
Table 14. ProcessorPM PLD Reference
Item
Description
Reference Designators
U6
Part Number
ispPAC-POWR6AT6-01-SN32I
Manufacturer
Lattice Semiconductor
Web Site
www.latticesemi.com
Power Supply
Two optional power sources are provided depending on jumper settings. A 3.0V supply rail is provided from the battery and can power a subset of the board including the ispMACH 4000ZE, current sensor circuit, and LCD panel.
Alternatively 3.3V and 1.8V supply rails are converted from the USB 5V interface when the board is connected to a
host PC. The ispMACH4000ZE device will be isolated from other subsystems to accommodate accurate current/power measurements.
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Pushbutton Switch
The board has one momentary push-button switch (S1). You may use the switch as a user-defined input for your
own custom CPLD designs.
Table 15. Push-button Reference
Item
Description
Reference Designators
S1
Part Number
EVQ-Q2K03W
Manufacturer
Panasonic ECG
Web Site
www.panasonic.com/industrial/components/components.html
Table 16. Push-button Pin Information
Button
Description (Pre-Programmed Pico Power)
ProcessorPM Pin
S1
Pico board reset
H11
Test Points
In order to check the various voltage levels used, test points are provided:
• R35, VCC (CORE)
• R34, VCCIO of all banks
USB Programming and Debug Interface
The USB B-type Mini socket of the Pico board serves as the programming and debug interface.
JTAG Programming: For JTAG programming a preprogrammed USB PHY peripheral controller is provided on the
Pico board to serve as the programming interface to the ispMACH 4000ZE CPLD.
Programming requires the ispVM System software (www.latticesemi.com/ispvm). The programming connection will
appear to the ispVM System software as if a regular parallel-type ispDOWNLOAD™ cable is connected to the PC.
Modifying the Pico Board
The ispMACH 4000ZE Pico evaluation board provides landing areas for additional circuits to support the following
functions:
• Rechargeable Lithium-Ion 20 mA rechargeable battery
• 15x2 Header
Note: Modifying your board requires good electronics handling and PCB fabrication techniques to avoid damage.
Add Support for a Rechargeable Battery
The Pico board can be upgraded to support a Lithium-Ion rechargeable battery. When connected to a PC’s USB
port the battery circuit will recharge the battery cell. Install R23, R26, R42 and Q6 (Figure 11) to provide a 20mA
constant current charge.
15x2 Header
Install a 30-pin header at location J2 – HEADER 15x2 (Figure 10).
Mechanical Specifications
Dimensions: 2 ½ in. [L] x 2 in. [W] x 3/8 in. [H]
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Environmental Requirements
The evaluation board must be stored between -40°C and 100°C. The recommended operating temperature is
between 0°C and 90°C.
The evaluation board can be damaged without proper anti-static handling.
Glossary
CPLD: Complex Programmable Logic Device
DIP: Dual in-line package.
I2C: Inter-Integrated Circuit.
LED: Light Emitting Diode.
Mixed Signal PLD: A PLD integrated with analog and mixed signal support circuitry.
PCB: Printed Circuit Board.
RoHS: Restriction of Hazardous Substances Directive.
PLL: Phase Locked Loop.
SPI: Serial Peripheral Interface.
SRAM: Static Random Access Memory.
TransFR: Transparent Field Reconfiguration.
UART: Universal Asynchronous Receiver/Transmitter.
USB: Universal Serial Bus.
WDT: Watchdog timer
Troubleshooting
No Current/Voltage Meter Readings Available
A low battery can cause the current/voltage meter features of the Pico Power demo to read 0µA/0V. The demo’s
counter and shift register features may operate but the additional current required to energize the current sensor
and POWR6AT6 may not be available once the battery begins to discharge. Install a new battery if this condition
occurs.
Determine the Source of a Pre-Programmed Part
It is possible that you may receive your Pico board after it has been reprogrammed by someone else. To restore the
board to the factory default, see the Download Demo Designs for details on downloading and reprogramming the
device.
You can also determine which demo design is currently programmed onto the Pico board by comparing the JEDEC
checksums against of the programming file with what is read from the programmed part.
To compare JEDEC file checksum:
1. Connect the Pico board to a host PC using the USB port.
2. Start ispVM and choose ispTools > Scan. The POWR605 and POWR6AT6 devices appear in the Device List.
3. Double-click the device row. The Device Information dialog appears.
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4. Click the Browse button. The Save as Data File dialog appears.
5. Specify a new JEDEC Data File name and click the Save button.
6. From the Operation list choose Read and Save JEDEC and click OK.
7. Choose Project > Download. ispVM reads the contents from the device and writes the results to the JEDEC
file specified.
Open the JEDEC file into a text editor and page to the bottom of the file.
Note the hexidecimal checksum at the line above the User Electronic Data note line. Compare this value
against the checksum of the original JEDEC demo programming files.
Ordering Information
Description
Ordering Part Number
IspMACH 4000ZE Pico Development Kit
China RoHS Environment-Friendly
Use Period (EFUP)
LC4256ZE-P-EVN
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
+1-503-268-8001 (Outside North America)
e-mail: techsupport@latticesemi.com
Internet: www.latticesemi.com
Revision History
Date
Version
September 2009
01.0
Change Summary
Initial release.
© 2009 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as
listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of
their respective holders. The speci• cations and information herein are subject to change without notice.
22
23
A
B
C
D
U1A
VCC_IO
E4
F4
G4
J5
D5
C1
0.1uF
DI
Bank 0
A1
B2
B1
C3
C2
C1
D1
D2
D3
E1
E2
F2
D4
F1
F3
G1
E3
G2
G3
H1
H3
H2
J1
J3
J2
K1
K2
L1
L2
M1
K3
M2
L3
J4
K4
M3
L4
M4
L5
K5
J6
M5
K6
L6
A7
D6
B6
A6
C6
B5
A5
A4
B4
C5
A3
C4
B3
A2
C2
0.1uF
DI
n/c
n/c
n/c
n/c
4K_SDA
4K_SCL
LCD_A3
LCD_B3
LCD_C3
LCD_D3
LCD_E3
LCD_F3
LCD_G3
LCD_C2
LCD_D2
LCD_E2
LCD_F2
LCD_G2
LCD_DP1
LCD_A1
LCD_B1
LCD_C1
LCD_D1
LCD_E1
LCD_F1
LCD_G1
LCD_DP2
LCD_A2
LCD_B2
VCC_IO
4
PROTO_K4
PROTO_M3
PROTO_L4
PROTO_M4
PROTO_K3
BDBUS0
BDBUS1
BDBUS2
BDBUS3
BDBUS4
BDBUS5
BDBUS6
BDBUS7
5
4
Lattice Semiconductor : LC4256ZE-05MN144C
DI
PCB Footprint = CSBGA144
Lattice_4kZE
TDI
NC / IOB0 / IOC6
NC / IOB1 / IOC5
IOA8 / IOB2 / IOC4
IOA9 / IOB3 / IOC3
IOA10 / IOB4 / IOC2
IOA11 / IOB5 / IOC1
NC / NC / IOD7
NC / NC / IOD6
NC / IOB6 / IOD5
IOA12 / IOB7 / IOD4
IOA13 / IOB8 / IOD3
IOA14 / IOB9 / IOD2
IOA15 / IOB10 / IOD1
DI0 / IOB11 / IOD0
IOB15 / IOC11 / IOE0
IOB14 / IOC10 / IOE1
IOB13 / IOC9 / IOE2
IOB12 / IOC8 / IOE3
NC / IOC7 / IOE4
NC / IOC6 / IOE5
NC / NC / IOE6
IOB11 / IOC5 / IOF1
IOB10 / IOC4 / IOF2
ispMACH4000ZE
IOB9 / IOC3 / IOF3
144 csBGA
IOB8 / IOC2 / IOF4
Pin name sequence
DI1 / IOC1 / IOF5
(64,128,256)
NC / IOC0 / IOF6
TCK
NC / NC / IOG7
NC / NC / IOG6
NC / IOD11 / IOG5
DI2 / IOD10 / IOG4
IOB7 / IOD9 / IOG3
IOB6 / IOD8 / IOG2
IOB5 / IOD7 / IOG1
IOB4 / IOD6 / IOG0
NC / IOD5 / IOH6
NC / IOD4 / IOH5
IOB3 / IOD3 / IOH4
IOB2 / IOD2 / IOH3
IOB1 / IOD1 / IOH2
IOB0 / IOD0 / IOH1
CLK1*I
CLK0*I
IOA0*OE0 / IOA0*OE0 / IOA1*OE0
IOA1 / IOA1 / IOA2
IOA2 / IOA2 / IOA3
IOA3 / IOA3 / IOA4
NC / IOA4 / IOA5
NC / IOA5 / IOA6
IOA4 / IOA6 / IOB1
IOA5 / IOA7 / IOB2
IOA6 / IOA8 / IOB3
IOA7 / IOA9 / IOB4
NC / IOA10 / IOB5
NC / IOA11 / IOB6
NC / NC / IOB7
NC / VCCIO0 / VCCIO0
VCCIO0
NC / VCCIO0 / VCCIO0
VCCIO0
VCCIO0
5
4K_TCK
To FT chip
4K_TDI
R46
10k
DI
VCC_IO
R45
10k
DI
CLK0_MACH
3
COM_LCD
To Proto Pin
COM_LCD
3
4S1
4S2
3S1
3S2
2S1
2S2
1S1
1S2
U12
GND
1-2IN
3-4IN
D1
D2
D3
D4
VCC
DI
QFN16
STG3690QTR
11
13
7
9
3
5
15
1
LUMEX-LCD2
DI
Part#
LCD-S301C31TR
PCB Footprint = LUMEX301
C3
D3
E3
DP2
C2
D2
E2
DP1
C1
D1
E1
COM
U2
B3
A3
F3
G3
B2
A2
F2
G2
B1
A1
F1
G1
24
13
14
15
16
17
18
19
20
21
22
23
14
6
2
10
16
4
8
12
+3.1V
2
+3.3V
ENABLE_6AT6b
USB_SDA
USB_SCL
6AT6_SDA
6AT6_SCL
C35
0.1uF
DI
+3.1V
1
Project
ispMACH4000ZE Pico Board
Thursday, August 6, 2009
Size
B
Date:
1
Sheet
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
LCD_B3
LCD_A3
LCD_F3
LCD_G3
LCD_B2
LCD_A2
LCD_F2
LCD_G2
LCD_B1
LCD_A1
LCD_F1
LCD_G1
Title
4KZE Bank 0 and 3-Digit LCD
Need to draw foot print .100" apart holes DIP
size, 24 holes .713" wide. Total Glass size
1.21" long plus bump
12
9
LCD_DP2
LCD_C3
8
LCD_C2
11
7
LCD_D2
LCD_D3
6
LCD_E2
10
5
LCD_DP1
LCD_E3
4
3
LCD_D1
LCD_C1
2
LCD_E1
1
2
C
C
Schematic Rev
Board Rev
1
of 5
A
B
C
D
Lattice Semiconductor
ispMACH 4000ZE Pico Development Kit
User’s Guide
Appendix A. Schematics
Figure 9. ispMACH 4000ZE Bank 0 and 3-Digit LCD
24
A
B
C
Lattice_4kZE
CSBGA144
DI
C3
0.1uF
DI
SM/C_0402
5
Bank 1
CLK2*I
IOC0 / IOE0 / IOI1
IOC1 / IOE1 / IOI2
IOC2 / IOE2 / IOI3
IOC3 / IOE3 / IOI4
NC / IOE4 / IOI5
NC / IOE5 / IOI6
IOC4 / IOE6 / IOJ1
IOC5 / IOE7 / IOJ2
IOC6 / IOE8 / IOJ3
IOC7 / IOE9 / IOJ4
NC / IOE10 / IOJ5
NC / IOE11 / IOJ6
NC / NC / IOJ7
TMS
NC / IOF0 / IOK6
NC / IOF1 / IOK5
IOC8 / IOF2 / IOK4
IOC9 / IOF3 / IOK3
IOC10 / IOF4 / IOK2
IOC11 / IOF5 / IOK1
NC / NC / IOL7
NC / NC / IOL6
NC / IOF6 / IOL5
ispMACH4000ZE
IOC12 / IOF7 / IOL4
144 csBGA
Pin name sequence IOC13 / IOF8 / IOL3
IOC14 / IOF9 / IOL2
(64,128,256)
IOC15 / IOF10 / IOL1
DI3 / IOF11 / IOL0
IOD15 / IOG11 / IOM0
IOD14 / IOG10 / IOM1
IOD13 / IOG9 / IOM2
IOD12 / IOG8 / IOM3
NC / IOG7 / IOM4
NC / IOG6 / IOM5
NC / NC / IOM6
IOD11 / IOG5 / ION1
IOD10 / IOG4 / ION2
IOD9 / IOG3 / ION3
IOD8 / IOG2 / ION4
DI4 / IOG1 / ION5
NC / IOG0 / ION6
TDO
NC / NC / IOO7
NC / NC / IOO6
NC / IOH11 / IOO5
DI5 / IOH10 / IOO4
IOD7 / IOH9 / IOO3
IOD6 / IOH8 / IOO2
IOD5 / IOH7 / IOO1
IOD4 / IOH6 / IOO0
NC / IOH5 / IOP6
NC / IOH4 / IOP5
IOD3 / IOH3 / IOP4
IOD2 / IOH2 / IOP3
IOD1 / IOH1 / IOP2
IOD0*OE1 / IOH0*OE1 / IOP1*OE1
CLK3*I
U1B
J8
H9
G9
F9
D8
VCCIO1
NC / VCCIO1 / VCCIO1
VCCIO1
NC / VCCIO1 / VCCIO1
VCCIO1
D
VCC_IO
5
M6
K7
M7
L7
J7
n/c
L8
M8
M9
L9
K8
M10
L10
K9
M11
M12
L12
L11
K10
K12
J10
K11
J12
J11
H10
H12
G11
H11
G12
G10
F12
F11
E11
E12
D10
F10
D12
E10
D11
E9
n/c
C12
C11
B12
B11
A12
C10
B10
A11
D9
n/c
B9
C9
A10
A9
B8
C8
A8
D7
n/c
B7
C7
C4
0.1uF
DI
SW0
SW1
SW2
SW3
VCC_IO
4
4
DI
3
4
ENABLE_6AT6b
2
1
GlobalReset
S1
Part Number:EVQ Q2K03W
Panasonic SMD
PCB Footprint = SMT_SW
C5
0.1uF
DI
R11
100k
DI
VCCIO_EXT
PROTO_L8
PROTO_M8
PROTO_M9
PROTO_L9
PROTO_K8
PROTO_K7
PROTO_M7
PROTO_L7
3
4K_TDO
SW0
SW1
SW2
SW3
4K_TMS
VMON_4
VCCIO_EXT
USB_TDI
USB_TDO
USB_TCK
USB_TMS
USB_SDA
USB_SCL
R12
100k
DI
R13
100k
DI
VCCIO_EXT
R14
100k
DI
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
1
2
3
4
DI
SWDIP-4
SW2
HEADER 15X2
R15
100k
DI
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
J2
Note: Add jumpers in copper(on bottom - layer # 4).
At pins 1, 3, 5, 7, 9 of J2
Cut to modify the JTAG chain.
3
8
7
6
5
2
CT1934MS-ND
D4
1N4148
DI
2
Project
ispMACH4000ZE Pico Board
Thursday, August 6, 2009
Size
B
Date:
1
Sheet
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
Title
4KZE Bank 1, DIP SW, Expansion Header
4K_TDI
6AT6_TDO
4K_TCK
4K_TMS
PROTO_K7
PROTO_M7
PROTO_K4
PROTO_M3
PROTO_L4
PROTO_M4
PROTO_K3
CLK0_MACH
VMON_3
+3.1V
1
C
C
Schematic Rev
Board Rev
2
of 5
A
B
C
D
Lattice Semiconductor
ispMACH 4000ZE Pico Development Kit
User’s Guide
Figure 10. ispMACH 4000ZE Bank 1, DIP, SW, Expansion Header
A
B
C
D
C6
0.1uF
DI
5
C7
0.1uF
DI
R9
1M
DI
C36
1uF
DI
R43
1M
DI
SM/R_0603
R1
10k
DI
VCC_CORE
U1C
1.8V CORE
PWR_ENABLEb
C28
0.33uF
DI
+5V_USB
Q1
ispMACH4000ZE
144 csBGA
Pin name sequence
(64,128,256)
DI
IRLML6402PbF
Q3
IRLML6402PbF
DI
CSBGA144
DI
Lattice_4kZE
+1.8V
R20
4.7k
SM/R_0402
DI
+5V
4
C31
1uF
DI
IN
U10
SOT-223_checkpins
1
GND
CORE_CURRENT_L
DI
IN
OUT
GND
SOT-23 1
3
U11
2
C32
1uF
DI
+1.8V
MCP1703-1802E/CB
+3.1V -> +1.8V Rail
[check package pins/tab]
+3.1V
2
4
NCP1117
DI
OUT
TAB
C29
6.8uF
DI
SM/C_0402
3
+3.3V
R18
100k
DI
SM/R_0402
100
0.1%
R34
VCC_IO
2
IO_CURRENT_H
2
+3.1V
10k
DI
+5V
BT1
V-
1
Batt_Cell_Holder
Vbat+2
Vbat+
ENABLE_6AT6b
Q6
2N3906
DNI
R42
15
DNI
SM/R_0402
+5V
V_BATT
R23
4.2k
DNI
SM/R_0402
R26
1k
DNI
SM/R_0402
Optional Lithium-Ion
20mA charger
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
Q5
2N2222
DI
+3.1V
CR2032
Battery Clip
2
3
BATTERY
1
Project
ispMACH4000ZE Pico Board
Thursday, August 6, 2009
Size
B
Date:
1
Sheet
C
C
Schematic Rev
Board Rev
3
of 5
Title
USB 5V to 3.3V, 4KZE Power Rails 3.0V Batt, 1.8V Rail and Current Monitors
R4
10k
DI
R16
100k
DI
SM/R_0402
R17
100k
DI
Q2
IRLML6402PbF
DI
R3
To U7 sense for current
Thin signal traces
Direct path from R34 to U7
IO_CURRENT_L
SM/R_0603
DI
VCC_IO
I/O Current
DI
DI
VCCIO_EXT
+5V
+3.1V
G5
E-Friendly
DI
G6
WEEE
10k
DI
SM/R_0402
R2
Q4
IRF240
Board Logos
PWR_VCCJ
+3.3V
G4
Lattice Logo
D3
1N4148
DI
D2
1N4148
DI
VCCIO_EXT
To U7 sense for current
Thin signal traces or non load bearing copper pour
Direct path from R35 to U7
CORE_CURRENT_H
R35
50
0.1%
SM/R_0603
DI
3
C30
10uF
DI
SM/C_0402
Core Current
D1
Blue
SM/D_0603
DI
R27
1k
SM/R_0402
DI
+5V
+5.0V_USB_CABLE -> +3.3V Rail +3.3V_USB
1
3
1
4
1
5
H5
H8
E8
E5
VCC
VCC
VCC
VCC
GND
GNDIO0
GNDIO0
GND
GNDIO0
NC / GNDIO1 / GNDIO1
GNDIO1
GND
GNDIO1
GNDIO1
GND
GNDIO1
NC / GNDIO0 / GNDIO0
GNDIO0
25
F6
G5
H4
G6
H6
H7
J9
G7
G8
F8
F7
E7
E6
F5
A
B
C
D
Lattice Semiconductor
ispMACH 4000ZE Pico Development Kit
User’s Guide
Figure 11. USB 5V to 3.3V, ispMACH 4000ZE Power Rails 3.0V Batt, 1.8V Rail and Current Monitors
A
B
C
D
TYPE_B
J1
MH1
MH2
CASE
CASE
CASE
CASE
NC
GND
DD+
VCC
10
11
6
7
8
9
4
5
2
3
1
USB_MINI_B DI
5
USB Connection
+5V_USB
5
R19
DI
DI
100k
C24
10nF
SM/R_0402
R41 DI
R40 DI
SM/R_0402
C8
0.1uF
+5V_USB
27
27
C19
12pF
DI
8
7
6
5
DI
1
VCC
NC
ORG
GND
U3
C21
33pF
DI
2
CS
SK
DIN
DOUT
4
R5
10k
SM/R_0402
Digi-Key Part Number 497-5090-1-ND
1
2
3
4
XTAL_HCM49
6MHz
X1
C22
33pF
DI
M93C46-W
DI
SOIC-8
M93C46-WMN6TP Manuf:ST Micro
18pF = 12pF + Ground Plane ( 6pF )
SHLD_Debug
SM/C_0402
C23
10nF
DI
L1
Ferrite_bead
SM/R_0603
DI
+5V_USB
4
R24
DI
R44
1M
DI
2.2k
EECS
EESK
EEDATA
1k
1.5k
R25
C20
12pF
DI
R28
DI
R6
10k
DI
0.1uF
DI
0.1uF
DI
C27
33nF
DI
C34
C33
47
2
1
48
4
44
43
5
7
8
6
TEST
EEDATA
EESK
EECS
RESET#
XTOUT
XTIN
RSTOUT#
USBDP
USBDM
3V3OUT
C9
0.1uF
DI
3
R33
330
DI
+5V_USB
3
DI
TQFP-48
U4
FT2232D
PWREN#
SI/WUB
TXDENB#
SLEEPB#
RXLEDB#
TXLEDB#
TXDB
RXDB
RTSB#
CTSB#
DTRB#
DRSB#
DCDB#
RIB#
SI/WUA
TXDENA
SLEEPA#
RXLED#
TXLED#
41
26
30
29
28
27
40
39
38
37
36
35
33
32
10
15
13
12
11
0.1uF
DI
0.1uF
DI
TXDA
RXDA
RTSA#
CTSA#
DTRA#
DSRA#
DCDA#
RIA#
C11
24
23
22
21
20
19
17
16
+3.3V
C10
+3.3V
46
AVCC
AGND
3
42
VCC
VCC
45
14
31
VCCIOA
VCCIOB
GND
GND
GND
GND
26
9
18
25
34
2
C12
0.1uF
DI
2
14
6
2
10
16
4
8
12
3
2
1
RN1C
RN1B
RN1A
DNI
4S1
4S2
3S1
3S2
2S1
2S2
1S1
1S2
11
13
7
9
3
5
15
1
16
15
14
13
12
11
10
9
DI
QFN16
0
0
0
0
0
0
0
0
STG3690QTR
GND
1-2IN
3-4IN
D1
D2
D3
D4
VCC
U5
+3.1V
USB_SCL
1
Project
ispMACH4000ZE Pico Board
Thursday, August 6, 2009
Size
B
Date:
1
Sheet
C
C
Schematic Rev
Board Rev
4
of 5
PWR_ENABLEb
BDBUS7
BDBUS6
BDBUS5
BDBUS4
BDBUS3
BDBUS2
BDBUS1
BDBUS0
JTAG TO MACH-4KZE
and POWR6AT6
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
USB_TMS
USB_TDO
USB_TDI
USB_TCK
USB_SDA
Title
USB to JTAG and I2C for the 4KZE and 6AT6
5
4
RN1D
6
7
8
RN1E
RN1F
RN1G
RN1H
High = JTAG
Low = I2C
+3.1V
A
B
C
D
Lattice Semiconductor
ispMACH 4000ZE Pico Development Kit
User’s Guide
Figure 12. USB to JTAG and I2C for the ispMACH 4000ZE and ispPAC-POWR6AT6
27
A
B
C
6AT6_TDO
4K_TCK
V_BATT
ENABLE_6AT6b
BATTERY
4K_TMS
4K_TDO
+3.1V
ENABLE_6AT6b
IO_CURRENT_L
IO_CURRENT_H
CORE_CURRENT_L
CORE_CURRENT_H
+3.1V
5
4S1
4S2
3S1
3S2
2S1
2S2
1S1
1S2
GND
1-2IN
3-4IN
4S1
4S2
3S1
3S2
2S1
2S2
1S1
1S2
GND
1-2IN
3-4IN
D1
D2
D3
D4
VCC
DI
QFN16
STG3690QTR
11
13
7
9
3
5
15
1
C14
0.1uF
DI
DI
QFN16
U8
D1
D2
D3
D4
VCC
STG3690QTR
11
13
7
9
3
5
15
1
U7
C13
0.1uF
DI
6
2
10
16
4
8
12
14
6
2
10
16
4
8
12
14
PWR_VCC
+3.1V
+3.1V
R32
2k
0.1%
DI
R39
100
0.1%
DI
R38
100
0.1%
DI
4
R37
50
0.1%
DI
R36
50
0.1%
DI
4
6
5
DI
-
+
LMP7716
U9B
PWR_VCC
R31
2k
0.1%
DI
-
DI
+
2
B
V_BATT
6AT6_TMS
6AT6_TDI
7
A
1
C26
0.01uF
DI
R30
2k
0.1%
DI
PWR_VCC
3
LMP7716
U9A
8
4
8
4
D
5
C25
0.01uF
DI
R29
2k
0.1%
DI
C15
0.1uF
DI
3
+5V
VMON_4
VMON_3
IO_CURRENT
CORE_CURRENT
3
R7
10k
DI
6AT6_TCK
R10
10k
DNI
R8
10k
DI
PWR_VCC
4
5
3
1
6
7
8
15
14
17
16
19
18
21
20
23
22
25
24
U6
QFN32
DI
2
ispPAC-POWR6AT6
TDI
TMS
TCK
TDO
CLTENb
VPS0
VPS1
VMON1
VMON1GS
VMON2
VMON2GS
VMON3
VMON3GS
VMON4
VMON4GS
VMON5
VMON5GS
VMON6
VMON6GS
2
32
10
11
9
26
27
28
29
30
31
12
13
2
R21
1.5k
DI
C16
0.1uF
DI
SM/C_0402
R22
1.5k
DI
C17
0.1uF
DI
SM/C_0402
Project
ispMACH4000ZE Pico Board
Thursday, August 6, 2009
Size
B
Date:
1
Sheet
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
NC
NC
NC
NC
NC
NC
NC
PWR_VCCJ
Title
Power Manager 6AT6 and Current Sense Amplifiers
GND
SCL
SDA
CLTLOCK/SMBA
DAC6
DAC5
DAC4
DAC3
DAC2
DAC1
VCCD
VCCA
VCCJ
PWR_VCCJ
1
C
C
Schematic Rev
Board Rev
5
of 5
6AT6_SCL
6AT6_SDA
C18
0.1uF
DI
SM/C_0402
PWR_VCC
A
B
C
D
Lattice Semiconductor
ispMACH 4000ZE Pico Development Kit
User’s Guide
Figure 13. ispPAC-POWR6AT6 and Current Sense Amplifiers
ispMACH 4000ZE Pico Development Kit
User’s Guide
Lattice Semiconductor
Appendix B. Bill of Materials
Table 17. Bill of Materials
Item
Quantity
Reference
Part Number
1
2
C19, C20
ECJ-0EC1H120J
2
2
C21, C22
ECJ-0EC1H330J
3
4
C23, C24, C25, C26
ECJ-0EB1E103K
4
1
C27
ECJ-0EB1A333K
5
21
C1-C18, C33, C34, C35
ECJ-0EX1C104K
6
1
C28
GRM155R61A334KE15D
7
3
C31, C32, C36
ECJ-0EB1A105M
8
1
C29
TAJA685K020RNJ
9
1
C30
F920J106MPA
10
0
11
0
R42
ERJ-3EKF15R0V
12
2
R40, R41
ERJ-2GEJ270X
13
2
R36, R37
RG1005P-49R9-B-T5
14
1
R35
TNPW060349R9BEEA
15
4
R38, R39
ERA-2AEB101X
16
2
R34
ERA-3AEB101V
17
1
R33
ERJ-2GEJ331X
18
4
R29-R32
ERA-2AEB202X
19
2
R27, R28
ERJ-2GEJ102X
20
0
R26
ERJ-3EKF1001V
21
3
R21, R22, R25
ERJ-2GEJ152X
22
1
R24
ERJ-2GEJ222X
23
0
R23
ERJ-3EKF4221V
24
1
R20
ERJ-2RKF4701X
25
10
R1-R8, R45, R46
ERJ-2GEJ103X
26
0
R10
ERJ-3EKF1002V
27
9
R11-R19
ERJ-2GEJ104X
28
3
R9, R43, R44
ERJ-2GEJ105X
29
1
RN1
EXB-2HVR000V
30
1
L1
MI0603J600R-00
31
1
J1
UX60-MB-5ST
32
1
J2
90131-0800
33
1
U1
MACH4ZE LC4256ZE-05MN144C
34
1
U2
LCD-S301C31TR
35
1
U3
M93C46_WMN6TP
36
1
U4
FT2232D_R
37
4
U5, U7, U8, U12
STG3690QTR
38
1
U6
ISPPAC-POWR6AT6_QFN
39
1
U9
LMP7716MM/NOPB
40
1
U10
NCP1117ST33T3G
41
1
U11
MCP1703T-1802E/CB
42
1
S1
Push-Button SW SMD Tactile Raised White
CRT0603-BY-10R0ELF
28
ispMACH 4000ZE Pico Development Kit
User’s Guide
Lattice Semiconductor
Table 17. Bill of Materials (Continued)
43
1
SW2
193-4MS
44
3
Q1, Q2, Q3
IRLML6402PBF
45
1
Q5
MMBT2222LT1G
46
1
Q4
IRLML2502TRPBF
47
0
Q6
MMBT3906LT1G
48
1
X1
HCM49 6.000MABJ-UT
49
1
D1
LTST-C190TBKT
50
3
D2, D3, D4
1N4148W-TP
51
1
BT1
BATHLD001
52
1
CR2032
53
3
SJ61A3
Notes:
1. Quantity 0 (zero) indicates an optional component. See the Modifying the Pico Board section for more information.
29
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