ispXPLD™ Evaluation Board
User’s Guide
October 2003
ebug02_01
Lattice Semiconductor
ispXPLD Evaluation Board User’s Guide
Introduction
The ispXPLD Evaluation Board is a platform to evaluate the Lattice ispXPLD device. The board features a 512macrocell ispXPLD device. Connectors are provided to access general purpose I/Os. Termination is provided for
selected I/Os for LVDS operation.
Features
• Power management provided via Lattice ispPAC® Power Manager device
• On-board 20MHz oscillator
• Multiple integrated Low Drop-Out (LDO) regulators provide power from single 5V supply
• Labeled test-points allow current measurement of each individual supply
• ispVM™ programming support
• Jumperless implementation
• ispDOWNLOAD® Cable (pDS4102-DL2) included
Figure 1. ispXPLD Evaluation Board
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Lattice Semiconductor
ispXPLD Evaluation Board User’s Guide
Electrical, Mechanical and Environmental Specifications
The nominal board dimensions are 4.5 inches by 5 inches. The environmental specifications are as follows:
• Operating temperature: 0°C to 55°C
• Storage temperature: -40°C to 75°C
• Humidity: < 95% without condensation
• 5VDC input, accessible via banana jacks or the included 5V, 4A AC adapter
Holes are included at the corners of the PCB to provide attachment of vertical stand-offs. The pads at these holes
are electrically floating.
Resources relating to the ispXPLD evaluation board, including a simple demonstration design, can be found on the
Lattice web site at www.latticesemi.com.
Table 1. Embedded Functions
Description
Source
20MHz clock
On-board oscillator
Reset
ispPAC device
ispXPLD Pin
Notes
GCLK0 (H2)
3.3V TTL output
Global RST (J11) AND I/O pin R9 Active low by default, programmable via ispPAC
ispPAC-POWR1208 Power Manager Device
The Power Manager device controls the sequencing and monitoring of the various independent power supplies
available on the ispXPLD board. Each supply can be activated in stages, with programmable delay increments. As
the Power Manager device enables each LDO, a corresponding LED deactivates for visual confirmation.
The Power Manager design and JEDEC files can be downloaded from the Latttice web site. The device is shipped
preprogrammed with this default configuration.
For a complete description of the operation of the ispPAC-POWR1208 device and the default design used on this
board, refer to the ispPAC-POWR1208 data sheet and PAC-Designer® documentation (PAC-Designer is the design
software for the ispPAC-POWR1208). These are available on the Lattice web site at www.latticesemi.com.
VCCO Configurations
The ispXPLD device supports multiple I/O standards, and features individual I/O bank supply pins for simultaneous
support of different interfaces. The ispXPLD evaluation board is set by default to supply 2.5V to all I/O banks. This
is adjustable via the addition of resistors. For alternate supply levels, specific resistor values can be installed as
described in Figure 2.
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Lattice Semiconductor
ispXPLD Evaluation Board User’s Guide
Figure 2. I/O Voltage Adjustments
From LDO Output
R Fixed TOP
R User TOP
R Fixed BOT
R User BOT
To LDO FB
User-installable
voltage set resistors
Table 2. VCCOX LDO Adjustments
VCCOX
R Fixed TOP
R Fixed BOT
R User TOP
R User BOT
2.5V
127.0K
110.0K
DNP
DNP
3.3V
127.0K
110.0K
DNP
200.0K
1.8V
127.0K
110.0K
110.0K
DNP
1.5V
127.0K
110.0K
402K
DNP
Resistor numbers and physical locations can be found in the schematic and bottom silkscreen drawing, in Appendix B of this document.
Switches
One push-button reset switch (SW1) is provided to force a reset of the ispPAC-POWR1208 device. When this
switch is activated, the power-up cycle of the ispPAC-POWR1208 device is re-started. This, in turn, cycles power to
the rest of the board. The ispXPLD device contains power-on reset circuitry, for predicable initialization.
Programming Headers
Separate 1x8 headers are provided to allow independent configuration of the ispXPLD and ispPAC devices. Pin 1
of both headers is VCC (red wire from download cable). Table 3 shows the programming header locations.
Table 3. Programming Connectors
Connector
Target Device
JTAG Connector P1
ispPAC-POWR1208
JTAG Connector P2
ispXPLD
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Lattice Semiconductor
ispXPLD Evaluation Board User’s Guide
I/O Connectors
Connectivity for general-purpose I/O pins is provided by both 2mm DIP headers and Mictor connectors on the
underside of the board. Tables 4 through 7 provide locations for the ispXPLD I/Os.
Table 4. I/O Bank 0
P4 (2mm)
J4 (Mictor)
Description
ispXPLD
Pin
Notes
Unpopulated Series Resistor for 2mm Header
1
1
GCLK0
H2
2
2
GND
-
3
3
M30_91N_IOB0_LVD
B7
100-ohm LVDS Termination
4
4
M26_92N_IOB0_LVD
D7
100-ohm LVDS Termination
5
5
M28_91P_IOB0_LVD
A7
100-ohm LVDS Termination
6
6
M24_92P_IOB0_LVD
C7
100-ohm LVDS Termination
7
7
M22_93N_IOB0_LVD
B6
100-ohm LVDS Termination
8
8
M20_94N_IOB0_LVD
E6
100-ohm LVDS Termination
9
9
M21_93P_IOB0_LVD
E7
100-ohm LVDS Termination
10
10
M18_94P_IOB0_LVD
A6
100-ohm LVDS Termination
11
11
M10_96P_IOB0_LVD
A3
100-ohm LVDS Termination
12
12
M6_97P_IOB0_LVD
B3
100-ohm LVDS Termination
13
13
M12_96N_IOB0_LVD
B5
100-ohm LVDS Termination
14
14
M8_97N_IOB0_LVD
B4
100-ohm LVDS Termination
15
15
M4_98P_IOB0_LVD
C6
100-ohm LVDS Termination
16
16
M0_99P_IOB0_LVD
D6
100-ohm LVDS Termination
17
17
M5_98N_IOB0_LVD
C5
100-ohm LVDS Termination
18
18
M2_99N_IOB0_LVD
D5
100-ohm LVDS Termination
19
19
N4_107P_IOB0_LVD
B2
100-ohm LVDS Termination
20
20
112P_IOB0_LVDT
D2
21
21
M5_107N_IOB0_LVD
A2
22
22
112N_IOB0_LVDT
E3
23
-
GND
-
24
-
GND
-
25
25
117P_IOB0_LVDT
E1
26
26
118P_IOB0_LVDT
F5
27
29
117N_IOB0_LVDT
D1
28
28
118N_IOB0_LVDT
F4
29
29
119P_IOB0_LVDT
F2
30
30
120P_IOB0_LVDT
G1
31
31
119N_IOB0_LVDT
E2
32
32
120N_IOB0_LVDT
F1
33
33
121P_IOB0_LVDT
G5
34
34
122P_IOB0_LVDT
G4
35
35
121N_IOB0_LVDT
F3
36
36
122N_IOB0_LVDT
H5
37
37
123P_IOB0_LVDT
H3
38
-
124P_IOB0_LVDT
H1
39
38
123N_IOB0_LVDT
G3
5
100-ohm LVDS Termination
Lattice Semiconductor
ispXPLD Evaluation Board User’s Guide
Table 4. I/O Bank 0 (Continued)
P4 (2mm)
J4 (Mictor)
Description
ispXPLD
Pin
40
-
124N_IOB0_LVDT
G2
41
-
O24_110P_IOB0
C1
42
-
GND
-
43
-
O24_110N_IOB0
B1
44
-
M14_95P_IOB0
A4
45
-
O24_109P_IOB0
E4
46
-
O20_111P_IOB0
C2
47
-
O24_109N_IOB0
C4
48
-
O22_111N_IOB0
D3
49
-
GND
-
50
-
GND
-
Notes
Table 5. I/O Bank 1
P5(2mm)
J5(Mictor)
Description
ispXPLD
Pin
1
1
GCLK1
J2
2
2
GND
-
3
3
A0_DATA0_0N_IOB1
K3
4
4
A2_DATA1_0N_IOB1
J3
5
5
A4_DATA2_0N_IOB1
J5
6
6
A6_DATA3_0N_IOB1
J4
7
7
A8_DATA4_0N_IOB1
L2
8
8
A10_DATA5_0N_IOB1
M1
9
9
A12_DATA6_0N_IOB1
K4
10
10
A14_DATA7_0N_IOB1
L3
11
11
A16_INITF_4P_IOB1
K5
12
12
A18_CSF_4N_IOB1
L5
13
13
A20_READ_5P_IOB1
N1
14
14
A22_CCLK_5N_IOB1
M2
15
15
PGMF
R3
10k-ohm Resistor to VCCJ
Notes
16
16
DONE
M4
Drives LED, see Schematic Figure 8
17
17
CFG0
L8
10k-ohm Resistor to VCCJ
18
18
GND
-
19
19
B2_8N_IOB1
P2
20
20
B0_8P_IOB1
N2
21
21
B5_9N_IOB1
R2
22
22
B4_9P_IOB1
R1
23
23
B8_10N_IOB1
T3
24
24
B6_10P_IOB1
T2
25
25
B16_11N_IOB1
P4
26
26
B14_11P_IOB1
N3
27
27
B20_12N_IOB1
M6
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Lattice Semiconductor
ispXPLD Evaluation Board User’s Guide
Table 5. I/O Bank 1 (Continued)
P5(2mm)
J5(Mictor)
Description
ispXPLD
Pin
28
28
B18_12P_IOB1
N5
29
29
B24_13P_IOB1
T4
30
36
B22_IOB1
P5
31
31
B28_14P_IOB1
R4
32
30
B26_13N_IOB1
T5
33
33
C0_15P_IOB1
R5
34
32
B30_14N_IOB1
N6
35
35
C12_IOB1
M7
36
34
C2_15N_IOB1
P6
37
37
C18_18N_IOB1
R6
38
38
C16_18P_IOB1
T6
39
-
C26_19N_IOB1
R7
40
-
C24_19P_IOB1
T7
41
-
D0_20N_IOB1
P7
42
-
C28_20P_IOB1
N7
43
-
D4_21N_IOB1
R8
44
-
D2_21P_IOB1
T8
45
-
D8_22N_IOB1
P8
46
-
D6_22P_IOB1
M8
47
-
D16_23N_IOB1
M9
48
-
D12_23P_IOB1
N8
49
-
GND
-
50
-
GND
-
Notes
Table 6. I/O Bank 2
P6(2mm)
J6(Mictor)
Description
ispXPLD
Pin
1
-
GND
-
Notes
2
-
GND
-
3
1
E0_27P_IOB2
T11
4
2
E2_27N_IOB2
T12
24.9-ohm Series Resistor
5
3
E4_28P_IOB2
P10
24.9-ohm Series Resistor
6
4
E6_28N_IOB2
R10
24.9-ohm Series Resistor
7
5
E8_29P_IOB2
R11
49.9-ohm Resistor to VCCOC
8
6
E10_29N_IOB2
M10
49.9-ohm Resistor to VCCOC
9
7
E12_30P_IOB2
M11
49.9-ohm Resistor to VCCOC
10
8
E16_30P_IOB2
T13
49.9-ohm Resistor to VCCOC
11
9
E18_IOB2
P11
12
10
GND
-
13
11
E24_32N_IOB2
R13
14
12
E22_32P_IOB2
R12
15
13
E28_33N_IOB2
T15
7
24.9-ohm Series Resistor
Lattice Semiconductor
ispXPLD Evaluation Board User’s Guide
Table 6. I/O Bank 2 (Continued)
ispXPLD
Pin
P6(2mm)
J6(Mictor)
Description
16
14
E26_33P_IOB2
N11
17
15
F2_34N_IOB2
N12
18
16
F0_34P_IOB2
R14
19
17
F6_35N_IOB2
R15
20
18
F4_35P_IOB2
P12
21
19
G6_42N_IOB2
P15
22
20
G4_42P_IOB2
P13
23
21
GOE0
H11
24
22
GND
-
25
23
G10_43N_IOB2
P14
26
24
G8_43P_IOB2
M13
27
25
G22_46N_IOB2
P16
28
26
G20_46P_IOB2
R16
29
27
G26_47N_IOB2
N14
30
28
G24_47P_IOB2
N15
31
29
G30_48N_IOB2
M16
32
30
G28_48P_IOB2
N16
33
31
H0_49N_IOB2
M15
34
32
H0_49P_IOB2
M14
35
-
GND
-
36
-
GND
-
37
33
H10_51N_IOB2
L12
38
34
H8_51P_IOB2
L13
39
35
H14_52N_IOB2
L16
40
36
H12_52P_IOB2
L15
41
37
H20_53N_IOB2
K15
42
38
H16_53P_IOB2
L14
43
-
H22_54N_IOB2
K12
44
-
H12_54P_IOB2
K14
45
-
H26_55N_IOB2
J13
46
-
H12_55P_IOB2
K13
47
-
H30_56N_IOB2
J12
48
-
H12_56P_IOB2
J14
49
-
GND
-
50
-
GND
-
Notes
Table 7. I/O Bank 3
P7(2mm)
J7(Mictor)
Description
ispXPLD
Pin
1
1
GND
-
2
2
GND
-
3
3
I30_57N_IOB3
H14
8
Notes
Lattice Semiconductor
ispXPLD Evaluation Board User’s Guide
Table 7. I/O Bank 3 (Continued)
Description
ispXPLD
Pin
4
I28_57P_IOB3
G16
5
I26_58N_IOB3
G15
P7(2mm)
J7(Mictor)
4
5
6
6
I24_PLLFBK1_58P
F15
7
7
I22_PLLRST1_59N
H12
8
8
I20_59P_IOB3
G14
9
9
I28_60N_IOB3
F16
10
10
I16_60P_IOB3
E16
11
11
I14_61N_IOB3
G13
12
12
I12_61P_IOB3
G12
13
13
I10_62N_IOB3
F14
14
14
I8_CLKOUT1_62P_IOB3
E15
15
15
I6_63N_IOB3
F12
16
16
I4_63P_IOB3
F13
17
17
I2_64N_IOB3
D16
18
18
IO_64P_IOB3
D15
19
19
J14_69N_IOB3
C16
20
20
J12_69P_IOB3
B16
21
21
J10_70N_IOB3
C15
22
22
J8_70P_IOB3
B15
23
23
J6_71N_IOB3
E14
24
24
J4_71P_IOB3
D14
25
25
J2_72N_IOB3
E13
26
26
J0_72P_IOB3
A15
27
27
K30_73N_IOB3
D12
28
28
K28_73P_IOB3
B14
29
29
K26_74N_IOB3
C13
30
30
K24_74P_IOB3
A14
31
31
K22_75N_IOB3
A13
32
32
K21_75P_IOB3
B13
33
33
K20_76N_IOB3
D11
34
34
K18_76P_IOB3
B12
35
35
K16_77N_IOB3
C12
36
36
K14_77P_IOB3
E11
37
-
GND
-
38
-
GOE1
H13
39
37
K0_81P_IOB3
A11
40
38
K2_81N_IOB3
A12
41
-
L28_82P_IOB3
C11
42
-
L30_82N_IOB3
B11
43
-
L24_83P_IOB3
A10
44
-
L26_83N_IOB3
B10
45
-
No Connect
-
46
-
L22_84N_IOB3
C10
9
Notes
Lattice Semiconductor
ispXPLD Evaluation Board User’s Guide
Table 7. I/O Bank 3 (Continued)
ispXPLD
Pin
P7(2mm)
J7(Mictor)
Description
47
-
L18_85P_IOB3_LCD2
E9
48
-
L20_85N_IOB3_LCD1
C9
49
-
GND
-
50
-
GND
-
Notes
The top side of the board also contains a 14-pin header, which is suitable for connection to an LCD display. 5V
Power and GND are provided in addition to 11 I/Os from the ispXPLD device. A contrast control is also available via
a 20K-ohm potentiometer mounted near the header. A compatible display is the Optrex DMC16207 (or equivalent)
16x2 character LCD module. Table 8 lists the pin locations for this feature.
Table 8. LCD Header
P3
Description
ispXPLD
Pin
1
GND
-
2
+5V
-
3
Contrast
-
4
L20_85N_IOB3_LCD1
C9
5
L18_85P_IOB3_LCD2
E9
6
L14_IOB3_LCD3
F9
7
L12_87N_IOB3_LCD4
A9
8
L10_87P_IOB3_LCD5
F8
9
L8_88N_IOB3_LCD6
E8
10
L6_88P_IOB3_LCD7
A8
11
L5_89N_IOB3_LCD8
B9
12
L4_89P_IOB3_LCD9
D8
13
L2_90N_IOB3_LCDA
B8
14
L0_90P_IOB3_LCDB
C8
Running the Sample Program
Requirements
• PC with ispVM System software version 13.1 (or later) programming management software, installed with appropriate drivers (USB driver for USB Cable, Windows NT/2000/XP parallel port driver for ispDOWNLOAD Cable).
Note: An option to install these drivers is included as part of the ispVM System setup.
• ispDOWNLOAD Cable (pDS4102-DL2, HW7265-DL3 or HW-USB-1A)
This sample program consists of a 10-bit counter running from the on-board 20MHz oscillator. The 10-bit counter
value is routed to output pins, as described below in Table 9.
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Lattice Semiconductor
ispXPLD Evaluation Board User’s Guide
Table 9. Counter Output Locations
Output
Board Location
Function
Counter[9]
P3, pin 14
Counter MSB output
Counter[8]
P3, pin 13
Counter[7]
P3, pin 12
Counter[6]
P3, pin 11
Counter[5]
P3, pin 10
Counter[4]
P3, pin 9
Counter[3]
P3, pin 8
Counter[2]
P3, pin 7
Counter[1]
P3, pin 6
Counter[0]
P3, pin 5
Counter LSB output
Download Procedures
1. Connect the ispXPLD Evaluation Board to the AC adaptor or an external 5V supply.
2. Connect the ispDOWNLOAD Cable to connector P2 to access the ispXPLD device. Pin 1 corresponds to VCC
(red wire on cable).
3. Start the ispVM System software.
4. Click the ‘SCAN’ button located in the toolbar. The ispXPLD should be automatically detected. The resulting
screen should be similar to Figure 3..
Figure 3. ispVM System Software Interface
5. Double-click the ispXPLD to open the device properties dialog.
In the device properties dialog, click the Browse button located under ‘Data File’. Locate the ‘demo.isc’ file. Click Ok
to both dialog boxes.
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Lattice Semiconductor
ispXPLD Evaluation Board User’s Guide
Figure 4. Selecting the Data File
6. Click the green ‘GO’ button. This will begin the download process.
Once the download is complete, the counter outputs should be viewable in the corresponding locations.
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
+1-408-826-6002 (Outside North America)
e-mail: techsupport@latticesemi.com
Internet: www.latticesemi.com
12
D
C
B
1
PLD_TDI
PLD_TDO
PLD_TCK
PLD_TMS
R15
10K
VCCPP
VCCOD
R17
10K
VCCOC
R18
10K
C1
0.1
P1
R2
R7
R8
R9
VCCOB
TP3
TP4
R203
R204
R205
R206
R202
2
V5
0
0
0
0
0
C5
10uF
R201
R200
0
NC_4
NC_8
NC_17
NC_18
IN_6
IN_7
EN
U4
TPS77501PWP
16
FB
15
R29
110K
TP11
3
4
TP13
R30
0.1
TP15
VCCJ
CURRENT SENSE
TP14
VCCPP
CURRENT SENSE
R26
0.1
D3
RED
R5
301
VCCPP
VCCJ
VCCPP
D4
RED
R6
301
VCCPP
5
Date:
File:
B
Size
Title
D6
RED
R20
301
VCCPP
D7
RED
R21
301
VCCPP
Number
6/19/2003
C:\wcn\..\XPLD_Sheet1.SchDoc
6
D8
RED
R22
301
VCCPP
Revision
6
Sheet 1 of TBD
Drawn By:
Schematic, XPLD Demo Board
D5
RED
R19
301
VCCPP
(LEDs light red to indicate input under threshold)
VCCOB_LDO_ENF
VCCOC_LDO_ENF
VCCOD_LDO_ENF
RSTF_FRM_POWERPAC
VCCOA_LDO_ENF
TP12
5
ispPAC-POWR1208 Comparator Status LEDs
VCC_LDO_ENF
VCCP_LDO_ENF
D2
RED
R4
301
VCCPP
Power Manager and VCCP/VCCJ LDO
C6
10
VCCJPP_LDO_RSTF
C4
39
R27
200K
DNP
0.1
R24
25
13
14
D1
RED
R3
301
VCCOB_LDO_ENF
VCCOC_LDO_ENF
VCCOD_LDO_ENF
RSTF_FRM_POWERPAC
VCCOA_LDO_ENF
0
RESET
4
VCCPP
VCC_LDO_ENF
VCCP_LDO_ENF
C3
0.1
R23
TP10
PP_COMP1_OUT
PP_COMP2_OUT
PP_COMP3_OUT
PP_COMP4_OUT
PP_COMP5_OUT
PP_COMP6_OUT
PP_COMP7_OUT
PP_COMP8_OUT
C2
0.01
VCCPP
12
13
14
15
4
3
2
1
23
22
21
20
19
18
17
16
5
11
27
OUT_13
OUT_14
CREF
POR
OUT5
OUT6
OUT7
OUT8
HVOUT1
HVOUT2
HVOUT3
HVOUT4
COMP1
COMP2
COMP3
COMP4
COMP5
COMP6
COMP7
COMP8
VDD
VDDINP
GND
isPAC-POWR1208-01T44I
VCCP and VCCJ Regulation
4
8
17
18
6
7
5
VMON1
VMON2
VMON3
VMON4
VMON5
VMON6
VMON7
VMON8
VMON9
VMON10
VMON11
VMON12
IN1
IN2
IN3
IN4
CLK
RESET
TDO
TDI
TMS
TCK
TRST
U1
3
(Power Manager and JTAG Power – 3.3V Nominal)
R28
10K
TP5
TP6
TP7
TP8
TP9
32
33
34
35
36
37
38
40
41
42
43
44
6
7
8
9
26
10
28
30
31
24
29
R1
10K
VCCPP
0 VCCPMON
VCCJMON
VCCOAMON
VCCOBMON
VCCOCMON
VCCODMON
VCC
PP_IN_1
PP_IN_2
PP_IN_3
PP_IN_4
TP1
TP2
22.1
VCCPP
R14
10K
R10
PP_TDO
VCCOA VCCJ VCCP
1
2
3
4 (NC)
5 (KEY)
6
7
8
VCCPP
DNP
DNP
DNP
DNP
2
ispPAC-POWR1208
Power Supply Controller
PP_IN_3
PP_IN_4
R16
10K
SW1
RESET SWITCH
Power Manager/Chained
JTAG ISP Header
PLD_TDI
PLD_TDO
PLD_TCK
PLD_TMS
TSM-108-03-L-SV-P
A
1
GND_1
GND_2
GND_3
GND_9
GND_10
GND_11
GND_12
GND_19
GND_20
HEATTAB
13
1
2
3
9
10
11
12
19
20
21
D
C
B
A
Lattice Semiconductor
ispXPLD Evaluation Board User’s Guide
Appendix A. Schematic
Figure 5. Lattice ispXPLD Evaluation Board Schematic
D
C
B
A
J3
1
1
3
2
J1
BLACK BANJACK
J2
RED BA NJA CK
D10
SK33-7
TP16
D11
6.0V
TP34
V5
TP40
(4.5V to 5.5V)
DC POWER INPUT
PJ-002BH-SMT
1
2
2
R37
365
D9
GRN
TP41
V5
C7
10uF
VCC_LDO_ENF
R34
DNP
4
8
17
18
6
7
5
V5
C9
10uF
VCCP_LDO_ENF
R41
DNP
4
8
17
18
6
7
5
V5
C11
10uF
VCCOA_LDO_ENF
R47
DNP
4
8
17
18
6
7
5
TPS76701QPWP
4
TPS77501PWP
TPS77501PWP
FB
OUT_13
OUT_14
RESET
FB
OUT_13
OUT_14
RESET
FB
OUT_13
OUT_14
RESET
3
4
VCC, VCCP & VCCOA LDOs
(2.55V NOMINAL)
NC_4
NC_8
NC_17
NC_18
IN_6
IN_7
EN
U7
NC_4
NC_8
NC_17
NC_18
IN_6
IN_7
EN
U6
NC_4
NC_8
NC_17
NC_18
IN_6
IN_7
EN
U5
VCCOA REGULATION
R97
10K
VCCPP
VCCOA_LDO_ENF
(2.55V NOMINAL)
VCCP REGULATION
R96
10K
VCCPP
VCCP_LDO_ENF
(1.85V NOMINAL)
VCC REGULATION
R95
10K
VCCPP
VCC_LDO_ENF
3
GND_1
GND_2
GND_3
GND_9
GND_10
GND_11
GND_12
GND_19
GND_20
HEATTAB
1
2
3
9
10
11
12
19
20
21
GND_1
GND_2
GND_3
GND_9
GND_10
GND_11
GND_12
GND_19
GND_20
HEATTAB
1
2
3
9
10
11
12
19
20
21
GND_1
GND_2
GND_3
GND_9
GND_10
GND_11
GND_12
GND_19
GND_20
HEATTAB
14
1
2
3
9
10
11
12
19
20
21
15
13
14
16
15
13
14
16
15
13
14
16
TP18
TP17
C12
10
C10
10
C8
10
R31
0.1
LDO_RSTF
TP20
R38
0.1
TP22
R44
0.1
TP24
5
Date:
File:
B
Size
Title
R48
110K
R45
127K
R42
110K
R39
127K
R35
110K
R32
61.9K
LDO_RSTF
USER INSTALLABLE
VOLTAGE SET
RESISTORS
R49
DNP
R46
DNP
VCCOA
USER INSTALLABLE
VOLTAGE SET
RESISTORS
R43
DNP
R40
DNP
VCCP
USER INSTALLABLE
VOLTAGE SET
RESISTORS
R36
DNP
R33
DNP
VCC
6/19/2003
C:\wcn\..\XPLD_Sheet2.SchDoc
Number
6
Revision
6
Sheet 2 of TBD
Drawn By:
Schematic, XPLD Demo Board
VCCOA
CURRENT SENSE
TP23
VCCP
CURRENT SENSE
TP21
VCC
CURRENT SENSE
TP19
5
D
C
B
A
Lattice Semiconductor
ispXPLD Evaluation Board User’s Guide
Figure 6. Lattice ispXPLD Evaluation Board Schematic
D
C
B
A
1
127.0K
1.8V
1.5V
110.0K
110.0K
110.0K
R Fixed
BOT
110.0K
R Fixed BOT
R Fixed TOP
40.2K
110.0K
DNP
R User
TOP
DNP
DNP
DNP
200.0K
R User
BOT
DNP
USER INSTALLABLE
VOLTAGE SET
RESISTORS
R User BOT
R User TOP
2
2
VCCOX LDO ADJUSTMENT
127.0K
127.0K
3.3V
R Fixed
TOP
127.0K
VCCOX
2.5V
TO LDO FB
FROM LDO OUTPUT
1
V5
C13
10uF
VCCOB_LDO_ENF
R53
DNP
4
8
17
18
6
7
5
V5
C15
10uF
VCCOC_LDO_ENF
R59
DNP
4
8
17
18
6
7
5
V5
C17
10uF
VCCOD_LDO_ENF
R65
DNP
4
8
17
18
6
7
5
TPS77501PWP
4
TPS77501PWP
TPS77501PWP
FB
OUT_13
OUT_14
RESET
FB
OUT_13
OUT_14
RESET
FB
OUT_13
OUT_14
RESET
15
13
14
16
15
13
14
16
15
13
14
16
TP27
TP26
TP25
3
4
VCCOB, VCCOC & VCCOD LDOs
(2.55V NOMINAL)
NC_4
NC_8
NC_17
NC_18
IN_6
IN_7
EN
U10
VCCOD REGULATION
R100
10K
VCCPP
VCCOD_LDO_ENF
(2.55V NOMINAL)
NC_4
NC_8
NC_17
NC_18
IN_6
IN_7
EN
U9
VCCOC REGULATION
R99
10K
VCCPP
VCCOC_LDO_ENF
(2.55V NOMINAL)
NC_4
NC_8
NC_17
NC_18
IN_6
IN_7
EN
U8
VCCOB REGULATION
R98
10K
VCCPP
VCCOB_LDO_ENF
3
GND_1
GND_2
GND_3
GND_9
GND_10
GND_11
GND_12
GND_19
GND_20
HEATTAB
1
2
3
9
10
11
12
19
20
21
GND_1
GND_2
GND_3
GND_9
GND_10
GND_11
GND_12
GND_19
GND_20
HEATTAB
1
2
3
9
10
11
12
19
20
21
GND_1
GND_2
GND_3
GND_9
GND_10
GND_11
GND_12
GND_19
GND_20
HEATTAB
15
1
2
3
9
10
11
12
19
20
21
C18
10
C16
10
C14
10
R50
0.1
TP29
R56
0.1
TP31
R62
0.1
TP33
5
Date:
File:
B
Size
Title
R66
110K
R63
127K
R60
110K
R57
127K
R54
110K
R51
127K
USER INSTALLABLE
VOLTAGE SET
RESISTORS
R67
DNP
R64
DNP
VCCOD
USER INSTALLABLE
VOLTAGE SET
RESISTORS
R61
DNP
R58
DNP
VCCOC
USER INSTALLABLE
VOLTAGE SET
RESISTORS
R55
DNP
R52
DNP
VCCOB
6/19/2003
C:\wcn\..\XPLD_Sheet3.SchDoc
Number
6
Revision
6
Sheet 3 of TBD
Drawn By:
Schematic, XPLD Demo Board
VCCOD
CURRENT SENSE
TP32
VCCOC
CURRENT SENSE
TP30
VCCOB
CURRENT SENSE
TP28
5
D
C
B
A
Lattice Semiconductor
ispXPLD Evaluation Board User’s Guide
Figure 7. Lattice ispXPLD Evaluation Board Schematic
16
D
C
B
1
VCCJ
VCCJ
C38
0.1
C35
0.1
R87
DNP
R86
110K
C37
0.01
C34
0.01
6
2
3
2
4
VCC
NC
GND
U2
GND
VDD
OUT
OUT
EN
DNP
OUT
OE
U12
20.000 MHz
OSCILLATORS
4
5
1
3 R90
1
2
R89
10K
VCCJ
USER INSTALLABLE
VREF MOD
RESISTORS
R84
DNP
R83
110K
VCCOD
R79
DNP
R78
110K
VCCOD
R77
DNP
R76
110K
VCCOC
R75
DNP
R74
110K
VCCOC
R73
DNP
VCCOB
R71
DNP
R69
DNP
VCCOA
R72
110K
VCCOB
R70
110K
R68
110K
VCCOA
2
22.1
D12
GRN
DONE
GOE0
GOE1
GCLK1
GCLK0
PGMF
CFG0
R101
100
10K
TP35
R94
DNP
RSTF_FRM_POWERPAC
R12
GOE0
GOE1
R80
10K
RESET
TOE
GOE0
GOE1
GCLK0
GCLK1
GCLK2
GCLK3
PROGRAM
CFG0
DONE
GND_P3
GND_M12
GND_M5
GND_K10
GND_K9
GND_K8
GND_K7
GND_K1
GND_J10
GND_J9
GND_J8
GND_J7
GND_H10
GND_H9
GND_H8
GND_H7
GND_G10
GND_G9
GND_G8
GND_G7
GND_E12
GND_E5
GND_C14
GND_C3
GNDP
VCCP
VCCJ
VCC_N13
VCC_N4
VCC_L11
VCC_L6
VCC_F11
VCC_F6
VC_D13
VCC_D4
VCC3_A16
VCC03_F10
VCC03_G11
VCC02_K11
VCC02_L10
VCC02_T16
VCC01_K6
VCC01_L7
VCC01_T1
P3
M12
M5
K10
K9
K8
K7
K1
J10
J9
J8
J7
H10
H9
H8
H7
G10
G9
G8
G7
E12
E5
C14
C3
K16
J16
J1
N13
N4
L11
L6
F11
F6
D13
D4
A16
F10
G11
K11
L10
T16
K6
L7
T1
A1
F7
G6
XPLD "SYSTEM" PINS
J11
J15
H11
H13
H2
J2
H15
H16
R3
L8
M4
R81
10K
TDO
TDI
TMS
TCK
VREF3/L16
VREF2/E20
VREF1/D10
VCCO0_A1
VCCO0_F7
VCCO0_G6
LC5512XX-XXF256X
VREF0/M16
U11A
4
C27
0.01
C23
0.01
C32
0.01
R11
C28
0.01
C24
0.01
VCCOC
C20
0.01
VCCOA
C19
0.01
0
C29
0.01
C30
0.01
VCCP
VCC
C25
0.01
C26
0.01
VCCOD
C22
0.01
VCCOB
C21
0.01
3
4
OSCILLATOR & XPLD SYSTEM PINS
LDO_RSTF
D9
XPLD_VREF3
VCCJ VCCJ
T14
XPLD_VREF2
K2
H6
H4
J6
L9
XPLD_VREF1
PLD_TDO
PLD_TDI
PLD_TMS
PLD_TCK
A5
3
XPLD_VREF0
GCLK0
GCLK1
GCLK2_DIFF
GCLK3_DIFF
PGMF
CFG0
DONE
(NC)
(KEY)
VCCJ
VCCJ
1
2
3
4
5
6
7
8
RSTF_FRM_POWERPAC
R82
301
VCCJ
PLD_TMS
PLD_TCK
PLD_TDI
PLD_TDO
JTAG
ISP HEADER
P2
TSM-108-03-L-SV-P
A
1
5
Date:
File:
B
Size
Title
C31
0.01
VCCJ
5
6/19/2003
C:\wcn\..\XPLD_Sheet4.SchDoc
Number
Revision
6
Sheet 4 of TBD
Drawn By:
Schematic, XPLD Demo Board
6
D
C
B
A
Lattice Semiconductor
ispXPLD Evaluation Board User’s Guide
Figure 8. Lattice ispXPLD Evaluation Board Schematic
17
D
C
B
A
R92
DNP
GCLK0
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
P4
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
M14_95P_IOB0
O20_111P_IOB0
O22_111N_IOB0
1118P_IOB0_LVDT
118N_IOB0_LVDT
120P_IOB0_LVDT
120N_IOB0_LVDT
122P_IOB0_LVDT
122N_IOB0_LVDT
124P_IOB0_LVDT
124N_IOB0_LVDT
M26_92N_IOB0_LVD
M24_92P _IOB0_LVD
M20_94N _IOB0_LVD
M18_94P _IOB0_LVD
M6_97P _IOB0_LVD
M8_97N_IOB0_LVD
M0_99P_IOB0_LVD
M2_99N _IOB0_LVD
112P_IOB0_LVDT
112N_IOB0_LVDT
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
J4
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
1118P_IOB0_LVDT
118N_IOB0_LVDT
120P_IOB0_LVDT
120N_IOB0_LVDT
122P_IOB0_LVDT
122N_IOB0_LVDT
123N_IOB0_LVDT
M26_92N_IOB0_LVD
M24_92P _IOB0_LVD
M20_94N _IOB0_LVD
M18_94P _IOB0_LVD
M6_97P _IOB0_LVD
M8_97N_IOB0_LVD
M0_99P_IOB0_LVD
M2_99N _IOB0_LVD
112P_IOB0_LVDT
112N_IOB0_LVDT
1
2
* BANK0 SIGNALS WITH "LVD" IN THE NETNAME ARE ROUTED
AS CONTROLLED IMPEDANCE DIFFERENTIAL PAIRS
MICTOR HEADER - I/O BANK 0
117P_IOB0_LVDT
117N_IOB0_LVDT
119P_IOB0_LVDT
119N_IOB0_LVDT
121P_IOB0_LVDT
121N_IOB0_LVDT
123P_IOB0_LVDT
M30_91N _IOB0_LVD
M28_91P _IOB0_LVD
M22_93N _IOB0_LVD
M21_93P_IOB0_LVD
M10_96P _IOB0_LVD
M12_96N _IOB0_LVD
M4_98P _IOB0_LVD
M5_98N_IOB0_LVD
N4_107P_IOB0_LVD
N5_107N _IOB0_LVD
GCLK0
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
2
2MM HEADER - I/O BANK 0
117P_IOB0_LVDT
117N_IOB0_LVDT
119P_IOB0_LVDT
119N_IOB0_LVDT
121P_IOB0_LVDT
121N_IOB0_LVDT
123P_IOB0_LVDT
123N_IOB0_LVDT
O24_110P_IOB0
O26_110N_IOB0
O28_109P_IOB0
O30_109N_IOB0
M30_91N _IOB0_LVD
M28_91P _IOB0_LVD
M22_93N _IOB0_LVD
M21_93P_IOB0_LVD
M10_96P _IOB0_LVD
M12_96N _IOB0_LVD
M4_98P _IOB0_LVD
M5_98N_IOB0_LVD
N4_107P_IOB0_LVD
N5_107N _IOB0_LVD
GCLK0
1
TMM-125-01-G-D-SM
MIS-019-01-L-D
G1
G2
G3
G4
G5
B7
A7
D7
C7
B6
E7
E6
A6
A4
B5
A3
B4
B3
C5
C6
D5
D6
A2
B2
C4
E4
B1
C1
D3
C2
E3
D2
D1
E1
F4
F5
E2
F2
F1
G1
F3
G5
H5
G4
G3
H3
G2
H1
K3
J3
J5
J4
L2
M1
K4
L3
K5
L5
N1
M2
P1
M3
L4
N2
P2
R1
R2
T2
T3
N3
P4
N5
M6
P5
T4
T5
R4
N6
R5
P6
M7
T6
R6
T7
R7
N7
P7
T8
R8
M8
P8
N8
M9
N10
T9
T10
R9
P9
N9
PP_IN_3
PP_IN_4
PP_IN_3
PP_IN_4
A0_DATA0_0P_IOB1
A2_DATA1_0N_IOB1
A4_DATA2_1P_IOB1
A6_DATA3_1N_IOB1
A8_DATA4_2P_IOB1
A10_DATA5_2N_IOB1
A12_DATA6_3P_IOB1
A14_DATA7_3N_IOB1
A16_INITF_4P_IOB1
A18_CSF_4N_IOB1
A20_READ_5P_IOB1
A22_CCLK_5N_IOB1
A26_IOB1
A28_7P_IOB1
A30_7N_IOB1
B0_8P_IOB1
B2_8N_IOB1
B4_9P_IOB1
B5_9N_IOB1
B6_10P_IOB1
B8_10N_IOB1
B14_11P_IOB1
B16_11N_IOB1
B18_12P_IOB1
B20_12N_IOB1
B22_IOB1
B24_13P_IOB1
B26_13N_IOB1
B28_14P_IOB1
B30_14N_IOB1
C0_15P_IOB1
C2_15N_IOB1
C12_IOB1
C16_18P_IOB1
C18_18N_IOB1
C24_19P_IOB1
C26_19N_IOB1
C28_20P_IOB1
D0_20N_IOB1
D2_21P_IOB1
D4_21N_IOB1
D6_22P_IOB1
D8_22N_IOB1
D12_23P_IOB1
D16_23N_IOB1
D18_24P_IOB1
TP36
D20_24N_IOB1
TP37
D22_25N_IOB1
TP38
RSTF_FRM_POWERPAC
XPLD I/O BANKS 0, 1
RSTF_FRM_POWERPAC
M30/91N (IOB0)
M28/91P (IOB0)
M26/92N (IOB0)
M24/92P (IOB0)
M22/93N (IOB0)
M21/93P (IOB0)
M20/94N (IOB0)
M18/94P (IOB0)
M14/95P (IOB0)
M12/96N (IOB0)
M10/96P (IOB0)
M8/97N (IOB0)
M6/97P (IOB0)
M5/98N (IOB0)
M4/98P (IOB0)
M2/99N (IOB0)
M0/99P (IOB0)
N5/107N (IOB0)
N4/107P (IOB0)
030/109N (IOB0)
028/109P (IOB0)
O26/110N (IOB0)
O24/110P (IOB0)
O22/111N (IOB0)
O20/111P (IOB0)
O18/112N (IOB0)
O16/112P (IOB0)
P30/117N (IOB0)
P28/117P (IOB0)
P26/118N (IOB0)
P24/118P (IOB0)
P22/119N (IOB0)
P20/119P/CLK_OUT0 (IOB0)
P18/120N (IOB0)
P16/120P (IOB0)
P14/121N (IOB0)
P12/121P (IOB0)
P10/122N (IOB0)
P8/122P/PLL_RST0 (IOB0)
P6/123N (IOB0)
P4/123P/PLL_FBK0 (IOB0)
P2/124N (IOB0)
P0/124P (IOB0)
(IOB1) A0/DATA0/0P
(IOB1) A2/DATA1/0N
(IOB1) A4/DATA2/1P
(IOB1) A6/DATA3/1N
(IOB1) A8/DATA4/2P
(IOB1) A10/DATA5/2N
(IOB1) A12/DATA6/3P
(IOB1) A14/DATA7/3N
(IOB1) A16/INITb/4P
(IOB1) A18/CSB/4N
(IOB1) A20/READ/5P
(IOB1) A22/CCLK/5N
(IOB1) A26
(IOB1) A28/7P
(IOB1) A30/7N
(IOB1) B0/8P
(IOB1) B2/8N
(IOB1) B4/9P
(IOB1) B5/9N
(IOB1) B6/10P
(IOB1) B8/10N
(IOB1) B14/11P
(IOB1) B16/11N
(IOB1) B18/12P
(IOB1) B20/12N
(IOB1) B22
(IOB1) B24/13P
(IOB1) B26/13N
(IOB1) B28/14P
(IOB1) B30/14N
(IOB1) C0/15P
(IOB1) C2/15N
(IOB1) C12
(IOB1) C16/18P
(IOB1) C18/18N
(IOB1) C24/19P
(IOB1) C26/19N
(IOB1) C28/20P
(IOB1) D0/20N
(IOB1) D2/21P
(IOB1) D4/21N
(IOB1) D6/22P
(IOB1) D8/22N
(IOB1) D12/23P
(IOB1) D16/23N
(IOB1) D18/24P
(IOB1) D20/24N
(IOB1) D22/25P
(IOB1) D24/25N
(IOB1) D26/26P
(IOB1) D28/26N
LC5512XX-XXF256X
4
3
4
BANK 0, 1 I/O AND HEADERS
M30_91N _IOB0_LVD
M28_91P _IOB0_LVD
M26_92N_IOB0_LVD
M24_92P _IOB0_LVD
M22_93N _IOB0_LVD
M21_93P_IOB0_LVD
M20_94N _IOB0_LVD
M18_94P _IOB0_LVD
M14_95P_IOB0
M12_96N _IOB0_LVD
M10_96P _IOB0_LVD
M8_97N_IOB0_LVD
M6_97P _IOB0_LVD
M5_98N_IOB0_LVD
M4_98P _IOB0_LVD
M2_99N _IOB0_LVD
M0_99P_IOB0_LVD
N5_107N _IOB0_LVD
N4_107P_IOB0_LVD
O30_109N_IOB0
O28_109P_IOB0
O26_110N_IOB0
O24_110P_IOB0
O22_111N_IOB0
O20_111P_IOB0
112N_IOB0_LVDT
112P_IOB0_LVDT
117N_IOB0_LVDT
117P_IOB0_LVDT
118N_IOB0_LVDT
1118P_IOB0_LVDT
119N_IOB0_LVDT
119P_IOB0_LVDT
120N_IOB0_LVDT
120P_IOB0_LVDT
121N_IOB0_LVDT
121P_IOB0_LVDT
122N_IOB0_LVDT
122P_IOB0_LVDT
123N_IOB0_LVDT
123P_IOB0_LVDT
124N_IOB0_LVDT
124P_IOB0_LVDT
U11B
* SEE SHEET 7FOR LVDS TERMINATIONS
3
GCLK1
R93
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
P5
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
B0_8P_IOB1
B4_9P_IOB1
B6_10P_IOB1
B14_11P_IOB1
B18_12P_IOB1
B22_IOB1
B26_13N_IOB1
B30_14N_IOB1
C2_15N_IOB1
C16_18P_IOB1
C24_19P_IOB1
C28_20P_IOB1
D2_21P_IOB1
D6_22P_IOB1
D12_23P_IOB1
A2_DATA1_0N_IOB1
A6_DATA3_1N_IOB1
A10_DATA5_2N_IOB1
A14_DATA7_3N_IOB1
A18_CSF_4N_IOB1
A22_CCLK_5N_IOB1
DONE
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
J5
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
B0_8P_IOB1
B4_9P_IOB1
B6_10P_IOB1
B14_11P_IOB1
B18_12P_IOB1
B26_13N_IOB1
B30_14N_IOB1
C2_15N_IOB1
B22_IOB1
C16_18P_IOB1
A2_DATA1_0N_IOB1
A6_DATA3_1N_IOB1
A10_DATA5_2N_IOB1
A14_DATA7_3N_IOB1
A18_CSF_4N_IOB1
A22_CCLK_5N_IOB1
DONE
5
Date:
File:
B
Size
Title
6/19/2003
C:\wcn\..\XPLD_Sheet5.SchDoc
Number
Revision
6
Sheet 5 of TBD
Drawn By:
Schematic, XPLD Demo Board
MICTOR HEADER - I/O BANK 1
GCLK1
A0_DATA0_0P_IOB1
A4_DATA2_1P_IOB1
A8_DATA4_2P_IOB1
A12_DATA6_3P_IOB1
A16_INITF_4P_IOB1
A20_READ_5P_IOB1
PGMF
PGMF
CFG0
CFG0
B2_8N_IOB1
B5_9N_IOB1
B8_10N_IOB1
B16_11N_IOB1
B20_12N_IOB1
B24_13P_IOB1
B28_14P_IOB1
C0_15P_IOB1
C12_IOB1
C18_18N_IOB1
GCLK1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
22.1
6
2MM HEADER - I/O BANK 1
A0_DATA0_0P_IOB1
A4_DATA2_1P_IOB1
A8_DATA4_2P_IOB1
A12_DATA6_3P_IOB1
A16_INITF_4P_IOB1
A20_READ_5P_IOB1
PGMF
PGMF
CFG0
CFG0
B2_8N_IOB1
B5_9N_IOB1
B8_10N_IOB1
B16_11N_IOB1
B20_12N_IOB1
B24_13P_IOB1
B28_14P_IOB1
C0_15P_IOB1
C12_IOB1
C18_18N_IOB1
C26_19N_IOB1
D0_20N_IOB1
D4_21N_IOB1
D8_22N_IOB1
D16_23N_IOB1
GCLK1
5
MIS-019-01-L-D
G1
G2
G3
G4
G5
DONE
DONE
D
C
B
A
Lattice Semiconductor
ispXPLD Evaluation Board User’s Guide
Figure 9. Lattice ispXPLD Evaluation Board Schematic
D
C
B
A
GO E0
GO E0
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
P6
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
H8_51P_IO B2
H12_52P_IO B2
H16_53P_IO B2
H20_54P_IO B2
H24_55P_IO B2
H28_56P_IO B2
G8_43P_IO B2
G20_46P_IO B2
G24_47P_IO B2
G28_48P_IO B2
H0_49P_IO B2
E22_32P_IO B2
E26_33P_IO B2
F0_34P_IOB 2
F4_35P_IOB 2
G4_42P_IOB2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
J6
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
1
2
G8_43P_IO B2
G20_46P_IOB2
G24_47P_IO B2
G28_48P_IO B2
H0_49P_IO B2
H8_51P_IO B2
H12_52P_IO B2
H16_53P_IO B2
E22_32P_IO B2
E26_33P_IO B2
F0_34P_IOB 2
F4_35P_IOB 2
G4_42P_IO B2
E2_27N_IOB2
E6_28N_IOB2
E10_29N_IO B2
E16_30P_IO B2
Mictor Header – I/O Bank 2
E0_27P_IO B2
E4_28P_IO B2
E8_29P_IO B2
E12_30P_IO B2
E18_IO B2
E24_32N_IO B2
E28_33N_IO B2
F2_34N_IO B2
F6_35N_IO B2
G6_42N_IOB2
GO E0
G10_43N_IO B2
G22_46N_IO B2
G26_47N_IO B2
G30_48N_IO B2
H0_49N _IOB2
H10_51N_IO B2
H14_52N_IO B2
H20_53N_IO B2
2
E2_27N_IOB2
E6_28N_IOB2
E10_29N_IO B2
E16_30P_IO B2
2mm Header – I/O Bank 2
H10_51N_IO B2
H14_52N_IO B2
H20_53N_IO B2
H22_54N_IO B2
H26_55N_IO B2
H30_56N_IO B2
E0_27P_IO B2
E4_28P_IO B2
E8_29P_IO B2
E12_30P_IO B2
E18_IO B2
E24_32N_IO B2
E28_33N_IO B2
F2_34N_IO B2
F6_35N_IO B2
G6_42N_IO B2
GO E0
G10_43N_IO B2
G22_46N_IO B2
G26_47N_IO B2
G30_48N_IO B2
H0_49N _IOB2
1
TM M -125-01-G -D-SM
M IS-019-01-L-D
G1
G2
G3
G4
G5
18
T11
T12
P10
R10
R11
M 10
M 11
T13
P11
R12
R13
N11
T15
R14
N12
P12
R15
P13
P15
M 13
P14
R16
P16
N15
N14
N16
M 16
M 14
M 15
L13
L12
L15
L16
L14
K15
K14
K12
K13
J13
J14
J12
(IO B3)I30/57N
(IOB3)I28/57P
(IO B3)I26/58N
(IOB3)I24/PLL_FBK1/58P
(IO B3)I22/PLL_RST1/59N
(IOB3)I20/59P
(IO B3)I18/60N
(IOB3)I16/60P
(IO B3)I14/61N
(IOB3)I12/61P
(IO B3)I10/62N
(IO B3)I8/CLK_OUT 1/62P
(IO B3)I6/63N
(IO B3)I4/63P
(IO B3)I2/64N
(IO B3)I0/64P
(IO B3)J14/69N
(IO B3)/J12/69P
(IO B3)J10/70N
(IOB3)J8/70P
(IO B3)J6/71N
(IOB3)J4/71P
(IO B3)J2/72N
(IOB3)J0/72P
(IO B3)K 30/73N
(IO B3)K 28/73P
(IO B3)K 26/74N
(IO B3)K 24/74P
(IO B3)K 22/75N
(IO B3)K 21/75P
(IO B3)K 20/76N
(IO B3)K 18/76P
(IO B3)K 16/77N
(IO B3)K 14/77P
(IO B3)K 4/80P
(IO B3)K 2/81N
(IO B3)K 0/81P
(IO B3)L30/82N
(IOB3)L28/82P
(IO B3)L26/83N
(IOB3)L24/83P
(IO B3)L22/84N
(IOB3)L21/84P
(IO B3)L20/85N
(IOB3)L18/85P
(IOB3)L14
(IO B3)L12/87N
(IOB3)L10/87P
(IOB3)L8/88N
(IO B3)L6/88P
(IOB3)L5/89N
(IO B3)L4/89P
(IOB3)L2/90N
(IO B3)L0/90P
LC 5512XX -XXF 256X
R25
49.9
XPLD I/O Banks 2, 3
E0/27P (IO B2)
E2/27N (IO B2)
E4/28P (IO B2)
E6/28N (IO B2)
E8/29P (IO B2)
E10/29N (IO B2)
E12/30P (IO B2)
E16/30N (IO B2)
E18(IO B2)
E22/32P (IO B2)
E24/32N (IO B2)
E26/33P (IO B2)
E28/33N (IO B2)
F0/34P (IO B2)
F2/34N (IOB2)
F4/35P (IO B2)
F6/35N (IOB2)
G4/42P (IO B2)
G6/42N (IO B2)
G8/43P (IO B2)
G10/43N (IO B2)
G20/46P (IO B2)
G22/46N (IO B2)
G24/47P (IO B2)
G26/47N (IO B2)
G28/48P (IO B2)
G30/48N (IO B2)
H0/49P (IOB2)
H2/49N (IO B2)
H8/51P (IOB2)
H10/51N (IO B2)
H12/52P (IO B2)
H14/52N (IO B2)
H16/53P (IO B2)
H18/53N (IO B2)
H20/54P (IO B2)
H22/54N (IO B2)
H24/55P (IO B2)
H26/55N (IO B2)
H28/56P (IO B2)
H30/56N (IO B2)
U11C
E8_29P_IO B2
E10_29N_IO B2
E12_30P_IO B2
E16_30P_IOB 2
R13
49.9
H14
G16
G15
F15
H12
G14
F16
E16
G13
G12
F14
E15
F12
F13
D16
D15
C16
B16
C15
B15
E14
D14
E13
A15
D12
B14
C13
A14
A13
B13
D11
B12
C12
E11
E10
A12
A11
B11
C11
B10
A10
C10
D10
C9
E9
F9
A9
F8
E8
A8
B9
D8
B8
C8
R88
49.9
I12_62N_IOB3
L20_85N_IO B3_LCD 1
L18_85P_IO B3_LCD 2
L14_IO B3_LCD 3
L12_87N_IO B3_LCD 4
L10_87P_IO B3_LCD 5
L8_88N _IOB3_LC D 6
L6_88P_IO B3_LC D7
L5_89N _IOB3_LC D 8
L4_89P_IO B3_LC D9
L2_90N _IOB3_LC D A
L0_90P_IO B3_LC DB
I30_57N _IO B3
I28_57P_IO B3
I26_58N _IO B3
I24_PLLFBK 1_58P
I22_PLLR ST 1_59N
I20_59P_IOB3
I28_60N_IOB3
I16_60P_IOB3
I14_61N_IOB3
I12_61P_IOB3
I12_62N_IOB3
I8_CLK OUT1_62P_IO B3
I6_63N_IOB3
I4_63P_IOB3
I2_64N_IOB3
I0_64P_IOB3
J14_69N_IO B3
J12_69P_IO B3
J10_70N_IO B3
J8_70P_IOB 3
J6_71N_IOB3
J4_71P_IOB 3
J2_72N_IOB3
J0_72P_IOB 3
K30_73N_IO B3
K28_73P_IO B3
K26_74N_IO B3
K24_74P_IO B3
K22_75N_IO B3
K21_75P_IO B3
K20_76N_IO B3
K18_76P_IO B3
K16_77N_IO B3
K14_77P_IO B3
K4_80P_IO B3
TP42
K2_81N _IOB3
K0_81P_IO B3
L30_82N_IO B3
L28_82P_IO B3
L26_83N_IO B3
L24_83P_IO B3
L22_84N_IO B3
R102
49.9
VCCO C
4
3
4
(Labeled Bank 3 and Bank 4 on PWB Silkscreen)
Banks 2, 3 I/O and Headers
R103
24.9
R104
24.9
R105
24.9
R106
24.9
E8_29P_IO B2
E10_29N_IO B2
E12_30P_IO B2
E16_30P_IO B2
E18_IO B2
E22_32P_IO B2
E24_32N_IO B2
E26_33P_IO B2
E28_33N_IO B2
F0_34P_IOB2
F2_34N_IO B2
F4_35P_IOB2
F6_35N_IO B2
G4_42P_IOB2
G6_42N_IOB2
G8_43P_IOB2
G10_43N_IO B2
G20_46P_IO B2
G22_46N_IO B2
G24_47P_IO B2
G26_47N_IO B2
G28_48P_IO B2
G30_48N_IO B2
H0_49P_IO B2
H0_49N _IOB2
H8_51P_IO B2
H10_51N_IO B2
H12_52P_IO B2
H14_52N_IO B2
H16_53P_IO B2
H20_53N_IO B2
H20_54P_IO B2
H22_54N_IO B2
H24_55P_IO B2
H26_55N_IO B2
H28_56P_IO B2
H30_56N_IO B2
E6_28N_IOB2
E4_28P_IO B2
E2_27N_IOB2
E0_27P_IO B2
3
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
P7
TM M -125-01-G -D-SM
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
J7
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
5
Date:
File:
B
Size
Titl
e
6/19/2003
C :\wcn\..
\XPLD_Sheet6.SchDoc
Number
6
Sheet6 of TB D
Drawn By:
Schemati
c,XPLD D em o Board
Revision
I28_57P_IO B3
I24_PLLFBK 1_58P
I20_59P_IO B3
I16_60P_IO B3
I12_61P_IO B3
I8_CLK OUT1_62P_IO B3
I4_63P_IOB3
I0_64P_IOB3
J12_69P_IOB 3
J8_70P_IO B3
J4_71P_IO B3
J0_72P_IO B3
K28_73P_IO B3
K24_74P_IO B3
K21_75P_IO B3
K18_76P_IO B3
K14_77P_IO B3
K2_81N _IOB 3
Mictor Header – I/O Bank 3
I30_57N _IO B3
I26_58N _IO B3
I22_PLLR ST 1_59N
I28_60N _IO B3
I14_61N _IO B3
I10_62N _IO B3
I6_63N_IOB 3
I2_64N_IOB 3
J14_69N_IO B3
J10_70N_IO B3
J6_71N_IOB 3
J2_72N_IOB 3
K30_73N_IO B3
K26_74N_IO B3
K22_75N_IO B3
K20_76N_IO B3
K16_77N_IO B3
K0_81P_IO B3
6
I28_57P_IO B3
I24_PLLFBK 1_58P
I20_59P_IO B3
I16_60P_IO B3
I12_61P_IO B3
I8_CLK OUT1_62P_IO B3
I4_63P_IOB3
I0_64P_IOB3
J12_69P_IOB 3
J8_70P_IO B3
J4_71P_IO B3
J0_72P_IO B3
K28_73P_IO B3
K24_74P_IO B3
K21_75P_IO B3
K18_76P_IO B3
K14_77P_IO B3
GO E1
GO E1
K2_81N _IOB 3
L30_82N_IO B3
L26_83N_IO B3
L22_84N_IO B3
L20_85N_IO B3_LCD 1
2mm Header – I/O Bank 3
L18_85P_IO B3_LCD 2
K0_81P_IO B3
L28_82P_IO B3
L24_83P_IO B3
I30_57N _IO B3
I26_58N _IO B3
I22_PLLR ST 1_59N
I28_60N _IO B3
I14_61N _IO B3
I10_62N _IO B3
I6_63N_IOB3
I2_64N_IOB3
J14_69N_IOB3
J10_70N_IOB3
J6_71N_IO B3
J2_72N_IO B3
K30_73N_IO B3
K26_74N_IO B3
K22_75N_IO B3
K20_76N_IO B3
K16_77N_IO B3
5
M IS-019-01-L-D
G1
G2
G3
G4
G5
D
C
B
A
Lattice Semiconductor
ispXPLD Evaluation Board User’s Guide
Figure 10. Lattice ispXPLD Evaluation Board Schematic
19
M 28_91P _IO B0_LVD
M 24_92P _IO B0_LVD
M 21_93P_IO B0_LVD
M 18_94P _IO B0_LVD
M 12_96N _IO B0_LVD
M 8_97N_IOB0_LV D
M 5_98N_IOB0_LV D
M 2_99N _IOB0_LVD
N5_107N _IOB0_LV D
V5
3
4
LVDS RX Termination and LCD Header
1
2
3
4
5
6
7
8
9
10
11
12
13
14
C33
0.1
P3
C36
10
5
Titl
e
Schemati
c,XPLD D em o Board
6
Revision
B
A
Date:
File:
B
Size
6/19/2003
C :\wcn\..
\XPLD_Sheet7.SCHDOC
Number
6
Sheet7 of TB D
Drawn By:
D
LCD Header
L20_85N_IO B3_LCD 1
L18_85P_IO B3_LCD 2
L14_IO B3_LCD 3
L12_87N_IO B3_LCD 4
L10_87P_IO B3_LCD 5
L8_88N _IOB3_LC D 6
L6_88P_IO B3_LC D7
L5_89N _IOB3_LC D 8
L4_89P_IO B3_LC D9
L2_90N _IOB3_LC D A
L0_90P_IO B3_LC DB
R91
20K
V5
5
D
2
100
100
100
100
100
100
100
100
100
4
C
1
R121
R123
R124
R125
R127
R129
R130
R131
R133
Bank 0 LVDS RCVRS Termination
(Associated I/O Pins in Figure 9)
M 30_91N _IO B0_LVD
M 26_92N _IO B0_LVD
M 22_93N _IO B0_LVD
M 20_94N _IO B0_LVD
M 10_96P _IO B0_LVD
M 6_97P _IO B0_LV D
M 4_98P _IO B0_LV D
M 0_99P_IOB0_LV D
N4_107P_IO B0_LVD
3
C
B
2
TSM -114-03-L-SV-P
A
1
Lattice Semiconductor
ispXPLD Evaluation Board User’s Guide
Figure 11. Lattice ispXPLD Evaluation Board Schematic
Lattice Semiconductor
ispXPLD Evaluation Board User’s Guide
Appendix B. Bottom Silkscreen Drawing
VCCOX LDO ADJUSTMENT
R USER
R USER
BOT
R
FIXED
R
FIXED
2
VCCOX
TOP
BOT
TOP
DNP
DNP
110.0K
127.0K
2.5V
200.OK
DNP
110.0K
127.0K
3.3V
DNP
110.0K
110.0K
127.0K
1.8V
DNP
40.2K
110.0K
127.0K
1.5V
20
40
50
19
39
49
P5
1
I/O BANK 1
R36
VCC0A RUSERBOT
2
38
1
37
R49
C34
R46
C35
P4
VCC0A RUSERTOP
P6
R33
2
19
20
39
40
49
50
VCC0B RUSERBOT
1
2
1
J5
38
I/O BANK 3
2
J6
C24
VREF3 RUSERBOT
VREF2 RUSERBOT
C26
C25
R79
C37
R77
C38
VREF2 RUSERTOP
VCC0C RUSERTOP
R58
50
R61
VCC0C RUSERBOT
37
1
38
2
J7
VCC0D RUSERBOT
R67
R64
VCC0D RUSERTOP
I/O BANK 4
1
39
19
49
P7
40
20
20
2
50
49
C3
1
C22
C21
C23
C28
C27
R87
R84
37
2
38
C29
1
R73
C31
R75
VREF1 RUSERBOT
C20
VREF1 RUSERTOP
R71
R69
VREF0 RUSERBOT
C19
C2
40
39
VREF3 RUSERTOP
R43
37
I/O BANK 0
20
19
R40
R52
VCC0B RUSERTOP
C30
J4
VREF0 RUSERTOP
R55
C33
