LCMXO1200C-4M132C

MachXO Family Data Sheet DS1002 Version 03.0, June 2013 MachXO Family Data Sheet Introduction June 2013 Data Sheet DS1002  Flexible I/O Buffer Features • Programmable sysIO™ buffer supports wide range of interfaces:  LVCMOS 3.3/2.5/1.8/1.5/1.2  LVTTL  PCI  LVDS, Bus-LVDS, LVPECL, RSDS  Non-volatile, Infinitely Reconfigurable • Instant-on – powers up in microseconds • Single chip, no external configuration memory required • Excellent design security, no bit stream to  intercept • Reconfigure SRAM based logic in milliseconds • SRAM and non-volatile memory programmable through JTAG port • Supports background programming of  non-volatile memory  sysCLOCK™ PLLs • Up to two analog PLLs per device • Clock multiply, divide, and phase shifting  System Level Support • IEEE Standard 1149.1 Boundary Scan • Onboard oscillator • Devices operate with 3.3V, 2.5V, 1.8V or 1.2V power supply • IEEE 1532 compliant in-system programming  Sleep Mode • Allows up to 100x static current reduction  TransFR™ Reconfiguration (TFR) • In-field logic update while system operates Introduction  High I/O to Logic Density • • • • 256 to 2280 LUT4s 73 to 271 I/Os with extensive package options Density migration supported Lead free/RoHS compliant packaging The MachXO is optimized to meet the requirements of applications traditionally addressed by CPLDs and low capacity FPGAs: glue logic, bus bridging, bus interfacing, power-up control, and control logic. These devices bring together the best features of CPLD and FPGA devices on a single chip.  Embedded and Distributed Memory • Up to 27.6 Kbits sysMEM™ Embedded Block RAM • Up to 7.7 Kbits distributed RAM • Dedicated FIFO control logic Table 1-1. MachXO Family Selection Guide LCMXO256 LCMXO640 LCMXO1200 LCMXO2280 LUTs Device 256 640 1200 2280 Dist. RAM (Kbits) 2.0 6.1 6.4 7.7 0 0 9.2 27.6 EBR SRAM (Kbits) Number of EBR SRAM Blocks (9 Kbits) VCC Voltage 0 0 1 3 1.2/1.8/2.5/3.3V 1.2/1.8/2.5/3.3V 1.2/1.8/2.5/3.3V 1.2/1.8/2.5/3.3V Number of PLLs 0 0 1 2 Max. I/O 78 159 211 271 78 74 73 73 113 113 113 Packages 100-pin TQFP (14x14 mm) 144-pin TQFP (20x20 mm) 100-ball csBGA (8x8 mm) 78 74 132-ball csBGA (8x8 mm) 101 101 101 256-ball caBGA (14x14 mm) 159 211 211 256-ball ftBGA (17x17 mm) 159 211 324-ball ftBGA (19x19 mm) 211 271 © 2013 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1-1 DS1002 Introduction_01.5 Introduction MachXO Family Data Sheet The devices use look-up tables (LUTs) and embedded block memories traditionally associated with FPGAs for flexible and efficient logic implementation. Through non-volatile technology, the devices provide the single-chip, highsecurity, instant-on capabilities traditionally associated with CPLDs. Finally, advanced process technology and careful design will provide the high pin-to-pin performance also associated with CPLDs. The ispLEVER® design tools from Lattice allow complex designs to be efficiently implemented using the MachXO family of devices. Popular logic synthesis tools provide synthesis library support for MachXO. The ispLEVER tools use the synthesis tool output along with the constraints from its floor planning tools to place and route the design in the MachXO device. The ispLEVER tool extracts the timing from the routing and back-annotates it into the design for timing verification. 1-2 MachXO Family Data Sheet Architecture June 2013 Data Sheet DS1002 Architecture Overview The MachXO family architecture contains an array of logic blocks surrounded by Programmable I/O (PIO). Some devices in this family have sysCLOCK PLLs and blocks of sysMEM™ Embedded Block RAM (EBRs). Figures 2-1, 2-2, and 2-3 show the block diagrams of the various family members. The logic blocks are arranged in a two-dimensional grid with rows and columns. The EBR blocks are arranged in a column to the left of the logic array. The PIO cells are located at the periphery of the device, arranged into Banks. The PIOs utilize a flexible I/O buffer referred to as a sysIO interface that supports operation with a variety of interface standards. The blocks are connected with many vertical and horizontal routing channel resources. The place and route software tool automatically allocates these routing resources. There are two kinds of logic blocks, the Programmable Functional Unit (PFU) and the Programmable Functional unit without RAM (PFF). The PFU contains the building blocks for logic, arithmetic, RAM, ROM, and register functions. The PFF block contains building blocks for logic, arithmetic, ROM, and register functions. Both the PFU and PFF blocks are optimized for flexibility, allowing complex designs to be implemented quickly and effectively. Logic blocks are arranged in a two-dimensional array. Only one type of block is used per row. In the MachXO family, the number of sysIO Banks varies by device. There are different types of I/O Buffers on different Banks. See the details in later sections of this document. The sysMEM EBRs are large, dedicated fast memory blocks; these blocks are found only in the larger devices. These blocks can be configured as RAM, ROM or FIFO. FIFO support includes dedicated FIFO pointer and flag “hard” control logic to minimize LUT use. The MachXO registers in PFU and sysI/O can be configured to be SET or RESET. After power up and device is configured, the device enters into user mode with these registers SET/RESET according to the configuration setting, allowing device entering to a known state for predictable system function. The MachXO architecture provides up to two sysCLOCK™ Phase Locked Loop (PLL) blocks on larger devices. These blocks are located at either end of the memory blocks. The PLLs have multiply, divide, and phase shifting capabilities that are used to manage the frequency and phase relationships of the clocks. Every device in the family has a JTAG Port that supports programming and configuration of the device as well as access to the user logic. The MachXO devices are available for operation from 3.3V, 2.5V, 1.8V, and 1.2V power supplies, providing easy integration into the overall system. © 2013 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 2-1 DS1002 Architecture_01.5 Architecture MachXO Family Data Sheet Figure 2-1. Top View of the MachXO1200 Device1 PIOs Arranged into sysIO Banks Programmable Functional Units with RAM (PFUs) sysMEM Embedded Block RAM (EBR) Programmable Functional Units without RAM (PFFs) sysCLOCK PLL JTAG Port 1. Top view of the MachXO2280 device is similar but with higher LUT count, two PLLs, and three EBR blocks. Figure 2-2. Top View of the MachXO640 Device PIOs Arranged into sysIO Banks Programmable Function Units without RAM (PFFs) Programmable Function Units with RAM (PFUs) JTAG Port 2-2 Architecture MachXO Family Data Sheet Figure 2-3. Top View of the MachXO256 Device Programmable Function Units without RAM (PFFs) JTAG Port PIOs Arranged into sysIO Banks Programmable Function Units with RAM (PFUs) PFU Blocks The core of the MachXO devices consists of PFU and PFF blocks. The PFUs can be programmed to perform Logic, Arithmetic, Distributed RAM, and Distributed ROM functions. PFF blocks can be programmed to perform Logic, Arithmetic, and Distributed ROM functions. Except where necessary, the remainder of this data sheet will use the term PFU to refer to both PFU and PFF blocks. Each PFU block consists of four interconnected Slices, numbered 0-3 as shown in Figure 2-4. There are 53 inputs and 25 outputs associated with each PFU block. Figure 2-4. PFU Diagram From Routing FCIN LUT4 & CARRY LUT4 & CARRY LUT4 & CARRY Slice 0 D FF/ Latch D FF/ Latch LUT4 & CARRY LUT4 & CARRY Slice 1 D FF/ Latch LUT4 & CARRY LUT4 & CARRY D FF/ Latch FCO Slice 3 Slice 2 D FF/ Latch LUT4 & CARRY D FF/ Latch D FF/ Latch D FF/ Latch To Routing Slice Each Slice contains two LUT4 lookup tables feeding two registers (programmed to be in FF or Latch mode), and some associated logic that allows the LUTs to be combined to perform functions such as LUT5, LUT6, LUT7, and LUT8. There is control logic to perform set/reset functions (programmable as synchronous/asynchronous), clock select, chip-select, and wider RAM/ROM functions. Figure 2-5 shows an overview of the internal logic of the Slice. The registers in the Slice can be configured for positive/negative and edge/level clocks. 2-3 Architecture MachXO Family Data Sheet There are 14 input signals: 13 signals from routing and one from the carry-chain (from the adjacent Slice/PFU). There are 7 outputs: 6 to the routing and one to the carry-chain (to the adjacent Slice/PFU). Table 2-1 lists the signals associated with each Slice. Figure 2-5. Slice Diagram To Adjacent Slice/PFU Slice OFX1 A1 B1 C1 D1 CO LUT4 & CARRY F1 F D SUM FF/ Latch Fast Connection to I/O Cell* Q1 CI From Routing To Routing M1 M0 CO A0 OFX0 Fast Connection to I/O Cell* LUT Expansion Mux B0 C0 D0 LUT4 & CARRY F0 F SUM OFX0 CI Control Signals selected and inverted per Slice in routing D FF/ Latch Q0 CE CLK LSR From Adjacent Slice/PFU Notes: Some inter-Slice signals are not shown. * Only PFUs at the edges have fast connections to the I/O cell. Table 2-1. Slice Signal Descriptions Function Type Signal Names Description Input Data signal A0, B0, C0, D0 Inputs to LUT4 Input Data signal A1, B1, C1, D1 Inputs to LUT4 Input Multi-purpose M0/M1 Input Control signal CE Multipurpose Input Clock Enable Input Control signal LSR Local Set/Reset Input Control signal CLK System Clock Input Inter-PFU signal FCIN Fast Carry In1 Output Data signals F0, F1 LUT4 output register bypass signals Output Data signals Q0, Q1 Output Data signals OFX0 Output of a LUT5 MUX Output Data signals OFX1 Output of a LUT6, LUT7, LUT82 MUX depending on the Slice Output Inter-PFU signal FCO Fast Carry Out1 Register Outputs 1. See Figure 2-4 for connection details. 2. Requires two PFUs. 2-4 Architecture MachXO Family Data Sheet Modes of Operation Each Slice is capable of four modes of operation: Logic, Ripple, RAM, and ROM. The Slice in the PFF is capable of all modes except RAM. Table 2-2 lists the modes and the capability of the Slice blocks. Table 2-2. Slice Modes Logic Ripple RAM ROM PFU Slice LUT 4x2 or LUT 5x1 2-bit Arithmetic Unit SP 16x2 ROM 16x1 x 2 PFF Slice LUT 4x2 or LUT 5x1 2-bit Arithmetic Unit N/A ROM 16x1 x 2 Logic Mode: In this mode, the LUTs in each Slice are configured as 4-input combinatorial lookup tables (LUT4). A LUT4 can have 16 possible input combinations. Any logic function with four inputs can be generated by programming this lookup table. Since there are two LUT4s per Slice, a LUT5 can be constructed within one Slice. Larger lookup tables such as LUT6, LUT7, and LUT8 can be constructed by concatenating other Slices. Ripple Mode: Ripple mode allows the efficient implementation of small arithmetic functions. In ripple mode, the following functions can be implemented by each Slice: • • • • • • • Addition 2-bit Subtraction 2-bit Add/Subtract 2-bit using dynamic control Up counter 2-bit Down counter 2-bit Ripple mode multiplier building block Comparator functions of A and B inputs - A greater-than-or-equal-to B - A not-equal-to B - A less-than-or-equal-to B Two additional signals, Carry Generate and Carry Propagate, are generated per Slice in this mode, allowing fast arithmetic functions to be constructed by concatenating Slices. RAM Mode: In this mode, distributed RAM can be constructed using each LUT block as a 16x2-bit memory. Through the combination of LUTs and Slices, a variety of different memories can be constructed. The ispLEVER design tool supports the creation of a variety of different size memories. Where appropriate, the software will construct these using distributed memory primitives that represent the capabilities of the PFU. Table 2-3 shows the number of Slices required to implement different distributed RAM primitives. Figure 2-6 shows the distributed memory primitive block diagrams. Dual port memories involve the pairing of two Slices. One Slice functions as the read-write port, while the other companion Slice supports the read-only port. For more information on RAM mode in MachXO devices, please see details of additional technical documentation at the end of this data sheet. Table 2-3. Number of Slices Required For Implementing Distributed RAM SPR16x2 DPR16x2 1 2 Number of Slices Note: SPR = Single Port RAM, DPR = Dual Port RAM 2-5 Architecture MachXO Family Data Sheet Figure 2-6. Distributed Memory Primitives SPR16x2 AD0 AD1 AD2 AD3 DPR16x2 DO0 DI0 DI1 WRE CK DO1 WAD0 WAD1 WAD2 WAD3 RAD0 RAD1 RAD2 RAD3 DI0 DI1 WCK WRE RDO0 RDO1 WDO0 WDO1 ROM16x1 AD0 AD1 AD2 AD3 DO0 ROM Mode: The ROM mode uses the same principal as the RAM modes, but without the Write port. Pre-loading is accomplished through the programming interface during configuration. PFU Modes of Operation Slices can be combined within a PFU to form larger functions. Table 2-4 tabulates these modes and documents the functionality possible at the PFU level. Table 2-4. PFU Modes of Operation Ripple RAM ROM LUT 4x8 or MUX 2x1 x 8 Logic 2-bit Add x 4 SPR16x2 x 4 DPR16x2 x 2 ROM16x1 x 8 LUT 5x4 or MUX 4x1 x 4 2-bit Sub x 4 SPR16x4 x 2 DPR16x4 x 1 ROM16x2 x 4 LUT 6x 2 or MUX 8x1 x 2 2-bit Counter x 4 SPR16x8 x 1 ROM16x4 x 2 LUT 7x1 or MUX 16x1 x 1 2-bit Comp x 4 ROM16x8 x 1 Routing There are many resources provided in the MachXO devices to route signals individually or as buses with related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) segments. The inter-PFU connections are made with three different types of routing resources: x1 (spans two PFUs), x2 (spans three PFUs) and x6 (spans seven PFUs). The x1, x2, and x6 connections provide fast and efficient connections in the horizontal and vertical directions. 2-6 Architecture MachXO Family Data Sheet The ispLEVER design tool takes the output of the synthesis tool and places and routes the design. Generally, the place and route tool is completely automatic, although an interactive routing editor is available to optimize the design. Clock/Control Distribution Network The MachXO family of devices provides global signals that are available to all PFUs. These signals consist of four primary clocks and four secondary clocks. Primary clock signals are generated from four 16:1 muxes as shown in Figure 2-7 and Figure 2-8. The available clock sources for the MachXO256 and MachXO640 devices are four dual function clock pins and 12 internal routing signals. The available clock sources for the MachXO1200 and MachXO2280 devices are four dual function clock pins, up to nine internal routing signals and up to six PLL outputs. Figure 2-7. Primary Clocks for MachXO256 and MachXO640 Devices 12 4 16:1 16:1 16:1 16:1 Routing Clock Pads 2-7 Primary Clock 0 Primary Clock 1 Primary Clock 2 Primary Clock 3 Architecture MachXO Family Data Sheet Figure 2-8. Primary Clocks for MachXO1200 and MachXO2280 Devices Up to 9 4 Up to 6 16:1 Primary Clock 0 Primary Clock 1 16:1 16:1 16:1 Routing Clock Pads Primary Clock 2 Primary Clock 3 PLL Outputs Four secondary clocks are generated from four 16:1 muxes as shown in Figure 2-9. Four of the secondary clock sources come from dual function clock pins and 12 come from internal routing. Figure 2-9. Secondary Clocks for MachXO Devices 12 4 16:1 16:1 Secondary (Control) Clocks 16:1 16:1 Routing Clock Pads 2-8 Architecture MachXO Family Data Sheet sysCLOCK Phase Locked Loops (PLLs) The MachXO1200 and MachXO2280 provide PLL support. The source of the PLL input divider can come from an external pin or from internal routing. There are four sources of feedback signals to the feedback divider: from CLKINTFB (internal feedback port), from the global clock nets, from the output of the post scalar divider, and from the routing (or from an external pin). There is a PLL_LOCK signal to indicate that the PLL has locked on to the input clock signal. Figure 2-10 shows the sysCLOCK PLL diagram. The setup and hold times of the device can be improved by programming a delay in the feedback or input path of the PLL which will advance or delay the output clock with reference to the input clock. This delay can be either programmed during configuration or can be adjusted dynamically. In dynamic mode, the PLL may lose lock after adjustment and not relock until the tLOCK parameter has been satisfied. Additionally, the phase and duty cycle block allows the user to adjust the phase and duty cycle of the CLKOS output. The sysCLOCK PLLs provide the ability to synthesize clock frequencies. Each PLL has four dividers associated with it: input clock divider, feedback divider, post scalar divider, and secondary clock divider. The input clock divider is used to divide the input clock signal, while the feedback divider is used to multiply the input clock signal. The post scalar divider allows the VCO to operate at higher frequencies than the clock output, thereby increasing the frequency range. The secondary divider is used to derive lower frequency outputs. Figure 2-10. PLL Diagram Dynamic Delay Adjustment LOCK RST CLKI (from routing or external pin) Input Clock Divider (CLKI) Delay Adjust Voltage Controlled VCO Oscillator Post Scalar Divider (CLKOP) Phase/Duty Select CLKOS CLKOP CLKFB (from Post Scalar Divider output, clock net, routing/external pin or CLKINTFB port Secondary Clock Divider (CLKOK) Feedback Divider (CLKFB) CLKOK CLKINTFB (internal feedback) Figure 2-11 shows the available macros for the PLL. Table 2-5 provides signal description of the PLL Block. Figure 2-11. PLL Primitive RST CLKI CLKOP CLKFB CLKOS DDA MODE EHXPLLC DDAIZR CLKOK LOCK DDAILAG CLKINTFB DDAIDEL[2:0] 2-9 Architecture MachXO Family Data Sheet Table 2-5. PLL Signal Descriptions Signal CLKI I/O Description I Clock input from external pin or routing I PLL feedback input from PLL output, clock net, routing/external pin or internal feedback from CLKINTFB port RST I “1” to reset the input clock divider CLKOS O PLL output clock to clock tree (phase shifted/duty cycle changed) CLKFB CLKOP O PLL output clock to clock tree (No phase shift) CLKOK O PLL output to clock tree through secondary clock divider LOCK O “1” indicates PLL LOCK to CLKI CLKINTFB O Internal feedback source, CLKOP divider output before CLOCKTREE DDAMODE I Dynamic Delay Enable. “1”: Pin control (dynamic), “0”: Fuse Control (static) DDAIZR I Dynamic Delay Zero. “1”: delay = 0, “0”: delay = on DDAILAG I Dynamic Delay Lag/Lead. “1”: Lag, “0”: Lead DDAIDEL[2:0] I Dynamic Delay Input For more information on the PLL, please see details of additional technical documentation at the end of this data sheet. sysMEM Memory The MachXO1200 and MachXO2280 devices contain sysMEM Embedded Block RAMs (EBRs). The EBR consists of a 9-Kbit RAM, with dedicated input and output registers. sysMEM Memory Block The sysMEM block can implement single port, dual port, pseudo dual port, or FIFO memories. Each block can be used in a variety of depths and widths as shown in Table 2-6. Table 2-6. sysMEM Block Configurations Memory Mode Configurations Single Port 8,192 x 1 4,096 x 2 2,048 x 4 1,024 x 9 512 x 18 256 x 36 True Dual Port 8,192 x 1 4,096 x 2 2,048 x 4 1,024 x 9 512 x 18 Pseudo Dual Port 8,192 x 1 4,096 x 2 2,048 x 4 1,024 x 9 512 x 18 256 x 36 FIFO 8,192 x 1 4,096 x 2 2,048 x 4 1,024 x 9 512 x 18 256 x 36 2-10 Architecture MachXO Family Data Sheet Bus Size Matching All of the multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB word 0 to MSB word 0, LSB word 1 to MSB word 1 and so on. Although the word size and number of words for each port varies, this mapping scheme applies to each port. RAM Initialization and ROM Operation If desired, the contents of the RAM can be pre-loaded during device configuration. By preloading the RAM block during the chip configuration cycle and disabling the write controls, the sysMEM block can also be utilized as a ROM. Memory Cascading Larger and deeper blocks of RAMs can be created using EBR sysMEM Blocks. Typically, the Lattice design tools cascade memory transparently, based on specific design inputs. Single, Dual, Pseudo-Dual Port and FIFO Modes Figure 2-12 shows the five basic memory configurations and their input/output names. In all the sysMEM RAM modes, the input data and address for the ports are registered at the input of the memory array. The output data of the memory is optionally registered at the memory array output. Figure 2-12. sysMEM Memory Primitives AD[12:0] DI[35:0] CLK CE RST WE CS[2:0] EBR ADA[12:0] DIA[17:0] CLKA CEA DO[35:0] RSTA WEA CSA[2:0] DOA[17:0] True Dual Port RAM Single Port RAM AD[12:0] CLK CE RST CS[2:0] EBR ADW[12:0] DI[35:0] CLKW CEW DO[35:0] WE RST CS[2:0] ROM DI[35:0] CLKW RSTA WE CEW EBR ADB[12:0] DIB[17:0] CEB CLKB RSTB WEB CSB[2:0] DOB[17:0] ADR[12:0] EBR DO[35:0] CER CLKR Pseudo-Dual Port RAM EBR FIFO 2-11 DO[35:0] CLKR RSTB RE RCE FF AF EF AE Architecture MachXO Family Data Sheet The EBR memory supports three forms of write behavior for single or dual port operation: 1. Normal – data on the output appears only during the read cycle. During a write cycle, the data (at the current address) does not appear on the output. This mode is supported for all data widths. 2. Write Through – a copy of the input data appears at the output of the same port. This mode is supported for all data widths. 3. Read-Before-Write – when new data is being written, the old contents of the address appears at the output. This mode is supported for x9, x18 and x36 data widths. FIFO Configuration The FIFO has a write port with Data-in, CEW, WE and CLKW signals. There is a separate read port with Data-out, RCE, RE and CLKR signals. The FIFO internally generates Almost Full, Full, Almost Empty and Empty Flags. The Full and Almost Full flags are registered with CLKW. The Empty and Almost Empty flags are registered with CLKR. The range of programming values for these flags are in Table 2-7. Table 2-7. Programmable FIFO Flag Ranges Flag Name Programming Range 1 to (up to 2N-1) Full (FF) Almost Full (AF) 1 to Full-1 Almost Empty (AE) 1 to Full-1 Empty (EF) 0 N = Address bit width The FIFO state machine supports two types of reset signals: RSTA and RSTB. The RSTA signal is a global reset that clears the contents of the FIFO by resetting the read/write pointer and puts the FIFO flags in their initial reset state. The RSTB signal is used to reset the read pointer. The purpose of this reset is to retransmit the data that is in the FIFO. In these applications it is important to keep careful track of when a packet is written into or read from the FIFO. Memory Core Reset The memory array in the EBR utilizes latches at the A and B output ports. These latches can be reset asynchronously. RSTA and RSTB are local signals, which reset the output latches associated with Port A and Port B respectively. The Global Reset (GSRN) signal resets both ports. The output data latches and associated resets for both ports are as shown in Figure 2-13. 2-12 Architecture MachXO Family Data Sheet Figure 2-13. Memory Core Reset Memory Core D SET Q Port A[17:0] LCLR Output Data Latches D SET Q Port B[17:0] LCLR RSTA RSTB GSRN Programmable Disable For further information on the sysMEM EBR block, see the details of additional technical documentation at the end of this data sheet. EBR Asynchronous Reset EBR asynchronous reset or GSR (if used) can only be applied if all clock enables are low for a clock cycle before the reset is applied and released a clock cycle after the reset is released, as shown in Figure 2-14. The GSR input to the EBR is always asynchronous. Figure 2-14. EBR Asynchronous Reset (Including GSR) Timing Diagram Reset Clock Clock Enable If all clock enables remain enabled, the EBR asynchronous reset or GSR may only be applied and released after the EBR read and write clock inputs are in a steady state condition for a minimum of 1/fMAX (EBR clock). The reset release must adhere to the EBR synchronous reset setup time before the next active read or write clock edge. If an EBR is pre-loaded during configuration, the GSR input must be disabled or the release of the GSR during device Wake Up must occur before the release of the device I/Os becoming active. These instructions apply to all EBR RAM, ROM and FIFO implementations. For the EBR FIFO mode, the GSR signal is always enabled and the WE and RE signals act like the clock enable signals in Figure 2-14. The reset timing rules apply to the RPReset input vs the RE input and the RST input vs. the WE and RE inputs. Both RST and RPReset are always asynchronous EBR inputs. Note that there are no reset restrictions if the EBR synchronous reset is used and the EBR GSR input is disabled 2-13 Architecture MachXO Family Data Sheet PIO Groups On the MachXO devices, PIO cells are assembled into two different types of PIO groups, those with four PIO cells and those with six PIO cells. PIO groups with four IOs are placed on the left and right sides of the device while PIO groups with six IOs are placed on the top and bottom. The individual PIO cells are connected to their respective sysIO buffers and PADs. On all MachXO devices, two adjacent PIOs can be joined to provide a complementary Output driver pair. The I/O pin pairs are labeled as "T" and "C" to distinguish between the true and complement pins. The MachXO1200 and MachXO2280 devices contain enhanced I/O capability. All PIO pairs on these larger devices can implement differential receivers. In addition, half of the PIO pairs on the left and right sides of these devices can be configured as LVDS transmit/receive pairs. PIOs on the top of these larger devices also provide PCI support. Figure 2-15. Group of Four Programmable I/O Cells This structure is used on the left and right of MachXO devices PIO A PADA "T" PIO B PADB "C" PIO C PADC "T" PIO D PADD "C" Four PIOs Figure 2-16. Group ofþSix Programmable I/O Cells This structure is used on the top and bottom of MachXO devices PIO A PADA "T" PIO B PADB "C" PIO C PADC "T" PIO D PADD "C" PIO E PADE "T" PIO F PADF "C" Six PIOs PIO The PIO blocks provide the interface between the sysIO buffers and the internal PFU array blocks. These blocks receive output data from the PFU array and a fast output data signal from adjacent PFUs. The output data and fast 2-14 Architecture MachXO Family Data Sheet output data signals are multiplexed and provide a single signal to the I/O pin via the sysIO buffer. Figure 2-17 shows the MachXO PIO logic. The tristate control signal is multiplexed from the output data signals and their complements. In addition a global signal (TSALL) from a dedicated pad can be used to tristate the sysIO buffer. The PIO receives an input signal from the pin via the sysIO buffer and provides this signal to the core of the device. In addition there are programmable elements that can be utilized by the design tools to avoid positive hold times. Figure 2-17. MachXO PIO Block Diagram From Routing TS TSALL From Routing TO sysIO Buffer Fast Output Data signal DO PAD 1 Input Data Signal 2 Programmable Delay Elements 3 + 4- Note: Buffer 1 tracks with VCCAUX Buffer 2 tracks with VCCIO. Buffer 3 tracks with internal 1.2V VREF. Buffer 4 is available in MachXO1200 and MachXO2280 devices only. From Complementary Pad sysIO Buffer Each I/O is associated with a flexible buffer referred to as a sysIO buffer. These buffers are arranged around the periphery of the device in groups referred to as Banks. The sysIO buffers allow users to implement the wide variety of standards that are found in today’s systems including LVCMOS, TTL, BLVDS, LVDS and LVPECL. In the MachXO devices, single-ended output buffers and ratioed input buffers (LVTTL, LVCMOS and PCI) are powered using VCCIO. In addition to the Bank VCCIO supplies, the MachXO devices have a VCC core logic power supply, and a VCCAUX supply that powers up a variety of internal circuits including all the differential and referenced input buffers. MachXO256 and MachXO640 devices contain single-ended input buffers and single-ended output buffers with complementary outputs on all the I/O Banks. MachXO1200 and MachXO2280 devices contain two types of sysIO buffer pairs. 1. Top and Bottom sysIO Buffer Pairs The sysIO buffer pairs in the top and bottom Banks of the device consist of two single-ended output drivers and two sets of single-ended input buffers (for ratioed or absolute input levels). The I/O pairs on the top and bottom 2-15 Architecture MachXO Family Data Sheet of the devices also support differential input buffers. PCI clamps are available on the top Bank I/O buffers. The PCI clamp is enabled after VCC, VCCAUX, and VCCIO are at valid operating levels and the device has been configured.  The two pads in the pair are described as “true” and “comp”, where the true pad is associated with the positive side of the differential input buffer and the comp (complementary) pad is associated with the negative side of the differential input buffer. 2. Left and Right sysIO Buffer Pairs The sysIO buffer pairs in the left and right Banks of the device consist of two single-ended output drivers and two sets of single-ended input buffers (supporting ratioed and absolute input levels). The devices also have a differential driver per output pair. The referenced input buffer can also be configured as a differential input buffer. In these Banks the two pads in the pair are described as “true” and “comp”, where the true pad is associated with the positive side of the differential I/O, and the comp (complementary) pad is associated with the negative side of the differential I/O. Typical I/O Behavior During Power-up The internal power-on-reset (POR) signal is deactivated when VCC and VCCAUX have reached satisfactory levels. After the POR signal is deactivated, the FPGA core logic becomes active. It is the user’s responsibility to ensure that all VCCIO Banks are active with valid input logic levels to properly control the output logic states of all the I/O Banks that are critical to the application. The default configuration of the I/O pins in a blank device is tri-state with a weak pull-up to VCCIO. The I/O pins will maintain the blank configuration until VCC, VCCAUX and VCCIO have reached satisfactory levels at which time the I/Os will take on the user-configured settings. The VCC and VCCAUX supply the power to the FPGA core fabric, whereas the VCCIO supplies power to the I/O buffers. In order to simplify system design while providing consistent and predictable I/O behavior, the I/O buffers should be powered up along with the FPGA core fabric. Therefore, VCCIO supplies should be powered up before or together with the VCC and VCCAUX supplies Supported Standards The MachXO sysIO buffer supports both single-ended and differential standards. Single-ended standards can be further subdivided into LVCMOS and LVTTL. The buffer supports the LVTTL, LVCMOS 1.2, 1.5, 1.8, 2.5, and 3.3V standards. In the LVCMOS and LVTTL modes, the buffer has individually configurable options for drive strength, bus maintenance (weak pull-up, weak pull-down, bus-keeper latch or none) and open drain. BLVDS and LVPECL output emulation is supported on all devices. The MachXO1200 and MachXO2280 support on-chip LVDS output buffers on approximately 50% of the I/Os on the left and right Banks. Differential receivers for LVDS, BLVDS and LVPECL are supported on all Banks of MachXO1200 and MachXO2280 devices. PCI support is provided in the top Banks of the MachXO1200 and MachXO2280 devices. Table 2-8 summarizes the I/O characteristics of the devices in the MachXO family. Tables 2-9 and 2-10 show the I/O standards (together with their supply and reference voltages) supported by the MachXO devices. For further information on utilizing the sysIO buffer to support a variety of standards please see the details of additional technical documentation at the end of this data sheet. 2-16 Architecture MachXO Family Data Sheet Table 2-8. I/O Support Device by Device MachXO256 Number of I/O Banks MachXO640 MachXO1200 MachXO2280 2 4 8 8 Single-ended  (all I/O Banks) Single-ended  (all I/O Banks) Single-ended  (all I/O Banks) Single-ended  (all I/O Banks) Differential Receivers (all I/O Banks) Differential Receivers (all I/O Banks) Single-ended buffers with complementary outputs (all I/O Banks) Single-ended buffers with complementary outputs (all I/O Banks) Type of Input Buffers Single-ended buffers with complementary outputs (all I/O Banks) Single-ended buffers with complementary outputs (all I/O Banks) Types of Output Buffers Differential buffers with Differential buffers with true LVDS outputs (50% true LVDS outputs (50% on left and right side) on left and right side) Differential Output  Emulation Capability All I/O Banks All I/O Banks All I/O Banks All I/O Banks PCI Support No No Top side only Top side only Table 2-9. Supported Input Standards VCCIO (Typ.) Input Standard 3.3V 2.5V 1.8V 1.5V 1.2V Single Ended Interfaces LVTTL Yes Yes Yes Yes Yes LVCMOS33 Yes Yes Yes Yes Yes LVCMOS25 Yes Yes Yes Yes Yes LVCMOS18 Yes LVCMOS15 LVCMOS12 1 PCI Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Differential Interfaces BLVDS2, LVDS2, LVPECL2, RSDS2 Yes 1. Top Banks of MachXO1200 and MachXO2280 devices only. 2. MachXO1200 and MachXO2280 devices only. 2-17 Architecture MachXO Family Data Sheet Table 2-10. Supported Output Standards Output Standard Drive VCCIO (Typ.) Single-ended Interfaces LVTTL 4mA, 8mA, 12mA, 16mA 3.3 LVCMOS33 4mA, 8mA, 12mA, 14mA 3.3 LVCMOS25 4mA, 8mA, 12mA, 14mA 2.5 LVCMOS18 4mA, 8mA, 12mA, 14mA 1.8 LVCMOS15 4mA, 8mA 1.5 LVCMOS12 2mA, 6mA 1.2 LVCMOS33, Open Drain 4mA, 8mA, 12mA, 14mA — LVCMOS25, Open Drain 4mA, 8mA, 12mA, 14mA — LVCMOS18, Open Drain 4mA, 8mA, 12mA, 14mA — LVCMOS15, Open Drain 4mA, 8mA — LVCMOS12, Open Drain 2mA, 6mA — N/A 3.3 N/A 2.5 BLVDS, RSDS N/A 2.5 LVPECL2 N/A 3.3 PCI333 Differential Interfaces LVDS1, 2 2 1. MachXO1200 and MachXO2280 devices have dedicated LVDS buffers. 2. These interfaces can be emulated with external resistors in all devices. 3. Top Banks of MachXO1200 and MachXO2280 devices only. sysIO Buffer Banks The number of Banks vary between the devices of this family. Eight Banks surround the two larger devices, the MachXO1200 and MachXO2280 (two Banks per side). The MachXO640 has four Banks (one Bank per side). The smallest member of this family, the MachXO256, has only two Banks. Each sysIO buffer Bank is capable of supporting multiple I/O standards. Each Bank has its own I/O supply voltage (VCCIO) which allows it to be completely independent from the other Banks. Figure 2-18, Figure 2-18, Figure 2-20 and Figure 2-21 shows the sysIO Banks and their associated supplies for all devices. 2-18 Architecture MachXO Family Data Sheet Figure 2-18. MachXO2280 Banks Bank 7 Bank 1 36 1 34 1 1 Bank 6 34 Bank 4 1 GND 31 VCCIO4 Bank 5 VCCIO1 GND VCCIO5 1 GND 33 Bank 3 GND 1 Bank 2 VCCIO6 35 GND GND Bank 0 VCCIO1 VCCIO7 GND VCCIO0 1 1 VCCIO2 GND VCCIO3 GND 33 35 Figure 2-19. MachXO1200 Banks Bank 7 Bank 1 30 1 26 1 1 Bank 6 Bank 5 20 1 2-19 Bank 4 GND 1 VCCIO4 28 GND GND 1 Bank 3 VCCIO6 24 26 VCCIO5 GND Bank 0 Bank 2 VCCIO7 GND VCCIO0 1 1 28 29 VCCIO2 GND VCCIO3 GND Architecture MachXO Family Data Sheet Figure 2-20. MachXO640 Banks Bank 3 40 VCCO2 GND 40 37 Bank 2 1 V CCO1 GND GND 42 1 Bank 0 Bank 1 V CCO3 GND V CCO0 1 1 Figure 2-21. MachXO256 Banks V CCO0 1 1 Bank 0 Bank 1 GND 41 37 GND V CCO1 Hot Socketing The MachXO devices have been carefully designed to ensure predictable behavior during power-up and powerdown. Leakage into I/O pins is controlled to within specified limits. This allows for easy integration with the rest of 2-20 Architecture MachXO Family Data Sheet the system. These capabilities make the MachXO ideal for many multiple power supply and hot-swap applications. Sleep Mode The MachXO “C” devices (VCC = 1.8/2.5/3.3V) have a sleep mode that allows standby current to be reduced dramatically during periods of system inactivity. Entry and exit to Sleep mode is controlled by the SLEEPN pin. During Sleep mode, the logic is non-operational, registers and EBR contents are not maintained, and I/Os are tristated. Do not enter Sleep mode during device programming or configuration operation. In Sleep mode, power supplies are in their normal operating range, eliminating the need for external switching of power supplies. Table 2-11 compares the characteristics of Normal, Off and Sleep modes. Table 2-11. Characteristics of Normal, Off and Sleep Modes Characteristic SLEEPN Pin Static Icc I/O Leakage Power Supplies VCC/VCCIO/VCCAUX Normal Off Sleep High — Low Typical L) 188 0pF — VOL VOH VCCIO/2 VOL VCCIO/2 VOH LVTTL + LVCMOS (H -> Z) VOH - 0.15 VOL LVTTL + LVCMOS (L -> Z) VOL - 0.15 VOH Note: Output test conditions for all other interfaces are determined by the respective standards. 3-17 MachXO Family Data Sheet Pinout Information June 2013 Data Sheet DS1002 Signal Descriptions Signal Name I/O Descriptions General Purpose [Edge] indicates the edge of the device on which the pad is located. Valid edge designations are L (Left), B (Bottom), R (Right), T (Top). [Row/Column Number] indicates the PFU row or the column of the device on which the PIO Group exists. When Edge is T (Top) or (Bottom), only need to specify Row Number. When Edge is L (Left) or R (Right), only need to specify Column Number. P[Edge] [Row/Column  Number]_[A/B/C/D/E/F] [A/B/C/D/E/F] indicates the PIO within the group to which the pad is connected. I/O Some of these user programmable pins are shared with special function pins. When not used as special function pins, these pins can be programmed as I/Os for user logic. During configuration of the user-programmable I/Os, the user has an option to tri-state the I/Os and enable an internal pull-up resistor. This option also applies to unused pins (or those not bonded to a package pin). The default during configuration is for user-programmable I/Os to be tri-stated with an internal pull-up resistor enabled. When the device is erased, I/Os will be tri-stated with an internal pull-up resistor enabled. GSRN I Global RESET signal (active low). Dedicated pad, when not in use it can be used as an I/O pin. TSALL I TSALL is a dedicated pad for the global output enable signal. When TSALL is high all the outputs are tristated. It is a dual function pin. When not in use, it can be used as an I/O pin. NC — No connect. GND — GND - Ground. Dedicated pins. VCC — VCC - The power supply pins for core logic. Dedicated pins. VCCAUX — VCCAUX - the Auxiliary power supply pin. This pin powers up a variety of internal circuits including all the differential and referenced input buffers. Dedicated pins. VCCIOx — VCCIO - The power supply pins for I/O Bank x. Dedicated pins. 1 SLEEPN I Sleep Mode pin - Active low sleep pin.þ When this pin is held high, the device operates normally.þ This pin has a weak internal pull-up, but when unused, an external pull-up to VCC is recommended. When driven low, the device moves into Sleep mode after a specified time. PLL and Clock Functions (Used as user programmable I/O pins when not used for PLL or clock pins) [LOC][0]_PLL[T, C]_IN — Reference clock (PLL) input Pads: [LOC] indicates location. Valid designations are ULM (Upper PLL) and LLM (Lower PLL). T = true and C = complement. [LOC][0]_PLL[T, C]_FB — Optional feedback (PLL) input Pads: [LOC] indicates location. Valid designations are ULM (Upper PLL) and LLM (Lower PLL). T = true and C = complement. PCLK [n]_[1:0] — Primary Clock Pads, n per side. Test and Programming (Dedicated pins) TMS I Test Mode Select input pin, used to control the 1149.1 state machine. TCK I Test Clock input pin, used to clock the 1149.1 state machine. TDI I Test Data input pin, used to load data into the device using an 1149.1 state machine. TDO O Output pin -Test Data output pin used to shift data out of the device using 1149.1. 1. Applies to MachXO “C” devices only. NC for “E” devices. © 2013 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 4-1 DS1002 Pinouts_01.9 Pinout Information MachXO Family Data Sheet Pin Information Summary LCMXO256C/E LCMXO640C/E 100 TQFP 100 csBGA 100 TQFP 144 TQFP 100 csBGA 132 csBGA 256 caBGA / 256 ftBGA Single Ended User I/O 78 78 74 113 74 101 159 Differential Pair User I/O1 38 38 17 43 17 42 79 Muxed 6 6 6 6 6 6 6 TAP 4 4 4 4 4 4 4 Pin Type Dedicated (Total Without Supplies) 5 5 5 5 5 5 5 VCC 2 2 2 4 2 4 4 VCCAUX VCCIO 1 1 1 2 1 2 2 Bank0 3 3 2 2 2 2 4 Bank1 3 3 2 2 2 2 4 Bank2 — — 2 2 2 2 4 Bank3 — — 2 2 2 2 4 8 8 10 12 10 12 18 GND NC Single Ended/Differential I/O per Bank 0 0 0 0 0 0 52 Bank0 41/20 41/20 18/5 29/10 18/5 26/11 42/21 Bank1 37/18 37/18 21/4 30/11 21/4 27/12 40/20 Bank2 — — 14/2 24/9 14/2 21/9 36/18 Bank3 — — 21/6 30/13 21/6 27/10 40/20 1. These devices support emulated LVDS outputs.þLVDS inputs are not supported. LCMXO1200C/E Pin Type LCMXO2280C/E 256 caBGA / 132 csBGA 256 ftBGA 100 TQFP 144 TQFP Single Ended User I/O 73 113 101 Differential Pair User I/O1 27 48 42 100 TQFP 144 TQFP 132 csBGA 256 caBGA / 256 ftBGA 211 73 113 101 211 271 105 30 47 41 105 134 324 ftBGA Muxed 6 6 6 6 6 6 6 6 6 TAP 4 4 4 4 4 4 4 4 4 Dedicated (Total Without Supplies) 5 5 5 5 5 5 5 5 5 VCC 4 4 4 4 2 4 4 4 6 VCCAUX 2 2 2 2 2 2 2 2 2 Bank0 1 1 1 2 1 1 1 2 2 Bank1 1 1 1 2 1 1 1 2 2 Bank2 1 1 1 2 1 1 1 2 2 Bank3 1 1 1 2 1 1 1 2 2 Bank4 1 1 1 2 1 1 1 2 2 Bank5 1 1 1 2 1 1 1 2 2 Bank6 1 1 1 2 1 1 1 2 2 Bank7 1 1 1 2 1 1 1 2 2 8 12 12 18 8 12 12 18 24 VCCIO GND NC 0 0 0 0 0 0 0 0 0 10/3 14/6 13/5 26/13 9/3 13/6 12/5 24/12 34/17 Bank1 8/2 15/7 13/5 28/14 9/3 16/7 14/5 30/15 36/18 Bank2 10/4 15/7 13/6 26/13 10/4 15/7 13/6 26/13 34/17 Bank3 11/5 15/7 14/7 28/14 11/5 15/7 14/7 28/14 34/17 Bank4 8/3 14/5 13/5 27/13 8/3 14/4 13/4 29/14 35/17 Bank5 5/2 10/4 8/2 22/11 5/2 10/4 8/2 20/10 30/15 Bank6 10/3 15/6 13/6 28/14 10/4 15/6 13/6 28/14 34/17 Bank7 11/5 15/6 14/6 26/13 11/5 15/6 14/6 26/13 34/17 Bank0 Single Ended/Differential I/O per Bank 1. These devices support on-chip LVDS buffers for left and right I/O Banks. 4-2 Pinout Information MachXO Family Data Sheet Power Supply and NC Signal 100 TQFP1 144 TQFP1 100 csBGA2 VCC LCMXO256/640: 35, 90 LCMXO1200/2280: 17, 35, 66, 91 21, 52, 93, 129 P7, B6 VCCIO0 LCMXO256: 60, 74, 92 LCMXO640: 80, 92 LCMXO1200/2280: 94 LCMXO640: 117, 135 LCMXO1200/2280: 135 LCMXO256: H14, A14, B5 LCMXO640: B12, B5 VCCIO1 LCMXO256: 10, 24, 41 LCMXO640: 60, 74 LCMXO1200/2280: 80 LCMXO640: 82, 98 LCMXO1200/2280: 117 LCMXO256: G1, P1, P10 LCMXO640: H14, A14 VCCIO2 LCMXO256: None LCMXO640: 29, 41 LCMXO1200/2280: 70 LCMXO640: 38, 63 LCMXO1200/2280: 98 LCMXO256: None LCMXO640: P4, P10 VCCIO3 LCMXO256: None LCMXO640: 10, 24 LCMXO1200/2280: 56 LCMXO640: 10, 26 LCMXO1200/2280: 82 LCMXO256: None LCMXO640: G1, P1 VCCIO4 LCMXO256/640: None LCMXO1200/2280: 44 LCMXO640: None LCMXO1200/2280: 63 — VCCIO5 LCMXO256/640: None LCMXO1200/2280: 27 LCMXO640: None LCMXO1200/2280: 38 — VCCIO6 LCMXO256/640: None LCMXO1200/2280: 20 LCMXO640: None LCMXO1200/2280: 26 — VCCIO7 LCMXO256/640: None LCMXO1200/2280: 6 LCMXO640: None LCMXO1200/2280: 10 — VCCAUX LCMXO256/640: 88 LCMXO1200/2280: 36, 90 53, 128 B7 GND3 LCMXO256: 40, 84, 62, 75, 93, 12, 16, 59, 88, 123, 118, 136, 83, 99, 25, 42 37, 64, 11, 27 LCMXO640: 40, 84, 81, 93, 62, 75, 30, 42, 12, 25 LCMXO1200/2280: 9, 41, 59, 83, 100, 76, 50, 26 NC4 LCMXO256: N9, B9, G14, B13, A4, H1, N2, N10 LCMXO640: N9, B9, A10, A4, G14, B13, N3, N10, H1, N2 — 1. Pin orientation follows the conventional order from pin 1 marking of the top side view and counter-clockwise. 2. Pin orientation A1 starts from the upper left corner of the top side view with alphabetical order ascending vertically and numerical order ascending horizontally. 3. All grounds must be electrically connected at the board level. For fpBGA and ftBGA packages, the total number of GND balls is less than the actual number of GND logic connections from the die to the common package GND plane. 4. NC pins should not be connected to any active signals, VCC or GND. 4-3 Pinout Information MachXO Family Data Sheet Power Supply and NC (Cont.) 132 csBGA1 Signal 256 caBGA / 256 ftBGA1 324 ftBGA1 VCC H3, P6, G12, C7 G7, G10, K7, K10 F14, G11, G9, H7, L7, M9 VCCIO0 LCMXO640: B11, C5 LCMXO1200/2280: C5 LCMXO640: F8, F7, F9, F10 LCMXO1200/2280: F8, F7 G8, G7 VCCIO1 LCMXO640: L12, E12 LCMXO1200/2280: B11 LCMXO640: H11, G11, K11, J11 LCMXO1200/2280: F9, F10 G12, G10 VCCIO2 LCMXO640: N2, M10 LCMXO1200/2280: E12 LCMXO640: L9, L10, L8, L7 LCMXO1200/2280: H11, G11 J12, H12 VCCIO3 LCMXO640: D2, K3  LCMXO1200/2280: L12 LCMXO640: K6, J6, H6, G6 LCMXO1200/2280: K11, J11 L12, K12 VCCIO4 LCMXO640: None LCMXO1200/2280: M10 LCMXO640: None LCMXO1200/2280: L9, L10 M12, M11 VCCIO5 LCMXO640: None LCMXO1200/2280: N2 LCMXO640: None LCMXO1200/2280: L8, L7 M8, R9 VCCIO6 LCMXO640: None LCMXO1200/2280: K3 LCMXO640: None LCMXO1200/2280: K6, J6 M7, K7 VCCIO7 LCMXO640: None LCMXO1200/2280: D2 LCMXO640: None LCMXO1200/2280: H6, G6 H6, J7 M10, F9 VCCAUX P7, A7 T9, A8 GND2 F1, P9, J14, C9, A10, B4, L13, D13, P2, N11, E1, L2 A1, A16, F11, G8, G9, H7, H8, H9, E14, F16, H10, H11, H8, H9, J10, H10, J7, J8, J9, J10, K8, K9, L6, J11, J4, J8, J9, K10, K11, K17, K8, T1, T16 K9, L10, L11, L8, L9, N2, P14, P5, R7 NC3 — — LCMXO640: E4, E5, F5, F6, C3, C2, G4, G5, H4, H5, K5, K4, M5, M4, P2, P3, N5, N6, M7, M8, N10, N11, R15, R16, P15, P16, M11, L11, N12, N13, M13, M12, K12, J12, F12, F13, E12, E13, D13, D14, B15, A15, C14, B14, E11, E10, E7, E6, D4, D3, B3, B2 LCMXO1200: None LCMXO2280: None 1. Pin orientation A1 starts from the upper left corner of the top side view with alphabetical order ascending vertically and numerical order ascending horizontally. 2. All grounds must be electrically connected at the board level. For fpBGA and ftBGA packages, the total number of GND balls is less than the actual number of GND logic connections from the die to the common package GND plane. 3. NC pins should not be connected to any active signals, VCC or GND. 4-4 Pinout Information MachXO Family Data Sheet LCMXO256 and LCMXO640 Logic Signal Connections: 100 TQFP LCMXO256 Pin Number Ball Function Bank 1 PL2A 2 3 4 5 6 Dual Function LCMXO640 Differential Ball Function Bank 1 T PL2A 3 PL2B 1 C PL2C 3 T PL3A 1 T PL2B 3 C PL3B 1 C PL2D 3 C PL3C 1 T PL3A 3 T PL3D 1 C PL3B 3 C 7 PL4A 1 T PL3C 3 T 8 PL4B 1 C PL3D 3 C 9 PL5A 1 T PL4A 3 10 VCCIO1 1 11 PL5B 1 12 GNDIO1 1 C VCCIO3 3 PL4C 3 GNDIO3 3 13 PL5C 1 14 PL5D 1 15 PL6A 1 16 PL6B 1 17 PL7A 1 18 PL7B 1 19 PL7C 1 T PL9C 3 20 PL7D 1 C PL10A 3 21 PL8A 1 T PL10C 3 GSRN TSALL T PL4D 3 C PL5B 3 T PL7B 3 C PL8C 3 T PL8D 3 C PL9A 3 22 PL8B 1 C PL11A 3 23 PL9A 1 T PL11C 3 24 VCCIO1 1 VCCIO3 3 25 GNDIO1 1 26 TMS 1 27 PL9B 1 28 TCK 1 29 PB2A 30 PB2B GNDIO3 3 TMS 2 C PB2C 2 TCK 2 1 T VCCIO2 2 1 C GNDIO2 2 TDO 2 T PB4C 2 TDI 2 PB4E 2 VCC - T PB5B 2 C PB5D 2 T PB6B 2 C PB6C 2 TMS TCK 31 TDO 1 32 PB2C 1 TDO 33 TDI 1 34 PB2D 1 35 VCC - 36 PB3A 1 37 PB3B 1 38 PB3C 1 39 PB3D 1 40 GND - GND - 41 VCCIO1 1 VCCIO2 2 42 GNDIO1 1 GNDIO2 2 TDI C PCLK1_1** PCLK1_0** 4-5 Dual Function Differential T T C GSRN TSALL T C TMS TCK TDO TDI PCLK2_1** PCLK2_0** Pinout Information MachXO Family Data Sheet LCMXO256 and LCMXO640 Logic Signal Connections: 100 TQFP (Cont.) LCMXO256 Pin Number Ball Function Bank 43 PB4A 44 45 46 Differential Ball Function Bank 1 T PB8B 2 PB4B 1 C PB8C 2 T PB4C 1 T PB8D 2 C PB4D 1 C PB9A 2 47 PB5A 1 48* SLEEPN - 49 PB5C 1 Dual Function LCMXO640 SLEEPN T PB9C 2 SLEEPN - PB9D 2 Dual Function Differential T SLEEPN C 50 PB5D 1 C PB9F 2 51 PR9B 0 C PR11D 1 C 52 PR9A 0 T PR11B 1 C 53 PR8B 0 C PR11C 1 T 54 PR8A 0 T PR11A 1 T 55 PR7D 0 C PR10D 1 C 56 PR7C 0 T PR10C 1 T 57 PR7B 0 C PR10B 1 C 58 PR7A 0 T PR10A 1 T C 59 PR6B 0 60 VCCIO0 0 61 PR6A 0 62 GNDIO0 0 GNDIO1 1 63 PR5D 0 C PR7B 1 64 PR5C 0 T PR6C 1 65 PR5B 0 C PR6B 1 66 PR5A 0 T PR5D 1 67 PR4B 0 C PR5B 1 68 PR4A 0 T PR4D 1 69 PR3D 0 C PR4B 1 70 PR3C 0 T PR3D 1 71 PR3B 0 C PR3B 1 72 PR3A 0 T PR2D 1 73 PR2B 0 C PR2B 1 74 VCCIO0 0 VCCIO1 1 75 GNDIO0 0 GNDIO1 1 76 PR2A 0 T PT9F 0 C 77 PT5C 0 PT9E 0 T 78 PT5B 0 C PT9C 0 79 PT5A 0 T PT9A 0 80 PT4F 0 C VCCIO0 0 81 PT4E 0 T GNDIO0 0 82 PT4D 0 C PT7E 0 83 PT4C 0 T PT7A 0 84 GND - GND - T 4-6 PR9D 1 VCCIO1 1 PR9B 1 Pinout Information MachXO Family Data Sheet LCMXO256 and LCMXO640 Logic Signal Connections: 100 TQFP (Cont.) LCMXO256 LCMXO640 Pin Number Ball Function Bank Dual Function Differential Ball Function Bank Dual Function 85 PT4B 0 PCLK0_1** C PT6B 0 PCLK0_1** PCLK0_0** PCLK0_0** 86 PT4A 0 87 PT3D 0 88 VCCAUX - 89 PT3C 0 90 VCC - 91 PT3B 0 92 VCCIO0 93 GNDIO0 94 PT3A 0 95 PT2F 96 PT2E 97 Differential T PT5B 0 C PT5A 0 VCCAUX - PT4F 0 VCC - PT3F 0 0 VCCIO0 0 0 GNDIO0 0 T PT3B 0 0 C PT3A 0 T 0 T PT2F 0 C PT2D 0 C PT2E 0 T 98 PT2C 0 T PT2B 0 C 99 PT2B 0 C PT2C 0 100 PT2A 0 T PT2A 0 T C * NC for “E” devices. ** Primary clock inputs are single-ended. 4-7 C T C T Pinout Information MachXO Family Data Sheet LCMXO1200 and LCMXO2280 Logic Signal Connections: 100 TQFP LCMXO1200 Pin Number Ball Function Bank 1 PL2A Dual Function LCMXO2280 Differential Ball Function Bank Dual Function Differential 7 T PL2A 7 LUM0_PLLT_FB_A T 2 PL2B 7 C PL2B 7 LUM0_PLLC_FB_A C 3 PL3C 7 T PL3C 7 LUM0_PLLT_IN_A T 4 PL3D 7 C PL3D 7 LUM0_PLLC_IN_A C 5 PL4B 7 PL4B 7 6 VCCIO7 7 VCCIO7 7 7 PL6A 7 T* PL7A 7 8 PL6B 7 C* PL7B 7 GSRN C* 9 GND - GND - 10 PL7C 7 T PL9C 7 T 11 PL7D 7 C PL9D 7 C 12 PL8C 7 T PL10C 7 T 13 PL8D 7 C PL10D 7 C 14 PL9C 6 PL11C 6 15 PL10A 6 T* PL13A 6 T* 16 PL10B 6 C* PL13B 6 C* 17 VCC - VCC - 18 PL11B 6 PL14D 6 GSRN 19 PL11C 6 PL14C 6 20 VCCIO6 6 TSALL VCCIO6 6 21 PL13C 6 PL16C 6 T* C TSALL T 22 PL14A 6 LLM0_PLLT_FB_A T* PL17A 6 LLM0_PLLT_FB_A T* 23 PL14B 6 LLM0_PLLC_FB_A C* PL17B 6 LLM0_PLLC_FB_A C* 24 PL15A 6 LLM0_PLLT_IN_A T* PL18A 6 LLM0_PLLT_IN_A T* 25 PL15B 6 LLM0_PLLC_IN_A C* LLM0_PLLC_IN_A C* 26** GNDIO6 GNDIO5 - 27 VCCIO5 5 28 TMS 5 TMS TCK PL18B 6 GNDIO6 GNDIO5 - VCCIO5 5 TMS 5 TMS TCK 29 TCK 5 30 PB3B 5 TCK 5 PB3B 5 31 PB4A 5 T PB4A 5 32 PB4B 5 33 TDO 5 TDO C PB4B 5 TDO 5 TDO 34 TDI 5 TDI TDI 5 TDI 35 VCC - VCC - 36 VCCAUX - VCCAUX - 37 PB6E 5 PB8E 5 38 PB6F 5 PB8F 5 39 PB7B 4 PCLK4_1**** PB10F 4 PCLK4_1**** 40 PB7F 4 PCLK4_0**** PB10B 4 PCLK4_0**** 41 GND - GND - T C 4-8 T C T C Pinout Information MachXO Family Data Sheet LCMXO1200 and LCMXO2280 Logic Signal Connections: 100 TQFP (Cont.) LCMXO1200 Pin Number Ball Function Bank 42 PB9A Differential Ball Function Bank 4 T PB12A 4 T C C 43 PB9B 4 44 VCCIO4 4 45 PB10A 4 Dual Function LCMXO2280 T 46 PB10B 4 47*** SLEEPN - C 48 PB11A 4 T 49 PB11B 4 C 50** GNDIO3 GNDIO4 - 51 PR16B 3 52 PR15B 3 SLEEPN PB12B 4 VCCIO4 4 PB13A 4 Dual Function Differential T PB13B 4 SLEEPN - PB16A 4 T PB16B 4 C GNDIO3 GNDIO4 - PR19B 3 C* PR18B 3 C SLEEPN C* 53 PR15A 3 T* PR18A 3 T* 54 PR14B 3 C* PR17B 3 C* 55 PR14A 3 T* PR17A 3 T* 56 VCCIO3 3 VCCIO3 3 57 PR12B 3 C* PR15B 3 C* 58 PR12A 3 T* PR15A 3 T* 59 GND - GND - 60 PR10B 3 C* PR13B 3 C* 61 PR10A 3 T* PR13A 3 T* 62 PR9B 3 C* PR11B 3 C* 63 PR9A 3 T* PR11A 3 T* 64 PR8B 2 C* PR10B 2 C* 65 PR8A 2 T* PR10A 2 T* 66 VCC - VCC - 67 PR6C 2 PR8C 2 68 PR6B 2 C* PR8B 2 C* 69 PR6A 2 T* PR8A 2 T* 70 VCCIO2 2 VCCIO2 2 71 PR4D 2 PR5D 2 72 PR4B 2 C* PR5B 2 C* 73 PR4A 2 T* PR5A 2 T* 74 PR2B 2 C PR3B 2 C* 75 PR2A 2 T PR3A 2 T* 76** GNDIO1 GNDIO2 GNDIO1 GNDIO2 - 77 PT11C 1 PT15C 1 78 PT11B 1 C PT14B 1 C 79 PT11A 1 T PT14A 1 T 80 VCCIO1 1 VCCIO1 1 81 PT9E 1 PT12D 1 - 4-9 C Pinout Information MachXO Family Data Sheet LCMXO1200 and LCMXO2280 Logic Signal Connections: 100 TQFP (Cont.) LCMXO1200 Pin Number Ball Function Bank 82 PT9A 1 Dual Function LCMXO2280 Differential Ball Function Bank PT12C 1 Dual Function Differential T 83 GND - GND - 84 PT8B 1 C PT11B 1 C 85 PT8A 1 T PT11A 1 T 86 PT7D 1 PCLK1_1**** PT10B 1 PCLK1_1**** 87 PT6F 0 PCLK0_0**** PT9B 1 PCLK1_0**** 88 PT6D 0 C PT8F 0 C 89 PT6C 0 T PT8E 0 T 90 VCCAUX - VCCAUX - 91 VCC - VCC - 92 PT5B 0 PT6D 0 93 PT4B 0 PT6F 0 94 VCCIO0 0 VCCIO0 0 95 PT3D 0 C PT4B 0 C 96 PT3C 0 T PT4A 0 T 97 PT3B 0 PT3B 0 98 PT2B 0 C PT2B 0 C 99 PT2A 0 T PT2A 0 T 100** GNDIO0 GNDIO7 - GNDIO0 GNDIO7 - *Supports true LVDS outputs. **Double bonded to the pin. ***NC for "E" devices. ****Primary clock inputs are single-ended. 4-10 Pinout Information MachXO Family Data Sheet LCMXO256 and LCMXO640 Logic Signal Connections: 100 csBGA LCMXO256 Ball Number Ball Function Bank B1 PL2A C1 D2 LCMXO640 Dual Function Differential Ball Number Ball Function Bank Dual Function Differential 1 T B1 PL2A 3 PL2B 1 C C1 PL2C 3 T PL3A 1 T D2 PL2B 3 C D1 PL3B 1 C D1 PL2D 3 C C2 PL3C 1 T C2 PL3A 3 T E1 PL3D 1 C E1 PL3B 3 C T E2 PL4A 1 T E2 PL3C 3 T F1 PL4B 1 C F1 PL3D 3 C F2 PL5A 1 T F2 PL4A 3 G2 PL5B 1 C G2 PL4C 3 H1 GNDIO1 1 H1 GNDIO3 3 H2 PL5C 1 H2 PL4D 3 J1 PL5D 1 J2 PL6A 1 K1 PL6B 1 K2 PL7A L1 PL7B L2 PL7C M1 M2 N1 T C J1 PL5B 3 T J2 PL7B 3 C K1 PL8C 3 1 T K2 PL8D 3 1 C L1 PL9A 3 1 T L2 PL9C 3 PL7D 1 C M1 PL10A 3 PL8A 1 T M2 PL10C 3 PL8B 1 C N1 PL11A 3 M3 PL9A 1 T M3 PL11C 3 N2 GNDIO1 1 N2 GNDIO3 3 P2 TMS 1 P2 TMS 2 P3 PL9B 1 N4 TCK 1 P4 PB2A 1 N3 PB2B 1 P5 TDO 1 N5 PB2C 1 P6 TDI 1 N6 PB2D 1 P7 VCC - N7 PB3A 1 P8 PB3B 1 N8 PB3C 1 P9 PB3D 1 N10 GNDIO1 1 GSRN TSALL TMS C P3 PB2C 2 N4 TCK 2 T P4 VCCIO2 2 C N3 GNDIO2 2 P5 TDO 2 T N5 PB4C 2 P6 TDI 2 C N6 PB4E 2 P7 VCC - TCK TDO TDI PCLK1_1** PCLK1_0** T N7 PB5B 2 C P8 PB5D 2 T N8 PB6B 2 C P9 PB6C 2 N10 GNDIO2 2 T C GSRN TSALL T C TMS TCK TDO TDI PCLK2_1** PCLK2_0** P11 PB4A 1 T P11 PB8B 2 N11 PB4B 1 C N11 PB8C 2 T P12 PB4C 1 T P12 PB8D 2 C N12 PB4D 1 C N12 PB9A 2 4-11 Pinout Information MachXO Family Data Sheet LCMXO256 and LCMXO640 Logic Signal Connections: 100 csBGA (Cont.) LCMXO256 LCMXO640 Ball Number Ball Function Dual Function Differential Bank P13 PB5A 1 M12* SLEEPN - P14 PB5C 1 T N13 PB5D 1 C Ball Number Ball Function Bank P13 PB9C 2 M12* SLEEPN - P14 PB9D 2 N13 PB9F 2 SLEEPN Dual Function Differential T SLEEPN C N14 PR9B 0 C N14 PR11D 1 C M14 PR9A 0 T M14 PR11B 1 C L13 PR8B 0 C L13 PR11C 1 T L14 PR8A 0 T L14 PR11A 1 T M13 PR7D 0 C M13 PR10D 1 C K14 PR7C 0 T K14 PR10C 1 T K13 PR7B 0 C K13 PR10B 1 C J14 PR7A 0 T J14 PR10A 1 T J13 PR6B 0 C J13 PR9D 1 T H13 PR6A 0 G14 GNDIO0 0 H13 PR9B 1 G14 GNDIO1 1 G13 PR5D 0 C G13 PR7B 1 F14 PR5C F13 PR5B 0 T F14 PR6C 1 0 C F13 PR6B 1 E14 PR5A 0 T E14 PR5D 1 E13 PR4B 0 C E13 PR5B 1 D14 PR4A 0 T D14 PR4D 1 D13 PR3D 0 C D13 PR4B 1 C14 PR3C 0 T C14 PR3D 1 C13 PR3B 0 C C13 PR3B 1 B14 PR3A 0 T B14 PR2D 1 C12 PR2B 0 C C12 PR2B 1 B13 GNDIO0 0 B13 GNDIO1 1 A13 PR2A 0 A13 PT9F 0 C A12 PT5C 0 A12 PT9E 0 T B11 PT5B 0 C B11 PT9C 0 A11 PT5A 0 T A11 PT9A 0 B12 PT4F 0 C B12 VCCIO0 0 A10 PT4E 0 T A10 GNDIO0 0 B10 PT4D 0 C B10 PT7E 0 A9 PT4C 0 T A9 PT7A 0 A8 PT4B 0 PCLK0_1** C A8 PT6B 0 PCLK0_1** B8 PT4A 0 PCLK0_0** T B8 PT5B 0 PCLK0_0** A7 PT3D 0 C A7 PT5A 0 B7 VCCAUX - B7 VCCAUX - A6 PT3C 0 A6 PT4F 0 B6 VCC - B6 VCC - A5 PT3B 0 A5 PT3F 0 T T C 4-12 C T Pinout Information MachXO Family Data Sheet LCMXO256 and LCMXO640 Logic Signal Connections: 100 csBGA (Cont.) LCMXO256 LCMXO640 Ball Number Ball Function Dual Function Differential Ball Number Ball Function Bank Bank A4 GNDIO0 0 B4 PT3A 0 A3 PT2F 0 B3 PT2E 0 T Dual Function Differential A4 GNDIO0 0 T B4 PT3B 0 C A3 PT3A 0 T B3 PT2F 0 C C A2 PT2D 0 C A2 PT2E 0 T C3 PT2C 0 T C3 PT2B 0 C A1 PT2B 0 C A1 PT2C 0 T B2 PT2A 0 B2 PT2A 0 N9 GND - N9 GND - B9 GND - B9 GND - B5 VCCIO0 0 B5 VCCIO0 0 A14 VCCIO0 0 A14 VCCIO1 1 H14 VCCIO0 0 H14 VCCIO1 1 P10 VCCIO1 1 P10 VCCIO2 2 G1 VCCIO1 1 G1 VCCIO3 3 P1 VCCIO1 1 P1 VCCIO3 3 *NC for “E” devices. **Primary clock inputs are single-ended. 4-13 T Pinout Information MachXO Family Data Sheet LCMXO640, LCMXO1200 and LCMXO2280 Logic Signal Connections:  132 csBGA LCMXO640 Ball Ball # Function Bank Dual Function LCMXO1200 Ball Differential Ball # Function Bank Dual Function LCMXO2280 Ball Differential Ball # Function Bank Dual Function Differential T B1 PL2A 3 T B1 PL2A 7 T B1 PL2A 7 LUM0_PLLT_FB_A C1 PL2B 3 C C1 PL3C 7 T C1 PL3C 7 LUM0_PLLT_IN_A T B2 PL2C 3 T B2 PL2B 7 C B2 PL2B 7 LUM0_PLLC_FB_A C C2 PL2D 3 C C2 PL4A 7 T* C2 PL4A 7 C3 PL3A 3 T C3 PL3D 7 C C3 PL3D 7 D1 PL3B 3 C D1 PL4B 7 C* D1 PL4B 7 D3 PL3D 3 D3 PL4C 7 D3 PL4C 7 E1 GNDIO3 3 E1 GNDIO7 7 E1 GNDIO7 7 E2 PL5A 3 T E2 PL6A 7 E3 PL5B 3 C E3 PL6B 7 F2 PL5D 3 F2 PL6D 7 F3 PL6B 3 F3 PL7C G1 PL6C 3 T G1 G2 PL6D 3 C G3 PL7A 3 T H2 PL7B 3 C H1 PL7C 3 GSRN T* E2 PL7A 7 E3 PL7B 7 F2 PL7D 7 7 T F3 PL9C 7 T PL7D 7 C G1 PL9D 7 C G2 PL8C 7 T G2 PL10C 7 T G3 PL8D 7 C G3 PL10D 7 C H2 PL10A 6 T* H2 PL12A 6 T* H1 PL10B 6 C* H1 PL12B 6 C* VCC - H3 VCC - H3 VCC - J1 PL8A 3 J1 PL11B 6 J1 PL14D 6 J2 PL8C 3 J2 PL11C 6 T J2 PL14C 6 J3 PL9A 3 T J3 PL11D 6 C J3 PL14B 6 C K2 PL9B 3 K1 PL9C 3 L2 GNDIO3 3 L1 PL10A 3 T L3 PL10B 3 M1 PL11A N1 PL11B M2 PL11C C C* C* GSRN H3 TSALL T* LUM0_PLLC_IN_A TSALL T* GSRN C* C TSALL T K2 PL12A 6 T* K2 PL15A 6 T* K1 PL12B 6 C* K1 PL15B 6 C* L2 GNDIO6 6 L2 GNDIO6 6 L1 PL14A 6 LLM0_PLLT_FB_A T* L1 PL17A 6 LLM0_PLLT_FB_A T* C L3 PL14B 6 LLM0_PLLC_FB_A C* L3 PL17B 6 LLM0_PLLC_FB_A C* 3 T M1 PL15A 6 LLM0_PLLT_IN_A T* M1 PL18A 6 LLM0_PLLT_IN_A T* 3 C N1 PL16A 6 T N1 PL19A 6 3 T M2 PL15B 6 C* M2 PL18B 6 LLM0_PLLC_IN_A C* C P1 PL11D 3 P2 GNDIO2 2 PL16B 6 GNDIO5 5 C PL19B 6 GNDIO5 5 C P3 TMS 2 P3 TMS 5 P3 TMS 5 PB2C 2 T M3 PB2C 5 T M3 PB2A 5 T N3 PB2D 2 C N3 PB2D 5 C N3 PB2B 5 C P4 TCK 2 PB3B 2 N4 PB3C 2 P5 PB3D 2 TCK P4 TCK 5 M4 PB3B 5 T N4 PB4A 5 C P5 PB4B 5 TMS P1 P2 T M3 M4 TMS P1 P2 LLM0_PLLC_IN_A TCK TMS P4 TCK 5 M4 PB3B 5 TCK T N4 PB4A 5 T C P5 PB4B 5 C N5 TDO 2 TDO N5 TDO 5 TDO N5 TDO 5 TDO M5 TDI 2 TDI M5 TDI 5 TDI M5 TDI 5 TDI N6 PB4E 2 T N6 PB5C 5 N6 PB6C 5 P6 VCC - P6 VCC - C M6 PB6A 5 M6 PB8A 5 P7 VCCAUX - P7 VCCAUX - T N7 PB6F 5 N7 PB8F 5 C M7 PB7B 4 M7 PB10F 4 N8 PB7C 4 T N8 PB10C 4 T T P8 PB7D 4 C P8 PB10D 4 C C M8 PB7F 4 T N9 PB9A 4 P6 VCC - M6 PB4F 2 P7 VCCAUX - N7 PB5A 2 M7 PB5B 2 N8 PB5D 2 P8 PB6A 2 M8 PB6B 2 N9 PB7A 2 PCLK2_1*** PCLK2_0*** PCLK4_1*** PCLK4_0*** T 4-14 M8 PB10B 4 N9 PB12A 4 PCLK4_1*** PCLK4_0*** T Pinout Information MachXO Family Data Sheet LCMXO640, LCMXO1200 and LCMXO2280 Logic Signal Connections:  132 csBGA (Cont.) LCMXO640 Ball Ball # Function Bank Dual Function LCMXO1200 Ball Differential Ball # Function Bank Dual Function LCMXO2280 Ball Differential Ball # Function Bank Dual Function Differential M9 PB7B 2 C M9 PB9B 4 C M9 PB12B 4 N10 PB7E 2 T N10 PB9C 4 T N10 PB12C 4 T P10 PB7F 2 C P10 PB9D 4 C P10 PB12D 4 C N11 GNDIO2 2 N11 GNDIO4 4 N11 GNDIO4 4 P11 PB8C 2 T P11 PB10A 4 T P11 PB13C 4 T M11 PB8D 2 C M11 PB10B 4 C M11 PB13D 4 C P12 PB9C 2 T P12 PB10C 4 P12 PB15B 4 P13 PB9D 2 C P13 PB11C 4 P13 PB16C 4 N12** SLEEPN - N12** SLEEPN - N12** SLEEPN - P14 PB9F 2 N14 PR11D 1 M14 PR11C N13 PR11B M12 PR11A M13 L14 SLEEPN T SLEEPN C T SLEEPN P14 PB11D 4 C P14 PB16D 4 C C N14 PR16B 3 C N14 PR19B 3 C 1 T M14 PR15B 3 C* M14 PR18B 3 C* 1 C N13 PR16A 3 T N13 PR19A 3 T 1 T M12 PR15A 3 T* M12 PR18A 3 T* PR10B 1 C M13 PR14B 3 C* M13 PR17B 3 C* PR10A 1 T L14 PR14A 3 T* L14 PR17A 3 T* L13 GNDIO1 1 L13 GNDIO3 3 L13 GNDIO3 3 K14 PR8D 1 C K14 PR12B 3 C* K14 PR15B 3 K13 PR8C 1 T K13 PR12A 3 T* K13 PR15A 3 T* K12 PR8B 1 C K12 PR11B 3 C* K12 PR14B 3 C* J13 PR8A 1 T J13 PR11A 3 T* J13 PR14A 3 T* J12 PR7C 1 J12 PR10B 3 C* J12 PR13B 3 C* H14 PR7B 1 C H14 PR10A 3 T* H14 PR13A 3 T* H13 PR7A 1 T H13 PR9B 3 C* H13 PR11B 3 C* C* H12 PR6D 1 C H12 PR9A 3 T* H12 PR11A 3 T* G13 PR6C 1 T G13 PR8B 2 C* G13 PR10B 2 C* G14 PR6B 1 G14 PR8A 2 T* G14 PR10A 2 T* G12 VCC - G12 VCC - G12 VCC - F14 PR5D 1 C F14 PR6C 2 F14 PR8C 2 F13 PR5C 1 T F13 PR6B 2 C* F13 PR8B 2 F12 PR4D 1 C F12 PR6A 2 T* F12 PR8A 2 T* E13 PR4C 1 T E13 PR5B 2 C* E13 PR7B 2 C* T* T* E14 PR4B 1 E14 PR5A 2 D13 GNDIO1 1 D13 GNDIO2 2 D14 PR3D 1 C D14 PR4B 2 D12 PR3C 1 T D12 PR4A 2 C14 PR2D 1 C C14 PR3D B14 PR2C 1 T B14 C13 PR2B 1 C A14 PR2A 1 T C* E14 PR7A 2 D13 GNDIO2 2 C* D14 PR5B 2 C* T* D12 PR5A 2 T* 2 C C14 PR4D 2 C PR2B 2 C B14 PR3B 2 C* C13 PR3C 2 T C13 PR4C 2 T A14 PR2A 2 T A14 PR3A 2 T* A13 PT9F 0 C A13 PT11D 1 C A13 PT16D 1 C A12 PT9E 0 T A12 PT11B 1 C A12 PT16B 1 C B13 PT9D 0 C B13 PT11C 1 T T B12 PT9C 0 T B12 PT10F 1 C12 PT9B 0 C C12 PT11A 1 A11 PT9A 0 T A11 PT10D 1 C11 PT8C 0 C11 PT10C 1 T A10 GNDIO0 0 A10 GNDIO1 1 B13 PT16C 1 B12 PT15D 1 T C12 PT16A 1 T C A11 PT14B 1 C C11 PT14A 1 T A10 GNDIO1 1 B10 PT7F 0 C B10 PT9F 1 C B10 PT12F 1 C C10 PT7E 0 T C10 PT9E 1 T C10 PT12E 1 T 4-15 Pinout Information MachXO Family Data Sheet LCMXO640, LCMXO1200 and LCMXO2280 Logic Signal Connections:  132 csBGA (Cont.) LCMXO640 Ball Ball # Function Bank Dual Function LCMXO1200 Ball Differential Ball # Function Bank Dual Function LCMXO2280 Ball Differential Ball # Function Bank B9 PT7B 0 C B9 PT9B 1 C B9 PT12D 1 A9 PT7A 0 T A9 PT9A 1 T A9 PT12C 1 A8 PT6B 0 PCLK0_1*** C A8 PT7D 1 PCLK1_1*** A8 PT10B 1 T B8 PT7B 1 B8 PT9D 1 PCLK0_0*** C C8 PT6F 0 PCLK1_0*** C8 PT9B 1 T B7 PT6D 0 B7 PT8D 0 - B8 PT6A 0 C8 PT5B 0 B7 PT5A 0 Dual Function Differential C T PCLK1_1*** PCLK1_0*** A7 VCCAUX - A7 VCCAUX - A7 VCCAUX C7 VCC - C7 VCC - C7 VCC - A6 PT4D 0 C A6 PT5D 0 C A6 PT7B 0 C B6 PT4C 0 T B6 PT5C 0 T B6 PT7A 0 T C6 PT3F 0 C C6 PT5B 0 C C6 PT6D 0 T T B5 PT3E 0 A5 PT3D 0 B5 PT5A 0 A5 PT4B 0 B4 GNDIO0 A4 PT3B C4 PT2F 0 A3 PT2D 0 0 B4 GNDIO0 0 0 A4 PT3D 0 C C4 PT3C 0 T A3 PT3B 0 C A2 PT2C 0 T A2 B3 PT2B 0 C B3 PT2B 0 C A2 PT3A 0 T B3 A1 PT2A 0 T A1 PT2A 0 T A1 F1 GND - F1 GND - C B5 PT6E 0 T A5 PT6F 0 C B4 GNDIO0 0 A4 PT4B 0 C4 PT4A 0 T A3 PT3B 0 C PT2B 0 C PT3A 0 T PT2A 0 T F1 GND - P9 GND - P9 GND - P9 GND J14 GND - J14 GND - J14 GND - C9 GND - C9 GND - C9 GND - C5 VCCIO0 0 C5 VCCIO0 0 C5 VCCIO0 0 B11 VCCIO0 0 B11 VCCIO1 1 B11 VCCIO1 1 E12 VCCIO1 1 E12 VCCIO2 2 E12 VCCIO2 2 L12 VCCIO1 1 L12 VCCIO3 3 L12 VCCIO3 3 M10 VCCIO2 2 M10 VCCIO4 4 M10 VCCIO4 4 N2 VCCIO2 2 N2 VCCIO5 5 N2 VCCIO5 5 D2 VCCIO3 3 D2 VCCIO7 7 D2 VCCIO7 7 K3 VCCIO3 3 K3 VCCIO6 6 K3 VCCIO6 6 *Supports true LVDS outputs. **NC for “E” devices. ***Primary clock inputs arer single-ended. 4-16 C Pinout Information MachXO Family Data Sheet LCMXO640, LCMXO1200 and LCMXO2280 Logic Signal Connections:  144 TQFP LCMXO640 Pin Number Ball Function Bank 1 PL2A 2 Dual Function LCMXO1200 Dual Function LCMXO2280 Differential Ball Function Differential Ball Function Bank Bank Dual Function 3 T PL2A 7 T PL2A 7 LUM0_PLLT_FB_A PL2C 3 T PL2B T 7 C PL2B 7 LUM0_PLLC_FB_A C 3 PL2B 3 C PL3A 7 T* PL3A 7 T* 4 PL3A 3 T PL3B 7 C* PL3B 7 C* 5 PL2D 3 C PL3C 7 T PL3C 7 LUM0_PLLT_IN_A T 6 PL3B 3 C PL3D 7 C PL3D 7 LUM0_PLLC_IN_A C 7 PL3C 3 T PL4A 7 T* PL4A 7 T* 8 PL3D 3 C PL4B 7 C* PL4B 7 C* 7 Differential 9 PL4A 3 PL4C 7 PL4C 10 VCCIO3 3 VCCIO7 7 VCCIO7 7 11 GNDIO3 3 GNDIO7 7 GNDIO7 7 12 PL4D 3 PL6C 7 13 PL5A 3 14 PL5B 3 15 PL5D 16 GND 17 PL6C 3 18 PL6D 3 19 PL7A 3 T PL10A 6 T* PL13A 6 T* 20 PL7B 3 C PL10B 6 C* PL13B 6 C* VCC - VCC - T PL11A 6 T* PL13D 6 PL5C 7 T PL6A 7 C PL6B 7 3 PL6D - GND T PL7C 7 C PL7D 7 21 VCC - 22 PL8A 3 23 PL8B 3 24 PL8C 3 25 PL9C 3 GSRN C TSALL T T* PL7A 7 C* PL7B 7 7 PL7D 7 - GND - T PL9C 7 T C PL9D 7 C PL11B 6 PL11C 6 PL12B 6 GSRN C* TSALL PL14D 6 PL14C 6 PL15B 6 T* GSRN C* C TSALL T 26 VCCIO3 3 VCCIO6 6 VCCIO6 6 27 GNDIO3 3 GNDIO6 6 GNDIO6 6 28 PL9D 3 C PL13D 6 PL16D 6 29 PL10A 3 T PL14A 6 LLM0_PLLT_FB_A T* PL17A 6 LLM0_PLLT_FB_A T* 30 PL10B 3 C PL14B 6 LLM0_PLLC_FB_A C* PL17B 6 LLM0_PLLC_FB_A C* 31 PL10C 3 T PL14C 6 T PL17C 6 T 32 PL11A 3 T PL14D 6 C PL17D 6 C 33 PL10D 3 C PL15A 6 LLM0_PLLT_IN_A T* PL18A 6 LLM0_PLLT_IN_A T* 34 PL11C 3 T PL15B 6 LLM0_PLLC_IN_A C* PL18B 6 LLM0_PLLC_IN_A C* 35 PL11B 3 C PL16A 6 T PL19A 6 T 36 PL11D 3 C PL16B 6 C PL19B 6 C 37 GNDIO2 2 GNDIO5 5 GNDIO5 5 38 VCCIO2 2 VCCIO5 5 VCCIO5 5 39 TMS 2 TMS 5 TMS 5 40 PB2C 2 PB2C 5 T PB2A 5 T 41 PB3A 2 T PB2D 5 C PB2B 5 C TMS TCK 2 TCK 5 TCK 5 43 PB3B 2 C PB3A 5 T PB3A 5 T 44 PB3C 2 T PB3B 5 C PB3B 5 C 45 PB3D 2 C PB4A 5 T PB4A 5 T 46 PB4A 2 T PB4B 5 C PB4B 5 C TDO 5 TDO 5 C PB4D 5 PB4D 5 TDO 2 48 PB4B 2 TDO TCK TMS 42 47 TCK TMS TDO TCK TDO 49 PB4C 2 T PB5A 5 T PB5A 5 T 50 PB4D 2 C PB5B 5 C PB5B 5 C 4-17 Pinout Information MachXO Family Data Sheet LCMXO640, LCMXO1200 and LCMXO2280 Logic Signal Connections:  144 TQFP (Cont.) LCMXO640 LCMXO1200 LCMXO2280 Pin Number Ball Function Bank Dual Function Ball Function Bank Dual Function 51 TDI 2 TDI TDI 5 TDI 52 VCC 53 VCCAUX - VCC - VCC - - VCCAUX - VCCAUX - 54 PB5A 2 55 PB5B 2 56 PB5D 2 57 PB6A 2 58 PB6B 2 59 GND - 60 PB7C 61 PB7E 62 PB8A 63 VCCIO2 64 GNDIO2 2 GNDIO4 4 65 PB8C 2 T PB10A 4 T PB13A 4 T 66 PB8D 2 C PB10B 4 C PB13B 4 C Differential Differential Ball Function Bank Dual Function TDI 5 TDI T PB6F 5 C PB7B 4 PB7C 4 T PB7D 4 C PB7F 4 GND - 2 PB9A 4 2 PB9B 4 2 PB9E 4 PB12E 4 2 VCCIO4 4 VCCIO4 4 GNDIO4 4 PCLKT2_1*** PCLKT2_0*** Differential PB8F 5 PB10F 4 T PB10C 4 T C PB10D 4 C PB10B 4 GND - T PB12A 4 T C PB12B 4 C PCLK4_1*** PCLK4_0*** PCLK4_1*** PCLK4_0*** 67 PB9A 2 T PB10C 4 T PB13C 4 T 68 PB9C 2 T PB10D 4 C PB13D 4 C PB14D 4 69 PB9B 2 70** SLEEPN - 71 PB9D 2 72 PB9F 2 73 PR11D 1 74 PR11B 1 75 PR11C 76 77 C PB10F 4 SLEEPN - PB11C 4 PB11D C C 1 T PR10D 1 PR11A 1 SLEEPN SLEEPN - T PB16C 4 T 4 C PB16D 4 C PR16B 3 C PR20B 3 C PR16A 3 T PR20A 3 T PR15B 3 C* PR19B 3 C C PR15A 3 T* PR19A 3 T T PR14D 3 C PR17D 3 C C SLEEPN SLEEPN 78 PR10B 1 C PR14C 3 T PR17C 3 T 79 PR10C 1 T PR14B 3 C* PR17B 3 C* 80 PR10A 1 T PR14A 3 T* PR17A 3 T* 81 PR9D 1 PR13D 3 PR16D 3 82 VCCIO1 1 VCCIO3 3 VCCIO3 3 83 GNDIO1 1 GNDIO3 3 GNDIO3 3 84 PR9A 1 PR12B 3 C* PR15B 3 85 PR8C 1 PR12A 3 T* PR15A 3 T* 86 PR8A 1 PR11B 3 C* PR14B 3 C* 87 PR7D 1 PR11A 3 T* PR14A 3 T* 88 GND - GND - GND - 89 PR7B 1 C PR10B 3 C* PR13B 3 90 PR7A 1 T PR10A 3 T* PR13A 3 T* 91 PR6D 1 C PR8B 2 C* PR10B 2 C* 92 PR6C 1 T PR8A 2 T* PR10A 2 T* 93 VCC - VCC - VCC - 94 PR5D 1 PR6B 2 C* PR8B 2 95 PR5B 1 PR6A 2 T* PR8A 2 T* 96 PR4D 1 PR5B 2 C* PR7B 2 C* T* T* 97 PR4B 1 98 VCCIO1 1 99 GNDIO1 1 100 PR4A 1 C T PR5A 2 PR7A 2 VCCIO2 2 VCCIO2 2 GNDIO2 2 GNDIO2 2 PR4C 2 PR5C 2 4-18 C* C* C* Pinout Information MachXO Family Data Sheet LCMXO640, LCMXO1200 and LCMXO2280 Logic Signal Connections:  144 TQFP (Cont.) LCMXO640 Pin Number Ball Function Bank 101 PR3D 102 Dual Function LCMXO1200 Differential Ball Function Bank 1 C PR4B PR3C 1 T 103 PR3B 1 104 PR2D 105 PR3A Dual Function LCMXO2280 Differential Ball Function Bank Dual Function 2 C* PR5B 2 C* PR4A 2 T* PR5A 2 T* C PR3D 2 C PR4D 2 C 1 C PR3C 2 T PR4C 2 T 1 T PR3B 2 C* PR4B 2 C* Differential 106 PR2B 1 C PR3A 2 T* PR4A 2 T* 107 PR2C 1 T PR2B 2 C PR3B 2 C* 108 PR2A 1 T PR2A 2 T PR3A 2 T* 109 PT9F 0 C PT11D 1 C PT16D 1 C 110 PT9D 0 C PT11C 1 T PT16C 1 T 111 PT9E 0 T PT11B 1 C PT16B 1 C 112 PT9B 0 C PT11A 1 T PT16A 1 T 113 PT9C 0 T PT10F 1 C PT15D 1 C T 114 PT9A 0 115 PT8C 0 116 PT8B 0 117 VCCIO0 0 118 GNDIO0 0 119 PT8A 0 120 PT7E 121 C PT10E 1 T PT15C 1 T PT10D 1 C PT14B 1 C PT10C 1 T PT14A 1 T VCCIO1 1 VCCIO1 1 GNDIO1 1 GNDIO1 1 PT9F 1 C PT12F 1 0 PT9E 1 T PT12E 1 T PT7C 0 PT9B 1 C PT12D 1 C 122 PT7A 0 PT9A 1 T PT12C 1 T 123 GND - GND - GND - 124 PT6B 0 125 PT6A 0 126 PT5C 0 127 PT5B 0 128 VCCAUX - VCCAUX - VCCAUX - 129 VCC - VCC - VCC - 130 PT4D 0 PT5D 0 C PT7B 0 C 131 PT4B 0 C PT5C 0 T PT7A 0 T 132 PT4A 0 T PT5B 0 C PT6D 0 T PT6E 0 T PT6F 0 C T PCLK0_1*** C PT7D 1 PT10B 1 T PT7B 1 C PT9D 1 PT7A 1 T PT9C 1 PT6F 0 PT9B 1 PCLK0_0*** 133 PT3F 0 PT5A 0 134 PT3D 0 PT4B 0 PCLK1_1*** PCLK1_0*** C PCLK1_1*** C T PCLK1_0*** 135 VCCIO0 0 VCCIO0 0 VCCIO0 0 136 GNDIO0 0 GNDIO0 0 GNDIO0 0 137 PT3B 0 C PT3D 0 C PT4B 0 T 138 PT2F 0 C PT3C 0 T PT4A 0 C C 139 PT3A 0 T PT3B 0 C PT3B 0 140 PT2D 0 C PT3A 0 T PT3A 0 T 141 PT2E 0 T PT2D 0 C PT2D 0 C 142 PT2B 0 C PT2C 0 T PT2C 0 T 143 PT2C 0 T PT2B 0 C PT2B 0 C 144 PT2A 0 T PT2A 0 T PT2A 0 T *Supports true LVDS outputs. **NC for “E” devices. ***Primary clock inputs arer single-ended. 4-19 Pinout Information MachXO Family Data Sheet LCMXO640, LCMXO1200 and LCMXO2280 Logic Signal Connections: 256 caBGA / 256 ftBGA LCMXO640 Ball Ball Number Function Bank Dual Function LCMXO1200 Ball Ball Differential Number Function Bank Dual Function LCMXO2280 Ball Ball Differential Number Function Bank GND GNDIO3 3 GND GNDIO7 7 VCCIO3 VCCIO3 3 VCCIO7 VCCIO7 7 E4 NC E4 PL2A 7 T E5 NC E5 PL2B 7 C Dual Function Differential GND GNDIO7 7 VCCIO7 VCCIO7 7 E4 PL2A 7 LUM0_PLLT_FB_A T E5 PL2B 7 LUM0_PLLC_FB_A C F5 NC F5 PL3A 7 T* F5 PL3A 7 T* F6 NC F6 PL3B 7 C* F6 PL3B 7 C* F3 PL3A 3 T F3 PL3C 7 T F3 PL3C 7 LUM0_PLLT_IN_A T F4 PL3B 3 C F4 PL3D 7 C F4 PL3D 7 LUM0_PLLC_IN_A C E3 PL2C 3 T E3 PL4A 7 T* E3 PL4A 7 T* E2 PL2D 3 C E2 PL4B 7 C* E2 PL4B 7 C* C3 NC C3 PL4C 7 T C3 PL4C 7 T C2 NC C2 PL4D 7 C C2 PL4D 7 C B1 PL2A 3 T B1 PL5A 7 T* B1 PL5A 7 T* C1 PL2B 3 C C1 PL5B 7 C* C1 PL5B 7 C* 7 VCCIO3 VCCIO3 3 VCCIO7 VCCIO7 7 VCCIO7 VCCIO7 GND GNDIO3 3 GND GNDIO7 7 GND GNDIO7 7 D2 PL3C 3 T D2 PL5C 7 T D2 PL6C 7 T D1 PL3D 3 C D1 PL5D 7 C D1 PL6D 7 C F2 PL5A 3 G2 PL5B 3 GSRN T F2 PL6A 7 C G2 PL6B 7 GSRN T* F2 PL7A 7 C* G2 PL7B 7 T* GSRN C* E1 PL4A 3 T E1 PL6C 7 T E1 PL7C 7 T F1 PL4B 3 C F1 PL6D 7 C F1 PL7D 7 C G4 NC G4 PL7A 7 T* G4 PL8A 7 T* G5 NC G5 PL7B 7 C* G5 PL8B 7 C* GND GND - GND GND - GND GND - G3 PL4C 3 T G3 PL7C 7 T G3 PL8C 7 T H3 PL4D 3 C H3 PL7D 7 C H3 PL8D 7 C H4 NC H4 PL8A 7 T* H4 PL9A 7 T* H5 NC H5 PL8B 7 C* H5 PL9B 7 C* - - VCCIO7 VCCIO7 7 VCCIO7 VCCIO7 7 - - GND GNDIO7 7 GND GNDIO7 7 G1 PL5C 3 T G1 PL8C 7 T G1 PL10C 7 T H1 PL5D 3 C H1 PL8D 7 C H1 PL10D 7 C H2 PL6A 3 T H2 PL9A 6 T* H2 PL11A 6 T* J2 PL6B 3 C J2 PL9B 6 C* J2 PL11B 6 C* J3 PL7C 3 T J3 PL9C 6 T J3 PL11C 6 T K3 PL7D 3 C K3 PL9D 6 C K3 PL11D 6 C J1 PL6C 3 T T* T* - - J1 PL10A 6 VCCIO6 VCCIO6 6 J1 PL12A 6 VCCIO6 VCCIO6 6 6 - - GND GNDIO6 6 GND GNDIO6 K1 PL6D 3 C K1 PL10B 6 C* K1 PL12B 6 K2 PL9A 3 T K2 PL10C 6 T K2 PL12C 6 T L2 PL9B 3 C L2 PL10D 6 C L2 PL12D 6 C C* L1 PL7A 3 T L1 PL11A 6 T* L1 PL13A 6 T* M1 PL7B 3 C M1 PL11B 6 C* M1 PL13B 6 C* P1 PL8D 3 N1 PL8C 3 C P1 PL11D 6 T N1 PL11C 6 L3 PL10A 3 T L3 PL12A M3 M2 PL10B 3 C M3 PL9C 3 T M2 N2 PL9D 3 C N2 TSALL C P1 PL14D 6 T N1 PL14C 6 6 T* L3 PL15A 6 T* PL12B 6 C* M3 PL15B 6 C* PL12C 6 T M2 PL15C 6 T PL12D 6 C N2 PL15D 6 C TSALL VCCIO3 VCCIO3 3 VCCIO6 VCCIO6 6 VCCIO6 VCCIO6 6 GND GNDIO3 3 GND GNDIO6 6 GND GNDIO6 6 4-20 C TSALL T Pinout Information MachXO Family Data Sheet LCMXO640, LCMXO1200 and LCMXO2280 Logic Signal Connections: 256 caBGA / 256 ftBGA (Cont.) LCMXO640 Ball Ball Number Function Bank Dual Function LCMXO1200 Ball Ball Differential Number Function Bank Dual Function LCMXO2280 Ball Ball Differential Number Function Bank Dual Function Differential J4 PL8A 3 T J4 PL13A 6 T* J4 PL16A 6 T* J5 PL8B 3 C J5 PL13B 6 C* J5 PL16B 6 C* R1 PL11A 3 T R1 PL13C 6 T R1 PL16C 6 T R2 PL11B 3 C R2 PL13D 6 C R2 PL16D 6 C - - - - - - GND GND - K5 NC K5 PL14A 6 LLM0_PLLT_FB_A T* K5 PL17A 6 LLM0_PLLT_FB_A T* K4 NC K4 PL14B 6 LLM0_PLLC_FB_A C* K4 PL17B 6 LLM0_PLLC_FB_A C* L5 PL10C 3 T L5 PL14C 6 T L5 PL17C 6 T L4 PL10D 3 C L4 PL14D 6 C L4 PL17D 6 C M5 NC M5 PL15A 6 LLM0_PLLT_IN_A T* M5 PL18A 6 LLM0_PLLT_IN_A T* M4 NC M4 PL15B 6 LLM0_PLLC_IN_A C* M4 PL18B 6 LLM0_PLLC_IN_A C* N4 PL11C 3 T N4 PL16A 6 T N4 PL19A 6 T N3 PL11D 3 C N3 PL16B 6 C N3 PL19B 6 C VCCIO3 VCCIO3 3 VCCIO6 VCCIO6 6 VCCIO6 VCCIO6 6 GND GNDIO3 3 GND GNDIO6 6 GND GNDIO6 6 GND GNDIO2 2 GND GNDIO5 5 GND GNDIO5 5 VCCIO2 VCCIO2 2 VCCIO5 VCCIO5 5 VCCIO5 VCCIO5 5 P4 TMS 2 P4 TMS 5 P4 TMS 5 P2 NC P2 PB2A 5 T P2 PB2A 5 T P3 NC P3 PB2B 5 C P3 PB2B 5 C N5 NC R3 TCK 2 TMS TCK N5 PB2C 5 R3 TCK 5 TMS T TCK N5 PB2C 5 R3 TCK 5 TMS T TCK N6 NC N6 PB2D 5 C N6 PB2D 5 T2 PB2A 2 T T2 PB3A 5 T T2 PB3A 5 T T3 PB2B 2 C T3 PB3B 5 C T3 PB3B 5 C R4 PB2C 2 T R4 PB3C 5 T R4 PB3C 5 T R5 PB2D 2 C R5 PB3D 5 C R5 PB3D 5 C P5 PB3A 2 T P5 PB4A 5 T P5 PB4A 5 T P6 PB3B 2 C P6 PB4B 5 C P6 PB4B 5 C T5 PB3C 2 M6 TDO 2 T TDO T5 PB4C 5 M6 TDO 5 T TDO T5 PB4C 5 M6 TDO 5 C T TDO T4 PB3D 2 C T4 PB4D 5 C T4 PB4D 5 C R6 PB4A 2 T R6 PB5A 5 T R6 PB5A 5 T GND GNDIO2 2 GND GNDIO5 5 GND GNDIO5 5 VCCIO2 VCCIO2 2 VCCIO5 VCCIO5 5 VCCIO5 VCCIO5 5 T6 PB4B 2 T6 PB5B 5 T6 PB5B 5 N7 TDI 2 N7 TDI 5 N7 TDI 5 T8 PB4C 2 T T8 PB5C 5 T T8 PB6A 5 T T7 PB4D 2 C T7 PB5D 5 C T7 PB6B 5 C M7 NC M7 PB6A 5 T M7 PB7C 5 T M8 NC M8 PB6B 5 C M8 PB7D 5 C C TDI C TDI C TDI T9 VCCAUX - T9 VCCAUX - T9 VCCAUX - R7 PB4E 2 T R7 PB6C 5 T R7 PB8C 5 T R8 PB4F 2 C R8 PB6D 5 C R8 PB8D 5 C - - VCCIO5 VCCIO5 5 VCCIO5 VCCIO5 5 - - GND GNDIO5 5 GND GNDIO5 5 P7 PB5C 2 T P7 PB6E 5 T P7 PB9A 4 T P8 PB5D 2 C P8 PB6F 5 C P8 PB9B 4 C N8 PB5A 2 N9 PB5B 2 P10 PB7B P9 PB7A M9 PB6B 2 T N8 PB7A 4 C N9 PB7B 4 2 C P10 PB7D 2 T P9 PB7C C M9 PB7F 4 PCLK2_1*** PCLK2_0*** T N8 PB10E 4 C N9 PB10F 4 4 C P10 PB10D 4 4 T P9 PB10C 4 C M9 PB10B 4 PCLK4_1*** PCLK4_0*** 4-21 T PCLK4_1*** C C T PCLK4_0*** C Pinout Information MachXO Family Data Sheet LCMXO640, LCMXO1200 and LCMXO2280 Logic Signal Connections: 256 caBGA / 256 ftBGA (Cont.) LCMXO640 Ball Ball Number Function Bank - Dual Function LCMXO1200 Ball Ball Differential Number Function Bank - VCCIO4 VCCIO4 Dual Function LCMXO2280 Ball Ball Differential Number Function Bank 4 VCCIO4 VCCIO4 Dual Function Differential 4 - - GND GNDIO4 4 GND GNDIO4 4 M10 PB6A 2 T M10 PB7E 4 T M10 PB10A 4 T R9 PB6C 2 T R9 PB8A 4 T R9 PB11C 4 T R10 PB6D 2 C R10 PB8B 4 C R10 PB11D 4 C T10 PB7C 2 T T10 PB8C 4 T T10 PB12A 4 T T11 PB7D 2 C T11 PB8D 4 C T11 PB12B 4 C N10 NC N10 PB8E 4 T N10 PB12C 4 T N11 NC N11 PB8F 4 C N11 PB12D 4 C 4 VCCIO2 VCCIO2 2 VCCIO4 VCCIO4 4 VCCIO4 VCCIO4 GND GNDIO2 2 GND GNDIO4 4 GND GNDIO4 4 R11 PB7E 2 T R11 PB9A 4 T R11 PB13A 4 T R12 PB7F 2 C R12 PB9B 4 C R12 PB13B 4 C P11 PB8A 2 T P11 PB9C 4 T P11 PB13C 4 T P12 PB8B 2 C P12 PB9D 4 C P12 PB13D 4 C T13 PB8C 2 T T13 PB9E 4 T T13 PB14A 4 T T12 PB8D 2 C T12 PB9F 4 C T12 PB14B 4 C R13 PB9A 2 T R13 PB10A 4 T R13 PB14C 4 T R14 PB9B 2 C R14 PB10B 4 C R14 PB14D 4 C GND GND - GND GND - GND GND - T14 PB9C 2 T T14 PB10C 4 T T14 PB15A 4 T T15 PB9D 2 C T15 PB10D 4 C T15 PB15B 4 C P13** SLEEPN - P13** SLEEPN - P13** SLEEPN - P14 PB9F 2 P14 PB10F 4 P14 PB15D 4 R15 NC R15 PB11A 4 T R15 PB16A 4 T R16 NC R16 PB11B 4 C R16 PB16B 4 C P15 NC P15 PB11C 4 T P15 PB16C 4 T P16 NC P16 PB11D 4 C P16 PB16D 4 C SLEEPN SLEEPN SLEEPN VCCIO2 VCCIO2 2 VCCIO4 VCCIO4 4 VCCIO4 VCCIO4 4 GND GNDIO2 2 GND GNDIO4 4 GND GNDIO4 4 GND GNDIO1 1 GND GNDIO3 3 GND GNDIO3 3 VCCIO1 VCCIO1 1 VCCIO3 VCCIO3 3 VCCIO3 VCCIO3 3 M11 NC M11 PR16B 3 C M11 PR20B 3 L11 NC L11 PR16A 3 T L11 PR20A 3 T N12 NC N12 PR15B 3 C* N12 PR18B 3 C* C N13 NC N13 PR15A 3 T* N13 PR18A 3 T* M13 NC M13 PR14D 3 C M13 PR17D 3 C M12 NC M12 PR14C 3 T M12 PR17C 3 T N14 PR11D 1 C N14 PR14B 3 C* N14 PR17B 3 C* N15 PR11C 1 T N15 PR14A 3 T* N15 PR17A 3 T* L13 PR11B 1 C L13 PR13D 3 C L13 PR16D 3 C L12 PR11A 1 T L12 PR13C 3 T L12 PR16C 3 T M14 PR10B 1 C M14 PR13B 3 C* M14 PR16B 3 C* 3 VCCIO1 VCCIO1 1 VCCIO3 VCCIO3 3 VCCIO3 VCCIO3 GND GNDIO1 1 GND GNDIO3 3 GND GNDIO3 3 L14 PR10A 1 T L14 PR13A 3 T* L14 PR16A 3 T* N16 PR10D 1 C N16 PR12D 3 C N16 PR15D 3 C M16 PR10C 1 T M16 PR12C 3 T M16 PR15C 3 T M15 PR9D 1 C M15 PR12B 3 C* M15 PR15B 3 C* L15 PR9C 1 T L15 PR12A 3 T* L15 PR15A 3 T* L16 PR9B 1 C L16 PR11D 3 C L16 PR14D 3 C K16 PR9A 1 T K16 PR11C 3 T K16 PR14C 3 T K13 PR8D 1 C K13 PR11B 3 C* K13 PR14B 3 C* 4-22 Pinout Information MachXO Family Data Sheet LCMXO640, LCMXO1200 and LCMXO2280 Logic Signal Connections: 256 caBGA / 256 ftBGA (Cont.) LCMXO640 Ball Ball Number Function Bank J13 PR8C 1 GND GND - K14 PR8B 1 J14 PR8A 1 K15 PR7D J15 PR7C - - Dual Function LCMXO1200 Ball Ball Differential Number Function Bank T J13 PR11A 3 GND GND - C K14 PR10D 3 T J14 PR10C 3 1 C K15 PR10B 1 T J15 GND Dual Function LCMXO2280 Ball Ball Differential Number Function Bank T* Dual Function Differential J13 PR14A 3 GND GND - C K14 PR13D 3 T J14 PR13C 3 T 3 C* K15 PR13B 3 C* PR10A 3 T* T* GNDIO3 3 J15 PR13A 3 GND GNDIO3 3 T* C - - VCCIO3 VCCIO3 3 VCCIO3 VCCIO3 3 K12 NC K12 PR9D 3 C K12 PR11D 3 J12 NC J12 PR9C 3 T J12 PR11C 3 T J16 PR7B J16 PR9B 3 C* J16 PR11B 3 C* 1 C C H16 PR7A 1 T H16 PR9A 3 T* H16 PR11A 3 T* H15 PR6B 1 C H15 PR8D 2 C H15 PR10D 2 C G15 PR6A 1 T G15 PR8C 2 T G15 PR10C 2 T H14 PR5D 1 C H14 PR8B 2 C* H14 PR10B 2 C* T T* T* G14 PR5C 1 GND GNDIO1 1 G14 PR8A 2 GND GNDIO2 2 G14 PR10A 2 GND GNDIO2 2 VCCIO1 VCCIO1 1 H13 PR6D 1 C VCCIO2 VCCIO2 2 H13 PR7D 2 C VCCIO2 VCCIO2 2 H13 PR9D 2 H12 PR6C 1 T H12 PR7C 2 T H12 PR9C 2 G13 PR4D 1 C G13 PR7B T 2 C* G13 PR9B 2 C* G12 PR4C 1 T G16 PR5B 1 C G12 G16 PR7A 2 T* G12 PR9A 2 T* PR6D 2 C G16 PR7D 2 F16 PR5A 1 T F16 C PR6C 2 T F16 PR7C 2 F15 PR4B 1 C F15 T PR6B 2 C* F15 PR7B 2 C* E15 PR4A E16 PR3B 1 T 1 C E15 PR6A 2 T* E15 PR7A 2 T* E16 PR5D 2 C E16 PR6D 2 D16 PR3A 1 T C D16 PR5C 2 T D16 PR6C 2 VCCIO1 VCCIO1 1 T VCCIO2 VCCIO2 2 VCCIO2 VCCIO2 2 GND GNDIO1 1 D15 PR2D 1 C GND GNDIO2 2 GND GNDIO2 2 D15 PR5B 2 C* D15 PR6B 2 C15 PR2C 1 C* T C15 PR5A 2 T* C15 PR6A 2 C16 PR2B T* 1 C C16 PR4D 2 C C16 PR5D 2 B16 C PR2A 1 T B16 PR4C 2 T B16 PR5C 2 T F14 PR3D 1 C F14 PR4B 2 C* F14 PR5B 2 C* E14 PR3C 1 T E14 PR4A 2 T* T* - - - - - - F12 NC F12 PR3D 2 F13 NC F13 PR3C 2 E12 NC E12 PR3B E13 NC E13 D13 NC D13 C E14 PR5A 2 GND GND - C F12 PR4D 2 T F13 PR4C 2 T 2 C* E12 PR4B 2 C* PR3A 2 T* E13 PR4A 2 T* PR2B 2 C D13 PR3B 2 C* T T* C D14 NC D14 PR2A 2 D14 PR3A 2 VCCIO0 VCCIO0 0 VCCIO2 VCCIO2 2 VCCIO2 VCCIO2 2 GND GNDIO0 0 GND GNDIO2 2 GND GNDIO2 2 GND GNDIO0 0 GND GNDIO1 1 GND GNDIO1 1 VCCIO0 VCCIO0 0 VCCIO1 VCCIO1 1 VCCIO1 VCCIO1 1 B15 NC B15 PT11D 1 C B15 PT16D 1 A15 NC A15 PT11C 1 T A15 PT16C 1 T C14 NC C14 PT11B 1 C C14 PT16B 1 C C B14 NC B14 PT11A 1 T B14 PT16A 1 T C13 PT9F 0 C C13 PT10F 1 C C13 PT15D 1 C B13 PT9E 0 T B13 PT10E 1 T B13 PT15C 1 T 4-23 Pinout Information MachXO Family Data Sheet LCMXO640, LCMXO1200 and LCMXO2280 Logic Signal Connections: 256 caBGA / 256 ftBGA (Cont.) LCMXO640 Ball Ball Number Function Bank Dual Function LCMXO1200 Ball Ball Differential Number Function Bank Dual Function LCMXO2280 Ball Ball Differential Number Function Bank Dual Function Differential E11 NC E11 PT10D 1 C E11 PT15B 1 E10 NC E10 PT10C 1 T E10 PT15A 1 C T D12 PT9D 0 C D12 PT10B 1 C D12 PT14D 1 C D11 PT9C 0 T D11 PT10A 1 T D11 PT14C 1 T A14 PT7F 0 C A14 PT9F 1 C A14 PT14B 1 C A13 PT7E 0 T A13 PT9E 1 T A13 PT14A 1 T C12 PT8B 0 C C12 PT9D 1 C C12 PT13D 1 C C11 PT8A 0 T T T - - C11 PT9C 1 VCCIO1 VCCIO1 1 C11 PT13C 1 VCCIO1 VCCIO1 1 - - GND GNDIO1 1 GND GNDIO1 1 B12 PT7B 0 C B12 PT9B 1 C B12 PT12D 1 B11 PT7A 0 T B11 PT9A 1 T B11 PT12C 1 T A12 PT7D 0 C A12 PT8F 1 C A12 PT12B 1 C A11 PT7C 0 T A11 PT8E 1 T T GND GND - GND GND - A11 PT12A 1 GND GND - C B10 PT5D 0 C B10 PT8D 1 C B10 PT11B 1 B9 PT5C 0 T B9 PT8C 1 T B9 PT11A 1 T D10 PT8D 0 C D10 PT8B 1 C D10 PT10F 1 C D9 PT8C 0 T T T - - D9 PT8A 1 VCCIO1 VCCIO1 1 D9 PT10E 1 VCCIO1 VCCIO1 1 - - GND GNDIO1 1 GND GNDIO1 1 C10 PT6D 0 C C10 PT7F 1 C C10 PT10D 1 C9 PT6C 0 T C9 PT7E 1 T C9 PT10C 1 A9 PT6B 0 C A9 PT7D 1 C A9 PT10B 1 PCLK0_1*** PCLK1_1*** C C T PCLK1_1*** C A10 PT6A 0 T A10 PT7C 1 T A10 PT10A 1 T E9 PT9B 0 C E9 PT7B 1 C E9 PT9D 1 C T E8 PT7A 1 T E8 PT9C 1 C D7 PT6F 0 C D7 PT9B 1 E8 PT9A 0 D7 PT5B 0 PCLK0_0*** T PCLK1_0*** D8 PT5A 0 VCCIO0 VCCIO0 0 D8 PT6E 0 VCCIO0 VCCIO0 0 GND GNDIO0 0 C8 PT4F 0 C GND GNDIO0 0 C8 PT6D 0 C B8 PT4E 0 T B8 PT6C 0 T A8 VCCAUX - A8 VCCAUX - A7 PT4D 0 C A6 PT4C 0 T A7 PT6B 0 A6 PT6A 0 VCC VCC - VCC VCC - B7 PT4B 0 C B7 PT5F 0 C B6 PT4A 0 T B6 PT5E 0 T C6 PT3C 0 T C6 PT5C 0 T C7 PT3D 0 C C7 PT5D 0 A5 PT3E 0 T A5 PT5A A4 PT3F 0 C A4 PT5B E7 NC E7 PT4C E6 NC E6 PT4D B5 PT3B 0 C B5 B4 PT3A 0 T B4 D5 PT2D 0 C D5 D6 PT2C 0 T C4 PT2E 0 T C5 PT2F 0 C - - - D4 NC C D8 PT9A 1 VCCIO0 VCCIO0 0 GND GNDIO0 0 C8 PT8D 0 C B8 PT8C 0 T A8 VCCAUX - C A7 PT7D 0 C T A6 PT7C 0 T VCC VCC - B7 PT7B 0 C B6 PT7A 0 T C6 PT6A 0 T C C7 PT6B 0 C 0 T A5 PT6C 0 T 0 C A4 PT6D 0 C 0 T E7 PT6E 0 T 0 C E6 PT6F 0 C PT3F 0 C B5 PT5D 0 C PT3E 0 T B4 PT5C 0 T PT3D 0 C D5 PT5B 0 C D6 PT3C 0 T D6 PT5A 0 T C4 PT4A 0 T C4 PT4A 0 T C5 PT4B 0 C C5 PT4B 0 C - - - D4 PT2D 0 T T PCLK1_0*** C 4-24 GND GND - D4 PT3D 0 T C Pinout Information MachXO Family Data Sheet LCMXO640, LCMXO1200 and LCMXO2280 Logic Signal Connections: 256 caBGA / 256 ftBGA (Cont.) LCMXO640 Ball Ball Number Function Bank D3 NC A3 PT2B 0 A2 PT2A 0 B3 NC Dual Function LCMXO1200 Ball Ball Differential Number Function Bank Dual Function LCMXO2280 Ball Ball Differential Number Function Bank Dual Function Differential D3 PT2C 0 T D3 PT3C 0 T C A3 PT3B 0 C A3 PT3B 0 C T A2 PT3A 0 T A2 PT3A 0 T B3 PT2B 0 C B3 PT2D 0 C T T B2 NC B2 PT2A 0 B2 PT2C 0 VCCIO0 VCCIO0 0 VCCIO0 VCCIO0 0 VCCIO0 VCCIO0 0 GND GNDIO0 0 GND GNDIO0 0 GND GNDIO0 0 A1 GND - A1 GND - A1 GND - A16 GND - A16 GND - A16 GND - F11 GND - F11 GND - F11 GND - G8 GND - G8 GND - G8 GND - G9 GND - G9 GND - G9 GND - H7 GND - H7 GND - H7 GND - H8 GND - H8 GND - H8 GND - H9 GND - H9 GND - H9 GND - H10 GND - H10 GND - H10 GND - J7 GND - J7 GND - J7 GND - J8 GND - J8 GND - J8 GND - J9 GND - J9 GND - J9 GND - J10 GND - J10 GND - J10 GND - K8 GND - K8 GND - K8 GND - K9 GND - K9 GND - K9 GND - L6 GND - L6 GND - L6 GND - T1 GND - T1 GND - T1 GND - T16 GND - T16 GND - T16 GND - G7 VCC - G7 VCC - G7 VCC - G10 VCC - G10 VCC - G10 VCC - K7 VCC - K7 VCC - K7 VCC - K10 VCC - K10 VCC - K10 VCC - H6 VCCIO3 3 H6 VCCIO7 7 H6 VCCIO7 7 G6 VCCIO3 3 G6 VCCIO7 7 G6 VCCIO7 7 K6 VCCIO3 3 K6 VCCIO6 6 K6 VCCIO6 6 J6 VCCIO3 3 J6 VCCIO6 6 J6 VCCIO6 6 L8 VCCIO2 2 L8 VCCIO5 5 L8 VCCIO5 5 L7 VCCIO2 2 L7 VCCIO5 5 L7 VCCIO5 5 L9 VCCIO2 2 L9 VCCIO4 4 L9 VCCIO4 4 L10 VCCIO2 2 L10 VCCIO4 4 L10 VCCIO4 4 K11 VCCIO1 1 K11 VCCIO3 3 K11 VCCIO3 3 J11 VCCIO1 1 J11 VCCIO3 3 J11 VCCIO3 3 H11 VCCIO1 1 H11 VCCIO2 2 H11 VCCIO2 2 G11 VCCIO1 1 G11 VCCIO2 2 G11 VCCIO2 2 F9 VCCIO0 0 F9 VCCIO1 1 F9 VCCIO1 1 F10 VCCIO0 0 F10 VCCIO1 1 F10 VCCIO1 1 F8 VCCIO0 0 F8 VCCIO0 0 F8 VCCIO0 0 F7 VCCIO0 0 F7 VCCIO0 0 F7 VCCIO0 0 * Supports true LVDS outputs. ** NC for “E” devices. *** Primary clock inputs are single-ended. 4-25 Pinout Information MachXO Family Data Sheet LCMXO2280 Logic Signal Connections: 324 ftBGA LCMXO2280 Ball Number Ball Function Bank GND GNDIO7 7 VCCIO7 VCCIO7 7 Dual Function Differential D4 PL2A 7 LUM0_PLLT_FB_A T F5 PL2B 7 LUM0_PLLC_FB_A C B3 PL3A 7 C3 PL3B 7 E4 PL3C 7 LUM0_PLLT_IN_A T G6 PL3D 7 LUM0_PLLC_IN_A C T* C* A1 PL4A 7 T* B1 PL4B 7 C* F4 PL4C 7 T VCC VCC - E3 PL4D 7 C D2 PL5A 7 T* D3 PL5B 7 C* G5 PL5C 7 T F3 PL5D 7 C T* C2 PL6A 7 VCCIO7 VCCIO7 7 GND GNDIO7 7 C1 PL6B 7 C* H5 PL6C 7 T G4 PL6D 7 C E2 PL7A 7 D1 PL7B 7 T* J6 PL7C 7 H4 PL7D 7 C F2 PL8A 7 T* E1 PL8B 7 C* GSRN C* T GND GND - J3 PL8C 7 T J5 PL8D 7 C G3 PL9A 7 T* H3 PL9B 7 C* K3 PL9C 7 T K5 PL9D 7 C F1 PL10A 7 T* VCCIO7 VCCIO7 7 GND GNDIO7 7 G1 PL10B 7 C* K4 PL10C 7 T K6 PL10D 7 C 4-26 Pinout Information MachXO Family Data Sheet LCMXO2280 Logic Signal Connections: 324 ftBGA (Cont.) LCMXO2280 Ball Number Ball Function Bank G2 PL11A 6 Dual Function Differential T* H2 PL11B 6 C* L3 PL11C 6 T L5 PL11D 6 C H1 PL12A 6 T* VCCIO6 VCCIO6 6 GND GNDIO6 6 J2 PL12B 6 C* L4 PL12C 6 T L6 PL12D 6 C K2 PL13A 6 T* K1 PL13B 6 C* T J1 PL13C 6 VCC VCC - L2 PL13D 6 C M5 PL14D 6 M3 PL14C 6 C L1 PL14B 6 C* M2 PL14A 6 T* M1 PL15A 6 T* N1 PL15B 6 C* M6 PL15C 6 T M4 PL15D 6 C VCCIO6 VCCIO6 6 GND GNDIO6 6 P1 PL16A 6 T* P2 PL16B 6 C* N3 PL16C 6 T N4 PL16D 6 C GND GND - TSALL T T1 PL17A 6 LLM0_PLLT_FB_A T* R1 PL17B 6 LLM0_PLLC_FB_A C* P3 PL17C 6 N5 PL17D 6 R3 PL18A 6 LLM0_PLLT_IN_A T* R2 PL18B 6 LLM0_PLLC_IN_A C* P4 PL19A 6 T N6 PL19B 6 C T U1 PL20A 6 VCCIO6 VCCIO6 6 GND GNDIO6 6 GND GNDIO5 5 VCCIO5 VCCIO5 5 4-27 T C Pinout Information MachXO Family Data Sheet LCMXO2280 Logic Signal Connections: 324 ftBGA (Cont.) LCMXO2280 Ball Number Ball Function Bank T2 PL20B 6 Dual Function Differential P6 TMS 5 V1 PB2A 5 T U2 PB2B 5 C T3 PB2C 5 T N7 TCK 5 R4 PB2D 5 R5 PB3A 5 T T4 PB3B 5 C C TMS TCK C VCC VCC - R6 PB3C 5 T P7 PB3D 5 C U3 PB4A 5 T T5 PB4B 5 C V2 PB4C 5 T N8 TDO 5 V3 PB4D 5 C T6 PB5A 5 T TDO GND GNDIO5 5 VCCIO5 VCCIO5 5 U4 PB5B 5 P8 PB5C 5 T T7 PB5D 5 C V4 TDI 5 R8 PB6A 5 T N9 PB6B 5 C U5 PB6C 5 T C TDI V5 PB6D 5 C U6 PB7A 5 T VCC VCC - V6 PB7B 5 P9 PB7C 5 T T8 PB7D 5 C U7 PB8A 5 T V7 PB8B 5 C M10 VCCAUX - U8 PB8C 5 T V8 PB8D 5 C VCCIO5 VCCIO5 5 GND GNDIO5 5 T9 PB8E 5 T U9 PB8F 5 C V9 PB9A 4 T 4-28 C Pinout Information MachXO Family Data Sheet LCMXO2280 Logic Signal Connections: 324 ftBGA (Cont.) LCMXO2280 Ball Number Ball Function Bank V10 PB9B 4 Dual Function Differential N10 PB9C 4 T R10 PB9D 4 C C P10 PB10F 4 T10 PB10E 4 PCLK4_1*** C T U10 PB10D 4 C V11 PB10C 4 U11 PB10B 4 T VCCIO4 VCCIO4 4 GND GNDIO4 4 T11 PB10A 4 T U12 PB11A 4 T C PCLK4_0*** C R11 PB11B 4 GND GND - T12 PB11C 4 T P11 PB11D 4 C V12 PB12A 4 T V13 PB12B 4 C R12 PB12C 4 T N11 PB12D 4 C U13 PB12E 4 T VCCIO4 VCCIO4 4 GND GNDIO4 4 V14 PB12F 4 C T13 PB13A 4 T P12 PB13B 4 C R13 PB13C 4 T N12 PB13D 4 C V15 PB14A 4 T U14 PB14B 4 C T V16 PB14C 4 GND GND - T14 PB14D 4 U15 PB15A 4 T V17 PB15B 4 C P13** SLEEPN - T15 PB15D 4 U16 PB16A 4 T C C SLEEPN V18 PB16B 4 N13 PB16C 4 T R14 PB16D 4 C VCCIO4 VCCIO4 4 GND GNDIO4 4 4-29 Pinout Information MachXO Family Data Sheet LCMXO2280 Logic Signal Connections: 324 ftBGA (Cont.) LCMXO2280 Ball Number Ball Function Bank GND GNDIO3 3 Dual Function Differential VCCIO3 VCCIO3 3 P15 PR20B 3 N14 PR20A 3 T N15 PR19B 3 C M13 PR19A 3 T R15 PR18B 3 C* T16 PR18A 3 T* N16 PR17D 3 C M14 PR17C 3 T U17 PR17B 3 C* VCC VCC - C U18 PR17A 3 T* R17 PR16D 3 C R16 PR16C 3 T C* P16 PR16B 3 VCCIO3 VCCIO3 3 GND GNDIO3 3 P17 PR16A 3 T* L13 PR15D 3 C M15 PR15C 3 T T17 PR15B 3 C* T18 PR15A 3 T* L14 PR14D 3 C L15 PR14C 3 T R18 PR14B 3 C* P18 PR14A 3 T* GND GND - K15 PR13D 3 C K13 PR13C 3 T N17 PR13B 3 C* N18 PR13A 3 T* K16 PR12D 3 C K14 PR12C 3 T M16 PR12B 3 C* L16 PR12A 3 T* GND GNDIO3 3 VCCIO3 VCCIO3 3 J16 PR11D 3 J14 PR11C 3 T M17 PR11B 3 C* L17 PR11A 3 T* J15 PR10D 2 C 4-30 C Pinout Information MachXO Family Data Sheet LCMXO2280 Logic Signal Connections: 324 ftBGA (Cont.) LCMXO2280 Ball Number Ball Function Bank J13 PR10C 2 Dual Function Differential T M18 PR10B 2 C* L18 PR10A 2 T* GND GNDIO2 2 VCCIO2 VCCIO2 2 H16 PR9D 2 H14 PR9C 2 T K18 PR9B 2 C* J18 PR9A 2 T* C C J17 PR8D 2 VCC VCC - H18 PR8C 2 T H17 PR8B 2 C* G17 PR8A 2 T* H13 PR7D 2 C H15 PR7C 2 T G18 PR7B 2 C* F18 PR7A 2 T* G14 PR6D 2 C G16 PR6C 2 T VCCIO2 VCCIO2 2 GND GNDIO2 2 E18 PR6B 2 C* F17 PR6A 2 T* G13 PR5D 2 C G15 PR5C 2 T E17 PR5B 2 C* T* E16 PR5A 2 GND GND - F15 PR4D 2 C E15 PR4C 2 T D17 PR4B 2 C* D18 PR4A 2 T* B18 PR3D 2 C C18 PR3C 2 T C16 PR3B 2 C* D16 PR3A 2 T* C17 PR2B 2 C T D15 PR2A 2 VCCIO2 VCCIO2 2 GND GNDIO2 2 GND GNDIO1 1 VCCIO1 VCCIO1 1 4-31 Pinout Information MachXO Family Data Sheet LCMXO2280 Logic Signal Connections: 324 ftBGA (Cont.) LCMXO2280 Ball Number Ball Function Bank E13 PT16D 1 Dual Function Differential C15 PT16C 1 T F13 PT16B 1 C C D14 PT16A 1 T A18 PT15D 1 C B17 PT15C 1 T A16 PT15B 1 C A17 PT15A 1 T VCC VCC - D13 PT14D 1 C F12 PT14C 1 T C14 PT14B 1 C E12 PT14A 1 T C13 PT13D 1 C B16 PT13C 1 T B15 PT13B 1 C A15 PT13A 1 T VCCIO1 VCCIO1 1 GND GNDIO1 1 B14 PT12F 1 C A14 PT12E 1 T D12 PT12D 1 C F11 PT12C 1 T B13 PT12B 1 C A13 PT12A 1 T C12 PT11D 1 C GND GND - B12 PT11C 1 T E11 PT11B 1 C D11 PT11A 1 T C11 PT10F 1 C A12 PT10E 1 T VCCIO1 VCCIO1 1 GND GNDIO1 1 F10 PT10D 1 C D10 PT10C 1 T B11 PT10B 1 A11 PT10A 1 PCLK1_1*** C T C E10 PT9D 1 C10 PT9C 1 D9 PT9B 1 E9 PT9A 1 T B10 PT8F 0 C 4-32 T PCLK1_0*** C Pinout Information MachXO Family Data Sheet LCMXO2280 Logic Signal Connections: 324 ftBGA (Cont.) LCMXO2280 Ball Number Ball Function Bank A10 PT8E 0 VCCIO0 VCCIO0 0 GND GNDIO0 0 Dual Function Differential T A9 PT8D 0 C C9 PT8C 0 T B9 PT8B 0 C F9 VCCAUX - A8 PT8A 0 T B8 PT7D 0 C T C8 PT7C 0 VCC VCC - A7 PT7B 0 C B7 PT7A 0 T A6 PT6A 0 T B6 PT6B 0 C D8 PT6C 0 T F8 PT6D 0 C C7 PT6E 0 T E8 PT6F 0 C D7 PT5D 0 C VCCIO0 VCCIO0 0 GND GNDIO0 0 E7 PT5C 0 T A5 PT5B 0 C C6 PT5A 0 T B5 PT4A 0 T A4 PT4B 0 C D6 PT4C 0 T F7 PT4D 0 C B4 PT4E 0 T GND GND - C5 PT4F 0 C F6 PT3D 0 C E5 PT3C 0 T E6 PT3B 0 C D5 PT3A 0 T A3 PT2D 0 C C4 PT2C 0 T A2 PT2B 0 C B2 PT2A 0 T VCCIO0 VCCIO0 0 GND GNDIO0 0 E14 GND - 4-33 Pinout Information MachXO Family Data Sheet LCMXO2280 Logic Signal Connections: 324 ftBGA (Cont.) LCMXO2280 Ball Number Ball Function Bank F16 GND - H10 GND - H11 GND - H8 GND - H9 GND - J10 GND - J11 GND - J4 GND - J8 GND - J9 GND - K10 GND - K11 GND - K17 GND - K8 GND - K9 GND - L10 GND - L11 GND - L8 GND - L9 GND - N2 GND - P14 GND - P5 GND - R7 GND - F14 VCC - G11 VCC - G9 VCC - H7 VCC - L7 VCC - M9 VCC - H6 VCCIO7 7 J7 VCCIO7 7 M7 VCCIO6 6 K7 VCCIO6 6 M8 VCCIO5 5 R9 VCCIO5 5 M12 VCCIO4 4 M11 VCCIO4 4 L12 VCCIO3 3 K12 VCCIO3 3 J12 VCCIO2 2 H12 VCCIO2 2 G12 VCCIO1 1 G10 VCCIO1 1 4-34 Dual Function Differential Pinout Information MachXO Family Data Sheet LCMXO2280 Logic Signal Connections: 324 ftBGA (Cont.) LCMXO2280 Ball Number Ball Function Bank G8 VCCIO0 0 G7 VCCIO0 0 * Supports true LVDS outputs. ** NC for “E” devices. *** Primary clock inputs are single-ended. 4-35 Dual Function Differential Pinout Information MachXO Family Data Sheet Thermal Management Thermal management is recommended as part of any sound FPGA design methodology. To assess the thermal characteristics of a system, Lattice specifies a maximum allowable junction temperature in all device data sheets. Designers must complete a thermal analysis of their specific design to ensure that the device and package do not exceed the junction temperature limits. Refer to the Thermal Management document to find the device/package specific thermal values. For Further Information For further information regarding Thermal Management, refer to the following: • Thermal Management document • TN1090 - Power Estimation and Management for MachXO Devices • Power Calculator tool included with the Lattice ispLEVER design tool, or as a standalone download from  www.latticesemi.com/software 4-36 MachXO Family Data Sheet Ordering Information June 2013 Data Sheet DS1002 Part Number Description LCMXO XXXX X – X XXXXXX X XX ES = Engineering Sample Blank = Production Device Device Family MachXO PLD Grade C = Commercial I = Industrial Logic Capacity 256 LUTs = 256 640 LUTs = 640 1200 LUTs = 1200 2280 LUTs = 2280 Package T100 = 100-pin TQFP T144 = 144-pin TQFP M100 = 100-ball csBGA M132 = 132-ball csBGA B256 = 256-ball caBGA FT256 = 256-ball ftBGA FT324 = 324-ball ftBGA SupplyVoltage C = 1.8V/2.5V/3.3V E = 1.2V Note: Parts dual marked as described. TN100 = 100-pin Lead-Free TQFP TN144 = 144-pin Lead-Free TQFP MN100 = 100-ball Lead-Free csBGA MN132 = 132-ball Lead-Free csBGA BN256 = 256-ball Lead-Free caBGA FTN256 = 256-ball Lead-Free ftBGA FTN324 = 324-ball Lead-Free ftBGA Speed 3 = Slowest 4 5 = Fastest Ordering Information Note: MachXO devices are dual marked except the slowest commercial speed grade device.þFor example the commercial speed grade LCMXO640E-4F256C is also marked with industrial grade -3I grade.þThe slowest commercial speed grade does not have industrial markings.þ The markings appears as follows: LCMXO640E 4F256C-3I Datecode Dual Mark © 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 5-1 DS1002 Ordering Information_01.8 Ordering Information MachXO Family Data Sheet Conventional Packaging Commercial Part Number LUTs Supply Voltage I/Os Grade Package Pins Temp. LCMXO256C-3T100C 256 1.8V/2.5V/3.3V 78 -3 TQFP 100 COM LCMXO256C-4T100C 256 1.8V/2.5V/3.3V 78 -4 TQFP 100 COM LCMXO256C-5T100C 256 1.8V/2.5V/3.3V 78 -5 TQFP 100 COM LCMXO256C-3M100C 256 1.8V/2.5V/3.3V 78 -3 csBGA 100 COM LCMXO256C-4M100C 256 1.8V/2.5V/3.3V 78 -4 csBGA 100 COM LCMXO256C-5M100C 256 1.8V/2.5V/3.3V 78 -5 csBGA 100 COM LUTs Supply Voltage I/Os Grade Package Pins Temp. LCMXO640C-3T100C Part Number 640 1.8V/2.5V/3.3V 74 -3 TQFP 100 COM LCMXO640C-4T100C 640 1.8V/2.5V/3.3V 74 -4 TQFP 100 COM LCMXO640C-5T100C 640 1.8V/2.5V/3.3V 74 -5 TQFP 100 COM LCMXO640C-3M100C 640 1.8V/2.5V/3.3V 74 -3 csBGA 100 COM LCMXO640C-4M100C 640 1.8V/2.5V/3.3V 74 -4 csBGA 100 COM LCMXO640C-5M100C 640 1.8V/2.5V/3.3V 74 -5 csBGA 100 COM LCMXO640C-3T144C 640 1.8V/2.5V/3.3V 113 -3 TQFP 144 COM LCMXO640C-4T144C 640 1.8V/2.5V/3.3V 113 -4 TQFP 144 COM LCMXO640C-5T144C 640 1.8V/2.5V/3.3V 113 -5 TQFP 144 COM LCMXO640C-3M132C 640 1.8V/2.5V/3.3V 101 -3 csBGA 132 COM LCMXO640C-4M132C 640 1.8V/2.5V/3.3V 101 -4 csBGA 132 COM LCMXO640C-5M132C 640 1.8V/2.5V/3.3V 101 -5 csBGA 132 COM LCMXO640C-3B256C 640 1.8V/2.5V/3.3V 159 -3 caBGA 256 COM LCMXO640C-4B256C 640 1.8V/2.5V/3.3V 159 -4 caBGA 256 COM LCMXO640C-5B256C 640 1.8V/2.5V/3.3V 159 -5 caBGA 256 COM LCMXO640C-3FT256C 640 1.8V/2.5V/3.3V 159 -3 ftBGA 256 COM LCMXO640C-4FT256C 640 1.8V/2.5V/3.3V 159 -4 ftBGA 256 COM LCMXO640C-5FT256C 640 1.8V/2.5V/3.3V 159 -5 ftBGA 256 COM LUTs Supply Voltage I/Os Grade Package Pins Temp. LCMXO1200C-3T100C 1200 1.8V/2.5V/3.3V 73 -3 TQFP 100 COM LCMXO1200C-4T100C 1200 1.8V/2.5V/3.3V 73 -4 TQFP 100 COM LCMXO1200C-5T100C 1200 1.8V/2.5V/3.3V 73 -5 TQFP 100 COM LCMXO1200C-3T144C 1200 1.8V/2.5V/3.3V 113 -3 TQFP 144 COM LCMXO1200C-4T144C 1200 1.8V/2.5V/3.3V 113 -4 TQFP 144 COM LCMXO1200C-5T144C 1200 1.8V/2.5V/3.3V 113 -5 TQFP 144 COM LCMXO1200C-3M132C 1200 1.8V/2.5V/3.3V 101 -3 csBGA 132 COM LCMXO1200C-4M132C 1200 1.8V/2.5V/3.3V 101 -4 csBGA 132 COM LCMXO1200C-5M132C 1200 1.8V/2.5V/3.3V 101 -5 csBGA 132 COM LCMXO1200C-3B256C 1200 1.8V/2.5V/3.3V 211 -3 caBGA 256 COM LCMXO1200C-4B256C 1200 1.8V/2.5V/3.3V 211 -4 caBGA 256 COM LCMXO1200C-5B256C 1200 1.8V/2.5V/3.3V 211 -5 caBGA 256 COM LCMXO1200C-3FT256C 1200 1.8V/2.5V/3.3V 211 -3 ftBGA 256 COM LCMXO1200C-4FT256C 1200 1.8V/2.5V/3.3V 211 -4 ftBGA 256 COM LCMXO1200C-5FT256C 1200 1.8V/2.5V/3.3V 211 -5 ftBGA 256 COM Part Number 5-2 Ordering Information MachXO Family Data Sheet Part Number LUTs Supply Voltage I/Os Grade Package Pins Temp. LCMXO2280C-3T100C 2280 1.8V/2.5V/3.3V 73 -3 TQFP 100 COM LCMXO2280C-4T100C 2280 1.8V/2.5V/3.3V 73 -4 TQFP 100 COM LCMXO2280C-5T100C 2280 1.8V/2.5V/3.3V 73 -5 TQFP 100 COM LCMXO2280C-3T144C 2280 1.8V/2.5V/3.3V 113 -3 TQFP 144 COM LCMXO2280C-4T144C 2280 1.8V/2.5V/3.3V 113 -4 TQFP 144 COM LCMXO2280C-5T144C 2280 1.8V/2.5V/3.3V 113 -5 TQFP 144 COM LCMXO2280C-3M132C 2280 1.8V/2.5V/3.3V 101 -3 csBGA 132 COM LCMXO2280C-4M132C 2280 1.8V/2.5V/3.3V 101 -4 csBGA 132 COM LCMXO2280C-5M132C 2280 1.8V/2.5V/3.3V 101 -5 csBGA 132 COM LCMXO2280C-3B256C 2280 1.8V/2.5V/3.3V 211 -3 caBGA 256 COM LCMXO2280C-4B256C 2280 1.8V/2.5V/3.3V 211 -4 caBGA 256 COM LCMXO2280C-5B256C 2280 1.8V/2.5V/3.3V 211 -5 caBGA 256 COM LCMXO2280C-3FT256C 2280 1.8V/2.5V/3.3V 211 -3 ftBGA 256 COM LCMXO2280C-4FT256C 2280 1.8V/2.5V/3.3V 211 -4 ftBGA 256 COM LCMXO2280C-5FT256C 2280 1.8V/2.5V/3.3V 211 -5 ftBGA 256 COM LCMXO2280C-3FT324C 2280 1.8V/2.5V/3.3V 271 -3 ftBGA 324 COM LCMXO2280C-4FT324C 2280 1.8V/2.5V/3.3V 271 -4 ftBGA 324 COM LCMXO2280C-5FT324C 2280 1.8V/2.5V/3.3V 271 -5 ftBGA 324 COM Part Number LUTs Supply Voltage I/Os Grade Package Pins Temp. LCMXO256E-3T100C 256 1.2V 78 -3 TQFP 100 COM LCMXO256E-4T100C 256 1.2V 78 -4 TQFP 100 COM LCMXO256E-5T100C 256 1.2V 78 -5 TQFP 100 COM LCMXO256E-3M100C 256 1.2V 78 -3 csBGA 100 COM LCMXO256E-4M100C 256 1.2V 78 -4 csBGA 100 COM LCMXO256E-5M100C 256 1.2V 78 -5 csBGA 100 COM LUTs Supply Voltage I/Os Grade Package Pins Temp. LCMXO640E-3T100C Part Number 640 1.2V 74 -3 TQFP 100 COM LCMXO640E-4T100C 640 1.2V 74 -4 TQFP 100 COM LCMXO640E-5T100C 640 1.2V 74 -5 TQFP 100 COM LCMXO640E-3M100C 640 1.2V 74 -3 csBGA 100 COM LCMXO640E-4M100C 640 1.2V 74 -4 csBGA 100 COM LCMXO640E-5M100C 640 1.2V 74 -5 csBGA 100 COM LCMXO640E-3T144C 640 1.2V 113 -3 TQFP 144 COM LCMXO640E-4T144C 640 1.2V 113 -4 TQFP 144 COM LCMXO640E-5T144C 640 1.2V 113 -5 TQFP 144 COM LCMXO640E-3M132C 640 1.2V 101 -3 csBGA 132 COM LCMXO640E-4M132C 640 1.2V 101 -4 csBGA 132 COM LCMXO640E-5M132C 640 1.2V 101 -5 csBGA 132 COM LCMXO640E-3B256C 640 1.2V 159 -3 caBGA 256 COM LCMXO640E-4B256C 640 1.2V 159 -4 caBGA 256 COM LCMXO640E-5B256C 640 1.2V 159 -5 caBGA 256 COM LCMXO640E-3FT256C 640 1.2V 159 -3 ftBGA 256 COM LCMXO640E-4FT256C 640 1.2V 159 -4 ftBGA 256 COM LCMXO640E-5FT256C 640 1.2V 159 -5 ftBGA 256 COM 5-3 Ordering Information MachXO Family Data Sheet Part Number LUTs Supply Voltage I/Os Grade Package Pins Temp. LCMXO1200E-3T100C 1200 1.2V 73 -3 TQFP 100 COM LCMXO1200E-4T100C 1200 1.2V 73 -4 TQFP 100 COM LCMXO1200E-5T100C 1200 1.2V 73 -5 TQFP 100 COM LCMXO1200E-3T144C 1200 1.2V 113 -3 TQFP 144 COM LCMXO1200E-4T144C 1200 1.2V 113 -4 TQFP 144 COM LCMXO1200E-5T144C 1200 1.2V 113 -5 TQFP 144 COM LCMXO1200E-3M132C 1200 1.2V 101 -3 csBGA 132 COM LCMXO1200E-4M132C 1200 1.2V 101 -4 csBGA 132 COM LCMXO1200E-5M132C 1200 1.2V 101 -5 csBGA 132 COM LCMXO1200E-3B256C 1200 1.2V 211 -3 caBGA 256 COM LCMXO1200E-4B256C 1200 1.2V 211 -4 caBGA 256 COM LCMXO1200E-5B256C 1200 1.2V 211 -5 caBGA 256 COM LCMXO1200E-3FT256C 1200 1.2V 211 -3 ftBGA 256 COM LCMXO1200E-4FT256C 1200 1.2V 211 -4 ftBGA 256 COM LCMXO1200E-5FT256C 1200 1.2V 211 -5 ftBGA 256 COM LUTs Supply Voltage I/Os Grade Package Pins Temp. LCMXO2280E-3T100C 2280 1.2V 73 -3 TQFP 100 COM LCMXO2280E-4T100C 2280 1.2V 73 -4 TQFP 100 COM LCMXO2280E-5T100C 2280 1.2V 73 -5 TQFP 100 COM LCMXO2280E-3T144C 2280 1.2V 113 -3 TQFP 144 COM LCMXO2280E-4T144C 2280 1.2V 113 -4 TQFP 144 COM LCMXO2280E-5T144C 2280 1.2V 113 -5 TQFP 144 COM LCMXO2280E-3M132C 2280 1.2V 101 -3 csBGA 132 COM LCMXO2280E-4M132C 2280 1.2V 101 -4 csBGA 132 COM LCMXO2280E-5M132C 2280 1.2V 101 -5 csBGA 132 COM LCMXO2280E-3B256C 2280 1.2V 211 -3 caBGA 256 COM LCMXO2280E-4B256C 2280 1.2V 211 -4 caBGA 256 COM LCMXO2280E-5B256C 2280 1.2V 211 -5 caBGA 256 COM LCMXO2280E-3FT256C 2280 1.2V 211 -3 ftBGA 256 COM LCMXO2280E-4FT256C 2280 1.2V 211 -4 ftBGA 256 COM LCMXO2280E-5FT256C 2280 1.2V 211 -5 ftBGA 256 COM LCMXO2280E-3FT324C 2280 1.2V 271 -3 ftBGA 324 COM LCMXO2280E-4FT324C 2280 1.2V 271 -4 ftBGA 324 COM LCMXO2280E-5FT324C 2280 1.2V 271 -5 ftBGA 324 COM Part Number 5-4 Ordering Information MachXO Family Data Sheet Conventional Packaging Industrial Part Number LUTs Supply Voltage I/Os Grade Package Pins Temp. LCMXO256C-3T100I 256 1.8V/2.5V/3.3V 78 -3 TQFP 100 IND LCMXO256C-4T100I 256 1.8V/2.5V/3.3V 78 -4 TQFP 100 IND LCMXO256C-3M100I 256 1.8V/2.5V/3.3V 78 -3 csBGA 100 IND LCMXO256C-4M100I 256 1.8V/2.5V/3.3V 78 -4 csBGA 100 IND LUTs Supply Voltage I/Os Grade Package Pins Temp. 640 1.8V/2.5V/3.3V 74 -3 TQFP 100 IND Part Number LCMXO640C-3T100I LCMXO640C-4T100I 640 1.8V/2.5V/3.3V 74 -4 TQFP 100 IND LCMXO640C-3M100I 640 1.8V/2.5V/3.3V 74 -3 csBGA 100 IND LCMXO640C-4M100I 640 1.8V/2.5V/3.3V 74 -4 csBGA 100 IND LCMXO640C-3T144I 640 1.8V/2.5V/3.3V 113 -3 TQFP 144 IND LCMXO640C-4T144I 640 1.8V/2.5V/3.3V 113 -4 TQFP 144 IND LCMXO640C-3M132I 640 1.8V/2.5V/3.3V 101 -3 csBGA 132 IND LCMXO640C-4M132I 640 1.8V/2.5V/3.3V 101 -4 csBGA 132 IND LCMXO640C-3B256I 640 1.8V/2.5V/3.3V 159 -3 caBGA 256 IND LCMXO640C-4B256I 640 1.8V/2.5V/3.3V 159 -4 caBGA 256 IND LCMXO640C-3FT256I 640 1.8V/2.5V/3.3V 159 -3 ftBGA 256 IND LCMXO640C-4FT256I 640 1.8V/2.5V/3.3V 159 -4 ftBGA 256 IND LUTs Supply Voltage I/Os Grade Package Pins Temp. LCMXO1200C-3T100I 1200 1.8V/2.5V/3.3V 73 -3 TQFP 100 IND LCMXO1200C-4T100I 1200 1.8V/2.5V/3.3V 73 -4 TQFP 100 IND LCMXO1200C-3T144I 1200 1.8V/2.5V/3.3V 113 -3 TQFP 144 IND LCMXO1200C-4T144I 1200 1.8V/2.5V/3.3V 113 -4 TQFP 144 IND LCMXO1200C-3M132I 1200 1.8V/2.5V/3.3V 101 -3 csBGA 132 IND LCMXO1200C-4M132I 1200 1.8V/2.5V/3.3V 101 -4 csBGA 132 IND LCMXO1200C-3B256I 1200 1.8V/2.5V/3.3V 211 -3 caBGA 256 IND LCMXO1200C-4B256I 1200 1.8V/2.5V/3.3V 211 -4 caBGA 256 IND LCMXO1200C-3FT256I 1200 1.8V/2.5V/3.3V 211 -3 ftBGA 256 IND LCMXO1200C-4FT256I 1200 1.8V/2.5V/3.3V 211 -4 ftBGA 256 IND LUTs Supply Voltage I/Os Grade Package Pins Temp. 2280 1.8V/2.5V/3.3V 73 -3 TQFP 100 IND Part Number Part Number LCMXO2280C-3T100I LCMXO2280C-4T100I 2280 1.8V/2.5V/3.3V 73 -4 TQFP 100 IND LCMXO2280C-3T144I 2280 1.8V/2.5V/3.3V 113 -3 TQFP 144 IND LCMXO2280C-4T144I 2280 1.8V/2.5V/3.3V 113 -4 TQFP 144 IND LCMXO2280C-3M132I 2280 1.8V/2.5V/3.3V 101 -3 csBGA 132 IND LCMXO2280C-4M132I 2280 1.8V/2.5V/3.3V 101 -4 csBGA 132 IND LCMXO2280C-3B256I 2280 1.8V/2.5V/3.3V 211 -3 caBGA 256 IND LCMXO2280C-4B256I 2280 1.8V/2.5V/3.3V 211 -4 caBGA 256 IND LCMXO2280C-3FT256I 2280 1.8V/2.5V/3.3V 211 -3 ftBGA 256 IND LCMXO2280C-4FT256I 2280 1.8V/2.5V/3.3V 211 -4 ftBGA 256 IND LCMXO2280C-3FT324I 2280 1.8V/2.5V/3.3V 271 -3 ftBGA 324 IND LCMXO2280C-4FT324I 2280 1.8V/2.5V/3.3V 271 -4 ftBGA 324 IND 5-5 Ordering Information MachXO Family Data Sheet LUTs Supply Voltage I/Os Grade Package Pins Temp. LCMXO256E-3T100I Part Number 256 1.2V 78 -3 TQFP 100 IND LCMXO256E-4T100I 256 1.2V 78 -4 TQFP 100 IND LCMXO256E-3M100I 256 1.2V 78 -3 csBGA 100 IND LCMXO256E-4M100I 256 1.2V 78 -4 csBGA 100 IND LUTs Supply Voltage I/Os Grade Package Pins Temp. LCMXO640E-3T100I 640 1.2V 74 -3 TQFP 100 IND LCMXO640E-4T100I 640 1.2V 74 -4 TQFP 100 IND LCMXO640E-3M100I 640 1.2V 74 -3 csBGA 100 IND LCMXO640E-4M100I 640 1.2V 74 -4 csBGA 100 IND LCMXO640E-3T144I 640 1.2V 113 -3 TQFP 144 IND LCMXO640E-4T144I 640 1.2V 113 -4 TQFP 144 IND LCMXO640E-3M132I 640 1.2V 101 -3 csBGA 132 IND LCMXO640E-4M132I 640 1.2V 101 -4 csBGA 132 IND LCMXO640E-3B256I 640 1.2V 159 -3 caBGA 256 IND LCMXO640E-4B256I 640 1.2V 159 -4 caBGA 256 IND LCMXO640E-3FT256I 640 1.2V 159 -3 ftBGA 256 IND LCMXO640E-4FT256I 640 1.2V 159 -4 ftBGA 256 IND Part Number LUTs Supply Voltage I/Os Grade Package Pins Temp. LCMXO1200E-3T100I Part Number 1200 1.2V 73 -3 TQFP 100 IND LCMXO1200E-4T100I 1200 1.2V 73 -4 TQFP 100 IND LCMXO1200E-3T144I 1200 1.2V 113 -3 TQFP 144 IND LCMXO1200E-4T144I 1200 1.2V 113 -4 TQFP 144 IND LCMXO1200E-3M132I 1200 1.2V 101 -3 csBGA 132 IND LCMXO1200E-4M132I 1200 1.2V 101 -4 csBGA 132 IND LCMXO1200E-3B256I 1200 1.2V 211 -3 caBGA 256 IND LCMXO1200E-4B256I 1200 1.2V 211 -4 caBGA 256 IND LCMXO1200E-3FT256I 1200 1.2V 211 -3 ftBGA 256 IND LCMXO1200E-4FT256I 1200 1.2V 211 -4 ftBGA 256 IND LUTs Supply Voltage I/Os Grade Package Pins Temp. LCMXO2280E-3T100I 2280 1.2V 73 -3 TQFP 100 IND LCMXO2280E-4T100I 2280 1.2V 73 -4 TQFP 100 IND LCMXO2280E-3T144I 2280 1.2V 113 -3 TQFP 144 IND LCMXO2280E-4T144I 2280 1.2V 113 -4 TQFP 144 IND LCMXO2280E-3M132I 2280 1.2V 101 -3 csBGA 132 IND LCMXO2280E-4M132I 2280 1.2V 101 -4 csBGA 132 IND LCMXO2280E-3B256I 2280 1.2V 211 -3 caBGA 256 IND LCMXO2280E-4B256I 2280 1.2V 211 -4 caBGA 256 IND LCMXO2280E-3FT256I 2280 1.2V 211 -3 ftBGA 256 IND LCMXO2280E-4FT256I 2280 1.2V 211 -4 ftBGA 256 IND LCMXO2280E-3FT324I 2280 1.2V 271 -3 ftBGA 324 IND LCMXO2280E-4FT324I 2280 1.2V 271 -4 ftBGA 324 IND Part Number 5-6 Ordering Information MachXO Family Data Sheet Lead-Free Packaging Commercial Part Number LUTs Supply Voltage I/Os Grade Package Pins Temp. LCMXO256C-3TN100C 256 1.8V/2.5V/3.3V 78 -3 Lead-Free TQFP 100 COM LCMXO256C-4TN100C 256 1.8V/2.5V/3.3V 78 -4 Lead-Free TQFP 100 COM LCMXO256C-5TN100C 256 1.8V/2.5V/3.3V 78 -5 Lead-Free TQFP 100 COM LCMXO256C-3MN100C 256 1.8V/2.5V/3.3V 78 -3 Lead-Free csBGA 100 COM LCMXO256C-4MN100C 256 1.8V/2.5V/3.3V 78 -4 Lead-Free csBGA 100 COM LCMXO256C-5MN100C 256 1.8V/2.5V/3.3V 78 -5 Lead-Free csBGA 100 COM LUTs Supply Voltage I/Os Grade Package Pins Temp. LCMXO640C-3TN100C Part Number 640 1.8V/2.5V/3.3V 74 -3 Lead-Free TQFP 100 COM LCMXO640C-4TN100C 640 1.8V/2.5V/3.3V 74 -4 Lead-Free TQFP 100 COM LCMXO640C-5TN100C 640 1.8V/2.5V/3.3V 74 -5 Lead-Free TQFP 100 COM LCMXO640C-3MN100C 640 1.8V/2.5V/3.3V 74 -3 Lead-Free csBGA 100 COM LCMXO640C-4MN100C 640 1.8V/2.5V/3.3V 74 -4 Lead-Free csBGA 100 COM LCMXO640C-5MN100C 640 1.8V/2.5V/3.3V 74 -5 Lead-Free csBGA 100 COM LCMXO640C-3TN144C 640 1.8V/2.5V/3.3V 113 -3 Lead-Free TQFP 144 COM LCMXO640C-4TN144C 640 1.8V/2.5V/3.3V 113 -4 Lead-Free TQFP 144 COM LCMXO640C-5TN144C 640 1.8V/2.5V/3.3V 113 -5 Lead-Free TQFP 144 COM LCMXO640C-3MN132C 640 1.8V/2.5V/3.3V 101 -3 Lead-Free csBGA 132 COM LCMXO640C-4MN132C 640 1.8V/2.5V/3.3V 101 -4 Lead-Free csBGA 132 COM LCMXO640C-5MN132C 640 1.8V/2.5V/3.3V 101 -5 Lead-Free csBGA 132 COM LCMXO640C-3BN256C 640 1.8V/2.5V/3.3V 159 -3 Lead-Free caBGA 256 COM LCMXO640C-4BN256C 640 1.8V/2.5V/3.3V 159 -4 Lead-Free caBGA 256 COM LCMXO640C-5BN256C 640 1.8V/2.5V/3.3V 159 -5 Lead-Free caBGA 256 COM LCMXO640C-3FTN256C 640 1.8V/2.5V/3.3V 159 -3 Lead-Free ftBGA 256 COM LCMXO640C-4FTN256C 640 1.8V/2.5V/3.3V 159 -4 Lead-Free ftBGA 256 COM LCMXO640C-5FTN256C 640 1.8V/2.5V/3.3V 159 -5 Lead-Free ftBGA 256 COM LUTs Supply Voltage I/Os Grade Package Pins Temp. LCMXO1200C-3TN100C 1200 1.8V/2.5V/3.3V 73 -3 Lead-Free TQFP 100 COM LCMXO1200C-4TN100C 1200 1.8V/2.5V/3.3V 73 -4 Lead-Free TQFP 100 COM LCMXO1200C-5TN100C 1200 1.8V/2.5V/3.3V 73 -5 Lead-Free TQFP 100 COM LCMXO1200C-3TN144C 1200 1.8V/2.5V/3.3V 113 -3 Lead-Free TQFP 144 COM LCMXO1200C-4TN144C 1200 1.8V/2.5V/3.3V 113 -4 Lead-Free TQFP 144 COM LCMXO1200C-5TN144C 1200 1.8V/2.5V/3.3V 113 -5 Lead-Free TQFP 144 COM LCMXO1200C-3MN132C 1200 1.8V/2.5V/3.3V 101 -3 Lead-Free csBGA 132 COM LCMXO1200C-4MN132C 1200 1.8V/2.5V/3.3V 101 -4 Lead-Free csBGA 132 COM LCMXO1200C-5MN132C 1200 1.8V/2.5V/3.3V 101 -5 Lead-Free csBGA 132 COM LCMXO1200C-3BN256C 1200 1.8V/2.5V/3.3V 211 -3 Lead-Free caBGA 256 COM LCMXO1200C-4BN256C 1200 1.8V/2.5V/3.3V 211 -4 Lead-Free caBGA 256 COM LCMXO1200C-5BN256C 1200 1.8V/2.5V/3.3V 211 -5 Lead-Free caBGA 256 COM LCMXO1200C-3FTN256C 1200 1.8V/2.5V/3.3V 211 -3 Lead-Free ftBGA 256 COM LCMXO1200C-4FTN256C 1200 1.8V/2.5V/3.3V 211 -4 Lead-Free ftBGA 256 COM LCMXO1200C-5FTN256C 1200 1.8V/2.5V/3.3V 211 -5 Lead-Free ftBGA 256 COM Part Number 5-7 Ordering Information MachXO Family Data Sheet LUTs Supply Voltage I/Os Grade Package Pins Temp. LCMXO2280C-3TN100C Part Number 2280 1.8V/2.5V/3.3V 73 -3 Lead-Free TQFP 100 COM LCMXO2280C-4TN100C 2280 1.8V/2.5V/3.3V 73 -4 Lead-Free TQFP 100 COM LCMXO2280C-5TN100C 2280 1.8V/2.5V/3.3V 73 -5 Lead-Free TQFP 100 COM LCMXO2280C-3TN144C 2280 1.8V/2.5V/3.3V 113 -3 Lead-Free TQFP 144 COM LCMXO2280C-4TN144C 2280 1.8V/2.5V/3.3V 113 -4 Lead-Free TQFP 144 COM LCMXO2280C-5TN144C 2280 1.8V/2.5V/3.3V 113 -5 Lead-Free TQFP 144 COM LCMXO2280C-3MN132C 2280 1.8V/2.5V/3.3V 101 -3 Lead-Free csBGA 132 COM LCMXO2280C-4MN132C 2280 1.8V/2.5V/3.3V 101 -4 Lead-Free csBGA 132 COM LCMXO2280C-5MN132C 2280 1.8V/2.5V/3.3V 101 -5 Lead-Free csBGA 132 COM LCMXO2280C-3BN256C 2280 1.8V/2.5V/3.3V 211 -3 Lead-Free caBGA 256 COM LCMXO2280C-4BN256C 2280 1.8V/2.5V/3.3V 211 -4 Lead-Free caBGA 256 COM LCMXO2280C-5BN256C 2280 1.8V/2.5V/3.3V 211 -5 Lead-Free caBGA 256 COM LCMXO2280C-3FTN256C 2280 1.8V/2.5V/3.3V 211 -3 Lead-Free ftBGA 256 COM LCMXO2280C-4FTN256C 2280 1.8V/2.5V/3.3V 211 -4 Lead-Free ftBGA 256 COM LCMXO2280C-5FTN256C 2280 1.8V/2.5V/3.3V 211 -5 Lead-Free ftBGA 256 COM LCMXO2280C-3FTN324C 2280 1.8V/2.5V/3.3V 271 -3 Lead-Free ftBGA 324 COM LCMXO2280C-4FTN324C 2280 1.8V/2.5V/3.3V 271 -4 Lead-Free ftBGA 324 COM LCMXO2280C-5FTN324C 2280 1.8V/2.5V/3.3V 271 -5 Lead-Free ftBGA 324 COM Part Number LUTs Supply Voltage I/Os Grade Package Pins Temp. LCMXO256E-3TN100C 256 1.2V 78 -3 Lead-Free TQFP 100 COM LCMXO256E-4TN100C 256 1.2V 78 -4 Lead-Free TQFP 100 COM LCMXO256E-5TN100C 256 1.2V 78 -5 Lead-Free TQFP 100 COM LCMXO256E-3MN100C 256 1.2V 78 -3 Lead-Free csBGA 100 COM LCMXO256E-4MN100C 256 1.2V 78 -4 Lead-Free csBGA 100 COM LCMXO256E-5MN100C 256 1.2V 78 -5 Lead-Free csBGA 100 COM LUTs Supply Voltage I/Os Grade Package Pins Temp. LCMXO640E-3TN100C Part Number 640 1.2V 74 -3 Lead-Free TQFP 100 COM LCMXO640E-4TN100C 640 1.2V 74 -4 Lead-Free TQFP 100 COM LCMXO640E-5TN100C 640 1.2V 74 -5 Lead-Free TQFP 100 COM LCMXO640E-3MN100C 640 1.2V 74 -3 Lead-Free csBGA 100 COM LCMXO640E-4MN100C 640 1.2V 74 -4 Lead-Free csBGA 100 COM LCMXO640E-5MN100C 640 1.2V 74 -5 Lead-Free csBGA 100 COM LCMXO640E-3TN144C 640 1.2V 113 -3 Lead-Free TQFP 144 COM LCMXO640E-4TN144C 640 1.2V 113 -4 Lead-Free TQFP 144 COM LCMXO640E-5TN144C 640 1.2V 113 -5 Lead-Free TQFP 144 COM LCMXO640E-3MN132C 640 1.2V 101 -3 Lead-Free csBGA 132 COM LCMXO640E-4MN132C 640 1.2V 101 -4 Lead-Free csBGA 132 COM LCMXO640E-5MN132C 640 1.2V 101 -5 Lead-Free csBGA 132 COM LCMXO640E-3BN256C 640 1.2V 159 -3 Lead-Free caBGA 256 COM LCMXO640E-4BN256C 640 1.2V 159 -4 Lead-Free caBGA 256 COM LCMXO640E-5BN256C 640 1.2V 159 -5 Lead-Free caBGA 256 COM LCMXO640E-3FTN256C 640 1.2V 159 -3 Lead-Free ftBGA 256 COM LCMXO640E-4FTN256C 640 1.2V 159 -4 Lead-Free ftBGA 256 COM LCMXO640E-5FTN256C 640 1.2V 159 -5 Lead-Free ftBGA 256 COM 5-8 Ordering Information MachXO Family Data Sheet LUTs Supply Voltage I/Os Grade Package Pins Temp. LCMXO1200E-3TN100C Part Number 1200 1.2V 73 -3 Lead-Free TQFP 100 COM LCMXO1200E-4TN100C 1200 1.2V 73 -4 Lead-Free TQFP 100 COM LCMXO1200E-5TN100C 1200 1.2V 73 -5 Lead-Free TQFP 100 COM LCMXO1200E-3TN144C 1200 1.2V 113 -3 Lead-Free TQFP 144 COM LCMXO1200E-4TN144C 1200 1.2V 113 -4 Lead-Free TQFP 144 COM LCMXO1200E-5TN144C 1200 1.2V 113 -5 Lead-Free TQFP 144 COM LCMXO1200E-3MN132C 1200 1.2V 101 -3 Lead-Free csBGA 132 COM LCMXO1200E-4MN132C 1200 1.2V 101 -4 Lead-Free csBGA 132 COM LCMXO1200E-5MN132C 1200 1.2V 101 -5 Lead-Free csBGA 132 COM LCMXO1200E-3BN256C 1200 1.2V 211 -3 Lead-Free caBGA 256 COM LCMXO1200E-4BN256C 1200 1.2V 211 -4 Lead-Free caBGA 256 COM LCMXO1200E-5BN256C 1200 1.2V 211 -5 Lead-Free caBGA 256 COM LCMXO1200E-3FTN256C 1200 1.2V 211 -3 Lead-Free ftBGA 256 COM LCMXO1200E-4FTN256C 1200 1.2V 211 -4 Lead-Free ftBGA 256 COM LCMXO1200E-5FTN256C 1200 1.2V 211 -5 Lead-Free ftBGA 256 COM Part Number LUTs Supply Voltage I/Os Grade Package Pins Temp. LCMXO2280E-3TN100C 2280 1.2V 73 -3 Lead-Free TQFP 100 COM LCMXO2280E-4TN100C 2280 1.2V 73 -4 Lead-Free TQFP 100 COM LCMXO2280E-5TN100C 2280 1.2V 73 -5 Lead-Free TQFP 100 COM LCMXO2280E-3TN144C 2280 1.2V 113 -3 Lead-Free TQFP 144 COM LCMXO2280E-4TN144C 2280 1.2V 113 -4 Lead-Free TQFP 144 COM LCMXO2280E-5TN144C 2280 1.2V 113 -5 Lead-Free TQFP 144 COM LCMXO2280E-3MN132C 2280 1.2V 101 -3 Lead-Free csBGA 132 COM LCMXO2280E-4MN132C 2280 1.2V 101 -4 Lead-Free csBGA 132 COM LCMXO2280E-5MN132C 2280 1.2V 101 -5 Lead-Free csBGA 132 COM LCMXO2280E-3BN256C 2280 1.2V 211 -3 Lead-Free caBGA 256 COM LCMXO2280E-4BN256C 2280 1.2V 211 -4 Lead-Free caBGA 256 COM LCMXO2280E-5BN256C 2280 1.2V 211 -5 Lead-Free caBGA 256 COM LCMXO2280E-3FTN256C 2280 1.2V 211 -3 Lead-Free ftBGA 256 COM LCMXO2280E-4FTN256C 2280 1.2V 211 -4 Lead-Free ftBGA 256 COM LCMXO2280E-5FTN256C 2280 1.2V 211 -5 Lead-Free ftBGA 256 COM LCMXO2280E-3FTN324C 2280 1.2V 271 -3 Lead-Free ftBGA 324 COM LCMXO2280E-4FTN324C 2280 1.2V 271 -4 Lead-Free ftBGA 324 COM LCMXO2280E-5FTN324C 2280 1.2V 271 -5 Lead-Free ftBGA 324 COM 5-9 Ordering Information MachXO Family Data Sheet Lead-Free Packaging Industrial Part Number LUTs Supply Voltage I/Os Grade Package Pins Temp. LCMXO256C-3TN100I 256 1.8V/2.5V/3.3V 78 -3 Lead-Free TQFP 100 IND LCMXO256C-4TN100I 256 1.8V/2.5V/3.3V 78 -4 Lead-Free TQFP 100 IND LCMXO256C-3MN100I 256 1.8V/2.5V/3.3V 78 -3 Lead-Free csBGA 100 IND LCMXO256C-4MN100I 256 1.8V/2.5V/3.3V 78 -4 Lead-Free csBGA 100 IND LUTs Supply Voltage I/Os Grade Package Pins Temp. 640 1.8V/2.5V/3.3V 74 -3 Lead-Free TQFP 100 IND Part Number LCMXO640C-3TN100I LCMXO640C-4TN100I 640 1.8V/2.5V/3.3V 74 -4 Lead-Free TQFP 100 IND LCMXO640C-3MN100I 640 1.8V/2.5V/3.3V 74 -3 Lead-Free csBGA 100 IND LCMXO640C-4MN100I 640 1.8V/2.5V/3.3V 74 -4 Lead-Free csBGA 100 IND LCMXO640C-3TN144I 640 1.8V/2.5V/3.3V 113 -3 Lead-Free TQFP 144 IND LCMXO640C-4TN144I 640 1.8V/2.5V/3.3V 113 -4 Lead-Free TQFP 144 IND LCMXO640C-3MN132I 640 1.8V/2.5V/3.3V 101 -3 Lead-Free csBGA 132 IND LCMXO640C-4MN132I 640 1.8V/2.5V/3.3V 101 -4 Lead-Free csBGA 132 IND LCMXO640C-3BN256I 640 1.8V/2.5V/3.3V 159 -3 Lead-Free caBGA 256 IND LCMXO640C-4BN256I 640 1.8V/2.5V/3.3V 159 -4 Lead-Free caBGA 256 IND LCMXO640C-3FTN256I 640 1.8V/2.5V/3.3V 159 -3 Lead-Free ftBGA 256 IND LCMXO640C-4FTN256I 640 1.8V/2.5V/3.3V 159 -4 Lead-Free ftBGA 256 IND LUTs Supply Voltage I/Os Grade Package Pins Temp. LCMXO1200C-3TN100I 1200 1.8V/2.5V/3.3V 73 -3 Lead-Free TQFP 100 IND LCMXO1200C-4TN100I 1200 1.8V/2.5V/3.3V 73 -4 Lead-Free TQFP 100 IND LCMXO1200C-3TN144I 1200 1.8V/2.5V/3.3V 113 -3 Lead-Free TQFP 144 IND LCMXO1200C-4TN144I 1200 1.8V/2.5V/3.3V 113 -4 Lead-Free TQFP 144 IND LCMXO1200C-3MN132I 1200 1.8V/2.5V/3.3V 101 -3 Lead-Free csBGA 132 IND LCMXO1200C-4MN132I 1200 1.8V/2.5V/3.3V 101 -4 Lead-Free csBGA 132 IND LCMXO1200C-3BN256I 1200 1.8V/2.5V/3.3V 211 -3 Lead-Free caBGA 256 IND LCMXO1200C-4BN256I 1200 1.8V/2.5V/3.3V 211 -4 Lead-Free caBGA 256 IND LCMXO1200C-3FTN256I 1200 1.8V/2.5V/3.3V 211 -3 Lead-Free ftBGA 256 IND LCMXO1200C-4FTN256I 1200 1.8V/2.5V/3.3V 211 -4 Lead-Free ftBGA 256 IND Part Number LUTs Supply Voltage I/Os Grade Package Pins Temp. LCMXO2280C-3TN100I Part Number 2280 1.8V/2.5V/3.3V 73 -3 Lead-Free TQFP 100 IND LCMXO2280C-4TN100I 2280 1.8V/2.5V/3.3V 73 -4 Lead-Free TQFP 100 IND LCMXO2280C-3TN144I 2280 1.8V/2.5V/3.3V 113 -3 Lead-Free TQFP 144 IND LCMXO2280C-4TN144I 2280 1.8V/2.5V/3.3V 113 -4 Lead-Free TQFP 144 IND LCMXO2280C-3MN132I 2280 1.8V/2.5V/3.3V 101 -3 Lead-Free csBGA 132 IND LCMXO2280C-4MN132I 2280 1.8V/2.5V/3.3V 101 -4 Lead-Free csBGA 132 IND LCMXO2280C-3BN256I 2280 1.8V/2.5V/3.3V 211 -3 Lead-Free caBGA 256 IND LCMXO2280C-4BN256I 2280 1.8V/2.5V/3.3V 211 -4 Lead-Free caBGA 256 IND LCMXO2280C-3FTN256I 2280 1.8V/2.5V/3.3V 211 -3 Lead-Free ftBGA 256 IND LCMXO2280C-4FTN256I 2280 1.8V/2.5V/3.3V 211 -4 Lead-Free ftBGA 256 IND LCMXO2280C-3FTN324I 2280 1.8V/2.5V/3.3V 271 -3 Lead-Free ftBGA 324 IND LCMXO2280C-4FTN324I 2280 1.8V/2.5V/3.3V 271 -4 Lead-Free ftBGA 324 IND 5-10 Ordering Information MachXO Family Data Sheet LUTs Supply Voltage I/Os Grade LCMXO256E-3TN100I Part Number 256 1.2V 78 -3 Lead-Free TQFP LCMXO256E-4TN100I 256 1.2V 78 -4 Lead-Free TQFP 100 IND LCMXO256E-3MN100I 256 1.2V 78 -3 Lead-Free csBGA 100 IND LCMXO256E-4MN100I 256 1.2V 78 -4 Lead-Free csBGA 100 IND LUTs Supply Voltage I/Os Grade Package Pins Temp. LCMXO640E-3TN100I 640 1.2V 74 -3 Lead-Free TQFP 100 IND LCMXO640E-4TN100I 640 1.2V 74 -4 Lead-Free TQFP 100 IND LCMXO640E-3MN100I 640 1.2V 74 -3 Lead-Free csBGA 100 IND LCMXO640E-4MN100I 640 1.2V 74 -4 Lead-Free csBGA 100 IND LCMXO640E-3TN144I 640 1.2V 113 -3 Lead-Free TQFP 144 IND LCMXO640E-4TN144I 640 1.2V 113 -4 Lead-Free TQFP 144 IND LCMXO640E-3MN132I 640 1.2V 101 -3 Lead-Free csBGA 132 IND LCMXO640E-4MN132I 640 1.2V 101 -4 Lead-Free csBGA 132 IND LCMXO640E-3BN256I 640 1.2V 159 -3 Lead-Free caBGA 256 IND LCMXO640E-4BN256I 640 1.2V 159 -4 Lead-Free caBGA 256 IND LCMXO640E-3FTN256I 640 1.2V 159 -3 Lead-Free ftBGA 256 IND LCMXO640E-4FTN256I 640 1.2V 159 -4 Lead-Free ftBGA 256 IND Package Part Number Part Number Package Pins Temp. 100 IND LUTs Supply Voltage I/Os Grade Pins Temp. LCMXO1200E-3TN100I 1200 1.2V 73 -3 Lead-Free TQFP 100 IND LCMXO1200E-4TN100I 1200 1.2V 73 -4 Lead-Free TQFP 100 IND LCMXO1200E-3TN144I 1200 1.2V 113 -3 Lead-Free TQFP 144 IND LCMXO1200E-4TN144I 1200 1.2V 113 -4 Lead-Free TQFP 144 IND LCMXO1200E-3MN132I 1200 1.2V 101 -3 Lead-Free csBGA 132 IND LCMXO1200E-4MN132I 1200 1.2V 101 -4 Lead-Free csBGA 132 IND LCMXO1200E-3BN256I 1200 1.2V 211 -3 Lead-Free caBGA 256 IND LCMXO1200E-4BN256I 1200 1.2V 211 -4 Lead-Free caBGA 256 IND LCMXO1200E-3FTN256I 1200 1.2V 211 -3 Lead-Free ftBGA 256 IND LCMXO1200E-4FTN256I 1200 1.2V 211 -4 Lead-Free ftBGA 256 IND LUTs Supply Voltage I/Os Grade Package Pins Temp. LCMXO2280E-3TN100I 2280 1.2V 73 -3 Lead-Free TQFP 100 IND LCMXO2280E-4TN100I 2280 1.2V 73 -4 Lead-Free TQFP 100 IND LCMXO2280E-3TN144I 2280 1.2V 113 -3 Lead-Free TQFP 144 IND LCMXO2280E-4TN144I 2280 1.2V 113 -4 Lead-Free TQFP 144 IND LCMXO2280E-3MN132I 2280 1.2V 101 -3 Lead-Free csBGA 132 IND LCMXO2280E-4MN132I 2280 1.2V 101 -4 Lead-Free csBGA 132 IND LCMXO2280E-3BN256I 2280 1.2V 211 -3 Lead-Free caBGA 256 IND LCMXO2280E-4BN256I 2280 1.2V 211 -4 Lead-Free caBGA 256 IND LCMXO2280E-3FTN256I 2280 1.2V 211 -3 Lead-Free ftBGA 256 IND LCMXO2280E-4FTN256I 2280 1.2V 211 -4 Lead-Free ftBGA 256 IND LCMXO2280E-3FTN324I 2280 1.2V 271 -3 Lead-Free ftBGA 324 IND LCMXO2280E-4FTN324I 2280 1.2V 271 -4 Lead-Free ftBGA 324 IND Part Number 5-11 MachXO Family Data Sheet Supplemental Information June 2013 Data Sheet DS1002 For Further Information A variety of technical notes for the MachXO family are available on the Lattice web site. • TN1091, MachXO sysIO Usage Guide • TN1089, MachXO sysCLOCK Design and Usage Guide • TN1092, Memory Usage Guide for MachXO Devices • TN1090, Power Estimation and Management for MachXO Devices • TN1086, MachXO JTAG Programming and Configuration User’s Guide • TN1087, Minimizing System Interruption During Configuration Using TransFR Technology • TN1097, MachXO Density Migration • AN8066, Boundary Scan Testability with Lattice sysIO Capability For further information on interface standards refer to the following web sites: • JEDEC Standards (LVTTL, LVCMOS): www.jedec.org • PCI: www.pcisig.com © 2013 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 6-1 DS1002 Further Information_01.3 MachXO Family Data Sheet Revision History June 2013 Data Sheet DS1002 Revision History Date Version Section February 2005 01.0 — Change Summary October 2005 01.1 Introduction Distributed RAM information in family table updated. Added footnote 1 fpBGA packaging to the family selection guide. Architecture sysIO Buffer section updated. Initial release. Hot Socketing section updated. Sleep Mode section updated. SLEEP Pin Characteristics section updated. Oscillator section updated. Security section updated. DC and Switching Characteristics Recommended Operating Conditions table updated. DC Electrical Characteristics table updated. Supply Current (Sleep Mode) table added with LCMXO256/640 data. Supply Current (Standby) table updated with LCMXO256/640 data. Initialization Supply Current table updated with LCMXO256/640 data. Programming and Erase Flash Supply Current table updated with LCMXO256/640 data. Register-to-Register Performance table updated (rev. A 0.16). External Switching Characteristics table updated (rev. A 0.16). Internal Timing Parameter table updated (rev. A 0.16). Family Timing Adders updated (rev. A 0.16). sysCLOCK Timingupdated (rev. A 0.16). MachXO "C" Sleep Mode Timing updated (A 0.16). JTAG Port Timing Specification updated (rev. A 0.16). Pinout Information SLEEPIN description updated. Pin Information Summary updated. Power Supply and NC Connection table has been updated. Logic Signal Connection section has been updated to include all devices/packages. Ordering Information Part Number Description section has been updated. Ordering Part Number section has been updated (added LCMXO256C/ LCMXO640C "4W"). Supplemental Information MachXO Density Migration Technical Note (TN1097) added. November 2005 01.2 Pinout Information Added “Power Supply and NC Connections” summary information for LCMXO1200 and LCMXO2280 in 100 TQFP package. December 2005 01.3 DC and Switching Characteristics Supply Current (Standby) table updated with LCMXO1200/2280 data. Ordering Information Ordering Part Number section updated (added LCMXO2280C "4W"). April 2006 02.0 Introduction Introduction paragraphs updated. Architecture Architecture Overview paragraphs updated. © 2013 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 7-1 Revision History MachXO Family Data Sheet Date Version Section April 2006 (cont.) 02.0 (cont.) Architecture (cont.) Change Summary “Top View of the MachXO1200 Device” figure updated. “Top View of the MachXO640 Device” figure updated. “Top View of the MachXO256 Device” figure updated. “Slice Diagram” figure updated. Slice Signal Descriptions table updated. Routing section updated. sysCLOCK Phase Lockecd Loops (PLLs) section updated. PLL Diagram updated. PLL Signal Descriptions table updated. sysMEM Memory section has been updated. PIO Groups section has been updated. PIO section has been updated. MachXO PIO Block Diagram updated. Supported Input Standards table updated. MachXO Configuration and Programming diagram updated. DC and Switching Characteristics Recommended Operating Conditions table - footnotes updated. MachXO256 and MachXO640 Hot Socketing Specifications - footnotes updated. Added MachXO1200 and MachXO2280 Hot Socketing Specifications table. DC Electrical Characteristics, footnotes have been updated. Supply Current (Sleep Mode) table has been updated, removed "4W" references. Footnotes have been updated. Supply Current (Standby) table and associated footnotes updated. Intialization Supply Current table and footnotes updated. Programming and Erase Flash Supply Current table and associated footnotes have been updatd. Register-to-Register Performance table updated (rev. A 0.19). MachXO External Switching Characteristics updated (rev. A 0.19). MachXO Internal Timing Parameters updated (rev. A 0.19). MachXO Family Timing Adders updated (rev. A 0.19). sysCLOCK Timing updated (rev. A 0.19). MachXO "C" Sleep Mode Timing updated (A 0.19). JTAG Port Timing Specification updated (rev. A 0.19). Test Fixture Required Components table updated. Pinout Information Signal Descriptions have been updated. Pin Information Summary has been updated. Footnote has been added. Power Supply and NC Connection table has been updated. Logic Signal Connections have been updated (PCLKTx_x --> PCLKx_x) Ordering Information Removed "4W" references. Added 256-ftBGA Ordering Part Numbers for MachXO640. May 2006 02.1 Pinout Information Removed [LOC][0]_PLL_RST from Signal Description table. PCLK footnote has been added to all appropriate pins. August 2006 02.2 Multiple Removed 256 fpBGA information for MachXO640. 7-2 Revision History MachXO Family Data Sheet Date Version Section November 2006 02.3 DC and Switching Characteristics Change Summary December 2006 02.4 Architecture February 2007 02.5 Architecture August 2007 02.6 DC and Switching Characteristics Updated sysIO Single-Ended DC Electrical Characteristics table. November 2007 02.7 DC and Switching Characteristics Added JTAG Port Timing Waveforms diagram. Pinout Information Added Thermal Management text section. Corrections to MachXO “C” Sleep Mode Timing table - value for tWSLEEPN (400ns) changed from max. to min. Value for tWAWAKE (100ns) changed from min. to max. Added Flash Download Time table. Pinout Information Supplemental Information June 2009 02.8 Introduction Pinout Information Ordering Information July 2010 02.9 June 2013 03.0 DC and Switching Characteristics All Architecture DC and Switching Characteristics EBR Asynchronous Reset section added. Power Supply and NC table: Pin/Ball orientation footnotes added. Updated EBR Asynchronous Reset section. Updated title list. Added 0.8-mm 256-pin caBGA package to MachXO Family Selection Guide table. Added Logic Signal Connections table for 0.8-mm 256-pin caBGA package. Updated Part Number Description diagram and Ordering Part Number tables with 0.8-mm 256-pin caBGA package information. Updated sysCLOCK PLL Timing table. Updated document with new corporate logo. Architecture Overview – Added information on the state of the register on power up and after configuration. MachXO1200 and MachXO2280 Hot Socketing Specifications table – Removed footnote 4. Added MachXO Programming/Erase Specifications table. 7-3