LCMXO3D-9400HC-6BG256I

MachXO3D Device Family Data Sheet FPGA-DS-02026-1.1 September 2020 MachXO3D Device Family Data Sheet Disclaimers Lattice makes no warranty, representation, or guarantee regarding the accuracy of information contained in this document or the suitability of its products for any particular purpose. All information herein is provided AS IS and with all faults, and all risk associated with such information is entirely with Buyer. Buyer shall not rely on any data and performance specifications or parameters provided herein. Products sold by Lattice have been subject to limited testing and it is the Buyer's responsibility to independently determine the suitability of any products and to test and verify the same. No Lattice products should be used in conjunction with mission- or safety-critical or any other application in which the failure of Lattice’s product could create a situation where personal injury, death, severe property or environmental damage may occur. The information provided in this document is proprietary to Lattice Semiconductor, and Lattice reserves the right to make any changes to the information in this document or to any products at any time without notice. © 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 2 FPGA-DS-02026-1.1 MachXO3D Device Family Data Sheet Contents Acronyms in This Document ................................................................................................................................................. 7 1. Introduction .................................................................................................................................................................. 8 1.1. Features .............................................................................................................................................................. 9 1.1.1. Solutions ......................................................................................................................................................... 9 1.1.2. Flexible Architecture ....................................................................................................................................... 9 1.1.3. Dedicated Embedded Security Block .............................................................................................................. 9 1.1.4. Pre-Engineered Source Synchronous I/O........................................................................................................ 9 1.1.5. High Performance, Flexible I/O Buffer ............................................................................................................ 9 1.1.6. Flexible On-Chip Clocking ............................................................................................................................... 9 1.1.7. Non-volatile, Reconfigurable .......................................................................................................................... 9 1.1.8. TransFR Reconfiguration............................................................................................................................... 10 1.1.9. Enhanced System Level Support ................................................................................................................... 10 1.1.10. Advanced Packaging ................................................................................................................................. 10 1.1.11. Applications .............................................................................................................................................. 10 2. Architecture ................................................................................................................................................................ 12 2.1. Architecture Overview ...................................................................................................................................... 12 2.2. PFU Blocks ......................................................................................................................................................... 13 2.2.1. Slices ............................................................................................................................................................. 13 2.2.2. Modes of Operation...................................................................................................................................... 15 2.2.3. RAM Mode .................................................................................................................................................... 16 2.2.4. ROM Mode.................................................................................................................................................... 16 2.3. Routing .............................................................................................................................................................. 16 2.4. Clock/Control Distribution Network .................................................................................................................. 16 2.4.1. sysCLOCK Phase Locked Loops (PLLs) ........................................................................................................... 18 2.5. sysMEM Embedded Block RAM Memory.......................................................................................................... 21 2.5.1. sysMEM Memory Block ................................................................................................................................ 21 2.5.2. Bus Size Matching ......................................................................................................................................... 21 2.5.3. RAM Initialization and ROM Operation ........................................................................................................ 21 2.5.4. Memory Cascading ....................................................................................................................................... 21 2.5.5. Single, Dual, Pseudo-Dual Port and FIFO Modes .......................................................................................... 22 2.5.6. FIFO Configuration ........................................................................................................................................ 23 2.5.7. Memory Core Reset ...................................................................................................................................... 24 2.5.8. EBR Asynchronous Reset .............................................................................................................................. 24 2.6. Programmable I/O Cells (PIC) ............................................................................................................................ 25 2.7. PIO ..................................................................................................................................................................... 27 2.7.1. Input Register Block ...................................................................................................................................... 27 2.7.2. Output Register Block ................................................................................................................................... 27 2.7.3. Tri-state Register Block ................................................................................................................................. 28 2.8. Input Gearbox ................................................................................................................................................... 28 2.9. Output Gearbox ................................................................................................................................................ 30 2.10. sysI/O Buffer...................................................................................................................................................... 32 2.10.1. Typical I/O Behavior during Power-up ..................................................................................................... 32 2.10.2. Supported Standards ................................................................................................................................ 32 2.10.3. sysI/O Buffer Banks .................................................................................................................................. 35 2.11. Hot Socketing .................................................................................................................................................... 35 2.12. On-chip Oscillator.............................................................................................................................................. 35 2.13. Embedded Hardened IP Functions .................................................................................................................... 36 2.13.1. Embedded Security Block (ESB) IP Core ................................................................................................... 37 2.13.2. Hardened I2C IP Core ................................................................................................................................ 38 2.13.3. Hardened SPI IP Core................................................................................................................................ 39 2.13.4. Hardened Timer/Counter ......................................................................................................................... 41 2.14. User Flash Memory (UFM) ................................................................................................................................ 42 © 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02026-1.1 3 MachXO3D Device Family Data Sheet 2.15. Standby Mode and Power Saving Options ........................................................................................................42 2.16. Power-On-Reset ................................................................................................................................................43 2.17. Configuration and Testing .................................................................................................................................44 2.17.1. IEEE 1149.1-Compliant Boundary Scan Testability ...................................................................................44 2.17.2. Device Configuration ................................................................................................................................44 2.18. TraceID ..............................................................................................................................................................46 2.19. Density Shifting .................................................................................................................................................46 3. DC and Switching Characteristics................................................................................................................................47 3.1. Absolute Maximum Rating ................................................................................................................................47 3.2. Recommended Operating Conditions ...............................................................................................................47 3.3. Power Supply Ramp Rates.................................................................................................................................47 3.4. Power-On-Reset Voltage Levels ........................................................................................................................48 3.5. Hot Socketing Specifications .............................................................................................................................48 3.6. Programming/Erase Specifications ...................................................................................................................48 3.7. ESD Performance...............................................................................................................................................48 3.8. DC Electrical Characteristics ..............................................................................................................................49 3.9. Static Supply Current .........................................................................................................................................50 3.10. Programming and Erase Supply Current............................................................................................................50 3.11. sysI/O Recommended Operating Conditions .....................................................................................................51 3.12. sysI/O Single-Ended DC Electrical Characteristics ..............................................................................................52 3.13. sysI/O Differential Electrical Characteristics .....................................................................................................53 3.13.1. LVDS ..........................................................................................................................................................53 3.13.2. LVDS Emulation ........................................................................................................................................53 3.13.3. LVDS25E DC Conditions ............................................................................................................................54 3.13.4. BLVDS........................................................................................................................................................54 3.13.5. BLVDS DC Condition..................................................................................................................................55 3.13.6. LVPECL .......................................................................................................................................................55 3.13.7. LVPECL DC Conditions...............................................................................................................................56 3.13.8. MIPI D-PHY Emulation ..............................................................................................................................56 3.14. Typical Building Block Function Performance ...................................................................................................59 3.14.1. Pin-to-Pin Performance (LVCMOS25 12 mA Drive) ..................................................................................59 3.14.2. Register-to-Register Performance ............................................................................................................59 3.15. Derating Logic Timing ........................................................................................................................................59 3.16. Maximum sysI/O Buffer Performance...............................................................................................................60 3.17. MachXO3D External Switching Characteristics – HE/HC Devices ......................................................................61 3.18. MachXO3D External Switching Characteristics – ZC Devices ............................................................................69 3.19. sysCLOCK PLL Timing .........................................................................................................................................75 3.20. Flash Download Time ........................................................................................................................................77 3.21. JTAG Port Timing Specifications ........................................................................................................................77 3.22. sysCONFIG Port Timing Specifications...............................................................................................................79 3.23. I2C Port Timing Specifications ............................................................................................................................79 3.24. SPI Port Timing Specifications ...........................................................................................................................80 3.25. Switching Test Conditions .................................................................................................................................80 4. Signal Descriptions ......................................................................................................................................................81 4.1. Pin Information Summary .................................................................................................................................82 5. Ordering Information..................................................................................................................................................84 5.1. MachXO3D Part Number Description ...............................................................................................................84 5.2. Ordering Information ........................................................................................................................................85 5.3. MachXO3D Low Power Commercial and Industrial Grade Devices, Halogen Free (RoHS) Packaging ..............86 5.4. MachXO3D Low Power Automotive Grade Devices, Halogen Free (RoHS) Packaging ......................................87 References ..........................................................................................................................................................................88 Revision History ..................................................................................................................................................................89 © 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 4 FPGA-DS-02026-1.1 MachXO3D Device Family Data Sheet Figures Figure 2.1. Top View of the MachXO3D Device .................................................................................................................. 12 Figure 2.2. PFU Block Diagram ............................................................................................................................................ 13 Figure 2.3. Slice Diagram .................................................................................................................................................... 14 Figure 2.4. Primary Clocks for MachXO3D Devices............................................................................................................. 17 Figure 2.5. Secondary High Fanout Nets for MachXO3D Devices ....................................................................................... 18 Figure 2.6. PLL Diagram ...................................................................................................................................................... 19 Figure 2.7. sysMEM Memory Primitives ............................................................................................................................. 22 Figure 2.8. Memory Core Reset .......................................................................................................................................... 24 Figure 2.9. EBR Asynchronous Reset (Including GSR) Timing Diagram............................................................................... 24 Figure 2.10. Group of Four Programmable I/O Cells .......................................................................................................... 26 Figure 2.11. MachXO3D Output Register Block Diagram (PIO on the Left, Top and Bottom Edges).................................. 28 Figure 2.12. Input Gearbox ................................................................................................................................................. 29 Figure 2.13. Output Gearbox .............................................................................................................................................. 31 Figure 2.14. MachXO3D I/O Banks ..................................................................................................................................... 35 Figure 2.15. Embedded Function Block Interface ............................................................................................................... 36 Figure 2.16. ESB Core Block Diagram .................................................................................................................................. 37 Figure 2.17. I2C Core Block Diagram ................................................................................................................................... 38 Figure 2.18. SPI Core Block Diagram ................................................................................................................................... 40 Figure 2.19. Timer/Counter Block Diagram ........................................................................................................................ 41 Figure 3.1. LVDS Using External Resistors (LVDS25E) ......................................................................................................... 53 Figure 3.2. BLVDS Multi-point-Output Example ................................................................................................................. 54 Figure 3.3. Differential LVPECL ........................................................................................................................................... 55 Figure 3.4. MIPI D-PHY Input Using External Resistors ....................................................................................................... 56 Figure 3.5. MIPI D-PHY Output Using External Resistors .................................................................................................... 57 Figure 3.6. Receiver GDDR71_RX. Waveforms ................................................................................................................... 68 Figure 3.7. Transmitter GDDR71_TX. Waveforms .............................................................................................................. 68 Figure 3.8. JTAG Port Timing Waveforms ........................................................................................................................... 78 Figure 3.9. Output Test Load, LVTTL and LVCMOS Standards ............................................................................................ 80 Figure 5.1. Top Markings for Commercial and Industrial Grade Devices ........................................................................... 85 Figure 5.2. Top Markings for Automotive Grade Devices ................................................................................................... 85 Tables Table 1.1. MachXO3D Family Selection Guide.................................................................................................................... 11 Table 2.1. Resources and Modes Available per Slice .......................................................................................................... 14 Table 2.2. Slice Signal Descriptions ..................................................................................................................................... 15 Table 2.3. Number of Slices Required For Implementing Distributed RAM ....................................................................... 16 Table 2.4. PLL Signal Descriptions ....................................................................................................................................... 20 Table 2.5. sysMEM Block Configurations ............................................................................................................................ 21 Table 2.6. EBR Signal Descriptions ...................................................................................................................................... 22 Table 2.7. Programmable FIFO Flag Ranges ....................................................................................................................... 23 Table 2.8. PIO Signal List ..................................................................................................................................................... 27 Table 2.9. Input Gearbox Signal List ................................................................................................................................... 28 Table 2.10. Output Gearbox Signal List .............................................................................................................................. 30 Table 2.11. Supported Input Standards .............................................................................................................................. 33 Table 2.12. Supported Output Standards ........................................................................................................................... 34 Table 2.13. Available MCLK Frequencies ............................................................................................................................ 36 Table 2.14. I2C Core Signal Description ............................................................................................................................... 39 Table 2.15. SPI Core Signal Description .............................................................................................................................. 40 © 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02026-1.1 5 MachXO3D Device Family Data Sheet Table 2.16. Timer/Counter Signal Description ....................................................................................................................41 Table 2.17. MachXO3D UFM Size .......................................................................................................................................42 Table 2.18. MachXO3D Power Saving Features Description ..............................................................................................43 Table 3.1. Absolute Maximum Rating1, 2, 3 ..........................................................................................................................47 Table 3.2. Recommended Operating Conditions1 ..............................................................................................................47 Table 3.3. Power Supply Ramp Rates .................................................................................................................................47 Table 3.4. Power-On Reset Voltage Levels1, 2, 3, 4 ................................................................................................................48 Table 3.5. Hot Socketing Specifications1, 2, 3 ........................................................................................................................48 Table 3.6. Programming/Erase Specifications ....................................................................................................................48 Table 3.7. DC Electrical Characteristics ...............................................................................................................................49 Table 3.8. Static Supply Current1, 2, 3, 6 .................................................................................................................................50 Table 3.9. Programming and Erase Supply Current1, 2, 3, 4 ...................................................................................................50 Table 3.10. sysI/O Recommended Operating Conditions ...................................................................................................51 Table 3.11. sysI/O Single-Ended DC Electrical Characteristics1, 2 ........................................................................................52 Table 3.12. LVDS .................................................................................................................................................................53 Table 3.13. LVDS25E DC Conditions ....................................................................................................................................54 Table 3.14. BLVDS DC Conditions........................................................................................................................................55 Table 3.15. LVPECL DC Conditions* .....................................................................................................................................56 Table 3.16. MIPI DC Conditions ..........................................................................................................................................57 Table 3.17. MIPI D-PHY Output DC Conditions ...................................................................................................................58 Table 3.18. Pin-to-Pin Performance (LVCMOS25 12 mA Drive) ..........................................................................................59 Table 3.19. Register-to-Register Performance....................................................................................................................59 Table 3.20. Maximum sysI/O Buffer Performance .............................................................................................................60 Table 3.21. MachXO3D External Switching Characteristics – HE/HC Devices1, 2, 3, 4, 5, 6, 10 ...................................................61 Table 3.22. MachXO3D External Switching Characteristics – ZC Devices1, 2, 3, 4, 5, 6 .............................................................69 Table 3.23. sysCLOCK PLL Timing ........................................................................................................................................75 Table 3.24. Flash Download Time .......................................................................................................................................77 Table 3.25. JTAG Port Timing Specifications .......................................................................................................................77 Table 3.26. sysCONFIG Port Timing Specifications .............................................................................................................79 Table 3.27. I2C Port Timing Specification1, 2 ........................................................................................................................79 Table 3.28. SPI Port Timing Specifications ..........................................................................................................................80 Table 3.29. Test Fixture Required Components, Non-Terminated Interfaces ....................................................................80 Table 4.1. Signal Descriptions .............................................................................................................................................81 Table 4.2. MachXO3D-4300 ................................................................................................................................................82 Table 4.3. MachXO3D-9400 ................................................................................................................................................83 © 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 6 FPGA-DS-02026-1.1 MachXO3D Device Family Data Sheet Acronyms in This Document A list of acronyms used in this document. Acronym Definition AES BGA BLVDS CMOS EBR ECDSA ECDH ECIES ECLK ESB FIPS HMAC HSP I2 C I3C IP JTAG LED LUT LVCMOS LVDS Advanced Encryption Standard Ball Grid Array Bidirectional Low Voltage Differential Signaling Complementary Metal Oxide Semiconductor Embedded Block RAM Elliptic Curve Digital Signature Algorithm Elliptic Curve Diffie-Hellman Elliptic Curve Integrated Encryption Scheme Edge Clock Embedded Security Block Federal Information Processing Standard Hash Message Authentication Code High Speed Port Inter-Integrated Circuit Improved Inter-Integrated Circuit Intellectual Property Joint Test Action Group Light-emitting Diode Look Up Table Low Voltage CMOS Low Voltage Differential Signaling LVPECL LVTTL MIPI MLVDS MES OTP PCLK PFU PLL Low Voltage Positive Emitter Coupled Logic Low Voltage Transistor-Transistor Logic Mobile Industry Processor Interface Multipoint Low-Voltage Differential Signaling Manufacture Electronic Signature One Time Programmable Primary Clock Programmable Functional Unit Phase Locked Loop POR RAM SHA SPI TransFR TRNG TTL UFM Power On Reset Random Access Memory Secure Hash Algorithm Serial Peripheral Interface Transparent Field Reconfiguration True Random Number Generator Transistor-Transistor Logic User Flash Memory © 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02026-1.1 7 MachXO3D Device Family Data Sheet 1. Introduction The MachXO3D™ device family is the next generation of Lattice Semiconductor Low Density PLDs including enhanced security features and on-chip dual boot flash. The enhanced security features include Advanced Encryption Standard (AES) AES-128/256, Secure Hash Algorithm (SHA) SHA-256, Elliptic Curve Digital Signature Algorithm (ECDSA), Elliptic Curve Integrated Encryption Scheme (ECIES), Hash Message Authentication Code (HMAC) HMAC-SHA256, Public Key Cryptography, and Unique Secure ID. The MachXO3D family is a Root-of-Trust hardware solution that can easily scale to protect the whole system with its enhanced bitstream security and user mode functions. MachXO3D device provides breakthrough I/O density with high number of options for I/O programmability. The device I/O features the support for latest industry standard I/O, including programmable slew-rate enhancements and I3C support. The MachXO3D family of low power, instant-on, Flash based PLDs have two devices with densities of 4300 and 9400 Look-Up Tables (LUTs). MachXO3D devices include on-chip dual boot configuration flash as well as multi-sectored User Flash Memory (UFM). In addition to LUT-based programmable logic, these devices feature Embedded Block RAM (EBR), Distributed RAM, Phase Locked Loops (PLLs), pre-engineered source synchronous I/O support, advanced configuration support including on-chip dual-boot capability and hardened versions of commonly used functions such as SPI controller, I2C controller, and timer/counter. The MachXO3D devices are designed on a 65-nm non-volatile low power process. The device architecture has several features such as programmable low swing differential I/O and the ability to turn off I/O banks, on-chip PLLs and oscillators dynamically. These features help manage static and dynamic power consumption resulting in low power for all members of the family. The MachXO3D devices are available in two performance levels: ultra low power (ZC) and high performance (HC). The ultra low power devices are offered in two speed grades: –2 and –3, with –3 being the fastest. Similarly, the high-performance devices are offered in two speed grades: –5 and –6, with –6 being the fastest. ZC/HC devices have an internal linear voltage regulator, which supports external VCC supply voltages of 3.3 V or 2.5 V. With the exception of power/performance profiles, the two types of devices, ZC and HC, are pin compatible with each other. MachXO3D also features a high performance automotive device (HE) that has VCC supply voltage of 1.2 V. The MachXO3D PLDs are available in a broad range of advanced halogen-free packages ranging from the space saving 10 x 10 mm QFN to the 19 x 19 mm caBGA. MachXO3D devices support density migration within the same package. Table 1.1 shows the LUT densities, package and I/O options, along with other key parameters. The MachXO3D devices offer enhanced I/O features such as drive strength control, finer slew rate control, I3C compatibility, bus-keeper latches, pull-up resistors, pull-down resistors, open drain outputs, and hot socketing. Pull-up, pull-down, and bus-keeper features are controllable on a per-pin basis. A user-programmable internal oscillator is included in MachXO3D devices. The clock output from this oscillator may be divided by the timer or counter for use as clock input in functions such as LED control, key-board scanner, and similar state machines. The MachXO3D devices also provide flexible, reliable, and secure configuration from on-chip Flash with the encryption and authentication options. These devices can also configure themselves from external SPI Flash or be configured by an external master through the JTAG test access port or through the SPI/I2C port. Additionally, MachXO3D devices support on-chip dual-boot capability to reduce the system cost and remote field upgrade TransFR capability. Lattice Semiconductor provides a variety of design tools that allow complex designs to be efficiently implemented using the MachXO3D family of devices. Popular logic synthesis tools provide synthesis library support for MachXO3D devices. Lattice design tools use the synthesis tool output along with the user-specified preferences and constraints to place and route the design in the MachXO3D device. These tools extract the timing from the routing and back-annotate it into the design for timing verification. Lattice Semiconductor provides many pre-engineered Intellectual Property (IP) LatticeCORETM modules, including a number of reference designs licensed free of charge, optimized for the MachXO3D PLD family. By using these configurable soft core IP cores as standardized blocks, you are free to concentrate on the unique aspects of their design, increasing their productivity. © 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 8 FPGA-DS-02026-1.1 MachXO3D Device Family Data Sheet 1.1. 1.1.1.              Dedicated Embedded Security Block Advanced Encryption Standard (AES): AES-128/256 Encryption/Decryption Secure Hash Algorithm (SHA): SHA-256 Elliptic Curve Digital Signature Algorithm (ECDSA): ECDSA-based authentication Hash Message Authentication Code (HMAC): HMAC-SHA256 Elliptic Curve Integrated Encryption Scheme (ECIES): ECIES Encryption and Decryption True Random Number Generator (TRNG) Key Management using Elliptic Curve DiffieHellman (ECDH) Public Key Cryptography Unique Secure ID Guard against malicious attacks Interface for user logic via WISHBONE and High Speed Port (HSP) Federal Information Processing Standard (FIPS) supported Security Protocols 1.1.4.     Flexible Architecture Logic Density ranging from 4.3K to 9.4K LUT4 High I/O to LUT ratio with up to 383 I/O pins 1.1.3.  Solutions Best-In-Class control PLD with advanced security functions, provide secure/authenticated boot and root of trust function Optimized footprint, logic density, I/O count, I/O performance devices for I/O management and logic applications High I/O logic, high I/O devices for I/O expansion applications 1.1.2.   Features Pre-Engineered Source Synchronous I/O 1.1.5.        Programmable sysI/OTM buffer supports wide range of interfaces:  LVCMOS 3.3/2.5/1.8/1.5/1.2  LVTTL  LVDS, Bus-LVDS, MLVDS, LVPECL  MIPI D-PHY Emulated  Schmitt trigger inputs, up to 0.5 V hysteresis Ideal for I/O bridging applications I3C compatible on selective I/O Slew rate control as Slow/Fast I/O support hot socketing On-chip differential termination Programmable pull-up or pull-down mode 1.1.6.         Flexible On-Chip Clocking Eight primary clocks Up to two edge clocks for high-speed I/O interfaces (top and bottom sides only) Two analog PLLs per device with fractional-n frequency synthesis  Wide input frequency range (7 MHz to 400 MHz). 1.1.7.  High Performance, Flexible I/O Buffer Non-volatile, Reconfigurable Instant-on  Powers up in microseconds On-chip dual boot Multi-sectored UFM for customer data storage Single-chip, secure solution Programmable through JTAG, SPI or I2C Reconfigurable Flash  Supports background programming of non-volatile memory DDR registers in I/O cells Dedicated gearing logic 7:1 Gearing for Display I/O Generic DDR, DDRx2, DDRx4 © 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02026-1.1 9 MachXO3D Device Family Data Sheet 1.1.8.  TransFR Reconfiguration In-field logic update while I/O holds the system state 1.1.10. Advanced Packaging   1.1.9.       Enhanced System Level Support On-chip hardened functions: SPI, I2C, and timer/counter On-chip oscillator with 5.5% accuracy for Commercial and Industrial operation and 9.6% accuracy for Automotive operation Unique TraceID for system tracking Single power supply with extended operating range IEEE Standard 1149.1 boundary scan IEEE 1532 compliant in-system programming  0.5 mm pitch: 4.3K to 9.4K densities with up to 58 I/O in QFN packages 0.8 mm pitch: 4.3K to 9.4K densities with up to 383 I/O in BGA packages Pin-compatible with MachXO3LF product family of devices 1.1.11. Applications       Secure boot and Root of Trust Consumer Electronics Compute and Storage Wireless Communications Industrial Control Systems Automotive System © 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 10 FPGA-DS-02026-1.1 MachXO3D Device Family Data Sheet Table 1.1. MachXO3D Family Selection Guide Features LUTs MachXO3D-4300 MachXO3D-9400 4300 9400 Distributed RAM (kbits) 34 73 EBR SRAM (kbits) 92 432 367/11224 1088/26934 UFM (kbits) Number of PLLs Hardened Functions 2 2 Security 1 1 I2 C 2 2 SPI 1 1 Timer/ Counter 1 1 1 1 On-chip Dual-boot Oscillator Yes Yes I3C compatible I/O Yes1 Yes1 MIPI D-PHY Support2 Yes Yes Core Vcc Temperature 2.5 – 3.3 V ZC/HC ZC/HC 1.2 V NA HE Commercial Yes Yes Industrial Yes Yes Automotive Yes3 Yes5 Packages I/O 72 QFN (10 mm x 10 mm, 0.5 mm) 58 (HC/ZC) 58 (HC/ZC) 256-ball caBGA (14 mm x 14 mm, 0.8 mm) 206 (HC6/ZC) 206 (HC/ZC) 400-ball caBGA (17 mm x 17 mm, 0.8 mm) — 335 (HC/ZC) 484-ball caBGA — 383 (HC/ZC6/HE6) (19 mm x 19 mm, 0.8 mm) Notes: 1. Four pairs of I/O in Bank 3 with I3C dynamic pull up capability. 2. HC device only. 3. HC/HE lowest speed grade device only. 4. When dual-boot is disabled, image space can be repurposed as extra UFM. Refer to Table 2.17 for more details. 5. ZC and HE lowest speed grade device only. 6. Package is available for automotive devices only. © 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02026-1.1 11 MachXO3D Device Family Data Sheet 2. Architecture 2.1. Architecture Overview The MachXO3D family architecture contains an array of logic blocks surrounded by Programmable I/O (PIO). All logic density devices in this family have sysCLOCK™ PLLs and blocks of sysMEM Embedded Block RAM (EBRs). Figure 2.1 shows the block diagrams of the various family members. Figure 2.1. Top View of the MachXO3D Device The logic blocks, Programmable Functional Unit (PFU) and sysMEM EBR blocks, are arranged in a two-dimensional grid with rows and columns. Each row has either the logic blocks or the EBR blocks. The PIO cells are located at the periphery of the device, arranged in banks. The PFU contains the building blocks for logic, arithmetic, RAM, ROM, and register functions. The PIOs utilize a flexible I/O buffer referred to as a sysI/O buffer that supports operation with a variety of interface standards. The blocks are connected with many vertical and horizontal routing channel resources. The place and route software tool automatically allocates these routing resources. In the MachXO3D family, the number of sysI/O banks varies by device. There are different types of I/O buffers on the different banks. Refer to the details in later sections of this document. The sysMEM EBRs are large, dedicated fast memory blocks. These blocks can be configured as RAM, ROM or FIFO. FIFO support includes dedicated FIFO pointer and flag hard control logic to minimize LUT usage. The MachXO3D registers in PFU and sysI/O can be configured to be SET or RESET. After power up and device is configured, the device enters into user mode with these registers SET/RESET according to the configuration setting, allowing device entering to a known state for predictable system function. The MachXO3D architecture also provides up to two sysCLOCK Phase Locked Loop (PLL) blocks. These blocks are located at the ends of the on-chip Flash block. The PLLs have multiply, divide, and phase shifting capabilities that are used to manage the frequency and phase relationships of the clocks. The Embedded Security Block (ESB) integrates multiple security blocks used for authenticated boot function of the MachXO3D device. User IP located in the fabric can also use these hardened blocks for implementing system level security functions. © 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 12 FPGA-DS-02026-1.1 MachXO3D Device Family Data Sheet MachXO3D devices provide commonly used hardened functions such as SPI controller, I2C controller, and timer/counter. MachXO3D devices also provide multiple blocks of User Flash Memory (UFM). These hardened functions and the UFM interface to the core logic and routing through a WISHBONE interface. The UFM space also provides the User Key storage for customer security functions. The UFM can also be accessed through the SPI, I2C, and JTAG ports. Every device in the family has a JTAG port that supports programming and configuration of the device as well as access to the user logic. The MachXO3D devices are available for operation from 3.3 V and 2.5 V power supplies, providing easy integration into the overall system. 2.2. PFU Blocks The core of the MachXO3D device consists of PFU blocks, which can be programmed to perform logic, arithmetic, distributed RAM and distributed ROM functions. Each PFU block consists of four interconnected slices numbered 0 to 3 as shown in Figure 2.2. Each slice contains two LUTs and two registers. There are 53 inputs and 25 outputs associated with each PFU block. Figure 2.2. PFU Block Diagram 2.2.1. Slices Slices 0-3 contain two LUT4s feeding two registers. Slices 0-2 can be configured as distributed memory. Table 2.1 shows the capability of the slices in PFU blocks along with the operation modes they enable. In addition, each PFU contains logic that allows the LUTs to be combined to perform functions such as LUT5, LUT6, LUT7 and LUT8. The control logic performs set/reset functions (programmable as synchronous/asynchronous), clock select, chip-select and wider RAM/ROM functions. © 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02026-1.1 13 MachXO3D Device Family Data Sheet Table 2.1. Resources and Modes Available per Slice Slice PFU Block Resources Modes Slice 0 2 LUT4s and 2 Registers Logic, Ripple, RAM, ROM Slice 1 Slice 2 Slice 3 2 LUT4s and 2 Registers 2 LUT4s and 2 Registers 2 LUT4s and 2 Registers Logic, Ripple, RAM, ROM Logic, Ripple, RAM, ROM Logic, Ripple, ROM Figure 2.3 shows an overview of the internal logic of the slice. The registers in the slice can be configured for positive/negative and edge triggered or level sensitive clocks. All slices have 15 inputs from routing and one from the carry-chain (from the adjacent slice or PFU). There are seven outputs: six for routing and one to carry-chain (to the adjacent PFU). Table 2.2 lists the signals associated with Slices 0-3. Figure 2.3. Slice Diagram © 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 14 FPGA-DS-02026-1.1 MachXO3D Device Family Data Sheet Table 2.2. Slice Signal Descriptions Function Input Input Type Data signal Data signal Signal Names A0, B0, C0, D0 A1, B1, C1, D1 Input Multi-purpose M0/M1 Input Control signal CE Input Control signal LSR Input Control signal CLK Input Inter-PFU signal FCIN Output Data signals F0, F1 Output Data signals Q0, Q1 Output Data signals OFX0 Output Data signals OFX1 Output Inter-PFU signal FCO Notes: 1. See Figure 2.2 for connection details. 2. Requires two PFUs. 2.2.2. Description Inputs to LUT4 Inputs to LUT4 Multi-purpose input Clock enable Local set/reset System clock Fast carry in1 LUT4 output register bypass signals Register outputs Output of a LUT5 MUX Output of a LUT6, LUT7, LUT82 MUX depending on the slice Fast carry out1 Modes of Operation Each slice has up to four potential modes of operation: Logic, Ripple, RAM and ROM. 2.2.2.1. Logic Mode In this mode, the LUTs in each slice are configured as 4-input combinatorial lookup tables. A LUT4 can have 16 possible input combinations. Any four input logic functions can be generated by programming this lookup table. Since there are two LUT4s per slice, a LUT5 can be constructed within one slice. Larger look-up tables such as LUT6, LUT7, and LUT8 can be constructed by concatenating other slices. Note that LUT8 requires more than four slices. 2.2.2.2. Ripple Mode Ripple mode supports the efficient implementation of small arithmetic functions. In Ripple mode, the following functions can be implemented by each slice:  Addition 2-bit  Subtraction 2-bit  Add/subtract 2-bit using dynamic control  Up counter 2-bit  Down counter 2-bit  Up/down counter with asynchronous clear  Up/down counter with preload (sync)  Ripple mode multiplier building block Multiplier support  Comparator functions of A and B inputs  A greater-than-or-equal-to B  A not-equal-to B  A less-than-or-equal-to B Ripple mode includes an optional configuration that performs arithmetic using fast carry chain methods. In this configuration (also referred to as CCU2 mode), two additional signals, Carry Generate and Carry Propagate, are generated on a per-slice basis to allow fast arithmetic functions to be constructed by concatenating slices. © 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02026-1.1 15 MachXO3D Device Family Data Sheet 2.2.3. RAM Mode In this mode, a 16x4-bit distributed single port RAM (SPR) can be constructed by using each LUT block in Slice 0 and Slice 1 as a 16x1-bit memory. Slice 2 is used to provide memory address and control signals. MachXO3D devices support distributed memory initialization. The Lattice design tools support the creation of a variety of different size memories. Where appropriate, the software constructs these using distributed memory primitives that represent the capabilities of the PFU. Table 2.3 shows the number of slices required to implement different distributed RAM primitives. Table 2.3. Number of Slices Required For Implementing Distributed RAM Number of slices SPR 16 x 4 PDPR 16 x 4 3 3 Note: SPR = Single Port RAM, PDPR = Pseudo Dual Port RAM 2.2.4. ROM Mode ROM mode uses the LUT logic; hence, slices 0-3 can be used in ROM mode. Preloading is accomplished through the programming interface during PFU configuration. 2.3. Routing There are many resources provided in the MachXO3D devices to route signals individually or as buses with related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) segments. The inter-PFU connections are made with three different types of routing resources: x1 (spans two PFUs), x2 (spans three PFUs) and x6 (spans seven PFUs). The x1, x2, and x6 connections provide fast and efficient connections in the horizontal and vertical directions. The design tools take the output of the synthesis tool and places and routes the design. Generally, the place and route tool is completely automatic, although an interactive routing editor is available to optimize the design. 2.4. Clock/Control Distribution Network Each MachXO3D device has eight clock inputs (PCLK [T, C] [Banknum]_[2..0]) – three pins on the left side, two pins each on the bottom and top sides and one pin on the right side. These clock inputs drive the clock nets. These eight inputs can be differential or single-ended and may be used as general purpose I/O if they are not used to drive the clock nets. When using a single ended clock input, only the PCLKT input can drive the clock tree directly. The MachXO3D architecture has three types of clocking resources: edge clocks, primary clocks, and secondary high fanout nets. MachXO3D devices have two edge clocks each on the top and bottom edges. Edge clocks are used to clock I/O registers and have low injection time and skew. Edge clock inputs are from PLL outputs, primary clock pads, edge clock bridge outputs and CIB sources. The eight primary clock lines in the primary clock network drive throughout the entire device and can provide clocks for all resources within the device including PFUs, EBRs and PICs. In addition to the primary clock signals, MachXO3D devices also have eight secondary high fanout signals, which can be used for global control signals, such as clock enables, synchronous or asynchronous clears, presets, output enables, etc. Internal logic can drive the global clock network for internally-generated global clocks and control signals. The maximum frequency for the primary clock network is shown in the MachXO3D External Switching Characteristics table. Primary clock signals for the MachXO3D devices are generated from eight 27:1 muxes. The available clock sources include eight I/O sources, 11 routing inputs, eight clock divider inputs and up to eight sysCLOCK PLL outputs. © 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 16 FPGA-DS-02026-1.1 MachXO3D Device Family Data Sheet Up to 8 8 11 8 27:1 Dynamic Clock Enable Primary Clock 0 27:1 Dynamic Clock Enable Primary Clock 1 27:1 Dynamic Clock Enable Primary Clock 2 27:1 Dynamic Clock Enable Primary Clock 3 27:1 Dynamic Clock Enable Primary Clock 4 27:1 Dynamic Clock Enable Primary Clock 5 27:1 Dynamic Clock Enable 27:1 Primary Clock 6 Clock Switch 27:1 Dynamic Clock Enable 27:1 Clock Switch Figure 2.4. Primary Clocks for MachXO3D Devices Eight secondary high fanout nets are generated from eight 8:1 muxes as shown in Figure 2.5. One of the eight inputs to the secondary high fanout net input mux comes from dual function clock pins and the remaining seven come from internal routing. The maximum frequency for the secondary clock network is shown in MachXO3D External Switching Characteristics table. © 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02026-1.1 17 MachXO3D Device Family Data Sheet 1 Clock Pads 7 8:1 Secondary High Fanout Net 0 8:1 Secondary High Fanout Net 1 8:1 Secondary High Fanout Net 2 8:1 Secondary High Fanout Net 3 8:1 Secondary High Fanout Net 4 8:1 Secondary High Fanout Net 5 8:1 Secondary High Fanout Net 6 8:1 Secondary High Fanout Net 7 Routing Figure 2.5. Secondary High Fanout Nets for MachXO3D Devices 2.4.1. sysCLOCK Phase Locked Loops (PLLs) The sysCLOCK PLLs provide the ability to synthesize clock frequencies. All MachXO3D devices have one or more sysCLOCK PLL. CLKI is the reference frequency input to the PLL and its source can come from an external I/O pin or from internal routing. CLKFB is the feedback signal to the PLL, which can come from internal routing or an external I/O pin. The feedback divider is used to multiply the reference frequency and thus synthesize a higher frequency clock output. The MachXO3D sysCLOCK PLLs support high resolution (16-bit) fractional-N synthesis. Fractional-N frequency synthesis allows you to generate an output clock, which is a non-integer multiple of the input frequency. Each output has its own output divider, thus allowing the PLL to generate different frequencies for each output. The output dividers can have a value from 1 to 128. The output dividers may also be cascaded together to generate low frequency clocks. The CLKOP, CLKOS, CLKOS2, and CLKOS3 outputs can all be used to drive the MachXO3D clock distribution network directly or general purpose routing resources can be used. The LOCK signal is asserted when the PLL determines it has achieved lock and deasserted if a loss of lock is detected. A block diagram of the PLL is shown in Figure 2.6. The setup and hold times of the device can be improved by programming a phase shift into the CLKOS, CLKOS2, and CLKOS3 output clock, which advance or delay the output clock with reference to the CLKOP output clock. This phase shift can be either programmed during configuration or can be adjusted dynamically. In dynamic mode, the PLL may lose lock after a phase adjustment on the output used as the feedback source and not relock until the tLOCK parameter has been satisfied. © 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 18 FPGA-DS-02026-1.1 MachXO3D Device Family Data Sheet The MachXO3D also has a feature that allows you to select between two different reference clock sources dynamically. This feature is implemented using the PLLREFCS primitive. The timing parameters for the PLL are shown in the sysCLOCK PLL Timing table. The MachXO3D PLL contains a WISHBONE port feature that allows the PLL settings, including divider values, to be dynamically changed from the user logic. When using this feature the EFB block must also be instantiated in the design to allow access to the WISHBONE ports. Similar to the dynamic phase adjustment, when PLL settings are updated through the WISHBONE port, the PLL may lose lock and not relock until the tLOCK parameter has been satisfied. The timing parameters for the PLL are shown in the sysCLOCK PLL Timing table. DPHSRC PHASESEL[1:0] Dynamic Phase Adjust PHASEDIR PHASESTEP STDBY CLKOP A0 CLKOP Divider (1 - 128) Phase Adjust/ Edge Trim A2 Mux ClkEn Synch B0 CLKOS Divider (1 - 128) Phase Adjust/ Edge Trim B2 Mux ClkEn Synch C0 CLKOS2 Divider (1 - 128) C2 Mux ClkEn Synch D2 Mux ClkEn Synch REFCLK CLKI CLKFB REFCLK Divider M (1 - 40) Phase detector, VCO, and loop filter. FBKSEL Fractional-N Synthesizer FBKCLK Divider N (1 - 40) D0 Internal Feedback D1 Mux CLKOS CLKOS2 Phase Adjust CLKOS3 Divider (1 - 128) CLKOS3 Phase Adjust CLKOP, CLKOS, CLKOS2, CLKOS3 LOCK 4 RST, RESETM, RESETC, RESETD Lock Detect ENCLKOP, ENCLKOS, ENCLKOS2, ENCLKOS3 PLLCLK, PLLRST, PLLSTB, PLLWE, PLLDATI[7:0], PLLADDR[4:0] PLLDATO[7:0] , PLLACK Figure 2.6. PLL Diagram © 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02026-1.1 19 MachXO3D Device Family Data Sheet Table 2.4 provides signal descriptions of the PLL block. Table 2.4. PLL Signal Descriptions Port Name I/O Description CLKI I Input clock to PLL CLKFB PHASESEL[1:0] PHASEDIR PHASESTEP CLKOP CLKOS CLKOS2 CLKOS3 I I I I O O O O Feedback clock Select which output is affected by Dynamic Phase adjustment ports Dynamic Phase adjustment direction Dynamic Phase step – toggle shifts VCO phase adjust by one step. Primary PLL output clock (with phase shift adjustment) Secondary PLL output clock (with phase shift adjust) Secondary PLL output clock2 (with phase shift adjust) Secondary PLL output clock3 (with phase shift adjust) LOCK O DPHSRC STDBY RST RESETM RESETC RESETD ENCLKOP ENCLKOS ENCLKOS2 ENCLKOS3 PLLCLK PLLRST PLLSTB PLLWE PLLADDR [4:0] PLLDATI [7:0] PLLDATO [7:0] PLLACK O I I I I I I I I I I I I I I I O O PLL LOCK, asynchronous signal. Active high indicates PLL is locked to input and feed- back signals. Dynamic Phase source – ports or WISHBONE is active Standby signal to power down the PLL PLL reset without resetting the M-divider. Active high reset. PLL reset – includes resetting the M-divider. Active high reset. Reset for CLKOS2 output divider only. Active high reset. Reset for CLKOS3 output divider only. Active high reset. Enable PLL output CLKOP Enable PLL output CLKOS when port is active Enable PLL output CLKOS2 when port is active Enable PLL output CLKOS3 when port is active PLL data bus clock input signal PLL data bus reset. This resets only the data bus not any register values. PLL data bus strobe signal PLL data bus write enable signal PLL data bus address PLL data bus data input PLL data bus data output PLL data bus acknowledge signal © 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 20 FPGA-DS-02026-1.1 MachXO3D Device Family Data Sheet 2.5. sysMEM Embedded Block RAM Memory The MachXO3D devices contain sysMEM Embedded Block RAMs (EBRs). The EBR consists of a 9 kb RAM, with dedicated input and output registers. This memory can be used for a wide variety of purposes including data buffering, PROM for the soft processor and FIFO. 2.5.1. sysMEM Memory Block The sysMEM block can implement single port, dual port, pseudo dual port, or FIFO memories. Each block can be used in a variety of depths and widths as shown in Table 2.5. Table 2.5. sysMEM Block Configurations Memory Mode Single Port True Dual Port Pseudo Dual Port FIFO 2.5.2. Configurations 8,192 x 1 4,096 x 2 2,048 x 4 1,024 x 9 8,192 x 1 4,096 x 2 2,048 x 4 1,024 x 9 8,192 x 1 4,096 x 2 2,048 x 4 1,024 x 9 512 x 18 8,192 x 1 4,096 x 2 2,048 x 4 1,024 x 9 512 x 18 Bus Size Matching All of the multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB word 0 to MSB word 0, LSB word 1 to MSB word 1, and so on. Although the word size and number of words for each port varies, this mapping scheme applies to each port. 2.5.3. RAM Initialization and ROM Operation If desired, the contents of the RAM can be preloaded during device configuration. EBR initialization data can be loaded from the Configuration Flash. MachXO3D EBR initialization data can also be loaded from the UFM. To maximize the number of UFM bits, initialize the EBRs used in your design to an all-zero pattern. Initializing to an all-zero pattern does not use up UFM bits. MachXO3D devices have been designed such that multiple EBRs share the same initialization memory space if they are initialized to the same pattern. By preloading the RAM block during the chip configuration cycle and disabling the write controls, the sysMEM block can also be utilized as a ROM. 2.5.4. Memory Cascading Larger and deeper blocks of RAM can be created using EBR sysMEM Blocks. Typically, the Lattice design tools cascade memory transparently, based on specific design inputs. © 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02026-1.1 21 MachXO3D Device Family Data Sheet 2.5.5. Single, Dual, Pseudo-Dual Port and FIFO Modes Figure 2.7 shows the five basic memory configurations and their input/output names. In all the sysMEM RAM modes, the input data and addresses for the ports are registered at the input of the memory array. The output data of the memory is optionally registered at the memory array output. CLK CE OCE DI[8:0] DIA[8:0] AD[12:0] DI[8:0] EBR DO[8:0] EBR RSTA WEA CSA[2:0] OCEA DOA[8:0] RST WE CS[2:0] ADW[8:0] DI[17:0] BE[1:0] CLKW CEW RST ADB[12:0] CLKB CEB ADA[12:0] CLKA CEA Single-Port RAM RSTB WEB CSB[2:0] OCEB DOB[8:0] CLKW WE RST EBR FULLI CSW[1:0] AFF FF AEF EF DO[17:0] ORE CLKR RE EMPTYI CSR[1:0] RPRST FIFO RAM CLKR CER EBR DO[17:0] OCER CSR[2:0] CSW[2:0] True Dual Po rt RAM DI[17:0] ADR[12:0] Pseudo Dual Port RAM AD[12:0] CLK CE OCE EBR DO[17:0] RST CS[2:0] ROM Figure 2.7. sysMEM Memory Primitives Table 2.6. EBR Signal Descriptions Port Name CLK CE OCE1 RST BE1 WE AD DI DO CS AFF FF Description Clock Clock Enable Output Clock Enable Reset Byte Enable Write Enable Address Bus Data In Data Out Chip Select FIFO RAM Almost Full Flag FIFO RAM Full Flag Active State Rising Clock Edge Active High Active High Active High Active High Active High — — — Active High — — © 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 22 FPGA-DS-02026-1.1 MachXO3D Device Family Data Sheet Port Name Description Active State AEF FIFO RAM Almost Empty Flag — EF FIFO RAM Empty Flag — RPRST FIFO RAM Read Pointer Reset — Notes: 1. Optional signals. 2. For dual port EBR primitives a trailing ‘A’ or ‘B’ in the signal name specifies the EBR port A or port B respectively. 3. For FIFO RAM mode primitive, a trailing ‘R’ or ‘W’ in the signal name specifies the FIFO read port or write port respectively. 4. For FIFO RAM mode primitive, FULLI has the same function as CSW(2) and EMPTYI has the same function as CSR(2). 5. In FIFO mode, CLKW is the write port clock, CSW is the write port chip select, CLKR is the read port clock, CSR is the chip select, ORE is the output read enable. The EBR memory supports three forms of write behavior for single or dual port operation:  Normal – Data on the output appears only during the read cycle. During a write cycle, the data (at the current address) does not appear on the output. This mode is supported for all data widths.  Write Through – A copy of the input data appears at the output of the same port. This mode is supported for all data widths.  Read-Before-Write – When new data is being written, the old contents of the address appears at the output. 2.5.6. FIFO Configuration The FIFO has a write port with data-in, CEW, WE and CLKW signals. There is a separate read port with data-out, RCE, RE and CLKR signals. The FIFO internally generates Almost Full, Full, Almost Empty and Empty Flags. The Full and Almost Full flags are registered with CLKW. The Empty and Almost Empty flags are registered with CLKR. Table 2.7 shows the range of programming values for these flags. Table 2.7. Programmable FIFO Flag Ranges Flag Name Full (FF) Almost Full (AF) Almost Empty (AE) Empty (EF) N = Address bit width. Programming Range 1 to max (up to 2N–1) 1 to Full–1 1 to Full–1 0 The FIFO state machine supports two types of reset signals: RST and RPRST. The RST signal is a global reset that clears the contents of the FIFO by resetting the read/write pointer and puts the FIFO flags in their initial reset state. The RPRST signal is used to reset the read pointer. The purpose of this reset is to retransmit the data that is in the FIFO. In these applications, it is important to keep careful track of when a packet is written into or read from the FIFO. © 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02026-1.1 23 MachXO3D Device Family Data Sheet 2.5.7. Memory Core Reset The memory core contains data output latches for ports A and B. These are simple latches that can be reset synchronously or asynchronously. RSTA and RSTB are local signals, which reset the output latches associated with port A and port B respectively. The Global Reset (GSRN) signal resets both ports. The output data latches and associated resets for both ports are as shown in Figure 2.8. Memory Core Figure 2.8. Memory Core Reset 2.5.8. EBR Asynchronous Reset EBR asynchronous reset or GSR (if used) can only be applied if all clock enables are low for a clock cycle before the reset is applied and released a clock cycle after the reset is released, as shown in Figure 2.9. The GSR input to the EBR is always asynchronous. Reset Clock Clock Enable Figure 2.9. EBR Asynchronous Reset (Including GSR) Timing Diagram © 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 24 FPGA-DS-02026-1.1 MachXO3D Device Family Data Sheet If all clock enables remain enabled, the EBR asynchronous reset or GSR may only be applied and released after the EBR read and write clock inputs are in a steady state condition for a minimum of 1/fMAX (EBR clock). The reset release must adhere to the EBR synchronous reset setup time before the next active read or write clock edge. If an EBR is preloaded during configuration, the GSR input must be disabled or the release of the GSR during device wake up must occur before the release of the device I/O becoming active. These instructions apply to all EBR RAM, ROM and FIFO implementations. For the EBR FIFO mode, the GSR signal is always enabled and the WE and RE signals act like the clock enable signals in Figure 2.9. The reset timing rules apply to the RPReset input versus the RE input and the RST input versus the WE and RE inputs. Both RST and RPReset are always asynchronous EBR inputs. Note that there are no reset restrictions if the EBR synchronous reset is used and the EBR GSR input is disabled. 2.6. Programmable I/O Cells (PIC) The programmable logic associated with an I/O is called a PIO. The individual PIO are connected to their respective sysI/O buffers and pads. On the MachXO3D devices, the PIO cells are assembled into groups of four PIO cells called a Programmable I/O Cell or PIC. The PICs are placed on all four sides of the device. On all the MachXO3D devices, two adjacent PIO can be combined to provide a complementary output driver pair. All PIO pairs can implement differential receivers. Half of the PIO pairs on the top edge of these devices can be configured as true LVDS transmit pairs. The PIO pairs on the bottom edge of these devices have on-chip differential termination. © 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02026-1.1 25 MachXO3D Device Family Data Sheet 1 PIC PIO A Input Register Block Output Register Block and Tristate Register Block Pin A PIO B Input Register Block Core Logic/ Routing Input Gearbox Output Gearbox Output Register Block and Tristate Register Block Pin B PIO C Input Register Block Output Register Block and Tristate Register Block Pin C PIO D Input Register Block Output Register Block and Tristate Register Block Pin D Figure 2.10. Group of Four Programmable I/O Cells © 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 26 FPGA-DS-02026-1.1 MachXO3D Device Family Data Sheet 2.7. PIO The PIO contains three blocks: an input register block, output register block, and tri-state register block. These blocks contain registers for operating in a variety of modes along with the necessary clock and selection logic. Table 2.8. PIO Signal List Pin Name CE D INDD INCK Q0 Q1 D0 D1 TD Q TQ SCLK RST 2.7.1. I/O Type Input Input Output Output Output Output Input Input Input Output Output Input Input Description Clock Enable Pin input from sysI/O buffer Register bypassed input Clock input DDR positive edge input Registered input/DDR negative edge input Output signal from the core (SDR and DDR) Output signal from the core (DDR) Tri-state signal from the core Data output signals to sysI/O Buffer Tri-state output signals to sysI/O Buffer System clock for input and output/tri-state blocks. Local set reset signal Input Register Block The input register blocks for the PIO on all edges contain delay elements and registers that can be used to condition high-speed interface signals before they are passed to the device core. 2.7.1.1. Left, Top, Bottom Edges Input signals are fed from the sysI/O buffer to the input register block (as signal D). If desired, the input signal can bypass the register and delay elements and be used directly as a combinatorial signal (INDD), and a clock (INCK). If an input delay is desired, users can select a fixed delay. I/O on the bottom edge also have a dynamic delay, DEL[4:0]. The delay, if selected, reduces input register hold time requirements when using a global clock. The input block allows two modes of operation. In single data rate (SDR) the data is registered with the system clock (SCLK) by one of the registers in the single data rate sync register block. In Generic DDR mode, two registers are used to sample the data on the positive and negative edges of the system clock (SCLK) signal, creating two data streams. 2.7.2. Output Register Block The output register block registers signals from the core of the device before they are passed to the sysI/O buffers. 2.7.2.1. Left, Top, Bottom Edges In SDR mode, D0 feeds one of the flip-flops that then feeds the output. The flip-flop can be configured as a D-type register or latch. In DDR generic mode, D0 and D1 inputs are fed into registers on the positive edge of the clock. At the next falling edge, the registered D1 input is registered into the register Q1. A multiplexer running off the same clock is used to switch the mux between the outputs of registers Q0 and Q1 that feeds the output. Figure 2.11 shows the output register block on the left, top and bottom edges. © 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02026-1.1 27 MachXO3D Device Family Data Sheet Q Q0 D0 Q D/L D1 D Q1 Q SCLK Ou tpu t path TD D Q TQ Tri-state path Figure 2.11. MachXO3D Output Register Block Diagram (PIO on the Left, Top and Bottom Edges) 2.7.3. Tri-state Register Block The tri-state register block registers tri-state control signals from the core of the device before they are passed to the sysI/O buffers. The block contains a register for SDR operation. In SDR, TD input feeds one of the flip-flops that then feeds the output. 2.8. Input Gearbox Each PIC on the bottom edge has a built-in 1:8 input gearbox. Each of these input gearboxes may be programmed as a 1:7 de-serializer or as one IDDRX4 (1:8) gearbox or as two IDDRX2 (1:4) gearboxes. Table 2.9 shows the gearbox signals. Table 2.9. Input Gearbox Signal List Name D ALIGNWD SCLK ECLK[1:0] RST I/O Type Input Input Input Input Input Q[7:0] Output Description High-speed data input after programmable delay in PIO A input register block Data alignment signal from device core Slow-speed system clock High-speed edge clock Reset Low-speed data to device core: Video RX(1:7): Q[6:0] GDDRX4(1:8): Q[7:0] GDDRX2(1:4)(IOL-A): Q4, Q5, Q6, Q7 GDDRX2(1:4)(IOL-C): Q0, Q1, Q2, Q3 These gearboxes have three stage pipeline registers. The first stage registers sample the high-speed input data by the high-speed edge clock on its rising and falling edges. The second stage registers perform data alignment based on the control signals UPDATE and SEL0 from the control block. The third stage pipeline registers pass the data to the device core synchronized to the low-speed system clock. Figure 2.12 shows a block diagram of the input gearbox. © 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 28 FPGA-DS-02026-1.1 MachXO3D Device Family Data Sheet Q21 Q43 D Q D Q Q65 Q0_ Q10 D Q CE Q32 D Q CE Q54 D Q CE D Q S2 Q21 Q43 D Q S0 cdn D Q S4 D Q T0 T2 T4 Q0 Q2 Q4 cdn Q65 S6 D Q Q_6 D Q CE D Q T6 Q6 D Q_6 D Q Q_6 D Q CE Q54 D Q Q65 Q54 D Q Q32 Q43 Q32 D Q CE D Q CE Q10 D Q Q21 D Q CE S7 S5 S3 S1 ECLK0/1 D Q D D D T7 Q7 T5 Q5 T3 Q3 T1 Q1 SCLK SEL0 UPD ATE Figure 2.12. Input Gearbox © 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02026-1.1 29 MachXO3D Device Family Data Sheet 2.9. Output Gearbox Each PIC on the top edge has a built-in 8:1 output gearbox. Each of these output gearboxes may be programmed as a 7:1 serializer or as one ODDRX4 (8:1) gearbox or as two ODDRX2 (4:1) gearboxes. Table 2.10 shows the gearbox signals. Table 2.10. Output Gearbox Signal List Name Q D[7:0] Video TX(7:1): D[6:0] GDDRX4(8:1): D[7:0] GDDRX2(4:1)(IOL-A): D[3:0] GDDRX2(4:1)(IOL-C): D[7:4] SCLK ECLK [1:0] RST I/O Type Output Input — — — — Input Input Input Description High-speed data output Low-speed data from device core — — — — Slow-speed system clock High-speed edge clock Reset The gearboxes have three stage pipeline registers. The first stage registers sample the low-speed input data on the low-speed system clock. The second stage registers transfer data from the low-speed clock registers to the high-speed clock registers. The third stage pipeline registers controlled by high-speed edge clock shift and mux the high-speed data out to the sysI/O buffer. Figure 2.13 shows the output gearbox block diagram. © 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 30 FPGA-DS-02026-1.1 MachXO3D Device Family Data Sheet G ND Figure 2.13. Output Gearbox © 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02026-1.1 31 MachXO3D Device Family Data Sheet 2.10. sysI/O Buffer Each I/O is associated with a flexible buffer referred to as a sysI/O buffer. These buffers are arranged around the periphery of the device in groups referred to as banks. The sysI/O buffers allow users to implement a wide variety of standards that are found in today’s systems including LVCMOS, TTL, LVDS, BLVDS, MLVDS, LVPECL, and I3C. Each bank is capable of supporting multiple I/O standards. In the MachXO3D devices, single-ended output buffers, ratioed input buffers (LVTTL, LVCMOS), differential (LVDS) input buffers are powered using I/O supply voltage (VCCIO). Each sysI/O bank has its own VCCIO. MachXO3D devices contain three types of sysI/O buffer pairs.  Left and Right sysI/O Buffer Pairs  The sysI/O buffer pairs in the left and right banks of the device consist of two single-ended output drivers and two single-ended input buffers (for ratioed inputs such as LVCMOS and LVTTL). The I/O pairs on the left and right of the devices also have differential input buffers. The selective I/O pairs of Bank 3 support I3C dynamic pull up capability. Bottom sysI/O Buffer Pairs  The sysI/O buffer pairs in the bottom bank of the device consist of two single-ended output drivers and two single-ended input buffers (for ratioed inputs such as LVCMOS and LVTTL). The I/O pairs on the bottom also have differential input buffers. Only the I/O on the bottom banks have differential input termination. Top sysI/O Buffer Pairs The sysI/O buffer pairs in the top bank of the device consist of two single-ended output drivers and two single- ended input buffers (for ratioed inputs such as LVCMOS and LVTTL). The I/O pairs on the top also have differential I/O buffers. Half of the sysI/O buffer pairs on the top edge have true differential outputs. The sysI/O buffer pair comprising of the A and B PIOs in every PIC on the top edge have a differential output driver. 2.10.1. Typical I/O Behavior during Power-up The internal power-on-reset (POR) signal is deactivated when VCC and VCCIO0 have reached VPORUP level defined in the Power-On-Reset Voltage table in the DC and Switching Characteristics section of this data sheet. After the POR signal is deactivated, the FPGA core logic becomes active. You need to ensure that all VCCIO banks are active with valid input logic levels to properly control the output logic states of all the I/O banks that are critical to the application. The default configuration of the I/O pins in a blank device is tri-state with a weak pull-down to GND (some pins such as PROGRAMN and the JTAG pins have weak pull-up to VCCIO as the default functionality). The I/O pins maintain the blank configuration until VCC and VCCIO (for I/O banks containing configuration I/O) reach VPORUP levels at which time the I/O takes on the user-configured settings only after a proper download/configuration. There are various ways for you to ensure that there are no spurious signals on critical outputs as the device powers up. 2.10.2. Supported Standards The MachXO3D sysI/O buffer supports both single-ended and differential standards. Single-ended standards can be further subdivided into LVCMOS, LVTTL and I3C. The buffer supports the LVTTL, I3C, LVCMOS 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V standards. In the LVCMOS and LVTTL modes, the buffer has individually configurable options for drive strength, bus maintenance (weak pull-up, weak pull-down, bus-keeper latch or none) and open drain. BLVDS, MLVDS and LVPECL output emulation is supported on all devices. The MachXO3D devices support on-chip LVDS output buffers on approximately 50% of the I/O on the top bank. Differential receivers for LVDS, BLVDS, MLVDS, and LVPECL are supported on all banks of MachXO3D devices. I3C support is provided with selective I/O in the left bank of the MachXO3D devices. © 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 32 FPGA-DS-02026-1.1 MachXO3D Device Family Data Sheet Table 2.11 summarizes the I/O characteristics of the MachXO3D PLDs and shows the I/O standards, together with their supply and reference voltages, supported by the MachXO3D devices. Table 2.11. Supported Input Standards VCCIO (Typ.) Input Standard Single-Ended Interfaces LVTTL LVCMOS33 3.3 V 2.5 V 1.8 V 1.5 V 1.2 V Yes Yes2 Yes2 Yes2 — Yes Yes2 Yes Yes2 Yes2 — 2 2 — Yes2 Yes — 2 LVCMOS25 Yes LVCMOS18 Yes2 Yes2 LVCMOS15 Yes 2 Yes 2 Yes — 2 Yes 2 Yes — 3 LVCMOS12 LVCMOS10R25 LVCMOS10R33 I3C33 I3C18 I3C12 Differential Interfaces LVDS BLVDS, MLVDS, LVPECL, RSDS MIPI1 LVTTLD Yes3 Yes — — Yes Yes Yes 2 Yes — 2 Yes Yes — 2 Yes2 Yes — — — — — — — — Yes — — — — — — Yes Yes Yes Yes Yes Yes Yes — — — — — — — — — Yes Yes2 — Yes Yes — — — — — — — — — LVCMOS33D Yes — LVCMOS25D Yes — LVCMOS18D Yes Yes Notes: 1. These interfaces can be emulated with external resistors in all devices. 2. For reduced functionality, refer to MachXO3D sysI/O Technical Note (FPGA-TN-02068) for more details. 3. This input standard can be supported with the referenced input buffer. © 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02026-1.1 33 MachXO3D Device Family Data Sheet Table 2.12. Supported Output Standards Output Standard Single-Ended Interfaces LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 LVCMOS10R25, Open Drain LVCMOS10R33, Open Drain LVCMOS33, Open Drain LVCMOS25, Open Drain LVCMOS18, Open Drain LVCMOS15, Open Drain LVCMOS12, Open Drain I3C33 I3C25 I3C12 Differential Interfaces LVDS* BLVDS, MLVDS, RSDS* LVPECL* MIPI* LVTTLD LVCMOS33D LVCMOS25D LVCMOS18D *Note: These interfaces can be emulated with external resistors in all devices. VCCIO (Typ.) 3.3 3.3 2.5 1.8 1.5 1.2 — — — — — — — 3.3 2.5 1.2 2.5, 3.3 2.5 3.3 2.5 3.3 3.3 2.5 1.8 © 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 34 FPGA-DS-02026-1.1 MachXO3D Device Family Data Sheet 2.10.3. sysI/O Buffer Banks MachXO3D device has six I/O banks, one bank on the top, right and bottom side and three banks on the left side. Figure 2.14 shows the sysI/O banks and their associated supplies for all devices. G ND V CCIO0 Bank 0 VCCIO5 G ND V CCIO1 VCCIO4 G ND G ND VCCIO3 G ND Bank 2 G ND V CCIO2 Figure 2.14. MachXO3D I/O Banks 2.11. Hot Socketing The MachXO3D devices have been carefully designed to ensure predictable behavior during power-up and power-down. Leakage into I/O pins is controlled to within specified limits. This allows for easy integration with the rest of the system. These capabilities make the MachXO3D device ideal for many multiple power supply and hot-swap applications. 2.12. On-chip Oscillator Every MachXO3D device has an internal CMOS oscillator. The oscillator output can be routed as a clock to the clock tree or as a reference clock to the sysCLOCK PLL using general routing resources. The oscillator frequency can be divided by internal logic. There is a dedicated programming bit and a user input to enable/disable the oscillator. The oscillator frequency ranges from 2.08 MHz to 133 MHz. The software default value of the Master Clock (MCLK) is nominally 2.08 MHz. When a different MCLK is selected during the design process, the following sequence takes place: Device powers up with a nominal MCLK frequency of 2.08 MHz. During configuration, users select a different master clock frequency. The MCLK frequency changes to the selected frequency once the clock configuration bits are received. If you do not select a master clock frequency, then the configuration bitstream defaults to the MCLK frequency of 2.08 MHz. © 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02026-1.1 35 MachXO3D Device Family Data Sheet Table 2.13 lists all the available MCLK frequencies. Table 2.13. Available MCLK Frequencies MCLK (MHz, Nominal) 2.08 (default) 2.46 3.17 4.29 5.54 7 8.31 MCLK (MHz, Nominal) 9.17 10.23 13.3 14.78 20.46 26.6 29.56 MCLK (MHz, Nominal) 33.25 38 44.33 53.2 66.5 88.67 133 2.13. Embedded Hardened IP Functions All MachXO3D devices provide embedded hardened functions such as Security, SPI, I2C, Timer/Counter, and User Flash Memory (UFM). These embedded blocks interface through the WISHBONE interface with routing as shown in Figure 2.15. For security block, it also has the high-speed interface with routing. Figure 2.15. Embedded Function Block Interface © 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 36 FPGA-DS-02026-1.1 MachXO3D Device Family Data Sheet 2.13.1. Embedded Security Block (ESB) IP Core Every MachXO3D device contains one ESB IP core. The core is responsible for all the security related functions, including encryption, authentication, and key generation in both configuration and user modes. Figure 2.16. ESB Core Block Diagram The ESB provides the following major functions:  Secure Hash Algorithm (SHA) — 256 bits  Elliptic Curve Digital Signature Algorithm (ECDSA) — Generation and verification  Message Authentication Codes (MACs) — Hash-based MAC (HMAC)  Elliptic Curve Diffie-Hellman (ECDH) Scheme  Elliptic Curve Cryptography (ECC) Key Pair Generation — Public key/Private key  Elliptic Curve Illustrated Encryption Standard (ECIES) Encryption/Decryption  True Random Number Generator (TRNG)  Advanced Encryption Standard (AES) — 128/256 bits  Authentication controller for configuration engine  WISHBONE interface to user logic  High Speed Port (HSP) for FIFO-based streaming data transfer  Unique Secure ID To ensure the security and authenticity of the configuration bitstream, MachXO3D devices offer the following features:  Bitstream Encryption  Bitstream Authentication  Bitstream Encryption and Authentication When encryption is enabled, Diamond software encrypts the bitstream using AES key. When authentication is enabled, Lattice Diamond software attaches a certificate, which is based on the bitstream digest to the bitstream using customer’s private key from the public/private ECDSA key pair. When both features are enabled, Lattice Diamond © 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02026-1.1 37 MachXO3D Device Family Data Sheet software generates the bitstream digest and attaches the ECDSA certificate/signature to this bitstream first. In the second step, this bitstream with the signature is encrypted using the AES Key. When programming the bitstream to the configuration image space, AES decryption and authentication are executed based on the associated AES/ECDSA public key. Once the authentication is successful, the programming is complete and the "Done" bit is set. If the authentication is unsuccessful, the MachXO3D device stays in an unprogrammed state. After programming successfully, the MachXO3D SRAM is configured from flash to enter normal mode after power-cycling, refresh, or ProgramN toggling. It is optional to run the authentication again for each configuration with the selection of fast boot. There are multiple hard/soft lock controls to enable the reading and writing of specific Flash location, configuration or UFM, for the high security application with the OTP option to prevent any further change to the device. MachXO3D device provides a unique, immutable key known with Unique Secure ID. Unique Secure ID is used by ESB to generate paired public key, to perform AES encryption and decryption, and to provide other security related functions. This Unique Secure ID is unique for every device, never leaves the device and is inaccessible. No peripheral can reach the Unique Secure ID including the device own fabric. User logic in the fabric can also access security functions in the ESB through the WISHBONE interface for the control and status register access. Payload data transfer in and out of the ESB is enabled through a FIFO-based pipelined High Speed Port. For example, the MachXO3D device can be used to authenticate the microcontroller firmware image stored in the SPI memory chip attached to the MachXO3D device before booting the microcontroller. Here the High Speed Port with the ESB can be used to transfer the contents stored in the SPI memory into the ESB for digesting of the firmware image, a step associated with the overall ECDSA authentication of the microcontroller firmware. 2.13.2. Hardened I2C IP Core Every MachXO3D device contains two I2C IP cores. These are the primary and secondary I2C IP cores. Either of the two cores can be configured either as an I2C master or as an I2C slave. The only difference between the two IP cores is that the primary core has pre-assigned I/O pins whereas users can assign I/O pins for the secondary core. When the IP core is configured as a master, it is able to control other devices on the I2C bus through the interface. When the core is configured as the slave, the device is able to provide I/O expansion to an I2C Master. The I2C cores support the following functionality:  Master and Slave operation  7-bit and 10-bit addressing  Multi-master arbitration support  Up to 400 kHz data transfer speed general call support  On-chip spike/glitch rejection to preserve data integrity  Interface to custom logic through 8-bit WISHBONE interface Figure 2.17. I2C Core Block Diagram © 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 38 FPGA-DS-02026-1.1 MachXO3D Device Family Data Sheet Table 2.14 describes the signals interfacing with the I2C cores. Table 2.14. I2C Core Signal Description Signal Name I/O i2c_scl Bi-directional i2c_sda Bi-directional i2c_irqo Output cfg_wake Output cfg_stdby Output Description Bidirectional clock line of the I2C core. The signal is an output if the I2C core is in master mode. The signal is an input if the I2C core is in slave mode. MUST be routed directly to the pre-assigned I/O of the chip. Refer to the Pin Information Summary section of this document for detailed pad and pin locations of I2C ports in each MachXO3D device. Bidirectional data line of the I2C core. The signal is an output when data is transmitted from the I2C core. The signal is an input when data is received into the I2C core. MUST be routed directly to the pre-assigned I/O of the chip. Refer to the Pin Information Summary section of this document for detailed pad and pin locations of I2C ports in each MachXO3D device. Interrupt request output signal of the I2C core. The intended usage of this signal is for it to be connected to the WISHBONE master controller (i.e. a microcontroller or state machine) and request an interrupt when a specific condition is met. These conditions are described with the I2C register definitions. Wake-up signal – To be connected only to the power module of the MachXO3D device. The signal is enabled only if the “Wakeup Enable” feature has been set within the EFB GUI, I2C Tab. Stand-by signal – To be connected only to the power module of the MachXO3D device. The signal is enabled only if the “Wakeup Enable” feature has been set within the EFB GUI, I2C Tab. 2.13.3. Hardened SPI IP Core Every MachXO3D device has a hard SPI IP core that can be configured as an SPI master or slave. When the IP core is configured as a master, it is able to control other SPI enabled chips connected to the SPI bus. When the core is configured as the slave, the device is able to interface to an external SPI master. The SPI IP core on MachXO3D devices supports the following functions:  Configurable Master and Slave modes  Full-duplex data transfer  Mode fault error flag with CPU interrupt capability double-buffered data register  Serial clock with programmable polarity and phase  LSB first or MSB first data transfer  Interface to custom logic through 8-bit WISHBONE interface © 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02026-1.1 39 MachXO3D Device Family Data Sheet EFB SPI Function MISO MOSI SPI Registers SCK MCSN SCSN Figure 2.18. SPI Core Block Diagram Table 2.15 describes the signals interfacing with the SPI cores. Table 2.15. SPI Core Signal Description Signal Name spi_csn[0] spi_csn[1..7] spi_scsn spi_irq spi_clk spi_miso spi_mosi I/O O O I O I/O I/O I/O Master/Slave Master Master Slave Master/Slave Master/Slave Master/Slave Master/Slave sn I Slave cfg_stdby O Master/Slave cfg_wake O Master/Slave Description SPI master chip-select output Additional SPI chip-select outputs (total up to eight slaves) SPI slave chip-select input Interrupt request SPI clock. Output in master mode. Input in slave mode. SPI data. Input in master mode. Output in slave mode. SPI data. Output in master mode. Input in slave mode. Configuration Slave Chip Select (active low), dedicated for selecting the Configuration Logic. Stand-by signal – To be connected only to the power module of the MachXO3D device. The signal is enabled only if the “Wakeup Enable” feature has been set within the EFB GUI, SPI Tab. Wake-up signal – To be connected only to the power module of the MachXO3D device. The signal is enabled only if the “Wakeup Enable” feature has been set within the EFB GUI, SPI Tab. © 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 40 FPGA-DS-02026-1.1 MachXO3D Device Family Data Sheet 2.13.4. Hardened Timer/Counter MachXO3D devices provide a hard Timer/Counter IP core. This Timer/Counter is a general purpose, bidirectional, 16-bit timer/counter module with independent output compare units and PWM support. The Timer/Counter supports the following functions:  Supports the following modes of operation:  Watchdog timer  Clear timer on compare match  Fast PWM  Phase and Frequency Correct PWM  Programmable clock input source  Programmable input clock prescaler  One static interrupt output to routing  One wake-up interrupt to on-chip standby mode controller  Three independent interrupt sources: overflow, output compare match, and input capture  Automatically reloading  Time-stamping support on the input capture unit  Waveform generation on the output  Glitch-free PWM waveform generation with variable PWM period  Internal WISHBONE bus access to the control and status registers  Stand-alone mode with preloaded control registers and direct reset input Figure 2.19. Timer/Counter Block Diagram Table 2.16. Timer/Counter Signal Description Port tc_clki tc_rstn I/O I I tc_ic I tc_int O tc_oc O Description Timer/Counter input clock signal Register tc_rstn_ena is preloaded by configuration to always keep this pin enabled Input capture trigger event, applicable for non-pwm modes with WISHBONE interface. If enabled, a rising edge of this signal is detected and synchronized to capture tc_cnt value into tc_icr for time-stamping. Without WISHBONE – Can be used as overflow flag With WISHBONE – Controlled by three IRQ registers Timer counter output signal © 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02026-1.1 41 MachXO3D Device Family Data Sheet 2.14. User Flash Memory (UFM) MachXO3D devices provide a UFM block that can be used for a variety of applications including storing a portion of the configuration image, initializing EBRs to store PROM data or, as a general purpose user Flash memory. It also has a dedicated block for the user key storage and lock control. The UFM block connects to the device core through the embedded function block WISHBONE interface. You can also access the UFM block through the JTAG, I2C, and SPI interfaces of the device. The UFM block offers the following features:  Non-volatile storage up to 1088 kb  Dedicated 172 kb non-volatile storage (UFM2/3) for user key  100K write cycles  Write access is performed page-wise; each page has 128 bits (16 bytes)  Auto-increment addressing  WISHBONE interface Table 2.17. MachXO3D UFM Size Device UFM0 (kbit) UFM1 (kbit) UFM2 (kbit) UFM3 (kbit) MACHXO3D-4300 98 98 147 24 CFG1 (kbit)* 755 MACHXO3D-9400 458 458 147 24 1,605 *Note: When the dual boot feature is disabled, the CFG1 space can be repurposed as the additional UFM usage. 2.15. Standby Mode and Power Saving Options MachXO3D devices are available in two options for maximum flexibility: ZC and HC devices. The ZC devices have ultra low static and dynamic power consumption. The HC devices are designed to provide high performance. The HC devices have a built-in voltage regulator to allow for 2.5 V VCC and 3.3 V VCC. MachXO3D devices have been designed with features that allow users to meet the static and dynamic power requirements of their applications by controlling various device subsystems such as the bandgap, power-on-reset circuitry, I/O bank controllers, power guard, on-chip oscillator, PLLs, etc. In order to maximize power savings, MachXO3D devices support a low power Stand-by mode. In the stand-by mode, the MachXO3D devices are powered on and configured. Internal logic, I/O and memories are switched on and remain operational, as the user logic waits for an external input. The device enters this mode when the standby input of the standby controller is toggled or when an appropriate I2C or JTAG instruction is issued by an external master. Various subsystems in the device such as the band gap, power-on-reset circuitry can be configured such that they are automatically turned “off” or go into a low power consumption state to save power when the device enters this state. Note that the MachXO3D devices are powered on when in standby mode and all power supplies should remain in the Recommended Operating Conditions. © 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 42 FPGA-DS-02026-1.1 MachXO3D Device Family Data Sheet Table 2.18. MachXO3D Power Saving Features Description Device Subsystem Bandgap Power-On-Reset (POR) On-Chip Oscillator PLL I/O Bank Controller Dynamic Clock Enable for Primary Clock Nets Power Guard Feature Description The bandgap can be turned off in standby mode. When the Bandgap is turned off, analog circuitry such as the POR, PLLs, on-chip oscillator, and differential I/O buffers are also turned off. The POR can be turned off in standby mode. This monitors VCC levels. In the event of unsafe VCC drops, this circuit reconfigures the device. When the POR circuitry is turned off, limited power detector circuitry is still active. This option is only recommended for applications in which the power supply rails are reliable. The on-chip oscillator has two power saving features. It may be switched off if it is not needed in your design. It can also be turned off in Standby mode. Similar to the on-chip oscillator, the PLL also has two power saving features. It can be statically switched off if it is not needed in a design. It can also be turned off in Standby mode. The PLL waits until all output clocks from the PLL are driven low before powering off. Differential I/O buffers (used to implement standards such as LVDS) consume more than ratioed single-ended I/O such as LVCMOS and LVTTL. The I/O bank controller allows you to turn these I/O off dynamically on a per bank selection. Each primary clock net can be dynamically disabled to save power. Power Guard is a feature implemented in input buffers. This feature allows users to switch off the input buffer when it is not needed. This feature can be used in both clock and data paths. Its biggest impact is that in the standby mode it can be used to switch off clock inputs that are distributed using general routing resources. 2.16. Power-On-Reset MachXO3D devices have power-on reset circuitry to monitor VCCINT and VCCIO voltage levels during power-up and operation. At power-up, the POR circuitry monitors VCCINT and VCCIO0 (controls configuration) voltage levels. It then triggers download from the on-chip configuration Flash memory after reaching the VPORUP level specified in the Power-On-Reset Voltage table in the DC and Switching Characteristics section of this data sheet. For “C” devices with voltage regulators, VCCINT is regulated from the VCC supply voltage. From this voltage reference, the time taken for configuration and entry into user mode is specified as Flash Download Time (tREFRESH) in the DC and Switching Characteristics section of this data sheet. Before and during configuration, the I/O are held in tri-state. I/O are released to user functionality once the device has finished configuration. Note that for C devices, a separate POR circuit monitors external VCC voltage in addition to the POR circuit that monitors the internal post-regulated power supply voltage level. Once the device enters into user mode, the POR circuitry can optionally continue to monitor VCCINT levels. If VCCINT drops below VPORDNBG level (with the bandgap circuitry switched on) or below VPORDNSRAM level (with the bandgap circuitry switched off to conserve power) device functionality cannot be guaranteed. In such a situation the POR issues a reset and begins monitoring the VCCINT and VCCIO voltage levels. VPORDNBG and VPORDNSRAM are both specified in the Power-On-Reset Voltage table in the DC and Switching Characteristics section of this data sheet. When the bandgap circuitry is switched off, the POR circuitry also shuts down. The device is designed such that a minimal, low power POR circuit is still operational (this corresponds to the VPORDNSRAM reset point described in the paragraph above). However, this circuit is not as accurate as the one that operates when the bandgap is switched on. The low power POR circuit emulates an SRAM cell and is biased to trip before the vast majority of SRAM cells flip. If you are concerned about the VCC supply dropping below VCC (min), they should not shut down the bandgap or POR circuit. © 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02026-1.1 43 MachXO3D Device Family Data Sheet 2.17. Configuration and Testing This section describes the configuration and testing features of the MachXO3D family. 2.17.1. IEEE 1149.1-Compliant Boundary Scan Testability All MachXO3D devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant test access port (TAP). This allows functional testing of the circuit board, on which the device is mounted, through a serial scan path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in and loaded directly onto test nodes, or test data to be captured and shifted out for verification. The test access port consists of dedicated I/O: TDI, TDO, TCK and TMS. The test access port shares its power supply with VCCIO Bank 0 and can operate with LVCMOS3.3, 2.5, 1.8, 1.5, and 1.2 standards. For more details on boundary scan test, see Boundary Scan Testability with Lattice sysI/O Capability (AN8066) and Minimizing System Interruption During Configuration Using TransFR Technology (TN1087). 2.17.2. Device Configuration All MachXO3D devices contain two ports that can be used for device configuration. The Test Access Port (TAP), which supports bit-wide configuration and the sysCONFIG port, which supports serial configuration through I2C or SPI. The TAP supports both the IEEE Standard 1149.1 Boundary Scan specification and the IEEE Standard 1532 In-System Configuration specification. There are various ways to configure a MachXO3D device:  Internal Flash Download  JTAG  Standard Serial Peripheral Interface (Master SPI mode) – interface to boot PROM memory  System microprocessor to drive a serial slave SPI port (SSPI mode)  Standard I2C Interface to system microprocessor Upon power-up, the configuration SRAM is ready to be configured using the selected sysCONFIG port. Once a configuration port is selected, it remains active throughout that configuration cycle. The IEEE 1149.1 port can be activated any time after power-up by sending the appropriate command through the TAP port. Optionally, the device can run a CRC check upon entering the user mode. This ensures that the device was configured correctly. The sysCONFIG port has 10 dual-function pins, which can be used as general purpose I/O, if they are not required for configuration. Lattice design software uses proprietary compression technology to compress bit-streams for use in MachXO3D devices. Use of this technology allows Lattice Semiconductor to provide a lower cost solution. In the unlikely event that this technology is unable to compress bitstreams to fit into the amount of on-chip Flash, there are a variety of techniques that can be utilized to allow the bitstream to fit in the on-chip Flash. 2.17.2.1. Encryption & Authentication With the Embedded Security Block, MachXO3D device can provide highly secured control for the device programming and configuration. It uses ECDSA256 algorithm for Configuration Image Authentication. It has the AES256 encryption for additional security and IP protection. 2.17.2.2. Transparent Field Reconfiguration (TransFR) TransFR is a unique Lattice technology that allows users to update their logic in the field without interrupting system operation using a simple push-button solution. For more details, refer to Minimizing System Interruption During Configuration Using TransFR Technology (TN1087) for details. © 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 44 FPGA-DS-02026-1.1 MachXO3D Device Family Data Sheet 2.17.2.3. Lock Bits and Lock Control Policy MachXO3D device has read, program, and erase permission control for external CFG ports and for internal WISHBONE bus to access Flash sectors. External CFG ports include JTAG, slave SPI, and slave I2C. The way to support this feature is to deploy three permission control setting bits for each sectors as SEC_READ, SEC_PROG, and SEC_ERASE.  SEC_READ — Disable the READ access. This prevents user content from being exposed to external CFG port.  SEC_PROG— Disable the PROGRAM access. This prevents unexpected incremental programming to modify the current user setting, such as AES KEY, ECDSA PUBLIC KEY or authenticated Bitstream, and others.  SEC_ERASE— Disable the ERASE access. This prevents unexpected incremental programming to modify the current user setting, such as AES KEY, ECDSA PUBLIC KEY or authenticated Bitstream, and others. This also ensures a safe boot up. MachXO3D device also provides Hard Lock and Soft Lock modes for flexible permission control. Soft Lock means the security setting bits can be modified by internal WISHBONE bus. In this way, user logic can enable or disable the access by altering the security control bits through internal WISHBONE Bus. Hard Lock mode means user logic cannot alter permission control bits through internal WISHBONE bus. The SEC_HLOCK bit is used to choose between the Soft Lock and Hard Lock modes. For detailed information regarding Lock Bits and Lock Control Policy, refer to MachXO3D Programming and Configuration Usage Guide (FPGA-TN-02069). 2.17.2.4. Tamper Detection and Response Configuration logic automatically detects a variety of threat from configuration ports. These threats include any commands/instructions that:  Try to access Flash/SRAM without entering password or with entering wrong password, if password protection is enabled.  Try to access Flash/SRAM that is under Soft/Hard Lock protection.  Attempt to enter MANUFACTURE mode.  Shift in a wrong password by LSC_SHIFT_PASSWORD. The Configuration module asserts threat detect to user logic once the enabled type of threat has been detected. Also, the Configuration module reports which type of threat is detected and from which configuration port the threat comes. Once a certain threat has been detected, User logic may inform the Configuration module to disable configuration ports to avoid a dictionary style attack. 2.17.2.5. Password The MachXO3D device maintains the legacy support, as in the previous generation, for password-based security access feature also known as Flash Protect Key. The Flash Protect Key feature provides a method of controlling access to the Configuration and Programming modes of the device. When enabled, the Configuration and Programming edit mode operations including Write, Verify and Erase operations are allowed only when coupled with a Flash Protect Key, which matches that expected by the device. Without a valid Flash Protect Key, you can perform only rudimentary non-configuration operations such as Read Device ID. 2.17.2.6. On-chip Dual Boot MachXO3D devices can optionally boot from two patterns, a primary bitstream and a golden bitstream. If the primary bitstream is found to be corrupt while being downloaded into the SRAM, the device shall then automatically re-boot from the golden bitstream. MachXO3D device also supports the option to boot from the latest image in a ping-pong style, or user select for the boot image. Beyond the On-chip boot, MachXO3D device also provides the external SPI flash boot option. Together with the On-chip boot flash, MachXO3D device can enable the flexible multi-boot function. © 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02026-1.1 45 MachXO3D Device Family Data Sheet 2.17.2.7. Soft Error Detection The Soft Error Detection (SED) feature is a CRC check of the SRAM cells after the device is configured. This check ensures that the SRAM cells were configured successfully. This feature is enabled by a configuration bit option. The Soft Error Detection (SED) can also be initiated in user mode via an input to the fabric. The clock for the Soft Error Detection (SED) circuit is generated using a dedicated divider. The undivided clock from the on-chip oscillator is the input to this divider. For low power applications, you can switch off the Soft Error Detection circuit. 2.17.2.8. Soft Error Correction The MachXO3D device supports Soft Error Correction (SEC). When BACKGROUND_RECONFIG is enabled using the Lattice Diamond Software in a design, asserting the PROGRAMN pin or issuing the REFRESH sysConfig command refreshes the SRAM array from configuration memory. Only the detected error bit is corrected. No other SRAM cells are changed, allowing the user design to function uninterrupted. During the project design phase, if the overall system cannot guarantee containment of the error or its subsequent effects on downstream data or control paths, Lattice Semiconductor recommends using SED only. MachXO3D device can then be soft-reset by asserting PROGRAMN or issuing the Refresh command over a sysConfig port in response to SED. Soft-reset additionally erases the SRAM array prior to the SRAM refresh, and asserts internal Reset circuitry to guarantee a known state. 2.18. TraceID Each MachXO3D device contains a unique (per device) TraceID that can be used for tracking purposes or for IP security applications. The TraceID is 64 bits long. Eight out of 64 bits are user-programmable, the remaining 56 bits are factory-programmed. The TraceID is accessible through the EFB WISHBONE interface and can also be accessed through the SPI, I2C, or JTAG interfaces. 2.19. Density Shifting The MachXO3D family has been designed to enable density migration within the same package. Furthermore, the architecture ensures a high success rate when performing design migration from lower density devices to higher density devices. In many cases, it is also possible to shift a lower utilization design targeted for a high-density device to a lower density device. However, the exact details of the final resource utilization impact the likely success in each case. When migrating from lower to higher density or higher to lower density, ensure to review all the power supplies and NC pins of the chosen devices. © 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 46 FPGA-DS-02026-1.1 MachXO3D Device Family Data Sheet 3. DC and Switching Characteristics 3.1. Absolute Maximum Rating Table 3.1. Absolute Maximum Rating1, 2, 3 MachXO3D ZC/HC (2.5 V/3.3 V) Supply Voltage VCC –0.5 V to 3.75 V Output Supply Voltage VCCIO –0.5 V to 3.75 V I/O Tri-state Voltage Applied 4, 5 –0.5 V to 3.75 V 4 Dedicated Input Voltage Applied –0.5 V to 3.75 V Storage Temperature (Ambient) –55 °C to 125 °C Junction Temperature (TJ) –40 °C to 125 °C Notes: 1. Stress above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. 2. Compliance with the Lattice Thermal Management (FPGA-TN-02044) document is required. 3. All voltages referenced to GND. 4. Overshoot and undershoot of –2 V to (VIHMAX + 2) volts is permitted for a duration of 100 MHz fPFD < 100 MHz — — — 0.039 218 0.015 UIPP ps p-p UIPP fOUT > 100 MHz fOUT < 100 MHz fOUT > 100 MHz fOUT < 100 MHz fOUT > 100 MHz fOUT < 100 MHz fOUT > 100 MHz fOUT < 100 MHz fPFD > 100 MHz fPFD < 100 MHz fOUT > 100 MHz fOUT < 100 MHz fOUT > 100 MHz — — — — — — — — — — — — — 345 0.38 625 0.44 210 0.008 390 0.01 160 0.011 320 0.38 270 ps p-p UIPP ps p-p UIPP ps p-p UIPP ps p-p UIPP ps p-p UIPP ps p-p UIPP ps p-p fOUT < 100 MHz — 0.44 UIPP © 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02026-1.1 75 MachXO3D Device Family Data Sheet Parameter Descriptions tSPO tW tLOCK2, 5 tUNLOCK Static Phase Offset Output Clock Pulse Width PLL Lock-in Time PLL Unlock Time tIPJIT6 Input Clock Period Jitter Conditions Divider ratio = integer At 90% or 10%3 — — fPFD ≥ 20 MHz fPFD < 20 MHz 90% to 90% 10% to 10% — — — — — — — Commercial/Industrial Min. Max. TBD 0.9 — — — — 0.75 0.7 — 1 3.1 10 3 TBD TBD Automotive Min. Max. TBD — 15 50 1,000 0.02 — — 15 — — — — — — Units ps ns ms ns ps p-p UIPP ns ns ms ns ns ns ns ns VCO Cycles tHI Input Clock High Time tLO Input Clock Low Time 5 tSTABLE STANDBY High to PLL Stable tRST RST/RESETM Pulse Width tRSTREC RST Recovery Time tRST_DIV RESETC/D Pulse Width tRSTREC_DIV RESETC/D Recovery Time tROTATE-SETUP PHASESTEP Setup Time tROTATE_WD PHASESTEP Pulse Width Notes: 1. Period jitter sample is taken over 10,000 samples of the primary PLL output with a clean reference clock. Cycle-to-cycle jitter is taken over 1000 cycles. Phase jitter is taken over 2000 cycles. All values per JESD65B. 2. Output clock is valid after tLOCK for PLL reset and dynamic delay adjustment. 3. Using LVDS output buffers. 4. CLKOS as compared to CLKOP output for one phase step at the maximum VCO frequency. See MachXO3D sysCLOCK PLL Design and Usage Guide (FPGA-TN-02070) for more details. 5. At minimum fPFD. As the fPFD increases, the time decreases to approximately 60% the value listed. 6. Maximum allowed jitter on an input clock. PLL unlock may occur if the input jitter exceeds this specification. Jitter on the input clock may be transferred to the output clocks, resulting in jitter measurements outside the output specifications listed in this table. 7. Edge Duty Trim Accuracy is a percentage of the setting value. For Commercial/Industrial devices, valid trim settings are 0 ps, 140 ps and 280 ps or Delay Multipliers of “0”, ”2” and ”4”, respectively, while for Automotive devices, valid trim settings are 0 ps and 280 ps or Delay Multipliers of “0” and ”4”, respectively. 8. Jitter values measured with the internal oscillator operating. The jitter values increase with loading of the PLD fabric and in the presence of SSO noise. © 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 76 FPGA-DS-02026-1.1 MachXO3D Device Family Data Sheet 3.20. Flash Download Time Table 3.24. Flash Download Time Symbol tREFRESH Parameter Device Typ. Units POR to Device I/O Active MACHXO3D-4300 MACHXO3D-9400 — 5.2 ms ms Notes:  Assumes sysMEM EBR initialized to an all zero pattern if they are used.  The NVCM/Flash download time is measured starting from the maximum voltage of POR trip point.  The worst case can be up to 1.75 times the Typ value. 3.21. JTAG Port Timing Specifications Table 3.25. JTAG Port Timing Specifications Symbol fMAX tBTCPH tBTCPL tBTS tBTH tBTCO tBTCODIS tBTCOEN tBTCRS tBTCRH tBUTCO tBTUODIS tBTUPOEN Parameter TCK clock frequency TCK [BSCAN] clock pulse width high TCK [BSCAN] clock pulse width low TCK [BSCAN] setup time TCK [BSCAN] hold time TAP controller falling edge of clock to valid output TAP controller falling edge of clock to valid disable TAP controller falling edge of clock to valid enable BSCAN test capture register setup time BSCAN test capture register hold time BSCAN test update register, falling edge of clock to valid output BSCAN test update register, falling edge of clock to valid disable BSCAN test update register, falling edge of clock to valid enable Min. — 20 20 10 10 — — — 8 20 — — — Max. 25 — — — — 10 12 12 — — 25 27 25 Units MHz ns ns ns ns ns ns ns ns ns ns ns ns © 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02026-1.1 77 MachXO3D Device Family Data Sheet Figure 3.8. JTAG Port Timing Waveforms © 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 78 FPGA-DS-02026-1.1 MachXO3D Device Family Data Sheet 3.22. sysCONFIG Port Timing Specifications Table 3.26. sysCONFIG Port Timing Specifications Symbol Parameter Min. Max. Units PROGRAMN low pulse accept PROGRAMN low pulse rejection MACHXO3D-4300 INITN low time MACHXO3D-9400 PROGRAMN low to INITN low PROGRAMN low to DONE low PROGRAMN low to I/O disable 109 — — — — — — — 60 130 175 150 165 196 ns ns us us ns ns ns CCLK clock frequency CCLK clock pulse width high — 7.5 66 — MHz ns tCCLKL tSTSU tSTH tSTCO tSTOZ tSTOV tSCS tSCSS tSCSH Master SPI CCLK clock pulse width low CCLK setup time CCLK hold time CCLK falling edge to valid output CCLK falling edge to valid disable CCLK falling edge to valid enable Chip select high time Chip select setup time Chip select hold time 7.5 2 0 — — — 25 3 3 — — — 14 12 14 — — — ns ns ns ns ns ns ns ns ns fMAX tMCLKH tMCLKL tSTSU tSTH tCSSPI tMCLK MCLK clock frequency MCLK clock pulse width high MCLK clock pulse width low MCLK setup time MCLK hold time INITN high to chip select low INITN high to first MCLK edge — 7.5 7.5 6 2 100 0.75 66 — — — — 200 1 MHz ns ns ns ns ns us All Configuration Modes tPRGM tPRGMJ tINITL tDPPINIT tDPPDONE tIODISS Slave SPI fMAX tCCLKH 3.23. I2C Port Timing Specifications Table 3.27. I2C Port Timing Specification1, 2 Symbol Parameter fMAX Maximum SCL clock frequency Notes: 1. MachXO3D device supports the following modes:  Standard-mode (Sm), with a bit rate up to 100 kb/s (user and configuration mode)  Fast-mode (Fm), with a bit rate up to 400 kb/s (user and configuration mode) 2. Refer to the I2C specification for timing requirements. Min. — Max. 400 Units kHz © 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02026-1.1 79 MachXO3D Device Family Data Sheet 3.24. SPI Port Timing Specifications Table 3.28. SPI Port Timing Specifications Symbol Parameter fMAX Maximum SCK clock frequency Min. Max. Units — 45 MHz Note: Applies to user mode only. For configuration mode timing specifications, refer to sysCONFIG Port Timing Specifications table in this data sheet. 3.25. Switching Test Conditions Figure 3.9 shows the output test load used for AC testing. The specific values for resistance, capacitance, voltage, and other test conditions are shown in Table 3.29. VT R1 Test Point DUT CL Figure 3.9. Output Test Load, LVTTL and LVCMOS Standards Table 3.29. Test Fixture Required Components, Non-Terminated Interfaces Test Condition Timing Ref. VT LVTTL, LVCMOS 3.3 = 1.5 V LVCMOS 2.5 = VCCIO/2 — LVCMOS 1.8 = VCCIO/2 — LVCMOS 1.5 = VCCIO/2 — LVCMOS 1.2 = VCCIO/2 — 1.5 1.5 VOL VOH VCCIO/2 VOL VCCIO/2 VOH LVTTL + LVCMOS (H -> Z) VOH – 0.15 VOL LVTTL + LVCMOS (L -> Z) VOL – 0.15 VOH LVTTL and LVCMOS settings (L -> H, H -> L) R1 ∞ CL 0 pF LVTTL and LVCMOS 3.3 (Z -> H) LVTTL and LVCMOS 3.3 (Z -> L) Other LVCMOS (Z -> H) Other LVCMOS (Z -> L) 188 0 pF — Note: Output test conditions for all other interfaces are determined by the respective standards. © 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 80 FPGA-DS-02026-1.1 MachXO3D Device Family Data Sheet 4. Signal Descriptions Table 4.1. Signal Descriptions Signal Name General Purpose I/O Descriptions [Edge] indicates the edge of the device on which the pad is located. Valid edge designations are L (Left), B (Bottom), R (Right), T (Top). [Row/Column Number] indicates the PFU row or the column of the device on which the PIO Group exists. When Edge is T (Top) or (Bottom), only need to specify Row Number. When Edge is L (Left) or R (Right), only need to specify Column Number. [A/B/C/D] indicates the PIO within the group to which the pad is connected. Some of these user-programmable pins are shared with special function pins. When not used P[Edge] [Row/Column I/O as special function pins, these pins can be programmed as I/O for user logic. Number]_[A/B/C/D] During configuration of the user-programmable I/O, you have an option to tri-state the I/O and enable an internal pull-up, pull-down or buskeeper resistor. This option also applies to unused pins (or those not bonded to a package pin). The default during configuration is for user-programmable I/O to be tri-stated with an internal pull-down resistor enabled. When the device is erased, I/O is tri-stated with an internal pull-down resistor enabled. Some pins, such as PROGRAMN and JTAG pins, default to tri-stated I/O with pull-up resistors enabled when the device is erased. NC — No connect. GND — GND – Ground. Dedicated pins. It is recommended that all GNDs are tied together. VCC – The power supply pins for core logic. Dedicated pins. It is recommended that all VCCs are VCC — tied to the same supply. VCCIO – The power supply pins for I/O Bank x. Dedicated pins. It is recommended that all VCCIOs VCCIOx — located in the same bank are tied to the same supply. PLL and Clock Functions (Used as user-programmable I/O pins when not used for PLL or clock pins) Reference Clock (PLL) input pads: [LOC] indicates location. Valid designations are L (Left PLL) and R (Right PLL). T = true and C = complement. Optional Feedback (PLL) input pads: [LOC] indicates location. Valid designations are L (Left [LOC]_GPLL[T, C]_FB — PLL) and R (Right PLL). T = true and C = complement. PCLK [n]_[2:0] — Primary Clock pads. One to three clock pads per side. Test and Programming (Dual function pins used for test access port and during sysCONFIG™) TMS I Test Mode Select input pin, used to control the 1149.1 state machine. TCK I Test Clock input pin, used to clock the 1149.1 state machine. TDI I Test Data input pin, used to load data into the device using an 1149.1 state machine. TDO O Output pin – Test Data output pin used to shift data out of the device using 1149.1. Optionally controls behavior of TDI, TDO, TMS, TCK. If the device is configured to use the JTAG pins (TDI, TDO, TMS, TCK) as general purpose I/O, then: JTAGENB I If JTAGENB is low: TDI, TDO, TMS and TCK can function a general purpose I/O. If JTAGENB is high: TDI, TDO, TMS and TCK function as JTAG pins. Configuration (Dual function pins used during sysCONFIG) PROGRAMN I Initiates configuration sequence when asserted low. This pin always has an active pull-up. [LOC]_GPLL[T, C]_IN — INITN I/O DONE I/O MCLK/CCLK I/O SN CSSPIN SI/SPISI SO/SPISO I I/O I/O I/O Open Drain pin. Indicates the FPGA is ready to be configured. During configuration, a pull-up is enabled. Open Drain pin. Indicates that the configuration sequence is complete, and the start-up sequence is in progress. Input Configuration Clock for configuring an FPGA in Slave SPI mode. Output Configuration Clock for configuring an FPGA in SPI and SPIm configuration modes. Slave SPI active low chip select input. Master SPI active low chip select output. Slave SPI serial data input and master SPI serial data output. Slave SPI serial data output and master SPI serial data input. © 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02026-1.1 81 MachXO3D Device Family Data Sheet Signal Name SCL I/O I/O Descriptions Slave I2C clock input and master I2C clock output. SDA I/O Slave I2C data input and master I2C data output. 4.1. Pin Information Summary Table 4.2. MachXO3D-4300 MachXO3D-4300 General Purpose I/O per Bank Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Total General Purpose Single Ended I/O Differential I/O per Bank Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Total General Purpose Differential I/O Dual Function I/O Number 7:1 or 8:1 Gearboxes Number of 7:1 or 8:1 Output Gearbox Available (Bank 0) Number of 7:1 or 8:1 Input Gearbox Available (Bank 2) High-speed Differential Outputs Bank 0 VCCIO Pins Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 VCC GND NC Reserved for Configuration Total Count of Bonded Pins QFN72 CABGA256 19 13 17 9 0 0 58 50 52 52 16 16 20 206 10 5 8 4 0 0 25 26 26 8 8 10 27 33 103 33 5 9 14 14 5 14 3 3 3 1 0 0 3 0 (ePAD) 0 1 72 4 4 4 1 2 1 8 24 1 1 256 © 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 82 FPGA-DS-02026-1.1 MachXO3D Device Family Data Sheet Table 4.3. MachXO3D-9400 MachXO3D-9400 QFN72 CABGA256 CABGA400 CABGA484 19 13 17 9 0 0 58 50 52 52 16 16 20 206 83 84 84 28 24 32 335 95 96 96 36 24 36 383 10 5 8 4 0 0 27 33 25 26 26 8 8 10 103 37 42 42 42 14 12 16 168 37 48 48 48 18 12 18 192 45 5 20 22 24 9 20 22 24 5 20 21 24 3 3 3 1 0 0 3 0 (ePAD) 0 1 72 4 4 4 1 2 1 8 24 1 1 256 5 5 5 2 2 2 10 33 0 1 400 9 9 9 3 3 3 12 52 0 1 484 General Purpose I/O per Bank Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Total General Purpose Single Ended I/O Differential I/O per Bank Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Total General Purpose Differential I/O Dual Function I/O Number 7:1 or 8:1 Gearboxes Number of 7:1 or 8:1 Output Gearbox Available (Bank 0) Number of 7:1 or 8:1 Input Gearbox Available (Bank 2) High-speed Differential Outputs Bank 0 VCCIO Pins Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 VCC GND NC Reserved for Configuration Total Count of Bonded Pins © 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02026-1.1 83 MachXO3D Device Family Data Sheet 5. Ordering Information 5.1. MachXO3D Part Number Description LXMXO3D Device Family Low Density LCMXO3D: MachXO3D FPGA COM/IND LAMXO3D: MachXO3D FPGA AUTO Grade C = Commercial I = Industrial E = Automotive Logic Capacity 4300 = 4320 LUTs 9400 = 9400 LUTs Package SG72 = 72-Pin Halogen-Free QFN (0.5 mm Pitch) BG256 = 256-Ball Halogen-Free caBGA (0.8 mm Pitch) BG400 = 400-Ball Halogen-Free caBGA (0.8 mm Pitch) BG484 = 484-Ball Halogen-Free caBGA (0.8 mm Pitch) Power/Performance Z = Low Power H = High Performance Supply Voltage C = 2.5 V / 3.3 V E = 1.2 V Speed 2 = Slowest (Low Power) 3 = Fastest (Low Power) 5 = Slowest (High Performance) 6 = Fastest (High Performance) © 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 84 FPGA-DS-02026-1.1 MachXO3D Device Family Data Sheet 5.2. Ordering Information MachXO3D devices have top-side markings as shown in the examples below. Markings for the 484-Ball caBGA package with MachXO3D-9400 device in Commercial Temperature in Speed Grade 5: LCMXO3D9400HC 5BG484C Datecode Figure 5.1. Top Markings for Commercial and Industrial Grade Devices Note: Markings are abbreviated for small packages. Markings for the 256-ball caBGA package with MachXO3D-9400 device in Automotive Temperature in Speed Grade 5: LAMXO3D9400HE 5BG484E Datecode Figure 5.2. Top Markings for Automotive Grade Devices © 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02026-1.1 85 MachXO3D Device Family Data Sheet 5.3. MachXO3D Low Power Commercial and Industrial Grade Devices, Halogen Free (RoHS) Packaging Part Number LUTs Supply Voltage Speed Package Leads Temp. LCMXO3D-4300HC-5SG72C LCMXO3D-4300HC-6SG72C LCMXO3D-4300HC-5SG72I LCMXO3D-4300HC-6SG72I LCMXO3D-4300HC-5BG256C LCMXO3D-4300HC-6BG256C LCMXO3D-4300HC-5BG256I LCMXO3D-4300HC-6BG256I LCMXO3D-4300ZC-2SG72C LCMXO3D-4300ZC-3SG72C LCMXO3D-4300ZC-2SG72I LCMXO3D-4300ZC-3SG72I LCMXO3D-4300ZC-2BG256C LCMXO3D-4300ZC-3BG256C LCMXO3D-4300ZC-2BG256I LCMXO3D-4300ZC-3BG256I LCMXO3D-9400HC-5SG72C LCMXO3D-9400HC-6SG72C LCMXO3D-9400HC-5SG72I LCMXO3D-9400HC-6SG72I LCMXO3D-9400HC-5BG256C 4300 4300 4300 4300 4300 4300 4300 4300 4300 4300 4300 4300 4300 4300 4300 4300 9400 9400 9400 9400 9400 2.5 V / 3.3 V 2.5 V / 3.3 V 2.5 V / 3.3 V 2.5 V / 3.3 V 2.5 V / 3.3 V 2.5 V / 3.3 V 2.5 V / 3.3 V 2.5 V / 3.3 V 2.5 V / 3.3 V 2.5 V / 3.3 V 2.5 V / 3.3 V 2.5 V / 3.3 V 2.5 V / 3.3 V 2.5 V / 3.3 V 2.5 V / 3.3 V 2.5 V / 3.3 V 2.5 V / 3.3 V 2.5 V / 3.3 V 2.5 V / 3.3 V 2.5 V / 3.3 V 2.5 V / 3.3 V 5 6 5 6 5 6 5 6 2 3 2 3 2 3 2 3 5 6 5 6 5 Halogen-Free QFN Halogen-Free QFN Halogen-Free QFN Halogen-Free QFN Halogen-Free caBGA Halogen-Free caBGA Halogen-Free caBGA Halogen-Free caBGA Halogen-Free QFN Halogen-Free QFN Halogen-Free QFN Halogen-Free QFN Halogen-Free caBGA Halogen-Free caBGA Halogen-Free caBGA Halogen-Free caBGA Halogen-Free QFN Halogen-Free QFN Halogen-Free QFN Halogen-Free QFN Halogen-Free caBGA 72 72 72 72 256 256 256 256 72 72 72 72 256 256 256 256 72 72 72 72 256 COM COM IND IND COM COM IND IND COM COM IND IND COM COM IND IND COM COM IND IND COM LCMXO3D-9400HC-6BG256C LCMXO3D-9400HC-5BG256I LCMXO3D-9400HC-6BG256I LCMXO3D-9400HC-5BG400C LCMXO3D-9400HC-6BG400C LCMXO3D-9400HC-5BG400I LCMXO3D-9400HC-6BG400I LCMXO3D-9400HC-5BG484C LCMXO3D-9400HC-6BG484C 9400 9400 9400 9400 9400 9400 9400 9400 9400 2.5 V / 3.3 V 2.5 V / 3.3 V 2.5 V / 3.3 V 2.5 V / 3.3 V 2.5 V / 3.3 V 2.5 V / 3.3 V 2.5 V / 3.3 V 2.5 V / 3.3 V 2.5 V / 3.3 V 6 5 6 5 6 5 6 5 6 Halogen-Free caBGA Halogen-Free caBGA Halogen-Free caBGA Halogen-Free caBGA Halogen-Free caBGA Halogen-Free caBGA Halogen-Free caBGA Halogen-Free caBGA Halogen-Free caBGA 256 256 256 400 400 400 400 484 484 COM IND IND COM COM IND IND COM COM LCMXO3D-9400HC-5BG484I LCMXO3D-9400HC-6BG484I LCMXO3D-9400ZC-2SG72C LCMXO3D-9400ZC-3SG72C LCMXO3D-9400ZC-2SG72I LCMXO3D-9400ZC-3SG72I LCMXO3D-9400ZC-2BG256C LCMXO3D-9400ZC-3BG256C LCMXO3D-9400ZC-2BG256I LCMXO3D-9400ZC-3BG256I LCMXO3D-9400ZC-2BG400C LCMXO3D-9400ZC-3BG400C LCMXO3D-9400ZC-2BG400I LCMXO3D-9400ZC-3BG400I 9400 9400 9400 9400 9400 9400 9400 9400 9400 9400 9400 9400 9400 9400 2.5 V / 3.3 V 2.5 V / 3.3 V 2.5 V / 3.3 V 2.5 V / 3.3 V 2.5 V / 3.3 V 2.5 V / 3.3 V 2.5 V / 3.3 V 2.5 V / 3.3 V 2.5 V / 3.3 V 2.5 V / 3.3 V 2.5 V / 3.3 V 2.5 V / 3.3 V 2.5 V / 3.3 V 2.5 V / 3.3 V 5 6 2 3 2 3 2 3 2 3 2 3 2 3 Halogen-Free caBGA Halogen-Free caBGA Halogen-Free QFN Halogen-Free QFN Halogen-Free QFN Halogen-Free QFN Halogen-Free caBGA Halogen-Free caBGA Halogen-Free caBGA Halogen-Free caBGA Halogen-Free caBGA Halogen-Free caBGA Halogen-Free caBGA Halogen-Free caBGA 484 484 72 72 72 72 256 256 256 256 400 400 400 400 IND IND COM COM IND IND COM COM IND IND COM COM IND IND © 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 86 FPGA-DS-02026-1.1 MachXO3D Device Family Data Sheet 5.4. MachXO3D Low Power Automotive Grade Devices, Halogen Free (RoHS) Packaging Part Number LUTs Supply Voltage Speed Package Leads Temp. LAMXO3D-4300HC-5BG256E LAMXO3D-9400ZC-2BG256E LAMXO3D-9400HE-5BG256E LAMXO3D-9400ZC-2BG484E LAMXO3D-9400HE-5BG484E 4300 9400 9400 9400 9400 2.5 V / 3.3 V 2.5 V / 3.3 V 1.2 V 2.5 V / 3.3 V 1.2 V 5 2 5 2 5 Halogen-Free caBGA Halogen-Free caBGA Halogen-Free caBGA Halogen-Free caBGA Halogen-Free caBGA 256 256 256 484 484 AUTO AUTO AUTO AUTO AUTO © 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02026-1.1 87 MachXO3D Device Family Data Sheet References A variety of technical notes for the MachXO3D family are available on the Lattice website.  MachXO3D sysCLOCK PLL Design and Usage Guide (FPGA-TN-02070)  Implementing High-Speed Interfaces with MachXO3D Devices Usage Guide (FPGA-TN-02065)  MachXO3D sysI/O Usage Guide (FPGA-TN-02068)  MachXO3D Programming and Configuration Usage Guide (FPGA-TN-02069)  PCB Layout Recommendations for BGA Packages (FPGA-TN-02024)  Minimizing System Interruption During Configuration Using TransFR Technology (TN1087)  Boundary Scan Testability with Lattice sysI/O Capability (AN8066)  Thermal Management document (FPGA-TN-02044)  Lattice Design Tools © 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 88 FPGA-DS-02026-1.1 MachXO3D Device Family Data Sheet Revision History Revision 1.1, September 2020 Section Change Summary Introduction    Added Automotive (HE) device information. Updated the on-chip oscillator item under Enhanced System Level Support in Features. Updated Table 1.1. MachXO3D Family Selection Guide.  Added MachXO3D-9400 Core VCC and Temperature values for Automotive.  Updated MachXO3D-9400 484-ball caBGA package information.  Added footnote. DC and Switching Characteristics   Updated the MachXO3D External Switching Characteristics – HE/HC Devices section heading. Updated following tables:  Table 3.2. Recommended Operating Conditions  Table 3.4. Power-On Reset Voltage Levels  Table 3.6. Programming/Erase Specifications  Table 3.7. DC Electrical Characteristics  Table 3.8. Static Supply Current  Table 3.9. Programming and Erase Supply Current  Table 3.11. sysI/O Single-Ended DC Electrical Characteristics  Table 3.17. MIPI D-PHY Output DC Conditions  Table 3.21. MachXO3D External Switching Characteristics – HE/HC Devices  Table 3.22. MachXO3D External Switching Characteristics – ZC Devices  Table 3.23. sysCLOCK PLL Timing  Table 3.25. JTAG Port Timing Specifications  Table 3.26. sysCONFIG Port Timing Specifications Ordering Information   Added HE Supply Voltage in MachXO3D Part Number Description. Updated figure caption to Figure 5.1. Top Markings for Commercial and Industrial Grade Devices. Added Figure 5.2. Top Markings for Automotive Grade Devices. Updated MachXO3D Low Power Commercial and Industrial Grade Devices, Halogen Free (RoHS) Packaging section. Added MachXO3D Low Power Automotive Grade Devices, Halogen Free (RoHS) Packaging section.    — Minor formatting/style adjustments Revision 1.0, November 2019 Section Change Summary All Production release. © 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02026-1.1 89 www.latticesemi.com