MachXO3 Family
Data Sheet
FPGA-DS-02032-3.1
July 2021
MachXO3 Family Data Sheet
Data Sheet
Disclaimers
Lattice makes no warranty, representation, or guarantee regarding the accuracy of information contained in this document or the suitability of its
products for any particular purpose. All information herein is provided AS IS and with all faults, and all risk associated with such information is entirely
with Buyer. Buyer shall not rely on any data and performance specifications or parameters provided herein. Products sold by Lattice have been
subject to limited testing and it is the Buyer's responsibility to independently determine the suitability of any products and to test and verify the
same. No Lattice products should be used in conjunction with mission- or safety-critical or any other application in which the failure of Lattice’s
product could create a situation where personal injury, death, severe property or environmental damage may occur. The information provided in this
document is proprietary to Lattice Semiconductor, and Lattice reserves the right to make any changes to the information in this document or to any
products at any time without notice.
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
2
FPGA-DS-02032-3.1
MachXO3 Family Data Sheet
Data Sheet
Contents
Acronyms in This Document ................................................................................................................................................. 7
1. Introduction .................................................................................................................................................................. 9
1.1.
Features ............................................................................................................................................................ 10
1.1.1. Solutions ....................................................................................................................................................... 10
1.1.2. Flexible Architecture .................................................................................................................................... 10
1.1.3. Advanced Packaging ..................................................................................................................................... 10
1.1.4. Pre-Engineered Source Synchronous I/O ..................................................................................................... 10
1.1.5. High Performance, Flexible I/O Buffer ......................................................................................................... 10
1.1.6. Flexible On-Chip Clocking ............................................................................................................................. 10
1.1.7. Non-volatile, Multi-time Programmable ...................................................................................................... 10
1.1.8. TransFR Reconfiguration .............................................................................................................................. 10
1.1.9. Enhanced System Level Support .................................................................................................................. 10
1.1.10. Applications .................................................................................................................................................. 10
1.1.11. Low Cost Migration Path .............................................................................................................................. 10
2. Architecture ................................................................................................................................................................ 12
2.1.
Architecture Overview ...................................................................................................................................... 12
2.2.
PFU Blocks ......................................................................................................................................................... 14
2.2.1. Slices ............................................................................................................................................................. 14
2.2.2. Modes of Operation ..................................................................................................................................... 16
2.2.3. RAM Mode ................................................................................................................................................... 16
2.2.4. ROM Mode ................................................................................................................................................... 16
2.3.
Routing .............................................................................................................................................................. 17
2.4.
Clock/Control Distribution Network .................................................................................................................. 17
2.4.1. sysCLOCK Phase Locked Loops (PLLs) ........................................................................................................... 19
2.5.
sysMEM Embedded Block RAM Memory .......................................................................................................... 22
2.5.1. sysMEM Memory Block ................................................................................................................................ 22
2.5.2. Bus Size Matching......................................................................................................................................... 22
2.5.3. RAM Initialization and ROM Operation ........................................................................................................ 22
2.5.4. Memory Cascading ....................................................................................................................................... 22
2.5.5. Single, Dual, Pseudo-Dual Port and FIFO Modes .......................................................................................... 23
2.5.6. FIFO Configuration ....................................................................................................................................... 24
2.5.7. Memory Core Reset...................................................................................................................................... 24
2.5.8. EBR Asynchronous Reset .............................................................................................................................. 25
2.6.
Programmable I/O Cells (PIC) ............................................................................................................................ 26
2.7.
PIO ..................................................................................................................................................................... 27
2.7.1. Input Register Block ..................................................................................................................................... 28
2.7.2. Output Register Block................................................................................................................................... 28
2.7.3. Tri-state Register Block................................................................................................................................. 29
2.8.
Input Gearbox ................................................................................................................................................... 29
2.9.
Output Gearbox ................................................................................................................................................ 31
2.10. sysI/O Buffer ..................................................................................................................................................... 33
2.10.1. Typical I/O Behavior during Power-up ......................................................................................................... 33
2.10.2. Supported Standards .................................................................................................................................... 33
2.10.3. sysI/O Buffer Banks ...................................................................................................................................... 35
2.11. Hot Socketing .................................................................................................................................................... 36
2.12. On-chip Oscillator.............................................................................................................................................. 36
2.13. Embedded Hardened IP Functions .................................................................................................................... 36
2.13.1. Hardened I2C IP Core .................................................................................................................................... 37
2.13.2. Hardened SPI IP Core.................................................................................................................................... 38
2.13.3. Hardened Timer/Counter ............................................................................................................................. 40
2.14. User Flash Memory (UFM) ................................................................................................................................ 41
2.15. Standby Mode and Power Saving Options ........................................................................................................ 41
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02032-3.1
3
MachXO3 Family Data Sheet
Data Sheet
2.16. Power On Reset ................................................................................................................................................. 42
2.17. Configuration and Testing ................................................................................................................................. 42
2.17.1. IEEE 1149.1-Compliant Boundary Scan Testability .......................................................................................42
2.17.2. Device Configuration ....................................................................................................................................42
2.18. TraceID .............................................................................................................................................................. 44
2.19. Density Shifting ................................................................................................................................................. 44
2.20. MachXO3LF to MachXO3L Low Cost Migration Path ........................................................................................ 44
3. DC and Switching Characteristics................................................................................................................................ 45
3.1.
Absolute Maximum Rating ................................................................................................................................ 45
3.2.
Recommended Operating Conditions ............................................................................................................... 45
3.3.
Power Supply Ramp Rates ................................................................................................................................. 45
3.4.
Power-On-Reset Voltage Levels ........................................................................................................................ 46
3.5.
Hot Socketing Specifications ............................................................................................................................. 46
3.6.
Programming/Erase Specifications ................................................................................................................... 46
3.7.
ESD Performance ............................................................................................................................................... 47
3.8.
DC Electrical Characteristics .............................................................................................................................. 47
3.9.
Static Supply Current – C/E Devices .................................................................................................................. 48
3.10. Programming and Erase Supply Current – C/E Devices ..................................................................................... 49
3.11. sysI/O Recommended Operating Conditions ..................................................................................................... 49
3.12. sysI/O Single-Ended DC Electrical Characteristics .............................................................................................. 50
3.13. sysI/O Differential Electrical Characteristics ..................................................................................................... 51
3.13.1. LVDS ..............................................................................................................................................................51
3.13.2. LVDS Emulation ............................................................................................................................................51
3.13.3. BLVDS ...........................................................................................................................................................53
3.13.4. LVPECL ..........................................................................................................................................................54
3.13.5. MIPI D-PHY Emulation ..................................................................................................................................55
3.14. Typical Building Block Function Performance – C/E Devices ............................................................................. 57
3.14.1. Pin-to-Pin Performance (LVCMOS25 12 mA Drive) ......................................................................................57
3.14.2. Register-to-Register Performance ................................................................................................................57
3.15. Derating Logic Timing ........................................................................................................................................ 58
3.16. Maximum sysI/O Buffer Performance ............................................................................................................... 58
3.17. MachXO3L/LF External Switching Characteristics – C/E Devices ...................................................................... 58
3.18. sysCLOCK PLL Timing ......................................................................................................................................... 68
3.19. Oscillator Output Frequency ............................................................................................................................. 69
3.20. NVCM/Flash Download Time ............................................................................................................................ 70
3.21. JTAG Port Timing Specifications ........................................................................................................................ 70
3.22. sysCONFIG Port Timing Specifications .............................................................................................................. 71
3.23. I2C Port Timing Specifications ............................................................................................................................ 72
3.24. SPI Port Timing Specifications ........................................................................................................................... 72
3.25. Switching Test Conditions ................................................................................................................................. 72
4. Signal Descriptions ...................................................................................................................................................... 74
4.1.
Pin Information Summary ................................................................................................................................. 75
5. MachXO3 Part Number Description ........................................................................................................................... 80
6. Ordering Information .................................................................................................................................................. 81
6.1.
MachXO3L Ultra Low Power Commercial and Industrial Grade Devices, Halogen Free (RoHS) Packaging ...... 81
6.2.
MachXO3LF Ultra Low Power Commercial and Industrial Grade Devices, Halogen Free (RoHS) Packaging .... 84
6.3.
MachXO3LF Ultra Low Power Automotive Grade Devices, Halogen Free (RoHS) Packaging ............................ 87
References .......................................................................................................................................................................... 88
Revision History .................................................................................................................................................................. 89
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
4
FPGA-DS-02032-3.1
MachXO3 Family Data Sheet
Data Sheet
Figures
Figure 2.1. Top View of the MachXO3L/LF-1300 Device .................................................................................................... 12
Figure 2.2. Top View of the MachXO3L/LF-4300 Device .................................................................................................... 13
Figure 2.3. PFU Block Diagram ............................................................................................................................................ 14
Figure 2.4. Slice Diagram .................................................................................................................................................... 15
Figure 2.5. Primary Clocks for MachXO3L/F Devices .......................................................................................................... 18
Figure 2.6. Secondary High Fanout Nets for MachXO3L/F Devices .................................................................................... 19
Figure 2.7. PLL Diagram ...................................................................................................................................................... 20
Figure 2.8. sysMEM Memory Primitives ............................................................................................................................. 23
Figure 2.9. Memory Core Reset .......................................................................................................................................... 25
Figure 2.10. EBR Asynchronous Reset (Including GSR) Timing Diagram ............................................................................. 25
Figure 2.11. Group of Four Programmable I/O Cells .......................................................................................................... 27
Figure 2.12. Output Register Block Diagram (PIO on the Left, Top and Bottom Edges) ..................................................... 29
Figure 2.13. Input Gearbox ................................................................................................................................................. 30
Figure 2.14. Output Gearbox .............................................................................................................................................. 32
Figure 2.15. MachXO3L/LF-1300 in 256 Ball Packages, MachXO3L/LF-2100, MachXO3L/LF-4300, MachXO3L/LF-6900 and
MachXO3L/LF-9400 Banks I/O Banks .............................................................................................................. 35
Figure 2.16. MachXO3L/LF-640 and MachXO3L/LF-1300 Banks ........................................................................................ 35
Figure 2.17. Embedded Function Block Interface ............................................................................................................... 37
Figure 2.18. I2C Core Block Diagram ................................................................................................................................... 37
Figure 2.19. SPI Core Block Diagram ................................................................................................................................... 39
Figure 2.20. Timer/Counter Block Diagram ........................................................................................................................ 40
Figure 3.1. LVDS Using External Resistors (LVDS25E) ......................................................................................................... 52
Figure 3.2. BLVDS Multi-point-Output Example ................................................................................................................. 53
Figure 3.3. Differential LVPECL ........................................................................................................................................... 54
Figure 3.4. MIPI D-PHY Input Using External Resistors ....................................................................................................... 55
Figure 3.5. MIPI D-PHY Output Using External Resistors .................................................................................................... 56
Figure 3.6.Receiver GDDR71_RX. Waveforms .................................................................................................................... 68
Figure 3.7. Transmitter GDDR71_TX. Waveforms .............................................................................................................. 68
Figure 3.8. JTAG Port Timing Waveforms ........................................................................................................................... 71
Figure 3.9. Output Test Load, LVTTL and LVCMOS Standards ............................................................................................ 73
Tables
Table 1.1. MachXO3L/LF Family Selection Guide ............................................................................................................... 11
Table 2.1. Resources and Modes Available per Slice .......................................................................................................... 14
Table 2.2. Slice Signal Descriptions ..................................................................................................................................... 15
Table 2.3. Number of Slices Required For Implementing Distributed RAM ....................................................................... 16
Table 2.4. PLL Signal Descriptions ....................................................................................................................................... 21
Table 2.5. sysMEM Block Configurations ............................................................................................................................ 22
Table 2.6. EBR Signal Descriptions ...................................................................................................................................... 23
Table 2.7. Programmable FIFO Flag Ranges ....................................................................................................................... 24
Table 2.8. PIO Signal List ..................................................................................................................................................... 27
Table 2.9. Input Gearbox Signal List ................................................................................................................................... 29
Table 2.10. Output Gearbox Signal List .............................................................................................................................. 31
Table 2.11. Supported Input Standards .............................................................................................................................. 34
Table 2.12. Supported Output Standards ........................................................................................................................... 34
Table 2.13. Available MCLK Frequencies ............................................................................................................................ 36
Table 2.14. I2C Core Signal Description ............................................................................................................................... 38
Table 2.15. SPI Core Signal Description .............................................................................................................................. 39
Table 2.16. Timer/Counter Signal Description .................................................................................................................... 40
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02032-3.1
5
MachXO3 Family Data Sheet
Data Sheet
Table 2.17. MachXO3L/LF Power Saving Features Description ..........................................................................................41
Table 3.1. Absolute Maximum Rating1, 2, 3 ..........................................................................................................................45
Table 3.2. Recommended Operating Conditions 1 ..............................................................................................................45
Table 3.3. Power Supply Ramp Rates .................................................................................................................................45
Table 3.4. Power-On Reset Voltage Levels .........................................................................................................................46
Table 3.5. Hot Socketing Specifications ..............................................................................................................................46
Table 3.6. Programming/Erase Specifications ....................................................................................................................46
Table 3.7. DC Electrical Characteristics ...............................................................................................................................47
Table 3.8. Static Supply Current – C/E Devices1, 2, 3, 6 ..........................................................................................................48
Table 3.9. Programming and Erase Supply Current – C/E Devices1, 2, 3, 4.............................................................................49
Table 3.10. sysI/O Recommended Operating Conditions ...................................................................................................49
Table 3.11. sysI/O Single-Ended DC Electrical Charateristics1, 2, 4 .......................................................................................50
Table 3.12. LVDS .................................................................................................................................................................51
Table 3.13. LVDS25E DC Conditions ....................................................................................................................................53
Table 3.14. BLVDS DC Condition .........................................................................................................................................54
Table 3.15. LVPECL DC Conditions ......................................................................................................................................55
Table 3.16. MIPI DC Conditions ..........................................................................................................................................56
Table 3.17. MIPI D-PHY Output DC Conditions ...................................................................................................................57
Table 3.18. Pin-to-Pin Performance (LVCMOS25 12 mA Drive) ..........................................................................................57
Table 3.19. Register-to-Register Performance....................................................................................................................57
Table 3.20. Maximum sysI/O Buffer Performance .............................................................................................................58
Table 3.21. MachXO3L/LF External Switching Characteristics – C/E Devices1, 2, 3, 4, 5, 6, 10 ...................................................58
Table 3.22. sysCLOCK PLL Timing ........................................................................................................................................68
Table 3.23. Oscillator Output Frequency ............................................................................................................................69
Table 3.24. NVCM/Flash Download Time ...........................................................................................................................70
Table 3.25. JTAG Port Timing Specifications .......................................................................................................................70
Table 3.26. sysCONFIG Port Timing Specifications .............................................................................................................71
Table 3.27. I2C Port Timing Specification ............................................................................................................................72
Table 3.28. SPI Port Timing Specifications ..........................................................................................................................72
Table 3.29. Test Fixture Required Components, Non-Terminated Interfaces ....................................................................73
Table 4.1. Signal Descriptions .............................................................................................................................................74
Table 4.2. MachXO3L/LF-640 and MachXO3L/LF-1300 Pin Summary ................................................................................75
Table 4.3. MachXO3L/LF-2100 Pin Summary ......................................................................................................................76
Table 4.4. MachXO3L/LF-4300 Pin Summary ......................................................................................................................77
Table 4.5. MachXO3L/LF-6900 Pin Summary ......................................................................................................................78
Table 4.6. MachXO3L/LF-9400C Pin Summary ...................................................................................................................79
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
6
FPGA-DS-02032-3.1
MachXO3 Family Data Sheet
Data Sheet
Acronyms in This Document
A list of acronyms used in this document.
Acronym
AES
BGA
caBGA
csfBGA
CE
CLK
CMOS
DDR
EBR
ECDSA
ECLK
ESB
FCIN
FCO
I2C
IP
I/O
JTAG
LED
LSR
LUT
LVCMOS
LVDS
LVPECL
LVTTL
MIPI
MLVDS
NVCM
PCI
PCLK
PDPR
PFU
PIC
PIO
PLD
PLL
RAM
ROM
SDR
SHA
SPI
Definition
Advanced Encryption Standard
Ball Grid Array
ChipArray Ball Grill Array
Chip Scale Flip-Chip Ball Grid Array
Clock Enable
System clock
Complementary Metal Oxide Semiconductor
Double Data Rate
Embedded Block RAM
Elliptic Curve Digital Signature Algorithm
Edge Clock
Embedded Security Block
Fast Carry In
Fast Carry Out
Inter-Integrated Circuit
Intellectual Property
Input/Output
Joint Test Action Group
Light-emitting Diode
Local Set/Reset
Look-Up Table
Low-Voltage CMOS
Low-Voltage Differential Signaling
Low-Voltage Positive/Pseudo Emitter-Coupled Logic
Low Voltage Transistor to Transistor Logic
Mobile Industry Processor Interface
Multipoint Low-Voltage Differential Signaling
Non Volatile Configuration Memory
Peripheral Component Interconnect
Primary Clock
Pseudo Dual Port RAM
Programmable Functional Unit
Programmable Interface Controllers
Programmed Input/Output
Programmable Logic Device
Phase Locked Loop
Random Access Memory
Read-only Memory
Single Data Rate
Secure Hash Algorithm
Serial Peripheral Interface
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02032-3.1
7
MachXO3 Family Data Sheet
Data Sheet
Acronym
SPR
SRAM
TransFR™
UFM
WLCSP
Definition
Single Port Random Access Memory
Static Random Access Memory
Transparent Field Reconfiguration
User Flash Memory
Wafer Level Chip Scale Package
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
8
FPGA-DS-02032-3.1
MachXO3 Family Data Sheet
Data Sheet
1. Introduction
MachXO3™ device family is an Ultra-Low Density
family that supports the most advanced programmable
bridging and I/O expansion. It has the breakthrough
I/O density and the lowest cost per I/O. The device I/O
features have the integrated support for latest industry
standard I/O.
The MachXO3L/LF family of low power, instant-on,
non-volatile PLDs has five devices with densities
ranging from 640 to 9400 Look-Up Tables (LUTs). In
addition to LUT-based, low-cost programmable logic
these devices feature Embedded Block RAM (EBR),
Distributed RAM, Phase Locked Loops (PLLs),
pre-engineered source synchronous I/O support,
advanced configuration support including dual-boot
capability and hardened versions of commonly used
functions such as SPI controller, I2C controller and
timer/counter. MachXO3LF devices also support User
Flash Memory (UFM). These features allow these
devices to be used in low cost, high volume
applications such as consumer electronics, compute
and storage, wireless communications, industrial
control, and automotive systems.
The MachXO3L/LF devices are designed on a 65 nm
non-volatile low power process. The device
architecture has several features such as
programmable low swing differential I/O and the
ability to turn off I/O banks, on-chip PLLs and
oscillators dynamically. These features help manage
static and dynamic power consumption resulting in low
static power for all members of the family.
The MachXO3L/LF devices are available in two versions
C and E with two speed grades: -5 and -6, with -6 being
the fastest. C devices have an internal linear voltage
regulator which supports external VCC supply voltages
of 3.3 V or 2.5 V. E devices only accept 1.2 V as the
external VCC supply voltage. With the exception of
power supply voltage both C and E are functionally
compatible with each other.
The MachXO3L/LF devices offer enhanced I/O features
such as drive strength control, slew rate control, PCI
compatibility, bus-keeper latches, pull-up resistors,
pull-down resistors, open drain outputs and hot
socketing. Pull-up, pull-down and bus-keeper features
are controllable on a “per-pin” basis. A userprogrammable internal oscillator is included in
MachXO3L/LF devices. The clock output from this
oscillator may be divided by the timer/counter for use
as clock input in functions such as LED control,
keyboard scanner and similar state machines.
The MachXO3L/LF devices also provide flexible,
reliable and secure configuration from on-chip
NVCM/Flash. These devices can also configure
themselves from external SPI Flash or be configured by
an external master through the JTAG test access port
or through the I2C port. Additionally, MachXO3L/LF
devices support dual-boot capability (using external
Flash memory) and remote field upgrade (TransFR)
capability.
Lattice provides a variety of design tools that allow
complex designs to be efficiently implemented using
the MachXO3L/LF family of devices. Popular logic
synthesis tools provide synthesis library support for
MachXO3L/LF. Lattice design tools use the synthesis
tool output along with the user-specified preferences
and constraints to place and route the design in the
MachXO3L/LF device. These tools extract the timing
from the routing and back-annotate it into the design
for timing verification.
Lattice provides many pre-engineered IP (Intellectual
Property) LatticeCORE™ modules, including a number
of reference designs licensed free of charge, optimized
for the MachXO3L/LF PLD family. By using these
configurable soft core IP cores as standardized blocks,
users are free to concentrate on the unique aspects of
their design, increasing their productivity.
The MachXO3L/LF PLDs are available in a broad range
of advanced halogen-free packages ranging from the
space saving 2.5 x 2.5 mm WLCSP to the 19 x 19 mm
caBGA. MachXO3L/LF devices support density
migration within the same package. Table 1.1 shows
the LUT densities, package and I/O options, along with
other key parameters.
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02032-3.1
9
MachXO3 Family Data Sheet
Data Sheet
1.1.
1.1.1.
•
•
•
Features
Solutions
Smallest footprint, lowest power, high data
throughput bridging solutions for mobile
applications
Optimized footprint, logic density, I/O count, I/O
performance devices for I/O management and
logic applications
High I/O logic, lowest cost I/O, high I/O devices for
I/O expansion applications
1.1.6.
•
•
•
•
•
Logic Density ranging from 64 to 9.4 k LUT4
High I/O to LUT ratio with up to 384 I/O pins
1.1.3.
•
•
•
Flexible Architecture
Advanced Packaging
0.4 mm pitch: 1 k to 4 k densities in very small
footprint WLCSP (2.5 mm × 2.5 mm to 3.8 mm ×
3.8 mm) with 28 to 63 I/O
0.5 mm pitch: 640 to 9.4 k LUT densities in 6 mm x
6 mm to 10 mm x 10 mm BGA packages with up to
281 I/O
0.8 mm pitch: 1 k to 9.4 k densities with up to 384
I/O in BGA packages
•
•
•
•
•
•
•
•
•
DDR registers in I/O cells
Dedicated gearing logic
7:1 Gearing for Display I/O
Generic DDR, DDRx2, DDRx4
1.1.5.
•
•
•
•
•
Pre-Engineered Source Synchronous
I/O
High Performance, Flexible I/O
Buffer
Programmable sysI/O™ buffer supports wide
range of interfaces:
• LVCMOS 3.3/2.5/1.8/1.5/1.2
• LVTTL
• LVDS, Bus-LVDS, MLVDS, LVPECL
• MIPI D-PHY Emulated
• Schmitt trigger inputs, up to 0.5 V hysteresis
Ideal for I/O bridging applications
I/O support hot socketing
On-chip differential termination
Programmable pull-up or pull-down mode
•
•
•
•
•
TransFR Reconfiguration
In-field logic update while I/O holds the system
state
1.1.9.
•
Non-volatile, Multi-time
Programmable
Instant-on
• Powers up in microseconds
Optional dual boot with external SPI memory
Single-chip, secure solution
Programmable through JTAG, SPI or I2C
MachXO3L includes multi-time programmable
NVCM
MachXO3LF reconfigurable Flash includes 100,000
write/erase cycle for commercial/industrial
devices and 10,000 for automotive devices
• Supports background programming of non
volatile memory
1.1.8.
•
1.1.4.
Eight primary clocks
Up to two edge clocks for high-speed I/O
interfaces (top and bottom sides only)
Up to two analog PLLs per device with fractional-n
frequency synthesis
• Wide input frequency range (7 MHz to
400 MHz).
1.1.7.
•
1.1.2.
Flexible On-Chip Clocking
Enhanced System Level Support
On-chip hardened functions: SPI, I2C,
timer/counter
On-chip oscillator with 5.5% accuracy for
commercial/industrial devices
Unique TraceID for system tracking
Single power supply with extended operating
range
IEEE Standard 1149.1 boundary scan
IEEE 1532 compliant in-system programming
1.1.10. Applications
•
•
•
•
•
Consumer Electronics
Compute and Storage
Wireless Communications
Industrial Control Systems
Automotive System
1.1.11. Low Cost Migration Path
•
•
Migration from the Flash based MachXO3LF to the
NVCM based MachXO3L
Pin compatible and equivalent timing
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
10
FPGA-DS-02032-3.1
MachXO3 Family Data Sheet
Data Sheet
Table 1.1. MachXO3L/LF Family Selection Guide
Features
MachXO3L-640/
MachXO3LF-640
MachXO3L1300/
MachXO3LF1300
MachXO3L2100/
MachXO3LF2100
MachXO3L4300/
MachXO3LF4300
MachXO3L6900/
MachXO3LF6900
MachXO3L9400/
MachXO3LF9400
LUTs
Distributed RAM (kb)
EBR SRAM (kb)
UFM (kb, MachXO3LF only)
640
5
64
64
1300
10
64
64
2100
16
74
80
4300
34
92
96
69004
54
240
256
94004
73
432
448
C5
E6
Number of PLLs
I2C
SPI
Hardened
Timer/
Functions
Counter
Oscillator
MIPI D-PHY Support
Multi Time Programmable
NVCM
—
Yes
1
2
1
Yes
Yes
1
2
1
Yes
Yes
1
2
1
Yes
Yes
2
2
1
Yes
Yes
2
2
1
Yes
Yes
2
2
1
1
1
1
1
1
1
1
Yes
1
Yes
1
Yes
MachXO3L-640
MachXO3L-1300
MachXO3L-2100
Programmable Flash
MachXO3LF-640
1
Yes
MachXO3L9400
MachXO3LF9400
—
MachXO3LF2100
MachXO3LF2100
1
Yes
MachXO3L6900
MachXO3LF6900
Automotive Qualified
MachXO3LF1300
MachXO3LF1300
1
Yes
MachXO3L4300
MachXO3LF4300
MachXO3LF4300
—
—
Device
Options
Packages
36-ball WLCSP1
(2.5 mm x 2.5 mm, 0.4 mm)
49-ball WLCSP1
(3.2 mm x 3.2 mm, 0.4 mm)
81-ball WLCSP1
(3.8 mm x 3.8 mm, 0.4 mm)
121-ball csfBGA1
(6 mm x 6 mm, 0.5 mm)
256-ball csfBGA1
(9 mm x 9 mm, 0.5 mm)
324-ball csfBGA1
(10 mm x 10 mm, 0.5 mm)
256-ball caBGA
(14 mm x 14 mm, 0.8 mm)
324-ball caBGA2
(15 mm x 15 mm, 0.8 mm)
400-ball caBGA
(17 mm x 17 mm, 0.8 mm)
484-ball caBGA
(19 mm x 19 mm, 0.8 mm)
I/O
28
38
63
100
100
100
100
206
206
206
206
268
268
281
2062, 7
2062, 7
2062
2797
2797
279
3352
3352
2062, 7
206
2063
3353
3843
Notes:
1. Package is only available for E=1.2 V devices.
2. Package is only available for C=2.5 V/3.3 V devices in 6900 LUT and smaller densities.
3. Package is available for both E=1.2 V and C=2.5 V/3.3 V devices.
4. Refer to Power and Thermal Estimation and Management for MachXO3 Devices (FPGA-TN-02059) for determination of safe
ambient operating conditions.
5. High Performance with regulator – VCC = 2.5 V/3.3 V.
6. High Performance without regulator – VCC = 1.2 V.
7. Package is available for automotive devices.
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02032-3.1
11
MachXO3 Family Data Sheet
Data Sheet
2. Architecture
2.1.
Architecture Overview
The MachXO3L/LF family architecture contains an array of logic blocks surrounded by Programmable I/O (PIO). All logic
density devices in this family have sysCLOCK™ PLLs and blocks of sysMEM Embedded Block RAM (EBRs). Figure 2.1 and
Figure 2.2 show the block diagrams of the various family members.
Configuration
Flash 1/2
UFM/User Key
Embedded Function Block (EFB)
Embedded Security Block
sysCLOCK PLL
sysMEM Embedded
Block RAM (EBR)
PIOs Arranged into
sysI/O Banks
Programmable Function Units
with Distributed RAM (PFUs)
Figure 2.1. Top View of the MachXO3L/LF-1300 Device
Notes:
•
•
MachXO3L/LF-640 is similar to MachXO3L/LF-1300. MachXO3L/LF-640 has a lower LUT count.
MachXO3L devices have NVCM, MachXO3LF devices have Flash.
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
12
FPGA-DS-02032-3.1
MachXO3 Family Data Sheet
Data Sheet
Embedded
Function Block (EFB)
NVCM1/UFM
sysCLOCK PLL
Configuration
NVCM0/Flash
sysMEM Embedded
Block (EBR)
PIOs Arranged Into
sysIO Banks
Programmable Function Units
with Distributed RAM (PFUs)
Notes:
MachXO3L/LF-1300, MachXO3L/LF-2100, MachXO3L/LF-6900 and MachXO3L/LF-9400 are similar to MachXO3L/LF-4300. MachXO3L/LF-1300 has
a lower LUT count, one PLL, and seven EBR blocks. MachXO3L/LF-2100 has a lower LUT count, one PLL, and eight EBR blocks.
MachXO3L/LF-6900 has a higher LUT count, two PLLs, and 26 EBR blocks. MachXO3L/LF-9400 has a higher LUT count, two PLLs, and 48 E blocks.
MachXO3L devices have NVCM, MachXO3LF devices have Flash.
Figure 2.2. Top View of the MachXO3L/LF-4300 Device
The logic blocks, Programmable Functional Unit (PFU) and sysMEM EBR blocks, are arranged in a two-dimensional grid
with rows and columns. Each row has either the logic blocks or the EBR blocks. The PIO cells are located at the
periphery of the device, arranged in banks. The PFU contains the building blocks for logic, arithmetic, RAM, ROM, and
register functions. The PIOs utilize a flexible I/O buffer referred to as a sysI/O buffer that supports operation with a
variety of interface standards. The blocks are connected with many vertical and horizontal routing channel resources.
The place and route software tool automatically allocates these routing resources.
In the MachXO3L/LF family, the number of sysI/O banks varies by device. There are different types of I/O buffers on the
different banks. Refer to the details in later sections of this document. The sysMEM EBRs are large, dedicated fast
memory blocks. These blocks can be configured as RAM, ROM or FIFO. FIFO support includes dedicated FIFO pointer
and flag “hard” control logic to minimize LUT usage.
The MachXO3L/LF registers in PFU and sysI/O can be configured to be SET or RESET. After power up and device is
configured, the device enters into user mode with these registers SET/RESET according to the configuration set-ting,
allowing device entering to a known state for predictable system function.
The MachXO3L/LF architecture also provides up to two sysCLOCK Phase Locked Loop (PLL) blocks. These blocks are
located at the ends of the on-chip NVCM/Flash block. The PLLs have multiply, divide, and phase shifting capabilities
that are used to manage the frequency and phase relationships of the clocks.
MachXO3L/LF devices provide commonly used hardened functions such as SPI controller, I2C controller and timer/
counter.
MachXO3LF devices also provide User Flash Memory (UFM). These hardened functions and the UFM interface to the
core logic and routing through a WISHBONE interface. The UFM can also be accessed through the SPI, I2C and JTAG
ports.
Every device in the family has a JTAG port that supports programming and configuration of the device as well as access
to the user logic. The MachXO3L/LF devices are available for operation from 3.3 V, 2.5 V and 1.2 V power supplies,
providing easy integration into the overall system.
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02032-3.1
13
MachXO3 Family Data Sheet
Data Sheet
2.2.
PFU Blocks
The core of the MachXO3L/LF device consists of PFU blocks, which can be programmed to perform logic, arithmetic,
distributed RAM and distributed ROM functions. Each PFU block consists of four interconnected slices numbered 0 to 3
as shown in Figure 2.3. Each slice contains two LUTs and two registers. There are 53 inputs and 25 outputs associated
with each PFU block.
From
Routing
FCIN
LUT4 &
CARRY
LUT4 &
CARRY
LUT4 &
CARRY
D
LUT4 &
CARRY
Slice 1
Slice 0
FF/
Latch
LUT4 &
CARRY
D
FF/
Latch
D
FF/
Latch
LUT4 &
CARRY
LUT4 &
CARRY
Slice 2
D
FF/
Latch
FCO
Slice 3
D
D
FF/
Latch
FF/
Latch
LUT4 &
CARRY
D
FF/
Latch
D
FF/
Latch
To
Routing
Figure 2.3. PFU Block Diagram
2.2.1.
Slices
Slices 0-3 contain two LUT4s feeding two registers. Slices 0-2 can be configured as distributed memory. Table 2.1 shows
the capability of the slices in PFU blocks along with the operation modes they enable. In addition, each PFU contains
logic that allows the LUTs to be combined to perform functions such as LUT5, LUT6, LUT7 and LUT8. The control logic
performs set/reset functions (programmable as synchronous/ asynchronous), clock select, chip select and wider
RAM/ROM functions.
Table 2.1. Resources and Modes Available per Slice
Slice
Slice 0
Slice 1
Slice 2
Slice 3
PFU Block
Resources
2 LUT4s and 2 Registers
2 LUT4s and 2 Registers
2 LUT4s and 2 Registers
2 LUT4s and 2 Registers
Modes
Logic, Ripple, RAM, ROM
Logic, Ripple, RAM, ROM
Logic, Ripple, RAM, ROM
Logic, Ripple, ROM
Figure 2.4 shows an overview of the internal logic of the slice. The registers in the slice can be configured for positive/
negative and edge triggered or level sensitive clocks. All slices have 15 inputs from routing and one from the carrychain (from the adjacent slice or PFU). There are seven outputs: six for routing and one to carry-chain (to the adjacent
PFU). Table 2.2 lists the signals associated with Slices 0-3.
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
14
FPGA-DS-02032-3.1
MachXO3 Family Data Sheet
Data Sheet
Figure 2.4. Slice Diagram
Table 2.2. Slice Signal Descriptions
Function
Type
Signal Names
Input
Data signal
A0, B0, C0, D0
Input
Data signal
A1, B1, C1, D1
Input
Multi-purpose
M0/M1
Input
Control signal
CE
Input
Control signal
LSR
Input
Control signal
CLK
Input
Inter-PFU signal
FCIN
Output
Data signals
F0, F1
Output
Data signals
Q0, Q1
Output
Data signals
OFX0
Output
Data signals
OFX1
Output
Inter-PFU signal
FCO
Notes:
1. See Figure 2.3 for connection details.
2. Requires two PFUs.
Description
Inputs to LUT4
Inputs to LUT4
Multi-purpose input
Clock enable
Local set/reset
System clock
Fast carry in1
LUT4 output register bypass signals
Register outputs
Output of a LUT5 MUX
Output of a LUT6, LUT7, LUT82 MUX depending on the slice
Fast carry out1
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02032-3.1
15
MachXO3 Family Data Sheet
Data Sheet
2.2.2.
Modes of Operation
Each slice has up to four potential modes of operation: Logic, Ripple, RAM and ROM.
2.2.2.1. Logic Mode
In this mode, the LUTs in each slice are configured as 4-input combinatorial lookup tables. A LUT4 can have 16 possible
input combinations. Any four input logic functions can be generated by programming this lookup table. Since there are
two LUT4s per slice, a LUT5 can be constructed within one slice. Larger look-up tables such as LUT6, LUT7 and LUT8 can
be constructed by concatenating other slices. Note LUT8 requires more than four slices.
2.2.2.2. Ripple Mode
Ripple mode supports the efficient implementation of small arithmetic functions. In Ripple mode, the following
functions can be implemented by each slice:
• Addition 2-bit
• Subtraction 2-bit
• Add/subtract 2-bit using dynamic control
• Up counter 2-bit
• Down counter 2-bit
• Up/down counter with asynchronous clear
• Up/down counter with preload (sync)
• Ripple mode multiplier building block
• Multiplier support
• Comparator functions of A and B inputs
• A greater-than-or-equal-to B
• A not-equal-to B
• A less-than-or-equal-to B
Ripple mode includes an optional configuration that performs arithmetic using fast carry chain methods. In this
configuration (also referred to as CCU2 mode) two additional signals, Carry Generate and Carry Propagate, are
generated on a per-slice basis to allow fast arithmetic functions to be constructed by concatenating slices.
2.2.3.
RAM Mode
In this mode, a 16x4-bit distributed single port RAM (SPR) can be constructed by using each LUT block in Slice 0 and Slice
1 as a 16x1-bit memory. Slice 2 is used to provide memory address and control signals.
MachXO3L/LF devices support distributed memory initialization.
The Lattice design tools support the creation of a variety of different size memories. Where appropriate, the software
will construct these using distributed memory primitives that represent the capabilities of the PFU. Table 2.3 shows the
number of slices required to implement different distributed RAM primitives. For more information about using RAM in
MachXO3L/LF devices, please see Memory Usage Guide for MachXO3 Devices (TN1290).
Table 2.3. Number of Slices Required For Implementing Distributed RAM
Number of slices
SPR 16 x 4
3
PDPR 16 x 4
3
Note: SPR = Single Pot RAM, PDPR = Pseudo Dual Port RAM
2.2.4.
ROM Mode
ROM mode uses the LUT logic; hence, slices 0-3 can be used in ROM mode. Preloading is accomplished through the
programming interface during PFU configuration.
For more information on the RAM and ROM modes, please refer to Memory Usage Guide for MachXO3 Devices (FPGATN-02060).
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
16
FPGA-DS-02032-3.1
MachXO3 Family Data Sheet
Data Sheet
2.3.
Routing
There are many resources provided in the MachXO3L/LF devices to route signals individually or as buses with related
control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) segments.
The inter-PFU connections are made with three different types of routing resources: x1 (spans two PFUs), x2 (spans
three PFUs) and x6 (spans seven PFUs). The x1, x2, and x6 connections provide fast and efficient connections in the
horizontal and vertical directions.
The design tools take the output of the synthesis tool and places and routes the design. Generally, the place and route
tool is completely automatic, although an interactive routing editor is available to optimize the design.
2.4.
Clock/Control Distribution Network
Each MachXO3L/LF device has eight clock inputs (PCLK [T, C] [Banknum]_[2..0]) – three pins on the left side, two pins
each on the bottom and top sides and one pin on the right side. These clock inputs drive the clock nets. These eight
inputs can be differential or single-ended and may be used as general purpose I/O if they are not used to drive the
clock nets. When using a single ended clock input, only the PCLKT input can drive the clock tree directly.
The MachXO3L/LF architecture has three types of clocking resources: edge clocks, primary clocks and secondary high
fanout nets. MachXO3L/LF devices have two edge clocks each on the top and bottom edges. Edge clocks are used to
clock I/O registers and have low injection time and skew. Edge clock inputs are from PLL outputs, primary clock pads,
edge clock bridge outputs and CIB sources.
The eight primary clock lines in the primary clock network drive throughout the entire device and can provide clocks for
all resources within the device including PFUs, EBRs and PICs. In addition to the primary clock signals, MachXO3L/LF
devices also have eight secondary high fanout signals which can be used for global control signals, such as clock
enables, synchronous or asynchronous clears, presets, output enables, etc. Internal logic can drive the global clock
network for internally-generated global clocks and control signals.
The maximum frequency for the primary clock network is shown in the MachXO3L/LF External Switching Characteristics
table.
Primary clock signals for the MachXO3L/LF-1300 and larger devices are generated from eight 27:1 muxes The available
clock sources include eight I/O sources, 11 routing inputs, eight clock divider inputs and up to eight sysCLOCK PLL
outputs.
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02032-3.1
17
MachXO3 Family Data Sheet
Data Sheet
Up to 8
8
11
8
27:1
Dynamic
Clock
Enable
Primary Clock 0
27:1
Dynamic
Clock
Enable
Primary Clock 1
27:1
Dynamic
Clock
Enable
Primary Clock 2
27:1
Dynamic
Clock
Enable
Primary Clock 3
Dynamic
Clock
Enable
Primary Clock 4
Dynamic
Clock
Enable
Primary Clock 5
27:1
27:1
27:1
Dynamic
Clock
Enable
27:1
Primary Clock 6
Clock
Switch
27:1
Dynamic
Clock
Enable
27:1
Clock
Switch
Figure 2.5. Primary Clocks for MachXO3L/F Devices
Eight secondary high fanout nets are generated from eight 8:1 muxes as shown in Figure 2.6. One of the eight inputs to
the secondary high fanout net input mux comes from dual function clock pins and the remaining seven come from
internal routing. The maximum frequency for the secondary clock network is shown in MachXO3L/LF External Switching
Characteristics table.
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
18
FPGA-DS-02032-3.1
MachXO3 Family Data Sheet
Data Sheet
1
7
8:1
Secondary High
Fanout Net 0
8:1
Secondary High
Fanout Net 1
8:1
Secondary High
Fanout Net 2
8:1
Secondary High
Fanout Net 3
8:1
Secondary High
Fanout Net 4
8:1
Clock Pads
Secondary High
Fanout Net 5
8:1
Secondary High
Fanout Net 6
8:1
Secondary High
Fanout Net 7
Routing
Figure 2.6. Secondary High Fanout Nets for MachXO3L/F Devices
2.4.1.
sysCLOCK Phase Locked Loops (PLLs)
The sysCLOCK PLLs provide the ability to synthesize clock frequencies. All MachXO3L/LF devices have one or more
sysCLOCK PLL. CLKI is the reference frequency input to the PLL and its source can come from an external I/O pin or from
internal routing. CLKFB is the feedback signal to the PLL which can come from internal routing or an external I/O pin.
The feedback divider is used to multiply the reference frequency and thus synthesize a higher frequency clock output.
The MachXO3L/LF sysCLOCK PLLs support high resolution (16-bit) fractional-N synthesis. Fractional-N frequency
synthesis allows the user to generate an output clock which is a non-integer multiple of the input frequency. For more
information about using the PLL with Fractional-N synthesis, please see MachXO3 sysCLOCK PLL Design and Usage
Guide (FPGA-TN-02058).
Each output has its own output divider, thus allowing the PLL to generate different frequencies for each output. The
output dividers can have a value from 1 to 128. The output dividers may also be cascaded together to generate low
frequency clocks. The CLKOP, CLKOS, CLKOS2, and CLKOS3 outputs can all be used to drive the MachXO3L/LF clock
distribution network directly or general purpose routing resources can be used.
The LOCK signal is asserted when the PLL determines it has achieved lock and de-asserted if a loss of lock is detected. A
block diagram of the PLL is shown in Figure 2.7.
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02032-3.1
19
MachXO3 Family Data Sheet
Data Sheet
The setup and hold times of the device can be improved by programming a phase shift into the CLKOS, CLKOS2, and
CLKOS3 output clocks which will advance or delay the output clock with reference to the CLKOP output clock.
This phase shift can be either programmed during configuration or can be adjusted dynamically. In dynamic mode, the
PLL may lose lock after a phase adjustment on the output used as the feedback source and not relock until the t LOCK
parameter has been satisfied.
The MachXO3L/LF also has a feature that allows the user to select between two different reference clock sources
dynamically. This feature is implemented using the PLLREFCS primitive. The timing parameters for the PLL are shown in
the sysCLOCK PLL Timing table.
The MachXO3L/LF PLL contains a WISHBONE port feature that allows the PLL settings, including divider values, to be
dynamically changed from the user logic. When using this feature the EFB block must also be instantiated in the design
to allow access to the WISHBONE ports. Similar to the dynamic phase adjustment, when PLL settings are updated
through the WISHBONE port the PLL may lose lock and not relock until the tLOCK parameter has been satisfied. The
timing parameters for the PLL are shown in the sysCLOCK PLL Timing table.
For more details on the PLL and the WISHBONE interface, see MachXO3 sysCLOCK PLL Design and Usage Guide (FPGATN-02058).
DPHSRC
PHASESEL[1:0]
Dynamic
Phase
Adjust
PHASEDIR
PHASESTEP
STDBY
A0
CLKOP
Divider
(1 - 128)
Phase
Adjust/
Edge Trim
A2
Mux
ClkEn
Synch
B0
CLKOS
Divider
(1 - 128)
Phase
Adjust/
Edge Trim
B2
Mux
ClkEn
Synch
C0
CLKOS2
Divider
(1 - 128)
C2
Mux
ClkEn
Synch
D2
Mux
ClkEn
Synch
CLKOP
REFCLK
CLKI
CLKFB
REFCLK
Divider
M (1 - 40)
Phase detector,
VCO, and
loop filter.
FBKSEL
Fractional-N
Synthesizer
FBKCLK
Divider
N (1 - 40)
D0
Internal Feedback
D1
Mux
CLKOS
CLKOS2
Phase
Adjust
CLKOS3
Divider
(1 - 128)
CLKOS3
Phase
Adjust
CLKOP, CLKOS, CLKOS2, CLKOS3
LOCK
4
RST, RESETM, RESETC, RESETD
Lock
Detect
ENCLKOP, ENCLKOS, ENCLKOS2, ENCLKOS3
PLLCLK, PLLRST, PLLSTB, PLLWE, PLLDATI[7:0], PLLADDR[4:0]
PLLDATO[7:0] , PLLACK
Figure 2.7. PLL Diagram
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
20
FPGA-DS-02032-3.1
MachXO3 Family Data Sheet
Data Sheet
Table 2.4 provides signal descriptions of the PLL block.
Table 2.4. PLL Signal Descriptions
Port Name
CLKI
CLKFB
PHASESEL[1:0]
PHASEDIR
PHASESTEP
CLKOP
CLKOS
CLKOS2
CLKOS3
LOCK
I/O
I
I
I
I
I
O
O
O
O
O
DPHSRC
STDBY
RST
RESETM
RESETC
RESETD
ENCLKOP
ENCLKOS
ENCLKOS2
ENCLKOS3
PLLCLK
PLLRST
PLLSTB
PLLWE
PLLADDR [4:0]
PLLDATI [7:0]
PLLDATO [7:0]
PLLACK
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
O
O
Description
Input clock to PLL
Feedback clock
Select which output is affected by Dynamic Phase adjustment ports
Dynamic Phase adjustment direction
Dynamic Phase step – toggle shifts VCO phase adjust by one step.
Primary PLL output clock (with phase shift adjustment)
Secondary PLL output clock (with phase shift adjust)
Secondary PLL output clock2 (with phase shift adjust)
Secondary PLL output clock3 (with phrase shift adjust)
PLL LOCK, asynchronous signal. Active high indicates PLL is locked to input and
feedback signals.
Dynamic Phase source – ports or WISHBONE is active
Standby signal to power down the PLL
PLL reset without resetting the M-driver. Active high reset.
PLL rest – includes resetting the M-divider. Active high reset.
Reset for CLKOS2 output divider only. Active high reset.
Reset for CLKOS3 output divider only. Active high reset.
Enable PLL output CLKOP
Enable PLL output CLKOS when port is active
Enable PLL output CLKOS2 when port is active
Enable PLL output CLKOS3 when port is active
PLL data bus clock input signal
PLL data bus reset. This resets only the data bus not any register values.
PLL data bus strobe signal
PLL data bus write enable signal
PLL data bus address
PLL data bus data input
PLL data bus data output
PLL data bus acknowledge signal
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02032-3.1
21
MachXO3 Family Data Sheet
Data Sheet
2.5.
sysMEM Embedded Block RAM Memory
The MachXO3L/LF devices contain sysMEM Embedded Block RAMs (EBRs). The EBR consists of a 9-Kbit RAM, with
dedicated input and output registers. This memory can be used for a wide variety of purposes including data buffering,
PROM for the soft processor and FIFO.
2.5.1.
sysMEM Memory Block
The sysMEM block can implement single port, dual port, pseudo dual port, or FIFO memories. Each block can be used in
a variety of depths and widths as shown in Table 2.5.
Table 2.5. sysMEM Block Configurations
Memory Mode
Single Port
True Dual Port
Pseudo Dual Port
FIFO
2.5.2.
Configurations
8,192 x 1
4,096 x 2
2,048 x 4
1,024 x 9
8,192 x 1
4,096 x 2
2,048 x 4
1,024 x 9
8,192 x 1
4,096 x 2
2,048 x 4
1,024 x 9
512 x 18
8,192 x 1
4,096 x 2
2,048 x 4
1,024 x 9
512 x 18
Bus Size Matching
All of the multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB word
0 to MSB word 0, LSB word 1 to MSB word 1, and so on. Although the word size and number of words for each port
varies, this mapping scheme applies to each port.
2.5.3.
RAM Initialization and ROM Operation
If desired, the contents of the RAM can be pre-loaded during device configuration. EBR initialization data can be loaded
from the NVCM or Configuration Flash.
MachXO3LF EBR initialization data can also be loaded from the UFM. To maximize the number of UFM bits, initialize
the EBRs used in your design to an all-zero pattern. Initializing to an all-zero pattern does not use up UFM bits.
MachXO3LF devices have been designed such that multiple EBRs share the same initialization memory space if they are
initialized to the same pattern.
By preloading the RAM block during the chip configuration cycle and disabling the write controls, the sysMEM block
can also be utilized as a ROM.
2.5.4.
Memory Cascading
Larger and deeper blocks of RAM can be created using EBR sysMEM Blocks. Typically, the Lattice design tools cascade
memory transparently, based on specific design inputs.
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
22
FPGA-DS-02032-3.1
MachXO3 Family Data Sheet
Data Sheet
2.5.5.
Single, Dual, Pseudo-Dual Port and FIFO Modes
Figure 2.8 shows the five basic memory configurations and their input/output names. In all the sysMEM RAM modes,
the input data and addresses for the ports are registered at the input of the memory array. The output data of the
memory is optionally registered at the memory array output.
DI[8:0]
DIA[8:0]
AD[12:0]
DI[8:0]
CLK
CE
OCE
EBR
DO[8:0]
EBR
RSTA
WEA
CSA[2:0]
OCEA
DOA[8:0]
RST
WE
CS[2:0]
Single-Port RAM
ADW[8:0]
DI[17:0]
BE[1:0]
CLKW
CEW
RST
ADB[12:0]
CLKB
CEB
ADA[12:0]
CLKA
CEA
RSTB
WEB
CSB[2:0]
OCEB
DOB[8:0]
DI[17:0]
CLKW
WE
EBR
RST
FULLI
CSW[1:0]
FIFO RAM
CLKR
EBR
CER
DO[17:0]
OCER
CSR[2:0]
CSW[2:0]
True Dual Port RAM
AFF
FF
AEF
EF
DO[17:0]
ORE
CLKR
RE
EMPTYI
CSR[1:0]
RPRST
ADR[12:0]
Pseudo Dual Port RAM
AD[12:0]
CLK
CE
OCE
EBR
DO[17:0]
RST
CS[2:0]
ROM
Figure 2.8. sysMEM Memory Primitives
Table 2.6. EBR Signal Descriptions
Port Name
CLK
CE
OCE1
RST
BE1
WE
AD
DI
DO
CS
AFF
FF
AEF
Description
Clock
Clock Enable
Output Clock Enable
Reset
Byte Enable
Write Enable
Address Bus
Data In
Data Out
Chip Select
FIFO RAM Almost Full Flag
FIFO RAM Full Flag
FIFO RAM Almost Empty Flag
Active State
Rising Clock Edge
Active High
Active High
Active High
Active High
Active High
—
—
—
Active High
—
—
—
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02032-3.1
23
MachXO3 Family Data Sheet
Data Sheet
Port Name
Description
Active State
—
EF
FIFO RAM Empty Flag
—
RPRST
FIFO RAM Read Pointer Reset
Notes:
1. Optional signals.
2. For dual port EBR primitives a trailing ‘A’ or ‘B’ in the signal name specifies the EBR port A or port B respectively.
3. For FIFO RAM mode primitive, a trailing ‘R’ or ‘W’ in the signal name specifies the FIFO read port or write port respectively.
4. For FIFO RAM mode primitive FULLI has the same function as CSW(2) and EMPTYI has the same function as CSR(2).
5. In FIFO mode, CLKW is the write port clock, CSW is the write port chip select, CLKR is the read port clock, CSR is the read port
chip select, ORE is the output read enable.
The EBR memory supports three forms of write behavior for single or dual port operation:
• Normal – Data on the output appears only during the read cycle. During a write cycle, the data (at the current
address) does not appear on the output. This mode is supported for all data widths.
• Write Through – A copy of the input data appears at the output of the same port. This mode is supported for all
data widths.
• Read-Before-Write – When new data is being written, the old contents of the address appears at the output.
2.5.6.
FIFO Configuration
The FIFO has a write port with data-in, CEW, WE and CLKW signals. There is a separate read port with data-out, RCE, RE
and CLKR signals. The FIFO internally generates Almost Full, Full, Almost Empty and Empty Flags. The Full and Almost
Full flags are registered with CLKW. The Empty and Almost Empty flags are registered with CLKR. Table 2.7 shows the
range of programming values for these flags.
Table 2.7. Programmable FIFO Flag Ranges
Flag Name
Full (FF)
Almost Full (AF)
Almost Empty (AE)
Empty (EF)
N = Address bit width.
Programming Range
1 to max (up to 2N-1)
1 to Full-1
1 to Full-1
0
The FIFO state machine supports two types of reset signals: RST and RPRST. The RST signal is a global reset that clears
the contents of the FIFO by resetting the read/write pointer and puts the FIFO flags in their initial reset state. The
RPRST signal is used to reset the read pointer. The purpose of this reset is to retransmit the data that is in the FIFO. In
these applications it is important to keep careful track of when a packet is written into or read from the FIFO.
2.5.7.
Memory Core Reset
The memory core contains data output latches for ports A and B. These are simple latches that can be reset
synchronously or asynchronously. RSTA and RSTB are local signals, which reset the output latches associated with port
A and port B respectively. The Global Reset (GSRN) signal resets both ports. The output data latches and associated
resets for both ports are as shown in Figure 2.9.
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
24
FPGA-DS-02032-3.1
MachXO3 Family Data Sheet
Data Sheet
Memory Core
Figure 2.9. Memory Core Reset
For further information on the sysMEM EBR block, please refer to Memory Usage Guide for MachXO3 Devices (FPGATN-02060).
2.5.8.
EBR Asynchronous Reset
EBR asynchronous reset or GSR (if used) can only be applied if all clock enables are low for a clock cycle before the
reset is applied and released a clock cycle after the reset is released, as shown in Figure 2.10. The GSR input to the EBR
is always asynchronous.
Reset
Clock
Clock
Enable
Figure 2.10. EBR Asynchronous Reset (Including GSR) Timing Diagram
If all clock enables remain enabled, the EBR asynchronous reset or GSR may only be applied and released after the EBR
read and write clock inputs are in a steady state condition for a minimum of 1/fMAX (EBR clock). The reset release must
adhere to the EBR synchronous reset setup time before the next active read or write clock edge.
If an EBR is pre-loaded during configuration, the GSR input must be disabled or the release of the GSR during device
wake up must occur before the release of the device I/O becoming active.
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02032-3.1
25
MachXO3 Family Data Sheet
Data Sheet
These instructions apply to all EBR RAM, ROM and FIFO implementations. For the EBR FIFO mode, the GSR signal is
always enabled and the WE and RE signals act like the clock enable signals in Figure 2.10. The reset timing rules apply
to the RPReset input versus the RE input and the RST input versus the WE and RE inputs. Both RST and RPReset are
always asynchronous EBR inputs. For more details refer to Memory Usage Guide for MachXO3 Devices (FPGA-TN02060).
Note that there are no reset restrictions if the EBR synchronous reset is used and the EBR GSR input is disabled.
2.6.
Programmable I/O Cells (PIC)
The programmable logic associated with an I/O is called a PIO. The individual PIO are connected to their respective
sysI/O buffers and pads. On the MachXO3L/LF devices, the PIO cells are assembled into groups of four PIO cells called a
Programmable I/O Cell or PIC. The PICs are placed on all four sides of the device.
On all the MachXO3L/LF devices, two adjacent PIOs can be combined to provide a complementary output driver pair.
All PIO pairs can implement differential receivers. Half of the PIO pairs on the top edge of these devices can be
configured as true LVDS transmit pairs. The PIO pairs on the bottom edge of these devices have on-chip differential
termination and, in the MachXO3L/LF-9400 devices, also provide PCI support.
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
26
FPGA-DS-02032-3.1
MachXO3 Family Data Sheet
Data Sheet
1 PIC
PIO A
Input Register
Block
Output Register
Block and
Tri-state
Register Block
Pin
A
PIO B
Input Register
Block
Core Logic/
Routing
Input
Gearbox
Output
Gearbox
Output Register
Block and
Tri-state
Register Block
Pin
B
PIO C
Input Register
Block
Output Register
Block and
Tri-state
Register Block
Pin
C
PIO D
Input Register
Block
Output Register
Block and
Tri-state
Register Block
Pin
D
Figure 2.11. Group of Four Programmable I/O Cells
2.7.
PIO
The PIO contains three blocks: an input register block, output register block and tri-state register block. These blocks contain
registers for operating in a variety of modes along with the necessary clock and selection logic.
Table 2.8. PIO Signal List
Pin Name
I/O Type
Description
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02032-3.1
27
MachXO3 Family Data Sheet
Data Sheet
CE
D
INDD
INCK
Q0
Q1
D0
D1
TD
Q
TQ
SCLK
RST
2.7.1.
Input
Input
Output
Output
Output
Output
Input
Input
Input
Output
Output
Input
Input
Clock Enable
Pin input from sysI/O buffer
Register bypassed input
Clock input
DDR positive edge input
Registered input/DDR negative edge input
Output signal from the core (SDR and DDR)
Output signal from the core (DDR)
Tri-state signal from the core
Data output signals to sysI/O Buffer
Tri-state output signals to sysI/O Buffer
System clock for input and output/tri-state blocks.
Local set reset signal
Input Register Block
The input register blocks for the PIOs on all edges contain delay elements and registers that can be used to condition
high-speed interface signals before they are passed to the device core.
2.7.1.1. Left, Top, Bottom Edges
Input signals are fed from the sysI/O buffer to the input register block (as signal D). If desired, the input signal can
bypass the register and delay elements and be used directly as a combinatorial signal (INDD), and a clock (INCK). If an
input delay is desired, users can select a fixed delay. I/O on the bottom edge also have a dynamic delay, DEL[4:0]. The
delay, if selected, reduces input register hold time requirements when using a global clock. The input block allows two
modes of operation. In single data rate (SDR) the data is registered with the system clock (SCLK) by one of the registers
in the single data rate sync register block. In Generic DDR mode, two registers are used to sample the data on the
positive and negative edges of the system clock (SCLK) signal, creating two data streams.
2.7.2.
Output Register Block
The output register block registers signals from the core of the device before they are passed to the sysI/O buffers.
2.7.2.1. Left, Top, Bottom Edges
In SDR mode, D0 feeds one of the flip-flops that then feeds the output. The flip-flop can be configured as a D-type
register or latch.
In DDR generic mode, D0 and D1 inputs are fed into registers on the positive edge of the clock. At the next falling edge
the registered D1 input is registered into the register Q1. A multiplexer running off the same clock is used to switch the
mux between the outputs of registers Q0 and Q1 that will then feed the output.
Figure 2.12 shows the output register block on the left, top and bottom edges.
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
28
FPGA-DS-02032-3.1
MachXO3 Family Data Sheet
Data Sheet
Q
Q0
D0
Q
D/L
D1
D
Q
Q
D
Q1
SCLK
Output path
TD
D/L
Q
TQ
Tri-state path
Figure 2.12. Output Register Block Diagram (PIO on the Left, Top and Bottom Edges)
2.7.3.
Tri-state Register Block
The tri-state register block registers tri-state control signals from the core of the device before they are passed to the
sysI/O buffers. The block contains a register for SDR operation. In SDR, TD input feeds one of the flip-flops that then
feeds the output.
2.8.
Input Gearbox
Each PIC on the bottom edge has a built-in 1:8 input gearbox. Each of these input gearboxes may be programmed as a
1:7 de-serializer or as one IDDRX4 (1:8) gearbox or as two IDDRX2 (1:4) gearboxes. Table 2.9 shows the gearbox signals.
Table 2.9. Input Gearbox Signal List
Name
D
ALIGNWD
SCLK
ECLK[1:0]
RST
Q[7:0]
I/O Type
Input
Input
Input
Input
Input
Output
Description
High-speed data input after programmable delay in PIO A input register block
Data alignment signal from device core
Slow-speed system clock
High-speed edge clock
Reset
Low-speed data to device core:
Video RX(1:7): Q[6:0]
GDDRX4(1:8): Q[7:0]
GDDRX2(1:4)(IOL-A): Q4, Q5, Q6, Q7
GDDRX2(1:4)(IOL-C): Q0, Q1, Q2, Q3
Note:
These gearboxes have three stage pipeline registers. The first stage registers sample the high-speed input data by the high-speed
edge clock on its rising and falling edges. The second stage registers perform data alignment based on the control signals UPDATE
and SEL0 from the control block. The third stage pipeline registers pass the data to the device core synchronized to the low-speed
system clock. Figure 2.13 shows a block diagram of the input gearbox.
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02032-3.1
29
MachXO3 Family Data Sheet
Data Sheet
Q21
Q43
D Q Q0_
D Q
Q65
Q10
D Q
CE
Q32
D Q
CE
Q54
D Q
CE
D Q
S2
Q21
Q43
D Q
S0
cdn
D Q
S4
D Q
T0
T2
T4
Q0
Q2
Q4
cdn
Q65
S6
D Q
Q_6
D Q
CE
D Q
T6
Q6
D
Q_6
D Q
Q_6
Q0_(x4)
Q43_(x2)
D Q
CE
Q54
D Q
Q54
D Q
Q32
Q65
D Q
CE
Q43
D Q
CE
Q32
Q10
D Q
Q21
D Q
CE
S7
S5
S3
S1
ECLK0/1
D Q
D
D
D
T7
Q7
T5
Q5
T3
Q3
T1
Q1
SCLK
SEL0
UPDATE
Figure 2.13. Input Gearbox
More information on the input gearbox is available in Implementing High-Speed Interfaces with MachXO3 Devices
(FPGA-TN-02057).
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
30
FPGA-DS-02032-3.1
MachXO3 Family Data Sheet
Data Sheet
2.9.
Output Gearbox
Each PIC on the top edge has a built-in 8:1 output gearbox. Each of these output gearboxes may be programmed as a
7:1 serializer or as one ODDRX4 (8:1) gearbox or as two ODDRX2 (4:1) gearboxes. Table 2.10 shows the gearbox signals.
Table 2.10. Output Gearbox Signal List
Name
Q
D[7:0]
Video TX(7:1): D[6:0]
GDDRX4(8:1): D[7:0]
GDDRX2(4:1)(IOL-A): D[3:0]
GDDRX2(4:1)(IOL-C): D[7:4]
SCLK
ECLK [1:0]
RST
I/O Type
Output
Input
—
—
—
—
Input
Input
Input
Description
High-speed data output
Low-speed data from device core
—
—
—
—
Slow-speed system clock
High-speed edge clock
Reset
The gearboxes have three stage pipeline registers. The first stage registers sample the low-speed input data on the lowspeed system clock. The second stage registers transfer data from the low-speed clock registers to the high- speed
clock registers. The third stage pipeline registers controlled by high-speed edge clock shift and mux the high-speed data
out to the sysI/O buffer. Figure 2.14 shows the output gearbox block diagram.
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02032-3.1
31
MachXO3 Family Data Sheet
Data Sheet
G ND
Figure 2.14. Output Gearbox
More information on the output gearbox is available in Implementing High-Speed Interfaces with MachXO3 Devices
(FPGA-TN-02057).
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
32
FPGA-DS-02032-3.1
MachXO3 Family Data Sheet
Data Sheet
2.10. sysI/O Buffer
Each I/O is associated with a flexible buffer referred to as a sysI/O buffer. These buffers are arranged around the
periphery of the device in groups referred to as banks. The sysI/O buffers allow users to implement a wide variety of
standards that are found in today’s systems including LVCMOS, TTL, PCI (MachXO3L/LF-9400 devices only), LVDS, BLVDS,
MLVDS and LVPECL.
Each bank is capable of supporting multiple I/O standards. In the MachXO3L/LF devices, single-ended output buffers,
ratioed input buffers (LVTTL, LVCMOS and PCI), differential (LVDS) input buffers are powered using I/O supply voltage
(VCCIO). Each sysI/O bank has its own VCCIO.
MachXO3L/LF devices contain three types of sysI/O buffer pairs.
• Left and Right sysI/O Buffer Pairs
•
The sysI/O buffer pairs in the left and right banks of the device consist of two single-ended output drivers and two
single-ended input buffers (for ratioed inputs such as LVCMOS and LVTTL). The I/O pairs on the left and right of the
devices also have differential input buffers.
Bottom sysI/O Buffer Pairs
•
The sysI/O buffer pairs in the bottom bank of the device consist of two single-ended output drivers and two singleended input buffers (for ratioed inputs such as LVCMOS and LVTTL). The I/O pairs on the bottom also have
differential input buffers. In the MachXO3L/LF-9400 devices, only the I/O on the bottom banks have programmable
PCI clamps and differential input termination. The PCI clamp is enabled after V CC and VCCIO are at valid operating
levels and the device has been configured.
Top sysI/O Buffer Pairs
The sysI/O buffer pairs in the top bank of the device consist of two single-ended output drivers and two
single-ended input buffers (for ratioed inputs such as LVCMOS and LVTTL). The I/O pairs on the top also have
differential I/O buffers. Half of the sysI/O buffer pairs on the top edge have true differential outputs. The sysI/O
buffer pair comprising of the A and B PIOs in every PIC on the top edge have a differential output driver.
2.10.1. Typical I/O Behavior during Power-up
The internal power-on-reset (POR) signal is deactivated when VCC and VCCIO0 have reached VPORUP level defined in the
Power-On-Reset Voltage table in the DC and Switching Characteristics section of this data sheet. After the POR signal is
deactivated, the FPGA core logic becomes active. It is the user’s responsibility to ensure that all V CCIO banks are active
with valid input logic levels to properly control the output logic states of all the I/O banks that are critical to the
application. The default configuration of the I/O pins in a blank device is tri-state with a weak pull-down to GND (some
pins such as PROGRAMN and the JTAG pins have weak pull-up to VCCIO as the default functionality). The I/O pins will
maintain the blank configuration until VCC and VCCIO (for I/O banks containing configuration I/O) have reached VPORUP
levels at which time the I/O will take on the user-configured settings only after a proper download/configuration.
2.10.2. Supported Standards
The MachXO3L/LF sysI/O buffer supports both single-ended and differential standards. Single-ended standards can be
further subdivided into LVCMOS, LVTTL, and PCI. The buffer supports the LVTTL, PCI, LVCMOS 1.2 V, 1.5 V, 1.8 V, 2.5 V,
and 3.3 V standards. In the LVCMOS and LVTTL modes, the buffer has individually configurable options for drive
strength, bus maintenance (weak pull-up, weak pull-down, bus-keeper latch or none) and open drain. BLVDS, MLVDS
and LVPECL output emulation is supported on all devices. The MachXO3L/LF devices support on-chip LVDS output
buffers on approximately 50% of the I/O on the top bank. Differential receivers for LVDS, BLVDS, MLVDS and LVPECL
are supported on all banks of MachXO3L/LF devices. PCI compatibility is supported in the bottom bank of the
MachXO3L/LF-9400 devices only. PCI support is provided by:
• Selecting the LVTTL33 buffer standard
• Enabling the clamp feature
• Setting 16 mA drive strength (PCI output only).
Table 2.11 shows the I/O standards (together with their supply and reference voltages) supported by the MachXO3L/LF
devices. For further information on utilizing the sysI/O buffer to support a variety of standards please see MachXO3
sysI/O Usage Guide (FPGA-TN-02047).
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02032-3.1
33
MachXO3 Family Data Sheet
Data Sheet
Table 2.11. Supported Input Standards
VCCIO (Typ.)
1.8 V
Input Standard
3.3 V
2.5 V
1.5 V
Single-Ended Interfaces
LVTTL
Yes
Yes2
Yes2
Yes2
LVCMOS33
Yes
Yes2
Yes2
Yes2
2
2
LVCMOS25
Yes
Yes
Yes
Yes2
2
2
LVCMOS18
Yes
Yes
Yes
Yes2
LVCMOS15
Yes2
Yes2
Yes2
Yes
2
2
2
LVCMOS12
Yes
Yes
Yes
Yes2
3
PCI
Yes
—
—
—
Differential Interfaces
LVDS
Yes
Yes
—
—
BLVDS, MLVDS, LVPECL
Yes
Yes
—
—
Yes
Yes
—
—
MIPI1
LVTTLD
Yes
—
—
—
LVCMOS33D
Yes
—
—
—
LVCMOS25D
—
Yes
—
—
LVCMOS18D
—
—
Yes
—
Notes:
1. These interfaces can be emulated with external resistors in all devices.
2. Reduced functionality. Refer to MachXO3 sysI/O Usage Guide (FPGA-TN-02047) for more details.
3. PCI input is supported for MachXO3L/LF-9400 devices, bottom bank 2 only. See the Supported Standards section.
1.2 V
—
—
—
—
Yes2
Yes
—
—
—
—
—
—
—
—
Table 2.12. Supported Output Standards
Output Standard
VCCIO (Typ.)
Single-Ended Interfaces
LVTTL
3.3
LVCMOS33
3.3
LVCMOS25
2.5
LVCMOS18
1.8
LVCMOS15
1.5
LVCMOS12
1.2
LVCMOS33, Open Drain
—
LVCMOS25, Open Drain
—
LVCMOS18, Open Drain
—
LVCMOS15, Open Drain
—
LVCMOS12, Open Drain
—
PCI332
3.3
Differential Interfaces
LVDS1
2.5, 3.3
BLVDS, MLVDS
2.5
LVPECL1
3.3
1
MIPI
2.5
LVTTLD
3.3
LVCMOS33D
3.3
LVCMOS25D
2.5
LVCMOS18D
1.8
Notes:
1. These interfaces can be emulated with external resistors in all devices.
2. PCI input is supported for MachXO3L/LF-9400 devices, bottom bank 2 only. See the Supported Standards section.
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
34
FPGA-DS-02032-3.1
MachXO3 Family Data Sheet
Data Sheet
2.10.3. sysI/O Buffer Banks
The numbers of banks vary between the devices of this family. MachXO3L/LF-1300 in the 256 Ball packages and the
MachXO3L/LF-2100 and higher density devices have six I/O banks (one bank on the top, right and bottom side and
three banks on the left side). The MachXO3L/LF-1300 and lower density devices have four banks (one bank per side).
Figure 2.15 and Figure 2.16 show the sysI/O banks and their associated supplies for all devices.
VCCIO0
GND
Bank 0
VCCIO5
GND
VCCIO1
VCCIO4
GND
GND
VCCIO3
GND
Bank 2
GND
VCCIO2
Figure 2.15. MachXO3L/LF-1300 in 256 Ball Packages, MachXO3L/LF-2100, MachXO3L/LF-4300, MachXO3L/LF-6900
and MachXO3L/LF-9400 Banks I/O Banks
GND
VCCIO0
Bank 0
VCCIO3
VCCIO1
GND
GND
Bank 2
GND
VCCIO2
Figure 2.16. MachXO3L/LF-640 and MachXO3L/LF-1300 Banks
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02032-3.1
35
MachXO3 Family Data Sheet
Data Sheet
2.11. Hot Socketing
The MachXO3L/LF devices have been carefully designed to ensure predictable behavior during power-up and powerdown. Leakage into I/O pins is controlled to within specified limits. This allows for easy integration with the rest of the
system. These capabilities make the MachXO3L/LF ideal for many multiple power supply and hot-swap applications.
2.12. On-chip Oscillator
Every MachXO3L/LF device has an internal CMOS oscillator. The oscillator output can be routed as a clock to the clock
tree or as a reference clock to the sysCLOCK PLL using general routing resources. The oscillator frequency can be
divided by internal logic. There is a dedicated programming bit and a user input to enable/disable the oscillator. The
oscillator frequency ranges from 2.08 MHz to 133 MHz. The software default value of the Master Clock (MCLK) is
nominally 2.08 MHz. When a different MCLK is selected during the design process, the following sequence takes place:
Device powers up with a nominal MCLK frequency of 2.08 MHz.
During configuration, users select a different master clock frequency.
The MCLK frequency changes to the selected frequency once the clock configuration bits are received.
If the user does not select a master clock frequency, then the configuration bitstream defaults to the MCLK frequency
of 2.08 MHz.
Table 2.13 lists all the available MCLK frequencies.
Table 2.13. Available MCLK Frequencies
MCLK (MHz, Nominal)
2.08 (default)
2.46
3.17
4.29
5.54
7
8.31
MCLK (MHz, Nominal)
9.17
10.23
13.3
14.78
20.46
26.6
29.56
MCLK (MHz, Nominal)
33.25
38
44.33
53.2
66.5
88.67
133
2.13. Embedded Hardened IP Functions
All MachXO3L/LF devices provide embedded hardened functions such as SPI, I 2C and Timer/Counter. MachXO3LF
devices also provide User Flash Memory (UFM). These embedded blocks interface through the WISHBONE interface
with routing as shown in Figure 2.17.
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
36
FPGA-DS-02032-3.1
MachXO3 Family Data Sheet
Data Sheet
Figure 2.17. Embedded Function Block Interface
2.13.1. Hardened I2C IP Core
Every MachXO3L/LF device contains two I2C IP cores. These are the primary and secondary I2C IP cores. Either of the
two cores can be configured either as an I2C master or as an I2C slave. The only difference between the two IP cores is
that the primary core has pre-assigned I/O pins whereas users can assign I/O pins for the secondary core.
When the IP core is configured as a master it will be able to control other devices on the I2C bus through the interface.
When the core is configured as the slave, the device will be able to provide I/O expansion to an I 2C Master. The I2C
cores support the following functionality:
• Master and Slave operation
• 7-bit and 10-bit addressing
• Multi-master arbitration support
• Up to 400 kHz data transfer speed
• General call support
• Interface to custom logic through 8-bit WISHBONE interface
Figure 2.18. I2C Core Block Diagram
Table 2.14 describes the signals interfacing with the I2C cores.
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02032-3.1
37
MachXO3 Family Data Sheet
Data Sheet
Table 2.14. I2C Core Signal Description
Signal Name
I/O
i2c_scl
Bi-directional
Description
Bi-directional clock line of the I2C core. The signal is an output if the I2C core is in master
mode. The signal is an input if the I2C core is in slave mode. MUST be routed directly to the
pre-assigned I/O of the chip. Refer to the Pinout Information section of this document for
detailed pad and pin locations of I2C ports in each MachXO3L/LF device.
Bi-directional
Bi-directional data line of the I2C core. The signal is an output when data is transmitted from
the I2C core. The signal is an input when data is received into the I2C core. MUST be routed
directly to the pre-assigned I/O of the chip. Refer to the Pinout Information section of this
document for detailed pad and pin locations of I2C ports in each MachXO3L/LF device.
i2c_irqo
Output
Interrupt request output signal of the I2C core. The intended usage of this signal is for it to be
connected to the WISHBONE master controller (i.e. a microcontroller or state machine) and
request an interrupt when a specific condition is met. These conditions are described with the
I2C register definitions.
cfg_wake
Output
cfg_stdby
Output
i2c_sda
Wake-up signal – To be connected only to the power module of the MachXO3L/LF device. The
signal is enabled only if the “Wakeup Enable” feature has been set within the EFB GUI, I2C
Tab.
Stand-by signal – To be connected only to the power module of the MachXO3L/LF device. The
signal is enabled only if the “Wakeup Enable” feature has been set within the EFB GUI, I2C
Tab.
2.13.2. Hardened SPI IP Core
Every MachXO3L/LF device has a hard SPI IP core that can be configured as a SPI master or slave. When the IP core is
configured as a master it will be able to control other SPI enabled chips connected to the SPI bus. When the core is
configured as the slave, the device will be able to interface to an external SPI master. The SPI IP core on MachXO3L/LF
devices supports the following functions:
• Configurable Master and Slave modes
• Full-Duplex data transfer
• Mode fault error flag with CPU interrupt capability
• Double-buffered data register
• Serial clock with programmable polarity and phase
• LSB First or MSB First Data Transfer
• Interface to custom logic through 8-bit WISHBONE interface
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
38
FPGA-DS-02032-3.1
MachXO3 Family Data Sheet
Data Sheet
There are some limitations on the use of the hardened user SPI. These are defined in the following technical notes:
• Minimizing System Interruption During Configuration Using TransFR Technology (FPGA-TN-02025) (Appendix B)
• Using Hardened Control Functions in MachXO3 Devices (FPGA-TN-02063)
Configuration
Logic
EFB
SPI Function
MISO
Core
Logic/
Routing
MOSI
EFB
WISHBONE
Interface
SPI
Registers
Control
Logic
SCK
MCSN
SCSN
Figure 2.19. SPI Core Block Diagram
Table 2.15 describes the signals interfacing with the SPI cores.
Table 2.15. SPI Core Signal Description
Signal Name
spi_csn[0]
spi_csn[1..7]
spi_scsn
spi_irq
spi_clk
spi_miso
spi_mosi
I/O
O
O
I
O
I/O
I/O
I/O
Master/Slave
Master
Master
Slave
Master/Slave
Master/Slave
Master/Slave
Master/Slave
sn
I
Slave
cfg_stdby
O
Master/Slave
cfg_wake
O
Master/Slave
Description
SPI master chip-select output
Additional SPI chip-select outputs (total up to eight slaves)
SPI slave chip-select input
Interrupt request
SPI clock. Output in master mode. Input in slave mode.
SPI data. Input in master mode. Output in slave mode.
SPI data. Output in master mode. Input in slave mode.
Configuration Slave Chip Select (active low), dedicated for selecting the
Configuration Logic.
Stand-by signal – To be connected only to the power module of the
MachXO3L/LF device. The signal is enabled only if the “Wakeup Enable” feature
has been set within the EFB GUI, SPI Tab.
Wake-up signal – To be connected only to the power module of the
MachXO3L/LF device. The signal is enabled only if the “Wakeup Enable” feature
has been set within the EFB GUI, SPI Tab.
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02032-3.1
39
MachXO3 Family Data Sheet
Data Sheet
2.13.3. Hardened Timer/Counter
MachXO3L/LF devices provide a hard Timer/Counter IP core. This Timer/Counter is a general purpose, bidirectional,
16-bit timer/counter module with independent output compare units and PWM support. The Timer/Counter supports
the following functions:
• Supports the following modes of operation:
• Watchdog timer
• Clear timer on compare match
• Fast PWM
• Phase and Frequency Correct PWM
• Programmable clock input source
• Programmable input clock prescaler
• One static interrupt output to routing
• One wake-up interrupt to on-chip standby mode controller
• Three independent interrupt sources: overflow, output compare match, and input capture
• Auto reload
• Time-stamping support on the input capture unit
• Waveform generation on the output
• Glitch-free PWM waveform generation with variable PWM period
• Internal WISHBONE bus access to the control and status registers
• Stand-alone mode with preloaded control registers and direct reset input
Figure 2.20. Timer/Counter Block Diagram
Table 2.16. Timer/Counter Signal Description
Port
tc_clki
tc_rstn
I/O
I
I
tc_ic
I
tc_int
O
tc_oc
O
Description
Timer/Counter input clock signal
Register tc_rstn_ena is preloaded by configuration to always keep this pin enabled.
Input capture trigger event, applicable for non-pwm modes with WISHBONE interface. If enabled,
a rising edge of this signal will be detected and synchronized to capture tc_cnt value into tc_icr
for time-stamping.
Without WISHBONE – Can be used as overflow flag With WISHBONE – Controlled by three IRQ
registers.
Timer counter output signal
For more details on these embedded functions, please refer to Using Hardened Control Functions in MachXO3 Devices
(FPGA-TN-02063).
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
40
FPGA-DS-02032-3.1
MachXO3 Family Data Sheet
Data Sheet
2.14. User Flash Memory (UFM)
MachXO3LF devices provide a User Flash Memory block, which can be used for a variety of applications including
storing a portion of the configuration image, initializing EBRs, to store PROM data or, as a general purpose user Flash
memory. The UFM block connects to the device core through the embedded function block WISHBONE interface. Users
can also access the UFM block through the JTAG, I2C and SPI interfaces of the device. The UFM block offers the
following features:
• Non-volatile storage up to 448 kbits
• 100,000 write/erase cycles for commercial/industrial devices and 10,000 for automotive devices
• Write access is performed page-wise; each page has 128 bits (16 bytes)
• Auto-increment addressing
• WISHBONE interface
For more information on the UFM, please refer to Using Hardened Control Functions in MachXO3 Devices (FPGA-TN02063).
2.15. Standby Mode and Power Saving Options
MachXO3L/LF devices are available in two options, the C and E devices. The C devices have a built-in voltage regulator
to allow for 2.5 V VCC and 3.3 V VCC while the E devices operate at 1.2 V VCC.
MachXO3L/LF devices have been designed with features that allow users to meet the static and dynamic power
requirements of their applications by controlling various device subsystems such as the bandgap, power-on-reset
circuitry, I/O bank controllers, power guard, on-chip oscillator, PLLs, etc. In order to maximize power savings,
MachXO3L/LF devices support a low power Stand-by mode.
In the stand-by mode the MachXO3L/LF devices are powered on and configured. Internal logic, I/O and memories are
switched on and remain operational, as the user logic waits for an external input. The device enters this mode when
the standby input of the standby controller is toggled or when an appropriate I2C or JTAG instruction is issued by an
external master. Various subsystems in the device such as the band gap, power-on-reset circuitry etc. can be
configured such that they are automatically turned “off” or go into a low power consumption state to save power when
the device enters this state. Note that the MachXO3L/LF devices are powered on when in standby mode and all power
supplies should remain in the Recommended Operating Conditions.
Table 2.17. MachXO3L/LF Power Saving Features Description
Device Subsystem
Bandgap
Power-On-Reset (POR)
On-Chip Oscillator
PLL
I/O Bank Controller
Dynamic Clock Enable for Primary
Clock Nets
Power Guard
Feature Description
The bandgap can be turned off in standby mode. When the Bandgap is turned off, analog
circuitry such as the POR, PLLs, on-chip oscillator, and differential I/O buffers are also
turned off. Bandgap can only be turned off for 1.2 V devices.
The POR can be turned off in standby mode. This monitors VCC levels. In the event of
unsafe VCC drops, this circuit reconfigures the device. When the POR circuitry is turned
off, limited power detector circuitry is still active. This option is only recommended for
applications in which the power supply rails are reliable.
The on-chip oscillator has two power saving features. It may be switched off if it is not
needed in your design. It can also be turned off in Standby mode.
Similar to the on-chip oscillator, the PLL also has two power saving features. It can be
statically switched off if it is not needed in a design. It can also be turned off in Standby
mode. The PLL will wait until all output clocks from the PLL are driven low before
powering off.
Differential I/O buffers (used to implement standards such as LVDS) consume more than
ratioed single-ended I/O such as LVCMOS and LVTTL. The I/O bank controller allows the
user to turn these I/O off dynamically on a per bank selection.
Each primary clock net can be dynamically disabled to save power.
Power Guard is a feature implemented in input buffers. This feature allows users to switch
off the input buffer when it is not needed. This feature can be used in both clock and data
paths. Its biggest impact is that in the standby mode it can be used to switch off clock
inputs that are distributed using general routing resources.
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02032-3.1
41
MachXO3 Family Data Sheet
Data Sheet
For more details on the standby mode refer to Power and Thermal Estimation and Management for MachXO3 Devices
(FPGA-TN-02059).
2.16. Power On Reset
MachXO3L/LF devices have power-on reset circuitry to monitor VCCINT and VCCIO voltage levels during power-up and
operation. At power-up, the POR circuitry monitors VCCINT and VCCIO0 (controls configuration) voltage levels. It then
triggers download from the on-chip configuration NVCM/Flash memory after reaching the VPORUP level specified in
the Power-On-Reset Voltage table in the DC and Switching Characteristics section of this data sheet. For “E” devices
without voltage regulators, VCCINT is the same as the VCC supply voltage. For “C” devices with voltage regulators, V CCINT is
regulated from the VCC supply voltage. From this voltage reference, the time taken for configuration and entry into user
mode is specified as NVCM/Flash Download Time (t REFRESH) in the DC and Switching Characteristics section of this data
sheet. Before and during configuration, the I/O are held in tri-state. I/O are released to user functionality once the
device has finished configuration. Note that for “C” devices, a separate POR circuit monitors external V CC voltage in
addition to the POR circuit that monitors the internal post-regulated power supply voltage level.
Once the device enters into user mode, the POR circuitry can optionally continue to monitor VCCINT levels. If VCCINT drops
below VPORDNBG level (with the bandgap circuitry switched on) or below VPORDNSRAM level (with the bandgap circuitry
switched off to conserve power) device functionality cannot be guaranteed. In such a situation the POR issues a reset
and begins monitoring the VCCINT and VCCIO voltage levels. VPORDNBG and VPORDNSRAM are both specified in the
Power-On-Reset Voltage table in the DC and Switching Characteristics section of this data sheet.
Note that once an “E” device enters user mode, users can switch off the bandgap to conserve power. When the
bandgap circuitry is switched off, the POR circuitry also shuts down. The device is designed such that a minimal, low
power POR circuit is still operational (this corresponds to the V PORDNSRAM reset point described in the paragraph above).
However this circuit is not as accurate as the one that operates when the bandgap is switched on. The low power POR
circuit emulates an SRAM cell and is biased to trip before the vast majority of SRAM cells flip. If users are concerned
about the VCC supply dropping below VCC (min) they should not shut down the bandgap or POR circuit.
2.17. Configuration and Testing
This section describes the configuration and testing features of the MachXO3L/LF family.
2.17.1. IEEE 1149.1-Compliant Boundary Scan Testability
All MachXO3L/LF devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant test access port
(TAP). This allows functional testing of the circuit board, on which the device is mounted, through a serial scan path
that can access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in and
loaded directly onto test nodes, or test data to be captured and shifted out for verification. The test access port
consists of dedicated I/O: TDI, TDO, TCK and TMS. The test access port shares its power supply with VCCIO Bank 0 and
can operate with LVCMOS3.3, 2.5, 1.8, 1.5, and 1.2 standards.
For more details on boundary scan test, see Boundary Scan Testability with Lattice sysI/O Capability (AN8066) and
Minimizing System Interruption During Configuration Using TransFR Technology (FPGA-TN-02025).
2.17.2. Device Configuration
All MachXO3L/LF devices contain two ports that can be used for device configuration. The Test Access Port (TAP),
which supports bit-wide configuration and the sysCONFIG port which supports serial configuration through I 2C or SPI.
The TAP supports both the IEEE Standard 1149.1 Boundary Scan specification and the IEEE Standard 1532 In-System
Configuration specification. There are various ways to configure a MachXO3L/LF device:
• Internal Flash Download
• JTAG
• Standard Serial Peripheral Interface (Master SPI mode) – interface to boot PROM memory
• System microprocessor to drive a serial slave SPI port (SSPI mode)
• Standard I2C Interface to system microprocessor
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
42
FPGA-DS-02032-3.1
MachXO3 Family Data Sheet
Data Sheet
Upon power-up, the configuration SRAM is ready to be configured using the selected sysCONFIG port. Once a
configuration port is selected, it will remain active throughout that configuration cycle. The IEEE 1149.1 port can be
activated any time after power-up by sending the appropriate command through the TAP port. Optionally the de- vice
can run a CRC check upon entering the user mode. This will ensure that the device was configured correctly.
The sysCONFIG port has 10 dual-function pins which can be used as general purpose I/O if they are not required for
configuration. See MachXO3 Programming and Configuration Usage Guide (FPGA-TN-02055) for more information
about using the dual-use pins as general purpose I/O.
Lattice design software uses proprietary compression technology to compress bit-streams for use in MachXO3L/ LF
devices. Use of this technology allows Lattice to provide a lower cost solution. In the unlikely event that this technology
is unable to compress bitstreams to fit into the amount of on-chip NVCM/Flash, there are a variety of techniques that
can be utilized to allow the bitstream to fit in the on-chip NVCM/Flash. For more details, refer to MachXO3
Programming and Configuration Usage Guide (FPGA-TN-02055).
The Test Access Port (TAP) has five dual purpose pins (TDI, TDO, TMS, TCK and JTAGENB). These pins are dual function
pins - TDI, TDO, TMS and TCK can be used as general purpose I/O if desired. For more details, refer to MachXO3
Programming and Configuration Usage Guide (FPGA-TN-02055).
2.17.2.1. TransFR (Transparent Field Reconfiguration)
TransFR is a unique Lattice technology that allows users to update their logic in the field without interrupting system
operation using a simple push-button solution. For more details, refer to Minimizing System Interruption During
Configuration Using TransFR Technology (FPGA-TN-02025) for details.
2.17.2.2. Security and One-Time Programmable Mode (OTP)
For applications where security is important, the lack of an external bitstream provides a solution that is inherently
more secure than SRAM-based FPGAs. This is further enhanced by device locking. MachXO3L/LF devices contain
security bits that, when set, prevent the readback of the SRAM configuration and NVCM/Flash spaces. The device can
be in one of two modes:
• Unlocked – Readback of the SRAM configuration and NVCM/Flash spaces is allowed.
• Permanently Locked – The device is permanently locked.
Once set, the only way to clear the security bits is to erase the device. To further complement the security of the
device, a One Time Programmable (OTP) mode is available. Once the device is set in this mode it is not possible to
erase or re-program the NVCM/Flash and SRAM OTP portions of the device. For more details, refer to MachXO3
Programming and Configuration Usage Guide (FPGA-TN-02055).
2.17.2.3. Password
The MachXO3LF supports a password-based security access feature also known as Flash Protect Key. Optionally, the
MachXO3L device can be ordered with a custom specification (c-spec) to support this feature. The Flash Protect Key
feature provides a method of controlling access to the Configuration and Programming modes of the device. When
enabled, the Configuration and Programming edit mode operations (including Write, Verify and Erase operations) are
allowed only when coupled with a Flash Protect Key which matches that expected by the device. Without a valid Flash
Protect Key, the user can perform only rudimentary non-configuration operations such as Read Device ID. For more
details, refer to Using Password Security with MachXO3 Devices (FPGA-TN-02072).
2.17.2.4. Dual Boot
MachXO3L/LF devices can optionally boot from two patterns, a primary bitstream and a golden bitstream. If the
primary bitstream is found to be corrupt while being downloaded into the SRAM, the device shall then automatically
re-boot from the golden bitstream. Note that the primary bitstream must reside in the external SPI Flash. The golden
image MUST reside in an on-chip NVCM/Flash. For more details, refer to MachXO3 Programming and Configuration
Usage Guide (FPGA-TN-02055).
2.17.2.5. Soft Error Detection
The SED feature is a CRC check of the SRAM cells after the device is configured. This check ensures that the SRAM cells
were configured successfully. This feature is enabled by a configuration bit option. The Soft Error Detection can also be
initiated in user mode via an input to the fabric. The clock for the Soft Error Detection circuit is generated using a
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02032-3.1
43
MachXO3 Family Data Sheet
Data Sheet
dedicated divider. The undivided clock from the on-chip oscillator is the input to this divider. For low power
applications users can switch off the Soft Error Detection circuit. For more details, refer to MachXO3 Soft Error
Detection Usage Guide (FPGA-TN-02062).
2.17.2.6. Soft Error Correction
The MachXO3LF device supports Soft Error Correction (SEC). Optionally, the MachXO3L device can be ordered with a
custom specification (c-spec) to support this feature. When BACKGROUND_RECONFIG is enabled using the Lattice
Diamond Software in a design, asserting the PROGRAMN pin or issuing the REFRESH sysConfig command refreshes the
SRAM array from configuration memory. Only the detected error bit is corrected. No other SRAM cells are changed,
allowing the user design to function uninterrupted.
During the project design phase, if the overall system cannot guarantee containment of the error or its subsequent
effects on downstream data or control paths, Lattice recommends using SED only. The MachXO3 can be then be
soft-reset by asserting PROGRAMN or issuing the Refresh command over a sysConfig port in response to SED. Soft-reset
additionally erases the SRAM array prior to the SRAM refresh, and asserts internal Reset circuitry to guarantee a known
state. For more details, refer to MachXO3 Soft Error Detection (SED)/Correction (SEC) Usage Guide (FPGA-TN-02062).
2.18. TraceID
Each MachXO3L/LF device contains a unique (per device), TraceID that can be used for tracking purposes or for IP
security applications. The TraceID is 64 bits long. Eight out of 64 bits are user-programmable, the remaining 56 bits are
factory-programmed. The TraceID is accessible through the EFB WISHBONE interface and can also be accessed through
the SPI, I2C, or JTAG interfaces.
2.19. Density Shifting
The MachXO3L/LF family has been designed to enable density migration within the same package. Furthermore, the
architecture ensures a high success rate when performing design migration from lower density devices to higher
density devices. In many cases, it is also possible to shift a lower utilization design targeted for a high-density device to
a lower density device. However, the exact details of the final resource utilization will impact the likely success in each
case. When migrating from lower to higher density or higher to lower density, ensure to review all the power supplies
and NC pins of the chosen devices. For more details refer to the MachXO3 migration files.
2.20. MachXO3LF to MachXO3L Low Cost Migration Path
To support the MachXO3LF to MachXO3L low cost migration path, the MachXO3L Migration options (JEDEC and
Bitstream) are added to the Process List in Diamond. This migration path is a time saving feature as it allows you to
validate functionality and timing on one project without having to recompile your design for the MachXO3L device.
MachXO3L device does not support UFM, SEC, and Password Protect features. For example if a MachXO3LF design is
using UFM, an error message is produced if converting this design to MachXO3L.
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
44
FPGA-DS-02032-3.1
MachXO3 Family Data Sheet
Data Sheet
3. DC and Switching Characteristics
3.1.
Absolute Maximum Rating
Table 3.1. Absolute Maximum Rating1, 2, 3
MachXO3L/LF E (1.2 V)
MachXO3L/LF C (2.5 V/3.3 V)6
Supply Voltage VCC
–0.5 V to 1.32 V
–0.5 V to 3.75 V
Output Supply Voltage VCCIO
–0.5 V to 3.75 V
–0.5 V to 3.75 V
I/O Tri-state Voltage Applied4, 5
–0.5 V to 3.75 V
–0.5 V to 3.75 V
Dedicated Input Voltage Applied4
–0.5 V to 3.75 V
–0.5 V to 3.75 V
Storage Temperature (Ambient)
–55 °C to 125 °C
–55 °C to 125 °C
Junction Temperature (TJ)
–40 °C to 125 °C
–40 °C to 125 °C
Notes:
1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is
not implied.
2. Compliance with the Lattice Thermal Management document is required.
3. All voltages referenced to GND.
4. Overshoot and undershoot of –2 V to (VIHMAX + 2) volts is permitted for a duration of 100 MHz
fPFD < 100 MHz
fOUT > 100 MHz
fOUT < 100 MHz
fOUT > 100 MHz
fOUT < 100 MHz
Divider ratio = integer
At 90% or 10%3
—
—
fPFD ≥ 20 MHz
fPFD < 20 MHz
90% to 90%
10% to 10%
—
—
—
—
—
—
PHASESTEP Pulse Width
—
Output Clock Cycle-to-cycle
Jitter
Output Clock Phase Jitter
Output Clock Period Jitter
(Fractional-N)
Output Clock Cycle-to-cycle
Jitter (Fractional-N)
–6
(Commercial/Industrial)
Min.
Max.
—
150
—
0.007
—
180
—
0.009
—
160
—
0.011
—
230
—
0.12
—
230
—
0.12
–120
120
—
0.9
—
15
—
50
—
1,000
—
0.02
—
0.5
—
0.5
—
15
—
1
—
1
—
10
—
1
—
10
–5
(Automotive)
Min.
Max.
—
150
—
0.010
—
180
—
0.015
—
160
—
0.011
—
TBD
—
TBD
—
TBD
—
TBD
–141
141
—
—
—
17.5
—
50
—
1,000
0.8
0.02
—
0.8
—
0.5
—
15
—
1
—
2.46
—
10
—
2.33
—
10
Units
ps p-p
UIPP
ps p-p
UIPP
ps p-p
UIPP
ps p-p
UIPP
ps p-p
UIPP
ps
ns
ms
ns
ps p-p
UIPP
ns
ns
ms
ns
ns
ns
ns
ns
SETUP
tROTATE_WD
4
—
4
—
VCO
Cycles
Notes:
1. Period jitter sample is taken over 10,000 samples of the primary PLL output with a clean reference clock. Cycle-to-cycle jitter is
taken over 1000 cycles. Phase jitter is taken over 2000 cycles. All values per JESD65B.
2. Output clock is valid after tLOCK for PLL reset and dynamic delay adjustment.
3. Using LVDS output buffers.
4. CLKOS as compared to CLKOP output for one phase step at the maximum VCO frequency. See MachXO3 sysCLOCK PLL Design
and Usage Guide (FPGA-TN-02058) for more details.
5. At minimum fPFD. As the fPFD increases the time will decrease to approximately 60% the value listed.
6. Maximum allowed jitter on an input clock. PLL unlock may occur if the input jitter exceeds this specification. Jitter on the input
clock may be transferred to the output clocks, resulting in jitter measurements outside the output specifications listed in this
table.
7. Edge Duty Trim Accuracy is a percentage of the setting value. Settings available are 70 ps, 140 ps, and 280 ps in addition to the
default value of none.
Edge Duty Trim Accuracy does not apply to Automotive.
8. Jitter values measured with the internal oscillator operating. The jitter values will increase with loading of the PLD fabric and in
the presence of SSO noise.
3.19. Oscillator Output Frequency
Table 3.23. Oscillator Output Frequency
Symbol
Parameter
–6
(Commercial/Industrial)
–5
(Automotive)
Units
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02032-3.1
69
MachXO3 Family Data Sheet
Data Sheet
Oscillator Output Frequency (Commercial
Grade Devices, 0 to 85°C)
Oscillator Output Frequency (Industrial Grade
Devices, –40 °C to 100 °C)
Oscillator Output Frequency (Automotive
Grade Devices, -40 to 125°C)
fMAX
Min.
Typ.
Max
Min.
Typ.
Max
125.685
133
140.315
—
—
—
MHz
124.355
133
141.645
—
—
—
MHz
—
—
—
122.360
133
143.640
MHz
tDT
Output Clock Duty Cycle
43
50
57
43
50
57
%
tOPJIT
Output Clock Period Jitter
—
—
0.02
—
—
0.02
UIPP
tSTABLEOSC
STDBY Low to Oscillator Stable
—
—
0.1
—
—
0.1
µs
Note: Output Clock Period Jitter specified at 133 MHz. The values for lower frequencies will be smaller UIPP. The typical value for
133 MHz is 95 ps and for 2.08 MHz the typical value is 1.54 ns.
3.20. NVCM/Flash Download Time
Table 3.24. NVCM/Flash Download Time
Symbol
Parameter
tREFRESH
POR to Device I/O Active
Device
LCMXO3L/LF-640
LCMXO3L/LF-1300
LCMXO3L/LF-1300 256-Ball Package
LCMXO3L/LF-2100
LCMXO3L/LF-2100 324-Ball Package
LCMXO3L/LF-4300
LCMXO3L/LF-4300 400-Ball Package
LCMXO3L/LF-6900
LCMXO3L/LF-9400C
Typ.
1.9
1.9
1.4
1.4
2.4
2.4
3.8
3.8
5.2
Units
ms
ms
ms
ms
ms
ms
ms
ms
ms
Notes:
•
Assumes sysMEM EBR initialized to an all zero pattern if they are used.
•
The NVCM/Flash download time is measured starting from the maximum voltage of POR trip point.
•
The worst case can be up to 1.75 times the Typ value.
3.21. JTAG Port Timing Specifications
Table 3.25. JTAG Port Timing Specifications
Symbol
Parameter
fMAX
tBTCPH
tBTCPL
tBTS
tBTH
tBTCO
tBTCODIS
tBTCOEN
tBTCRS
tBTCRH
TCK clock frequency
TCK [BSCAN] clock pulse width high
TCK [BSCAN] clock pulse width low
TCK [BSCAN] setup time
TCK [BSCAN] hold time
TAP controller falling edge of clock to valid output
TAP controller falling edge of clock to valid disable
TAP controller falling edge of clock to valid enable
BSCAN test capture register setup time
BSCAN test capture register hold time
BSCAN test update register, falling edge of clock to
valid output
BSCAN test update register, falling edge of clock to
valid disable
tBUTCO
tBTUODIS
tBTUPOEN
BSCAN test update register, falling edge of clock to
Commercial/Industrial
Min.
Max.
25
—
20
—
20
—
10
—
8
—
10
—
10
—
10
—
8
—
20
—
Automotive
Min.
Max.
25
—
20
—
20
—
10
—
10
—
10
—
12
—
12
—
8
—
20
—
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
25
—
25
ns
—
25
—
27
ns
—
25
—
25
ns
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
70
FPGA-DS-02032-3.1
MachXO3 Family Data Sheet
Data Sheet
valid enable
Figure 3.8. JTAG Port Timing Waveforms
3.22. sysCONFIG Port Timing Specifications
Table 3.26. sysCONFIG Port Timing Specifications
Symbol
Parameter
All Configuration Modes
tPRGM
PROGRAMN low pulse accept
tPRGMJ
PROGRAMN low pulse rejection
LCMXO3L/LF-640/
LCMXO3L/LF-1300
LCMXO3L/LF-1300
256-Ball Package/
LCMXO3L/LF-2100
LCMXO3L/LF-2100
tINITL
INITN low time
324-Ball Package/
LCMXO3-4300
LCMXO3L/LF-4300
400-Ball Package/
LCMXO3-6900
LCMXO3L/LF-9400C
tDPPINIT
PROGRAMN low to INITN low
tDPPDONE
PROGRAMN low to DONE low
Commercial/Industrial
Min.
Max.
Automotive
Min.
Max.
Units
55
—
—
25
55
—
—
25
ns
ns
—
55
—
—
us
—
70
—
93
us
—
105
—
130
us
—
130
—
—
us
—
—
—
175
150
150
—
—
—
—
150
150
us
ns
ns
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02032-3.1
71
MachXO3 Family Data Sheet
Data Sheet
tIODISS
Slave SPI
fMAX
tCCLKH
tCCLKL
tSTSU
tSTH
tSTCO
tSTOZ
tSTOV
tSCS
tSCSS
tSCSH
Master SPI
fMAX
tMCLKH
tMCLKL
tSTSU
tSTH
tCSSPI
tMCLK
PROGRAMN low to I/O disable
—
120
—
120
ns
CCLK clock frequency
CCLK clock pulse width high
CCLK clock pulse width low
CCLK setup time
CCLK hold time
CCLK falling edge to valid output
CCLK falling edge to valid disable
CCLK falling edge to valid enable
Chip select high time
Chip select setup time
Chip select hold time
—
7.5
7.5
2
0
—
—
—
25
3
3
66
—
—
—
—
10
10
10
—
—
—
—
7.5
7.5
2
0
—
—
—
25
3
3
66
—
—
—
—
14
12
14
—
—
—
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MCLK clock frequency
MCLK clock pulse width high
MCLK clock pulse width low
MCLK setup time
MCLK hold time
INITN high to chip select low
INITN high to first MCLK edge
—
3.75
3.75
5
1
100
0.75
133
—
—
—
—
200
1
—
7.5
7.5
6
3
100
0.75
66
—
—
—
—
200
1
MHz
ns
ns
ns
ns
ns
us
3.23. I2C Port Timing Specifications
Table 3.27. I2C Port Timing Specification
Symbol
Parameter
fMAX
Maximum SCL clock frequency
Min.
Max.
Units
—
400
kHz
Min.
Max.
Units
—
45
MHz
Notes:
•
MachXO3L/LF supports the following modes:
•
Standard-mode (Sm), with a bit rate up to 100 kb/s (user and configuration mode)
•
Fast-mode (Fm), with a bit rate up to 400 kb/s (user and configuration mode)
•
Refer to the I2C specification for timing requirements.
3.24. SPI Port Timing Specifications
Table 3.28. SPI Port Timing Specifications
Symbol
Parameter
fMAX
Maximum SCK clock frequency
Note: Applies to user mode only. For configuration mode timing specifications, refer to sysCONFIG Port Timing Specifications table in
this data sheet.
3.25. Switching Test Conditions
Figure 3.9 shows the output test load used for AC testing. The specific values for resistance, capacitance, voltage, and
other test conditions are shown in Table 3.29.
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
72
FPGA-DS-02032-3.1
MachXO3 Family Data Sheet
Data Sheet
VT
R1
Test Point
DUT
CL
Figure 3.9. Output Test Load, LVTTL and LVCMOS Standards
Table 3.29. Test Fixture Required Components, Non-Terminated Interfaces
Test Condition
LVTTL and LVCMOS settings (L -> H, H -> L)
R1
CL
0 pF
Timing Ref.
VT
LVTTL, LVCMOS 3.3 = 1.5 V
—
LVCMOS 2.5 = VCCIO/2
—
LVCMOS 1.8 = VCCIO/2
—
LVCMOS 1.5 = VCCIO/2
—
LVCMOS 1.2 = VCCIO/2
LVTTL and LVCMOS 3.3 (Z -> H)
1.5
—
VOL
LVTTL and LVCMOS 3.3 (Z -> L)
1.5
VOH
Other LVCMOS (Z -> H)
Other LVCMOS (Z -> L)
188
0 pF
VCCIO/2
VOL
VCCIO/2
VOH
LVTTL + LVCMOS (H -> Z)
VOH – 0.15
VOL
LVTTL + LVCMOS (L -> Z)
VOL – 0.15
VOH
Note: Output test conditions for all other interfaces are determined by the respective standards.
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02032-3.1
73
MachXO3 Family Data Sheet
Data Sheet
4. Signal Descriptions
Table 4.1. Signal Descriptions
Signal Name
General Purpose
I/O
Descriptions
[Edge] indicates the edge of the device on which the pad is located. Valid edge designations
are L (Left), B (Bottom), R (Right), T (Top).
[Row/Column Number] indicates the PFU row or the column of the device on which the PIO
Group exists. When Edge is T (Top) or (Bottom), only need to specify Row Number. When
Edge is L (Left) or R (Right), only need to specify Column Number.
[A/B/C/D] indicates the PIO within the group to which the pad is connected.
Some of these user-programmable pins are shared with special function pins. When not used
P[Edge] [Row/Column
I/O
as special function pins, these pins can be programmed as I/O for user logic.
Number]_[A/B/C/D]
During configuration of the user-programmable I/O, the user has an option to tri-state the
I/O and enable an internal pull-up, pull-down or buskeeper resistor. This option also applies
to unused pins (or those not bonded to a package pin). The default during configuration is for
user-programmable I/O to be tri-stated with an internal pull-down resistor enabled. When
the device is erased, I/O will be tri-stated with an internal pull-down resistor enabled. Some
pins, such as PROGRAMN and JTAG pins, default to tri-stated I/O with pull-up resistors
enabled when the device is erased.
NC
—
No connect.
GND
—
GND – Ground. Dedicated pins. It is recommended that all GNDs are tied together.
VCC – The power supply pins for core logic. Dedicated pins. It is recommended that all VCCs are
VCC
—
tied to the same supply.
VCCIO – The power supply pins for I/O Bank x. Dedicated pins. It is recommended that all VCCIOs
VCCIOx
—
located in the same bank are tied to the same supply.
PLL and Clock Functions (Used as user-programmable I/O pins when not used for PLL or clock pins)
Reference Clock (PLL) input pads: [LOC] indicates location. Valid designations are L (Left PLL)
[LOC]_GPLL[T, C]_IN
—
and R (Right PLL). T = true and C = complement.
Optional Feedback (PLL) input pads: [LOC] indicates location. Valid designations are L (Left
[LOC]_GPLL[T, C]_FB
—
PLL) and R (Right PLL). T = true and C = complement.
PCLK [n]_[2:0]
—
Primary Clock pads. One to three clock pads per side.
Test and Programming (Dual function pins used for test access port and during sysCONFIG™)
TMS
I
Test Mode Select input pin, used to control the 1149.1 state machine.
TCK
I
Test Clock input pin, used to clock the 1149.1 state machine.
TDI
I
Test Data input pin, used to load data into the device using an 1149.1 state machine.
TDO
O
Output pin – Test Data output pin used to shift data out of the device using 1149.1.
Optionally controls behavior of TDI, TDO, TMS, TCK. If the device is configured to use the
JTAG pins (TDI, TDO, TMS, TCK) as general purpose I/O, then:
If JTAGENB is low: TDI, TDO, TMS and TCK can function a general purpose I/O.
JTAGENB
I
If JTAGENB is high: TDI, TDO, TMS and TCK function as JTAG pins.
For more details, refer to MachXO3 Programming and Configuration Usage Guide (FPGA-TN02055).
Configuration (Dual function pins used during sysCONFIG)
PROGRAMN
I
Initiates configuration sequence when asserted low. This pin always has an active pull-up.
Open Drain pin. Indicates the FPGA is ready to be configured. During configuration, a pull-up
INITN
I/O
is enabled.
Open Drain pin. Indicates that the configuration sequence is complete, and the start-up
DONE
I/O
sequence is in progress.
Input Configuration Clock for configuring an FPGA in Slave SPI mode. Output Configuration
MCLK/CCLK
I/O
Clock for configuring an FPGA in SPI and SPIm configuration modes.
SN
I
Slave SPI active low chip select input.
CSSPIN
I/O
Master SPI active low chip select output.
SI/SPISI
I/O
Slave SPI serial data input and master SPI serial data output.
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
74
FPGA-DS-02032-3.1
MachXO3 Family Data Sheet
Data Sheet
Signal Name
SO/SPISO
SCL
SDA
4.1.
I/O
I/O
I/O
I/O
Descriptions
Slave SPI serial data output and master SPI serial data input.
Slave I2C clock input and master I2C clock output.
Slave I2C data input and master I2C data output.
Pin Information Summary
Table 4.2. MachXO3L/LF-640 and MachXO3L/LF-1300 Pin Summary
General Purpose I/O per Bank
Bank 0
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
Total General Purpose Single Ended I/O
Minimum Reserved for Configuration*
Maximum Programmable Single Ended I/O
Differential I/O per Bank
Bank 0
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
Total General Purpose Differential I/O
Dual Function I/O
Number 7:1 or 8:1 Gearboxes
Number of 7:1 or 8:1 Output Gearbox Available (Bank 0)
Number of 7:1 or 8:1 Input Gearbox Available (Bank 2)
High-speed Differential Outputs
Bank 0
VCCIO Pins
Bank 0
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
VCC
GND
NC
Total Count of Bonded Pins
*Note: One pin for JTAGENB or four pins for JTAG.
MachXO3L/
LF-640
CSFBGA121
WLCSP36
CSFBGA121
CSFBGA256
CABGA256
25
26
26
24
0
0
101
1
100
16
0
9
4
0
0
29
1
28
25
26
26
24
0
0
101
1
100
51
52
52
16
16
20
207
1
206
51
52
52
16
16
20
207
1
206
12
13
13
11
0
0
49
33
8
0
4
2
0
0
14
25
12
13
13
11
0
0
49
33
25
26
26
8
8
10
103
33
25
26
26
8
8
10
103
33
7
7
3
2
7
7
14
14
14
14
7
3
7
14
14
1
1
1
3
0
0
4
10
0
121
1
0
1
1
0
0
2
2
0
36
1
1
1
3
0
0
4
10
0
121
4
3
4
2
2
2
8
24
0
256
4
4
4
1
2
1
8
24
1
256
MachXO3L/LF-1300
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02032-3.1
75
MachXO3 Family Data Sheet
Data Sheet
Table 4.3. MachXO3L/LF-2100 Pin Summary
WLCSP49
General Purpose I/O per Bank
Bank 0
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
Total General Purpose Single Ended I/O
Minimum Reserved for Configuration*
Maximum Programmable Single Ended I/O
Differential I/O per Bank
Bank 0
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
Total General Purpose Differential I/O
Dual Function I/O
Number 7:1 or 8:1 Gearboxes
Number of 7:1 or 8:1 Output Gearbox Available
(Bank 0)
Number of 7:1 or 8:1 Input Gearbox Available
(Bank 2)
High-speed Differential Outputs
Bank 0
VCCIO Pins
Bank 0
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
VCC
GND
NC
Total Count of Bonded Pins
*Note: One pin for JTAGENB or four pins for JTAG.
MachXO3L/LF-2100
CSFBGA121 CSFBGA256 CSFBGA324 CABGA256 CABGA324
20
0
13
0
0
6
39
1
38
25
26
26
7
7
10
101
1
100
51
52
52
16
16
20
207
1
206
72
62
72
22
14
27
269
1
268
51
52
52
16
16
20
207
1
206
72
68
72
24
16
28
280
1
279
10
0
6
0
0
3
19
25
12
13
13
3
3
5
49
33
25
26
26
8
8
10
103
33
36
30
36
10
6
13
131
37
25
26
26
8
8
10
103
33
36
34
36
12
8
14
140
37
5
7
14
18
14
18
6
13
14
18
14
18
5
7
14
18
14
18
2
0
1
0
0
1
2
4
0
49
1
1
1
1
1
1
4
10
0
121
4
3
4
2
2
2
8
24
0
256
4
4
4
2
2
2
8
16
13
324
4
4
4
1
2
1
8
24
1
256
4
4
4
2
2
2
10
16
0
324
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
76
FPGA-DS-02032-3.1
MachXO3 Family Data Sheet
Data Sheet
Table 4.4. MachXO3L/LF-4300 Pin Summary
WLCSP81
General Purpose I/O per Bank
Bank 0
30
Bank 1
0
Bank 2
20
Bank 3
7
Bank 4
0
Bank 5
7
Total General Purpose
64
Single Ended I/O
Minimum Reserved for
1
Configuration*
Maximum Programmable Single
63
Ended I/O
Differential I/O per Bank
Bank 0
15
Bank 1
0
Bank 2
10
Bank 3
3
Bank 4
0
Bank 5
3
Total General Purpose
31
Differential I/O
Dual Function I/O
25
Number 7:1 or 8:1 Gearboxes
Number of 7:1 or 8:1 Output
10
Gearboxes Available (Bank 0)
Number of 7:1 or 8:1 Input
10
Gearboxes Available (Bank 2)
High-speed Differential Outputs
Bank 0
10
VCCIO Pins
Bank 0
3
Bank 1
0
Bank 2
2
Bank 3
1
Bank 4
0
Bank 5
1
VCC
4
GND
6
NC
0
Total Count of Bonded Pins
81
*Note: One pin for JTAGENB or four pins for JTAG.
CSFBGA121
MachXO3L/LF-4300
CSFBGA256 CSFBGA324 CABGA256
CABGA324
CABGA400
25
26
26
7
7
10
51
52
52
16
16
20
72
62
72
22
14
27
51
52
52
16
16
20
72
68
72
24
16
28
84
84
84
28
24
32
101
207
269
207
280
336
1
1
1
1
1
1
100
206
268
206
279
335
12
13
13
3
3
5
25
26
26
8
8
10
36
30
36
10
6
13
25
26
26
8
8
10
36
34
36
12
8
14
42
42
42
14
12
16
49
103
131
103
140
168
37
37
37
37
37
37
7
18
18
18
18
21
13
18
18
18
18
21
7
18
18
18
18
21
1
1
1
1
1
1
4
10
0
121
4
3
4
2
2
2
8
24
0
256
4
4
4
2
2
2
8
16
13
324
4
4
4
1
2
1
8
24
1
256
4
4
4
2
2
2
10
16
0
324
5
5
5
2
2
2
10
33
0
400
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02032-3.1
77
MachXO3 Family Data Sheet
Data Sheet
Table 4.5. MachXO3L/LF-6900 Pin Summary
CSFBGA256
General Purpose I/O per Bank
Bank 0
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
Total General Purpose Single Ended I/O
Minimum Reserved for Configuration*
Maximum Programmable Single Ended I/O
Differential I/O per Bank
Bank 0
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
Total General Purpose Differential I/O
Dual Function I/O
Number 7:1 or 8:1 Gearboxes
Number of 7:1 or 8:1 Output Gearbox Available (Bank 0)
Number of 7:1 or 8:1 Input Gearbox Available (Bank 2)
High-speed Differential Outputs
Bank 0
VCCIO Pins
Bank 0
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
VCC
GND
NC
Total Count of Bonded Pins
*Note: One pin for JTAGENB or four pins for JTAG.
MachXO3L/LF-6900
CSFBGA324
CABGA256 CABGA324
CABGA400
51
52
52
16
16
20
207
1
206
74
68
72
24
16
28
282
1
281
51
52
52
16
16
20
207
1
206
72
68
72
24
16
28
280
1
279
84
84
84
28
24
32
336
1
335
25
26
26
8
8
10
103
37
36
34
36
12
8
14
140
37
25
26
26
8
8
10
103
37
36
34
36
12
8
14
140
37
42
42
42
14
12
16
168
37
20
20
21
21
20
20
21
21
21
21
20
21
20
21
21
4
3
4
2
2
2
8
24
0
256
4
4
4
2
2
2
8
16
0
324
4
4
4
1
2
1
8
24
1
256
4
4
4
2
2
2
10
16
0
324
5
5
5
2
2
2
10
33
0
400
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
78
FPGA-DS-02032-3.1
MachXO3 Family Data Sheet
Data Sheet
Table 4.6. MachXO3L/LF-9400C Pin Summary
CSFBGA256
General Purpose I/O per Bank
Bank 0
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
Total General Purpose Single Ended I/O
Minimum Reserved for Configuration*
Maximum Programmable Single Ended I/O
Differential I/O per Bank
Bank 0
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
Total General Purpose Differential I/O
Dual Function I/O
Number 7:1 or 8:1 Gearboxes
Number of 7:1 or 8:1 Output Gearbox Available (Bank 0)
Number of 7:1 or 8:1 Input Gearbox Available (Bank 2)
High-speed Differential Outputs
Bank 0
VCCIO Pins
Bank 0
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
VCC
GND
NC
Total Count of Bonded Pins
*Note: One pin for JTAGENB or four pins for JTAG.
MachXO3L/LF-9400C
CABGA256
CABGA400
CABGA484
51
52
52
16
16
20
207
1
206
51
52
52
16
16
20
207
1
206
84
84
84
28
24
32
336
1
335
96
96
96
36
24
36
384
1
383
25
26
26
8
8
10
103
37
25
26
26
8
8
10
103
37
42
42
42
14
12
16
168
37
48
48
48
18
12
18
192
45
20
20
20
20
22
22
24
24
20
20
21
24
4
3
4
2
2
2
8
24
0
256
4
4
4
1
2
1
8
24
1
256
5
5
5
2
2
2
10
33
0
400
9
9
9
3
3
3
12
52
0
484
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02032-3.1
79
MachXO3 Family Data Sheet
Data Sheet
5. MachXO3 Part Number Description
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
80
FPGA-DS-02032-3.1
MachXO3 Family Data Sheet
Data Sheet
6. Ordering Information
LCMXO3L/LF devices have top-side markings as shown in the examples below for the 256-Ball caBGA package with
MachXO3-6900 device in Commercial Temperature in Speed Grade 5. Notice that for the MachXO3LF device, LMXO3LF
is used instead of LCMXO3LF as in the Part Number.
Note: Markings are abbreviated for small packages. MachXO3L WLSC packages (UWG) are dual speed grade marked 5C-5I.
LAMXO3LF devices have top-side markings as shown in the examples below:
Markings for the 324-ball caBGA package with LAMXO3LF-4300C device in Automotive Temperature in Speed Grade 5
6.1.
MachXO3L Ultra Low Power Commercial and Industrial Grade Devices,
Halogen Free (RoHS) Packaging
Part Number
LUTs
Supply Voltage
Speed
Package
Leads
Temp.
LCMXO3L-640E-5MG121C
LCMXO3L-640E-6MG121C
LCMXO3L-640E-5MG121I
640
640
640
1.2 V
1.2 V
1.2 V
5
6
5
Halogen-Free csfBGA
Halogen-Free csfBGA
Halogen-Free csfBGA
121
121
121
COM
COM
IND
LCMXO3L-640E-6MG121I
640
1.2 V
6
Halogen-Free csfBGA
121
IND
Part Number
LUTs
Supply Voltage
Speed
Package
Leads
Temp.
LCMXO3L-1300E-5UWG36CTR
LCMXO3L-1300E-5UWG36CTR50
1300
1300
1.2 V
1.2 V
5
5
Halogen-Free WLCSP
Halogen-Free WLCSP
36
36
COM
COM
LCMXO3L-1300E-5UWG36CTR1K
LCMXO3L-1300E-5UWG36ITR
LCMXO3L-1300E-5UWG36ITR50
1300
1300
1300
1.2 V
1.2 V
1.2 V
5
5
5
Halogen-Free WLCSP
Halogen-Free WLCSP
Halogen-Free WLCSP
36
36
36
COM
IND
IND
LCMXO3L-1300E-5UWG36ITR1K
LCMXO3L-1300E-5MG121C
1300
1300
1.2 V
1.2 V
5
5
Halogen-Free WLCSP
Halogen-Free csfBGA
36
121
IND
COM
LCMXO3L-1300E-6MG121C
LCMXO3L-1300E-5MG121I
LCMXO3L-1300E-6MG121I
1300
1300
1300
1.2 V
1.2 V
1.2 V
6
5
6
Halogen-Free csfBGA
Halogen-Free csfBGA
Halogen-Free csfBGA
121
121
121
COM
IND
IND
LCMXO3L-1300E-5MG256C
LCMXO3L-1300E-6MG256C
1300
1300
1.2 V
1.2 V
5
6
Halogen-Free csfBGA
Halogen-Free csfBGA
256
256
COM
COM
LCMXO3L-1300E-5MG256I
1300
1.2 V
5
Halogen-Free csfBGA
256
IND
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02032-3.1
81
MachXO3 Family Data Sheet
Data Sheet
Part Number
LUTs
Supply Voltage
Speed
Package
Leads
Temp.
LCMXO3L-1300E-6MG256I
LCMXO3L-1300C-5BG256C
LCMXO3L-1300C-6BG256C
1300
1300
1300
1.2 V
2.5 V/3.3 V
2.5 V/3.3 V
6
5
6
Halogen-Free csfBGA
Halogen-Free caBGA
Halogen-Free caBGA
256
256
256
IND
COM
COM
LCMXO3L-1300C-5BG256I
LCMXO3L-1300C-6BG256I
1300
1300
2.5 V/3.3 V
2.5 V/3.3 V
5
6
Halogen-Free caBGA
Halogen-Free caBGA
256
256
IND
IND
Part Number
LCMXO3L-2100E-5UWG49CTR
LUTs
2100
Supply Voltage
1.2 V
Speed
5
Package
Halogen-Free WLCSP
Leads
49
Temp.
COM
LCMXO3L-2100E-5UWG49CTR50
LCMXO3L-2100E-5UWG49CTR1K
LCMXO3L-2100E-5UWG49ITR
2100
2100
2100
1.2 V
1.2 V
1.2 V
5
5
5
Halogen-Free WLCSP
Halogen-Free WLCSP
Halogen-Free WLCSP
49
49
49
COM
COM
IND
LCMXO3L-2100E-5UWG49ITR50
LCMXO3L-2100E-5UWG49ITR1K
2100
2100
1.2 V
1.2 V
5
5
Halogen-Free WLCSP
Halogen-Free WLCSP
49
49
IND
IND
LCMXO3L-2100E-5MG121C
LCMXO3L-2100E-6MG121C
LCMXO3L-2100E-5MG121I
2100
2100
2100
1.2 V
1.2 V
1.2 V
5
6
5
Halogen-Free csfBGA
Halogen-Free csfBGA
Halogen-Free csfBGA
121
121
121
COM
COM
IND
LCMXO3L-2100E-6MG121I
LCMXO3L-2100E-5MG256C
2100
2100
1.2 V
1.2 V
6
5
Halogen-Free csfBGA
Halogen-Free csfBGA
121
256
IND
COM
LCMXO3L-2100E-6MG256C
LCMXO3L-2100E-5MG256I
LCMXO3L-2100E-6MG256I
2100
2100
2100
1.2 V
1.2 V
1.2 V
6
5
6
Halogen-Free csfBGA
Halogen-Free csfBGA
Halogen-Free csfBGA
256
256
256
COM
IND
IND
LCMXO3L-2100E-5MG324C
LCMXO3L-2100E-6MG324C
LCMXO3L-2100E-5MG324I
2100
2100
2100
1.2 V
1.2 V
1.2 V
5
6
5
Halogen-Free csfBGA
Halogen-Free csfBGA
Halogen-Free csfBGA
324
324
324
COM
COM
IND
LCMXO3L-2100E-6MG324I
LCMXO3L-2100C-5BG256C
2100
2100
1.2 V
2.5 V/3.3 V
6
5
Halogen-Free csfBGA
Halogen-Free caBGA
324
256
IND
COM
LCMXO3L-2100C-6BG256C
LCMXO3L-2100C-5BG256I
LCMXO3L-2100C-6BG256I
2100
2100
2100
2.5 V/3.3 V
2.5 V/3.3 V
2.5 V/3.3 V
6
5
6
Halogen-Free caBGA
Halogen-Free caBGA
Halogen-Free caBGA
256
256
256
COM
IND
IND
LCMXO3L-2100C-5BG324C
LCMXO3L-2100C-6BG324C
2100
2100
2.5 V/3.3 V
2.5 V/3.3 V
5
6
Halogen-Free caBGA
Halogen-Free caBGA
324
324
COM
COM
LCMXO3L-2100C-5BG324I
LCMXO3L-2100C-6BG324I
2100
2100
2.5 V/3.3 V
2.5 V/3.3 V
5
6
Halogen-Free caBGA
Halogen-Free caBGA
324
324
IND
IND
Part Number
LCMXO3L-4300E-5UWG81CTR
LCMXO3L-4300E-5UWG81CTR50
LUTs
4300
4300
Supply Voltage
1.2 V
1.2 V
Speed
5
5
Package
Halogen-Free WLCSP
Halogen-Free WLCSP
Leads
81
81
Temp.
COM
COM
LCMXO3L-4300E-5UWG81CTR1K
LCMXO3L-4300E-5UWG81ITR
4300
4300
1.2 V
1.2 V
5
5
Halogen-Free WLCSP
Halogen-Free WLCSP
81
81
COM
IND
LCMXO3L-4300E-5UWG81ITR50
LCMXO3L-4300E-5UWG81ITR1K
LCMXO3L-4300E-5MG121C
4300
4300
4300
1.2 V
1.2 V
1.2 V
5
5
5
Halogen-Free WLCSP
Halogen-Free WLCSP
Halogen-Free csfBGA
81
81
121
IND
IND
COM
LCMXO3L-4300E-6MG121C
LCMXO3L-4300E-5MG121I
4300
4300
1.2 V
1.2 V
6
5
Halogen-Free csfBGA
Halogen-Free csfBGA
121
121
COM
IND
LCMXO3L-4300E-6MG121I
LCMXO3L-4300E-5MG256C
LCMXO3L-4300E-6MG256C
4300
4300
4300
1.2 V
1.2 V
1.2 V
6
5
6
Halogen-Free csfBGA
Halogen-Free csfBGA
Halogen-Free csfBGA
121
256
256
IND
COM
COM
LCMXO3L-4300E-5MG256I
4300
1.2 V
5
Halogen-Free csfBGA
256
IND
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
82
FPGA-DS-02032-3.1
MachXO3 Family Data Sheet
Data Sheet
Part Number
LUTs
Supply Voltage
Speed
Package
Leads
Temp.
LCMXO3L-4300E-6MG256I
LCMXO3L-4300E-5MG324C
LCMXO3L-4300E-6MG324C
4300
4300
4300
1.2 V
1.2 V
1.2 V
6
5
6
Halogen-Free csfBGA
Halogen-Free csfBGA
Halogen-Free csfBGA
256
324
324
IND
COM
COM
LCMXO3L-4300E-5MG324I
LCMXO3L-4300E-6MG324I
LCMXO3L-4300C-5BG256C
4300
4300
4300
1.2 V
1.2 V
2.5 V/3.3 V
5
6
5
Halogen-Free csfBGA
Halogen-Free csfBGA
Halogen-Free caBGA
324
324
256
IND
IND
COM
LCMXO3L-4300C-6BG256C
LCMXO3L-4300C-5BG256I
4300
4300
2.5 V/3.3 V
2.5 V/3.3 V
6
5
Halogen-Free caBGA
Halogen-Free caBGA
256
256
COM
IND
LCMXO3L-4300C-6BG256I
LCMXO3L-4300C-5BG324C
LCMXO3L-4300C-6BG324C
4300
4300
4300
2.5 V/3.3 V
2.5 V/3.3 V
2.5 V/3.3 V
6
5
6
Halogen-Free caBGA
Halogen-Free caBGA
Halogen-Free caBGA
256
324
324
IND
COM
COM
LCMXO3L-4300C-5BG324I
LCMXO3L-4300C-6BG324I
4300
4300
2.5 V/3.3 V
2.5 V/3.3 V
5
6
Halogen-Free caBGA
Halogen-Free caBGA
324
324
IND
IND
LCMXO3L-4300C-5BG400C
LCMXO3L-4300C-6BG400C
LCMXO3L-4300C-5BG400I
4300
4300
4300
2.5 V/3.3 V
2.5 V/3.3 V
2.5 V/3.3 V
5
6
5
Halogen-Free caBGA
Halogen-Free caBGA
Halogen-Free caBGA
400
400
400
COM
COM
IND
LCMXO3L-4300C-6BG400I
4300
2.5 V/3.3 V
6
Halogen-Free caBGA
400
IND
Part Number
LCMXO3L-6900E-5MG256C
LCMXO3L-6900E-6MG256C
LUTs
6900
6900
Supply Voltage
1.2 V
1.2 V
Speed
5
6
Package
Halogen-Free csfBGA
Halogen-Free csfBGA
Leads
256
256
Temp.
COM
COM
LCMXO3L-6900E-5MG256I
LCMXO3L-6900E-6MG256I
LCMXO3L-6900E-5MG324C
6900
6900
6900
1.2 V
1.2 V
1.2 V
5
6
5
Halogen-Free csfBGA
Halogen-Free csfBGA
Halogen-Free csfBGA
256
256
324
IND
IND
COM
LCMXO3L-6900E-6MG324C
LCMXO3L-6900E-5MG324I
6900
6900
1.2 V
1.2 V
6
5
Halogen-Free csfBGA
Halogen-Free csfBGA
324
324
COM
IND
LCMXO3L-6900E-6MG324I
LCMXO3L-6900C-5BG256C
LCMXO3L-6900C-6BG256C
6900
6900
6900
1.2 V
2.5 V/3.3 V
2.5 V/3.3 V
6
5
6
Halogen-Free csfBGA
Halogen-Free caBGA
Halogen-Free caBGA
324
256
256
IND
COM
COM
LCMXO3L-6900C-5BG256I
LCMXO3L-6900C-6BG256I
6900
6900
2.5 V/3.3 V
2.5 V/3.3 V
5
6
Halogen-Free caBGA
Halogen-Free caBGA
256
256
IND
IND
LCMXO3L-6900C-5BG324C
LCMXO3L-6900C-6BG324C
LCMXO3L-6900C-5BG324I
6900
6900
6900
2.5 V/3.3 V
2.5 V/3.3 V
2.5 V/3.3 V
5
6
5
Halogen-Free caBGA
Halogen-Free caBGA
Halogen-Free caBGA
324
324
324
COM
COM
IND
LCMXO3L-6900C-6BG324I
LCMXO3L-6900C-5BG400C
LCMXO3L-6900C-6BG400C
6900
6900
6900
2.5 V/3.3 V
2.5 V/3.3 V
2.5 V/3.3 V
6
5
6
Halogen-Free caBGA
Halogen-Free caBGA
Halogen-Free caBGA
324
400
400
IND
COM
COM
LCMXO3L-6900C-5BG400I
LCMXO3L-6900C-6BG400I
6900
6900
2.5 V/3.3 V
2.5 V/3.3 V
5
6
Halogen-Free caBGA
Halogen-Free caBGA
400
400
IND
IND
Part Number
LCMXO3L-9400E-5MG256C
LUTs
9400
Supply Voltage
1.2 V
Speed
5
Package
Halogen-Free csfBGA
Leads
256
Temp.
COM
LCMXO3L-9400E-6MG256C
LCMXO3L-9400E-5MG256I
9400
9400
1.2 V
1.2 V
6
5
Halogen-Free csfBGA
Halogen-Free csfBGA
256
256
COM
IND
LCMXO3L-9400E-6MG256I
LCMXO3L-9400E-5BG256C
LCMXO3L-9400E-6BG256C
9400
9400
9400
1.2 V
1.2 V
1.2 V
6
5
6
Halogen-Free csfBGA
Halogen-Free caBGA
Halogen-Free caBGA
256
256
256
IND
COM
COM
LCMXO3L-9400E-5BG256I
9400
1.2 V
5
Halogen-Free caBGA
256
IND
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02032-3.1
83
MachXO3 Family Data Sheet
Data Sheet
Part Number
LUTs
Supply Voltage
Speed
Package
Leads
Temp.
LCMXO3L-9400E-6BG256I
LCMXO3L-9400E-5BG400C
LCMXO3L-9400E-6BG400C
9400
9400
9400
1.2 V
1.2 V
1.2 V
6
5
6
Halogen-Free caBGA
Halogen-Free caBGA
Halogen-Free caBGA
256
400
400
IND
COM
COM
LCMXO3L-9400E-5BG400I
LCMXO3L-9400E-6BG400I
LCMXO3L-9400E-5BG484C
9400
9400
9400
1.2 V
1.2 V
1.2 V
5
6
5
Halogen-Free caBGA
Halogen-Free caBGA
Halogen-Free caBGA
400
400
484
IND
IND
COM
LCMXO3L-9400E-6BG484C
LCMXO3L-9400E-5BG484I
9400
9400
1.2 V
1.2 V
6
5
Halogen-Free caBGA
Halogen-Free caBGA
484
484
COM
IND
LCMXO3L-9400E-6BG484I
LCMXO3L-9400C-5BG256C
LCMXO3L-9400C-6BG256C
9400
9400
9400
1.2 V
2.5 V/3.3 V
2.5 V/3.3 V
6
5
6
Halogen-Free caBGA
Halogen-Free caBGA
Halogen-Free caBGA
484
256
256
IND
COM
COM
LCMXO3L-9400C-5BG256I
LCMXO3L-9400C-6BG256I
9400
9400
2.5 V/3.3 V
2.5 V/3.3 V
5
6
Halogen-Free caBGA
Halogen-Free caBGA
256
256
IND
IND
LCMXO3L-9400C-5BG400C
LCMXO3L-9400C-6BG400C
LCMXO3L-9400C-5BG400I
9400
9400
9400
2.5 V/3.3 V
2.5 V/3.3 V
2.5 V/3.3 V
5
6
5
Halogen-Free caBGA
Halogen-Free caBGA
Halogen-Free caBGA
400
400
400
COM
COM
IND
LCMXO3L-9400C-6BG400I
LCMXO3L-9400C-5BG484C
9400
9400
2.5 V/3.3 V
2.5 V/3.3 V
6
5
Halogen-Free caBGA
Halogen-Free caBGA
400
484
IND
COM
LCMXO3L-9400C-6BG484C
LCMXO3L-9400C-5BG484I
LCMXO3L-9400C-6BG484I
9400
9400
9400
2.5 V/3.3 V
2.5 V/3.3 V
2.5 V/3.3 V
6
5
6
Halogen-Free caBGA
Halogen-Free caBGA
Halogen-Free caBGA
484
484
484
COM
IND
IND
6.2.
MachXO3LF Ultra Low Power Commercial and Industrial Grade Devices,
Halogen Free (RoHS) Packaging
Part Number
LCMXO3LF-640E-5MG121C
LCMXO3LF-640E-6MG121C
LUTs
640
640
Supply Voltage
1.2 V
1.2 V
Speed
5
6
Package
Halogen-Free csfBGA
Halogen-Free csfBGA
Leads
121
121
Temp.
COM
COM
LCMXO3LF-640E-5MG121I
LCMXO3LF-640E-6MG121I
640
640
1.2 V
1.2 V
5
6
Halogen-Free csfBGA
Halogen-Free csfBGA
121
121
IND
IND
Part Number
LCMXO3LF-1300E-5UWG36CTR
LUTs
1300
Supply Voltage
1.2 V
Speed
5
Package
Halogen-Free WLCSP
Leads
36
Temp.
COM
LCMXO3LF-1300E-5UWG36CTR50
LCMXO3LF-1300E-5UWG36CTR1K
LCMXO3LF-1300E-5UWG36ITR
1300
1300
1300
1.2 V
1.2 V
1.2 V
5
5
5
Halogen-Free WLCSP
Halogen-Free WLCSP
Halogen-Free WLCSP
36
36
36
COM
COM
IND
LCMXO3LF-1300E-5UWG36ITR50
LCMXO3LF-1300E-5UWG36ITR1K
1300
1300
1.2 V
1.2 V
5
5
Halogen-Free WLCSP
Halogen-Free WLCSP
36
36
IND
IND
LCMXO3LF-1300E-5MG121C
LCMXO3LF-1300E-6MG121C
LCMXO3LF-1300E-5MG121I
1300
1300
1300
1.2 V
1.2 V
1.2 V
5
6
5
Halogen-Free csfBGA
Halogen-Free csfBGA
Halogen-Free csfBGA
121
121
121
COM
COM
IND
LCMXO3LF-1300E-6MG121I
LCMXO3LF-1300E-5MG256C
LCMXO3LF-1300E-6MG256C
1300
1300
1300
1.2 V
1.2 V
1.2 V
6
5
6
Halogen-Free csfBGA
Halogen-Free csfBGA
Halogen-Free csfBGA
121
256
256
IND
COM
COM
LCMXO3LF-1300E-5MG256I
LCMXO3LF-1300E-6MG256I
1300
1300
1.2 V
1.2 V
5
6
Halogen-Free csfBGA
Halogen-Free csfBGA
256
256
IND
IND
LCMXO3LF-1300C-5BG256C
1300
2.5 V/3.3 V
5
Halogen-Free caBGA
256
COM
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
84
FPGA-DS-02032-3.1
MachXO3 Family Data Sheet
Data Sheet
Part Number
LUTs
Supply Voltage
Speed
Package
Leads
Temp.
LCMXO3LF-1300C-6BG256C
LCMXO3LF-1300C-5BG256I
LCMXO3LF-1300C-6BG256I
1300
1300
1300
2.5 V/3.3 V
2.5 V/3.3 V
2.5 V/3.3 V
6
5
6
Halogen-Free caBGA
Halogen-Free caBGA
Halogen-Free caBGA
256
256
256
COM
IND
IND
Part Number
LCMXO3LF-2100E-5UWG49CTR
LUTs
2100
Supply Voltage
1.2 V
Speed
5
Package
Halogen-Free WLCSP
Leads
49
Temp.
COM
LCMXO3LF-2100E-5UWG49CTR50
LCMXO3LF-2100E-5UWG49CTR1K
2100
2100
1.2 V
1.2 V
5
5
Halogen-Free WLCSP
Halogen-Free WLCSP
49
49
COM
COM
LCMXO3LF-2100E-5UWG49ITR
LCMXO3LF-2100E-5UWG49ITR50
LCMXO3LF-2100E-5UWG49ITR1K
2100
2100
2100
1.2 V
1.2 V
1.2 V
5
5
5
Halogen-Free WLCSP
Halogen-Free WLCSP
Halogen-Free WLCSP
49
49
49
IND
IND
IND
LCMXO3LF-2100E-5MG121C
LCMXO3LF-2100E-6MG121C
2100
2100
1.2 V
1.2 V
5
6
Halogen-Free csfBGA
Halogen-Free csfBGA
121
121
COM
COM
LCMXO3LF-2100E-5MG121I
LCMXO3LF-2100E-6MG121I
LCMXO3LF-2100E-5MG256C
2100
2100
2100
1.2 V
1.2 V
1.2 V
5
6
5
Halogen-Free csfBGA
Halogen-Free csfBGA
Halogen-Free csfBGA
121
121
256
IND
IND
COM
LCMXO3LF-2100E-6MG256C
LCMXO3LF-2100E-5MG256I
2100
2100
1.2 V
1.2 V
6
5
Halogen-Free csfBGA
Halogen-Free csfBGA
256
256
COM
IND
LCMXO3LF-2100E-6MG256I
LCMXO3LF-2100E-5MG324C
LCMXO3LF-2100E-6MG324C
2100
2100
2100
1.2 V
1.2 V
1.2 V
6
5
6
Halogen-Free csfBGA
Halogen-Free csfBGA
Halogen-Free csfBGA
256
324
324
IND
COM
COM
LCMXO3LF-2100E-5MG324I
LCMXO3LF-2100E-6MG324I
LCMXO3LF-2100C-5BG256C
2100
2100
2100
1.2 V
1.2 V
2.5 V/3.3 V
5
6
5
Halogen-Free csfBGA
Halogen-Free csfBGA
Halogen-Free caBGA
324
324
256
IND
IND
COM
LCMXO3LF-2100C-6BG256C
LCMXO3LF-2100C-5BG256I
2100
2100
2.5 V/3.3 V
2.5 V/3.3 V
6
5
Halogen-Free caBGA
Halogen-Free caBGA
256
256
COM
IND
LCMXO3LF-2100C-6BG256I
LCMXO3LF-2100C-5BG324C
LCMXO3LF-2100C-6BG324C
2100
2100
2100
2.5 V/3.3 V
2.5 V/3.3 V
2.5 V/3.3 V
6
5
6
Halogen-Free caBGA
Halogen-Free caBGA
Halogen-Free caBGA
256
324
324
IND
COM
COM
LCMXO3LF-2100C-5BG324I
LCMXO3LF-2100C-6BG324I
2100
2100
2.5 V/3.3 V
2.5 V/3.3 V
5
6
Halogen-Free caBGA
Halogen-Free caBGA
324
324
IND
IND
Part Number
LCMXO3LF-4300E-5UWG81CTR
LUTs
4300
Supply Voltage
1.2 V
Speed
5
Package
Halogen-Free WLCSP
Leads
81
Temp.
COM
LCMXO3LF-4300E-5UWG81CTR50
LCMXO3LF-4300E-5UWG81CTR1K
LCMXO3LF-4300E-5UWG81ITR
4300
4300
4300
1.2 V
1.2 V
1.2 V
5
5
5
Halogen-Free WLCSP
Halogen-Free WLCSP
Halogen-Free WLCSP
81
81
81
COM
COM
IND
LCMXO3LF-4300E-5UWG81ITR50
LCMXO3LF-4300E-5UWG81ITR1K
4300
4300
1.2 V
1.2 V
5
5
Halogen-Free WLCSP
Halogen-Free WLCSP
81
81
IND
IND
LCMXO3LF-4300E-5MG121C
LCMXO3LF-4300E-6MG121C
LCMXO3LF-4300E-5MG121I
4300
4300
4300
1.2 V
1.2 V
1.2 V
5
6
5
Halogen-Free csfBGA
Halogen-Free csfBGA
Halogen-Free csfBGA
121
121
121
COM
COM
IND
LCMXO3LF-4300E-6MG121I
LCMXO3LF-4300E-5MG256C
4300
4300
1.2 V
1.2 V
6
5
Halogen-Free csfBGA
Halogen-Free csfBGA
121
256
IND
COM
LCMXO3LF-4300E-6MG256C
LCMXO3LF-4300E-5MG256I
LCMXO3LF-4300E-6MG256I
4300
4300
4300
1.2 V
1.2 V
1.2 V
6
5
6
Halogen-Free csfBGA
Halogen-Free csfBGA
Halogen-Free csfBGA
256
256
256
COM
IND
IND
LCMXO3LF-4300E-5MG324C
4300
1.2 V
5
Halogen-Free csfBGA
324
COM
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02032-3.1
85
MachXO3 Family Data Sheet
Data Sheet
Part Number
LUTs
Supply Voltage
Speed
Package
Leads
Temp.
LCMXO3LF-4300E-6MG324C
LCMXO3LF-4300E-5MG324I
LCMXO3LF-4300E-6MG324I
4300
4300
4300
1.2 V
1.2 V
1.2 V
6
5
6
Halogen-Free csfBGA
Halogen-Free csfBGA
Halogen-Free csfBGA
324
324
324
COM
IND
IND
LCMXO3LF-4300C-5BG256C
LCMXO3LF-4300C-6BG256C
LCMXO3LF-4300C-5BG256I
4300
4300
4300
2.5 V/3.3 V
2.5 V/3.3 V
2.5 V/3.3 V
5
6
5
Halogen-Free caBGA
Halogen-Free caBGA
Halogen-Free caBGA
256
256
256
COM
COM
IND
LCMXO3LF-4300C-6BG256I
LCMXO3LF-4300C-5BG324C
4300
4300
2.5 V/3.3 V
2.5 V/3.3 V
6
5
Halogen-Free caBGA
Halogen-Free caBGA
256
324
IND
COM
LCMXO3LF-4300C-6BG324C
LCMXO3LF-4300C-5BG324I
LCMXO3LF-4300C-6BG324I
4300
4300
4300
2.5 V/3.3 V
2.5 V/3.3 V
2.5 V/3.3 V
6
5
6
Halogen-Free caBGA
Halogen-Free caBGA
Halogen-Free caBGA
324
324
324
COM
IND
IND
LCMXO3LF-4300C-5BG400C
LCMXO3LF-4300C-6BG400C
4300
4300
2.5 V/3.3 V
2.5 V/3.3 V
5
6
Halogen-Free caBGA
Halogen-Free caBGA
400
400
COM
COM
LCMXO3LF-4300C-5BG400I
LCMXO3LF-4300C-6BG400I
4300
4300
2.5 V/3.3 V
2.5 V/3.3 V
5
6
Halogen-Free caBGA
Halogen-Free caBGA
400
400
IND
IND
Part Number
LCMXO3LF-6900E-5MG256C
LUTs
6900
Supply Voltage
1.2 V
Speed
5
Package
Halogen-Free csfBGA
Leads
256
Temp.
COM
LCMXO3LF-6900E-6MG256C
LCMXO3LF-6900E-5MG256I
LCMXO3LF-6900E-6MG256I
6900
6900
6900
1.2 V
1.2 V
1.2 V
6
5
6
Halogen-Free csfBGA
Halogen-Free csfBGA
Halogen-Free csfBGA
256
256
256
COM
IND
IND
LCMXO3LF-6900E-5MG324C
LCMXO3LF-6900E-6MG324C
LCMXO3LF-6900E-5MG324I
6900
6900
6900
1.2 V
1.2 V
1.2 V
5
6
5
Halogen-Free csfBGA
Halogen-Free csfBGA
Halogen-Free csfBGA
324
324
324
COM
COM
IND
LCMXO3LF-6900E-6MG324I
LCMXO3LF-6900C-5BG256C
6900
6900
1.2 V
2.5 V/3.3 V
6
5
Halogen-Free csfBGA
Halogen-Free caBGA
324
256
IND
COM
LCMXO3LF-6900C-6BG256C
LCMXO3LF-6900C-5BG256I
LCMXO3LF-6900C-6BG256I
6900
6900
6900
2.5 V/3.3 V
2.5 V/3.3 V
2.5 V/3.3 V
6
5
6
Halogen-Free caBGA
Halogen-Free caBGA
Halogen-Free caBGA
256
256
256
COM
IND
IND
LCMXO3LF-6900C-5BG324C
LCMXO3LF-6900C-6BG324C
6900
6900
2.5 V/3.3 V
2.5 V/3.3 V
5
6
Halogen-Free caBGA
Halogen-Free caBGA
324
324
COM
COM
LCMXO3LF-6900C-5BG324I
LCMXO3LF-6900C-6BG324I
LCMXO3LF-6900C-5BG400C
6900
6900
6900
2.5 V/3.3 V
2.5 V/3.3 V
2.5 V/3.3 V
5
6
5
Halogen-Free caBGA
Halogen-Free caBGA
Halogen-Free caBGA
324
324
400
IND
IND
COM
LCMXO3LF-6900C-6BG400C
LCMXO3LF-6900C-5BG400I
LCMXO3LF-6900C-6BG400I
6900
6900
6900
2.5 V/3.3 V
2.5 V/3.3 V
2.5 V/3.3 V
6
5
6
Halogen-Free caBGA
Halogen-Free caBGA
Halogen-Free caBGA
400
400
400
COM
IND
IND
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
86
FPGA-DS-02032-3.1
MachXO3 Family Data Sheet
Data Sheet
Part Number
LUTs
Supply Voltage
Speed
Package
Leads
Temp.
LCMXO3LF-9400E-5MG256C
LCMXO3LF-9400E-6MG256C
LCMXO3LF-9400E-5MG256I
9400
9400
9400
1.2 V
1.2 V
1.2 V
5
6
5
Halogen-Free csfBGA
Halogen-Free csfBGA
Halogen-Free csfBGA
256
256
256
COM
COM
IND
LCMXO3LF-9400E-6MG256I
LCMXO3LF-9400E-5BG256C
LCMXO3LF-9400E-6BG256C
9400
9400
9400
1.2 V
1.2 V
1.2 V
6
5
6
Halogen-Free csfBGA
Halogen-Free caBGA
Halogen-Free caBGA
256
256
256
IND
COM
COM
LCMXO3LF-9400E-5BG256I
LCMXO3LF-9400E-6BG256I
9400
9400
1.2 V
1.2 V
5
6
Halogen-Free caBGA
Halogen-Free caBGA
256
256
IND
IND
LCMXO3LF-9400E-5BG400C
LCMXO3LF-9400E-6BG400C
LCMXO3LF-9400E-5BG400I
9400
9400
9400
1.2 V
1.2 V
1.2 V
5
6
5
Halogen-Free caBGA
Halogen-Free caBGA
Halogen-Free caBGA
400
400
400
COM
COM
IND
LCMXO3LF-9400E-6BG400I
LCMXO3LF-9400E-5BG484C
9400
9400
1.2 V
1.2 V
6
5
Halogen-Free caBGA
Halogen-Free caBGA
400
484
IND
COM
LCMXO3LF-9400E-6BG484C
LCMXO3LF-9400E-5BG484I
LCMXO3LF-9400E-6BG484I
9400
9400
9400
1.2 V
1.2 V
1.2 V
6
5
6
Halogen-Free caBGA
Halogen-Free caBGA
Halogen-Free caBGA
484
484
484
COM
IND
IND
LCMXO3LF-9400C-5BG256C
LCMXO3LF-9400C-6BG256C
9400
9400
2.5 V/3.3 V
2.5 V/3.3 V
5
6
Halogen-Free caBGA
Halogen-Free caBGA
256
256
COM
COM
LCMXO3LF-9400C-5BG256I
LCMXO3LF-9400C-6BG256I
LCMXO3LF-9400C-5BG400C
9400
9400
9400
2.5 V/3.3 V
2.5 V/3.3 V
2.5 V/3.3 V
5
6
5
Halogen-Free caBGA
Halogen-Free caBGA
Halogen-Free caBGA
256
256
400
IND
IND
COM
LCMXO3LF-9400C-6BG400C
LCMXO3LF-9400C-5BG400I
LCMXO3LF-9400C-6BG400I
9400
9400
9400
2.5 V/3.3 V
2.5 V/3.3 V
2.5 V/3.3 V
6
5
6
Halogen-Free caBGA
Halogen-Free caBGA
Halogen-Free caBGA
400
400
400
COM
IND
IND
LCMXO3LF-9400C-5BG484C
LCMXO3LF-9400C-6BG484C
9400
9400
2.5 V/3.3 V
2.5 V/3.3 V
5
6
Halogen-Free caBGA
Halogen-Free caBGA
484
484
COM
COM
LCMXO3LF-9400C-5BG484I
LCMXO3LF-9400C-6BG484I
9400
9400
2.5 V/3.3 V
2.5 V/3.3 V
5
6
Halogen-Free caBGA
Halogen-Free caBGA
484
484
IND
IND
6.3.
MachXO3LF Ultra Low Power Automotive Grade Devices, Halogen Free
(RoHS) Packaging
Part Number
LUTs
Supply Voltage
Speed
Package
Leads
Temp.
LAMXO3LF-1300E-5BG256E
LAMXO3LF-1300C-5BG256E
LAMXO3LF-2100E-5BG256E
1300
1300
2100
1.2
3.3
1.2
5
5
5
Halogen-Free caBGA
Halogen-Free caBGA
Halogen-Free caBGA
256
256
256
AUTO
AUTO
AUTO
LAMXO3LF-2100C-5BG256E
LAMXO3LF-2100E-5BG324E
2100
2100
3.3
1.2
5
5
Halogen-Free caBGA
Halogen-Free caBGA
256
324
AUTO
AUTO
LAMXO3LF-2100C-5BG324E
LAMXO3LF-4300E-5BG256E
LAMXO3LF-4300C-5BG256E
2100
4300
4300
3.3
1.2
3.3
5
5
5
Halogen-Free caBGA
Halogen-Free caBGA
Halogen-Free caBGA
324
256
256
AUTO
AUTO
AUTO
LAMXO3LF-4300E-5BG324E
LAMXO3LF-4300C-5BG324E
4300
4300
1.2
3.3
5
5
Halogen-Free caBGA
Halogen-Free caBGA
324
324
AUTO
AUTO
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02032-3.1
87
MachXO3 Family Data Sheet
Data Sheet
References
A variety of technical notes for the MachXO3 family are available on the Lattice web site.
• MachXO3 sysCLOCK PLL Design and Usage Guide (FPGA-TN-02058)
• Implementing High-Speed Interfaces with MachXO3 Devices (FPGA-TN-02057)
• MachXO3 sysI/O Usage Guide (FPGA-TN-02047)
• MachXO3 Programming and Configuration Usage Guide (FPGA-TN-02055)
• PCB Layout Recommendations for BGA Packages (FPGA-TN-02024)
• Minimizing System Interruption During Configuration Using TransFR Technology (FPGA-TN-02025)
• Boundary Scan Testability with Lattice sysI/O Capability (AN8066)
• MachXO3 Device Pinout File
• Thermal Management (FPGA-TN-02044)
• Lattice Design Tools
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
88
FPGA-DS-02032-3.1
MachXO3 Family Data Sheet
Data Sheet
Revision History
Revision 3.1, July 2021
Section
Architecture
DC and Switching Characteristics
Change Summary
Removed RSDS from Table 2.11 and Table 2.12.
•
•
•
Updated Table 3.16.
Replaced note 4 below Table 3.11 to better clarify the voltage specs for I/Os with mixed
voltage support.
Updated Table 3.17.
Revision 3.0, June 2021
Section
Architecture
—
Change Summary
Added a graphical MUX symbol in Figure 2.13. Input Gearbox.
Minor editorial and style changes.
Revision 2.9, April 2021
Section
DC and Switching Characteristics
Change Summary
Updated Table 3.6. Programming/Erase Specifications. Indicated MachXO3L and MachXO3LF
in NPROGCYC parameter.
Revision 2.8, January 2021
Section
Acronyms in This Document
Introduction
Architecture
DC and Switching Characteristics
MachXO3 Part Number
Description
Ordering Information
Change Summary
Added items.
•
In Features section:
•
Indicated 10,000 write/erase cycle for automotive.
•
Indicated on-chip oscillator with 5.5% accuracy is for commercial/industrial
devices.
•
Updated Table 1.1. MachXO3L/LF Family Selection Guide.
Indicated 10,000 write/erase cycle for automotive in the User Flash Memory (UFM) section.
•
•
•
Added automotive data in Table 3.4. Power-On Reset Voltage Levels.
Updated tRETENTION values in Table 3.6. Programming/Erase Specifications.
Added automotive data and updated IPU values in Table 3.7. DC Electrical
Characteristics.
•
Added VINP, VINM, and VOS rows for automotive in Table 3.12. LVDS.
•
Added automotive data in Table 3.21. MachXO3L/LF External Switching Characteristics
– C/E Devices.
•
Indicated commercial/industrial and automotive data in Table 3.22. sysCLOCK PLL
Timing.
•
Added Oscillator Output Frequency section.
•
Added automotive data inTable 3.25. JTAG Port Timing Specifications.
•
Added automotive data in Table 3.26. sysCONFIG Port Timing Specifications.
Fixed error in device family names. Changed LCMXO3X and LAMXO3X to LCMXO3 and
LAMXO3 under Device Family.
•
•
Removed marking for LAMX3LF-13.
Updated the MachXO3LF Ultra Low Power Automotive Grade Devices, Halogen Free
(RoHS) PackagingMachXO3LF Ultra Low Power Automotive Grade Devices, Halogen
Free (RoHS) Packaging section.
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02032-3.1
89
MachXO3 Family Data Sheet
Data Sheet
Revision 2.7, October 2020
Section
Ordering Information
Change Summary
Updated the MachXO3LF Ultra Low Power Automotive Grade Devices, Halogen Free (RoHS)
Packaging section.
Revision 2.6, September 2020
Section
All
Change Summary
•
•
Added automotive data.
Minor formatting changes.
DC and Switching Characteristics
•
•
Corrected footnotes in Table 3.6. Programming/Erase Specifications.
Added Automotive values to the following tables:
•
Table 3.3. Power Supply Ramp Rates
•
Table 3.4. Power-On Reset Voltage Levels
•
Table 3.6. Programming/Erase Specifications
•
Table 3.7. DC Electrical Characteristics
•
Table 3.21. MachXO3L/LF External Switching Characteristics – C/E Devices
•
Table 3.24. JTAG Port Timing Specifications
•
Table 3.25. sysCONFIG Port Timing Specifications
Updated TSU Min value for -5 Commercial/Industrial in Table 3.21. MachXO3L/LF
External Switching Characteristics – C/E Devices. Changes were applied under Generic
DDRX1 Inputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input –
GDDRX1_RX.SCLK.Centered and Generic DDRX2 Inputs with Clock and Data Centered at
Pin Using PCLK Pin for Clock Input – GDDRX2_RX.ECLK.Centered.
•
Revision 2.5, March 2020
Section
Disclaimers
Architecture
Change Summary
Added this section.
•
•
Added the MachXO3LF to MachXO3L Low Cost Migration Path section.
Removed last paragraph from the Typical I/O Behavior during Power-up section.
DC and Switching Characteristics
•
•
•
Added NVCM Programming cycles and Flash Feature Row Programming Cycles to Table
3.6.
Added clarification to "Blank Pattern" in footnote to Table 3.9.
Added footnote to clarify VCCIO in Table 3.12.
•
•
Added rows and footnote to clarify configuration usage in Table 4.1 thru Table 4.6.
Added "Pin Summary" to table captions for clarity.
Signal Descriptions
Revision 2.4, February 2019
Section
Architecture
Change Summary
Updated Figure 2.12. Output Register Block Diagram (PIO on the Left, Top and Bottom
Edges) caption.
Revision 2.3, November 2018
Section
Architecture
References
Change Summary
Clarified PCI support in the following sections and tables:
•
Programmable I/O Cells (PIC)Programmable I/O Cells (PIC)
•
sysI/O Buffer
•
Table 2.11. Supported Input Standards
•
Table 2.12. Supported Output Standards
Updated PCB Layout Recommendations for BGA Packages document number to FPGA-TN02024.
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
90
FPGA-DS-02032-3.1
MachXO3 Family Data Sheet
Data Sheet
Revision 2.2, October 2018
Section
Introduction
Architecture
Ordering Information
All
Change Summary
•
Added Device Options to Table 1.1. MachXO3L/LF Family Selection Guide.
•
Updated footnotes.
General update to Table 2.11. Supported Input Standards
•
Corrected BG256 packages for 1300 LUT parts.
•
Added information on dual marking for MachXO3L WLCS packages.
Minor formatting changes.
Revision 2.1, March 2018
Section
DC and Switching Characteristics
Ordering Information
Revision History
Change Summary
Removed extraneous TJAUTO specification from Table 3.2 Recommended Operating
Conditions.
Restored MachXO3LF Ultra Low Power Commercial and Industrial Grade Devices, Halogen
Free (RoHS) Packaging section back to the Ordering Information section.
Restored Revision History contents for Revision 1.6 and prior back to this Revision History
section.
Revision 2.0, January 2018
Section
All
Change Summary
•
•
•
Applied new company template.
Changed document number fron DS1047 to FPGA-DS-02032.
Fixed various reference links.
DC and Switching Characteristics
•
•
Added Programming/Erase Specifications section. Clarified Write/Erase cycle.
Removed unnecessary C2 Dedicated Input Capacitance specification from the DC
Electrical Characteristics section.
Added note to the NVCM/Flash Download Time section to clarify maximum tREFRESH
time.
•
Revision 1.9, October 2017
Section
Introduction
Change Summary
•
•
•
•
•
•
•
Architecture
•
•
DC and Switching Characteristics
•
•
•
•
Updated Features section. Changed Advanced Packaging feature to “0.5 mm pitch: 640
to 9.4K LUT densities....”
Updated Table 1.1, MachXO3L Family Selection Guide.
Added footnotes to MachXO3L-6900/MachXO3LF-6900 and MachXO3L9400/MachXO3LF-9400 LUTs.
Added UFM (kbits, MachXO3LF only) feature.
Moved footnotes from packages to corresponding I/O values in 256- ball caBGA, 400ball caBGA and 484-ball caBGA.
Updated footnote 2.
Added footnotes 3 and 4.
Updated User Flash Memory (UFM) section. Changed feature to “Non-volatile storage
up to 448 kbits”.
Updated Standby Mode and Power Saving Options section. Updated the title of TN1289
reference.
Updated Absolute Maximum Ratings section. Added footnote 6.
Updated Static Supply Current – C/E Devices section.
Updated the title of TN1289 reference in footnote 1.
Removed footnote 7. Updated Programming and Erase Supply Current – C/E Devices
section. Updated the title of TN1289 reference in footnote 1
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02032-3.1
91
MachXO3 Family Data Sheet
Data Sheet
Section
Ordering Information
Change Summary
•
•
Updated the MachXO3L Ultra Low Power Commercial and Industrial Grade Devices,
Halogen Free (RoHS) Packaging section. Added MachXO3L-9600E part numbers.
Updated the MachXO3LF Ultra Low Power Commercial and Industrial Grade Devices,
Halogen Free (RoHS) Packaging section. Added MachXO3LF-9600E part numbers.
Revision 1.8, February 2017
Section
Architecture
Change Summary
•
•
Updated Supported Standards section.
Corrected “MDVS” to “MLDVS” in Table 2.11, Supported Input Standards.
DC and Switching Characteristics
•
Updated ESD Performance section. Added reference to the MachXO2 Product Family
Qualification Summary document.
Updated Static Supply Current – C/E Devices section. Added footnote 7.
Updated MachXO3L/LF External Switching Characteristics – C/E Devices section.
Populated values for MachXO3L/LF-9400.
Under 7:1 LVDS Outputs – GDDR71_TX.ECLK.7:1, corrected “tDVB” to “tDIB” and
“tDVA” to “tDIA” and revised their descriptions.
Added Figure 3-6, Receiver GDDR71_RX Waveforms and Figure 3-7, Transmitter
GDDR71_TX Waveforms.
•
•
•
•
•
Pinout Information
•
Updated the Pin Information Summary section. Added MachXO3L/LF- 9600C packages.
Revision 1.7, May 2016
Section
DC and Switching Characteristics
Change Summary
•
•
•
•
•
•
•
Ordering Information
•
•
Updated Absolute Maximum Ratings section. Modified I/O Tri-state Voltage Applied
and Dedicated Input Voltage Applied footnotes.
Updated sysI/O Recommended Operating Conditions section.
Added standards.
Added VREF (V)
Added footnote 4.
Updated sysI/O Single-Ended DC Electrical Characteristics section.
Added I/O standards.
Updated MachXO3L Ultra Low Power Commercial and Industrial Grade Devices,
Halogen Free (RoHS) Packaging section. Added LCMXO3L- 9400C part numbers.
Updated MachXO3LF Ultra Low Power Commercial and Industrial Grade Devices,
Halogen Free (RoHS) Packaging section. Added LCMXO3L- 9400C part numbers.
Revision 1.6, April 2016
Section
Introduction
Change Summary
•
•
•
•
•
•
•
Updated Features section.
Revised logic density range and I/O to LUT ratio under Flexible Architecture.
Revised 0.8 mm pitch information under Advanced Packaging.
Added MachXO3L-9400/MachXO3LF-9400 information to Table 1-1, MachXO3L/LF
Family Selection Guide.
Updated Introduction section.
Changed density from 6900 to 9400 LUTs.
Changed caBGA packaging to 19 x 19 mm.
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
92
FPGA-DS-02032-3.1
MachXO3 Family Data Sheet
Data Sheet
Section
Architecture
Change Summary
DC and Switching Characteristics
•
Pinout Information
Ordering Information
•
•
•
•
•
•
•
•
•
Updated Architecture Overview section.
Changed statement to “All logic density devices in this family...”
Updated Figure 2-2 heading and notes.
Updated sysCLOCK Phase Locked Loops (PLLs) section.
Changed statement to “All MachXO3L/LF devices have one or more sysCLOCK PLL.”
Updated Programmable I/O Cells (PIC) section.
Changed statement to “All PIO pairs can implement differential receivers.”
Updated sysI/O Buffer Banks section. Updated Figure 2-5 heading.
Updated Device Configuration section. Added Password and Soft Error Correction.
Updated Static Supply Current – C/E Devices section. Added LCMXO3L/LF-9400C and
LCMXO3L/LF-9400E devices.
•
Updated Programming and Erase Supply Current – C/E Devices section.
•
Added LCMXO3L/LF-9400C and LCMXO3L/LF-9400E devices.
•
Changed LCMXO3L/LF-640E and LCMXO3L/LF-1300E Typ. values.
•
Updated MachXO3L/LF External Switching Characteristics – C/E Devices section. Added
MachXO3L/LF-9400 devices.
•
Updated NVCM/Flash Download Time section. Added LCMXO3L/LF-9400C device.
•
Updated sysCONFIG Port Timing Specifications section.
•
Added LCMXO3L/LF-9400C device.
•
Changed tINITL units to from ns to us.
•
Changed tDPPINIT and tDPPDONE Max. values are per PCN#03A-16.
Updated Pin Information Summary section. Added LCMXO3L/LF-9400C device.
•
•
•
•
•
Updated MachXO3 Part Number Description section.
Added 9400 = 9400 LUTs.
Added BG484 package.
Updated MachXO3L Ultra Low Power Commercial and Industrial Grade Devices,
Halogen Free (RoHS) Packaging section. Added LCMXO3L-9400C part numbers.
Updated MachXO3LF Ultra Low Power Commercial and Industrial Grade Devices,
Halogen Free (RoHS) Packaging section. Added LCMXO3L-9400C part numbers.
Revision 1.5, September 2015
Section
DC and Switching Characteristics
Change Summary
•
•
•
•
•
Updated the MIPI D-PHY Emulation section. Revised Table 3-5, MIPI DPHY Output DC
Conditions.
Revised RL Typ. value.
Revised RH description and values.
Updated the Maximum sysI/O Buffer Performance section. Revised MIPI Max. Speed
value.
Updated the MachXO3L/LF External Switching Characteristics – C/E Devices section.
Added footnotes 14 and 15.
Revision 1.4, August 2015
Section
Architecture
Change Summary
Updated the Device Configuration section. Added JTAGENB to TAP dual purpose pins.
Ordering Information
Updated the top side markings section to indicate the use of LMXO3LF for the LCMXO3LF
device.
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02032-3.1
93
MachXO3 Family Data Sheet
Data Sheet
Revision 1.3, March 2015
Section
All
Change Summary
General update. Added MachXO3LF devices.
Revision 1.2, August 2015
Section
Introduction
Architecture
DC and Switching Characteristics
Change Summary
Updated Table 1-1, MachXO3L Family Selection Guide. Revised XO3L-2100 and XO3L-4300
I/O for 324-ball csfBGA package.
Updated the Dual Boot section. Corrected information on where the primary bitstream and
the golden image must reside.
•
•
•
Pinout Information
•
•
•
•
•
•
Updated the BLVDS section. Changed output impedance nominal values in Table 3-2,
BLVDS DC Condition.
Updated the LVPECL section. Changed output impedance nominal value in Table 3-3,
LVPECL DC Condition.
Updated the sysCONFIG Port Timing Specifications section. Updated INITN low time
values.
Changed General Purpose I/O Bank 5 values for MachXO3L-2100 and MachXO3L-4300
CSFBGA 324 package.
Changed Number 7:1 or 8:1 Gearboxes for MachXO3L-640 and MachXO3L-1300.
Removed DQS Groups (Bank 1) section.
Changed VCCIO Pins Bank 1 values for MachXO3L-1300, MachXO3L-2100, MachXO3L4300 and MachXO3L-6900 CSFBGA 256 package.
Changed GND values for MachXO3L-1300, MachXO3L-2100, MachXO3L-4300 and
MachXO3L-6900 CSFBGA 256 package.
Changed NC values for MachXO3L-2100 and MachXO3L-4300 CSFBGA 324 package.
Revision 1.1, July 2014
Section
DC and Switching Characteristics
Pinout Information
Ordering Information
Change Summary
•
•
Updated the Static Supply Current – C/E Devices section. Added devices.
Updated the Programming and Erase Supply Current – C/E Device section. Added
devices.
•
Updated the sysI/O Single-Ended DC Electrical Characteristics section. Revised footnote
4.
•
Added the NVCM Download Time section.
•
Updated the Typical Building Block Function Performance – C/E Devices section. Added
information to footnote.
Updated the Pin Information Summary section.
•
•
Updated the MachXO3L Part Number Description section. Added packages.
Updated the Ordering Information section. General update.
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
94
FPGA-DS-02032-3.1
MachXO3 Family Data Sheet
Data Sheet
Revision 1.0, June 2014
Section
Introduction
Change Summary
•
•
Architecture
Updated Features section.
Updated Table 1-1, MachXO3L Family Selection Guide. Changed fcCSP packages to
csfBGA. Adjusted 121-ball csfBGA arrow.
•
Introduction section general update.
General update.
DC and Switching Characteristics
•
•
•
•
•
•
Updated sysI/O Recommended Operating Conditions section. Removed VREF (V)
column. Added standards.
Updated Maximum sysI/O Buffer Performance section. Added MIPI I/O standard.
Updated MIPI D-PHY Emulation section. Changed Low Speed to Low Power. Updated
Table 3-4, MIPI DC Conditions.
Updated Table 3-5, MIPI D-PHY Output DC Conditions.
Updated Maximum sysI/O Buffer Performance section.
Updated MachXO3L External Switching Characteristics – C/E Device section.
Revision 00.3, May 2014
Section
Introduction
Architecture
Change Summary
•
Updated Features section.
•
Updated Table 1-1, MachXO3L Family Selection Guide. Moved 121-ball fcCSP arrow.
•
General update of Introduction section.
General update.
Pinout Information
Updated Pin Information Summary section. Updated or added data on WLCSP49, WLCSP81,
CABGA324, and CABGA400 for specific devices.
Ordering Information
•
•
•
•
•
Updated MachXO3L Part Number Description section. Updated or added data on
WLCSP49, WLCSP81, CABGA324, and CABGA400 for specific devices.
Updated Ultra Low Power Commercial and Industrial Grade Devices, Halogen Free
(RoHS) Packaging section. Added part numbers.
Revision 00.2, February 2014
DC and Switching Characteristics section:
Updated MachXO3L External Switching Characteristics – C/E Devices table. Removed
LPDDR and DDR2 parameters.
Revision 00.2, February 2014
Section
DC and Switching Characteristics
Change Summary
Updated MachXO3L External Switching Characteristics – C/E Devices table. Removed LPDDR
and DDR2 parameters.
Revision 00.1, February 2014
Section
All
Change Summary
Initial release.
© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02032-3.1
95
www.latticesemi.com
工商网监
湘ICP备2023018690号
