MachXO3L Starter Kit
User Guide
November 2014
EB95_1.0
MachXO3L Starter Kit User Guide
Introduction
Thank you for choosing the Lattice Semiconductor MachXO3L Starter Kit!
This user’s guide describes how to start using the MachXO3L Starter Kit, an easy-to-use platform for evaluating
and designing with the MachXO3L ultra-low density FPGA. Along with the board and accessories, this kit includes
a pre-loaded demonstration design. You may also reprogram the on-board MachXO3L device to review your own
custom designs.
The MachXO3L Starter Kit currently features the MachXO3L-6900C device in the 256-ball 0.8 mm pitch caBGA
package.
See the Ordering Information section for more information.
Note: Static electricity can severely shorten the lifespan of electronic components. See the Storage and Handling
section of this document for handling and storage tips.
Features
The MachXO3L Starter Kit includes:
• MachXO3L Board – The board is a 3” x 3” form factor that features the following on-board components and circuits:
— MachXO3L FPGA – LCMXO3L-6900C-5BG256C
— USB mini-B connector for power and programming
— Eight LEDs
— 4-position DIP switch
— Momentary push button switch
— 40-hole prototype area
— Four 2 x 20 expansion header landings for general I/O, JTAG, and external power
— 1 x 8 expansion header landing for JTAG
— 1 x 6 expansion header landing for SPI/I2C
— 3.3 V and 1.2 V supply rails
• Pre-loaded Demo – The kit includes a pre-loaded counter design that highlights use of the embedded
MachXO3L oscillator and programmable I/Os configured for LED drive.
• USB Connector Cable – The board is powered from the USB mini-B socket when connected to a host PC. The
USB channel also provides a programming interface to the MachXO3L JTAG port.
• Lattice Development Kits and Boards Web Page – Visit www.latticesemi.com/breakoutboards for the latest
documentation (including this guide) and drivers for the kit.
The content of this user’s guide includes demo operation, programming instructions, top-level functional descriptions of the Starter Kit, descriptions of the on-board connectors, and a complete set of schematics.
2
MachXO3L Starter Kit User Guide
Figure 1. MachXO3L Board, Top Side
Two 2 x 20 Header
Landings (J3, J4)
JTAG Header
Landing (J1)
LED array
(D9-D2)
SPI/I2C Header
Landing (J7)
MachXO3L PLD
(U5)
4 x 10 40-Hole
Prototype array
USB Mini-B
Socket (J2)
4-Position DIP
Switch (SW2)
Power LED,
Blue (D1)
Push Button
Switch (SW1)
FTDI USB to
UART/FIFO IC (U1)
Two 2 x 20 Header
Landings (J6, J8)
Storage and Handling
Static electricity can shorten the lifespan of electronic components. Please observe these tips to prevent damage
that could occur from electro-static discharge:
• Use anti-static precautions such as operating on an anti-static mat and wearing an anti-static wrist-band.
• Store the evaluation board in the packaging provided.
• Touch a metal USB housing to equalize voltage potential between you and the board.
Software Requirements
You should install the following software before you begin developing new designs for the Starter Kit:
• Lattice Diamond® design software
• FTDI Chip USB hardware drivers (installed as an option within the Diamond installation program)
MachXO3L Device
This board currently features the MachXO3L-6900C FPGA which offers embedded Non-Volatile Configuration
Memory (NVCM) technology for instant-on operation in a single chip. Numerous system functions are included,
such as two PLLs and 256 kbits of embedded RAM plus hardened implementations of I2C and SPI. Flexible, high
performance I/Os support numerous single-ended and differential standards including LVDS. The 256-ball BGA
package provides up to 206 user I/Os in a 14 mm x 14 mm form factor. A complete description of this device can be
found in the MachXO3 Family Data Sheet.
3
MachXO3L Starter Kit User Guide
Demonstration Design
Lattice provides a simple, pre-programmed demo to illustrate basic operation of the MachXO3L device. The design
integrates an up-counter with the on-chip oscillator.
Note: To restore the factory default demo and program it with other Lattice-supplied examples see the Download
Demo Designs section of this document.
Run the Demonstration Design
Upon power-up, the preprogrammed demonstration design automatically loads and drives the LED array in a 1-hertz
pattern. The program shows a clock divider driven either by the MachXO3L internal oscillator or the external FTDI
clock chip. The divider modules (heartbeat.v and kitcar.v) are clocked at the default frequency of 12 MHz which
divides the clock to cycle the LED display approximately once per second. The resulting light pattern is determined by
the DIP Switch (SW2) setting as shown in Table 1.
Figure 2. Demonstration Design Block Diagram
MachXO3L
XO3L_SK_blink.v
OSCH
12.09 MHz
Kitcar.v
Heartbeat.v
1x8
LED
Array
X1
12.0 MHz
SW2
4-Position DIPSW
SW1
Momentary PB
Async Reset
Table 1. DIP Switch Setting and LED Behavior
Switch
Setting
DIP_SW[1]
0 (Down)
External 12.0 MHz (X1)
1 (Up)
Internal 12.09 MHz (OSCH)
001
1 Hz Sweep
011
1 Hz Left-Right
DIP_SW[2:4]
LED Behavior
111
1 Hz Blink
Others
1 Hz Alternating
WARNING: Do not connect the board to your PC before you follow the driver installation procedure of this section.
Communication between the board and a PC via the USB connection cable requires installation of the FTDI chip
USB hardware drivers. Loading these drivers enables the computer to recognize and program the board. Drivers
can be loaded as part of the installation of Lattice Diamond design software or Diamond Programmer, or as a
stand-alone package.
To load the FTDI Chip USB hardware drivers as part of the Lattice Diamond installation:
1. Select Programmer Drivers in the Product Options of Lattice Diamond Setup.
2. Select FTDI Windows USB Driver or All Drivers in the LSC Drivers Install/Uninstall dialog box.
3. Click Finish to install the USB driver.
4
MachXO3L Starter Kit User Guide
4. After the driver installation is complete, connect the USB cable from a USB port on your PC to the board’s USB
mini-B socket (J2). After the connection is made, a blue Power LED (D1) will light indicating the board is powered on.
5. The demonstration design will automatically load and drive the LED array in a repeating pattern.
To load the FTDI chip USB hardware drivers via the stand-alone package on a Windows system:
1. Browse to www.latticesemi.com/breakoutboards and download the FTDI Chip USB Hardware Drivers package.
2. Extract the FTDI chip USB Hardware driver package to your PC hard drive.
3. Connect the USB cable from a USB port on your PC to the board’s USB mini-B socket (J2). After the connection is made, a blue Power LED (D1) will light indicating the board is powered on.
4. If you are prompted, “Windows may connect to Windows Update” select No, not this time from available
options and click Next to proceed with the installation. Choose the Install from specific location (Advanced)
option and click Next.
5. Search for the best driver in these locations and click the Browse button to browse to the Windows driver folder
created in the Download Windows USB Hardware Drivers section. Select the CDM 2.04.06 WHQL Certified
folder and click OK.
6. Click Next. A screen will display as Windows copies the required driver files. Windows will display a message
indicating that the installation was successful.
7. Click Finish to install the USB driver.
8. The demonstration design will automatically load and drive the LED array in a repeating pattern.
See the Troubleshooting section of this guide if the board does not function as expected.
Download Demo Designs
The counter demo is preprogrammed into the board, however over time it is likely your board will be modified. Lattice distributes source and programming files for demonstration designs compatible with the Starter Kit. The demo
design for the board is available on the web.
To download demo designs:
1. Browse to the Lattice Development Kits and Boards web page (www.latticesemi.com/breakoutboards) of the
Lattice web site. Select MachXO3L Starter Kit Demo Source and save the file.
2. Extract the contents of MachXO3L_Starter_Kit.zip to an accessible location on your hard drive.
3. Open the Blink.ldf project file in the Lattice Diamond design software.
4. Run the Process Flow and regenerate the Bitstream file.
Continue to Programming a Demo Design with Lattice Diamond Design Software.
5
MachXO3L Starter Kit User Guide
Programming a Demo Design with the Lattice Diamond Programmer
The demonstration design is pre-programmed into the MachXO3L board by Lattice. If you have changed the design
but now want to restore the board to factory settings, use the procedure described below.
To program the MachXO3L device:
1. Install, license and run Lattice Diamond software. See www.latticesemi.com/latticediamond for download and
licensing information.
2. Connect the USB cable to the host PC and the MachXO3L board.
3. From Diamond, open the Blink.ldf project file.
4. Click the Programmer icon.
5. Click Detect Cable. The Programmer will detect the cable (Cable: USB2, Port: FTUSB-0). If the cable is not
detected, see the Troubleshooting section.
6. Click Device Properties.
7. Change Access Mode to SPI Flash Programming.
8. Choose SPI Flash Background Erase, Program, Verify operation.
9. Select Blink_impl1.bit programming file.
10. Under SPI Flash Options, change Vendor to SPANSION and change Device to SPI-S25FL004D or SPIS25FL204K. Click OK.
11. Click the Program icon. When complete, PASS is displayed in the Status column.
12. Change Access mode to NVCM Programming Mode and NVCM Refresh, then click Program (or powercycle the Starter Kit board) to initiate a re-boot from the SPI flash.
6
MachXO3L Starter Kit User Guide
MachXO3L Starter Kit
This section describes the features of the MachXO3L Starter Kit in detail.
Overview
The Starter Kit is a complete development platform for the MachXO3L FPGA. The board includes a prototyping
area, a USB program/power port, an LED array, switches, and header landings with electrical connections to most
of the FPGA’s programmable I/O, power, and configuration pins. The board is powered by the PC’s USB port or
optionally with external power. You may create or modify the program files and reprogram the board using Lattice
Diamond software.
Figure 3. MachXO3L-6900C Block Diagram
Bank 0
GPIO
USB Mini B
Socket
USB
Controller
2 x 20 Header
Landing (J3)
JTAG
Programming
1 x 8 Header
Landing (J1,
Optional JTAG
Interface)
Bank 1
GPIO
Bank 3, 4 and 5
2 x 20 Header
Landing (J8)
GPIO
2 x 20 Header
Landing (J4)
MachXO3L-6900C device
8
4
DIP_SW
GPIO
2 x 20 Header
Landing (J6)
Bank 2
1 x 6 Header
Landing (J7,
Optional SPI,
I2C Intrfaces)
Bank 0, 2
7
LED
Array
MachXO3L Starter Kit User Guide
Table 2 describes the components on the board and the interfaces it supports.
Table 2. Starter Kit Components and Interfaces
Component/Interface
Schematic
Reference
Type
Description
Circuits
USB Controller
USB Mini-B Socket
Circuit
U1: FT2232H
USB-to-JTAG interface and dual USB UART/FIFO IC
I/O
J2:USB_MINI_B
Programming and debug interface
FPGA
U5: LCMXO3L6900C-5BG256C
6900-LUT device packaged in a 14 mm x14 mm,
256-ball caBGA
Output
Components
LCMXO3L
Interfaces
LED Array
D9-D2
Red LEDs
Push Button Switch
Input
SW1
Momentary User Input
4-position DIP Switch
Input
SW2
User inputs
Four 2 x 20 Header
Landings
I/O
J3: header_2x20
J4: header_2x20
J6: header_2x20
J8: header_2x20
User-definable I/O
1 x 8 Header Landing
I/O
J1: header_1x8
Optional JTAG interface
1 x 6 Header Landing
I/O
J7: header_1x6
Optional SPI/I2C interfaces
4 x 10 40-Hole
Prototype Area
Test Points
Prototype area 100 mil centered holes.
Power
TP1: +3.3 V
TP2: +1.2 V
TP3: GND
Power and ground reference points
Subsystems
This section describes the principle sub systems for the Starter Kit in alphabetical order.
Clock Sources
Clock sources for the LED demonstration designs originate from the MachXO3L on-chip oscillator or the 12 MHz
crystal X1. You may use an expansion header landing to drive a FPGA input with an external clock source.
Expansion Header Landings
The expansion header landings provide access to user GPIOs, primary inputs, clocks, and VCCO pins of the
MachXO3L. The remaining pins serve as power supplies for external connections. Each landing is configured as
one 2 x 20 100 mil.
Table 3. Expansion Connector Reference
Item
Description
Reference Designators
J3, J4, J6, J8
Part Number
header_2x20
8
MachXO3L Starter Kit User Guide
Table 4. Expansion Header Pin Information (J3)
Header Pin Number
–6900C Function
MachXO3L Ball
1
VCCIO0
D5,D12,G8,G9
2
VCCIO0
D5,D12,G8,G9
3
PT36C/INITn
A13
4
PT36D/DONE
C13
5
PT22A
F8
6
PT35B
B12
7
PT35A
C12
8
PT26B
E11
9
PT27B
E10
10
PT27A
D10
11
GND
—
—
F9
C10
E8
E9
E7
D8
D7
C7
—
—
C5
D6
E6
C4
A10
F7
D9
B9
—
—
B6
B7
B5
A5
B4
A4
—
A3
12
GND
13
PT26A
14
PT27C/JTAGENB
15
PT17B
16
PT21B
17
PT14B
18
PT21A
19
PT16B
20
PT15B
21
GND
22
GND
23
PT10B
24
PT14A
25
PT16A
26
PT9A
27
PT25B
28
PT17A
29
PT22B
30
PT25A
31
GND
32
GND
33
PT11B
34
PT15A
35
PT9B
36
PT11A
37
PT12B
38
PT10A
39
GND
40
PT12A
9
MachXO3L Starter Kit User Guide
Table 5. Expansion Header Pin Information (J4)
Header Pin Number
–6900C Function
MachXO3L Ball
1
VCCIO1
E13,H10,J10,M13
2
VCCIO1
E13,H10,J10,M13
3
PR19D
K12
4
PR19C
K13
5
PR23A
M14
6
PR24B
N14
7
PR18B
L14
8
PR24A
N16
9
PR23B
M15
10
PR21B
M16
11
GND
—
—
L15
L16
K14
K16
K15
J14
H14
J15
—
—
J16
H15
H16
G15
G16
F15
F16
E15
—
—
E16
E14
D16
C15
D14
F14
G14
B16
12
GND
13
PR21A
14
PR18A
15
PR17A
16
PR16B
17
PR17B
18
PR15B
19
PR12A/PCLKT1_0
20
PR16A
21
GND
22
GND
23
PR15A
24
PR11B
25
PR12B/PCLKC1_0
26
PR9A
27
PR11A
28
PR5B
29
PR7B
30
PR2B/R_GPLLC_FB
31
GND
32
GND
33
PR5A
34
PR3B/R_GPLLC_IN
35
PR3A/R_GPLLT_IN
36
PR2C
37
PR2A/R_GPLLT_FB
38
PR7A
39
PR9B
40
PR2D
10
MachXO3L Starter Kit User Guide
Table 6. Expansion Header Pin Information (J6)
Header Pin Number
–6900C Function
MachXO3L Ball
1
VCCIO2
K8,K9,N5,N12
2
VCCIO2
K8,K9,N5,N12
3
PB35B
T12
4
PB34B
T14
5
PB35A
R11
6
PB34A
R13
7
PB31A
T11
8
PB28B
M11
9
PB31B
P11
10
PB28A
N10
11
GND
—
—
T10
P10
R9
R10
T9
N9
P9
M8
—
—
T8
L8
P8
M6
R7
R8
P7
T7
—
—
L7
R6
N6
T5
R4
P4
T3
T4
12
GND
13
PB26B
14
PB29A
15
PB26A
16
PB29B
17
PB23A/PCLKT2_1
18
PB21B
19
PB23B/PCLKC2_1
20
PB21A
21
GND
22
GND
23
PB18B
24
PB15B
25
PB18A
26
PB15A
27
PB13A
28
PB16B/PCLKC2_0
29
PB13B
30
PB16A/PCLKT2_0
31
GND
32
GND
33
PB10B
34
PB9B
35
PB10A
36
PB9A
37
PB7B
38
PB4A
39
PB7A
40
PB4B
11
MachXO3L Starter Kit User Guide
Table 7. Expansion Header Pin Information (J8)
Header Pin Number
–6900C Function
MachXO3L Ball
1
VCCIO5
E4
2
VCCIO3
M4
3
PL9D
H6
4
PL25B
N3
5
PL25A
M2
6
PL22B/PCLKC3_0
M1
7
PL22A/PCLKT3_0
L2
8
PL19A
L1
9
PL19B
L3
10
PL19D
L5
11
GND
—
—
K4
J1
K1
J2
J3
H3
H2
H1
—
—
G2
G1
F2
F1
E2
E1
D2
D1
—
C2
C1
G3
B1
D3
E3
F3
F5
H7,J7
12
GND
13
PL19C
14
PL12A/PCLKT4_0
15
PL15B
16
PL15A
17
PL12B/PCLKC4_0
18
PL11A
19
PL10B
20
PL11B
21
GND
22
GND
23
PL9A
24
PL10A
25
PL6B/PCLKC5_0
26
PL8B
27
PL4A/L_GPLLT_IN
28
PL6A/PCLKT5_0
29
PL4D
30
PL3B/L_GPLLC_FB
31
GND
32
PL2D
33
PL4C
34
PL9B
35
PL2C
36
PL3A/L_GPLLT_FB
37
PL4B/L_GPLLC_IN
38
PL8A
39
PL9C
40
VCCIO4
12
MachXO3L Starter Kit User Guide
Figure 4. J3/J4 Header Landing Callout
J3
J4
1
2
VCCIO0 VCCIO0
A13
C13
F8
B12
C12
E11
E10
D10
GND
GND
F9
C10
E8
E9
E7
D8
D7
C7
GND
GND
C5
D6
E6
C4
A10
F7
D9
B9
GND
GND
B6
B7
B5
A5
B4
A4
GND
A3
39
40
1
2
VCCIO1 VCCIO1
K12
K13
M14
N14
L14
N16
M15
M16
GND
GND
L15
L16
K14
K16
K15
J14
H14
J15
GND
GND
J16
H15
H16
G15
G16
F15
F16
E15
GND
GND
E16
E14
D16
C15
D14
F14
G14
B16
39
40
Top Side
J3
J4
Figure 5. J6/J8 Header Landing Callout
Top Side
J6
J8
13
J6
J8
1
2
VCCIO2 VCCIO2
T12
T14
R11
R13
T11
M11
P11
N10
GND
GND
T10
P10
R9
R10
T9
N9
P9
M8
GND
GND
T8
L8
P8
M6
R7
R8
P7
T7
GND
GND
L7
R6
N6
T5
R4
P4
T3
T4
39
40
1
2
VCCIO5 VCCIO3
H6
N3
M2
M1
L2
L1
L3
L5
GND
GND
K4
J1
K1
J2
J3
H3
H2
H1
GND
GND
G2
G1
F2
F1
E2
E1
D2
D1
GND
C2
C1
G3
B1
D3
E3
F3
F5
VCCIO4
39
40
MachXO3L Starter Kit User Guide
Figure 6. J1 Header Landing and LED Array Callout
LED Array
J1
J1
LED
Net
MachXO3L
Ball
D9
D8
D7
D6
D5
D4
D3
D2
LED0
LED1
LED2
LED3
LED4
LED5
LED6
LED7
H11
J13
J11
L12
K11
L13
N15
P16
8
D9
D2
J7
Top Side
TCK
GND
TMS
nc
nc
TDI
TDO
VCCIO0
LCMXO2-7000HE
4TG144C
1
J7
6
DIP_SW1
MCLK
SISPI
SPISO
SN
SCL
SDA
1
DIP_SW4
Net
MachXO3L
Ball
DIP_SW1
DIP_SW2
DIP_SW3
DIP_SW4
H11
J13
J11
L12
MachXO3L FPGA
The LCMXO3L-6900C-5BG256C is a 256-ball caBGA package FPGA device which provides up to 206 usable I/Os
in a 14 mm x 14 mm package. 150 I/Os are accessible from the board headers, switches and LEDs.
Table 8. MachXO3L FPGA Interface Reference
Item
Description
Reference Designators
U5
Part Number
LCMXO3L-6900C-5BG256C
Manufacturer
Lattice Semiconductor
Web Site
www.latticesemi.com
Programming Interface Circuits
For power and programming an FTDI USB UART/FIFO IC converter provides a communication interface between a
PC host and the JTAG programming chain of the Starter Kit. The USB 5 V supply is also used as a source for the
3.3 V supply rail. A USB mini-B socket is provided for the USB connector cable.
Table 9. USB/JTAG Interface Reference
Item
Description
Reference Designators
U1
Part Number
FT2232HL
Manufacturer
Future Technology Devices International (FTDI)
Web Site
www.ftdichip.com
14
MachXO3L Starter Kit User Guide
Table 10. JTAG Programming Pin Information
Description
MachXO3L Pin
Test Data Output
C6:TDO
Test Data Input
A6:TDI
Test Mode Select
B8:TMS
Test Clock
A7:TCK
Table 11. SPI Programming Pin Information
Description
MachXO3L Pin
Master Clock/Config Clock
P6:MCLK/CCLK
Serial Data Input
P13: SI/SISPI
Serial Data Output
T6: SO/SPISO
SPI Slave Select
R12: SN
Table 12. I2C Programming Pin Information
Description
MachXO3L Pin
Serial Data
C9:SDA
Serial Clock
A9:SCL
LEDs
A blue LED (D1) is used to indicate USB 5V power. Eight red LEDs are driven by I/O pins of the MachXO3L device.
Table 13. Power and User LEDs Reference
Item
Description
Reference Designators
Red LEDs (D2, D3, D4, D5, D6, D7, D8, D9)
Blue LEDs (D1)
Part Number
LTST-C190KRKT (D2-D9)
LTST-C190TBKT (D1)
Manufacturer
Lite-On It Corporation
Web Site
www.liteonit.com
Power Supply
3.3 V and 1.2 V power supply rails are converted from the USB 5 V interface when the board is connected to a host
PC.
Test Points
In order to check the various voltage levels used, test points are provided:
• TP1: +3.3 V
• TP2: +1.2 V
• TP3: GND
USB Programming and Debug Interface
The USB mini-B socket of the Starter Kit serves as the programming and debug interface.
JTAG Programming: For JTAG programming, a preprogrammed USB PHY peripheral controller is provided on the
Starter Kit to serve as the programming interface to the MachXO3L FPGA.
Programming requires the Lattice Diamond or ispVM System software.
15
MachXO3L Starter Kit User Guide
Table 14. USB Interface Reference
Item
Description
Reference Designators
U1
Part Number
FT2232HL
Manufacturer
Future Technology Devices International (FTDI)
Web Site
www.ftdichip.com
Board Modifications
This section describes modifications to the board to change or add functionality.
Bypassing the USB Programming Interface
The USB programming interface circuit (USB Programming and Debug Interface section) may be optionally
bypassed by removing the 0 Ohm resistors: R4, R5, R6, R7 (See Appendix A. Schematics, Sheet 2 of 8). Header
landing J1 provides JTAG signal access for jumper wires or a 1 x 8 pin header.
Applying External Power
The Starter Kit is powered by the circuit of Schematic Sheet 3 of 8 based on the 5 V USB power source. You may
disconnect this power source by removing the 0 Ohm resistors: R35 (VCC_1.2 V) and R42 (VCC_3.3 V). Power
connections are available from the test points, TP1 (+3.3 V) and TP2 (+1.2 V).
Measuring Bank and Core Power
Test points (TP1, TP2) provide access to power supplies of the MachXO3L FPGA. Inline 1 Ohm resistors: R31
(VCCIO0, +3.3 V, Bank 0), R25 (VCCIO1, +3.3 V, Bank 1), R37 (VCCIO2, +3.3 V, Bank 2), R32 (VCCIO3, +3.3 V,
Bank 3), R26 (VCCIO4, +3.3 V, Bank 4), R38 (VCCIO5, +3.3 V, Bank 5), R24 (VCC core, +1.2 V) can be used to measure current for the power supplies.
Mechanical Specifications
Dimensions: 3 in. [L] x 3 in. [W] x 1/2 in. [H]
Environmental Requirements
The evaluation board must be stored between –40° C and 100° C. The recommended operating temperature is
between 0° C and 90° C.
The board can be damaged without proper anti-static handling.
Glossary
FPGA: Field Programmable Gate Array
DIP: Dual in-line package
LED: Light Emitting Diode.
LUT: Look Up Table
PCB: Printed Circuit Board
RoHS: Restriction of Hazardous Substances Directive
USB: Universal Serial Bus
WDT: Watchdog Timer
16
MachXO3L Starter Kit User Guide
Troubleshooting
Use the tips in this section to diagnose problems with the Starter Kit.
LEDs Do Not Flash
If power is applied but the board does not flash according to the preprogrammed counter demonstration then it is
likely the board has been reprogrammed with a new design. Follow the directions in the Demonstration Design section to restore the factory default.
USB Cable Not Detected
If Lattice Diamond Programmer or ispVM System does not recognize the USB cable after installing the Lattice USB
port drivers and rebooting, the incorrect USB driver may have been installed. This usually occurs if you attach the
board to your PC prior to installing the Lattice-supplied USB driver.
To access the Troubleshooting the USB Driver Installation Guide:
For Diamond software and standalone Diamond Programmer:
1. Start Diamond or Diamond Programmer and choose Help.
2. Search for USB driver or Troubleshooting, then select the Troubleshooting the USB Driver topic.
3. Follow the directions to install the Lattice USB driver.
For ispVM:
1. Start ispVM System and choose Options > Cable and I/O Port Setup.
The Cable and I/O Port Setup Dialog appears.
2. Click the Troubleshooting the USB Driver Installation Guide link.
The Troubleshooting the USB Driver Installation Guide document appears in your system’s PDF file reader.
3. Follow the directions to install the Lattice USB driver.
Determine the Source of a Pre-Programmed Device
If the Starter Kit has been reprogrammed, the original demo design can be restored. To restore the board to the
factory default, see the Download Demo Designs section for details on downloading and reprogramming the
device.
Ordering Information
Description
MachXO3L Starter Kit
Ordering Part Number
LCMXO3L-6900C-S-EVN
Technical Support Assistance
e-mail:
techsupport@latticesemi.com
Internet: www.latticesemi.com
17
China RoHS Environment-Friendly
Use Period (EFUP)
MachXO3L Starter Kit User Guide
Revision History
Date
Version
November 2014
1.0
Change Summary
Initial release.
© 2014 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as
listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of
their respective holders. The specifications and information herein are subject to change without notice.
18
A
B
C
5
USB
CONNECTOR
Power from USB 5V
USB to
JTAG / RS232
4
SPI
LEDS (1-8)
RS232_I/F
JTAG_I/F
I/O'S
I2C
SPI FLASH
HEADER
HEADER
D
4
BANK-0
HEADER
I/O'S
BANK-4
HEADER
BANK-5
BANK-1
3
LCMXO3L-6900C-5BG256C
BANK-2
3
I/O'S
I/O'S
19
I/O'S
5
2
I/O'S
2
HEADER
Date:
Size
B
12-SEP-14
Project
MACHXO3 Starter Kit - LCMXO3L-6900C
Title
MACHXO3 Starter Kit - BLOCK DIAGRAM
1
Sheet
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
1
1.0
A
Schematic Rev
Board Rev
1
of 8
A
B
C
D
MachXO3L Starter Kit User Guide
Appendix A. Schematics
Figure 7. Block Diagram
BANK-3
A
B
C
0.1uF
C7
CS
CLK
DI
DO
C11
0.1uF
5
93LC56C-I/SN
VCC
NU
ORG
VSS
0.1uF
8
7
6
5
U2
C10
+3.3V
+3.3V
1
2
3
4
0.1uF
C12
10K
R11
+3.3V
10K
R12
12K
0.1uF
C13
10K
R13
0.1uF
C14
R19
4
L2
2
1
600ohm 500mA
Sheet[4]
C8
18pF
12MHZ
0.1uF
10uF
2
1
C6
C5
VCC1_8FT
+3.3V
L1
2
1
600ohm 500mA
3
0
12MHZ
4
3
+3.3V
C3
4.7uF
C1
4.7uF
G1 G2
1
X1
1
2
1
2
+3.3V
R23
R9
2.2K
12K
C9
18pF
FT_EECS
FT_EECLK
FT_EEDATA
R10
Sheet[3]
Sheet[3]
0.1uF
C4
0.1uF
C2
DM
DP
3
3
13
3
2
63
62
61
6
14
7
8
49
50
VCC1_8FT
FT2232H
+3.3V
PWREN#
BCBUS0
BCBUS1
BCBUS2
BCBUS3
BCBUS4
BCBUS5
BCBUS6
BCBUS7
BDBUS0
BDBUS1
BDBUS2
BDBUS3
BDBUS4
BDBUS5
BDBUS6
BDBUS7
ACBUS0
ACBUS1
ACBUS2
ACBUS3
ACBUS4
ACBUS5
ACBUS6
ACBUS7
ADBUS0
ADBUS1
ADBUS2
ADBUS3
ADBUS4
ADBUS5
ADBUS6
ADBUS7
SUSPEND#
FTDI High-Speed USB
TEST
OSCO
OSCI
EECS
EECLK
EEDATA
REF
RESET#
DM
DP
VREGOUT
VREGIN
U1
FT2232HL
AGND
10
D
4
4
9
VPHY
VPLL
12
37
64
VCORE
VCORE
VCORE
20
31
42
56
VCCIO
VCCIO
VCCIO
VCCIO
GND
GND
GND
GND
GND
GND
GND
GND
20
1
5
11
15
25
35
47
51
5
36
60
48
52
53
54
55
57
58
59
2
Title
0
0
0
Date:
Size
B
R14
R15
R16
R17
R18
R20
R21
R22
Sheet[6]
Sheet[6]
Sheet[6]
FTDI_SCL
FTDI_SDA
USB_I2C_EN
12-SEP-14
1
Sheet
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
USB to JTAG I/F
R27
R62
R82
1
RS232_Rx_TTL
Sheet[4]
RS232_Tx_TTL
Sheet[4]
RTSn
Sheet[4]
CTSn
Sheet[4]
DTRn
Sheet[4]
DSRn
Sheet[4]
DCDn
Sheet[4]
RI
Sheet[4]
R8
2.2K
TCK
TMS
TDO
TDI
Project
MACHXO3 Starter Kit - LCMXO3L-6900C
DNI
DNI
DNI
FOR FUTURE I2C FUNCTION
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
0
0
0
0
0
0
0
0
Header 1x8
DNI
4.7K 4.7K 4.7K
FOR FUTURE RS232 FUNCTION
R4
R5
R6
R7
1
2
3
4
5
6
7
8
R3 R1 R2
38
39
40
41
43
44
45
46
0
0
0
0
J1
1
2
3
4
5
6
7
8
VCCIO0
26
27
28
29
30
32
33
34
16
17
18
19
21
22
23
24
2
1.0
A
Schematic Rev
Sheet[4]
Sheet[4]
Sheet[4]
Sheet[4]
Board Rev
2
of 8
TCK
TDI
TDO
TMS
A
B
C
D
MachXO3L Starter Kit User Guide
Figure 8. USB Interface to JTAG
A
B
C
VCC
DD+
ID
GND
D1
Blue
5
1K
R41
1
2
3
4
5
10uF
C17
3
Input
U3
0
IN
U4
Tab
Output
4
2
1
2
4
DM
DP
R42
100
R36
R35
0.1uF
NCP1117
OUT
TAB
GND
0.1uF
FAN1112
3
C16
600ohm 500mA
L3
R30
10uF
C19
VBUS_5V
SKT_MINIUSB_B_RA
J2
1
2
C15
0
0
4
Sheet[2]
Sheet[2]
22uF
C18
2
1
600ohm 500mA
0.1uF
22uF
L4
C21
C20
+1.2V
1
1
TP5
L5
+3.3V
VCC_CORE
1
2
600ohm 500mA
VCC_CORE
DNI
R86
+1.2V
R24
+3.3V
1
D
1
2
3
+3.3V
VCCIO3
DNI
R34
+1.2V
R32
+3.3V
VCCIO0
DNI
R33
+1.2V
R31
+3.3V
3
TP6
TP9
VCCIO3
TP1
C62
1uF
C61
10uF
1
1
1
1
VCCIO0
1
1
1
0.1uF
C63
+3.3V
+1.2V
VCCIO4
VCCIO1
TP7
1
1
VCCIO4
TP10
1
1
TP2
0.01uF
C64
DNI
R29
+1.2V
R26
+3.3V
VCCIO1
DNI
R28
+1.2V
R25
+3.3V
1
1
VBUS_5V
GND
1
1
TP3
VCCIO5
DNI
R40
+1.2V
R38
+3.3V
VCCIO2
DNI
R39
+1.2V
R37
+3.3V
2
2
1
1
1
1
TP8
Date:
Size
B
Title
VCCIO5
TP11
1
12-SEP-14
Project
MACHXO3 Starter Kit - LCMXO3L-6900C
POWER REGULATORS
1
Sheet
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
1.0
A
Schematic Rev
Board Rev
3
of 8
NOTE : Boot from external SPI Flash (U6)
requires VCCIO2 set to 3.3V. Use caution
when setting VCCIO2 to any other voltage.
VCCIO2
1
4
1
21
1
5
A
B
C
D
MachXO3L Starter Kit User Guide
Figure 9. FPGA
22
A
B
C
D
0.01uF
C22
12MHZ
TCK
TMS
TDO
TDI
B7
C7
E6
D7
F7
E8
A7
B8
IO_B7
IO_C7
IO_E6
IO_D7
IO_F7
IO_E8
TCK
TMS
0.1uF
5
C24
0.1uF
D5
D12
D8
E9
C6
A6
TDO
TDI
C8
A8
D6
E7
IO_D6
IO_E7
12MHZ
A3
B4
IO_A3
IO_B4
IO_D8
IO_E9
A5
B6
IO_A5
IO_B6
C23
VCCIO0
Sheet[2]
Sheet[2]
Sheet[2]
Sheet[2]
Sheet[2]
B3
A4
C5
CREST
IO_A4
IO_C5
C4
B5
IO_C4
IO_B5
LCMXO3L-6900C-5BG256C
VCCIO0/VCCIO0/VCCIO0
VCCIO0/VCCIO0/VCCIO0
PT17C/PT19A*/PT21A*
PT17D/PT19B*/PT21B*
PT18A*/PT20A*/PT22A*
PT18B*/PT20B*/PT22B*
PT20A*/PT23A*/PT27A*
PT20B*/PT23B*/PT27B*
PT19C/PT22A*/PT26A*
PT19D/PT22B*/PT26B*
PT19A*/PT21A*/PT25A*
PT19B*/PT21B*/PT25B*
4
1K-2K/4K/7K || 2nd_Fn.
VCCIO0/VCCIO0/VCCIO0
VCCIO0/VCCIO0/VCCIO0
* = TRUE LVDS Output
PT24C/PT28C/PT36C || INITN
PT24D/PT28D/PT36D || DONE
PT24A*/PT28A*/PT36A*
PT24B*/PT28B*/PT36B*
PT23A*/PT27A*/PT35A*
PT23B*/PT27B*/PT35B*
PT22C/PT26A*/PT34A*
PT22D/PT26B*/PT34B*
PT22A*/PT25A*/PT33A*
PT22B*/PT25B*/PT33B*
PT21C/PT24C/PT32A*
PT21D/PT24D/PT32B*
PT21A*/PT24A*/PT28A*
PT21B*/PT24B*/PT28B*
PT20C/PT23C/PT27C || JTAGENB
PT20D/PT23D/PT27D || PROGRAMN
PT17A*/PT18A*/PT18A* || PCLKT0_1
PT17B*/PT18B*/PT18B* || PCLKC0_1
PT16C/PT15C/PT17C || TCK
PT16D/PT15D/PT17D || TMS
PT16A*/PT15A*/PT17A*
PT16B*/PT15B*/PT17B*
PT13C/PT14C/PT16A*
PT13D/PT14D/PT16B*
PT13A*/PT14A*/PT15A*
PT13B*/PT14B*/PT15B*
BANK0
PT18C/PT20C/PT22C || SCL/PCLKT0_0
PT18D/PT20D/PT22D || SDA/PCLKC0_0
PT12C/PT13C/PT14C || TDO
PT12D/PT13D/PT14D || TDI
PT12A*/PT13A*/PT14A*
PT12B*/PT13B*/PT14B*
PT11C/PT12A*/PT12A*
PT11D/PT12B*/PT12B*
PT11A*/PT11A*/PT11A*
PT11B*/PT11B*/PT11B*
PT10A*/PT10A*/PT10A*
PT10B*/PT10B*/PT10B*
PT9C/PT9C/PT9C
PT9A*/PT9A*/PT9A*
PT9B*/PT9B*/PT9B*
U5A
4
G8
G9
A13
C13
B14
A15
C12
B12
B13
A14
B11
A12
F10
D11
A11
C11
C10
B10
D10
E10
F9
E11
B9
A10
A9
C9
F8
D9
0.1uF
C25
INITN
DONE
IO_C12
IO_B12
DCDn
RI
CTSn
DSRn
RTSn
DTRn
49.9
49.9
0.1uF
C26
RS232_Rx_TTL
RS232_Tx_TTL
JTAGENB
PROGRAMN
IO_D10
IO_E10
IO_F9
IO_E11
IO_B9
IO_A10
SCL_1
SDA_1
IO_F8
IO_D9
Sheet[2]
Sheet[2]
Sheet[2]
Sheet[2]
0.1uF
C27
3
VCCIO0
150
150
Sheet[2]
Sheet[2]
TP4
150pF
DNI
C66
R44
2K
VCCIO0
DCDn
Sheet[2]
RI
Sheet[2]
CTSn
DSRn
RTSn
DTRn
RS232_Rx_TTL
RS232_Tx_TTL
150pF
DNI
C65
R87
R88
R43
2K
3
1
5
R90
R89
SCL Sheet[6]
SDA Sheet[6]
2
SYS_RST
SW1
2
Date:
Size
B
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
0.1uF
IO_B6
IO_B5
IO_B4
IO_C5
IO_E6
IO_A10
IO_D9
IO_F9
IO_E8
IO_E7
IO_D7
INITN
IO_F8
IO_C12
IO_E10
VCCIO0
12-SEP-14
Project
MACHXO3 Starter Kit - LCMXO3L-6900C
1
Sheet
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
Header 2x20
J3
CREST
C28
Title
BANK0 I/0
4.7K
R45
VCCIO0
IO_B7
IO_A5
IO_A4
IO_A3
IO_D6
IO_C4
IO_F7
IO_B9
JTAGENB
IO_E9
IO_D8
IO_C7
DONE
IO_B12
IO_E11
IO_D10
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
NOTE : MAKE PWR TRACES
CAPABLE OF 1A
VCCIO0
1
1.0
A
Schematic Rev
Board Rev
of 8
4
A
B
C
D
MachXO3L Starter Kit User Guide
Figure 10. FPGA
23
A
B
C
D
5
LED6
LED7
Sheet[8]
Sheet[8]
0.01uF
C29
LED4
LED5
Sheet[8]
Sheet[8]
0.1uF
N15
P16
LED6
LED7
0.1uF
K11
L13
LED4
LED5
C31
J11
L12
LED2
LED3
E13
H10
P15
R16
J16
J14
H11
J13
LED0
LED1
H13
J12
G11
H12
F12
G13
F13
G12
C16
D15
C15
B16
IO_J16
IO_J14
IO_C15
IO_B16
C30
VCCIO1
LED2
LED3
LED0
LED1
Sheet[8]
Sheet[8]
Sheet[8]
Sheet[8]
5
PR6A/PR9A/PR11A DQS0
PR6B/PR9B/PR11B DQS0N
PR5A/PR8A/PR9A
PR5B/PR8B/PR9B
PR4A/PR6A/PR7A
PR4B/PR6B/PR7B
DQ1
PR14A/PR19A/PR24A
PR14B/PR19B/PR24B
PR13A/PR18A/PR23A
PR13B/PR18B/PR23B
PR12A/PR16A/PR21A
PR12B/PR16B/PR21B
PR11C/PR15C/PR19C
PR11D/PR15D/PR19D
PR11A/PR15A/PR18A
PR11B/PR15B/PR18B
PR10A/PR14A/PR17A
PR10B/PR14B/PR17B
PR9A/PR13A/PR16A DQS1
PR9B/PR13B/PR16B DQS1N
PR7A/PR10A/PR12A || PCLKT1_0
PR7B/PR10B/PR12B || PCLKC1_0
DQ0
PR3A/PR5A/PR5A
PR3B/PR5B/PR5B
PR2A/PR3A/PR3A || R_GPLLT_IN**
PR2B/PR3B/PR3B || R_GPLLC_IN**
PR1A/PR2A/PR2A || R_GPLLT_FB**
PR1B/PR2B/PR2B || R_GPLLC_FB**
BANK1
LCMXO3L-6900C-5BG256C
4
VCCIO1/VCCIO1/VCCIO1
VCCIO1/VCCIO1/VCCIO1
1K-2K/4K/7K || 2nd_Fn.
VCCIO1/VCCIO1/VCCIO1
VCCIO1/VCCIO1/VCCIO1
** = 2nd_Fn. applicable for 4K and 7K devices only.
PR14C/PR20C/PR25C
PR14D/PR20D/PR25D
PR13C/PR18C/PR23C
PR13D/PR18D/PR23D
PR12C/PR16C/PR21C
PR12D/PR16D/PR21D
PR10C/PR14C/PR17C
PR10D/PR14D/PR17D
PR9C/PR13C/PR16C
PR9D/PR13D/PR16D
PR7C/PR10C/PR15A
PR7D/PR10D/PR15B
PR6C/PR9C/PR11C
PR6D/PR9D/PR11D
PR5C/PR8C/PR10C
PR5D/PR8D/PR10D
PR4C/PR6C/PR7C
PR4D/PR6D/PR7D
PR3C/PR5C/PR6C
PR3D/PR5D/PR6D
PR2C/PR4C/PR4C
PR2D/PR4D/PR4D
PR1C/PR2C/PR2C
PR1D/PR2D/PR2D
U5B
4
IO_E16
IO_F15
E16
F15
IO_N16
IO_N14
N16
N14
0.1uF
C32
IO_M14
IO_M15
M14
M15
J10
M13
IO_L15
IO_M16
IO_K13
IO_K12
IO_L16
IO_L14
IO_K14
IO_K15
IO_J15
IO_K16
IO_H14
IO_H16
IO_G16
IO_H15
IO_G15
IO_G14
L15
M16
K13
K12
L16
L14
K14
K15
J15
K16
H14
H16
G16
H15
G15
G14
IO_F14
IO_F16
IO_D16
IO_E14
D16
E14
F14
F16
IO_D14
IO_E15
D14
E15
0.1uF
0.1uF
3
C34
C33
3
VCCIO1
IO_E14
IO_C15
IO_F14
IO_B16
IO_H15
IO_G15
IO_F15
IO_E15
IO_L16
IO_K16
IO_J14
IO_J15
IO_K13
IO_N14
IO_N16
IO_M16
Proto Type Area
J5
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
Header 2x20
J4
VCCIO1
2
Date:
Size
B
Title
Project
MACHXO3 Starter Kit - LCMXO3L-6900C
12-SEP-14
1
1
Sheet
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
IO_E16
IO_D16
IO_D14
IO_G14
IO_J16
IO_H16
IO_G16
IO_F16
IO_L15
IO_K14
IO_K15
IO_H14
IO_K12
IO_M14
IO_L14
IO_M15
BANK1 I/O
PROTOTYPE AREA
FILL AVAILABLE AREA
Proto Type Area, Holes on 0.1 inch Centers
DNI
1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
NOTE : MAKE PWR TRACES
CAPABLE OF 1A
VCCIO1
2
1.0
A
Schematic Rev
Board Rev
5
of 8
A
B
C
D
MachXO3L Starter Kit User Guide
Figure 11. Power LEDs
A
B
C
D
Sheet[4]
Sheet[4]
0
0
MCLK
SPISO
0.1uF
0.1uF
P8
T8
IO_P8
IO_T8
C37
T7
R8
IO_T7
IO_R8
K8
K9
N8
L9
M6
L8
M7
N7
R7
P7
IO_M6
IO_L8
IO_R7
IO_P7
C36
VCCIO2
N6
L7
IO_N6
IO_L7
P6
T6
T5
R6
IO_T5
IO_R6
R81
R83
T3
R4
R5
P5
IO_T3
IO_R4
R84
T2
R3
P4
T4
LCMXO3L-6900C-5BG256C
5
DNI
DNI
0
SCL
CON6
R92
R91
PB24A/PB29A/PB37A
PB24B/PB29B/PB37B
PB22A/PB27A/PB35A
PB22B/PB27B/PB35B
PB22C/PB26A/PB34A
PB22D/PB26B/PB34B
PB21C/PB24C/PB31C
PB21D/PB24D/PB31D
PB21A/PB24A/PB31A
PB21B/PB24B/PB31B
PB19A/PB23A/PB29A
PB19B/PB23B/PB29B
PB19C/PB23C/PB28A
PB19D/PB23D/PB28B
FTDI_SCL
FTDI_SDA
4
CSSPIN
VCCIO2/VCCIO2/VCCIO2
VCCIO2/VCCIO2/VCCIO2
PB25C/PB30C/PB38C
PB25D/PB30D/PB38D
PB25A/PB30A/PB38A || SN
PB25B/PB30B/PB38B || SI/SISPI
NOTE : PLACE J7 NEAR J1
DNI
J7
TP13
1
0
1
2
3
4
5
6
TP14
1
SDA
SN
SPISO
SISPI
MCLK
FTDI_SCL
Sheet[2]
SDA
SCL
FTDI_SDA
Sheet[2]
Sheet[2] USB_I2C_EN
TP15
1
PB18A/PB21A/PB26A
PB18B/PB21B/PB26B
PB18C/PB21C/PB26C
PB18D/PB21D/PB26D
1K-2K/4K/7K || 2nd_Fn.
VCCIO2/VCCIO2/VCCIO2
VCCIO2/VCCIO2/VCCIO2
PB12C/PB15C/PB18C
PB12D/PB15D/PB18D
PB12A/PB15A/PB18A
PB12B/PB15B/PB18B
PB11A/PB13A/PB16A || PCLKT2_0
PB11B/PB13B/PB16B || PCLKC2_0
PB11C/PB12A/PB15A
PB11D/PB12B/PB15B
PB9C/PB10C/PB13C
PB9D/PB10D/PB13D
PB9A/PB10A/PB13A
PB9B/PB10B/PB13B
PB8A/PB9A/PB12A || MCLK/CCLK
PB8B/PB9B/PB12B || SO/SPISO
PB8C/PB9C/PB10A
PB8D/PB9D/PB10B
PB6A/PB7A/PB9A
PB6B/PB7B/PB9B
PB6C/PB6A/PB7A
PB6D/PB6B/PB7B
PB16C/PB18A/PB21A
PB16D/PB18B/PB21B
PB16A/PB20A/PB23A || PCLKT2_1
PB16B/PB20B/PB23B || PCLKC2_1
BANK2
PB5A/PB4A/PB6A || CSSPIN
PB5B/PB4B/PB6B
PB3C/PB3C/PB4C
PB3D/PB3D/PB4D
PB3A/PB3A/PB4A
PB3B/PB3B/PB4B
NOTE : PLACE TEST POINTS NEAR PIN 1 OF J7 AND THE SAME LINE
0.01uF
C35
0
CSSPIN
NOTE : PLACE R84,R81,R83,R85 CLOSE TO U5
IO_P4
IO_T4
U5C
4
N10
M11
N5
N12
T15
R14
R12
P13
P12
T13
R11
T12
R13
T14
M10
N11
T11
P11
P10
R10
0
TP12
0.1uF
C38
SN
R67
MCLK
1
0.1uF
C39
0
SISPI
IO_R11
IO_T12
IO_R13
IO_T14
IO_T11
IO_P11
IO_P10
IO_R10
IO_N10
IO_M11
IO_R9
IO_T10
R9
T10
M9
L10
IO_T9
IO_P9
IO_M8
IO_N9
T9
P9
M8
N9
0.1uF
C40
R85
1
3
6
5
1K
R63
3
CS
WP
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
Header 2x20
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
NOTE : MAKE PWR TRACES
CAPABLE OF 1A
VCCIO2
J6
IO_L7
IO_N6
IO_R4
IO_T3
IO_T8
IO_P8
IO_R7
IO_P7
IO_T10
IO_R9
IO_T9
IO_P9
IO_T12
IO_R11
IO_T11
IO_P11
2
7
2
SPI FLASH
SPISO
S25FL204K0TMFI041
HOLD
SDO
10K 10K 10K
R64 R65 R66
100nF
10V
C41
+3.3V
2
NOTE : ROUTE J6 TRACES AS 100OHMS, LENGTH MATCHED
DIFFERENTIAL PAIRS
VCCIO2
NOTE : PLACE SPI FLASH IN THE BOTTOM SIDE
SCK
SDI
U6
IO_R6
IO_T5
IO_P4
IO_T4
IO_L8
IO_M6
IO_R8
IO_T7
IO_P10
IO_R10
IO_N9
IO_M8
IO_T14
IO_R13
IO_M11
IO_N10
SISPI
VCCIO2
10K
R80
VCCIO2
3
8
VCC
GND
24
4
5
Title
Date:
Size
B
R59 DNI
R60 DNI
R61 DNI
IO_R13
IO_T14
IO_R11
IO_T12
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
BANK2 I/O
12-SEP-14
Project
MACHXO3 Starter Kit - LCMXO3L-6900C
1
Sheet
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
NOTE : PLACE ALL THE LVDS DIFF TERMINATION
RESISTORS IN TOP AND CLOSE TO U5
R58 DNI
IO_P10
IO_R10
R57 DNI
R56 DNI
R55 DNI
R54 DNI
R53 DNI
R52 DNI
R51 DNI
R50 DNI
R49 DNI
R48 DNI
R47 DNI
R46 DNI
IO_T11
IO_P11
IO_N10
IO_M11
IO_R9
IO_T10
IO_T9
IO_P9
IO_M8
IO_N9
IO_P8
IO_T8
IO_T7
IO_R8
IO_M6
IO_L8
IO_R7
IO_P7
IO_N6
IO_L7
IO_T5
IO_R6
IO_T3
IO_R4
IO_P4
IO_T4
1
1.0
A
Schematic Rev
Board Rev
of 8
6
A
B
C
D
MachXO3L Starter Kit User Guide
Figure 12. Bank 2 I/O
25
A
B
C
D
IO_J1
IO_J3
IO_H3
IO_H1
IO_G1
IO_H2
IO_L2
IO_M1
5
K4
L5
IO_K4
IO_L5
J1
J3
H3
H1
H4
J6
G1
H2
PL14C/PL20C/PL25C
PL14D/PL20D/PL25D
PL14A/PL20A/PL25A
PL14B/PL20B/PL25B
PL13A/PL19A/PL24A
PL13B/PL19B/PL24B
PL10A/PL14A/PL17A
PL10B/PL14B/PL17B
PL10C/PL14C/PL16C
PL10D/PL14D/PL16D
PL9C/PL13C/PL15C
PL9D/PL13D/PL15D
PL9A/PL13A/PL15A
PL9B/PL13B/PL15B
BANK4
1K-2K/4K/7K || 2nd_Fn.
VCCIO4/VCCIO4/VCCIO4
VCCIO4/VCCIO4/VCCIO4
PL7C/PL10C/PL12A || PCLKT4_0
PL7D/PL10D/PL12B || PCLKC4_0
PL7A/PL10A/PL11A
PL7B/PL10B/PL11B
PL6C/PL9C/PL10C
PL6D/PL9D/PL10D
PL6A/PL9A/PL10A
PL6B/PL9B/PL10B
U5E
LCMXO3L-6900C-5BG256C
1K-2K/4K/7K || 2nd_Fn.
VCCIO3/VCCIO3/VCCIO3
PL12A/PL17A/PL22A || PCLKT3_0
PL12B/PL17B/PL22B || PCLKC3_0
PL12C/PL17C/PL21C
PL12D/PL17D/PL21D
PL11C/PL16C/PL19C
PL11D/PL16D/PL19D
PL13C/PL18C/PL23C
PL13D/PL18D/PL23D
BANK3
PL11A/PL16A/PL19A
PL11B/PL16B/PL19B
U5D
LCMXO3L-6900C-5BG256C
L2
M1
K5
L4
L1
L3
IO_L1
IO_L3
5
C44
VCCIO3
H7
J7
K3
K2
J5
K6
H5
J4
J2
K1
M4
0.1uF
0.1uF
4
C50
C49
0.1uF
0.1uF
0.1uF
C43
C48
IO_J2
IO_K1
0.1uF
C42
VCCIO4
VCCIO4
IO_N3
IO_M1
IO_L1
IO_L5
IO_G1
IO_F1
IO_E1
IO_D1
IO_C2
IO_G3
IO_D3
IO_F3
IO_J1
IO_J2
IO_H3
IO_H1
E1
F2
IO_E1
IO_F2
3
BANK5
PL3C/PL6C/PL6C
PL3D/PL6D/PL6D
MAKE PWR TRACES
CAPABLE OF 1A
Header 2x20
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
VCCIO5
IO_C1
IO_B1
IO_E3
IO_F5
IO_G2
IO_F2
IO_E2
IO_D2
IO_K4
IO_K1
IO_J3
IO_H2
IO_H6
IO_M2
IO_L2
IO_L3
1K-2K/4K/7K || 2nd_Fn.
MAKE PWR TRACES
CAPABLE OF 1A
J8
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
PL5C/PL8C/PL9C
PL5D/PL8D/PL9D
PL5A/PL8A/PL9A
PL5B/PL8B/PL9B
PL4A/PL7A/PL8A
PL4B/PL7B/PL8B
PL4C/PL7C/PL7C
PL4D/PL7D/PL7D
VCCIO5/VCCIO5/VCCIO5
PL3A/PL6A/PL6A || PCLKT5_0
PL3B/PL6B/PL6B || PCLKC5_0
PL2C/PL4C/PL4C
PL2D/PL4D/PL4D
PL2A/PL4A/PL4A || L_GPLLT_IN
PL2B/PL4B/PL4B || L_GPLLC_IN
PL1A/PL3A/PL3A || L_GPLLT_FB
PL1B/PL3B/PL3B || L_GPLLC_FB
PL1C/PL2C/PL2C
PL1D/PL2D/PL2D
U5F
LCMXO3L-6900C-5BG256C
VCCIO3
F4
G6
E2
E3
C1
D2
D3
D1
B1
C2
IO_C1
IO_D2
3
IO_E2
IO_E3
IO_M2
IO_N3
M2
N3
R1
P2
IO_D3
IO_D1
IO_B1
IO_C2
DIP_SW3
DIP_SW4
DIP_SW1
DIP_SW2
M3
N1
N2
P1
4
E4
F5
H6
G2
G3
F3
F1
G5
G4
2
0.1uF
C47
Date:
4.7K
R69
4.7K
R71
1
2
3
4
12-SEP-14
SW-DIP4
1
2
3
4
SW2
1
8
7
6
5
1
Sheet
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
4.7K
R70
Project
MACHXO3 Starter Kit - LCMXO3L-6900C
4.7K
R68
PLACE THE RESISTORS IN THE TOP
BANK3,4,5 I/O
VCCIO5
VCCIO3
Size
B
Title
DIP_SW1
DIP_SW2
DIP_SW3
DIP_SW4
0.1uF
C46
IO_F5
IO_H6
IO_G2
IO_G3
IO_F3
IO_F1
0.1uF
C45
2
1.0
A
Schematic Rev
Board Rev
7
of 8
8
7
6
5
A
B
C
D
MachXO3L Starter Kit User Guide
Figure 13. Bank 3, 4, 5 I/O
26
A
B
C
5
C52
1uF
C51
10uF
B2
B15
C3
C14
D4
D13
E5
E12
F6
F11
H8
H9
J8
J9
L6
L11
M5
M12
N4
N13
P3
P14
R2
R15
0.1uF
C53
VCC_CORE
A2
0.1uF
C54
0.1uF
C55
4
0.1uF
C56
0.01uF
C57
0.1uF
C58
0.1uF
C59
PLACE DECOUPLING CAPACITORS CLOSE TO THE U5 POWER PINS
NC/NC/NC
0.01uF
C60
3
Sheet[5]
Sheet[5]
Sheet[5]
Sheet[5]
Sheet[5]
Sheet[5]
Sheet[5]
Sheet[5]
LED7
LED6
LED5
LED4
LED3
LED2
LED1
LED0
R72
1K
D2
Red
R73
1K
D3
Red
D4
Red
R74
1K
D5
Red
R75
1K
LEDs
D6
Red
R76
1K
D7
Red
R77
1K
1
D8
Red
R78
1K
D9
Red
R79
1K
2
Date:
Size
B
Title
12-SEP-14
Project
MACHXO3 Starter Kit - LCMXO3L-6900C
POWER DECOUPLING AND LED'S
1
Sheet
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
1.0
A
Schematic Rev
Board Rev
8
of 8
Note : LEDs are controlled by XO3L I/O Bank 1. When
VCCIO1 is set to a voltage less than 3.3V, observe all I/O
overdrive requirements. Refer to Lattice TN1280
"MachXO3L sysIO Usage Guide" for more information.
LAYOUT LEDs IN A SINGLE ROW
1
2
A1
A16
G7
G10
K7
K10
T1
T16
+3.3V
2
1
2
VCC/VCC/VCC
VCC/VCC/VCC
VCC/VCC/VCC
VCC/VCC/VCC
VCC/VCC/VCC
VCC/VCC/VCC
VCC/VCC/VCC
VCC/VCC/VCC
LCMXO3L-6900C-5BG256C
1K-2K/4K/7K
GND/GND/GND
GND/GND/GND
GND/GND/GND
GND/GND/GND
GND/GND/GND
GND/GND/GND
GND/GND/GND
GND/GND/GND
GND/GND/GND
GND/GND/GND
GND/GND/GND
GND/GND/GND
GND/GND/GND
GND/GND/GND
GND/GND/GND
GND/GND/GND
GND/GND/GND
GND/GND/GND
GND/GND/GND
GND/GND/GND
GND/GND/GND
GND/GND/GND
GND/GND/GND
GND/GND/GND
VCC_CORE
3
1
2
U5G
4
1
2
1
2
1
2
1
2
1
2
D
5
A
B
C
D
MachXO3L Starter Kit User Guide
Figure 14. Power Decoupling and LEDs
MachXO3L Starter Kit User Guide
Appendix B. Bill of Materials
Table 15. MachXO3L Starter Kit Bill of Materials
Item Quantity
Reference
Value
4.7 uF
Manufacturer
MFG Pin
1
2
C1,C3
Panasonic
ECJ-1VB0J475K
2
44
C2,C4,C6,C7,C10,C11,C12,C13,C14 0.1 uF
,C15,C16,C21,C23,C24,C25,C26,C2
7,C28,C30,C31,C32,C33,C34,C36,C
37,C38,C39,C40,C42,C43,C44,C45,
C46,C47,C48,C49,C50,C53,C54,
C55,C56,C58,C59,C63
Kemet
C0402C104K4RACTU
3
5
C5,C17,C19,C51,C61
10 uF
Taiyo Yuden
LMK107BJ106MALTD
4
2
C8,C9
18 pF
Kemet
C0402C180K3GACTU
5
2
C18,C20
22 uF
Taiyo Yuden
LMK212BJ226MG-T
6
6
C22,C29,C35,C57,C60,C64
0.01 uF
Kemet
C0402C103J4RACTU
7
1
C41
100 nF
Murata
GRM155R61A104KA01D
8
2
C52,C62
1 uF
Kemet
C0402C105K9PACTU
9
2
C65,C66
150 pF
Kemet
C0402C104K4RACTU
10
1
D1
Blue
LITE-On INC
LTST-C190TBKT
11
8
D2,D3,D4,D5,D6,D7,D8,D9
Red
LITE-On INC
LTST-C190KRKT
12
1
J1
Header 1 x 8
Molex
0022284081
13
1
J2
Mini USB-B
Neltron
5075BMR-05-SM-CR
14
4
J3,J4,J6,J8
Header 2 x 20 Samtec
TSW-120-07-G-D
16
1
J7
Header 1 x 6
Samtec
TSW-106-07-F-S-ND
17
5
L1,L2,L3,L4,L5
600 Ohm
500 mA
Murata
BLM18AG601SN1D
18
8
R1,R2,R3,R45,R68,R69,R70,R71
4.7 K
Vishay
CRCW06034K70FKEA
19
13
R4,R5,R6,R7,R23,R30,R35,R42,R67 0
,R81,R83, R84,R85
Yageo
RC0603JR-070RL
20
2
R8,R9
2.2 K
Vishay
CRCW06032K20FKEA
21
2
R10,R19
12 K
Yageo
RC0603FR-0712KL
22
7
R11,R12,R13,R64,R65,R66,R80
10 K
Stackpole Electronics Inc
RMCF0603JT10K0
23
13
R14,R15,R16,R17,R18,R20,R21,R2 0
2,R27,R62, R82,R91,R92
Yageo
RC0603JR-070RL
24
7
R24,R25,R26,R31,R32,R37,R38
1
Vishay
CRCW06031R00JNEAHP
25
7
R28,R29,R33,R34,R39,R40,R86
1
Vishay
CRCW06031R00JNEAHP
26
1
R36
100
Yageo
RC0603FR-07100RL
27
10
R41,R63,R72,R73,R74,R75,R76,R7 1 K
7,R78,R79
Yageo
RC0603FR-071KL
28
2
R43,R44
2K
Vishay
CRCW06032K00JNEA
29
16
R46,R47,R48,R49,R50,R51,R52,R5 100
3,R54,R55,R56,R57,R58,R59,R60,
R61
Yageo
RC0402FR07100RL
30
2
R87,R88
49.9
Vishay
CRCW060349R9FKEA
31
2
R89,R90
150
Vishay
CRCW0603150RJNEA
32
1
SW1
E-Switch
TL1015AF160QG
33
1
SW2
CTS Electrocomponents
195-4MST
35
1
U1
FTDI
FT2232HL
36
1
U2
Microchip
93LC56C-I/SN
37
1
U3
Fairchild Semi
FAN1112SX
DIP
27
MachXO3L Starter Kit User Guide
Table 15. MachXO3L Starter Kit Bill of Materials (Continued)
Item Quantity
Reference
Value
Manufacturer
MFG Pin
38
1
U4
On Semi
NCP1117ST33T3G
39
1
U5
Lattice semi
LCMXO3L-6900C5BG256C
40
1
U6
Spansion
S25FL204K0TMFI041
41
1
X1
TXC
7M-12.000MAAJ-T
12 MHz
28
工商网监
湘ICP备2023018690号
