LCMXO640LUTSE-3FTN256C

MachXO Family Data Sheet DS1002 Version 02.7, November 2007 MachXO Family Data Sheet Introduction August 2006 Data Sheet DS1002 Features ■ Non-volatile, Infinitely Reconfigurable • Instant-on – powers up in microseconds • Single chip, no external configuration memory required • Excellent design security, no bit stream to intercept • Reconfigure SRAM based logic in milliseconds • SRAM and non-volatile memory programmable through JTAG port • Supports background programming of non-volatile memory ■ Flexible I/O Buffer • Programmable sysIO™ buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2 − LVTTL − PCI − LVDS, Bus-LVDS, LVPECL, RSDS ■ sysCLOCK™ PLLs • Up to two analog PLLs per device • Clock multiply, divide, and phase shifting ■ System Level Support • IEEE Standard 1149.1 Boundary Scan • Onboard oscillator • Devices operate with 3.3V, 2.5V, 1.8V or 1.2V power supply • IEEE 1532 compliant in-system programming ■ Sleep Mode • Allows up to 100x static current reduction ■ TransFR™ Reconfiguration (TFR) • In-field logic update while system operates ■ High I/O to Logic Density • • • • 256 to 2280 LUT4s 73 to 271 I/Os with extensive package options Density migration supported Lead free/RoHS compliant packaging Introduction The MachXO is optimized to meet the requirements of applications traditionally addressed by CPLDs and low capacity FPGAs: glue logic, bus bridging, bus interfacing, power-up control, and control logic. These devices bring together the best features of CPLD and FPGA devices on a single chip. ■ Embedded and Distributed Memory • Up to 27.6 Kbits sysMEM™ Embedded Block RAM • Up to 7.5 Kbits distributed RAM • Dedicated FIFO control logic Table 1-1. MachXO Family Selection Guide Device LUTs Dist. RAM (Kbits) EBR SRAM (Kbits) Number of EBR SRAM Blocks (9 Kbits) VCC Voltage Number of PLLs Max. I/O Packages 100-pin TQFP (14x14 mm) 144-pin TQFP (20x20 mm) 100-ball csBGA (8x8 mm) 132-ball csBGA (8x8 mm) 256-ball ftBGA (17x17 mm) 324-ball ftBGA (19x19 mm) 78 78 LCMXO256 256 2.0 0 0 LCMXO640 640 6.0 0 0 1.2/1.8/2.5/3.3V 0 159 74 113 74 101 159 LCMXO1200 1200 6.25 9.2 1 1.2/1.8/2.5/3.3V 1 211 73 113 101 211 LCMXO2280 2280 7.5 27.6 3 1.2/1.8/2.5/3.3V 2 271 73 113 101 211 271 1.2/1.8/2.5/3.3V 0 78 © 2006 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1-1 DS1002 Introduction_01.3 Lattice Semiconductor Introduction MachXO Family Data Sheet The devices use look-up tables (LUTs) and embedded block memories traditionally associated with FPGAs for flexible and efficient logic implementation. Through non-volatile technology, the devices provide the single-chip, highsecurity, instant-on capabilities traditionally associated with CPLDs. Finally, advanced process technology and careful design will provide the high pin-to-pin performance also associated with CPLDs. The ispLEVER® design tools from Lattice allow complex designs to be efficiently implemented using the MachXO family of devices. Popular logic synthesis tools provide synthesis library support for MachXO. The ispLEVER tools use the synthesis tool output along with the constraints from its floor planning tools to place and route the design in the MachXO device. The ispLEVER tool extracts the timing from the routing and back-annotates it into the design for timing verification. 1-2 MachXO Family Data Sheet Architecture February 2007 Data Sheet DS1002 Architecture Overview The MachXO family architecture contains an array of logic blocks surrounded by Programmable I/O (PIO). Some devices in this family have sysCLOCK PLLs and blocks of sysMEM™ Embedded Block RAM (EBRs). Figures 2-1, 2-2, and 2-3 show the block diagrams of the various family members. The logic blocks are arranged in a two-dimensional grid with rows and columns. The EBR blocks are arranged in a column to the left of the logic array. The PIO cells are located at the periphery of the device, arranged into Banks. The PIOs utilize a flexible I/O buffer referred to as a sysIO interface that supports operation with a variety of interface standards. The blocks are connected with many vertical and horizontal routing channel resources. The place and route software tool automatically allocates these routing resources. There are two kinds of logic blocks, the Programmable Functional Unit (PFU) and the Programmable Functional unit without RAM (PFF). The PFU contains the building blocks for logic, arithmetic, RAM, ROM, and register functions. The PFF block contains building blocks for logic, arithmetic, ROM, and register functions. Both the PFU and PFF blocks are optimized for flexibility, allowing complex designs to be implemented quickly and effectively. Logic blocks are arranged in a two-dimensional array. Only one type of block is used per row. In the MachXO family, the number of sysIO Banks varies by device. There are different types of I/O Buffers on different Banks. See the details in later sections of this document. The sysMEM EBRs are large, dedicated fast memory blocks; these blocks are found only in the larger devices. These blocks can be configured as RAM, ROM or FIFO. FIFO support includes dedicated FIFO pointer and flag “hard” control logic to minimize LUT use. The MachXO architecture provides up to two sysCLOCK™ Phase Locked Loop (PLL) blocks on larger devices. These blocks are located at either end of the memory blocks. The PLLs have multiply, divide, and phase shifting capabilities that are used to manage the frequency and phase relationships of the clocks. Every device in the family has a JTAG Port that supports programming and configuration of the device as well as access to the user logic. The MachXO devices are available for operation from 3.3V, 2.5V, 1.8V, and 1.2V power supplies, providing easy integration into the overall system. © 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 2-1 DS1002 Architecture_01.4 Lattice Semiconductor Figure 2-1. Top View of the MachXO1200 Device1 Architecture MachXO Family Data Sheet PIOs Arranged into sysIO Banks sysMEM Embedded Block RAM (EBR) Programmable Functional Units with RAM (PFUs) Programmable Functional Units without RAM (PFFs) sysCLOCK PLL JTAG Port 1. Top view of the MachXO2280 device is similar but with higher LUT count, two PLLs, and three EBR blocks. Figure 2-2. Top View of the MachXO640 Device PIOs Arranged into sysIO Banks Programmable Function Units without RAM (PFFs) Programmable Function Units with RAM (PFUs) JTAG Port 2-2 Lattice Semiconductor Figure 2-3. Top View of the MachXO256 Device Architecture MachXO Family Data Sheet JTAG Port Programmable Function Units without RAM (PFFs) PIOs Arranged into sysIO Banks Programmable Function Units with RAM (PFUs) PFU Blocks The core of the MachXO devices consists of PFU and PFF blocks. The PFUs can be programmed to perform Logic, Arithmetic, Distributed RAM, and Distributed ROM functions. PFF blocks can be programmed to perform Logic, Arithmetic, and Distributed ROM functions. Except where necessary, the remainder of this data sheet will use the term PFU to refer to both PFU and PFF blocks. Each PFU block consists of four interconnected Slices, numbered 0-3 as shown in Figure 2-4. There are 53 inputs and 25 outputs associated with each PFU block. Figure 2-4. PFU Diagram From Routing FCIN LUT4 & CARRY LUT4 & CARRY LUT4 & CARRY LUT4 & CARRY LUT4 & CARRY LUT4 & CARRY LUT4 & CARRY LUT4 & CARRY FCO Slice 0 Slice 1 Slice 2 Slice 3 D FF/ Latch D FF/ Latch D FF/ Latch D FF/ Latch D FF/ Latch D FF/ Latch D FF/ Latch D FF/ Latch To Routing Slice Each Slice contains two LUT4 lookup tables feeding two registers (programmed to be in FF or Latch mode), and some associated logic that allows the LUTs to be combined to perform functions such as LUT5, LUT6, LUT7, and LUT8. There is control logic to perform set/reset functions (programmable as synchronous/asynchronous), clock select, chip-select, and wider RAM/ROM functions. Figure 2-5 shows an overview of the internal logic of the Slice. The registers in the Slice can be configured for positive/negative and edge/level clocks. 2-3 Lattice Semiconductor Architecture MachXO Family Data Sheet There are 14 input signals: 13 signals from routing and one from the carry-chain (from the adjacent Slice/PFU). There are 7 outputs: 6 to the routing and one to the carry-chain (to the adjacent Slice/PFU). Table 2-1 lists the signals associated with each Slice. Figure 2-5. Slice Diagram To Adjacent Slice/PFU Slice OFX1 A1 B1 C1 D1 CO F1 F SUM D LUT4 & CARRY CI FF/ Latch Fast Connection to I/O Cell* Q1 To Routing From Routing M1 M0 LUT Expansion Mux A0 B0 CO OFX0 Fast Connection to I/O Cell* F0 C0 D0 LUT4 & CARRY CI F SUM OFX0 D FF/ Latch Q0 Control Signals selected and inverted per Slice in routing CE CLK LSR From Adjacent Slice/PFU Notes: Some inter-Slice signals are not shown. * Only PFUs at the edges have fast connections to the I/O cell. Table 2-1. Slice Signal Descriptions Function Input Input Input Input Input Input Input Output Output Output Output Output Type Data signal Data signal Multi-purpose Control signal Control signal Control signal Inter-PFU signal Data signals Data signals Data signals Data signals Inter-PFU signal Signal Names A0, B0, C0, D0 Inputs to LUT4 A1, B1, C1, D1 Inputs to LUT4 M0/M1 CE LSR CLK FCIN F0, F1 Q0, Q1 OFX0 OFX1 FCO Multipurpose Input Clock Enable Local Set/Reset System Clock Fast Carry In1 LUT4 output register bypass signals Register Outputs Output of a LUT5 MUX Output of a LUT6, LUT7, LUT82 MUX depending on the Slice Fast Carry Out1 Description 1. See Figure 2-4 for connection details. 2. Requires two PFUs. 2-4 Lattice Semiconductor Architecture MachXO Family Data Sheet Modes of Operation Each Slice is capable of four modes of operation: Logic, Ripple, RAM, and ROM. The Slice in the PFF is capable of all modes except RAM. Table 2-2 lists the modes and the capability of the Slice blocks. Table 2-2. Slice Modes Logic PFU Slice PFF Slice LUT 4x2 or LUT 5x1 LUT 4x2 or LUT 5x1 Ripple 2-bit Arithmetic Unit 2-bit Arithmetic Unit RAM SP 16x2 N/A ROM ROM 16x1 x 2 ROM 16x1 x 2 Logic Mode: In this mode, the LUTs in each Slice are configured as 4-input combinatorial lookup tables (LUT4). A LUT4 can have 16 possible input combinations. Any logic function with four inputs can be generated by programming this lookup table. Since there are two LUT4s per Slice, a LUT5 can be constructed within one Slice. Larger lookup tables such as LUT6, LUT7, and LUT8 can be constructed by concatenating other Slices. Ripple Mode: Ripple mode allows the efficient implementation of small arithmetic functions. In ripple mode, the following functions can be implemented by each Slice: • • • • • • • Addition 2-bit Subtraction 2-bit Add/Subtract 2-bit using dynamic control Up counter 2-bit Down counter 2-bit Ripple mode multiplier building block Comparator functions of A and B inputs - A greater-than-or-equal-to B - A not-equal-to B - A less-than-or-equal-to B Two additional signals, Carry Generate and Carry Propagate, are generated per Slice in this mode, allowing fast arithmetic functions to be constructed by concatenating Slices. RAM Mode: In this mode, distributed RAM can be constructed using each LUT block as a 16x2-bit memory. Through the combination of LUTs and Slices, a variety of different memories can be constructed. The ispLEVER design tool supports the creation of a variety of different size memories. Where appropriate, the software will construct these using distributed memory primitives that represent the capabilities of the PFU. Table 2-3 shows the number of Slices required to implement different distributed RAM primitives. Figure 2-6 shows the distributed memory primitive block diagrams. Dual port memories involve the pairing of two Slices. One Slice functions as the read-write port, while the other companion Slice supports the read-only port. For more information on RAM mode in MachXO devices, please see details of additional technical documentation at the end of this data sheet. Table 2-3. Number of Slices Required For Implementing Distributed RAM SPR16x2 Number of Slices 1 DPR16x2 2 Note: SPR = Single Port RAM, DPR = Dual Port RAM 2-5 Lattice Semiconductor Figure 2-6. Distributed Memory Primitives SPR16x2 AD0 AD1 AD2 AD3 DI0 DI1 WRE CK Architecture MachXO Family Data Sheet DPR16x2 DO0 DO1 WAD0 WAD1 WAD2 WAD3 DI0 DI1 WCK WRE RAD0 RAD1 RAD2 RAD3 RDO0 RDO1 WDO0 WDO1 ROM16x1 AD0 AD1 AD2 AD3 DO0 ROM Mode: The ROM mode uses the same principal as the RAM modes, but without the Write port. Pre-loading is accomplished through the programming interface during configuration. PFU Modes of Operation Slices can be combined within a PFU to form larger functions. Table 2-4 tabulates these modes and documents the functionality possible at the PFU level. Table 2-4. PFU Modes of Operation Logic LUT 4x8 or MUX 2x1 x 8 LUT 5x4 or MUX 4x1 x 4 LUT 6x 2 or MUX 8x1 x 2 LUT 7x1 or MUX 16x1 x 1 Ripple 2-bit Add x 4 2-bit Sub x 4 2-bit Counter x 4 2-bit Comp x 4 RAM SPR16x2 x 4 DPR16x2 x 2 SPR16x4 x 2 DPR16x4 x 1 SPR16x8 x 1 ROM ROM16x1 x 8 ROM16x2 x 4 ROM16x4 x 2 ROM16x8 x 1 Routing There are many resources provided in the MachXO devices to route signals individually or as buses with related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) segments. The inter-PFU connections are made with three different types of routing resources: x1 (spans two PFUs), x2 (spans three PFUs) and x6 (spans seven PFUs). The x1, x2, and x6 connections provide fast and efficient connections in the horizontal and vertical directions. 2-6 Lattice Semiconductor Architecture MachXO Family Data Sheet The ispLEVER design tool takes the output of the synthesis tool and places and routes the design. Generally, the place and route tool is completely automatic, although an interactive routing editor is available to optimize the design. Clock/Control Distribution Network The MachXO family of devices provides global signals that are available to all PFUs. These signals consist of four primary clocks and four secondary clocks. Primary clock signals are generated from four 16:1 muxes as shown in Figure 2-7 and Figure 2-8. The available clock sources for the MachXO256 and MachXO640 devices are four dual function clock pins and 12 internal routing signals. The available clock sources for the MachXO1200 and MachXO2280 devices are four dual function clock pins, up to nine internal routing signals and up to six PLL outputs. Figure 2-7. Primary Clocks for MachXO256 and MachXO640 Devices 12 4 16:1 Primary Clock 0 16:1 Primary Clock 1 16:1 Primary Clock 2 16:1 Primary Clock 3 Routing Clock Pads 2-7 Lattice Semiconductor Figure 2-8. Primary Clocks for MachXO1200 and MachXO2280 Devices Up to 9 4 Up to 6 Architecture MachXO Family Data Sheet 16:1 Primary Clock 0 Primary Clock 1 16:1 16:1 Primary Clock 2 16:1 Primary Clock 3 Routing Clock Pads PLL Outputs Four secondary clocks are generated from four 16:1 muxes as shown in Figure 2-9. Four of the secondary clock sources come from dual function clock pins and 12 come from internal routing. Figure 2-9. Secondary Clocks for MachXO Devices 12 4 16:1 16:1 Secondary (Control) Clocks 16:1 16:1 Routing Clock Pads 2-8 Lattice Semiconductor sysCLOCK Phase Locked Loops (PLLs) Architecture MachXO Family Data Sheet The MachXO1200 and MachXO2280 provide PLL support. The source of the PLL input divider can come from an external pin or from internal routing. There are four sources of feedback signals to the feedback divider: from CLKINTFB (internal feedback port), from the global clock nets, from the output of the post scalar divider, and from the routing (or from an external pin). There is a PLL_LOCK signal to indicate that the PLL has locked on to the input clock signal. Figure 2-10 shows the sysCLOCK PLL diagram. The setup and hold times of the device can be improved by programming a delay in the feedback or input path of the PLL which will advance or delay the output clock with reference to the input clock. This delay can be either programmed during configuration or can be adjusted dynamically. In dynamic mode, the PLL may lose lock after adjustment and not relock until the tLOCK parameter has been satisfied. Additionally, the phase and duty cycle block allows the user to adjust the phase and duty cycle of the CLKOS output. The sysCLOCK PLLs provide the ability to synthesize clock frequencies. Each PLL has four dividers associated with it: input clock divider, feedback divider, post scalar divider, and secondary clock divider. The input clock divider is used to divide the input clock signal, while the feedback divider is used to multiply the input clock signal. The post scalar divider allows the VCO to operate at higher frequencies than the clock output, thereby increasing the frequency range. The secondary divider is used to derive lower frequency outputs. Figure 2-10. PLL Diagram Dynamic Delay Adjustment LOCK RST CLKI (from routing or external pin) Input Clock Divider (CLKI) Delay Adjust Voltage Controlled VCO Oscillator Post Scalar Divider (CLKOP) Phase/Duty Select CLKOS CLKOP Feedback Divider (CLKFB) Secondary Clock Divider (CLKOK) CLKFB (from Post Scalar Divider output, clock net, routing/external pin or CLKINTFB port CLKOK CLKINTFB (internal feedback) Figure 2-11 shows the available macros for the PLL. Table 2-5 provides signal description of the PLL Block. Figure 2-11. PLL Primitive RST CLKI CLKFB DDA MODE DDAIZR DDAILAG DDAIDEL[2:0] CLKOP CLKOS EHXPLLC CLKOK LOCK CLKINTFB 2-9 Lattice Semiconductor Table 2-5. PLL Signal Descriptions Signal CLKI CLKFB RST CLKOS CLKOP CLKOK LOCK CLKINTFB DDAMODE DDAIZR DDAILAG DDAIDEL[2:0] I/O I I I O O O O O I I I I Clock input from external pin or routing Description Architecture MachXO Family Data Sheet PLL feedback input from PLL output, clock net, routing/external pin or internal feedback from CLKINTFB port “1” to reset the input clock divider PLL output clock to clock tree (phase shifted/duty cycle changed) PLL output clock to clock tree (No phase shift) PLL output to clock tree through secondary clock divider “1” indicates PLL LOCK to CLKI Internal feedback source, CLKOP divider output before CLOCKTREE Dynamic Delay Enable. “1”: Pin control (dynamic), “0”: Fuse Control (static) Dynamic Delay Zero. “1”: delay = 0, “0”: delay = on Dynamic Delay Lag/Lead. “1”: Lag, “0”: Lead Dynamic Delay Input For more information on the PLL, please see details of additional technical documentation at the end of this data sheet. sysMEM Memory The MachXO1200 and MachXO2280 devices contain sysMEM Embedded Block RAMs (EBRs). The EBR consists of a 9-Kbit RAM, with dedicated input and output registers. sysMEM Memory Block The sysMEM block can implement single port, dual port, pseudo dual port, or FIFO memories. Each block can be used in a variety of depths and widths as shown in Table 2-6. Table 2-6. sysMEM Block Configurations Memory Mode Configurations 8,192 x 1 4,096 x 2 2,048 x 4 1,024 x 9 512 x 18 256 x 36 8,192 x 1 4,096 x 2 2,048 x 4 1,024 x 9 512 x 18 8,192 x 1 4,096 x 2 2,048 x 4 1,024 x 9 512 x 18 256 x 36 8,192 x 1 4,096 x 2 2,048 x 4 1,024 x 9 512 x 18 256 x 36 Single Port True Dual Port Pseudo Dual Port FIFO 2-10 Lattice Semiconductor Architecture MachXO Family Data Sheet Bus Size Matching All of the multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB word 0 to MSB word 0, LSB word 1 to MSB word 1 and so on. Although the word size and number of words for each port varies, this mapping scheme applies to each port. RAM Initialization and ROM Operation If desired, the contents of the RAM can be pre-loaded during device configuration. By preloading the RAM block during the chip configuration cycle and disabling the write controls, the sysMEM block can also be utilized as a ROM. Memory Cascading Larger and deeper blocks of RAMs can be created using EBR sysMEM Blocks. Typically, the Lattice design tools cascade memory transparently, based on specific design inputs. Single, Dual, Pseudo-Dual Port and FIFO Modes Figure 2-12 shows the five basic memory configurations and their input/output names. In all the sysMEM RAM modes, the input data and address for the ports are registered at the input of the memory array. The output data of the memory is optionally registered at the memory array output. Figure 2-12. sysMEM Memory Primitives ADA[12:0] DIA[17:0] CLKA CEA DO[35:0] RSTA WEA CSA[2:0] DOA[17:0] AD[12:0] DI[35:0] CLK CE RST WE CS[2:0] EBR EBR ADB[12:0] DIB[17:0] CEB CLKB RSTB WEB CSB[2:0] DOB[17:0] Single Port RAM True Dual Port RAM AD[12:0] CLK CE RST CS[2:0] EBR ADW[12:0] DI[35:0] CLKW CEW DO[35:0] WE RST CS[2:0] ADR[12:0] EBR DO[35:0] CER CLKR ROM Pseudo-Dual Port RAM DI[35:0] CLKW RSTA WE CEW EBR DO[35:0] CLKR RSTB RE RCE FF AF EF AE FIFO 2-11 Lattice Semiconductor Architecture MachXO Family Data Sheet The EBR memory supports three forms of write behavior for single or dual port operation: 1. Normal – data on the output appears only during the read cycle. During a write cycle, the data (at the current address) does not appear on the output. This mode is supported for all data widths. 2. Write Through – a copy of the input data appears at the output of the same port. This mode is supported for all data widths. 3. Read-Before-Write – when new data is being written, the old contents of the address appears at the output. This mode is supported for x9, x18 and x36 data widths. FIFO Configuration The FIFO has a write port with Data-in, CEW, WE and CLKW signals. There is a separate read port with Data-out, RCE, RE and CLKR signals. The FIFO internally generates Almost Full, Full, Almost Empty and Empty Flags. The Full and Almost Full flags are registered with CLKW. The Empty and Almost Empty flags are registered with CLKR. The range of programming values for these flags are in Table 2-7. Table 2-7. Programmable FIFO Flag Ranges Flag Name Full (FF) Almost Full (AF) Almost Empty (AE) Empty (EF) N = Address bit width Programming Range 1 to (up to 2N-1) 1 to Full-1 1 to Full-1 0 The FIFO state machine supports two types of reset signals: RSTA and RSTB. The RSTA signal is a global reset that clears the contents of the FIFO by resetting the read/write pointer and puts the FIFO flags in their initial reset state. The RSTB signal is used to reset the read pointer. The purpose of this reset is to retransmit the data that is in the FIFO. In these applications it is important to keep careful track of when a packet is written into or read from the FIFO. Memory Core Reset The memory array in the EBR utilizes latches at the A and B output ports. These latches can be reset asynchronously. RSTA and RSTB are local signals, which reset the output latches associated with Port A and Port B respectively. The Global Reset (GSRN) signal resets both ports. The output data latches and associated resets for both ports are as shown in Figure 2-13. 2-12 Lattice Semiconductor Figure 2-13. Memory Core Reset Memory Core SET Architecture MachXO Family Data Sheet D Q Port A[17:0] LCLR Output Data Latches D SET Q Port B[17:0] LCLR RSTA RSTB GSRN Programmable Disable For further information on the sysMEM EBR block, see the details of additional technical documentation at the end of this data sheet. EBR Asynchronous Reset EBR asynchronous reset or GSR (if used) can only be applied if all clock enables are low for a clock cycle before the reset is applied and released a clock cycle after the reset is released, as shown in Figure 2-14. The GSR input to the EBR is always asynchronous. Figure 2-14. EBR Asynchronous Reset (Including GSR) Timing Diagram Reset Clock Clock Enable If all clock enables remain enabled, the EBR asynchronous reset or GSR may only be applied and released after the EBR read and write clock inputs are in a steady state condition for a minimum of 1/fMAX (EBR clock). The reset release must adhere to the EBR synchronous reset setup time before the next active read or write clock edge. If an EBR is pre-loaded during configuration, the GSR input must be disabled or the release of the GSR during device Wake Up must occur before the release of the device I/Os becoming active. These instructions apply to all EBR RAM, ROM and FIFO implementations. For the EBR FIFO mode, the GSR signal is always enabled and the WE and RE signals act like the clock enable signals in Figure 2-14. The reset timing rules apply to the RPReset input vs the RE input and the RST input vs. the WE and RE inputs. Both RST and RPReset are always asynchronous EBR inputs. Note that there are no reset restrictions if the EBR synchronous reset is used and the EBR GSR input is disabled 2-13 Lattice Semiconductor Architecture MachXO Family Data Sheet PIO Groups On the MachXO devices, PIO cells are assembled into two different types of PIO groups, those with four PIO cells and those with six PIO cells. PIO groups with four IOs are placed on the left and right sides of the device while PIO groups with six IOs are placed on the top and bottom. The individual PIO cells are connected to their respective sysIO buffers and PADs. On all MachXO devices, two adjacent PIOs can be joined to provide a complementary Output driver pair. The I/O pin pairs are labeled as "T" and "C" to distinguish between the true and complement pins. The MachXO1200 and MachXO2280 devices contain enhanced I/O capability. All PIO pairs on these larger devices can implement differential receivers. In addition, half of the PIO pairs on the left and right sides of these devices can be configured as LVDS transmit/receive pairs. PIOs on the top of these larger devices also provide PCI support. Figure 2-15. Group of Four Programmable I/O Cells This structure is used on the left and right of MachXO devices PIO A PADA "T" PIO B Four PIOs PIO C PADB "C" PADC "T" PIO D PADD "C" Figure 2-16. Group of Six Programmable I/O Cells This structure is used on the top and bottom of MachXO devices PIO A PADA "T" PIO B PADB "C" PIO C Six PIOs PIO D PADC "T" PADD "C" PIO E PADE "T" PIO F PADF "C" PIO The PIO blocks provide the interface between the sysIO buffers and the internal PFU array blocks. These blocks receive output data from the PFU array and a fast output data signal from adjacent PFUs. The output data and fast 2-14 Lattice Semiconductor Architecture MachXO Family Data Sheet output data signals are multiplexed and provide a single signal to the I/O pin via the sysIO buffer. Figure 2-17 shows the MachXO PIO logic. The tristate control signal is multiplexed from the output data signals and their complements. In addition a global signal (TSALL) from a dedicated pad can be used to tristate the sysIO buffer. The PIO receives an input signal from the pin via the sysIO buffer and provides this signal to the core of the device. In addition there are programmable elements that can be utilized by the design tools to avoid positive hold times. Figure 2-17. MachXO PIO Block Diagram From Routing TS TSALL From Routing sysIO Buffer Fast Output Data signal DO TO PAD 1 Input Data Signal 2 3 4+ Programmable Delay Elements Note: Buffer 1 tracks with VCCAUX Buffer 2 tracks with VCCIO. Buffer 3 tracks with internal 1.2V VREF. Buffer 4 is available in MachXO1200 and MachXO2280 devices only. From Complementary Pad sysIO Buffer Each I/O is associated with a flexible buffer referred to as a sysIO buffer. These buffers are arranged around the periphery of the device in groups referred to as Banks. The sysIO buffers allow users to implement the wide variety of standards that are found in today’s systems including LVCMOS, TTL, BLVDS, LVDS and LVPECL. In the MachXO devices, single-ended output buffers and ratioed input buffers (LVTTL, LVCMOS and PCI) are powered using VCCIO. In addition to the Bank VCCIO supplies, the MachXO devices have a VCC core logic power supply, and a VCCAUX supply that powers up a variety of internal circuits including all the differential and referenced input buffers. MachXO256 and MachXO640 devices contain single-ended input buffers and single-ended output buffers with complementary outputs on all the I/O Banks. MachXO1200 and MachXO2280 devices contain two types of sysIO buffer pairs. 1. Top and Bottom sysIO Buffer Pairs The sysIO buffer pairs in the top and bottom Banks of the device consist of two single-ended output drivers and two sets of single-ended input buffers (for ratioed or absolute input levels). The I/O pairs on the top and bottom 2-15 Lattice Semiconductor Architecture MachXO Family Data Sheet of the devices also support differential input buffers. PCI clamps are available on the top Bank I/O buffers. The PCI clamp is enabled after VCC, VCCAUX, and VCCIO are at valid operating levels and the device has been configured. The two pads in the pair are described as “true” and “comp”, where the true pad is associated with the positive side of the differential input buffer and the comp (complementary) pad is associated with the negative side of the differential input buffer. 2. Left and Right sysIO Buffer Pairs The sysIO buffer pairs in the left and right Banks of the device consist of two single-ended output drivers and two sets of single-ended input buffers (supporting ratioed and absolute input levels). The devices also have a differential driver per output pair. The referenced input buffer can also be configured as a differential input buffer. In these Banks the two pads in the pair are described as “true” and “comp”, where the true pad is associated with the positive side of the differential I/O, and the comp (complementary) pad is associated with the negative side of the differential I/O. Typical I/O Behavior During Power-up The internal power-on-reset (POR) signal is deactivated when VCC and VCCAUX have reached satisfactory levels. After the POR signal is deactivated, the FPGA core logic becomes active. It is the user’s responsibility to ensure that all VCCIO Banks are active with valid input logic levels to properly control the output logic states of all the I/O Banks that are critical to the application. The default configuration of the I/O pins in a blank device is tri-state with a weak pull-up to VCCIO. The I/O pins will maintain the blank configuration until VCC, VCCAUX and VCCIO have reached satisfactory levels at which time the I/Os will take on the user-configured settings. The VCC and VCCAUX supply the power to the FPGA core fabric, whereas the VCCIO supplies power to the I/O buffers. In order to simplify system design while providing consistent and predictable I/O behavior, the I/O buffers should be powered up along with the FPGA core fabric. Therefore, VCCIO supplies should be powered up before or together with the VCC and VCCAUX supplies Supported Standards The MachXO sysIO buffer supports both single-ended and differential standards. Single-ended standards can be further subdivided into LVCMOS and LVTTL. The buffer supports the LVTTL, LVCMOS 1.2, 1.5, 1.8, 2.5, and 3.3V standards. In the LVCMOS and LVTTL modes, the buffer has individually configurable options for drive strength, bus maintenance (weak pull-up, weak pull-down, bus-keeper latch or none) and open drain. BLVDS and LVPECL output emulation is supported on all devices. The MachXO1200 and MachXO2280 support on-chip LVDS output buffers on approximately 50% of the I/Os on the left and right Banks. Differential receivers for LVDS, BLVDS and LVPECL are supported on all Banks of MachXO1200 and MachXO2280 devices. PCI support is provided in the top Banks of the MachXO1200 and MachXO2280 devices. Table 2-8 summarizes the I/O characteristics of the devices in the MachXO family. Tables 2-9 and 2-10 show the I/O standards (together with their supply and reference voltages) supported by the MachXO devices. For further information on utilizing the sysIO buffer to support a variety of standards please see the details of additional technical documentation at the end of this data sheet. 2-16 Lattice Semiconductor Table 2-8. I/O Support Device by Device MachXO256 Number of I/O Banks 2 Single-ended (all I/O Banks) Type of Input Buffers 4 Single-ended (all I/O Banks) MachXO640 8 Architecture MachXO Family Data Sheet MachXO1200 8 Single-ended (all I/O Banks) Differential Receivers (all I/O Banks) MachXO2280 Single-ended (all I/O Banks) Differential Receivers (all I/O Banks) Single-ended buffers with complementary outputs (all I/O Banks) Single-ended buffers with complementary outputs (all I/O Banks) Types of Output Buffers Single-ended buffers with complementary outputs (all I/O Banks) Single-ended buffers with complementary outputs (all I/O Banks) Differential buffers with Differential buffers with true LVDS outputs (50% true LVDS outputs (50% on left and right side) on left and right side) Differential Output Emulation Capability PCI Support All I/O Banks No All I/O Banks No All I/O Banks Top side only All I/O Banks Top side only Table 2-9. Supported Input Standards VCCIO (Typ.) Input Standard Single Ended Interfaces LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 PCI1 Differential Interfaces BLVDS2, LVDS2, LVPECL2, RSDS2 √ √ √ √ √ 1. Top Banks of MachXO1200 and MachXO2280 devices only. 2. MachXO1200 and MachXO2280 devices only. 3.3V √ √ √ 2.5V √ √ √ 1.8V √ √ √ √ 1.5V √ √ √ √ 1.2V √ √ √ √ √ √ √ √ √ 2-17 Lattice Semiconductor Table 2-10. Supported Output Standards Output Standard Single-ended Interfaces LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 LVCMOS33, Open Drain LVCMOS25, Open Drain LVCMOS18, Open Drain LVCMOS15, Open Drain LVCMOS12, Open Drain PCI333 Differential Interfaces LVDS1, 2 BLVDS, RSDS LVPECL2 2 Architecture MachXO Family Data Sheet Drive 4mA, 8mA, 12mA, 16mA 4mA, 8mA, 12mA, 14mA 4mA, 8mA, 12mA, 14mA 4mA, 8mA, 12mA, 14mA 4mA, 8mA 2mA, 6mA 4mA, 8mA, 12mA, 14mA 4mA, 8mA, 12mA, 14mA 4mA, 8mA, 12mA, 14mA 4mA, 8mA 2mA, 6mA N/A N/A N/A N/A VCCIO (Typ.) 3.3 3.3 2.5 1.8 1.5 1.2 — — — — — 3.3 2.5 2.5 3.3 1. MachXO1200 and MachXO2280 devices have dedicated LVDS buffers. 2. These interfaces can be emulated with external resistors in all devices. 3. Top Banks of MachXO1200 and MachXO2280 devices only. sysIO Buffer Banks The number of Banks vary between the devices of this family. Eight Banks surround the two larger devices, the MachXO1200 and MachXO2280 (two Banks per side). The MachXO640 has four Banks (one Bank per side). The smallest member of this family, the MachXO256, has only two Banks. Each sysIO buffer Bank is capable of supporting multiple I/O standards. Each Bank has its own I/O supply voltage (VCCIO) which allows it to be completely independent from the other Banks. Figure 2-18, Figure 2-18, Figure 2-20 and Figure 2-21 shows the sysIO Banks and their associated supplies for all devices. 2-18 Lattice Semiconductor Figure 2-18. MachXO2280 Banks GND VCCIO0 1 1 Architecture MachXO Family Data Sheet VCCIO1 35 1 GND 36 1 Bank 0 Bank 1 Bank 7 VCCIO7 GND VCCIO2 GND Bank 2 34 1 34 1 Bank 6 VCCIO6 GND VCCIO3 GND Bank 3 33 1 Bank 5 31 1 Bank 4 33 35 VCCIO5 VCCIO4 Figure 2-19. MachXO1200 Banks GND VCCIO0 1 1 GND Bank 0 24 1 GND VCCIO1 Bank 1 GND 30 1 Bank 7 VCCIO7 GND VCCIO2 GND Bank 2 26 1 26 1 Bank 6 VCCIO6 GND VCCIO3 GND Bank 3 28 1 Bank 5 20 1 Bank 4 28 29 VCCIO5 VCCIO4 GND 2-19 GND Lattice Semiconductor Figure 2-20. MachXO640 Banks V CCO0 GND Architecture MachXO Family Data Sheet 1 1 Bank 0 42 1 Bank 3 V CCO3 GND V CCO1 GND Bank 1 40 1 Bank 2 40 37 VCCO2 Figure 2-21. MachXO256 Banks GND V CCO0 1 1 Bank 0 GND Bank 1 GND V CCO1 41 37 Hot Socketing The MachXO devices have been carefully designed to ensure predictable behavior during power-up and powerdown. Leakage into I/O pins is controlled to within specified limits. This allows for easy integration with the rest of 2-20 Lattice Semiconductor Architecture MachXO Family Data Sheet the system. These capabilities make the MachXO ideal for many multiple power supply and hot-swap applications. Sleep Mode The MachXO “C” devices (VCC = 1.8/2.5/3.3V) have a sleep mode that allows standby current to be reduced dramatically during periods of system inactivity. Entry and exit to Sleep mode is controlled by the SLEEPN pin. During Sleep mode, the logic is non-operational, registers and EBR contents are not maintained, and I/Os are tristated. Do not enter Sleep mode during device programming or configuration operation. In Sleep mode, power supplies are in their normal operating range, eliminating the need for external switching of power supplies. Table 2-11 compares the characteristics of Normal, Off and Sleep modes. Table 2-11. Characteristics of Normal, Off and Sleep Modes Characteristic SLEEPN Pin Static Icc I/O Leakage Power Supplies VCC/VCCIO/VCCAUX Logic Operation I/O Operation JTAG and Programming circuitry EBR Contents and Registers Normal High Typical H) Other LVCMOS (Z -> L) LVTTL + LVCMOS (H -> Z) LVTTL + LVCMOS (L -> Z) 188 0pF 1.5 VCCIO/2 VCCIO/2 VOH - 0.15 VOL - 0.15 Note: Output test conditions for all other interfaces are determined by the respective standards. 3-18 MachXO Family Data Sheet Pinout Information November 2007 Data Sheet DS1002 Signal Descriptions Signal Name General Purpose [Edge] indicates the edge of the device on which the pad is located. Valid edge designations are L (Left), B (Bottom), R (Right), T (Top). [Row/Column Number] indicates the PFU row or the column of the device on which the PIO Group exists. When Edge is T (Top) or (Bottom), only need to specify Row Number. When Edge is L (Left) or R (Right), only need to specify Column Number. P[Edge] [Row/Column Number]_[A/B/C/D/E/F] [A/B/C/D/E/F] indicates the PIO within the group to which the pad is connected. I/O Some of these user programmable pins are shared with special function pins. When not used as special function pins, these pins can be programmed as I/Os for user logic. During configuration of the user-programmable I/Os, the user has an option to tri-state the I/Os and enable an internal pull-up resistor. This option also applies to unused pins (or those not bonded to a package pin). The default during configuration is for user-programmable I/Os to be tri-stated with an internal pull-up resistor enabled. When the device is erased, I/Os will be tri-stated with an internal pull-up resistor enabled. GSRN TSALL NC GND VCC VCCAUX VCCIOx SLEEPN1 I I — — — — — I Global RESET signal (active low). Dedicated pad, when not in use it can be used as an I/O pin. TSALL is a dedicated pad for the global output enable signal. When TSALL is high all the outputs are tristated. It is a dual function pin. When not in use, it can be used as an I/O pin. No connect. GND - Ground. Dedicated pins. VCC - The power supply pins for core logic. Dedicated pins. VCCAUX - the Auxiliary power supply pin. This pin powers up a variety of internal circuits including all the differential and referenced input buffers. Dedicated pins. VCCIO - The power supply pins for I/O Bank x. Dedicated pins. Sleep Mode pin - Active low sleep pin. When this pin is held high, the device operates normally. This pin has a weak internal pull-up, but when unused, an external pull-up to VCC is recommended. When driven low, the device moves into Sleep mode after a specified time. Reference clock (PLL) input Pads: [LOC] indicates location. Valid designations are ULM (Upper PLL) and LLM (Lower PLL). T = true and C = complement. Optional feedback (PLL) input Pads: [LOC] indicates location. Valid designations are ULM (Upper PLL) and LLM (Lower PLL). T = true and C = complement. Primary Clock Pads, n per side. Test Mode Select input pin, used to control the 1149.1 state machine. Test Clock input pin, used to clock the 1149.1 state machine. Test Data input pin, used to load data into the device using an 1149.1 state machine. Output pin -Test Data output pin used to shift data out of the device using 1149.1. I/O Descriptions PLL and Clock Functions (Used as user programmable I/O pins when not used for PLL or clock pins) [LOC][0]_PLL[T, C]_IN [LOC][0]_PLL[T, C]_FB PCLK [n]_[1:0] TMS TCK TDI TDO — — — I I I O Test and Programming (Dedicated pins) 1. Applies to MachXO “C” devices only. NC for “E” devices. © 2006 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 4-1 DS1002 Pinouts_01.7 Lattice Semiconductor Pinout Information MachXO Family Data Sheet Pin Information Summary LCMXO256C/E Pin Type Single Ended User I/O Differential Pair User I/O1 Muxed TAP Dedicated (Total Without Supplies) VCC VCCAUX Bank0 VCCIO Bank1 Bank2 Bank3 GND NC Bank0 Single Ended/Differential I/O per Bank Bank1 Bank2 Bank3 100 TQFP 78 38 6 4 5 2 1 3 3 — — 8 0 41/20 37/18 — — 100 csBGA 78 38 6 4 5 2 1 3 3 — — 8 0 41/20 37/18 — — 100 TQFP 74 17 6 4 5 2 1 2 2 2 2 10 0 18/5 21/4 14/2 21/6 144 TQFP 113 43 6 4 5 4 2 2 2 2 2 12 0 29/10 30/11 24/9 30/13 LCMXO640C/E 100 csBGA 74 17 6 4 5 2 1 2 2 2 2 10 0 18/5 21/4 14/2 21/6 132 csBGA 101 42 6 4 5 4 2 2 2 2 2 12 0 26/11 27/12 21/9 27/10 256 ftBGA 159 79 6 4 5 4 2 4 4 4 4 18 52 42/21 40/20 36/18 40/20 1. These devices support emulated LVDS outputs. LVDS inputs are not supported. LCMXO1200C/E Pin Type Single Ended User I/O Differential Pair User I/O1 Muxed TAP Dedicated (Total Without Supplies) VCC VCCAUX Bank0 Bank1 Bank2 VCCIO Bank3 Bank4 Bank5 Bank6 Bank7 GND NC Bank0 Bank1 Bank2 Single Ended/Differential I/O per Bank Bank3 Bank4 Bank5 Bank6 Bank7 100 TQFP 73 27 6 4 5 4 2 1 1 1 1 1 1 1 1 8 0 10/3 8/2 10/4 11/5 8/3 5/2 10/3 11/5 144 TQFP 113 48 6 4 5 4 2 1 1 1 1 1 1 1 1 12 0 14/6 15/7 15/7 15/7 14/5 10/4 15/6 15/6 132 csBGA 101 42 6 4 5 4 2 1 1 1 1 1 1 1 1 12 0 13/5 13/5 13/6 14/7 13/5 8/2 13/6 14/6 256 ftBGA 211 105 6 4 5 4 2 2 2 2 2 2 2 2 2 18 0 26/13 28/14 26/13 28/14 27/13 22/11 28/14 26/13 100 TQFP 73 30 6 4 5 2 2 1 1 1 1 1 1 1 1 8 0 9/3 9/3 10/4 11/5 8/3 5/2 10/4 11/5 144 TQFP 113 47 6 4 5 4 2 1 1 1 1 1 1 1 1 12 0 13/6 16/7 15/7 15/7 14/4 10/4 15/6 15/6 LCMXO2280C/E 132 csBGA 101 41 6 4 5 4 2 1 1 1 1 1 1 1 1 12 0 12/5 14/5 13/6 14/7 13/4 8/2 13/6 14/6 256 ftBGA 211 105 6 4 5 4 2 2 2 2 2 2 2 2 2 18 0 24/12 30/15 26/13 28/14 29/14 20/10 28/14 26/13 324 ftBGA 271 134 6 4 5 6 2 2 2 2 2 2 2 2 2 24 0 34/17 36/18 34/17 34/17 35/17 30/15 34/17 34/17 1. These devices support on-chip LVDS buffers for left and right I/O Banks. 4-2 Lattice Semiconductor Pinout Information MachXO Family Data Sheet Power Supply and NC Signal VCC VCCIO0 100 TQFP1 LCMXO256/640: 35, 90 LCMXO1200/2280: 17, 35, 66, 91 LCMXO256: 60, 74, 92 LCMXO640: 80, 92 LCMXO1200/2280: 94 LCMXO256: 10, 24, 41 LCMXO640: 60, 74 LCMXO1200/2280: 80 LCMXO256: None LCMXO640: 29, 41 LCMXO1200/2280: 70 LCMXO256: None LCMXO640: 10, 24 LCMXO1200/2280: 56 LCMXO256/640: None LCMXO1200/2280: 44 LCMXO256/640: None LCMXO1200/2280: 27 LCMXO256/640: None LCMXO1200/2280: 20 LCMXO256/640: None LCMXO1200/2280: 6 LCMXO256/640: 88 LCMXO1200/2280: 36, 90 144 TQFP1 21, 52, 93, 129 LCMXO640: 117, 135 LCMXO1200/2280: 135 LCMXO640: 82, 98 LCMXO1200/2280: 117 LCMXO640: 38, 63 LCMXO1200/2280: 98 LCMXO640: 10, 26 LCMXO1200/2280: 82 LCMXO640: None LCMXO1200/2280: 63 LCMXO640: None LCMXO1200/2280: 38 LCMXO640: None LCMXO1200/2280: 26 LCMXO640: None LCMXO1200/2280: 10 53, 128 P7, B6 LCMXO256: H14, A14, B5 LCMXO640: B12, B5 LCMXO256: G1, P1, P10 LCMXO640: H14, A14 LCMXO256: None LCMXO640: P4, P10 LCMXO256: None LCMXO640: G1, P1 — — — — B7 LCMXO256: N9, B9, G14, B13, A4, H1, N2, N10 LCMXO640: N9, B9, A10, A4, G14, B13, N3, N10, H1, N2 100 csBGA2 VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCAUX GND3 LCMXO256: 40, 84, 62, 75, 93, 12, 16, 59, 88, 123, 118, 136, 83, 99, 25, 42 37, 64, 11, 27 LCMXO640: 40, 84, 81, 93, 62, 75, 30, 42, 12, 25 LCMXO1200/2280: 9, 41, 59, 83, 100, 76, 50, 26 NC4 — 1. Pin orientation follows the conventional order from pin 1 marking of the top side view and counter-clockwise. 2. Pin orientation A1 starts from the upper left corner of the top side view with alphabetical order ascending vertically and numerical order ascending horizontally. 3. All grounds must be electrically connected at the board level. For fpBGA and ftBGA packages, the total number of GND balls is less than the actual number of GND logic connections from the die to the common package GND plane. 4. NC pins should not be connected to any active signals, VCC or GND. 4-3 Lattice Semiconductor Pinout Information MachXO Family Data Sheet Power Supply and NC (Cont.) Signal VCC VCCIO0 VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCAUX GND2 132 csBGA1 H3, P6, G12, C7 LCMXO640: B11, C5 LCMXO1200/2280: C5 LCMXO640: L12, E12 LCMXO1200/2280: B11 LCMXO640: N2, M10 LCMXO1200/2280: E12 LCMXO640: D2, K3 LCMXO1200/2280: L12 LCMXO640: None LCMXO1200/2280: M10 LCMXO640: None LCMXO1200/2280: N2 LCMXO640: None LCMXO1200/2280: K3 LCMXO640: None LCMXO1200/2280: D2 P7, A7 F1, P9, J14, C9, A10, B4, L13, D13, P2, N11, E1, L2 256 ftBGA1 G7, G10, K7, K10 LCMXO640: F8, F7, F9, F10 LCMXO1200/2280: F8, F7 LCMXO640: H11, G11, K11, J11 LCMXO1200/2280: F9, F10 LCMXO640: L9, L10, L8, L7 LCMXO1200/2280: H11, G11 LCMXO640: K6, J6, H6, G6 LCMXO1200/2280: K11, J11 LCMXO640: None LCMXO1200/2280: L9, L10 LCMXO640: None LCMXO1200/2280: L8, L7 LCMXO640: None LCMXO1200/2280: K6, J6 LCMXO640: None LCMXO1200/2280: H6, G6 T9, A8 G8, G7 G12, G10 J12, H12 L12, K12 M12, M11 M8, R9 M7, K7 H6, J7 M10, F9 324 ftBGA1 F14, G11, G9, H7, L7, M9 A1, A16, F11, G8, G9, H7, H8, H9, E14, F16, H10, H11, H8, H9, J10, H10, J7, J8, J9, J10, K8, K9, L6, J11, J4, J8, J9, K10, K11, K17, K8, T1, T16 K9, L10, L11, L8, L9, N2, P14, P5, R7 — LCMXO640: E4, E5, F5, F6, C3, C2, G4, G5, H4, H5, K5, K4, M5, M4, P2, P3, N5, N6, M7, M8, N10, N11, R15, R16, P15, P16, M11, L11, N12, N13, M13, M12, K12, J12, F12, F13, E12, E13, D13, D14, B15, A15, C14, B14, E11, E10, E7, E6, D4, D3, B3, B2 LCMXO1200: None LCMXO2280: None NC3 — 1. Pin orientation A1 starts from the upper left corner of the top side view with alphabetical order ascending vertically and numerical order ascending horizontally. 2. All grounds must be electrically connected at the board level. For fpBGA and ftBGA packages, the total number of GND balls is less than the actual number of GND logic connections from the die to the common package GND plane. 3. NC pins should not be connected to any active signals, VCC or GND. 4-4 Lattice Semiconductor Pinout Information MachXO Family Data Sheet LCMXO256 and LCMXO640 Logic Signal Connections: 100 TQFP LCMXO256 Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Ball Function PL2A PL2B PL3A PL3B PL3C PL3D PL4A PL4B PL5A VCCIO1 PL5B GNDIO1 PL5C PL5D PL6A PL6B PL7A PL7B PL7C PL7D PL8A PL8B PL9A VCCIO1 GNDIO1 TMS PL9B TCK PB2A PB2B TDO PB2C TDI PB2D VCC PB3A PB3B PB3C PB3D GND VCCIO1 GNDIO1 Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 PCLK1_0** PCLK1_1** T C T C TDI C TDO T TCK T C TMS C TSALL GSRN T C T C T C T C T C T C Dual Function Differential T C T C T C T C T Ball Function PL2A PL2C PL2B PL2D PL3A PL3B PL3C PL3D PL4A VCCIO3 PL4C GNDIO3 PL4D PL5B PL7B PL8C PL8D PL9A PL9C PL10A PL10C PL11A PL11C VCCIO3 GNDIO3 TMS PB2C TCK VCCIO2 GNDIO2 TDO PB4C TDI PB4E VCC PB5B PB5D PB6B PB6C GND VCCIO2 GNDIO2 LCMXO640 Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 PCLK2_0** PCLK2_1** TDI TDO TCK TMS TSALL T C GSRN C T Dual Function Differential T T C C T C T C 4-5 Lattice Semiconductor Pinout Information MachXO Family Data Sheet LCMXO256 and LCMXO640 Logic Signal Connections: 100 TQFP (Cont.) LCMXO256 Pin Number 43 44 45 46 47 48* 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Ball Function PB4A PB4B PB4C PB4D PB5A SLEEPN PB5C PB5D PR9B PR9A PR8B PR8A PR7D PR7C PR7B PR7A PR6B VCCIO0 PR6A GNDIO0 PR5D PR5C PR5B PR5A PR4B PR4A PR3D PR3C PR3B PR3A PR2B VCCIO0 GNDIO0 PR2A PT5C PT5B PT5A PT4F PT4E PT4D PT4C GND Bank 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C T C T C T T C T C T C T C T C T C T SLEEPN T C C T C T C T C T C Dual Function Differential T C T C Ball Function PB8B PB8C PB8D PB9A PB9C SLEEPN PB9D PB9F PR11D PR11B PR11C PR11A PR10D PR10C PR10B PR10A PR9D VCCIO1 PR9B GNDIO1 PR7B PR6C PR6B PR5D PR5B PR4D PR4B PR3D PR3B PR2D PR2B VCCIO1 GNDIO1 PT9F PT9E PT9C PT9A VCCIO0 GNDIO0 PT7E PT7A GND LCMXO640 Bank 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 C T C C T T C T C T SLEEPN C T T C Dual Function Differential 4-6 Lattice Semiconductor Pinout Information MachXO Family Data Sheet LCMXO256 and LCMXO640 Logic Signal Connections: 100 TQFP (Cont.) LCMXO256 Pin Number 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Ball Function PT4B PT4A PT3D VCCAUX PT3C VCC PT3B VCCIO0 GNDIO0 PT3A PT2F PT2E PT2D PT2C PT2B PT2A Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T C T C T C T C T Dual Function PCLK0_1** PCLK0_0** Differential C T C Ball Function PT6B PT5B PT5A VCCAUX PT4F VCC PT3F VCCIO0 GNDIO0 PT3B PT3A PT2F PT2E PT2B PT2C PT2A LCMXO640 Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T C T C T C Dual Function PCLK0_1** PCLK0_0** C T Differential * NC for “E” devices. ** Primary clock inputs are single-ended. 4-7 Lattice Semiconductor Pinout Information MachXO Family Data Sheet LCMXO1200 and LCMXO2280 Logic Signal Connections: 100 TQFP LCMXO1200 Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26** 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 Ball Function PL2A PL2B PL3C PL3D PL4B VCCIO7 PL6A PL6B GND PL7C PL7D PL8C PL8D PL9C PL10A PL10B VCC PL11B PL11C VCCIO6 PL13C PL14A PL14B PL15A PL15B GNDIO6 GNDIO5 VCCIO5 TMS TCK PB3B PB4A PB4B TDO TDI VCC VCCAUX PB6E PB6F PB7B PB7F GND Bank 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 4 PCLK4_1**** PCLK4_0**** T C TDO TDI T C TMS TCK LLM0_PLLT_FB_A LLM0_PLLC_FB_A LLM0_PLLT_IN_A LLM0_PLLC_IN_A T* C* T* C* TSALL T* C* T C T C GSRN T* C* Dual Function Differential T C T C Ball Function PL2A PL2B PL3C PL3D PL4B VCCIO7 PL7A PL7B GND PL9C PL9D PL10C PL10D PL11C PL13A PL13B VCC PL14D PL14C VCCIO6 PL16C PL17A PL17B PL18A PL18B GNDIO6 GNDIO5 VCCIO5 TMS TCK PB3B PB4A PB4B TDO TDI VCC VCCAUX PB8E PB8F PB10F PB10B GND Bank 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 4 PCLK4_1**** PCLK4_0**** T C TDO TDI T C TMS TCK LLM0_PLLT_FB_A LLM0_PLLC_FB_A LLM0_PLLT_IN_A LLM0_PLLC_IN_A T* C* T* C* TSALL C T T* C* T C T C GSRN T* C* LCMXO2280 Dual Function LUM0_PLLT_FB_A LUM0_PLLC_FB_A LUM0_PLLT_IN_A LUM0_PLLC_IN_A Differential T C T C 4-8 Lattice Semiconductor Pinout Information MachXO Family Data Sheet LCMXO1200 and LCMXO2280 Logic Signal Connections: 100 TQFP (Cont.) LCMXO1200 Pin Number 42 43 44 45 46 47*** 48 49 50** 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76** 77 78 79 80 81 Ball Function PB9A PB9B VCCIO4 PB10A PB10B SLEEPN PB11A PB11B GNDIO3 GNDIO4 PR16B PR15B PR15A PR14B PR14A VCCIO3 PR12B PR12A GND PR10B PR10A PR9B PR9A PR8B PR8A VCC PR6C PR6B PR6A VCCIO2 PR4D PR4B PR4A PR2B PR2A GNDIO1 GNDIO2 PT11C PT11B PT11A VCCIO1 PT9E Bank 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 C T C* T* C T C* T* C* T* C* T* C* T* C* T* C* T* C* T* SLEEPN T C T C Dual Function Differential T C Ball Function PB12A PB12B VCCIO4 PB13A PB13B SLEEPN PB16A PB16B GNDIO3 GNDIO4 PR19B PR18B PR18A PR17B PR17A VCCIO3 PR15B PR15A GND PR13B PR13A PR11B PR11A PR10B PR10A VCC PR8C PR8B PR8A VCCIO2 PR5D PR5B PR5A PR3B PR3A GNDIO1 GNDIO2 PT15C PT14B PT14A VCCIO1 PT12D Bank 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 C C T C* T* C* T* C* T* C* T* C* T* C* T* C* T* C* T* C* T* SLEEPN T C T C LCMXO2280 Dual Function Differential T C 4-9 Lattice Semiconductor Pinout Information MachXO Family Data Sheet LCMXO1200 and LCMXO2280 Logic Signal Connections: 100 TQFP (Cont.) LCMXO1200 Pin Number 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100** Ball Function PT9A GND PT8B PT8A PT7D PT6F PT6D PT6C VCCAUX VCC PT5B PT4B VCCIO0 PT3D PT3C PT3B PT2B PT2A GNDIO0 GNDIO7 Bank 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 C T C T PCLK1_1**** PCLK1_0**** C T C T Dual Function Differential Ball Function PT12C GND PT11B PT11A PT10B PT9B PT8F PT8E VCCAUX VCC PT6D PT6F VCCIO0 PT4B PT4A PT3B PT2B PT2A GNDIO0 GNDIO7 Bank 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 C T C T PCLK1_1**** PCLK1_0**** C T C T LCMXO2280 Dual Function Differential T *Supports true LVDS outputs. **Double bonded to the pin. ***NC for "E" devices. ****Primary clock inputs are single-ended. 4-10 Lattice Semiconductor Pinout Information MachXO Family Data Sheet LCMXO256 and LCMXO640 Logic Signal Connections: 100 csBGA LCMXO256 Ball Number B1 C1 D2 D1 C2 E1 E2 F1 F2 G2 H1 H2 J1 J2 K1 K2 L1 L2 M1 M2 N1 M3 N2 P2 P3 N4 P4 N3 P5 N5 P6 N6 P7 N7 P8 N8 P9 N10 P11 N11 P12 N12 Ball Function PL2A PL2B PL3A PL3B PL3C PL3D PL4A PL4B PL5A PL5B GNDIO1 PL5C PL5D PL6A PL6B PL7A PL7B PL7C PL7D PL8A PL8B PL9A GNDIO1 TMS PL9B TCK PB2A PB2B TDO PB2C TDI PB2D VCC PB3A PB3B PB3C PB3D GNDIO1 PB4A PB4B PB4C PB4D Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 T C T C PCLK1_0** PCLK1_1** T C T C TDI C TDO T TCK T C TMS C TSALL GSRN T C T C T C T C T C T Dual Function Differential T C T C T C T C T C Ball Number B1 C1 D2 D1 C2 E1 E2 F1 F2 G2 H1 H2 J1 J2 K1 K2 L1 L2 M1 M2 N1 M3 N2 P2 P3 N4 P4 N3 P5 N5 P6 N6 P7 N7 P8 N8 P9 N10 P11 N11 P12 N12 Ball Function PL2A PL2C PL2B PL2D PL3A PL3B PL3C PL3D PL4A PL4C GNDIO3 PL4D PL5B PL7B PL8C PL8D PL9A PL9C PL10A PL10C PL11A PL11C GNDIO3 TMS PB2C TCK VCCIO2 GNDIO2 TDO PB4C TDI PB4E VCC PB5B PB5D PB6B PB6C GNDIO2 PB8B PB8C PB8D PB9A LCMXO640 Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 T C PCLK2_0** PCLK2_1** TDI TDO TCK TMS TSALL T C GSRN C T Dual Function Differential T T C C T C T C 4-11 Lattice Semiconductor Pinout Information MachXO Family Data Sheet LCMXO256 and LCMXO640 Logic Signal Connections: 100 csBGA (Cont.) LCMXO256 Ball Number P13 M12* P14 N13 N14 M14 L13 L14 M13 K14 K13 J14 J13 H13 G14 G13 F14 F13 E14 E13 D14 D13 C14 C13 B14 C12 B13 A13 A12 B11 A11 B12 A10 B10 A9 A8 B8 A7 B7 A6 B6 A5 Ball Function PB5A SLEEPN PB5C PB5D PR9B PR9A PR8B PR8A PR7D PR7C PR7B PR7A PR6B PR6A GNDIO0 PR5D PR5C PR5B PR5A PR4B PR4A PR3D PR3C PR3B PR3A PR2B GNDIO0 PR2A PT5C PT5B PT5A PT4F PT4E PT4D PT4C PT4B PT4A PT3D VCCAUX PT3C VCC PT3B Bank 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C T PCLK0_1** PCLK0_0** C T C T C T C T C T C T C T C T C T C T C SLEEPN T C C T C T C T C T C T Dual Function Differential Ball Number P13 M12* P14 N13 N14 M14 L13 L14 M13 K14 K13 J14 J13 H13 G14 G13 F14 F13 E14 E13 D14 D13 C14 C13 B14 C12 B13 A13 A12 B11 A11 B12 A10 B10 A9 A8 B8 A7 B7 A6 B6 A5 Ball Function PB9C SLEEPN PB9D PB9F PR11D PR11B PR11C PR11A PR10D PR10C PR10B PR10A PR9D PR9B GNDIO1 PR7B PR6C PR6B PR5D PR5B PR4D PR4B PR3D PR3B PR2D PR2B GNDIO1 PT9F PT9E PT9C PT9A VCCIO0 GNDIO0 PT7E PT7A PT6B PT5B PT5A VCCAUX PT4F VCC PT3F LCMXO640 Bank 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 PCLK0_1** PCLK0_0** C T C T C C T T C T C T SLEEPN C Dual Function Differential T 4-12 Lattice Semiconductor Pinout Information MachXO Family Data Sheet LCMXO256 and LCMXO640 Logic Signal Connections: 100 csBGA (Cont.) LCMXO256 Ball Number A4 B4 A3 B3 A2 C3 A1 B2 N9 B9 B5 A14 H14 P10 G1 P1 Ball Function GNDIO0 PT3A PT2F PT2E PT2D PT2C PT2B PT2A GND GND VCCIO0 VCCIO0 VCCIO0 VCCIO1 VCCIO1 VCCIO1 Bank 0 0 0 0 0 0 0 0 0 0 0 1 1 1 T C T C T C T Dual Function Differential Ball Number A4 B4 A3 B3 A2 C3 A1 B2 N9 B9 B5 A14 H14 P10 G1 P1 Ball Function GNDIO0 PT3B PT3A PT2F PT2E PT2B PT2C PT2A GND GND VCCIO0 VCCIO1 VCCIO1 VCCIO2 VCCIO3 VCCIO3 LCMXO640 Bank 0 0 0 0 0 0 0 0 0 1 1 2 3 3 T C T C T C Dual Function Differential *NC for “E” devices. **Primary clock inputs are single-ended. 4-13 Lattice Semiconductor Pinout Information MachXO Family Data Sheet LCMXO640, LCMXO1200 and LCMXO2280 Logic Signal Connections: 132 csBGA LCMXO640 Ball Ball # Function Bank B1 C1 B2 C2 C3 D1 D3 E1 E2 E3 F2 F3 G1 G2 G3 H2 H1 H3 J1 J2 J3 K2 K1 L2 L1 L3 M1 N1 M2 P1 P2 P3 M3 N3 P4 M4 N4 P5 N5 M5 N6 P6 M6 P7 N7 M7 N8 P8 M8 N9 PL2A PL2B PL2C PL2D PL3A PL3B PL3D GNDIO3 PL5A PL5B PL5D PL6B PL6C PL6D PL7A PL7B PL7C VCC PL8A PL8C PL9A PL9B PL9C GNDIO3 PL10A PL10B PL11A PL11B PL11C PL11D GNDIO2 TMS PB2C PB2D TCK PB3B PB3C PB3D TDO TDI PB4E VCC PB4F VCCAUX PB5A PB5B PB5D PB6A PB6B PB7A 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 PCLK2_0*** T C T PCLK2_1*** T C C TDO TDI T T C TCK TMS T C T C T C T C TSALL T C T C T C GSRN T C Dual Function LCMXO1200 Ball Differential Ball # Function Bank T C T C T C B1 C1 B2 C2 C3 D1 D3 E1 E2 E3 F2 F3 G1 G2 G3 H2 H1 H3 J1 J2 J3 K2 K1 L2 L1 L3 M1 N1 M2 P1 P2 P3 M3 N3 P4 M4 N4 P5 N5 M5 N6 P6 M6 P7 N7 M7 N8 P8 M8 N9 PL2A PL3C PL2B PL4A PL3D PL4B PL4C GNDIO7 PL6A PL6B PL6D PL7C PL7D PL8C PL8D PL10A PL10B VCC PL11B PL11C PL11D PL12A PL12B GNDIO6 PL14A PL14B PL15A PL16A PL15B PL16B GNDIO5 TMS PB2C PB2D TCK PB3B PB4A PB4B TDO TDI PB5C VCC PB6A VCCAUX PB6F PB7B PB7C PB7D PB7F PB9A 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 PCLK4_0*** T PCLK4_1*** T C TDO TDI T C TCK TMS T C LLM0_PLLC_IN_A LLM0_PLLT_FB_A LLM0_PLLC_FB_A LLM0_PLLT_IN_A T* C* T* T C* C TSALL T C T* C* T C T C T* C* GSRN T* C* Dual Function LCMXO2280 Ball Differential Ball # Function Bank T T C T* C C* B1 C1 B2 C2 C3 D1 D3 E1 E2 E3 F2 F3 G1 G2 G3 H2 H1 H3 J1 J2 J3 K2 K1 L2 L1 L3 M1 N1 M2 P1 P2 P3 M3 N3 P4 M4 N4 P5 N5 M5 N6 P6 M6 P7 N7 M7 N8 P8 M8 N9 PL2A PL3C PL2B PL4A PL3D PL4B PL4C GNDIO7 PL7A PL7B PL7D PL9C PL9D PL10C PL10D PL12A PL12B VCC PL14D PL14C PL14B PL15A PL15B GNDIO6 PL17A PL17B PL18A PL19A PL18B PL19B GNDIO5 TMS PB2A PB2B TCK PB3B PB4A PB4B TDO TDI PB6C VCC PB8A VCCAUX PB8F PB10F PB10C PB10D PB10B PB12A 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 PCLK4_0*** T PCLK4_1*** T C TDO TDI T C TCK TMS T C LLM0_PLLC_IN_A LLM0_PLLT_FB_A LLM0_PLLC_FB_A LLM0_PLLT_IN_A T* C* T* T C* C T* C* TSALL C T T C T C T* C* GSRN T* C* LUM0_PLLC_IN_A Dual Function LUM0_PLLT_FB_A LUM0_PLLT_IN_A LUM0_PLLC_FB_A Differential T T C T* C C* 4-14 Lattice Semiconductor Pinout Information MachXO Family Data Sheet LCMXO640, LCMXO1200 and LCMXO2280 Logic Signal Connections: 132 csBGA (Cont.) LCMXO640 Ball Ball # Function Bank M9 N10 P10 N11 P11 M11 P12 P13 N12** P14 N14 M14 N13 M12 M13 L14 L13 K14 K13 K12 J13 J12 H14 H13 H12 G13 G14 G12 F14 F13 F12 E13 E14 D13 D14 D12 C14 B14 C13 A14 A13 A12 B13 B12 C12 A11 C11 A10 B10 C10 PB7B PB7E PB7F GNDIO2 PB8C PB8D PB9C PB9D SLEEPN PB9F PR11D PR11C PR11B PR11A PR10B PR10A GNDIO1 PR8D PR8C PR8B PR8A PR7C PR7B PR7A PR6D PR6C PR6B VCC PR5D PR5C PR4D PR4C PR4B GNDIO1 PR3D PR3C PR2D PR2C PR2B PR2A PT9F PT9E PT9D PT9C PT9B PT9A PT8C GNDIO0 PT7F PT7E 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 C T C T C T C T C T C T C T C T C T C T C T C T C T C T C T C T SLEEPN T C T C Dual Function LCMXO1200 Ball Differential Ball # Function Bank C T C M9 N10 P10 N11 P11 M11 P12 P13 N12** P14 N14 M14 N13 M12 M13 L14 L13 K14 K13 K12 J13 J12 H14 H13 H12 G13 G14 G12 F14 F13 F12 E13 E14 D13 D14 D12 C14 B14 C13 A14 A13 A12 B13 B12 C12 A11 C11 A10 B10 C10 PB9B PB9C PB9D GNDIO4 PB10A PB10B PB10C PB11C SLEEPN PB11D PR16B PR15B PR16A PR15A PR14B PR14A GNDIO3 PR12B PR12A PR11B PR11A PR10B PR10A PR9B PR9A PR8B PR8A VCC PR6C PR6B PR6A PR5B PR5A GNDIO2 PR4B PR4A PR3D PR2B PR3C PR2A PT11D PT11B PT11C PT10F PT11A PT10D PT10C GNDIO1 PT9F PT9E 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 C T T C T C* T* C C T T C C T C* T* C* T* C* T* C* T* C* T* C* T* C* T* SLEEPN C C C* T T* C* T* T T C Dual Function LCMXO2280 Ball Differential Ball # Function Bank C T C M9 N10 P10 N11 P11 M11 P12 P13 N12** P14 N14 M14 N13 M12 M13 L14 L13 K14 K13 K12 J13 J12 H14 H13 H12 G13 G14 G12 F14 F13 F12 E13 E14 D13 D14 D12 C14 B14 C13 A14 A13 A12 B13 B12 C12 A11 C11 A10 B10 C10 PB12B PB12C PB12D GNDIO4 PB13C PB13D PB15B PB16C SLEEPN PB16D PR19B PR18B PR19A PR18A PR17B PR17A GNDIO3 PR15B PR15A PR14B PR14A PR13B PR13A PR11B PR11A PR10B PR10A VCC PR8C PR8B PR8A PR7B PR7A GNDIO2 PR5B PR5A PR4D PR3B PR4C PR3A PT16D PT16B PT16C PT15D PT16A PT14B PT14A GNDIO1 PT12F PT12E 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 C T T C T C* T* C C* T T* C C T C* T* C* T* C* T* C* T* C* T* C* T* C* T* SLEEPN C C C* T T* C* T* T T C Dual Function Differential C T C 4-15 Lattice Semiconductor Pinout Information MachXO Family Data Sheet LCMXO640, LCMXO1200 and LCMXO2280 Logic Signal Connections: 132 csBGA (Cont.) LCMXO640 Ball Ball # Function Bank B9 A9 A8 B8 C8 B7 A7 C7 A6 B6 C6 B5 A5 B4 A4 C4 A3 A2 B3 A1 F1 P9 J14 C9 C5 B11 E12 L12 M10 N2 D2 K3 PT7B PT7A PT6B PT6A PT5B PT5A VCCAUX VCC PT4D PT4C PT3F PT3E PT3D GNDIO0 PT3B PT2F PT2D PT2C PT2B PT2A GND GND GND GND VCCIO0 VCCIO0 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO3 VCCIO3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 2 2 3 3 C T C T C T C T PCLK0_0*** PCLK0_1*** Dual Function LCMXO1200 Ball Differential Ball # Function Bank C T C T C T B9 A9 A8 B8 C8 B7 A7 C7 A6 B6 C6 B5 A5 B4 A4 C4 A3 A2 B3 A1 F1 P9 J14 C9 C5 B11 E12 L12 M10 N2 D2 K3 PT9B PT9A PT7D PT7B PT6F PT6D VCCAUX VCC PT5D PT5C PT5B PT5A PT4B GNDIO0 PT3D PT3C PT3B PT2B PT3A PT2A GND GND GND GND VCCIO0 VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO7 VCCIO6 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 7 6 C T C C T T C T C T PCLK1_0*** PCLK1_1*** Dual Function LCMXO2280 Ball Differential Ball # Function Bank C T B9 A9 A8 B8 C8 B7 A7 C7 A6 B6 C6 B5 A5 B4 A4 C4 A3 A2 B3 A1 F1 P9 J14 C9 C5 B11 E12 L12 M10 N2 D2 K3 PT12D PT12C PT10B PT9D PT9B PT8D VCCAUX VCC PT7B PT7A PT6D PT6E PT6F GNDIO0 PT4B PT4A PT3B PT2B PT3A PT2A GND GND GND GND VCCIO0 VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO7 VCCIO6 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 7 6 C T C C T T T C C T PCLK1_0*** PCLK1_1*** Dual Function Differential C T *Supports true LVDS outputs. **NC for “E” devices. ***Primary clock inputs arer single-ended. 4-16 Lattice Semiconductor Pinout Information MachXO Family Data Sheet LCMXO640, LCMXO1200 and LCMXO2280 Logic Signal Connections: 144 TQFP LCMXO640 Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 LCMXO1200 Differential T T C T C C T C LCMXO2280 Differential T C T* C* T C T* C* Ball Function PL2A PL2C PL2B PL3A PL2D PL3B PL3C PL3D PL4A VCCIO3 GNDIO3 PL4D PL5A PL5B PL5D GND PL6C PL6D PL7A PL7B VCC PL8A PL8B PL8C PL9C VCCIO3 GNDIO3 PL9D PL10A PL10B PL10C PL11A PL10D PL11C PL11B PL11D GNDIO2 VCCIO2 TMS PB2C PB3A TCK PB3B PB3C PB3D PB4A TDO PB4B PB4C PB4D Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Dual Function Ball Function PL2A PL2B PL3A PL3B PL3C PL3D PL4A PL4B PL4C VCCIO7 GNDIO7 PL5C Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 5 5 5 5 Dual Function Ball Function PL2A PL2B PL3A PL3B PL3C PL3D PL4A PL4B PL4C VCCIO7 GNDIO7 PL6C Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 5 5 5 5 Dual Function LUM0_PLLT_FB_A LUM0_PLLC_FB_A Differential T C T* C* LUM0_PLLT_IN_A LUM0_PLLC_IN_A T C T* C* T GSRN C PL6A PL6B PL6D GND T* GSRN C* PL7A PL7B PL7D GND T* GSRN C* T C T C PL7C PL7D PL10A PL10B VCC T C T* C* PL9C PL9D PL13A PL13B VCC T C T* C* T C TSALL T PL11A PL11B PL11C PL12B VCCIO6 GNDIO6 T* C* TSALL PL13D PL14D PL14C PL15B VCCIO6 GNDIO6 PL16D C TSALL T C T C T T C T C C PL13D PL14A PL14B PL14C PL14D PL15A PL15B PL16A PL16B GNDIO5 VCCIO5 LLM0_PLLT_FB_A LLM0_PLLC_FB_A T* C* T C PL17A PL17B PL17C PL17D PL18A PL18B PL19A PL19B GNDIO5 VCCIO5 LLM0_PLLT_FB_A LLM0_PLLC_FB_A T* C* T C LLM0_PLLT_IN_A LLM0_PLLC_IN_A T* C* T C LLM0_PLLT_IN_A LLM0_PLLC_IN_A T* C* T C TMS TMS PB2C T PB2D TCK C T C T PB3A PB3B PB4A PB4B TDO C T C PB4D PB5A PB5B TMS T C TCK T C T C TDO TMS PB2A PB2B TCK PB3A PB3B PB4A PB4B TDO PB4D T C PB5A PB5B TMS T C TCK T C T C TDO TCK TDO T C 4-17 Lattice Semiconductor Pinout Information MachXO Family Data Sheet LCMXO640, LCMXO1200 and LCMXO2280 Logic Signal Connections: 144 TQFP (Cont.) LCMXO640 Pin Number 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70** 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 LCMXO1200 Differential Ball Function TDI VCC VCCAUX T PB6F PB7B PB7C T PB7D PB7F GND PB9A PB9B PB9E VCCIO4 GNDIO4 T C T T C PB10A PB10B PB10C PB10D PB10F SLEEPN C PB11C PB11D C C T C T C T T PR16B PR16A PR15B PR15A PR14D PR14C PR14B PR14A PR13D VCCIO3 GNDIO3 PR12B PR12A PR11B PR11A GND C T C T PR10B PR10A PR8B PR8A VCC PR6B PR6A PR5B C PR5A VCCIO2 GNDIO2 T PR4C LCMXO2280 Differential Ball Function TDI VCC VCCAUX PB8F Ball Function TDI VCC VCCAUX PB5A PB5B PB5D PB6A PB6B GND PB7C PB7E PB8A VCCIO2 GNDIO2 PB8C PB8D PB9A PB9C PB9B SLEEPN PB9D PB9F PR11D PR11B PR11C PR10D PR11A PR10B PR10C PR10A PR9D VCCIO1 GNDIO1 PR9A PR8C PR8A PR7D GND PR7B PR7A PR6D PR6C VCC PR5D PR5B PR4D PR4B VCCIO1 GNDIO1 PR4A Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Dual Function TDI Bank 5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 Dual Function TDI Bank 5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 Dual Function TDI Differential PCLKT2_1*** C PCLK4_1*** T C PCLK4_0*** PB10F PB10C PB10D PB10B GND T C PB12A PB12B PB12E VCCIO4 GNDIO4 T C T C PB13A PB13B PB13C PB13D PB14D PCLK4_1*** T C PCLK4_0*** PCLKT2_0*** C T C T C T C SLEEPN SLEEPN T C C T C* T* C T C* T* SLEEPN PB16C PB16D PR20B PR20A PR19B PR19A PR17D PR17C PR17B PR17A PR16D VCCIO3 GNDIO3 C* T* C* T* PR15B PR15A PR14B PR14A GND C* T* C* T* PR13B PR13A PR10B PR10A VCC C* T* C* T* PR8B PR8A PR7B PR7A VCCIO2 GNDIO2 PR5C SLEEPN T C C T C T C T C* T* C* T* C* T* C* T* C* T* C* T* C* T* 4-18 Lattice Semiconductor Pinout Information MachXO Family Data Sheet LCMXO640, LCMXO1200 and LCMXO2280 Logic Signal Connections: 144 TQFP (Cont.) LCMXO640 Pin Number 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 LCMXO1200 Differential C T C C T C T T C C T C T T LCMXO2280 Differential C* T* C T C* T* C T C T C T C T C T Ball Function PR3D PR3C PR3B PR2D PR3A PR2B PR2C PR2A PT9F PT9D PT9E PT9B PT9C PT9A PT8C PT8B VCCIO0 GNDIO0 PT8A PT7E PT7C PT7A GND PT6B PT6A PT5C PT5B VCCAUX VCC PT4D PT4B PT4A PT3F PT3D VCCIO0 GNDIO0 PT3B PT2F PT3A PT2D PT2E PT2B PT2C PT2A Bank 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Dual Function Ball Function PR4B PR4A PR3D PR3C PR3B PR3A PR2B PR2A PT11D PT11C PT11B PT11A PT10F PT10E PT10D Bank 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Dual Function Ball Function PR5B PR5A PR4D PR4C PR4B PR4A PR3B PR3A PT16D PT16C PT16B PT16A PT15D PT15C PT14B PT14A VCCIO1 GNDIO1 Bank 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Dual Function Differential C* T* C T C* T* C* T* C T C T C T C T C PT10C VCCIO1 GNDIO1 T PT9F PT9E PT9B PT9A GND C T C T PT12F PT12E PT12D PT12C GND C T C T PCLK0_1*** C T PT7D PT7B PT7A PCLK1_1*** C T PCLK1_0*** PT10B PT9D PT9C PT9B VCCAUX VCC C T C T PT7B PT7A PT6D PT6E PT6F VCCIO0 GNDIO0 C T C T C T C T PT4B PT4A PT3B PT3A PT2D PT2C PT2B PT2A PCLK1_1*** C T PCLK1_0*** PCLK0_0*** PT6F VCCAUX VCC PT5D C T PT5C PT5B PT5A PT4B VCCIO0 GNDIO0 C C T C T C T T PT3D PT3C PT3B PT3A PT2D PT2C PT2B PT2A C T T C T C C T C T C T *Supports true LVDS outputs. **NC for “E” devices. ***Primary clock inputs arer single-ended. 4-19 Lattice Semiconductor Pinout Information MachXO Family Data Sheet LCMXO640, LCMXO1200 and LCMXO2280 Logic Signal Connections: 256 ftBGA LCMXO640 Ball Ball Number Function Bank GND VCCIO3 E4 E5 F5 F6 F3 F4 E3 E2 C3 C2 B1 C1 VCCIO3 GND D2 D1 F2 G2 E1 F1 G4 G5 GND G3 H3 H4 H5 G1 H1 H2 J2 J3 K3 J1 K1 K2 L2 L1 M1 P1 N1 L3 M3 M2 N2 VCCIO3 GND GNDIO3 VCCIO3 NC NC NC NC PL3A PL3B PL2C PL2D NC NC PL2A PL2B VCCIO3 GNDIO3 PL3C PL3D PL5A PL5B PL4A PL4B NC NC GND PL4C PL4D NC NC PL5C PL5D PL6A PL6B PL7C PL7D PL6C PL6D PL9A PL9B PL7A PL7B PL8D PL8C PL10A PL10B PL9C PL9D VCCIO3 GNDIO3 3 3 3 3 3 3 3 3 3 3 3 3 3 TSALL C T C T C C T T C T C 3 3 3 3 3 3 3 T C T C T C T 3 3 T C 3 3 3 3 3 3 3 3 3 3 GSRN T C T C T C T C 3 3 3 3 T C T C 3 3 LCMXO1200 Ball Ball Differential Number Function Bank GND VCCIO7 E4 E5 F5 F6 F3 F4 E3 E2 C3 C2 B1 C1 VCCIO7 GND D2 D1 F2 G2 E1 F1 G4 G5 GND G3 H3 H4 H5 VCCIO7 GND G1 H1 H2 J2 J3 K3 J1 VCCIO6 GND K1 K2 L2 L1 M1 P1 N1 L3 M3 M2 N2 VCCIO6 GND GNDIO7 VCCIO7 PL2A PL2B PL3A PL3B PL3C PL3D PL4A PL4B PL4C PL4D PL5A PL5B VCCIO7 GNDIO7 PL5C PL5D PL6A PL6B PL6C PL6D PL7A PL7B GND PL7C PL7D PL8A PL8B VCCIO7 GNDIO7 PL8C PL8D PL9A PL9B PL9C PL9D PL10A VCCIO6 GNDIO6 PL10B PL10C PL10D PL11A PL11B PL11D PL11C PL12A PL12B PL12C PL12D VCCIO6 GNDIO6 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 TSALL C* T C T* C* C T T* C* T C T C T* C* T C T* T C T* C* GSRN T C T* C* T C T* C* T C T* C* T C T* C* T C T* C* LCMXO2280 Ball Ball Differential Number Function Bank GND VCCIO7 E4 E5 F5 F6 F3 F4 E3 E2 C3 C2 B1 C1 VCCIO7 GND D2 D1 F2 G2 E1 F1 G4 G5 GND G3 H3 H4 H5 VCCIO7 GND G1 H1 H2 J2 J3 K3 J1 VCCIO6 GND K1 K2 L2 L1 M1 P1 N1 L3 M3 M2 N2 VCCIO6 GND GNDIO7 VCCIO7 PL2A PL2B PL3A PL3B PL3C PL3D PL4A PL4B PL4C PL4D PL5A PL5B VCCIO7 GNDIO7 PL6C PL6D PL7A PL7B PL7C PL7D PL8A PL8B GND PL8C PL8D PL9A PL9B VCCIO7 GNDIO7 PL10C PL10D PL11A PL11B PL11C PL11D PL12A VCCIO6 GNDIO6 PL12B PL12C PL12D PL13A PL13B PL14D PL14C PL15A PL15B PL15C PL15D VCCIO6 GNDIO6 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 TSALL C* T C T* C* C T T* C* T C T C T* C* T C T* T C T* C* GSRN T C T* C* T C T* C* LUM0_PLLT_IN_A LUM0_PLLC_IN_A LUM0_PLLT_FB_A LUM0_PLLC_FB_A T C T* C* T C T* C* T C T* C* Dual Function Dual Function Dual Function Differential 4-20 Lattice Semiconductor Pinout Information MachXO Family Data Sheet LCMXO640, LCMXO1200 and LCMXO2280 Logic Signal Connections: 256 ftBGA (Cont.) LCMXO640 Ball Ball Number Function Bank J4 J5 R1 R2 K5 K4 L5 L4 M5 M4 N4 N3 VCCIO3 GND GND VCCIO2 P4 P2 P3 N5 R3 N6 T2 T3 R4 R5 P5 P6 T5 M6 T4 R6 GND VCCIO2 T6 N7 T8 T7 M7 M8 T9 R7 R8 P7 P8 N8 N9 P10 P9 M9 PL8A PL8B PL11A PL11B NC NC PL10C PL10D NC NC PL11C PL11D VCCIO3 GNDIO3 GNDIO2 VCCIO2 TMS NC NC NC TCK NC PB2A PB2B PB2C PB2D PB3A PB3B PB3C TDO PB3D PB4A GNDIO2 VCCIO2 PB4B TDI PB4C PB4D NC NC VCCAUX PB4E PB4F PB5C PB5D PB5A PB5B PB7B PB7A PB6B 2 2 2 2 2 2 2 PCLK2_0*** PCLK2_1*** T C T C C T C 2 2 T C 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 TDI T C C TDO C T T C T C T C T 2 TCK 3 3 3 3 2 2 2 TMS T C 3 3 T C 3 3 3 3 - LCMXO1200 Ball Ball Differential Number Function Bank T C T C J4 J5 R1 R2 K5 K4 L5 L4 M5 M4 N4 N3 VCCIO6 GND GND VCCIO5 P4 P2 P3 N5 R3 N6 T2 T3 R4 R5 P5 P6 T5 M6 T4 R6 GND VCCIO5 T6 N7 T8 T7 M7 M8 T9 R7 R8 VCCIO5 GND P7 P8 N8 N9 P10 P9 M9 PL13A PL13B PL13C PL13D PL14A PL14B PL14C PL14D PL15A PL15B PL16A PL16B VCCIO6 GNDIO6 GNDIO5 VCCIO5 TMS PB2A PB2B PB2C TCK PB2D PB3A PB3B PB3C PB3D PB4A PB4B PB4C TDO PB4D PB5A GNDIO5 VCCIO5 PB5B TDI PB5C PB5D PB6A PB6B VCCAUX PB6C PB6D VCCIO5 GNDIO5 PB6E PB6F PB7A PB7B PB7D PB7C PB7F 6 6 6 6 6 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 PCLK4_0*** PCLK4_1*** T C T C C T C T C TDI T C T C C TDO C T TCK C T C T C T C T TMS T C T LLM0_PLLT_IN_A LLM0_PLLC_IN_A LLM0_PLLT_FB_A LLM0_PLLC_FB_A T* C* T C T* C* T C LCMXO2280 Ball Ball Differential Number Function Bank T* C* T C J4 J5 R1 R2 GND K5 K4 L5 L4 M5 M4 N4 N3 VCCIO6 GND GND VCCIO5 P4 P2 P3 N5 R3 N6 T2 T3 R4 R5 P5 P6 T5 M6 T4 R6 GND VCCIO5 T6 N7 T8 T7 M7 M8 T9 R7 R8 VCCIO5 GND P7 P8 N8 N9 P10 P9 M9 PL16A PL16B PL16C PL16D GND PL17A PL17B PL17C PL17D PL18A PL18B PL19A PL19B VCCIO6 GNDIO6 GNDIO5 VCCIO5 TMS PB2A PB2B PB2C TCK PB2D PB3A PB3B PB3C PB3D PB4A PB4B PB4C TDO PB4D PB5A GNDIO5 VCCIO5 PB5B TDI PB6A PB6B PB7C PB7D VCCAUX PB8C PB8D VCCIO5 GNDIO5 PB9A PB9B PB10E PB10F PB10D PB10C PB10B 6 6 6 6 6 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 PCLK4_0*** PCLK4_1*** T C T C C T C T C TDI T C T C C TDO C T TCK C T C T C T C T TMS T C T LLM0_PLLT_IN_A LLM0_PLLC_IN_A LLM0_PLLT_FB_A LLM0_PLLC_FB_A T* C* T C T* C* T C Dual Function Dual Function Dual Function Differential T* C* T C 4-21 Lattice Semiconductor Pinout Information MachXO Family Data Sheet LCMXO640, LCMXO1200 and LCMXO2280 Logic Signal Connections: 256 ftBGA (Cont.) LCMXO640 Ball Ball Number Function Bank M10 R9 R10 T10 T11 N10 N11 VCCIO2 GND R11 R12 P11 P12 T13 T12 R13 R14 GND T14 T15 P13** P14 R15 R16 P15 P16 VCCIO2 GND GND VCCIO1 M11 L11 N12 N13 M13 M12 N14 N15 L13 L12 M14 VCCIO1 GND L14 N16 M16 M15 L15 L16 K16 K13 PB6A PB6C PB6D PB7C PB7D NC NC VCCIO2 GNDIO2 PB7E PB7F PB8A PB8B PB8C PB8D PB9A PB9B GND PB9C PB9D SLEEPN PB9F NC NC NC NC VCCIO2 GNDIO2 GNDIO1 VCCIO1 NC NC NC NC NC NC PR11D PR11C PR11B PR11A PR10B VCCIO1 GNDIO1 PR10A PR10D PR10C PR9D PR9C PR9B PR9A PR8D 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 T C T C T C T C C T C T C 2 2 1 1 2 2 2 2 2 2 2 2 2 2 2 2 SLEEPN T C T C T C T C T C 2 2 2 2 2 T T C T C LCMXO1200 Ball Ball Differential Number Function Bank VCCIO4 GND M10 R9 R10 T10 T11 N10 N11 VCCIO4 GND R11 R12 P11 P12 T13 T12 R13 R14 GND T14 T15 P13** P14 R15 R16 P15 P16 VCCIO4 GND GND VCCIO3 M11 L11 N12 N13 M13 M12 N14 N15 L13 L12 M14 VCCIO3 GND L14 N16 M16 M15 L15 L16 K16 K13 VCCIO4 GNDIO4 PB7E PB8A PB8B PB8C PB8D PB8E PB8F VCCIO4 GNDIO4 PB9A PB9B PB9C PB9D PB9E PB9F PB10A PB10B GND PB10C PB10D SLEEPN PB10F PB11A PB11B PB11C PB11D VCCIO4 GNDIO4 GNDIO3 VCCIO3 PR16B PR16A PR15B PR15A PR14D PR14C PR14B PR14A PR13D PR13C PR13B VCCIO3 GNDIO3 PR13A PR12D PR12C PR12B PR12A PR11D PR11C PR11B 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 T* C T C* T* C T C* C T C* T* C T C* T* C T C* T C T C SLEEPN T C T C T C T C T C T T C T C T C LCMXO2280 Ball Ball Differential Number Function Bank VCCIO4 GND M10 R9 R10 T10 T11 N10 N11 VCCIO4 GND R11 R12 P11 P12 T13 T12 R13 R14 GND T14 T15 P13** P14 R15 R16 P15 P16 VCCIO4 GND GND VCCIO3 M11 L11 N12 N13 M13 M12 N14 N15 L13 L12 M14 VCCIO3 GND L14 N16 M16 M15 L15 L16 K16 K13 VCCIO4 GNDIO4 PB10A PB11C PB11D PB12A PB12B PB12C PB12D VCCIO4 GNDIO4 PB13A PB13B PB13C PB13D PB14A PB14B PB14C PB14D GND PB15A PB15B SLEEPN PB15D PB16A PB16B PB16C PB16D VCCIO4 GNDIO4 GNDIO3 VCCIO3 PR20B PR20A PR18B PR18A PR17D PR17C PR17B PR17A PR16D PR16C PR16B VCCIO3 GNDIO3 PR16A PR15D PR15C PR15B PR15A PR14D PR14C PR14B 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 T* C T C* T* C T C* C T C* T* C T C* T* C T C* T C T C SLEEPN T C T C T C T C T C T T C T C T C Dual Function Dual Function Dual Function Differential 4-22 Lattice Semiconductor Pinout Information MachXO Family Data Sheet LCMXO640, LCMXO1200 and LCMXO2280 Logic Signal Connections: 256 ftBGA (Cont.) LCMXO640 Ball Ball Number Function Bank J13 GND K14 J14 K15 J15 K12 J12 J16 H16 H15 G15 H14 G14 GND VCCIO1 H13 H12 G13 G12 G16 F16 F15 E15 E16 D16 VCCIO1 GND D15 C15 C16 B16 F14 E14 F12 F13 E12 E13 D13 D14 VCCIO0 GND GND VCCIO0 B15 A15 C14 B14 C13 B13 PR8C GND PR8B PR8A PR7D PR7C NC NC PR7B PR7A PR6B PR6A PR5D PR5C GNDIO1 VCCIO1 PR6D PR6C PR4D PR4C PR5B PR5A PR4B PR4A PR3B PR3A VCCIO1 GNDIO1 PR2D PR2C PR2B PR2A PR3D PR3C NC NC NC NC NC NC VCCIO0 GNDIO0 GNDIO0 VCCIO0 NC NC NC NC PT9F PT9E 0 0 C T 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C T C T C T C T C T C T C T C T C T C T C T 1 1 1 1 1 C T C T LCMXO1200 Ball Ball Differential Number Function Bank T J13 GND K14 J14 K15 J15 GND VCCIO3 K12 J12 J16 H16 H15 G15 H14 G14 GND VCCIO2 H13 H12 G13 G12 G16 F16 F15 E15 E16 D16 VCCIO2 GND D15 C15 C16 B16 F14 E14 F12 F13 E12 E13 D13 D14 VCCIO2 GND GND VCCIO1 B15 A15 C14 B14 C13 B13 PR11A GND PR10D PR10C PR10B PR10A GNDIO3 VCCIO3 PR9D PR9C PR9B PR9A PR8D PR8C PR8B PR8A GNDIO2 VCCIO2 PR7D PR7C PR7B PR7A PR6D PR6C PR6B PR6A PR5D PR5C VCCIO2 GNDIO2 PR5B PR5A PR4D PR4C PR4B PR4A PR3D PR3C PR3B PR3A PR2B PR2A VCCIO2 GNDIO2 GNDIO1 VCCIO1 PT11D PT11C PT11B PT11A PT10F PT10E 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 C T C T C T C T C* T* C T C* T* C T C* T* C T C* T* C T C* T* C T C T C* T* C T C* T* C T C* T* LCMXO2280 Ball Ball Differential Number Function Bank T* J13 GND K14 J14 K15 J15 GND VCCIO3 K12 J12 J16 H16 H15 G15 H14 G14 GND VCCIO2 H13 H12 G13 G12 G16 F16 F15 E15 E16 D16 VCCIO2 GND D15 C15 C16 B16 F14 E14 GND F12 F13 E12 E13 D13 D14 VCCIO2 GND GND VCCIO1 B15 A15 C14 B14 C13 B13 PR14A GND PR13D PR13C PR13B PR13A GNDIO3 VCCIO3 PR11D PR11C PR11B PR11A PR10D PR10C PR10B PR10A GNDIO2 VCCIO2 PR9D PR9C PR9B PR9A PR7D PR7C PR7B PR7A PR6D PR6C VCCIO2 GNDIO2 PR6B PR6A PR5D PR5C PR5B PR5A GND PR4D PR4C PR4B PR4A PR3B PR3A VCCIO2 GNDIO2 GNDIO1 VCCIO1 PT16D PT16C PT16B PT16A PT15D PT15C 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 C T C T C T C T C* T* C* T* C* T* C T C* T* C T C* T* C T C* T* C T C T C* T* C T C* T* C T C* T* Dual Function Dual Function Dual Function Differential T* 4-23 Lattice Semiconductor Pinout Information MachXO Family Data Sheet LCMXO640, LCMXO1200 and LCMXO2280 Logic Signal Connections: 256 ftBGA (Cont.) LCMXO640 Ball Ball Number Function Bank E11 E10 D12 D11 A14 A13 C12 C11 B12 B11 A12 A11 GND B10 B9 D10 D9 C10 C9 A9 A10 E9 E8 D7 D8 VCCIO0 GND C8 B8 A8 A7 A6 VCC B7 B6 C6 C7 A5 A4 E7 E6 B5 B4 D5 D6 C4 C5 D4 NC NC PT9D PT9C PT7F PT7E PT8B PT8A PT7B PT7A PT7D PT7C GND PT5D PT5C PT8D PT8C PT6D PT6C PT6B PT6A PT9B PT9A PT5B PT5A VCCIO0 GNDIO0 PT4F PT4E VCCAUX PT4D PT4C VCC PT4B PT4A PT3C PT3D PT3E PT3F NC NC PT3B PT3A PT2D PT2C PT2E PT2F NC 0 0 0 0 0 0 C T C T T C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C T T C T C C T C T PCLK0_0*** PCLK0_1*** C T C T C T C T 0 0 0 0 0 0 0 0 C T C T C T C T 0 0 0 0 0 0 C T C T C T LCMXO1200 Ball Ball Differential Number Function Bank E11 E10 D12 D11 A14 A13 C12 C11 VCCIO1 GND B12 B11 A12 A11 GND B10 B9 D10 D9 VCCIO1 GND C10 C9 A9 A10 E9 E8 D7 D8 VCCIO0 GND C8 B8 A8 A7 A6 VCC B7 B6 C6 C7 A5 A4 E7 E6 B5 B4 D5 D6 C4 C5 D4 PT10D PT10C PT10B PT10A PT9F PT9E PT9D PT9C VCCIO1 GNDIO1 PT9B PT9A PT8F PT8E GND PT8D PT8C PT8B PT8A VCCIO1 GNDIO1 PT7F PT7E PT7D PT7C PT7B PT7A PT6F PT6E VCCIO0 GNDIO0 PT6D PT6C VCCAUX PT6B PT6A VCC PT5F PT5E PT5C PT5D PT5A PT5B PT4C PT4D PT3F PT3E PT3D PT3C PT4A PT4B PT2D 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C C T T C T C T C C T C T T C C T C T PCLK1_0*** PCLK1_1*** C T C T C T C T C T C T C T C T LCMXO2280 Ball Ball Differential Number Function Bank C T C T C T C T E11 E10 D12 D11 A14 A13 C12 C11 VCCIO1 GND B12 B11 A12 A11 GND B10 B9 D10 D9 VCCIO1 GND C10 C9 A9 A10 E9 E8 D7 D8 VCCIO0 GND C8 B8 A8 A7 A6 VCC B7 B6 C6 C7 A5 A4 E7 E6 B5 B4 D5 D6 C4 C5 GND D4 PT15B PT15A PT14D PT14C PT14B PT14A PT13D PT13C VCCIO1 GNDIO1 PT12D PT12C PT12B PT12A GND PT11B PT11A PT10F PT10E VCCIO1 GNDIO1 PT10D PT10C PT10B PT10A PT9D PT9C PT9B PT9A VCCIO0 GNDIO0 PT8D PT8C VCCAUX PT7D PT7C VCC PT7B PT7A PT6A PT6B PT6C PT6D PT6E PT6F PT5D PT5C PT5B PT5A PT4A PT4B GND PT3D 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C C T T C T C T C C T C T T C C T C T PCLK1_0*** PCLK1_1*** C T C T C T C T C T C T C T C T Dual Function Dual Function Dual Function Differential C T C T C T C T 4-24 Lattice Semiconductor Pinout Information MachXO Family Data Sheet LCMXO640, LCMXO1200 and LCMXO2280 Logic Signal Connections: 256 ftBGA (Cont.) LCMXO640 Ball Ball Number Function Bank D3 A3 A2 B3 B2 VCCIO0 GND A1 A16 F11 G8 G9 H7 H8 H9 H10 J7 J8 J9 J10 K8 K9 L6 T1 T16 G7 G10 K7 K10 H6 G6 K6 J6 L8 L7 L9 L10 K11 J11 H11 G11 F9 F10 F8 F7 NC PT2B PT2A NC NC VCCIO0 GNDIO0 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC VCC VCC VCC VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO0 VCCIO0 VCCIO0 VCCIO0 0 0 3 3 3 3 2 2 2 2 1 1 1 1 0 0 0 0 0 0 C T LCMXO1200 Ball Ball Differential Number Function Bank D3 A3 A2 B3 B2 VCCIO0 GND A1 A16 F11 G8 G9 H7 H8 H9 H10 J7 J8 J9 J10 K8 K9 L6 T1 T16 G7 G10 K7 K10 H6 G6 K6 J6 L8 L7 L9 L10 K11 J11 H11 G11 F9 F10 F8 F7 PT2C PT3B PT3A PT2B PT2A VCCIO0 GNDIO0 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC VCC VCC VCC VCCIO7 VCCIO7 VCCIO6 VCCIO6 VCCIO5 VCCIO5 VCCIO4 VCCIO4 VCCIO3 VCCIO3 VCCIO2 VCCIO2 VCCIO1 VCCIO1 VCCIO0 VCCIO0 0 0 0 0 0 0 0 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 LCMXO2280 Ball Ball Differential Number Function Bank T C T C T D3 A3 A2 B3 B2 VCCIO0 GND A1 A16 F11 G8 G9 H7 H8 H9 H10 J7 J8 J9 J10 K8 K9 L6 T1 T16 G7 G10 K7 K10 H6 G6 K6 J6 L8 L7 L9 L10 K11 J11 H11 G11 F9 F10 F8 F7 PT3C PT3B PT3A PT2D PT2C VCCIO0 GNDIO0 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC VCC VCC VCC VCCIO7 VCCIO7 VCCIO6 VCCIO6 VCCIO5 VCCIO5 VCCIO4 VCCIO4 VCCIO3 VCCIO3 VCCIO2 VCCIO2 VCCIO1 VCCIO1 VCCIO0 VCCIO0 0 0 0 0 0 0 0 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 Dual Function Dual Function Dual Function Differential T C T C T * Supports true LVDS outputs. ** NC for “E” devices. *** Primary clock inputs are single-ended. 4-25 Lattice Semiconductor Pinout Information MachXO Family Data Sheet LCMXO2280 Logic Signal Connections: 324 ftBGA LCMXO2280 Ball Number GND VCCIO7 D4 F5 B3 C3 E4 G6 A1 B1 F4 VCC E3 D2 D3 G5 F3 C2 VCCIO7 GND C1 H5 G4 E2 D1 J6 H4 F2 E1 GND J3 J5 G3 H3 K3 K5 F1 VCCIO7 GND G1 K4 K6 Ball Function GNDIO7 VCCIO7 PL2A PL2B PL3A PL3B PL3C PL3D PL4A PL4B PL4C VCC PL4D PL5A PL5B PL5C PL5D PL6A VCCIO7 GNDIO7 PL6B PL6C PL6D PL7A PL7B PL7C PL7D PL8A PL8B GND PL8C PL8D PL9A PL9B PL9C PL9D PL10A VCCIO7 GNDIO7 PL10B PL10C PL10D Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 C* T C T C T* C* T C T* GSRN C* T C T* C* T C T* C* C T* C* T C T* LUM0_PLLT_IN_A LUM0_PLLC_IN_A LUM0_PLLT_FB_A LUM0_PLLC_FB_A T C T* C* T C T* C* T Dual Function Differential 4-26 Lattice Semiconductor Pinout Information MachXO Family Data Sheet LCMXO2280 Logic Signal Connections: 324 ftBGA (Cont.) LCMXO2280 Ball Number G2 H2 L3 L5 H1 VCCIO6 GND J2 L4 L6 K2 K1 J1 VCC L2 M5 M3 L1 M2 M1 N1 M6 M4 VCCIO6 GND P1 P2 N3 N4 GND T1 R1 P3 N5 R3 R2 P4 N6 U1 VCCIO6 GND GND VCCIO5 Ball Function PL11A PL11B PL11C PL11D PL12A VCCIO6 GNDIO6 PL12B PL12C PL12D PL13A PL13B PL13C VCC PL13D PL14D PL14C PL14B PL14A PL15A PL15B PL15C PL15D VCCIO6 GNDIO6 PL16A PL16B PL16C PL16D GND PL17A PL17B PL17C PL17D PL18A PL18B PL19A PL19B PL20A VCCIO6 GNDIO6 GNDIO5 VCCIO5 Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 5 5 LLM0_PLLT_IN_A LLM0_PLLC_IN_A LLM0_PLLT_FB_A LLM0_PLLC_FB_A T* C* T C T* C* T C T T* C* T C TSALL C C T C* T* T* C* T C C* T C T* C* T Dual Function Differential T* C* T C T* 4-27 Lattice Semiconductor Pinout Information MachXO Family Data Sheet LCMXO2280 Logic Signal Connections: 324 ftBGA (Cont.) LCMXO2280 Ball Number T2 P6 V1 U2 T3 N7 R4 R5 T4 VCC R6 P7 U3 T5 V2 N8 V3 T6 GND VCCIO5 U4 P8 T7 V4 R8 N9 U5 V5 U6 VCC V6 P9 T8 U7 V7 M10 U8 V8 VCCIO5 GND T9 U9 V9 Ball Function PL20B TMS PB2A PB2B PB2C TCK PB2D PB3A PB3B VCC PB3C PB3D PB4A PB4B PB4C TDO PB4D PB5A GNDIO5 VCCIO5 PB5B PB5C PB5D TDI PB6A PB6B PB6C PB6D PB7A VCC PB7B PB7C PB7D PB8A PB8B VCCAUX PB8C PB8D VCCIO5 GNDIO5 PB8E PB8F PB9A Bank 6 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 4 T C T T C C T C T C TDI T C T C T C T C TDO C T T C T C T TCK C T C TMS T C T Dual Function Differential C 4-28 Lattice Semiconductor Pinout Information MachXO Family Data Sheet LCMXO2280 Logic Signal Connections: 324 ftBGA (Cont.) LCMXO2280 Ball Number V10 N10 R10 P10 T10 U10 V11 U11 VCCIO4 GND T11 U12 R11 GND T12 P11 V12 V13 R12 N11 U13 VCCIO4 GND V14 T13 P12 R13 N12 V15 U14 V16 GND T14 U15 V17 P13** T15 U16 V18 N13 R14 VCCIO4 GND Ball Function PB9B PB9C PB9D PB10F PB10E PB10D PB10C PB10B VCCIO4 GNDIO4 PB10A PB11A PB11B GND PB11C PB11D PB12A PB12B PB12C PB12D PB12E VCCIO4 GNDIO4 PB12F PB13A PB13B PB13C PB13D PB14A PB14B PB14C GND PB14D PB15A PB15B SLEEPN PB15D PB16A PB16B PB16C PB16D VCCIO4 GNDIO4 Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 T C T C SLEEPN C T C C T C T C T C T T C T C T C T T T C PCLK4_0*** PCLK4_1*** Dual Function Differential C T C C T C T C 4-29 Lattice Semiconductor Pinout Information MachXO Family Data Sheet LCMXO2280 Logic Signal Connections: 324 ftBGA (Cont.) LCMXO2280 Ball Number GND VCCIO3 P15 N14 N15 M13 R15 T16 N16 M14 U17 VCC U18 R17 R16 P16 VCCIO3 GND P17 L13 M15 T17 T18 L14 L15 R18 P18 GND K15 K13 N17 N18 K16 K14 M16 L16 GND VCCIO3 J16 J14 M17 L17 J15 Ball Function GNDIO3 VCCIO3 PR20B PR20A PR19B PR19A PR18B PR18A PR17D PR17C PR17B VCC PR17A PR16D PR16C PR16B VCCIO3 GNDIO3 PR16A PR15D PR15C PR15B PR15A PR14D PR14C PR14B PR14A GND PR13D PR13C PR13B PR13A PR12D PR12C PR12B PR12A GNDIO3 VCCIO3 PR11D PR11C PR11B PR11A PR10D Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 C T C* T* C C T C* T* C T C* T* T* C T C* T* C T C* T* T* C T C* C T C T C* T* C T C* Dual Function Differential 4-30 Lattice Semiconductor Pinout Information MachXO Family Data Sheet LCMXO2280 Logic Signal Connections: 324 ftBGA (Cont.) LCMXO2280 Ball Number J13 M18 L18 GND VCCIO2 H16 H14 K18 J18 J17 VCC H18 H17 G17 H13 H15 G18 F18 G14 G16 VCCIO2 GND E18 F17 G13 G15 E17 E16 GND F15 E15 D17 D18 B18 C18 C16 D16 C17 D15 VCCIO2 GND GND VCCIO1 Ball Function PR10C PR10B PR10A GNDIO2 VCCIO2 PR9D PR9C PR9B PR9A PR8D VCC PR8C PR8B PR8A PR7D PR7C PR7B PR7A PR6D PR6C VCCIO2 GNDIO2 PR6B PR6A PR5D PR5C PR5B PR5A GND PR4D PR4C PR4B PR4A PR3D PR3C PR3B PR3A PR2B PR2A VCCIO2 GNDIO2 GNDIO1 VCCIO1 Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 C T C* T* C T C* T* C T C* T* C T C* T* T C* T* C T C* T* C T C T C* T* C Dual Function Differential T C* T* 4-31 Lattice Semiconductor Pinout Information MachXO Family Data Sheet LCMXO2280 Logic Signal Connections: 324 ftBGA (Cont.) LCMXO2280 Ball Number E13 C15 F13 D14 A18 B17 A16 A17 VCC D13 F12 C14 E12 C13 B16 B15 A15 VCCIO1 GND B14 A14 D12 F11 B13 A13 C12 GND B12 E11 D11 C11 A12 VCCIO1 GND F10 D10 B11 A11 E10 C10 D9 E9 B10 Ball Function PT16D PT16C PT16B PT16A PT15D PT15C PT15B PT15A VCC PT14D PT14C PT14B PT14A PT13D PT13C PT13B PT13A VCCIO1 GNDIO1 PT12F PT12E PT12D PT12C PT12B PT12A PT11D GND PT11C PT11B PT11A PT10F PT10E VCCIO1 GNDIO1 PT10D PT10C PT10B PT10A PT9D PT9C PT9B PT9A PT8F Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 PCLK1_0*** PCLK1_1*** C T C T C T C T C T C T C T C T C T C T C C T C T C T C T Dual Function Differential C T C T C T C T 4-32 Lattice Semiconductor Pinout Information MachXO Family Data Sheet LCMXO2280 Logic Signal Connections: 324 ftBGA (Cont.) LCMXO2280 Ball Number A10 VCCIO0 GND A9 C9 B9 F9 A8 B8 C8 VCC A7 B7 A6 B6 D8 F8 C7 E8 D7 VCCIO0 GND E7 A5 C6 B5 A4 D6 F7 B4 GND C5 F6 E5 E6 D5 A3 C4 A2 B2 VCCIO0 GND E14 Ball Function PT8E VCCIO0 GNDIO0 PT8D PT8C PT8B VCCAUX PT8A PT7D PT7C VCC PT7B PT7A PT6A PT6B PT6C PT6D PT6E PT6F PT5D VCCIO0 GNDIO0 PT5C PT5B PT5A PT4A PT4B PT4C PT4D PT4E GND PT4F PT3D PT3C PT3B PT3A PT2D PT2C PT2B PT2A VCCIO0 GNDIO0 GND Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C C T C T C T C T T C T T C T C T C T T C T C T C C T C T C T C Dual Function Differential T 4-33 Lattice Semiconductor Pinout Information MachXO Family Data Sheet LCMXO2280 Logic Signal Connections: 324 ftBGA (Cont.) LCMXO2280 Ball Number F16 H10 H11 H8 H9 J10 J11 J4 J8 J9 K10 K11 K17 K8 K9 L10 L11 L8 L9 N2 P14 P5 R7 F14 G11 G9 H7 L7 M9 H6 J7 M7 K7 M8 R9 M12 M11 L12 K12 J12 H12 G12 G10 Ball Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC VCC VCC VCC VCC VCC VCCIO7 VCCIO7 VCCIO6 VCCIO6 VCCIO5 VCCIO5 VCCIO4 VCCIO4 VCCIO3 VCCIO3 VCCIO2 VCCIO2 VCCIO1 VCCIO1 Bank 7 7 6 6 5 5 4 4 3 3 2 2 1 1 Dual Function Differential 4-34 Lattice Semiconductor Pinout Information MachXO Family Data Sheet LCMXO2280 Logic Signal Connections: 324 ftBGA (Cont.) LCMXO2280 Ball Number G8 G7 Ball Function VCCIO0 VCCIO0 Bank 0 0 Dual Function Differential * Supports true LVDS outputs. ** NC for “E” devices. *** Primary clock inputs are single-ended. 4-35 Lattice Semiconductor Pinout Information MachXO Family Data Sheet Thermal Management Thermal management is recommended as part of any sound FPGA design methodology. To assess the thermal characteristics of a system, Lattice specifies a maximum allowable junction temperature in all device data sheets. Designers must complete a thermal analysis of their specific design to ensure that the device and package do not exceed the junction temperature limits. Refer to the Thermal Management document to find the device/package specific thermal values. For Further Information For further information regarding Thermal Management, refer to the following located on the Lattice website at www.latticesemi.com. • Thermal Management document • Technical Note TN1090 - Power Estimation and Management for MachXO Devices • Power Calculator tool included with Lattice’s ispLEVER design tool, or as a standalone download from www.latticesemi.com/software 4-36 MachXO Family Data Sheet Ordering Information August 2006 Data Sheet DS1002 Part Number Description LCMXO XXXX X – X XXXXXX X XX Device Family MachXO Crossover PLD Logic Capacity 256 LUTs = 256 640 LUTs = 640 1200 LUTs = 1200 2280 LUTs = 2280 Supply Voltage C = 1.8V/2.5V/3.3V E = 1.2V Note: Parts dual marked as described. ES = Engineering Sample Blank = Production Device Grade C = Commercial I = Industrial Package T100 = 100-pin TQFP T144 = 144-pin TQFP M100 = 100-ball csBGA M132 = 132-ball csBGA FT256 = 256-ball ftBGA FT324 = 324-ball ftBGA TN100 = 100-pin Lead-Free TQFP TN144 = 144-pin Lead-Free TQFP MN100 = 100-ball Lead-Free csBGA MN132 = 132-ball Lead-Free csBGA FTN256 = 256-ball Lead-Free ftBGA FTN324 = 324-ball Lead-Free ftBGA Speed 3 = Slowest 4 5 = Fastest Ordering Information Note: MachXO devices are dual marked except the slowest commercial speed grade device. For example the commercial speed grade LCMXO640E-4F256C is also marked with industrial grade -3I grade. The slowest commercial speed grade does not have industrial markings. The markings appears as follows: LCMXO640E 4F256C-3I Datecode Dual Mark © 2006 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 5-1 DS1002 Ordering Information_01.5 Lattice Semiconductor Conventional Packaging Commercial Part Number LCMXO256C-3T100C LCMXO256C-4T100C LCMXO256C-5T100C LCMXO256C-3M100C LCMXO256C-4M100C LCMXO256C-5M100C LUTs 256 256 256 256 256 256 Supply Voltage 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V I/Os 78 78 78 78 78 78 Grade -3 -4 -5 -3 -4 -5 Ordering Information MachXO Family Data Sheet Package TQFP TQFP TQFP csBGA csBGA csBGA Pins 100 100 100 100 100 100 Temp. COM COM COM COM COM COM Part Number LCMXO640C-3T100C LCMXO640C-4T100C LCMXO640C-5T100C LCMXO640C-3M100C LCMXO640C-4M100C LCMXO640C-5M100C LCMXO640C-3T144C LCMXO640C-4T144C LCMXO640C-5T144C LCMXO640C-3M132C LCMXO640C-4M132C LCMXO640C-5M132C LCMXO640C-3FT256C LCMXO640C-4FT256C LCMXO640C-5FT256C Part Number LCMXO1200C-3T100C LCMXO1200C-4T100C LCMXO1200C-5T100C LCMXO1200C-3T144C LCMXO1200C-4T144C LCMXO1200C-5T144C LCMXO1200C-3M132C LCMXO1200C-4M132C LCMXO1200C-5M132C LCMXO1200C-3FT256C LCMXO1200C-4FT256C LCMXO1200C-5FT256C LUTs 640 640 640 640 640 640 640 640 640 640 640 640 640 640 640 LUTs 1200 1200 1200 1200 1200 1200 1200 1200 1200 1200 1200 1200 Supply Voltage 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V Supply Voltage 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V I/Os 74 74 74 74 74 74 113 113 113 101 101 101 159 159 159 I/Os 73 73 73 113 113 113 101 101 101 211 211 211 Grade -3 -4 -5 -3 -4 -5 -3 -4 -5 -3 -4 -5 -3 -4 -5 Grade -3 -4 -5 -3 -4 -5 -3 -4 -5 -3 -4 -5 Package TQFP TQFP TQFP csBGA csBGA csBGA TQFP TQFP TQFP csBGA csBGA csBGA ftBGA ftBGA ftBGA Package TQFP TQFP TQFP TQFP TQFP TQFP csBGA csBGA csBGA ftBGA ftBGA ftBGA Pins 100 100 100 100 100 100 144 144 144 132 132 132 256 256 256 Pins 100 100 100 144 144 144 132 132 132 256 256 256 Temp. COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM Temp. COM COM COM COM COM COM COM COM COM COM COM COM 5-2 Lattice Semiconductor Part Number LCMXO2280C-3T100C LCMXO2280C-4T100C LCMXO2280C-5T100C LCMXO2280C-3T144C LCMXO2280C-4T144C LCMXO2280C-5T144C LCMXO2280C-3M132C LCMXO2280C-4M132C LCMXO2280C-5M132C LCMXO2280C-3FT256C LCMXO2280C-4FT256C LCMXO2280C-5FT256C LCMXO2280C-3FT324C LCMXO2280C-4FT324C LCMXO2280C-5FT324C Part Number LCMXO256E-3T100C LCMXO256E-4T100C LCMXO256E-5T100C LCMXO256E-3M100C LCMXO256E-4M100C LCMXO256E-5M100C Part Number LCMXO640E-3T100C LCMXO640E-4T100C LCMXO640E-5T100C LCMXO640E-3M100C LCMXO640E-4M100C LCMXO640E-5M100C LCMXO640E-3T144C LCMXO640E-4T144C LCMXO640E-5T144C LCMXO640E-3M132C LCMXO640E-4M132C LCMXO640E-5M132C LCMXO640E-3FT256C LCMXO640E-4FT256C LCMXO640E-5FT256C LUTs 2280 2280 2280 2280 2280 2280 2280 2280 2280 2280 2280 2280 2280 2280 2280 LUTs 256 256 256 256 256 256 LUTs 640 640 640 640 640 640 640 640 640 640 640 640 640 640 640 Supply Voltage 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V Supply Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Supply Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V I/Os 73 73 73 113 113 113 101 101 101 211 211 211 271 271 271 I/Os 78 78 78 78 78 78 I/Os 74 74 74 74 74 74 113 113 113 101 101 101 159 159 159 Grade -3 -4 -5 -3 -4 -5 -3 -4 -5 -3 -4 -5 -3 -4 -5 Grade -3 -4 -5 -3 -4 -5 Grade -3 -4 -5 -3 -4 -5 -3 -4 -5 -3 -4 -5 -3 -4 -5 Ordering Information MachXO Family Data Sheet Package TQFP TQFP TQFP TQFP TQFP TQFP csBGA csBGA csBGA ftBGA ftBGA ftBGA ftBGA ftBGA ftBGA Package TQFP TQFP TQFP csBGA csBGA csBGA Package TQFP TQFP TQFP csBGA csBGA csBGA TQFP TQFP TQFP csBGA csBGA csBGA ftBGA ftBGA ftBGA Pins 100 100 100 144 144 144 132 132 132 256 256 256 324 324 324 Pins 100 100 100 100 100 100 Pins 100 100 100 100 100 100 144 144 144 132 132 132 256 256 256 Temp. COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM Temp. COM COM COM COM COM COM Temp. COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM 5-3 Lattice Semiconductor Part Number LCMXO1200E-3T100C LCMXO1200E-4T100C LCMXO1200E-5T100C LCMXO1200E-3T144C LCMXO1200E-4T144C LCMXO1200E-5T144C LCMXO1200E-3M132C LCMXO1200E-4M132C LCMXO1200E-5M132C LCMXO1200E-3FT256C LCMXO1200E-4FT256C LCMXO1200E-5FT256C Part Number LCMXO2280E-3T100C LCMXO2280E-4T100C LCMXO2280E-5T100C LCMXO2280E-3T144C LCMXO2280E-4T144C LCMXO2280E-5T144C LCMXO2280E-3M132C LCMXO2280E-4M132C LCMXO2280E-5M132C LCMXO2280E-3FT256C LCMXO2280E-4FT256C LCMXO2280E-5FT256C LCMXO2280E-3FT324C LCMXO2280E-4FT324C LCMXO2280E-5FT324C LUTs 1200 1200 1200 1200 1200 1200 1200 1200 1200 1200 1200 1200 LUTs 2280 2280 2280 2280 2280 2280 2280 2280 2280 2280 2280 2280 2280 2280 2280 Supply Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Supply Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V I/Os 73 73 73 113 113 113 101 101 101 211 211 211 I/Os 73 73 73 113 113 113 101 101 101 211 211 211 271 271 271 Grade -3 -4 -5 -3 -4 -5 -3 -4 -5 -3 -4 -5 Grade -3 -4 -5 -3 -4 -5 -3 -4 -5 -3 -4 -5 -3 -4 -5 Ordering Information MachXO Family Data Sheet Package TQFP TQFP TQFP TQFP TQFP TQFP csBGA csBGA csBGA ftBGA ftBGA ftBGA Package TQFP TQFP TQFP TQFP TQFP TQFP csBGA csBGA csBGA ftBGA ftBGA ftBGA ftBGA ftBGA ftBGA Pins 100 100 100 144 144 144 132 132 132 256 256 256 Pins 100 100 100 144 144 144 132 132 132 256 256 256 324 324 324 Temp. COM COM COM COM COM COM COM COM COM COM COM COM Temp. COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM 5-4 Lattice Semiconductor Conventional Packaging Industrial Part Number LCMXO256C-3T100I LCMXO256C-4T100I LCMXO256C-3M100I LCMXO256C-4M100I LUTs 256 256 256 256 Supply Voltage 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V I/Os 78 78 78 78 Grade -3 -4 -3 -4 Ordering Information MachXO Family Data Sheet Package TQFP TQFP csBGA csBGA Pins 100 100 100 100 Temp. IND IND IND IND Part Number LCMXO640C-3T100I LCMXO640C-4T100I LCMXO640C-3M100I LCMXO640C-4M100I LCMXO640C-3T144I LCMXO640C-4T144I LCMXO640C-3M132I LCMXO640C-4M132I LCMXO640C-3FT256I LCMXO640C-4FT256I Part Number LCMXO1200C-3T100I LCMXO1200C-4T100I LCMXO1200C-3T144I LCMXO1200C-4T144I LCMXO1200C-3M132I LCMXO1200C-4M132I LCMXO1200C-3FT256I LCMXO1200C-4FT256I Part Number LCMXO2280C-3T100I LCMXO2280C-4T100I LCMXO2280C-3T144I LCMXO2280C-4T144I LCMXO2280C-3M132I LCMXO2280C-4M132I LCMXO2280C-3FT256I LCMXO2280C-4FT256I LCMXO2280C-3FT324I LCMXO2280C-4FT324I LUTs 640 640 640 640 640 640 640 640 640 640 LUTs 1200 1200 1200 1200 1200 1200 1200 1200 LUTs 2280 2280 2280 2280 2280 2280 2280 2280 2280 2280 Supply Voltage 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V Supply Voltage 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V Supply Voltage 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V I/Os 74 74 74 74 113 113 101 101 159 159 I/Os 73 73 113 113 101 101 211 211 I/Os 73 73 113 113 101 101 211 211 271 271 Grade -3 -4 -3 -4 -3 -4 -3 -4 -3 -4 Grade -3 -4 -3 -4 -3 -4 -3 -4 Grade -3 -4 -3 -4 -3 -4 -3 -4 -3 -4 Package TQFP TQFP csBGA csBGA TQFP TQFP csBGA csBGA ftBGA ftBGA Package TQFP TQFP TQFP TQFP csBGA csBGA ftBGA ftBGA Package TQFP TQFP TQFP TQFP csBGA csBGA ftBGA ftBGA ftBGA ftBGA Pins 100 100 100 100 144 144 132 132 256 256 Pins 100 100 144 144 132 132 256 256 Pins 100 100 144 144 132 132 256 256 324 324 Temp. IND IND IND IND IND IND IND IND IND IND Temp. IND IND IND IND IND IND IND IND Temp. IND IND IND IND IND IND IND IND IND IND 5-5 Lattice Semiconductor Part Number LCMXO256E-3T100I LCMXO256E-4T100I LCMXO256E-3M100I LCMXO256E-4M100I Part Number LCMXO640E-3T100I LCMXO640E-4T100I LCMXO640E-3M100I LCMXO640E-4M100I LCMXO640E-3T144I LCMXO640E-4T144I LCMXO640E-3M132I LCMXO640E-4M132I LCMXO640E-3FT256I LCMXO640E-4FT256I Part Number LCMXO1200E-3T100I LCMXO1200E-4T100I LCMXO1200E-3T144I LCMXO1200E-4T144I LCMXO1200E-3M132I LCMXO1200E-4M132I LCMXO1200E-3FT256I LCMXO1200E-4FT256I Part Number LCMXO2280E-3T100I LCMXO2280E-4T100I LCMXO2280E-3T144I LCMXO2280E-4T144I LCMXO2280E-3M132I LCMXO2280E-4M132I LCMXO2280E-3FT256I LCMXO2280E-4FT256I LCMXO2280E-3FT324I LCMXO2280E-4FT324I LUTs 256 256 256 256 LUTs 640 640 640 640 640 640 640 640 640 640 LUTs 1200 1200 1200 1200 1200 1200 1200 1200 LUTs 2280 2280 2280 2280 2280 2280 2280 2280 2280 2280 Supply Voltage 1.2V 1.2V 1.2V 1.2V Supply Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Supply Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Supply Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V I/Os 78 78 78 78 I/Os 74 74 74 74 113 113 101 101 159 159 I/Os 73 73 113 113 101 101 211 211 I/Os 73 73 113 113 101 101 211 211 271 271 Grade -3 -4 -3 -4 Grade -3 -4 -3 -4 -3 -4 -3 -4 -3 -4 Grade -3 -4 -3 -4 -3 -4 -3 -4 Grade -3 -4 -3 -4 -3 -4 -3 -4 -3 -4 Ordering Information MachXO Family Data Sheet Package TQFP TQFP csBGA csBGA Package TQFP TQFP csBGA csBGA TQFP TQFP csBGA csBGA ftBGA ftBGA Package TQFP TQFP TQFP TQFP csBGA csBGA ftBGA ftBGA Package TQFP TQFP TQFP TQFP csBGA csBGA ftBGA ftBGA ftBGA ftBGA Pins 100 100 100 100 Pins 100 100 100 100 144 144 132 132 256 256 Pins 100 100 144 144 132 132 256 256 Pins 100 100 144 144 132 132 256 256 324 324 Temp. IND IND IND IND Temp. IND IND IND IND IND IND IND IND IND IND Temp. IND IND IND IND IND IND IND IND Temp. IND IND IND IND IND IND IND IND IND IND 5-6 Lattice Semiconductor Lead-Free Packaging Commercial Part Number LCMXO256C-3TN100C LCMXO256C-4TN100C LCMXO256C-5TN100C LCMXO256C-3MN100C LCMXO256C-4MN100C LCMXO256C-5MN100C LUTs 256 256 256 256 256 256 Supply Voltage 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V I/Os 78 78 78 78 78 78 Grade -3 -4 -5 -3 -4 -5 Ordering Information MachXO Family Data Sheet Package Lead-Free TQFP Lead-Free TQFP Lead-Free TQFP Lead-Free csBGA Lead-Free csBGA Lead-Free csBGA Pins 100 100 100 100 100 100 Temp. COM COM COM COM COM COM Part Number LCMXO640C-3TN100C LCMXO640C-4TN100C LCMXO640C-5TN100C LCMXO640C-3MN100C LCMXO640C-4MN100C LCMXO640C-5MN100C LCMXO640C-3TN144C LCMXO640C-4TN144C LCMXO640C-5TN144C LCMXO640C-3MN132C LCMXO640C-4MN132C LCMXO640C-5MN132C LCMXO640C-3FTN256C LCMXO640C-4FTN256C LCMXO640C-5FTN256C Part Number LCMXO1200C-3TN100C LCMXO1200C-4TN100C LCMXO1200C-5TN100C LCMXO1200C-3TN144C LCMXO1200C-4TN144C LCMXO1200C-5TN144C LCMXO1200C-3MN132C LCMXO1200C-4MN132C LCMXO1200C-5MN132C LCMXO1200C-3FTN256C LCMXO1200C-4FTN256C LCMXO1200C-5FTN256C Part Number LCMXO2280C-3TN100C LCMXO2280C-4TN100C LCMXO2280C-5TN100C LUTs 640 640 640 640 640 640 640 640 640 640 640 640 640 640 640 LUTs 1200 1200 1200 1200 1200 1200 1200 1200 1200 1200 1200 1200 LUTs 2280 2280 2280 Supply Voltage 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V Supply Voltage 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V Supply Voltage 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V I/Os 74 74 74 74 74 74 113 113 113 101 101 101 159 159 159 I/Os 73 73 73 113 113 113 101 101 101 211 211 211 I/Os 73 73 73 Grade -3 -4 -5 -3 -4 -5 -3 -4 -5 -3 -4 -5 -3 -4 -5 Grade -3 -4 -5 -3 -4 -5 -3 -4 -5 -3 -4 -5 Grade -3 -4 -5 Package Lead-Free TQFP Lead-Free TQFP Lead-Free TQFP Lead-Free csBGA Lead-Free csBGA Lead-Free csBGA Lead-Free TQFP Lead-Free TQFP Lead-Free TQFP Lead-Free csBGA Lead-Free csBGA Lead-Free csBGA Lead-Free ftBGA Lead-Free ftBGA Lead-Free ftBGA Package Lead-Free TQFP Lead-Free TQFP Lead-Free TQFP Lead-Free TQFP Lead-Free TQFP Lead-Free TQFP Lead-Free csBGA Lead-Free csBGA Lead-Free csBGA Lead-Free ftBGA Lead-Free ftBGA Lead-Free ftBGA Package Lead-Free TQFP Lead-Free TQFP Lead-Free TQFP Pins 100 100 100 100 100 100 144 144 144 132 132 132 256 256 256 Pins 100 100 100 144 144 144 132 132 132 256 256 256 Pins 100 100 100 Temp. COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM Temp. COM COM COM COM COM COM COM COM COM COM COM COM Temp. COM COM COM 5-7 Lattice Semiconductor Part Number LCMXO2280C-3TN144C LCMXO2280C-4TN144C LCMXO2280C-5TN144C LCMXO2280C-3MN132C LCMXO2280C-4MN132C LCMXO2280C-5MN132C LCMXO2280C-3FTN256C LCMXO2280C-4FTN256C LCMXO2280C-5FTN256C LCMXO2280C-3FTN324C LCMXO2280C-4FTN324C LCMXO2280C-5FTN324C Part Number LCMXO256E-3TN100C LCMXO256E-4TN100C LCMXO256E-5TN100C LCMXO256E-3MN100C LCMXO256E-4MN100C LCMXO256E-5MN100C Part Number LCMXO640E-3TN100C LCMXO640E-4TN100C LCMXO640E-5TN100C LCMXO640E-3MN100C LCMXO640E-4MN100C LCMXO640E-5MN100C LCMXO640E-3TN144C LCMXO640E-4TN144C LCMXO640E-5TN144C LCMXO640E-3MN132C LCMXO640E-4MN132C LCMXO640E-5MN132C LCMXO640E-3FTN256C LCMXO640E-4FTN256C LCMXO640E-5FTN256C LUTs 2280 2280 2280 2280 2280 2280 2280 2280 2280 2280 2280 2280 LUTs 256 256 256 256 256 256 LUTs 640 640 640 640 640 640 640 640 640 640 640 640 640 640 640 Supply Voltage 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V Supply Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Supply Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V I/Os 113 113 113 101 101 101 211 211 211 271 271 271 I/Os 78 78 78 78 78 78 I/Os 74 74 74 74 74 74 113 113 113 101 101 101 159 159 159 Grade -3 -4 -5 -3 -4 -5 -3 -4 -5 -3 -4 -5 Grade -3 -4 -5 -3 -4 -5 Grade -3 -4 -5 -3 -4 -5 -3 -4 -5 -3 -4 -5 -3 -4 -5 Ordering Information MachXO Family Data Sheet Package Lead-Free TQFP Lead-Free TQFP Lead-Free TQFP Lead-Free csBGA Lead-Free csBGA Lead-Free csBGA Lead-Free ftBGA Lead-Free ftBGA Lead-Free ftBGA Lead-Free ftBGA Lead-Free ftBGA Lead-Free ftBGA Package Lead-Free TQFP Lead-Free TQFP Lead-Free TQFP Lead-Free csBGA Lead-Free csBGA Lead-Free csBGA Package Lead-Free TQFP Lead-Free TQFP Lead-Free TQFP Lead-Free csBGA Lead-Free csBGA Lead-Free csBGA Lead-Free TQFP Lead-Free TQFP Lead-Free TQFP Lead-Free csBGA Lead-Free csBGA Lead-Free csBGA Lead-Free ftBGA Lead-Free ftBGA Lead-Free ftBGA Pins 144 144 144 132 132 132 256 256 256 324 324 324 Pins 100 100 100 100 100 100 Pins 100 100 100 100 100 100 144 144 144 132 132 132 256 256 256 Temp. COM COM COM COM COM COM COM COM COM COM COM COM Temp. COM COM COM COM COM COM Temp. COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM 5-8 Lattice Semiconductor Part Number LCMXO1200E-3TN100C LCMXO1200E-4TN100C LCMXO1200E-5TN100C LCMXO1200E-3TN144C LCMXO1200E-4TN144C LCMXO1200E-5TN144C LCMXO1200E-3MN132C LCMXO1200E-4MN132C LCMXO1200E-5MN132C LCMXO1200E-3FTN256C LCMXO1200E-4FTN256C LCMXO1200E-5FTN256C Part Number LCMXO2280E-3TN100C LCMXO2280E-4TN100C LCMXO2280E-5TN100C LCMXO2280E-3TN144C LCMXO2280E-4TN144C LCMXO2280E-5TN144C LCMXO2280E-3MN132C LCMXO2280E-4MN132C LCMXO2280E-5MN132C LCMXO2280E-3FTN256C LCMXO2280E-4FTN256C LCMXO2280E-5FTN256C LCMXO2280E-3FTN324C LCMXO2280E-4FTN324C LCMXO2280E-5FTN324C LUTs 1200 1200 1200 1200 1200 1200 1200 1200 1200 1200 1200 1200 LUTs 2280 2280 2280 2280 2280 2280 2280 2280 2280 2280 2280 2280 2280 2280 2280 Supply Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Supply Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V I/Os 73 73 73 113 113 113 101 101 101 211 211 211 I/Os 73 73 73 113 113 113 101 101 101 211 211 211 271 271 271 Grade -3 -4 -5 -3 -4 -5 -3 -4 -5 -3 -4 -5 Grade -3 -4 -5 -3 -4 -5 -3 -4 -5 -3 -4 -5 -3 -4 -5 Ordering Information MachXO Family Data Sheet Package Lead-Free TQFP Lead-Free TQFP Lead-Free TQFP Lead-Free TQFP Lead-Free TQFP Lead-Free TQFP Lead-Free csBGA Lead-Free csBGA Lead-Free csBGA Lead-Free ftBGA Lead-Free ftBGA Lead-Free ftBGA Package Lead-Free TQFP Lead-Free TQFP Lead-Free TQFP Lead-Free TQFP Lead-Free TQFP Lead-Free TQFP Lead-Free csBGA Lead-Free csBGA Lead-Free csBGA Lead-Free ftBGA Lead-Free ftBGA Lead-Free ftBGA Lead-Free ftBGA Lead-Free ftBGA Lead-Free ftBGA Pins 100 100 100 144 144 144 132 132 132 256 256 256 Pins 100 100 100 144 144 144 132 132 132 256 256 256 324 324 324 Temp. COM COM COM COM COM COM COM COM COM COM COM COM Temp. COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM 5-9 Lattice Semiconductor Lead-Free Packaging Industrial Part Number LCMXO256C-3TN100I LCMXO256C-4TN100I LCMXO256C-3MN100I LCMXO256C-4MN100I LUTs 256 256 256 256 Supply Voltage 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V I/Os 78 78 78 78 Grade -3 -4 -3 -4 Ordering Information MachXO Family Data Sheet Package Lead-Free TQFP Lead-Free TQFP Lead-Free csBGA Lead-Free csBGA Pins 100 100 100 100 Temp. IND IND IND IND Part Number LCMXO640C-3TN100I LCMXO640C-4TN100I LCMXO640C-3MN100I LCMXO640C-4MN100I LCMXO640C-3TN144I LCMXO640C-4TN144I LCMXO640C-3MN132I LCMXO640C-4MN132I LCMXO640C-3FTN256I LCMXO640C-4FTN256I Part Number LCMXO1200C-3TN100I LCMXO1200C-4TN100I LCMXO1200C-3TN144I LCMXO1200C-4TN144I LCMXO1200C-3MN132I LCMXO1200C-4MN132I LCMXO1200C-3FTN256I LCMXO1200C-4FTN256I Part Number LCMXO2280C-3TN100I LCMXO2280C-4TN100I LCMXO2280C-3TN144I LCMXO2280C-4TN144I LCMXO2280C-3MN132I LCMXO2280C-4MN132I LCMXO2280C-3FTN256I LCMXO2280C-4FTN256I LCMXO2280C-3FTN324I LCMXO2280C-4FTN324I LUTs 640 640 640 640 640 640 640 640 640 640 LUTs 1200 1200 1200 1200 1200 1200 1200 1200 LUTs 2280 2280 2280 2280 2280 2280 2280 2280 2280 2280 Supply Voltage 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V Supply Voltage 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V Supply Voltage 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V I/Os 74 74 74 74 113 113 101 101 159 159 I/Os 73 73 113 113 101 101 211 211 I/Os 73 73 113 113 101 101 211 211 271 271 Grade -3 -4 -3 -4 -3 -4 -3 -4 -3 -4 Grade -3 -4 -3 -4 -3 -4 -3 -4 Grade -3 -4 -3 -4 -3 -4 -3 -4 -3 -4 Package Lead-Free TQFP Lead-Free TQFP Lead-Free csBGA Lead-Free csBGA Lead-Free TQFP Lead-Free TQFP Lead-Free csBGA Lead-Free csBGA Lead-Free ftBGA Lead-Free ftBGA Package Lead-Free TQFP Lead-Free TQFP Lead-Free TQFP Lead-Free TQFP Lead-Free csBGA Lead-Free csBGA Lead-Free ftBGA Lead-Free ftBGA Package Lead-Free TQFP Lead-Free TQFP Lead-Free TQFP Lead-Free TQFP Lead-Free csBGA Lead-Free csBGA Lead-Free ftBGA Lead-Free ftBGA Lead-Free ftBGA Lead-Free ftBGA Pins 100 100 100 100 144 144 132 132 256 256 Pins 100 100 144 144 132 132 256 256 Pins 100 100 144 144 132 132 256 256 324 324 Temp. IND IND IND IND IND IND IND IND IND IND Temp. IND IND IND IND IND IND IND IND Temp. IND IND IND IND IND IND IND IND IND IND 5-10 Lattice Semiconductor Part Number LCMXO256E-3TN100I LCMXO256E-4TN100I LCMXO256E-3MN100I LCMXO256E-4MN100I Part Number LCMXO640E-3TN100I LCMXO640E-4TN100I LCMXO640E-3MN100I LCMXO640E-4MN100I LCMXO640E-3TN144I LCMXO640E-4TN144I LCMXO640E-3MN132I LCMXO640E-4MN132I LCMXO640E-3FTN256I LCMXO640E-4FTN256I Part Number LCMXO1200E-3TN100I LCMXO1200E-4TN100I LCMXO1200E-3TN144I LCMXO1200E-4TN144I LCMXO1200E-3MN132I LCMXO1200E-4MN132I LCMXO1200E-3FTN256I LCMXO1200E-4FTN256I Part Number LCMXO2280E-3TN100I LCMXO2280E-4TN100I LCMXO2280E-3TN144I LCMXO2280E-4TN144I LCMXO2280E-3MN132I LCMXO2280E-4MN132I LCMXO2280E-3FTN256I LCMXO2280E-4FTN256I LCMXO2280E-3FTN324I LCMXO2280E-4FTN324I LUTs 256 256 256 256 LUTs 640 640 640 640 640 640 640 640 640 640 LUTs 1200 1200 1200 1200 1200 1200 1200 1200 LUTs 2280 2280 2280 2280 2280 2280 2280 2280 2280 2280 Supply Voltage 1.2V 1.2V 1.2V 1.2V Supply Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Supply Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Supply Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V I/Os 78 78 78 78 I/Os 74 74 74 74 113 113 101 101 159 159 I/Os 73 73 113 113 101 101 211 211 I/Os 73 73 113 113 101 101 211 211 271 271 Grade -3 -4 -3 -4 Grade -3 -4 -3 -4 -3 -4 -3 -4 -3 -4 Grade -3 -4 -3 -4 -3 -4 -3 -4 Grade -3 -4 -3 -4 -3 -4 -3 -4 -3 -4 Ordering Information MachXO Family Data Sheet Package Lead-Free TQFP Lead-Free TQFP Lead-Free csBGA Lead-Free csBGA Package Lead-Free TQFP Lead-Free TQFP Lead-Free csBGA Lead-Free csBGA Lead-Free TQFP Lead-Free TQFP Lead-Free csBGA Lead-Free csBGA Lead-Free ftBGA Lead-Free ftBGA Package Lead-Free TQFP Lead-Free TQFP Lead-Free TQFP Lead-Free TQFP Lead-Free csBGA Lead-Free csBGA Lead-Free ftBGA Lead-Free ftBGA Package Lead-Free TQFP Lead-Free TQFP Lead-Free TQFP Lead-Free TQFP Lead-Free csBGA Lead-Free csBGA Lead-Free ftBGA Lead-Free ftBGA Lead-Free ftBGA Lead-Free ftBGA Pins 100 100 100 100 Pins 100 100 100 100 144 144 132 132 256 256 Pins 100 100 144 144 132 132 256 256 Pins 100 100 144 144 132 132 256 256 324 324 Temp. IND IND IND IND Temp. IND IND IND IND IND IND IND IND IND IND Temp. IND IND IND IND IND IND IND IND Temp. IND IND IND IND IND IND IND IND IND IND 5-11 MachXO Family Data Sheet Supplemental Information November 2007 Data Sheet DS1002 For Further Information A variety of technical notes for the MachXO family are available on the Lattice web site at www.latticesemi.com. • • • • • • • • MachXO sysIO Usage Guide (TN1091) MachXO sysCLOCK PLL Design and Usage Guide (TN1089) MachXO Memory Usage Guide (TN1092) Power Estimation and Management for MachXO Devices (TN1090) MachXO JTAG Programming and Configuration User’s Guide (TN1086) Minimizing System Interruption During Configuration Using TransFR Technology (TN1087) MachXO Density Migration (TN1097) IEEE 1149.1 Boundary Scan Testability in Lattice Devices For further information on interface standards refer to the following web sites: • JEDEC Standards (LVTTL, LVCMOS): www.jedec.org • PCI: www.pcisig.com © 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 6-1 DS1002 Further Information_01.2 MachXO Family Data Sheet Revision History November 2007 Data Sheet DS1002 Revision History Date February 2005 October 2005 Version 01.0 01.1 Section — Introduction Architecture Initial release. Distributed RAM information in family table updated. Added footnote 1 fpBGA packaging to the family selection guide. sysIO Buffer section updated. Hot Socketing section updated. Sleep Mode section updated. SLEEP Pin Characteristics section updated. Oscillator section updated. Security section updated. DC and Switching Characteristics Recommended Operating Conditions table updated. DC Electrical Characteristics table updated. Supply Current (Sleep Mode) table added with LCMXO256/640 data. Supply Current (Standby) table updated with LCMXO256/640 data. Initialization Supply Current table updated with LCMXO256/640 data. Programming and Erase Flash Supply Current table updated with LCMXO256/640 data. Register-to-Register Performance table updated (rev. A 0.16). External Switching Characteristics table updated (rev. A 0.16). Internal Timing Parameter table updated (rev. A 0.16). Family Timing Adders updated (rev. A 0.16). sysCLOCK Timingupdated (rev. A 0.16). MachXO "C" Sleep Mode Timing updated (A 0.16). JTAG Port Timing Specification updated (rev. A 0.16). Pinout Information SLEEPIN description updated. Pin Information Summary updated. Power Supply and NC Connection table has been updated. Logic Signal Connection section has been updated to include all devices/packages. Ordering Information Part Number Description section has been updated. Ordering Part Number section has been updated (added LCMXO256C/ LCMXO640C "4W"). Supplemental Information November 2005 December 2005 01.2 01.3 Pinout Information DC and Switching Characteristics Ordering Information April 2006 02.0 Introduction Architecture MachXO Density Migration Technical Note (TN1097) added. Added “Power Supply and NC Connections” summary information for LCMXO1200 and LCMXO2280 in 100 TQFP package. Supply Current (Standby) table updated with LCMXO1200/2280 data. Ordering Part Number section updated (added LCMXO2280C "4W"). Introduction paragraphs updated. Architecture Overview paragraphs updated. Change Summary © 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 7-1 Lattice Semiconductor Date April 2006 (cont.) Version 02.0 (cont.) Section Architecture (cont.) Revision History MachXO Family Data Sheet Change Summary “Top View of the MachXO1200 Device” figure updated. “Top View of the MachXO640 Device” figure updated. “Top View of the MachXO256 Device” figure updated. “Slice Diagram” figure updated. Slice Signal Descriptions table updated. Routing section updated. sysCLOCK Phase Lockecd Loops (PLLs) section updated. PLL Diagram updated. PLL Signal Descriptions table updated. sysMEM Memory section has been updated. PIO Groups section has been updated. PIO section has been updated. MachXO PIO Block Diagram updated. Supported Input Standards table updated. MachXO Configuration and Programming diagram updated. DC and Switching Characteristics Recommended Operating Conditions table - footnotes updated. MachXO256 and MachXO640 Hot Socketing Specifications - footnotes updated. Added MachXO1200 and MachXO2280 Hot Socketing Specifications table. DC Electrical Characteristics, footnotes have been updated. Supply Current (Sleep Mode) table has been updated, removed "4W" references. Footnotes have been updated. Supply Current (Standby) table and associated footnotes updated. Intialization Supply Current table and footnotes updated. Programming and Erase Flash Supply Current table and associated footnotes have been updatd. Register-to-Register Performance table updated (rev. A 0.19). MachXO External Switching Characteristics updated (rev. A 0.19). MachXO Internal Timing Parameters updated (rev. A 0.19). MachXO Family Timing Adders updated (rev. A 0.19). sysCLOCK Timing updated (rev. A 0.19). MachXO "C" Sleep Mode Timing updated (A 0.19). JTAG Port Timing Specification updated (rev. A 0.19). Test Fixture Required Components table updated. Pinout Information Signal Descriptions have been updated. Pin Information Summary has been updated. Footnote has been added. Power Supply and NC Connection table has been updated. Logic Signal Connections have been updated (PCLKTx_x --> PCLKx_x) Ordering Information May 2006 August 2006 02.1 02.2 Pinout Information Multiple Removed "4W" references. Added 256-ftBGA Ordering Part Numbers for MachXO640. Removed [LOC][0]_PLL_RST from Signal Description table. PCLK footnote has been added to all appropriate pins. Removed 256 fpBGA information for MachXO640. 7-2 Lattice Semiconductor Date November 2006 Version 02.3 Section DC and Switching Characteristics Revision History MachXO Family Data Sheet Change Summary Corrections to MachXO “C” Sleep Mode Timing table - value for tWSLEEPN (400ns) changed from max. to min. Value for tWAWAKE (100ns) changed from min. to max. Added Flash Download Time table. EBR Asynchronous Reset section added. Power Supply and NC table: Pin/Ball orientation footnotes added. Updated EBR Asynchronous Reset section. Updated sysIO Single-Ended DC Electrical Characteristics table. Added JTAG Port Timing Waveforms diagram. Added Thermal Management text section. Updated title list. December 2006 February 2007 August 2007 November 2007 02.4 02.5 02.6 02.7 Architecture Pinout Information Architecture DC and Switching Characteristics DC and Switching Characteristics Pinout Information Supplemental Information 7-3