Lattice Embedded Vision Development Kit
User Guide
FPGA-UG-02015-1.3
November 2018
Lattice Embedded Vision Development Kit
User Guide
Contents
Acronyms in This Document .................................................................................................................................................4
1. Introduction ..................................................................................................................................................................5
2. Functional Description ..................................................................................................................................................6
2.1.
CrossLink .............................................................................................................................................................6
2.2.
ECP5.....................................................................................................................................................................7
2.3.
SiI1136 .................................................................................................................................................................7
3. Demo Requirements .....................................................................................................................................................8
3.1.
CrossLink VIP Input Bridge Board ........................................................................................................................9
3.2.
ECP5 VIP Processor Board .................................................................................................................................11
3.3.
HDMI VIP Output Bridge Board .........................................................................................................................13
4. Jumper Settings ..........................................................................................................................................................15
5. Demo Procedure .........................................................................................................................................................16
6. Demo Package Directory Structure.............................................................................................................................17
7. Pinout Information .....................................................................................................................................................18
7.1.
CrossLink ...........................................................................................................................................................18
7.2.
ECP5...................................................................................................................................................................19
8. Ordering Information ..................................................................................................................................................20
References ..........................................................................................................................................................................21
Technical Support ...............................................................................................................................................................22
Appendix A. Lattice Embedded Vision Development Kit Setup ..........................................................................................23
Appendix B. Programming the Lattice Embedded Vision Development Kit .......................................................................24
Using Diamond Programmer with the EVDK ..................................................................................................................24
ECP5 SPI Flash Programming ..........................................................................................................................................24
Erasing the ECP5 Prior to Reprogramming .................................................................................................................24
Programming the SPI on the ECP5 VIP Processor Board ............................................................................................25
CrossLink SPI Flash Programming ...................................................................................................................................27
Erasing the CrossLink FPGA Prior to Reprogramming.................................................................................................27
Programming the SPI on the CrossLink VIP Input Bridge Board .................................................................................28
Troubleshooting CrossLink VIP Input Bridge Board Programming .............................................................................30
Revision History ..................................................................................................................................................................31
© 2017-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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Figures
Figure 2.1. 2:1 MIPI CSI-2 to HDMI Bridge System Diagram ................................................................................................. 6
Figure 2.2. CrossLink Functional Block Diagram ................................................................................................................... 6
Figure 2.3. ECP5 Functional Block Diagram .......................................................................................................................... 7
Figure 2.4. SiI1136 Functional Block Diagram ...................................................................................................................... 7
Figure 3.1. Dual Camera to HDMI Setup ............................................................................................................................... 8
Figure 3.2.Top and Bottom View of CrossLink VIP Input Bridge Board .............................................................................. 10
Figure 3.3. Top and Bottom View of ECP5 VIP Processor Board ........................................................................................ 12
Figure 3.4. Top and Bottom View of HDMI VIP Output Board ........................................................................................... 14
Figure 5.1. Dual Camera Merged Image ............................................................................................................................. 16
Figure B.1. Create a New Blank Project .............................................................................................................................. 24
Figure B.2. Selecting Device ................................................................................................................................................ 25
Figure B.3. Device Operation .............................................................................................................................................. 25
Figure B.4. Device Properties.............................................................................................................................................. 26
Figure B.5. Output Console ................................................................................................................................................. 27
Figure B.6. Select Device..................................................................................................................................................... 27
Figure B.7. Device Operation .............................................................................................................................................. 28
Figure B.8. Device Properties.............................................................................................................................................. 29
Figure B.9. Output Console ................................................................................................................................................. 29
Tables
Table 4.1. CrossLink VIP Input Bridge Board ....................................................................................................................... 15
Table 4.2. ECP5 VIP Processor Board .................................................................................................................................. 15
Table 7.1. CrossLink Pinouts ............................................................................................................................................... 18
Table 7.2. ECP5 Pinouts ...................................................................................................................................................... 19
Table 8.1. Ordering Information ......................................................................................................................................... 20
Table B.1. SPI Flash Options Selection Guide ..................................................................................................................... 26
Table B.2. SPI Flash Options Selection Guide ..................................................................................................................... 28
© 2017-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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Acronyms in This Document
A list of acronyms used in this document.
Acronym
Definition
CSI
EVDK
GPIO
HDMI
I2 C
MIPI
VIP
USB
Camera Serial Interface
Embedded Vision Development Kit
General Purpose Input/Output
High Definition Multimedia Interface
Inter-Integrated Circuit
Mobile Industry Processing Interface
Video Interface Platform
Universal Serial Bus
© 2017-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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1. Introduction
This document describes the design and setup procedure for the Lattice Embedded Vision Development Kit (EVDK) to
demonstrate dual CSI-2 camera to High Definition Multimedia Interface (HDMI®) bridging that features the CrossLink™,
FPGA, ECP5™ FPGA and SiI1136 transmitter devices.
Figure 2.1 shows the Lattice Embedded Vision Development Kit that is designed as a stackable modular architecture
with 80 mm × 80 mm form factor. The Lattice Embedded Vision Development Kit consists of three boards:
CrossLink Video Interface Platform (VIP) Input Bridge Board
ECP5 VIP Processor Board
HDMI VIP Output Bridge Board
The figures shown in this document are of the Revision C version of the Embedded Vision Development Kit, for earlier
versions refer to the individual evaluation board’s user guide. For more information on Embedded Vision Development
Kit, visit www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/EmbeddedVisionDevelopmentKit.aspx
Input Video
Source Board
ECP5 Video
Processor Board
1.
Output Video
Delivery Board
2.
3.
.
Figure 1.1. 2:1 MIPI CSI-2 to HDMI Bridge
© 2017-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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2. Functional Description
The dual camera Mobile Industry Processing Interface (MIPI®) CSI-2 to HDMI demo uses a Sony IMX214 camera to
output 1080p video over four MIPI data lanes, each running at 371.25 Mb/s. CrossLink VIP input bridge board receives
the MIPI video stream from onboard camera sensor and extracts the video pixels. These video pixels from two cameras
are merged side by side and the combined image data is transmitted to ECP5 in the form of parallel CMOS interface on
the ECP5 video processor board through board-to-board connectors.
The ECP5 FPGA processes the merged sensor image and sends processed parallel image data to the Sil1136 HDMI
transmitter on the HDMI VIP output bridge board through board to board connectors. The Sil1136 chip transmits the
video data via HDMI to the 1080p display.
Camera 1
CrossLink VIP
Bridge Board
RAW+FV/LV
I2C Control
ECP5 VIP Board
RGB Parallel
HSYNC/VSYNC
HDMI VIP Output
Board
HDMI
Monitor
Camera 2
Figure 2.1. 2:1 MIPI CSI-2 to HDMI Bridge System Diagram
2.1. CrossLink
The dual-camera-to-parallel design receives the serial, source-synchronous MIPI data from two MPI CSI-2 cameras,
reserializes the serial data into bytes and extracts the control signal from MIPI data packets. The byte data is sent to
Byte to Pixel module which converts the byte data into RAW10 data. The two streams of RAW data are sent to the
Image merger logic which combines the parallel data from both data streams and sends it to the ECP5 board. The
onboard CSI-2 cameras are configured through the I2C master interface on ECP5 VIP processor board. Figure 2.2 shows
the CrossLink functional block diagram.
Line Valid
X4 Lane MIPI I/F
(CAM1)
D-PHY Wrapper
Hard D-PHY
Cross Domain
FIFO
Write Byte
Write Byte
Clock
Clock
Write Byte Clock
RX Global Operation
Controller
Byte to Pixel
Frame Valid
Pixel Clock
FIFO
Pixel Data
Control Capture
Read Byte
Clock
Read Byte
Clock
Read Byte Pixel
Clock
Clock
Line Valid
Image
Merger
LP HS
Controller
Frame Valid
Pixel Clock
Pixel Data
Line Valid
X4 Lane MIPI I/F
(CAM2)
D-PHY Wrapper
Hard D-PHY
Cross Domain
FIFO
Write Byte
Write Byte
Clock
Clock
Write Byte Clock
RX Global Operation
Controller
Byte to Pixel
Frame Valid
Pixel Clock
FIFO
Pixel Data
Control Capture
Read Byte
Clock
Read Byte
Clock
Read Byte Pixel
Clock
Clock
LP HS
Controller
Write Byte
Clock
PLL
Read Byte
Clock
Pixel Clock
Figure 2.2. CrossLink Functional Block Diagram
© 2017-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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2.2. ECP5
The ECP5 FPGA receives RAW10 data from CrossLink, does the fundamental image processing, and sends it to the
HDMI board. Figure 2.3 shows the Lattice Programmable Image Processing Module. This module improves the quality
of an image from a sensor by:
Auto Brightness – The Auto Brightness module adjusts the intensity of incoming sensor data.
Debayer – The Debayer converts the RAW10 Bayer data into separate red, green and blue pixels per clock cycle.
Color Space Converter – Colors directly from an image sensor do not match the real world by default. The Color
Space Converter matrix corrects this issue. There are gain and offset controls for each color, as well as the
influence of one color on the other.
Gamma Correction – Gamma Correction is a type of pre-distortion correction made to video frames to offset the
non-linear behavior of display systems.
Line Valid
Frame Valid
Pixel Clock
Auto
Brightness
Line Valid
Vsync
Frame Valid
Pixel Clock
Hsync
Data Enable
Debayer
Pixel Clock
Vsync
Hsync
Color Space
Converter
Gamma
Correction
Pixel Data
Data Enable
Pixel Clock
Pixel Data
Figure 2.3. ECP5 Functional Block Diagram
2.3. SiI1136
Figure 2.4 shows the functional block diagram of the SiI1136 HDMI transmitter. This transmitter device is configured to
output 1080p60 through the ECP5 I2C Master interface on ECP5 VIP processor board. It receives 36-bit RGB data and
control signals from ECP5 and converts it to HDMI format that is displayed on the HDMI monitor.
I2C
I2C Slave
Controller
I2C Master
Controller
DDC
Vsync
Hsync
Data Enable
Pixel Clock
HDMI Transmitter
SiI1136
CEC
Pixel Data
36-bit RGB
Parallel to HDMI
HDMI
HPD
Figure 2.4. SiI1136 Functional Block Diagram
© 2017-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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3. Demo Requirements
The following equipment is required for the demo:
LF-EVDK1-EVN Demo Kit
HDMI monitor
HDMI cable
DC power adapter (12 V)
Laptop/PC
Bit/JED file
USB 2.0 Type A to Mini-B cable*
Lattice Diamond® Programmer version 3.7 or higher*
*Note: Required only in re-programming.
Figure 3.1. Dual Camera to HDMI Setup
© 2017-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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3.1. CrossLink VIP Input Bridge Board
Flash Chip CRESETB
Wakeup System Reset
SPI Flash (U9) Select (J4) Selection (J30) (SW1) (SW3)
External Programming
Header (J29)
IMX214 Camera Sensor
Connector (CN1)
User LEDs
(D7-D10)
FPGA SPI Chip Select (J2)
Power LEDs
IMX214 Camera Sensor
Connector (CN2)
LIF-MD6000-CSFBGA81 (U4)
Sensor Reset (SW2)
External Clock
Debug Header
Connection (J22) (J28)
Clock Selection
Header (J23)
© 2017-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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Lattice Embedded Vision Development Kit
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Upstream Header (J3)
Upstream Header (J1)
Figure 3.2.Top and Bottom View of CrossLink VIP Input Bridge Board
© 2017-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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3.2. ECP5 VIP Processor Board
12V DC Power
Jack (J4)
USB Mini-B
Connector (J2)
Downstream
Connector (J13)
Power LEDs
FTDI Chip (U2)
LFE5UM-85F-BG756
(U17)
DDR3 Memory
(U12, U19)
Downstream
Connector (J12)
© 2017-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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ispClock
USER3 (J54)
Daisy Chain JTAG
Header (J50)
Bank 2 Voltage
Selection Header (J55)
JTAG Header (J1)
Debug Header (J14)
Power ON/OFF
Switch (SW2)
ispClock5406D (U53)
FTDI Reset (J53)
SPI Flash (U52)
ECP5 Configuration
Selection Header (J3)
FTDI EEPROM (U4)
System Reset (SW1)
User LEDs
ProgramN (SW4)
Upstream Connector
(J10)
Nanovesta Connectors
(CN1, CN2)
FTDI TCK Pull
Up/Down (J52)
Bank 0 Voltage
Selection Header (J7)
Upstream Connector
(J11)
Bank 1, 8, 3 Voltage
Selection Headers
(J6, J9, J5)
General Purpose
Switches (SW3)
Bank 4 Voltage
Selection Header(J51)
Figure 3.3. Top and Bottom View of ECP5 VIP Processor Board
© 2017-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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3.3. HDMI VIP Output Bridge Board
User LEDs
SiI1136
Type-A HDMI
Connector
SW1
J4
© 2017-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-UG-02015-1.3
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Downstream
Connector (J2)
Downstream
Connector (J1)
Figure 3.4. Top and Bottom View of HDMI VIP Output Board
© 2017-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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4. Jumper Settings
Table 4.1. CrossLink VIP Input Bridge Board
Jumper
J2
J4
J30
—
Description
CrossLink SPI Chip Select
SPI Flash Chip Select
CRESETB selection
—
Default
Short
Short
Open
All other headers should be kept open.
Table 4.2. ECP5 VIP Processor Board
Jumper
J3
J5
J6
J7
J9
J50
J51
J52
J53
J55
—
Description
ECP5 Configuration Selection
Bank 3 Voltage Selection
Bank 1 Voltage Selection
Bank 0 Voltage Selection
Default
Connect 1 and 2 and connect 5 and 6 (Master SPI)
Connect 1 and 2 (3.3 V)
Connect 1 and 2 (3.3 V)
Connect 2 and 3 (3.3 V)
Bank 8 Voltage Selection
JTAG Daisy Chain
Bank 4 Voltage Selection
FTDI TCK Pull Up/Down
FTDI Reset
Bank 2 Voltage
—
Connect 1 and 2 (3.3 V)
Connect 1 and 2 and connect 3 and 5 (ECP5 Only)
Connect 1 and 2 (3.3 V)
Connect 2 and 3 (JTAG)
Connect 1 and 2 (Pulled High)
Connect 2 and 3 (3.3 V)
All other headers should be kept open.
© 2017-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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5. Demo Procedure
To set up the demonstration:
1.
Connect the ECP5 VIP processor board to the wall socket using 12 V power adapter.
2.
Power up the demo kit by turning on SW2 on ECP5 VIP processor board.
3.
Connect the HDMI cable from CN1 of HDMI VIP output board to the HDMI display/monitor. The monitor displays
the dual camera merged image as shown in Figure 5.1.
Figure 5.1. Dual Camera Merged Image
© 2017-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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6. Demo Package Directory Structure
The key files and directories are listed below:
Dual_CSI-2_Camera_to_HDMI_Bridge_Demo
CrossLink_DualCSI2toRaw10
(Main directory)
(CrossLink design directory)
bitstream
DualCSI2toRaw10.bit
(CrossLink bitstream)
source
(CrossLink source files)
DualCSI2toRaw10.ldf
(CrossLink Diamond Project File)
DualCSI2toRaw10.lpf
(CrossLink Project Settings File)
DualCSI2toRaw101.sty
(CrossLink Project Strategy File)
ECP5_Raw10toParallel
(ECP5 design directory)
bitstream
Raw10toParallel.bit
(ECP5 bitstream)
source
(ECP5 source files)
Raw10toParallel.ldf
(ECP5 Diamond Project File)
Raw10toParallel.lpf
(ECP5 Project Settings File)
Raw10toParallel1.sty
(ECP5 Project Strategy File)
© 2017-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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7. Pinout Information
7.1. CrossLink
Table 7.1 lists the CrossLink pinouts used for the demo.
Table 7.1. CrossLink Pinouts
Port Name
Pin
reset_n_i
J4
Camera Sensor Interface
clk_p_i
A1
clk_n_i
A2
d0_p_i
B1
d0_n_i
B2
d1_p_i
A3
Bank
1
Buffer Type
LVCMOS33_IN
Site
PB38C
Properties
Pull: Up, Clamp: On, Hysteresis: On
61
61
61
61
61
DPHY_BIDI
DPHY_BIDI
DPHY_BIDI
DPHY_BIDI
DPHY_BIDI
DPHY1_CKP
DPHY1_CKN
DPHY1_DP0
DPHY1_DN0
DPHY1_DP1
—
—
—
—
—
d1_n_i
d2_p_i
d2_n_i
d3_p_i
d3_n_i
clk_p_i_s
clk_n_i_s
d0_p_i_s
d0_n_i_s
d1_p_i_s
B3
C1
C2
A4
B4
A8
A9
B7
A7
B8
61
61
61
61
61
60
60
60
60
60
DPHY_BIDI
DPHY_BIDI
DPHY_BIDI
DPHY_BIDI
DPHY_BIDI
DPHY_BIDI
DPHY_BIDI
DPHY_BIDI
DPHY_BIDI
DPHY_BIDI
DPHY1_DN1
DPHY1_DP2
DPHY1_DN2
DPHY1_DP3
DPHY1_DN3
DPHY0_CKP
DPHY0_CKN
DPHY0_DP0
DPHY0_DN0
DPHY0_DP1
—
—
—
—
—
—
—
—
—
—
d1_n_i_s
d2_p_i_s
d2_n_i_s
d3_p_i_s
d3_n_i_s
ECP5 Interface
pixel_clk
fv
lv
pixdata[0]
pixdata[1]
pixdata[2]
pixdata[3]
pixdata[4]
pixdata[5]
pixdata[6]
pixdata[7]
pixdata[8]
pixdata[9]
B9
B6
A6
C8
C9
60
60
60
60
60
DPHY_BIDI
DPHY_BIDI
DPHY_BIDI
DPHY_BIDI
DPHY_BIDI
DPHY0_DN1
DPHY0_DP2
DPHY0_DN2
DPHY0_DP3
DPHY0_DN3
—
—
—
—
—
J6
J3
H3
F9
F8
G9
G8
E9
E8
H9
H8
F7
E7
1
1
1
2
2
2
2
2
2
2
2
2
2
LVCMOS33_OUT
LVCMOS33_OUT
LVCMOS33_OUT
LVCMOS33_OUT
LVCMOS33_OUT
LVCMOS33_OUT
LVCMOS33_OUT
LVCMOS33_OUT
LVCMOS33_OUT
LVCMOS33_OUT
LVCMOS33_OUT
LVCMOS33_OUT
LVCMOS33_OUT
PB29C
PB43C
PB43D
PB2A
PB2B
PB2C
PB2D
PB6A
PB6B
PB6C
PB6D
PB12A
PB12B
Drive: 6 mA, Clamp: On
Drive: 6 mA, Clamp: On
Drive: 6 mA, Clamp: On
Drive: 6 mA, Clamp: On
Drive: 6 mA, Clamp: On
Drive: 6 mA, Clamp: On
Drive: 6 mA, Clamp: On
Drive: 6 mA, Clamp: On
Drive: 6 mA, Clamp: On
Drive: 6 mA, Clamp: On
Drive: 6 mA, Clamp: On
Drive: 6 mA, Clamp: On
Drive: 6 mA, Clamp: On
© 2017-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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7.2. ECP5
Table 7.2 lists the ECP5 pinouts used for the demo.
Table 7.2. ECP5 Pinouts
Port Name
Pin
clk_i
E17
reset_n
AH1
q
AG30
CrossLink Interface
CSI2_sens_clk
P27
CSI2_sens_fv
K27
CSI2_sens_lv
K26
CSI2_sens_data[0] A13
CSI2_sens_data[1] A8
CSI2_sens_data[2] F9
CSI2_sens_data[3] D9
CSI2_sens_data[4] C9
CSI2_sens_data[5] A9
CSI2_sens_data[6] C10
CSI2_sens_data[7] B10
CSI2_sens_data[8] A10
CSI2_sens_data[9] E11
reset_crosslink
D13
Camera Sensor Interface
scl
D15
Bank
1
8
4
Buffer Type
LVCMOS33_IN
LVCMOS33_IN
LVCMOS33_OUT
Site
—
PB4B
PB114B
Properties
—
Pull: Down, Clamp: On, Hysteresis: On
Drive:8 mA, Clamp: On, Slew: Slow
2
2
2
0
0
0
0
0
0
0
0
0
0
0
LVCMOS33_IN
LVCMOS33_IN
LVCMOS33_IN
LVCMOS33_IN
LVCMOS33_IN
LVCMOS33_IN
LVCMOS33_IN
LVCMOS33_IN
LVCMOS33_IN
LVCMOS33_IN
LVCMOS33_IN
LVCMOS33_IN
LVCMOS33_IN
LVCMOS33_OUT
PR44C
PR38A
PR38B
PT42B
PT20B
PT22A
PT22B
PT24A
PT24B
PT29B
PT31A
PT31B
PT33B
PT40B
Pull: Down, Clamp: On, Hysteresis: On
Pull: Down, Clamp: On, Hysteresis: On
Pull: Down, Clamp: On, Hysteresis: On
Pull: Down, Clamp: On, Hysteresis: On
Pull: Down, Clamp: On, Hysteresis: On
Pull: Down, Clamp: On, Hysteresis: On
Pull: Down, Clamp: On, Hysteresis: On
Pull: Down, Clamp: On, Hysteresis: On
Pull: Down, Clamp: On, Hysteresis: On
Pull: Down, Clamp: On, Hysteresis: On
Pull: Down, Clamp: On, Hysteresis: On
Pull: Down, Clamp: On, Hysteresis: On
Pull: Down, Clamp: On, Hysteresis: On
Drive:8 mA, Clamp: On, Slew: Slow
0
LVCMOS33_OUT
PT51B
Drive:8 mA, Clamp: On, Slew: Slow
scl2
sda
sda2
reset_sensor
SiI1136 Interface
HDMI_scl
HDMI_sda
pixclk_out
data_enable
hsync
vsync
pix_blue[0]
pix_blue[1]
pix_blue[2]
pix_blue[3]
pix_blue[4]
pix_blue[5]
pix_blue[6]
pix_blue[7]
pix_blue[8]
pix_blue[9]
A14
F15
B14
B4
0
0
0
0
LVCMOS33_OUT
LVCMOS33_OUT
LVCMOS33_OUT
LVCMOS33_OUT
PT49B
PT51A
PT49A
PT4B
Drive:8 mA, Clamp: On, Slew: Slow
Drive:8 mA, Clamp: On, Slew: Slow
Drive:8 mA, Clamp: On, Slew: Slow
Drive:8 mA, Clamp: On, Slew: Slow
AG1
AJ1
E25
C25
D25
A25
T31
R32
Y32
W31
T29
U28
V27
V26
AC31
AB32
8
8
1
1
1
1
3
3
3
3
3
3
3
3
3
3
PB4A
PB6A
PT110A
PT107A
PT107B
PT105A
PR65B
PR65A
PR86B
PR86A
PR53C
PR53D
PR56C
PR56D
PR89C
PR92A
Drive:8 mA, Clamp: On, Slew: Slow
Drive:8 mA, Clamp: On, Slew: Slow
Drive:8 mA, Clamp: On, Slew: Slow
Drive:8 mA, Clamp: On, Slew: Slow
Drive:8 mA, Clamp: On, Slew: Slow
Drive:8 mA, Clamp: On, Slew: Slow
Drive:8 mA, Clamp: On, Slew: Slow
Drive:8 mA, Clamp: On, Slew: Slow
Drive:8 mA, Clamp: On, Slew: Slow
Drive:8 mA, Clamp: On, Slew: Slow
Drive:8 mA, Clamp: On, Slew: Slow
Drive:8 mA, Clamp: On, Slew: Slow
Drive:8 mA, Clamp: On, Slew: Slow
Drive:8 mA, Clamp: On, Slew: Slow
Drive:8 mA, Clamp: On, Slew: Slow
Drive:8 mA, Clamp: On, Slew: Slow
LVCMOS33_OUT
LVCMOS33_OUT
LVCMOS33_OUT
LVCMOS33_OUT
LVCMOS33_OUT
LVCMOS33_OUT
LVCMOS33_OUT
LVCMOS33_OUT
LVCMOS33_OUT
LVCMOS33_OUT
LVCMOS33_OUT
LVCMOS33_OUT
LVCMOS33_OUT
LVCMOS33_OUT
LVCMOS33_OUT
LVCMOS33_OUT
© 2017-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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8. Ordering Information
Table 8.1. Ordering Information
Description
Lattice Embedded Vision Development Kit
Ordering Part Number
LF-EVDK1-EVN
© 2017-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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FPGA-UG-02015-1.3
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References
For more information, refer to:
ECP5 and ECP5-5G Family Data Sheet (FPGA-DS-02012, previously DS1044)
CrossLink Family Data Sheet (FPGA-DS-02007)
SiI9136-3/SiI1136 HDMI Deep Color Transmitter (SiI-DS-1084)
For schematics, refer to:
ECP5 VIP Processor Board Evaluation Board User Guide (FPGA-EB-02001)
CrossLink VIP Input Bridge Board Evaluation Board User Guide (FPGA-EB-02002)
HDMI VIP Output Bridge Board Evaluation Board User Guide (FPGA-EB-02003)
© 2017-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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Technical Support
For assistance, submit a technical support case at www.latticesemi.com/techsupport.
© 2017-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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Appendix A. Lattice Embedded Vision Development Kit Setup
To set up the display demo boards:
1.
Connect the J3 and J1 connectors of the CrossLink VIP input bridge board to the J10 and J11 connectors of the
ECP5 VIP board.
2.
Connect the J13 and J12 connectors of the ECP5 VIP board to the J2 and J1 connectors of the HDMI VIP output
board.
3.
Connect one end of the HDMI cable to the C1 connector of the HDMI VIP output board and the other end to the
monitor.
4.
Connect the 12 V wall power adapter cable to the J4 connector of the ECP5 VIP board.
5.
The Dual CSI-2 camera to HDMI Bridge design should be programmed into the SPI Flash on the EVDK. This loads the
reference design on power up. Refer to Appendix B. Programming the Lattice Embedded Vision Development Kit to
update or change the FPGA or SPI Flash images.
© 2017-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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Appendix B. Programming the Lattice Embedded Vision
Development Kit
Using Diamond Programmer with the EVDK
The EVDK has a built-in download controller for programming. It uses an FT2232H Future Technology Devices
International (FTDI) part to convert USB to JTAG. To use the built-in download controller, connect the USB cable from
J2 of the ECP5 VIP Processor Board to your PC (with Diamond programming software installed). A mini USB to USB-A
cable is included in the EVDK. The USB hub on the PC detects the cable of the USB function on Port 0, making the builtin download controller available for use with the Diamond programming software.
In order to provide a single programming interface for the EVDK, the ECP5 VIP Processor Board’s JTAG interface is
shared with the CrossLink VIP Input Bridge Board’s SPI programming interface. During a JTAG scan, the Diamond
Programmer only sees one of the devices:
LFE5UM-85F, if the CrossLink device is currently programmed
LIF-MD6000, if the CrossLink device is not programmed
A JTAG scan also erases both ECP5 and CrossLink SRAM images, requiring you to reprogram both devices. When using
the Diamond Programmer, selecting Create a new blank project and manually selecting the device family and device
prevents the erasure of both devices.
Figure B.1. Create a New Blank Project
ECP5 SPI Flash Programming
Erasing the ECP5 Prior to Reprogramming
If the ECP5 is already programmed (either directly, or loaded from SPI Flash), erase first the ECP5 SRAM memory, then
program the ECP5’s SPI Flash in the next section. Keep the board powered when re-programming the SPI Flash in the
next section.
To erase the ECP5:
1.
Launch Diamond Programmer with Create a new blank project.
2.
Select ECP5UM for Device Family and LFE5UM-85F for Device.
© 2017-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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FPGA-UG-02015-1.3
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Figure B.2. Selecting Device
3.
Right-click and select Device Properties.
4.
Select JTAG 1532 Mode for Access Mode and Erase Only for Operation.
Figure B.3. Device Operation
5.
Click OK to close the Device Properties window.
6.
Click the Program button
in Diamond Programmer to start the Erase sequence.
Programming the SPI on the ECP5 VIP Processor Board
To program the SPI:
1.
Ensure the ECP5 device is erased by performing Steps 1-6.
2.
Right-click and select Device Properties.
3.
Select SPI Flash Background Programming for Access mode and make the following selections:
a.
For Programming File, browse and select the ECP5 bitfile (*.bit)
b.
For SPI Flash Options, refer Table B.1.
© 2017-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-UG-02015-1.3
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Lattice Embedded Vision Development Kit
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Table B.1. SPI Flash Options Selection Guide
Item
Family
Vendor
Rev A/B
SPI Serial Flash
Micron
Rev C
SPI Serial Flash
Macronix
Device
Comment
SPI-N25Q128A
—
MX25L12835F
If the above device is not available in
Diamond Programmer, select Macronix
MX25L12805.
Figure B.4. Device Properties
4.
Click OK to close the Device Properties window.
5.
Click the Program button
6.
After successful programming, the Output console displays the results as shown in Figure B.5.
in Diamond Programmer to start the programming sequence.
© 2017-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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FPGA-UG-02015-1.3
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Figure B.5. Output Console
CrossLink SPI Flash Programming
Erasing the CrossLink FPGA Prior to Reprogramming
If the CrossLink device is already programmed (either directly, or loaded from SPI Flash), follow this procedure to first
erase the CrossLink SRAM memory before re-programming the CrossLink’s SPI Flash. If you are doing this, keep the
board powered when re-programming the SPI Flash (so it does not reload on reboot).
To erase CrossLink:
1.
Launch Diamond Programmer with Create a new blank project.
2.
Select LIFMD for Device Family and LIF-MD6000 for Device.
Figure B.6. Select Device
3.
Right-click and select Device Properties.
4.
Select SSPI SRAM Programming for Access Mode and Erase Only for Operation.
© 2017-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-UG-02015-1.3
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Lattice Embedded Vision Development Kit
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Figure B.7. Device Operation
5.
Click OK to close the Device Properties window.
6.
Click the Program button
in Diamond Programmer to start the Erase sequence.
Programming the SPI on the CrossLink VIP Input Bridge Board
To program the SPI:
1.
Ensure the CrossLink device is erased by performing Steps 1-6.
2.
Right-click and select Device Properties.
3.
Select SPI Flash Programming for Access mode and make the following selections:
a.
For Programming File, browse and select the CrossLink bitfile (*.bit).
b.
For SPI Flash Options, refer to Table B.2.
Table B.2. SPI Flash Options Selection Guide
Item
Family
Vendor
Device
Comment
Rev A/B
SPI Serial Flash
Micron / ST Micro
SPI-M25PX16
Marked with ST-Micro
Logo
Rev C – Option 1
SPI Serial Flash
Micron
MT25QL128
Marked with Micron
Logo
Rev C – Option 2
SPI Serial Flash
Micron / ST Micro
SPI-M25PX16
Marked with ST-Micro
Logo
Rev C – Option 3
SPI Serial Flash
Numonyx / Micron
M25P128
Marked with Lot Code
Only – No Vendor or
Part Number Marking
Note: Boards are populated with one of any qualified SPI Flash Device (U9). This device is located just below the Lattice logo on the
top of the board. It is best to verify this device visually by the marking on the device. Use this table to determine the correct
selection in Diamond Programmer.
© 2017-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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FPGA-UG-02015-1.3
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Figure B.8. Device Properties
4.
Click OK to close the Device Properties window.
5.
Click the Program button
6.
After successful programming, the Output console displays the results as shown in Figure B.9.
in Diamond Programmer to start the programming sequence.
Figure B.9. Output Console
© 2017-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-UG-02015-1.3
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Lattice Embedded Vision Development Kit
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Troubleshooting CrossLink VIP Input Bridge Board Programming
To troubleshoot CrossLink (LIF-MD6000) programming:
1.
Make sure the CrossLink device is erased prior to programming SPI flash. If you re-power the board, it will reload
the SPI Flash image to the CrossLink. Follow the sequence in the Crosslink SPI Flash Programming section of this
document. Erase CrossLink (LIF-MD6000) first, and then perform the SPI Flash programming sequence without repowering the board.
2.
R47 is a pull-up resistor on the SPI SCK line. This was originally specified as 1 kΩ. Later testing suggests 10 kΩ
improves noise immunity for SPI Programming. If possible, changing this resistor to 10 kΩ may improve SPI
programming consistency. Boards populated with R47 = 10 kΩ have a small dot in the silkscreen box, just above
the copyright mark.
3.
For short-term workaround of SPI Flash programming issues, you can use SSPI SRAM Programming (programming
CrossLink SRAM directly). This programming will only be retained as long as power remains applied to the board,
and the device is not reset.
© 2017-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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Revision History
Revision 1.3, November 2018
Section
Change Summary
Appendix B. Programming the
Lattice Embedded Vision
Development Kit
Revision History
Changed value of device in Revision C under Table B.1. SPI Flash Options Selection
Guide.
Updated Figure B.4. Device Properties.
Updated Table B.1. SPI Flash Options Selection Guide.
Updated Table B.2. SPI Flash Options Selection Guide.
Added Troubleshooting CrossLink VIP Input Bridge Board Programming section.
Updated revision history table to new template.
Revision 1.2, February 2018
Section
Introduction
Functional Description
Demo Package Directory
Structure
Change Summary
Updated figures for Rev C board.
Updated ECP5 section for ECP5 Design.
General update.
Appendix B. Programming the
Lattice Embedded Vision
Development Kit
Added this section in the document.
Revision 1.1, January 2018
Section
All
Introduction
Appendix A. Lattice Embedded
Vision Development Kit Setup
Change Summary
Updated Lattice Semiconductor Logo on the cover pages, headers, and footers of this
document.
Changed pASSP to FPGA.
Changed pASSP to FPGA.
Revision 1.0, April 2017
Section
All
Change Summary
Initial release.
© 2017-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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