LF500-PAC-EV

ispXPGA™ Evaluation Board User’s Guide October 2004 ebug02_02 Lattice Semiconductor ispXPGA Evaluation Board User’s Guide Introduction The ispXPGA Evaluation Board is a versatile platform that enables the user to program, evaluate, and de-bug a design for the Lattice ispXPGA architecture. The board features a 900-ball fpBGA ispXPGA device with SMA connectors for access to the device’s High Speed Interface (sysHSI™) and other I/Os. Connectors are also available to access general-purpose I/Os. Termination is provided for selected I/Os for LVDS operation. Features • Power management provided via ispPAC® Power Manager device • On-board 20MHz oscillator • Multiple integrated Low Drop-Out (LDO) regulators provide power from single 5V supply • ispVM® programming support • Jumperless implementation • ispDOWNLOAD® Cable (pDS4102-DL2A) included • 900-ball fpBGA ispXPGA device (ispXPGA 1200 or ispXPGA 500) Figure 1. ispXPGA Evaluation Board Electrical, Mechanical and Environmental Specifications The nominal board dimensions are 4.5 inches by 5 inches. The environmental specifications are as follows: • Operating temperature: 0°C to 55°C • Storage temperature: -40°C to 75°C • Humidity: < 95% without condensation 2 Lattice Semiconductor ispXPGA Evaluation Board User’s Guide • 5VDC input, accessible via banana jacks or the included 5V, 4A AC adapter Holes are included at the corners of the PCB to provide attachment of vertical stand-offs. The pads at these holes are electrically floating. Resources relating to the ispXPGA Evaluation Board, including a simple demonstration design, can be found on the Lattice web site at www.latticesemi.com. Table 1. Embedded Functions Description Source 20MHz clock On-board oscillator Reset ispPAC device ispXPGA Pin Notes GCLK0 (R3) 3.3V TTL output Global RST (AK28) AND I/O pin AF21 Active low by default, programmable via ispPAC ispXPGA Device The board features an ispXPGA device in a 900-ball fpBGA package. Benefiting from a compatible layout, it is also possible to use an ispXPGA device in the smaller 516-ball fpBGA package. This provides a future option to evaluate devices with a smaller density. ispPAC-POWR1208 Power Manager Device The Power Manager device controls the sequencing and monitoring of the various independent power supplies available on the ispXPLD board. Each supply can be activated in stages, with programmable delay increments. As the Power Manager device enables each LDO, a corresponding LED deactivates for visual confirmation. The Power Manager design and JEDEC files can be downloaded from the Lattice web site. The device is shipped preprogrammed with this default configuration. For a complete description of the operation of the ispPAC-POWR1208 device and the default design used on this board, refer to the ispPAC-POWR1208 data sheet and PAC-Designer® documentation (PAC-Designer is the design software for the ispPAC-POWR1208). These are available on the Lattice web site at www.latticesemi.com. VCCO Configurations The ispXPGA device supports multiple I/O standards and individual I/O bank supply pins for simultaneous support of different interfaces. The ispXPGA evaluation board is set by default to supply 2.5V to all I/O banks. This is adjustable via the addition of resistors. For alternate supply levels, specific resistor values can be installed as described in Figure 2. Figure 2. I/O Voltage Adjustments From LDO Output R Fixed TOP R User TOP R Fixed BOT R User BOT To LDO FB User-installable voltage set resistors 3 Lattice Semiconductor ispXPGA Evaluation Board User’s Guide Table 2. VCCOX LDO Adjustments VCCOX R Fixed TOP R Fixed BOT R User TOP R User BOT 2.5V 127.0K 110.0K DNP DNP 3.3V 127.0K 110.0K DNP 200.0K 1.8V 127.0K 110.0K 110.0K DNP 1.5V 127.0K 110.0K 402K DNP Resistor numbers and physical location can be found in the schematic and bottom silk screen drawing, at the end of this document. Switches One push-button reset switch (SW1) is provided to force a reset of the ispPAC-POWR1208 device. When this switch is activated, the power-up cycle of the ispPAC-POWR1208 device is re-started. This, in turn, cycles power to the rest of the board. The ispXPGA device contains power-on reset circuitry, for predicable initialization. Programming Headers Separate 1x8 headers are provided to allow independent configuration the ispXPGA and ispPAC devices. Pin 1 of both headers is VCC (red wire from download cable). Table 3 shows the programming header locations. Table 3. Programming Connectors Connector Target Device JTAG Connector P1 ispPAC-POWR1208 JTAG Connector P2 ispXPGA I/O Connectors Connectivity for general-purpose I/O pins is provided by both 2mm DIP headers and Mictor connectors on the underside of the board. Tables 2 and 3 provide locations for the ispXPGA I/Os. Table 4 lists the High-Speed SMA connector locations. Table 4. I/O Banks 2, 3 P4 (2mm) J26 (Mictor) 1 1 GCLK2 Description ispXPGA Pin Notes 2 2 GND — 3 3 GCLK3 T5 4 4 GND 5 5 BK3_IO12_LP180_LVDT 6 6 BK3_IO14_LP182_LVDT AJ18 LVDS Transmit Resistor Network 7 7 BK3_IO13_LP180_LVDT AG18 LVDS Transmit Resistor Network 8 8 BK3_IO15_LP182_LVDT AK18 LVDS Transmit Resistor Network 9 9 BK3_IO10_LP179_LVDT AF17 LVDS Transmit Resistor Network 10 10 BK3_IO8_LP178_LVDT AH17 LVDS Transmit Resistor Network 11 11 BK3_IO11_LP179_LVDT AE17 LVDS Transmit Resistor Network 12 12 BK3_IO9_LP178_LVDT AG17 LVDS Transmit Resistor Network 13 13 BK3_IO6_LP175_LVDT AK17 LVDS Transmit Resistor Network 14 14 BK3_IO0_LP172_LVDT AK16 LVDS Transmit Resistor Network 15 15 BK3_IO7_LP175_LVDT AJ17 LVDS Transmit Resistor Network 16 16 BK3_IO1_LP172_LVDT AJ16 LVDS Transmit Resistor Network T4 — AH18 4 LVDS Transmit Resistor Network Lattice Semiconductor ispXPGA Evaluation Board User’s Guide Table 4. I/O Banks 2, 3 (Continued) P4 (2mm) J26 (Mictor) 17 17 BK3_IO2_LP173_LVDT Description ispXPGA Pin Notes 18 18 19 19 20 20 BK3_IO5_LP174_LVDT AE16 LVDS Transmit Resistor Network 21 21 BK3_IO16_LP187_LVDT AE18 LVDS Transmit Resistor Network 22 22 BK2_IO16_LP134_LVDR AG8 100Ω LVDS Receive Termination 23 23 BK3_IO17_LP187_LVDT AD18 LVDS Transmit Resistor Network 24 24 BK2_IO17_LP134_LVDR AH8 100Ω LVDS Receive Termination 25 — GND AH16 LVDS Transmit Resistor Network BK3_IO4_LP174_LVDT AF16 LVDS Transmit Resistor Network BK3_IO3_LP173_LVDT AG16 LVDS Transmit Resistor Network — 26 — GND 27 25 BK2_IO0_LP116_LVDR AG5 — 100Ω LVDS Receive Termination 28 26 BK2_IO10_LP123_LVDR AG7 100Ω LVDS Receive Termination 29 27 BK2_IO1_LP116_LVDR AH5 100Ω LVDS Receive Termination 30 28 BK2_IO11_LP123_LVDR AH7 100Ω LVDS Receive Termination 31 29 BK2_IO18_LP135_LVDR AJ7 100Ω LVDS Receive Termination 32 30 BK2_IO4_LP118_LVDR AG6 100Ω LVDS Receive Termination 33 31 BK2_IO19_LP135_LVDR AK7 100Ω LVDS Receive Termination 34 32 BK2_IO5_LP118_LVDR AH6 100Ω LVDS Receive Termination 35 33 BK2_IO14_LP129_LVDR AJ6 100Ω LVDS Receive Termination 36 34 BK2_IO6_LP121_LVDR AJ5 100Ω LVDS Receive Termination 37 35 BK2_IO15_LP129_LVDR AK6 100Ω LVDS Receive Termination 38 36 BK2_IO7_LP121_LVDR AK5 100Ω LVDS Receive Termination 39 37 BK2_IO2_LP117_LVDR AJ4 100Ω LVDS Receive Termination 40 38 BK2_IO8_LP122_LVDR AE7 100Ω LVDS Receive Termination 41 — BK3_IO2_LP117_LVDR AH16 100Ω LVDS Receive Termination 42 — BK2_IO9_LP122_LVDR AF7 100Ω LVDS Receive Termination 43 — GND 44 — GND 45 — BK3_IO20_LP189 AH191 46 — BK3_IO21_LP189 AG191 47 — BK3_IO22_LP190 AK201 48 — BK3_IO23_LP190 AJ201 49 — GND — 50 — GND — — — 1. Available on the ispXPGA 1200 only. 5 Lattice Semiconductor ispXPGA Evaluation Board User’s Guide Table 5. I/O Banks 6, 7 P6 (2mm) J28 (Mictor) 1 2 Description ispXPGA Pin Notes 1 GCLK6 R27 100Ω LVDS Receive Termination 2 GCLK7 R26 100Ω LVDS Receive Termination 3 — GND 4 — GND 5 3 BK6_IO0_INITB D26 6 4 BK6_IO1_CCLK C26 7 5 BK6_IO4_CSB D25 8 6 BK6_IO5_READ C25 9 7 BK6_IO8_LP350 F24 10 8 BK6_IO9_LP350 E24 — — 11 9 BK6_IO10_LP351 A25 12 10 BK6_IO11_LP351 B25 13 11 BK6_IO32_DATA7 F20 14 12 BK6_IO33_DATA6 E20 15 13 BK6_IO36_DATA5 F19 16 14 BK6_IO37_DATA4 E19 17 15 BK6_IO50_DATA3 F17 18 16 BK6_IO51_DATA2 E17 19 17 BK6_IO54_DATA1 B17 20 18 BK6_IO55_DATA0 A17 21 19 PGMF A28 10KΩ Resistor to VCCJ 22 20 DONE B28 Drives LED, See Figure 8. 23 21 CFG0 C27 10KΩ Resistor to VCCJ 24 22 25 - GND — 26 - GND — 27 23 BK7_IO34_LP430 A91 49.9Ω to VCCOD 28 24 BK7_IO35_LP430 1 49.9Ω to VCCOD 29 30 25 26 E10 1 BK7_IO33_LP429 B9 F10 BK7_IO36_LP432 1 49.9Ω to VCCOD 1 49.9Ω to VCCOD BK7_IO37_LP432 G10 1 24.9Ω in Series 31 27 BK7_IO38_LP433 A8 32 28 BK7_IO39_LP433 B81 24.9Ω in Series 33 29 BK7_IO40_LP434 D9 24.9Ω in Series 34 30 BK7_IO41_LP434 E9 24.9Ω in Series 35 31 BK7_IO42_LP435 A7 36 32 BK7_IO43_LP435 B7 37 33 BK7_IO44_LP439 C8 38 34 BK7_IO45_LP439 D8 39 35 BK7_IO48_LP448 E8 40 36 BK7_IO49_LP446 F8 41 37 BK7_IO50_LP447 C7 6 Lattice Semiconductor ispXPGA Evaluation Board User’s Guide Table 5. I/O Banks 6, 7 (Continued) P6 (2mm) J28 (Mictor) 42 38 BK7_IO51_LP447 Description ispXPGA Pin D7 43 — BK7_IO52_LP448 E7 44 — BK7_IO53_LP448 F7 45 — BK7_IO54_LP449 A5 46 — BK7_IO55_LP449 B5 47 — BK7_IO56_LP453 C6 48 — BK7_IO57_LP453 D6 49 — GND — 50 — GND — Notes 1. Available on the ispXPGA 1200 only Table 6. HSI SMA Connectors SMA Description ispXPGA Pin Notes J6 SS_CLK_IN_1P V29 100Ω LVDS Receive Termination J7 SS_CLK_IN_1N V30 100Ω LVDS Receive Termination J11 HSI7A_SINP N29 100Ω LVDS Receive Termination J10 HSI7A_SINN N30 100Ω LVDS Receive Termination J15 HSI7B_SINP L30 100Ω LVDS Receive Termination J14 HSI7B_SINN L29 100Ω LVDS Receive Termination J19 HSI8A_SINP L26 100Ω LVDS Receive Termination J18 HSI8A_SINN L25 100Ω LVDS Receive Termination J23 HSI8B_SINP H301 100Ω LVDS Receive Termination J22 HSI8B_SINN H291 100Ω LVDS Receive Termination 1 J8 HSI1A_SOUTP H1 J9 HSI1A_SOUTN H21 J12 HSI1B_SOUTP K1 J13 HSI1B_SOUTN K2 J16 HSI2A_SOUTP M1 J17 HSI2A_SOUTN M2 J20 HSI2B_SOUTP N1 J21 HSI2B_SOUTN N2 J5 SS_CLK_OUT_0P U2 J4 SS_CLK_OUT_0N U1 1. Available on the ispXPGA 1200 only. The topside of the board also contains a 14-pin header, which is suitable for connection to an LCD display. 5V Power and GND are provided in addition to 11 I/Os from the ispXPGA device. A contrast control is also available via a 20K-ohm potentiometer mounted near the header. A compatible display is the Optrex DMC16207 (or equivalent) 16x2 character LCD module. Table 7 lists the pin locations for this feature. 7 Lattice Semiconductor ispXPGA Evaluation Board User’s Guide Table 7. LCD Header P3 Description ispXPGA Pin 1 GND — 2 +5V — 3 Contrast — 4 BK7_IO13_LCD1 D13 5 BK7_IO14_LCD2 B13 6 BK7_IO15_LCD3 A13 7 BK7_IO16_LCD4 F13 8 BK7_IO17_LCD5 G13 9 BK7_IO18_LCD6 A12 10 BK7_IO19_LCD7 B12 11 BK7_IO20_LCD8 C121 12 BK7_IO21_LCD9 D121 13 BK7_IO22_LCDA A111 14 BK7_IO23_LCDB B111 1. Available on the ispXPGA 1200 only. Running the Sample Program The following example is shown with the ispXPGA 1200 device targeted. To target the ispXPGA 500 device, use the sample program for the ispXPGA 500 and follow the same procedure (selecting LFX500C as appropriate). Both sample programs are available for download from the Lattice web site at www.latticesemi.com/boards. Requirements • PC with Lattice ispVM System version 13.1 (or later) programming management software, installed with appropriate drivers (USB driver for USB Cable, Windows NT/2000/XP parallel port driver for ispDOWNLOAD Cable). Note: An option to install these drivers is included as part of the ispVM System setup. • ispDOWNLOAD Cable (pDS4102-DL2A, HW7265-DL3A or HW-USB-1A) This sample program consists of a 10-bit counter running from the on-board 20MHz oscillator. The sysCLOCK™ PLL adjusts the internal clock frequency to 70MHz. The 10-bit counter value is routed to output pins as well as a sysHSI™ block, where it is 10b12b encoded and serialized. The outputs for observation are listed in Table . Table 8. Sample Program Signal Locations Output Board Location 1 Function Counter[9] P3, pin 14 Counter[8] P3, pin 131 Counter[7] P3, pin 121 Counter[6] P3, pin 111 Counter[5] P3, pin 10 Counter[4] P3, pin 9 Counter[3] P3, pin 8 Counter[2] P3, pin 7 Counter[1] P3, pin 6 Counter[0] P3, pin 5 Counter LSB output cslock P3, pin 4 CSPLL Lock Indicator from sysHSI Block Counter MSB output 8 Lattice Semiconductor ispXPGA Evaluation Board User’s Guide Table 8. Sample Program Signal Locations (Continued) Output Board Location sout_p SMA J81 High-speed Serial Output, Positive Polarity (LVDS). sout_n SMA J91 High-speed Serial Output, Negative Polarity (LVDS). sout_p sout_n Function SMA J12 2 High-speed Serial Output, Positive Polarity (LVDS). SMA J13 2 High-speed Serial Output, Negative Polarity (LVDS). 1. ispXPGA 1200 only 2. ispXPGA 500 only Download Procedures 1. Connect the ispXPGA Evaluation Board to the AC adaptor or an external 5V supply. 2. Connect the ispDOWNLOAD cable to connector P2 to access the ispXPGA device. Pin 1 corresponds to VCC (red wire on cable). 3. Start the ispVM System software. 4. Click the ‘SCAN’ button located in the toolbar. The ispXPGA should be automatically detected. The resulting screen should be similar to Figure 3. Figure 3. ispVM System Interface 5. Double-click the device to open the properties dialog, as shown in Figure 4. In the device properties dialog, click the Browse button located under ‘Data File’. Locate the ‘demo.isc’ file. Click OK to both dialog boxes. 9 Lattice Semiconductor ispXPGA Evaluation Board User’s Guide Figure 4. Selecting the Data File 6. Click the green ‘GO’ button. This will begin the download process into the device. Once the download is complete, the counter outputs, CSLOCK signal, and high speed data should be viewable in the corresponding locations. Technical Support Assistance Hotline: 1-800-LATTICE (North America) +1-408-826-6002 (Outside North America) e-mail: techsupport@latticesemi.com Internet: www.latticesemi.com 10 D C B 1 FPG A _TD I FPG A _TD O FPG A _TCK FPG A _TM S R15 10K VCCPP VCCOD R17 10K VCCOC R18 10K C1 0.1 P1 R2 R7 R8 R9 VCCOB TP4 R203 R204 R205 R206 R202 2 VCCPP V5 0 0 0 0 0 R200 0 R28 10K TP5 TP6 TP7 TP8 TP9 0 VC CPMO N VC CJM O N VC COAM ON VC CO BM ON VC CO CM ON VC CODM O N NC _4 NC _8 NC _17 NC _18 IN _6 IN _7 EN U4 UT1 UT2 UT3 UT4 TPS77501PW P FB 15 R29 110K TP11 R26 0.1 3 4 TP13 R30 0.1 TP15 VCCJ Current Sense TP14 VCCP Current Sense TP12 D3 RED R5 301 VCCPP VCCJ VCCPP D4 RED R6 301 VCCPP 5 Date: File: B Size Titl e D5 RED R19 301 VCCPP D7 RED R21 301 VCCPP Number 6/18/2003 C :\wcn\.. \XPGA_Sheet01.SC HDO C 6 D8 RED R22 301 VCCPP Revision 6 Sheet1 of TB D D rawn By: Schemati c,XPGA Dem o Board D6 RED R20 301 VCCPP (LEDs light red to indicate input under threshold) VC CO B_LD O_EN F VC CO C_LD O_EN F VC COD_LDO_EN F RSTF_FRM _POW ER PA C VC COA_LDO_EN F VC C_LD O_EN F VC CP_LDO _ENF D2 RED R4 301 VCCPP 5 Power Manager Comparator Status LEDs Power Manager & VCCPP/VCCJLDO C6 10 16 R27 200K VCCJPP_LD O _RSTF C4 13 14 0.1 R24 RESET D1 RED R3 301 VCCO B_LD O_EN F VCCO C_LD O_EN F VCCO D_LDO_EN F RSTF_FRM _POW ER PA C VCCO A_LDO_EN F DN P 0 4 VCCPP 39 R23 C3 0.1 VCC_LD O_EN F VCCP _LDO _ENF P1_OU T P2_OU T P3_OU T P4_OU T P5_OU T P6_OU T P7_OU T P8_OU T TP10 PP_COM PP_COM PP_COM PP_COM PP_COM PP_COM PP_COM PP_COM C2 0.01 VCCPP 25 12 13 14 15 4 3 2 1 23 22 21 20 19 18 17 16 5 11 27 OU T_13 OU T_14 CR EF POR OU T5 OU T6 OU T7 OU T8 HVO HVO HVO HVO CO M P1 CO M P2 CO M P3 CO M P4 CO M P5 CO M P6 CO M P7 CO M P8 VDD VDD INP GND ispPAC-POW R1208-01T44I VM ON 1 VM ON 2 VM ON 3 VM ON 4 VM ON 5 VM ON 6 VM ON 7 VM ON 8 VM ON 9 VM ON 10 VM ON 11 VM ON 12 IN 1 IN 2 IN 3 IN 4 CLK RESET TDO TDI TM S TCK TRST U1 VCCP & VCCJ Regulation 4 8 17 18 6 7 5 32 33 34 35 36 37 38 40 41 42 43 44 6 7 8 9 26 10 28 30 31 24 29 R1 10K VCCPP 3 (Power Manager & JTAG Power – 3.35V nominal) C5 10uF R201 TP1 TP55 22.1 VCC PP_IN_1 PP_IN_2 PP_IN_3 PP_IN_4 R14 10K R10 PP_TDO VCCOA VCCJ VCCP TP3 1 2 3 4 (N C) 5 (K EY ) 6 7 8 VCCPP DN P DN P DN P DN P 2 ispPACPOWR1208 Power Supply Controller PP_IN_3 PP_IN_4 R16 10K SW 1 RESET Sw itch Power Manager/Chained JTAG ISP Header FPG A _TD I FPG A _TD O FPG A _TCK FPG A _TM S TSM -108-03-L-SV-P A 1 G N D _1 G N D _2 G N D _3 G N D _9 G N D _10 G N D _11 G N D _12 G N D _19 G N D _20 H EATTA B 11 1 2 3 9 10 11 12 19 20 21 D C B A Lattice Semiconductor ispXPGA Evaluation Board User’s Guide Appendix A. Schematics Figure 5. Lattice ispXPGA Evaluation Board Schematic D C B A J3 1 PJ-002BH -SM T 1 1 3 2 J1 2 D9 GR N R96 10K VCCP P VCCP _LDO _ENF V5 C9 10uF VCCP _LDO _ENF R41 DN P (1.8V Nominal) VCC Regulation C7 10uF VC CLDO IN V5 C11 10uF VCC OA_ LD O_EN F R47 DN P 4 8 17 18 6 7 5 4 8 17 18 6 7 5 NC _4 NC _8 NC _17 NC _18 IN _6 IN _7 EN U7 NC _4 NC _8 NC _17 NC _18 IN _6 IN _7 EN U6 IN EN U5 TPS77501PW P FB OU T_13 OU T_14 RESET FB OU T_13 OU T_14 RESET FB OU T TPS75501KTT TPS77501PW P 4 3 4 VCC, VCCP & VCCOA LDOs (2.55V Nominal) 2 1 R34 DN P VCCOA Regulation R97 10K VCCP P VCCO A_LDO_EN F (2.55V Nominal) R37 365 TP70 0 10K VCCP Regulation D11 6.0V V5 TP69 TP56 TP34 R11 R95 VCC_LD O_EN F VC CPP (4.5V to 5.5V) D10 SK 33-7 TP68 V5 VCC_LD O_EN F 3 DC Power Input BLACKBANJACK J2 RED BA N JA CK TP67 2 GN D H EATTA B 3 6 G N D _1 G N D _2 G N D _3 G N D _9 G N D _10 G N D _11 G N D _12 G N D _19 G N D _20 H EATTA B 1 2 3 9 10 11 12 19 20 21 GN D _1 GN D _2 GN D _3 GN D _9 GN D _10 GN D _11 GN D _12 GN D _19 GN D _20 HEATTA B 12 1 2 3 9 10 11 12 19 20 21 15 13 14 16 15 13 14 16 5 4 TP18 TP17 C12 10 C10 10 C8 100 R31 0.02 TP20 R38 0.1 TP22 R44 0.1 TP24 5 Date: File: B Size Titl e R48 110K R45 127K R42 110K R39 127K R35 30.1K R32 15.4K USER INSTALLABLE VOLTAGE SET RESISTORS R49 DN P R46 DN P VCCOA USER INSTALLABLE VOLTAGE SET RESISTORS R43 DN P R40 DN P VCCP USER INSTALLABLE VOLTAGE SET RESISTORS R36 DN P R33 DN P VCC 6/18/2003 C :\wcn\.. \XPGA_Sheet02.SC HDO C Number 6 Revision 6 Sheet2 of TBD D rawn By: Schemati c,XP GA Dem o Board VCCOA CURRENT SENSE TP23 VCCP CURRENT SENSE TP21 VCC CURRENT SENSE TP19 5 D C B A Lattice Semiconductor ispXPGA Evaluation Board User’s Guide Figure 6. Lattice ispXPGA Evaluation Board Schematic D C B A 127.0K 127.0K 1.8V 1.5V 1 127.0K 3.3V 110.0K 110.0K 110.0K R Fixed BOT 110.0K R Fixed BOT R Fixed TOP 40.2K 110.0K DNP R User TOP DNP DN P DN P 200.0 K R User BOT DN P User Installable Voltage Set Resistors R User BOT R User TOP 2 2 VCCOX LDO Adjustment R Fixed TOP 127.0 K VCCOX 2.5V TO LD O F B FR OM LDO O UTPU T 1 V5 C13 10uF VCCO B_LD O_EN F R53 DN P V5 C15 10uF VCCO C_LD O_EN F R59 DN P V5 C17 10uF VCC OD_LD O_EN F R65 DN P 4 8 17 18 6 7 5 4 8 17 18 6 7 5 4 8 17 18 6 7 5 NC _4 NC _8 NC _17 NC _18 IN _6 IN _7 EN U10 NC _4 NC _8 NC _17 NC _18 IN _6 IN _7 EN U9 NC _4 NC _8 NC _17 NC _18 IN _6 IN _7 EN U8 TPS77501PW P 4 TPS77501PW P TPS77501PW P FB OU T_13 OU T_14 RESET FB OU T_13 OU T_14 RESET FB OU T_13 OU T_14 RESET 15 13 14 16 15 13 14 16 15 13 14 16 TP27 TP26 TP25 3 4 VCCOB, VCCOC & VCCOD LDOs (2.55V Nominal) VCCOD Regulation R100 10K VCCP P VCCO D_LDO_EN F (2.55V Nominal) VCCOC Regulation R99 10K VCCP P VCCO C_LD O_EN F (2.55V Nominal) VCCOB Regulation R98 10K VCCP P VCCO B_LD O_EN F 3 G N D _1 G N D _2 G N D _3 G N D _9 G N D _10 G N D _11 G N D _12 G N D _19 G N D _20 H EATTA B 1 2 3 9 10 11 12 19 20 21 G N D _1 G N D _2 G N D _3 G N D _9 G N D _10 G N D _11 G N D _12 G N D _19 G N D _20 H EATTA B 1 2 3 9 10 11 12 19 20 21 GN D _1 GN D _2 GN D _3 GN D _9 GN D _10 GN D _11 GN D _12 GN D _19 GN D _20 HEATTA B 13 1 2 3 9 10 11 12 19 20 21 C18 10 C16 10 C14 10 R50 0.1 TP29 R56 0.1 TP31 R62 0.1 5 Date: File: B Size Titl e R66 110K R63 127K R60 110K R57 127K R54 110K R51 127K User Installable Voltage Set Resistors R67 DN P R64 DN P VCCOD User Installable Voltage Set Resistors R61 DN P R58 DN P VCCOC User Installable Voltage Set Resistors R55 DN P R52 DN P VCCOB 6/18/2003 C :\wcn\.. \XPGA_Sheet03.SC HDO C Number 6 Revision 6 Sheet3 of TB D D rawn By: Schematic,XP GA Dem o Board TP33 VCCOD Current Sense TP32 VCCOC Current Sense TP30 VCCOB Current Sense TP28 5 D C B A Lattice Semiconductor ispXPGA Evaluation Board User’s Guide Figure 7. Lattice ispXPGA Evaluation Board Schematic 14 D C B A VCCJ VCCJ C70 0.1 C48 0.1 1 C71 0.01 C47 0.01 6 2 3 2 4 Oscillators R88 DN P R87 110K VC C NC GN D U2 GN D VD D OU T OU T EN DN P OU T OE U12 20.000M H z 4 5 1 3 R90 1 R89 10K VCCJ USER INSTALLABLE VREF MOD RESISTORS R85 DN P R84 110K VCCO D R81 DN P R80 110K VCCO D R77 DN P R76 110K VCCO C R75 DN P R74 110K VCCO C R73 DN P VCCO B R71 DN P R69 DN P VCCO A R72 110K VCCO B R70 110K R68 110K VCCO A 1 22.1 2 2 D12 GRN DO NE 1 2 3 4 5 6 7 8 GC LK6_DIFF GC LK7_DIFF TP35 GC LK2 GC LK3 GC LK0 PGM F CFG 0 FPG A _TM S FPG A _TCK FPGA _TD I FPG A _TD O TSM -108-03-L-SV-P VCCJ TP36 DX P DX N 100 R101 100 R78 10K R12 AK2 8 AK3 AJ28 AH2 7 R3 R4 T4 T5 T28 T27 R27 R26 A28 C27 B28 R79 10K VCCO 7_C10 VCCO 7_E13 VC CO 7_K11 VCCO 7_L12 VCCO 7_L13 VCCO 7_L14 VCCO 7_L15 VCCO 7_M 15 VCCO 6_C21 VCCO 6_E18 VC CO 6_K20 VCCO 6_L16 VCCO 6_L17 VCCO 6_L18 VCCO 6_L19 VCCO 6_M 16 VC CO 5_K28 VCCO 5_L21 VCCO 5_M 20 VC CO 5_N20 VC CO 5_N26 VCCO 5_P20 VCCO 5_R19 VCCO 5_R20 VCCO 4_AA28 VCCO 4_T19 VCCO 4_T20 VC CO 4_U20 VC CO 4_V20 VC CO 4_V26 VCCO 4_W 20 VC CO 4_Y21 VCCO 3_AA20 VCCO 3_AF18 VCCO 3_AH21 VCCO 3_W 16 VC CO 3_Y16 VC CO 3_Y17 VC CO 3_Y18 VC CO 3_Y19 VCCO 2_AA11 VCCO 2_AF13 VCCO 2_AH10 VCCO 2_W 15 VC CO 2_Y12 VC CO 2_Y13 VC CO 2_Y14 VC CO 2_Y15 VCCO 1_AA 3 VCCO 1_T11 VC C01_T12 VC CO 1_U11 VC CO 1_V11 VCCO 1_V5 VCCO 1_W 11 VC CO 1_Y10 VCCO 0_K3 VCCO 0_L10 VCCO 0_M 11 VC CO 0_N11 VCCO 0_N5 VCCO 0_P11 VCCO 0_R11 VCCO 0_R12 LFX1200C-XXF900X XPGA “System” & I/O PWR Pins RESET TO E DX P DX N GC LK0 GC LK1 GC LK2 GC LK3 GC LK4 GC LK5 GC LK6 GC LK7 PROGRA M CFG 0 DO NE TD O TD I TM S TC K VR EF6_BK 6_IO 12_LP356 VR EF7_BK 7_IO 47_LP441 VR EF4_BK 4_IO 12_LP236 VR EF5_BK 5_IO 48_LP333 VR EF2_BK 2_IO 12_LP128 VR EF3_BK 3_IO 49_LP213 VR EF0_BK 0_IO 12_LP8 VR EF1_BK 1_IO 49_LP105 U11D 4 C10 E13 K11 L12 L13 L14 L15 M 15 C21 E18 K20 L16 L17 L18 L19 M 16 K28 L21 M 20 N20 N26 P20 R19 R20 AA2 8 T19 T20 U20 V2 0 V2 6 W 20 Y2 1 AA2 0 AF18 AH2 1 W 16 Y1 6 Y1 7 Y1 8 Y1 9 AA1 1 AF13 AH1 0 W 15 Y1 2 Y1 3 Y1 4 Y1 5 AA3 T11 T12 U11 V1 1 V5 W 11 Y1 0 K3 L10 M 11 N11 N5 P11 R11 R12 C49 0.01 C43 0.01 C39 0.01 C35 0.01 C31 0.01 C27 0.01 C23 0.01 C19 0.01 3 4 Oscillator & ispXPGA System Pins 10K RSTF_FRM _POW ER PA C TP2 TP16 A3 C4 AJ3 AH4 VCCJ VCCJ R102 FPG A _TD O FPG A _TD I FPG A _TM S FPG A _TCK GC LK0 GC LK1 GC LK2 GC LK3 GC LK4_DIFF GC LK5_DIFF GC LK6_DIFF GC LK7_DIFF PGM F CFG 0 DO NE (N C) (K EY ) VCCJ RSTF_FRM _POW ER PA C R82 301 VC CJ JTAG ISP HEADER P2 D24 B6 XP GA _VREF2 XP GA _VREF3 AD2 7 H25 XP GA _VREF1 G6 AD6 AE8 AG2 4 XP GA _VREF0 3 C50 0.01 C44 0.01 C40 0.01 C36 0.01 C32 0.01 C28 0.01 C24 0.01 C20 0.01 C26 0.01 C22 0.01 C34 0.01 C30 0.01 C42 0.01 C38 0.01 C51 0.01 C45 0.01 5 Date: File: B Size Titl e C52 0.01 C46 0.01 VCCO D C41 0.01 C37 0.01 VCCO C C33 0.01 C29 0.01 VCCO B C25 0.01 C21 0.01 VCCO A 5 6/18/2003 C :\wcn\.. \XPGA_Sheet04.SC HDO C Number Revision 6 Sheet4 of TBD D rawn By: Schemati c,XP GA Dem o Board 6 D C B A Lattice Semiconductor ispXPGA Evaluation Board User’s Guide Figure 8. Lattice ispXPGA Evaluation Board Schematic 15 D C B A 1 1 R24 R25 AA6 AA7 AA8 AA9 AB 8 AC 7 T6 T7 T8 T9 T10 U7 U8 U9 U10 V8 V9 V1 0 W7 W8 W9 W 10 Y7 Y8 Y9 H5 H6 H7 J8 K6 K7 K8 K9 L7 L8 L9 M7 M8 M9 M 10 N8 N9 N10 P7 P8 P9 P10 R8 R9 R10 E25 E26 F22 F25 G16 NC _G 17 NC _G 19 NC _G 20 NC _G 22 NC _G 23 NC _G 24 NC _H 16 NC _H 17 NC _H 18 NC _H 19 NC _H 20 NC _H 21 NC _H 22 NC _H 23 NC _J16 NC _J17 NC _J18 NC _J19 NC _J20 NC _J21 NC _J22 NC _K 16 NC _K 17 NC _K 18 NC _K 19 NC _K 21 NC _E5 NC _E6 NC _F6 NC _F9 NC _G 11 NC _G 12 NC _G 14 NC _G 15 NC _G 7 NC _G 8 NC _G 9 NC _H 8 NC _H 9 NC _H 10 NC _H 11 NC _H 12 NC _H 13 NC _H 14 NC _H 15 NC _J9 NC _J10 NC _J11 NC _J12 NC _J13 NC _J14 NC _J15 NC _K 10 NC _K 12 NC _K 13 NC _K 14 NC _K 15 LF X1200C-XXF900X NCs 1/2 NC _R24 NC _R25 NC _A A6 NC _A A7 NC _A A8 NC _A A9 NC _A B8 NC _A C7 NC _T6 NC _T7 NC _T8 NC _T9 NC _T10 NC _U 7 NC _U 8 NC _U 9 NC _U 10 NC _V 8 NC _V 9 NC _V 10 NC _W 7 NC _W 8 NC _W 9 NC _W 10 NC _Y 7 NC _Y 8 NC _Y 9 NC _H 5 NC _H 6 NC _H 7 NC _J8 NC _K 6 NC _K 7 NC _K 8 NC _K 9 NC _L7 NC _L8 NC _L9 NC _M 7 NC _M 8 NC _M 9 NC _M 10 NC _N 8 NC _N 9 NC _N 10 NC _P7 NC _P8 NC _P9 NC _P10 NC _R8 NC _R9 NC _R10 NC _E25 NC _E26 NC _F22 NC _F25 NC _G 16 U11C 2 2 G17 G19 G20 G22 G23 G24 H16 H17 H18 H19 H20 H21 H22 H23 J16 J17 J18 J19 J20 J21 J22 K16 K17 K18 K19 K21 E5 E6 F6 F9 G11 G12 G14 G15 G7 G8 G9 H8 H9 H10 H11 H12 H13 H14 H15 J9 J10 J11 J12 J13 J14 J15 K10 K12 K13 K14 K15 LFX1200C-XXF900X GN D_A1 GN D_A2 GN D_A2 9 GN D_A3 0 GN D_AB 28 GN D_AB 3 GN D_AG 27 GN D_AG 4 GN D_AH2 2 GN D_AH2 8 GN D_AH3 GN D_AH9 GN D_AJ1 GN D_AJ2 GN D_AJ29 GN D_AJ30 GN D_AK1 GN D_AK2 GN D_AK2 9 GN D_AK3 0 GN D_B1 GN D_B2 GN D_B29 GN D_B30 GN D_C22 GN D_C28 GN D_C3 GN D_C9 GN D_D27 GN D_D4 GN D_J28 GN D_J3 GN D_N13 GN D_N14 GN D_N15 GN D_N16 GN D_N17 GN D_N18 GN D_P13 GN D_P14 GN D_P15 GN D_P16 GN D_P17 GN D_P18 GN D_R13 GN D_R14 GN D_R15 GN D_R16 GN D_R17 GN D_R18 GN D_T1 3 GN D_T1 4 GN D_T1 5 U11A GN D_T16 GN D_T17 GN D_T18 GN D_U13 GN D_U14 GN D_U15 GN D_U16 GN D_U17 GN D_U18 GN D_V1 3 GN D_V1 4 GN D_V1 5 GN D_V1 6 GN D_V1 7 GN D_V1 8 GN DP_R28 GN DP_T3 VCCP _R5 VCCP _T26 VCCJ VC C_L11 VC C_L20 VC C_M 12 VC C_M 13 VC C_M 14 VC C_M 17 VC C_M 18 VC C_M 19 VCC_N 12 VCC_N 19 VC C_P12 VC C_P19 VCC_U 12 VCC_U 19 VCC_V12 VCC_V19 VC C_W 12 VC C_W 13 VC C_W 14 VC C_W 17 VC C_W 18 VC C_W 19 VCC_Y11 VCC_Y20 T16 T17 T18 U13 U14 U15 U16 U17 U18 V1 3 V1 4 V1 5 V1 6 V1 7 V1 8 R28 T3 R5 T26 B3 L11 L20 M 12 M 13 M 14 M 17 M 18 M 19 N12 N19 P12 P19 U12 U19 V1 2 V1 9 W 12 W 13 W 14 W 17 W 18 W 19 Y1 1 Y2 0 C66 0.01 C65 0.01 VC CJ C62 0.01 C58 0.01 C57 0.01 C61 0.01 C54 0.01 C53 0.01 4 0 C67 0.01 R25 3 4 C64 0.01 C60 0.01 C56 0.01 0 VC C VC C VC C R13 C63 0.01 C59 0.01 C55 0.01 XPGA Power & NC Sections CORE, JTAG and PLL PWR A1 A2 A29 A30 AB 28 AB 3 AG 27 AG4 AH 22 AH 28 AH3 AH9 AJ1 AJ2 AJ29 AJ30 AK1 AK2 AK 29 AK 30 B1 B2 B29 B30 C22 C28 C3 C9 D27 D4 J28 J3 N13 N14 N15 N16 N17 N18 P13 P14 P15 P16 P17 P18 R13 R14 R15 R16 R17 R18 T13 T14 T15 3 VC CP VC CP 5 5 Date: File: B Size Titl e NC _A F26 NC _A A10 NC _A A12 NC _A A13 NC _A A14 NC _A A15 NC _A B10 NC _A B11 NC _A B12 NC _A B13 NC _A B14 NC _A B15 NC _A B9 NC _A C10 NC _A C11 NC _A C12 NC _A C13 NC _A C14 NC _A C15 NC _A C8 NC _A C9 NC _A D11 NC _A D12 NC _A D14 NC _A D15 NC _A D7 NC _A D8 NC _A D9 NC _A E6 NC _A E9 NC _A F5 NC _A F6 NC _H 24 NC _J23 NC _K 22 NC _K 23 NC _K 24 NC _K 25 NC _L22 NC _L23 NC _L24 NC _M 21 NC _M 22 NC _M 23 NC _M 24 NC _N 21 NC _N 22 NC _N 23 NC _P21 NC _P22 NC _P23 NC _P24 NC _R21 NC _R22 NC _R23 LF X1200C-XXF900X NCs 2/2 NC _A A22 NC _A A23 NC _A A24 NC _A A25 NC _A B23 NC _A C24 NC _T21 NC _T22 NC _T23 NC _T24 NC _T25 NC _U 21 NC _U 22 NC _U 23 NC _U 24 NC _V 21 NC _V 22 NC _V 23 NC _W 21 NC _W 22 NC _W 23 NC _W 24 NC _Y 22 NC _Y 23 NC _Y 24 NC _A A16 NC _A A17 NC _A A18 NC _A A19 NC _A A21 NC _A B15 NC _A B16 NC _A B17 NC _A B18 NC _A B19 NC _A B20 NC _A B21 NC _A C16 NC _A C17 NC _A C18 NC _A C19 NC _A C20 NC _A C21 NC _A C22 NC _A C23 NC _A D16 NC _A D17 NC _A D19 NC _A D20 NC _A D22 NC _A D23 NC _A D24 NC _A E22 NC _A E25 NC _A F25 U11B Number 6/18/2003 C :\wcn\.. \XPGA_Sheet05.SC HDO C 6 Sheet5 of TB D D rawn By: Revision AF26 AA1 0 AA1 2 AA1 3 AA1 4 AA1 5 AB 10 AB 11 AB 12 AB 13 AB 14 AB 15 AB 9 AC 10 AC 11 AC 12 AC 13 AC 14 AC 15 AC 8 AC 9 AD1 1 AD1 2 AD1 4 AD1 5 AD7 AD8 AD9 AE6 AE9 AF5 AF6 H24 J23 K22 K23 K24 K25 L22 L23 L24 M 21 M 22 M 23 M 24 N21 N22 N23 P21 P22 P23 P24 R21 R22 R23 Schemati c,XPGA Dem o Board AA2 2 AA2 3 AA2 4 AA2 5 AB 23 AC 24 T21 T22 T23 T24 T25 U21 U22 U23 U24 V2 1 V2 2 V2 3 W 21 W 22 W 23 W 24 Y2 2 Y2 3 Y2 4 AA1 6 AA1 7 AA1 8 AA1 9 AA2 1 AB 16 AB 17 AB 18 AB 19 AB 20 AB 21 AB 22 AC 16 AC 17 AC 18 AC 19 AC 20 AC 21 AC 22 AC 23 AD1 6 AD1 7 AD1 9 AD2 0 AD2 2 AD2 3 AD2 4 AE22 AE25 AF25 6 D C B A Lattice Semiconductor ispXPGA Evaluation Board User’s Guide Figure 9. Lattice ispXPGA Evaluation Board Schematic 16 D C B A 1 1 J8 J9 J21 SM A J20 SM A TP41 TP42 TP43 TP44 TP39 TP40 HSI2B_SOUT P HSI2B_SOUT N HSI2A_SO UTP HSI2A_SO UTN HSI1B_SOUT P HSI1B_SOUT N HSI1A_SO UTP HSI1A_SO UTN D3 E3 C2 C1 E4 F5 D2 D1 F4 F3 E2 E1 G5 F1 F2 G4 G3 G2 G1 H3 H4 H1 H2 J7 J6 J1 J2 J4 J5 K1 K2 K5 K4 L1 L2 L6 L5 M1 M2 L3 L4 M6 M5 M4 M3 N1 N2 N7 N6 P1 P2 N3 N4 P6 P5 P3 P4 R7 R6 R1 R2 BK 0_IO 0_LP0 BK 0_IO 1_LP0 BK 0_IO 2_LP1 BK 0_IO 3_LP1 BK 0_IO 4_LP2 BK 0_IO 5_LP2 BK 0_IO 6_HSI0ASO U TP_LP5 BK 0_IO 7_HSI0ASO U TN_LP5 BK 0_IO 8_LP6 BK 0_IO 9_LP6 BK 0_IO 10_HSI0ASIN P_LP 7 BK 0_IO 11_HSI0ASIN N_LP7 BK 0_IO 13_LP8 BK 0_IO 14_HSI0BSOU TP_LP9 BK 0_IO 15_HSI0BSOU TN _LP9 BK 0_IO 16_LP10 BK 0_IO 17_LP10 BK 0_IO 18_HSI0BSIN P_LP 11 BK 0_IO 19_HSI0BSIN N_LP12 BK 0_IO 20_LP12 BK 0_IO 21_LP12 BK 0_IO 22_HSI1ASOUTP_LP13 BK 0_IO 23_HSI1ASOUTN _LP 13 BK 0_IO 24_LP14 BK 0_IO 25_LP15 BK 0_IO 26_HSI1ASIN P_LP 15 BK 0_IO 27_HSI1ASIN N_LP15 BK 0_IO 28_LP16 BK 0_IO 29_LP16 BK 0_IO 30_HSI1BSOU TP_LP17 BK 0_IO 31_HSI1BSOU TN _LP17 BK 0_IO 32_LP18 BK 0_IO 33_LP18 BK 0_IO 34_HSI1BSIN P_LP 19 BK 0_IO 35_HSI1BSIN N_LP19 BK 0_IO 36_LP20 BK 0_IO 37_LP20 BK 0_IO 38_HSI2ASOUTP_LP37 BK 0_IO 39_HSI2ASOUTN _LP 37 BK 0_IO 39_LP38 BK 0_IO 40_LP38 BK 0_IO 42_HSI2ASIN P_LP 39 BK 0_IO 43_HSI2ASIN N_LP39 BK 0_IO 44_LP40 BK 0_IO 45_LP41 BK 0_IO 46_HSI2BSOU TP_LP41 BK 0_IO 47_HSI2BSOU TN _LP41 BK 0_IO 48_LP42 BK 0_IO 49_LP42 BK 0_IO 50_HSI2BSIN P_LP 43 BK 0_IO 51_HSI2BSIN N_LP43 BK 0_IO 52_LP44 BK 0_IO 53_LP44 BK 0_IO 54_PLLR ST0_LP53 BK 0_IO 55_PLLR ST1_LP53 BK 0_IO 56_LP54 BK 0_IO 57_LP54 BK 0_IO 58_PLLFBK 0_LP55 BK 0_IO 59_PLLFBK 1_LP55 BK 0_IO 60_CLK OUT0_LP 56 BK 0_IO 61_CLK OUT1_LP 56 U11E 3 BK 1_IO 0_CLKO UT2_LP57 BK 1_IO 1_CLKO UT3_LP57 BK 1_IO 2_SSCL KOUT 0P_LP58 BK 1_IO 3_SSCLKOU T0N_LP58 BK 1_IO 4_PLLF BK 2_LP59 BK 1_IO 5_PLLF BK 3_LP59 BK 1_IO 6_SSCLKIN0P_LP60 BK 1_IO 7_SSC LKIN 0N _LP60 BK 1_IO 8_LP69 BK 1_IO 9_LP69 BK 1_IO 10_LP70 BK 1_IO 11_LP70 BK 1_IO 12_PLLR ST2_LP71 BK 1_IO 13_PLLR ST3_LP71 BK 1_IO 14_LP72 BK 1_IO 15_LP72 BK 1_IO 16_LP73 BK 1_IO 17_LP73 BK 1_IO 18_LP74 BK 1_IO 19_LP74 BK 1_IO 20_LP75 BK 1_IO 21_LP75 BK 1_IO 22_LP76 BK 1_IO 23_LP76 BK 1_IO 24_LP93 BK 1_IO 25_LP93 BK 1_IO 26_HSI3ASO UTP_LP94 BK 1_IO 27_HSI3ASOUTN_LP94 BK 1_IO 28_LP95 BK 1_IO 29_LP95 BK 1_IO 30_HSI3ASIN P_LP96 BK 1_IO 31_HSI3ASINN _LP96 BK 1_IO 32_LP97 BK 1_IO 33_LP97 BK 1_IO 34_HSI3BSO UTP_LP98 BK 1_IO 35_HSI3BSOU TN _LP98 BK 1_IO 36_LP99 BK 1_IO 37_LP99 BK 1_IO 38_HSI3BSIN P_LP 100 BK 1_IO 39_HSI3BSINN_LP 100 BK 1_IO 40_LP101 BK 1_IO 41_LP101 BK 1_IO 42_HSI4ASOUTP_LP 102 BK 1_IO 43_HSI4ASOU TN _LP102 BK 1_IO 44_LP103 BK 1_IO 45_LP103 BK 1_IO 46_HSI4ASIN P_LP 104 BK 1_IO 47_HSI4ASIN N_LP 104 BK 1_IO 48_LP105 BK 1_IO 50_HSI4BSOU TP_LP106 BK 1_IO 51_HSI4BSO U TN_LP106 BK 1_IO 52_LP107 BK 1_IO 53_LP107 BK 1_IO 54_HSI4BSIN P_LP 108 BK 1_IO 55_HSI4BSINN_LP 108 BK 1_IO 56_LP111 BK 1_IO 57_LP111 BK 1_IO 58_LP112 BK 1_IO 59_LP112 BK 1_IO 60_LP113 BK 1_IO 61_LP113 LF X1200C-XXF900X 4 T2 T1 U2 U1 U3 U4 V1 V2 U5 U6 V4 V3 V6 V7 W1 W2 W3 W4 W5 W6 Y6 Y5 Y4 Y3 AA5 AA4 Y2 Y1 AB 7 AB 6 AA2 AA1 AB 5 AB 4 AB 2 AB 1 AC 6 AC 5 AC 2 AC 1 AC 4 AC 3 AD2 AD1 AD3 AD4 AE2 AE1 AD5 AF2 AF1 AE3 AE4 AG1 AG2 AE5 AF4 AH1 AH2 AF3 AG3 TP53 TP54 TP37 TP38 SS_CLK_O UT_0P SS_CLK_O UT_0N 2 3 4 XPGA I/O Banks 0, 1 (HSI/Source Synchronous Out) J17 SM A J16 SM A J13 SM A J12 SM A SM A SM A 2 5 Date: File: B Size 6/18/2003 C :\wcn\.. \XPGA_Sheet06.SC HDO C Number 6 Revision 6 Sheet6 of TB D D rawn By: Schemati c,XPGA Dem o Board SM A SM A Titl e J5 J4 5 D C B A Lattice Semiconductor ispXPGA Evaluation Board User’s Guide Figure 10. Lattice ispXPGA Evaluation Board Schematic 17 D C B A AG5 AH5 AJ4 AK4 AG6 AH6 AJ5 AK5 AE7 AF7 AG7 AH7 AF8 AJ6 AK6 AG8 AH8 AJ7 AK7 AF9 AG9 AJ8 AK8 AD1 0 AE10 AJ9 AK9 AF10 AG1 0 AK1 0 AJ10 AE11 AF11 AG1 1 AH1 1 AE12 AF12 AJ11 AK1 1 AG1 2 AH1 2 AK1 2 AJ12 AD1 3 AE13 AK1 3 AJ13 AG1 3 AH1 3 AE14 AF14 AG1 4 AH1 4 AJ14 AK1 4 AE15 AF15 AG1 5 AH1 5 AJ15 AK1 5 1 BK 3_IO 0_LP172 BK 3_IO 1_LP172 BK 3_IO 2_LP173 BK 3_IO 3_LP173 BK 3_IO 4_LP174 BK 3_IO 5_LP174 BK 3_IO 6_LP175 BK 3_IO 7_LP175 BK 3_IO 8_LP178 BK 3_IO 9_LP178 BK 3_IO 10_LP179 BK 3_IO 11_LP179 BK 3_IO 12_LP180 BK 3_IO 13_LP180 BK 3_IO 14_LP182 BK 3_IO 15_LP182 BK 3_IO 16_LP187 BK 3_IO 17_LP187 BK 3_IO 18_LP188 BK 3_IO 19_LP188 BK 3_IO 20_LP189 BK 3_IO 21_LP189 BK 3_IO 22_LP190 BK 3_IO 23_LP190 BK 3_IO 24_LP191 BK 3_IO 25_LP191 BK 3_IO 26_LP193 BK 3_IO 27_LP193 BK 3_IO 28_LP197 BK 3_IO 29_LP197 BK 3_IO 30_LP198 BK 3_IO 31_LP198 BK 3_IO 32_LP200 BK 3_IO 33_LP200 BK 3_IO 34_LP201 BK 3_IO 35_LP201 BK 3_IO 36_LP202 BK 3_IO 37_LP202 BK 3_IO 38_LP205 BK 3_IO 39_LP205 BK 3_IO 40_LP206 BK 3_IO 41_LP206 BK 3_IO 42_LP207 BK 3_IO 43_LP207 BK 3_IO 44_LP209 BK 3_IO 45_LP209 BK 3_IO 46_LP212 BK 3_IO 47_LP212 BK 3_IO 48_LP213 BK 3_IO 50_LP220 BK 3_IO 51_LP220 BK 3_IO 52_LP221 BK 3_IO 53_LP221 BK 3_IO 54_LP222 BK 3_IO 55_LP222 BK 3_IO 56_LP225 BK 3_IO 57_LP225 BK 3_IO 58_LP226 BK 3_IO 59_LP226 BK 3_IO 60_LP227 BK 3_IO 61_LP227 LFX1200C-X XF900X XPGA I/O Banks 2, 3 BK 2_IO 0_LP116 BK 2_IO 1_LP116 BK 2_IO 2_LP117 BK 2_IO 3_LP117 BK 2_IO 4_LP118 BK 2_IO 5_LP118 BK 2_IO 6_LP121 BK 2_IO 7_LP121 BK 2_IO 8_LP122 BK 2_IO 9_LP122 BK 2_IO 10_LP123 BK 2_IO 11_LP123 BK 2_IO 13_LP128 BK 2_IO 14_LP129 BK 2_IO 15_LP129 BK 2_IO 16_LP134 BK 2_IO 17_LP134 BK 2_IO 18_LP135 BK 2_IO 19_LP135 BK 2_IO 20_LP136 BK 2_IO 21_LP136 BK 2_IO 22_LP137 BK 2_IO 23_LP137 BK 2_IO 24_LP140 BK 2_IO 25_LP140 BK 2_IO 26_LP141 BK 2_IO 27_LP141 BK 2_IO 28_LP143 BK 2_IO 29_LP143 BK 2_IO 30_LP144 BK 2_IO 31_LP144 BK 2_IO 32_LP145 BK 2_IO 33_LP145 BK 2_IO 34_LP148 BK 2_IO 35_LP148 BK 2_IO 36_LP149 BK 2_IO 37_LP149 BK 2_IO 38_LP150 BK 2_IO 39_LP150 BK 2_IO 40_LP151 BK 2_IO 41_LP151 BK 2_IO 42_LP152 BK 2_IO 43_LP152 BK 2_IO 44_LP153 BK 2_IO 45_LP153 BK 2_IO 46_LP160 BK 2_IO 47_LP160 BK 2_IO 48_LP161 BK 2_IO 49_LP161 BK 2_IO 50_LP162 BK 2_IO 51_LP162 BK 2_IO 52_LP163 BK 2_IO 53_LP163 BK 2_IO 54_LP166 BK 2_IO 55_LP166 BK 2_IO 56_LP167 BK 2_IO 57_LP167 BK 2_IO 58_LP168 BK 2_IO 59_LP168 BK 2_IO 60_LP169 BK 2_IO 61_LP169 U11F 2 3 4 GC LK2 GC LK3 GC LK2 GC LK3 3 4 XPGA I/O Banks 2, 3 & Headers BK 3_IO 0_LP172_LVD T_B AK 16 AJ16 BK 3_IO 1_LP172_LVD T_B BK 3_IO 2_LP173_LVD T_B AH 16 AG 16 BK 3_IO 3_LP173_LVD T_B AF16 BK 3_IO 4_LP 174_LVD T_B BK 3_IO 5_LP 174_LVD T_B AE16 BK 3_IO 6_LP 175_LVD T_B AK 17 BK 3_IO 7_LP 175_LV DT_B AJ17 BK 3_IO 8_LP 178_LV DT_B AH 17 BK 3_IO 9_LP 178_LV DT_B AG 17 BK 3_IO 10_LP179_LVDT _B AF17 BK 3_IO 11_LP179_LVDT _B AE17 BK 3_IO 12_LP180_LVDT _B AH 18 BK 3_IO 13_LP180_LVDT _B AG 18 BK 3_IO 14_LP182_LVDT _B AJ18 BK 3_IO 15_LP182_LVDT _B AK 18 BK 3_IO 16_LP187_LVDT _B AE18 BK 3_IO 17_LP187_LVDT _B AD 18 AJ19 AK 19 BK 3_IO 20_LP189 AH 19 BK 3_IO 21_LP189 AG 19 BK 3_IO 22_LP190 AK 20 BK 3_IO 23_LP190 AJ20 AF19 AE19 AH 20 AG 20 AF20 AE20 AJ21 AK 21 AG 21 AF21 RSTF_FRM _POW ER PA C RSTF_FRM _POW ER PA C AK 22 AJ22 AE21 AD 21 AG 22 AF22 AG 23 AH 23 AJ23 AK 23 AF23 AE23 AJ24 AK 24 AH 24 AJ25 AK 25 AF24 PP_IN _3 AE24 PP_IN_3 PP_IN _4 AK 26 PP_IN_4 AJ26 AH 25 AG 25 AK 27 TP46 AJ27 TP48 AG 26 TP50 AH 26 TP52 *See Figure 14 for LVDS, TX, RX Terminations 2 *Bank2, 3 signals with "LVD" in the netname are routed as controlled impedance differential pairs. TP45 TP47 TP49 TP51 BK 2_IO 14_LP129_LVDR BK 2_IO 15_LP129_LVDR BK 2_IO 16_LP134_LVDR BK 2_IO 17_LP134_LVDR BK 2_IO 18_LP135_LVDR BK 2_IO 19_LP135_LVDR BK 2_IO 0_LP116_LV DR BK 2_IO 1_LP116_LV DR BK 2_IO 2_LP117_LV DR BK 2_IO 3_LP117_LV DR BK 2_IO 4_LP118_LV DR BK 2_IO 5_LP118_LV DR BK 2_IO 6_LP121_LV DR BK 2_IO 7_LP121_LV DR BK 2_IO 8_LP122_LV DR BK 2_IO 9_LP122_LV DR BK 2_IO 10_LP123_LVDR BK 2_IO 11_LP123_LVDR 1 22.1 22.1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 P4 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 BK 3_IO 21_LP189 BK 3_IO 23_LP190 BK 2_IO 10_LP123_LVDR BK 2_IO 11_LP123_LVDR BK 2_IO 4_LP118_LV DR BK 2_IO 5_LP118_LV DR BK 2_IO 6_LP121_LV DR BK 2_IO 7_LP121_LV DR BK 2_IO 8_LP122_LV DR BK 2_IO 9_LP122_LV DR BK 3_IO 14_LP182_LVDT BK 3_IO 15_LP182_LVDT BK 3_IO 8_LP178_LV DT BK 3_IO 9_LP178_LV DT BK 3_IO 0_LP172_LV DT BK 3_IO 1_LP172_LV DT BK 3_IO 4_LP174_LV DT BK 3_IO 5_LP174_LV DT BK 2_IO 16_LP134_LVDR BK 2_IO 17_LP134_LVDR 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 J26 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 BK 3_IO 14_LP182_LVDT BK 3_IO 15_LP182_LVDT BK 3_IO 8_LP178_LVD T BK 3_IO 9_LP178_LVD T BK 3_IO 0_LP172_LVD T BK 3_IO 1_LP172_LVD T BK 3_IO 4_LP174_LVD T BK 3_IO 5_LP174_LVD T BK 2_IO 16_LP134_LVDR BK 2_IO 17_LP134_LVDR BK 2_IO 10_LP123_LVDR BK 2_IO 11_LP123_LVDR BK 2_IO 4_LP118_LVD R BK 2_IO 5_LP118_LVD R BK 2_IO 6_LP121_LVD R BK 2_IO 7_LP121_LVD R BK 2_IO 3_LP117_LV DR 5 Date: File: B Size Titl e 6/18/2003 C :\wcn\.. \XPGA_Sheet07.SC HDO C Number 6 Revision 6 Sheet7 of TB D D rawn By: Schemati c,XPGA Demo Board Mictor Header – I/O Banks 2, 3 BK 3_IO 12_LP180_LVDT BK 3_IO 13_LP180_LVDT BK 3_IO 10_LP179_LVDT BK 3_IO 11_LP179_LVDT BK 3_IO 6_LP175_LV DT BK 3_IO 7_LP175_LV DT BK 3_IO 2_LP173_LV DT BK 3_IO 3_LP173_LV DT BK 3_IO 16_LP187_LVDT BK 3_IO 17_LP187_LVDT BK 2_IO 0_LP116_LV DR BK 2_IO 1_LP116_LV DR BK 2_IO 18_LP135_LVDR BK 2_IO 19_LP135_LVDR BK 2_IO 14_LP129_LVDR BK 2_IO 15_LP129_LVDR BK 2_IO 2_LP117_LV DR GC LK2 GC LK3 2 mm Header – I/O Banks 2, 3 BK 3_IO 20_LP189 BK 3_IO 22_LP190 BK 2_IO 0_LP116_LV DR BK 2_IO 1_LP116_LV DR BK 2_IO 18_LP135_LVDR BK 2_IO 19_LP135_LVDR BK 2_IO 14_LP129_LVDR BK 2_IO 15_LP129_LVDR BK 2_IO 2_LP117_LV DR BK 2_IO 3_LP117_LV DR BK 3_IO 12_LP180_LVDT BK 3_IO 13_LP180_LVDT BK 3_IO 10_LP179_LVDT BK 3_IO 11_LP179_LVDT BK 3_IO 6_LP175_LV DT BK 3_IO 7_LP175_LVD T BK 3_IO 2_LP173_LV DT BK 3_IO 3_LP173_LVD T BK 3_IO 16_LP187_LVDT BK 3_IO 17_LP187_LVDT GC LK2 R92 GC LK3 R93 5 MIS-019-01-L-D G1 G2 G3 G4 G5 D C B A Lattice Semiconductor ispXPGA Evaluation Board User’s Guide Figure 11. Lattice ispXPGA Evaluation Board Schematic 18 D C B A 1 1 J6 SM A J7 SM A R105 100 TP65 TP66 TP63 TP64 TP61 TP62 AG2 8 AF27 AF28 AE26 AE27 AE28 AH3 0 AH2 9 AD2 5 AD2 6 AG2 9 AG3 0 AD2 8 AF29 AF30 AC 25 AC 26 AE29 AE30 AC 28 AC 27 AD2 9 AD3 0 AB 24 AB 25 AC 29 AC 30 AB 27 AB 26 AB 30 AB 29 AA2 6 AA2 7 AA3 0 AA2 9 Y2 5 Y2 6 Y2 8 Y2 7 W 25 W 26 W 27 W 28 V2 4 V2 5 Y2 9 Y3 0 V2 7 V2 8 W 29 W 30 U25 U26 V2 9 V3 0 U28 U27 U29 U30 T30 T29 LF X1200C-XXF900X BK 5_IO 0_CLKO UT6_LP 285 BK 5_IO 1_CLKO UT7_LP 285 BK 5_IO 2_PLLF BK 6_LP286 BK 5_IO 3_PLLF BK 7_LP286 BK 5_IO 4_LP287 BK 5_IO 5_LP287 BK 5_IO 6_PLLR ST6_LP 288 BK 5_IO 7_PLLR ST7_LP 288 BK 5_IO 8_LP297 BK 5_IO 9_LP297 BK 5_IO 10_HSI7ASIN P_LP 298 BK 5_IO 11_HSI7ASIN N_LP 298 BK 5_IO 12_LP299 BK 5_IO 13_LP299 BK 5_IO 14_HSI7ASOUTP_LP 300 BK 5_IO 15_HSI7ASO UTN _LP 300 BK 5_IO 16_LP301 BK 5_IO 17_LP301 BK 5_IO 18_HSI7BSIN P_LP 302 BK 5_IO 19_HSI7BSINN_LP 302 BK 5_IO 20_LP303 BK 5_IO 21_LP303 BK 5_IO 22_HSI7BSO U TP_LP 304 BK 5_IO 23_HSI7BSOU TN _LP304 BK 5_IO 24_LP321 BK 5_IO 25_LP321 BK 5_IO 26_HSI8ASIN P_LP 322 BK 5_IO 27_HSI8ASIN N_LP 322 BK 5_IO 28_LP323 BK 5_IO 29_LP323 BK 5_IO 30_HSI8ASOUTP_LP 324 BK 5_IO 31_HSI8ASO UTN _LP 324 BK 5_IO 32_LP325 BK 5_IO 33_LP325 BK 5_IO 34_HSI8BSIN P_LP 326 BK 5_IO 35_HSI8BSINN_LP 326 BK 5_IO 36_LP327 BK 5_IO 37_LP327 BK 5_IO 38_HSI8BSO U TP_LP 328 BK 5_IO 39_HSI8BSOU TN _LP328 BK 5_IO 40_LP329 BK 5_IO 41_LP329 BK 5_IO 42_HSI9ASIN P_LP 330 BK 5_IO 43_HSI9ASIN N_LP 330 BK 5_IO 44_LP331 BK 5_IO 45_LP331 BK 5_IO 46_HSI9ASOUTP_LP 332 BK 5_IO 47_HSI9ASO UTN _LP 332 BK 5_IO 48_LP333 BK 5_IO 50_HSI9BSIN P_LP 334 BK 5_IO 51_HSI9BSINN_LP 334 BK 5_IO 52_LP335 BK 5_IO 53_LP335 BK 5_IO 54_HSI9BSO U TP_LP 336 BK 5_IO 55_HSI9BSOU TN _LP336 BK 5_IO 56_LP339 BK 5_IO 57_LP339 BK 5_IO 58_LP340 BK 5_IO 59_LP340 BK 5_IO 60_LP341 BK 5_IO 61_LP341 XPGA I/O Banks 4, 5 BK 4_IO 0_LP 228 BK 4_IO 1_LP 228 BK 4_IO 2_LP 229 BK 4_IO 3_LP 229 BK 4_IO 4_LP 230 BK 4_IO 5_LP 230 BK 4_IO 6_HSI5ASIN P_LP233 BK 4_IO 7_HSI5ASIN N _LP 233 BK 4_IO 8_LP 234 BK 4_IO 9_LP 234 BK 4_IO 10_HSI5ASO UTP_LP235 BK 4_IO 11_HSI5ASO UTN _LP 235 BK 4_IO 13_LP236 BK 4_IO 14_HSI5BSINP_LP237 BK 4_IO 15_HSI5BSINN_LP237 BK 4_IO 16_LP238 BK 4_IO 17_LP238 BK 4_IO 18_HSI5BSO U TP_LP239 BK 4_IO 19_HSI5BSO U TN_LP239 BK 4_IO 20_LP240 BK 4_IO 21_LP240 BK 4_IO 22_HSI6ASIN P_LP241 BK 4_IO 23_HSI6ASINN _LP241 BK 4_IO 24_LP242 BK 4_IO 25_LP242 BK 4_IO 26_HSI6ASO UTP_LP243 BK 4_IO 27_HSI6ASO UTN _LP 243 BK 4_IO 28_LP244 BK 4_IO 29_LP244 BK 4_IO 30_HSI6BSINP_LP245 BK 4_IO 31_HSI6BSINN_LP245 BK 4_IO 32_LP246 BK 4_IO 33_LP246 BK 4_IO 34_HSI6BSO U TP_LP247 BK 4_IO 35_HSI6BSO U TN_LP247 BK 4_IO 36_LP248 BK 4_IO 37_LP248 BK 4_IO 38_LP265 BK 4_IO 39_LP265 BK 4_IO 40_LP266 BK 4_IO 41_LP266 BK 4_IO 42_LP267 BK 4_IO 43_LP267 BK 4_IO 44_LP268 BK 4_IO 45_LP268 BK 4_IO 46_LP269 BK 4_IO 47_LP269 BK 4_IO 48_PLLRST4_LP270 BK 4_IO 49_PLLRST5_LP270 BK 4_IO 50_LP271 BK 4_IO 51_LP271 BK 4_IO 52_LP272 BK 4_IO 53_LP272 BK 4_IO 54_SSC LKIN 1P_LP281 BK 4_IO 55_SSC LKIN 1N_LP281 BK 4_IO 56_PLLFB K4_LP282 BK 4_IO 57_PLLFB K5_LP282 BK 4_IO 58_SSC LKOU T1P_LP 283 BK 4_IO 59_SSC LKOU T1N _LP283 BK 4_IO 60_CLK OUT4_LP 284 BK 4_IO 61_CLK OUT5_LP 284 U11G 3 R29 R30 P30 P29 P27 P28 P26 P25 N27 N28 N29 N30 N25 N24 M 29 M 30 M 28 M 27 L30 L29 M 26 M 25 K30 K29 L28 L27 L26 L25 K27 K26 J30 J29 J26 J27 H30 H29 J25 J24 G30 G29 H27 H28 F30 F29 G27 G28 E30 E29 H26 D30 D29 F28 F27 C30 C29 G26 G25 F26 E28 E27 D28 4 R104 100 R103 100 R94 100 R86 100 TP59 TP60 TP57 TP58 HSI8B_SINP HSI8B_SINN HSI8A_SINP HSI8A_SINN HSI7B_SINP HSI7B_SINN HSI7A_SINP HSI7A_SINN 2 3 4 XPGA I/O Banks 4, 5 (HSI/Source Synchronous In) SS_CLK_IN_1P SS_CLK_IN_1N 2 SM A J22 SM A J18 SM A J14 SM A J10 5 5 Date: File: B Size Titl e 6/18/2003 C :\wcn\.. \XPGA_Sheet08.SC HDO C Number Revision 6 Sheet8 of TB D D rawn By: Schemati c,XPGA Dem o Board SM A J23 SM A J19 SM A J15 SM A J11 6 D C B A Lattice Semiconductor ispXPGA Evaluation Board User’s Guide Figure 12. Lattice ispXPGA Evaluation Board Schematic 19 D C B A 1 BK 6_IO 54_DAT A1 BK 6_IO 55_DAT A0 BK 6_IO 50_DAT A3 BK 6_IO 51_DAT A2 BK 6_IO 36_DAT A5 BK 6_IO 37_DAT A4 BK 6_IO 32_DAT A7 BK 6_IO 33_DAT A6 BK 6_IO 8_LP350 BK 6_IO 9_LP350 BK 6_IO 10_LP351 BK 6_IO 11_LP351 BK 6_IO 4_CSB BK 6_IO 5_READ BK 6_IO 0_IN ITB BK 6_IO 1_CCL K 1 D26 C26 B27 A27 D25 C25 B26 A26 F24 E24 A25 B25 C24 A24 B24 F23 E23 A23 B23 C23 D23 E22 D22 G21 F21 B22 A22 E21 D21 A21 B21 F20 E20 D20 C20 F19 E19 B20 A20 D19 C19 A19 B19 G18 F18 A18 B18 D18 C18 F17 E17 D17 C17 B17 A17 F16 E16 D16 C16 B16 A16 2 BK 7_IO 0_LP399 BK 7_IO 1_LP399 BK 7_IO 2_LP400 BK 7_IO 3_LP400 BK 7_IO 4_LP401 BK 7_IO 5_LP401 BK 7_IO 6_LP403 BK 7_IO 7_LP403 BK 7_IO 8_LP409 BK 7_IO 9_LP409 BK 7_IO 10_LP411 BK 7_IO 11_LP411 BK 7_IO 12_LP412 BK 7_IO 13_LP412 BK 7_IO 14_LP413 BK 7_IO 15_LP413 BK 7_IO 16_LP415 BK 7_IO 17_LP415 BK 7_IO 18_LP416 BK 7_IO 19_LP416 BK 7_IO 20_LP417 BK 7_IO 21_LP417 BK 7_IO 22_LP424 BK 7_IO 23_LP424 BK 7_IO 24_LP425 BK 7_IO 25_LP425 BK 7_IO 26_LP426 BK 7_IO 27_LP426 BK 7_IO 28_LP427 BK 7_IO 29_LP427 BK 7_IO 30_LP428 BK 7_IO 31_LP428 BK 7_IO 32_LP429 BK 7_IO 33_LP429 BK 7_IO 34_LP430 BK 7_IO 35_LP430 BK 7_IO 36_LP432 BK 7_IO 37_LP432 BK 7_IO 38_LP433 BK 7_IO 39_LP433 BK 7_IO 40_LP434 BK 7_IO 41_LP434 BK 7_IO 42_LP435 BK 7_IO 43_LP435 BK 7_IO 44_LP439 BK 7_IO 45_LP439 BK 7_IO 46_LP441 BK 7_IO 48_LP446 BK 7_IO 49_LP446 BK 7_IO 50_LP447 BK 7_IO 51_LP447 BK 7_IO 52_LP448 BK 7_IO 53_LP448 BK 7_IO 54_LP449 BK 7_IO 55_LP449 BK 7_IO 56_LP453 BK 7_IO 57_LP453 BK 7_IO 58_LP454 BK 7_IO 59_LP454 BK 7_IO 60_LP455 BK 7_IO 61_LP455 LFX1200C-XXF900X XPGA I/O Banks 6, 7 BK 6_IO 0_INITB _LP342 BK 6_IO 1_CCL K_LP 342 BK 6_IO 2_LP343 BK 6_IO 3_LP343 BK 6_IO 4_CSB _LP345 BK 6_IO 5_REA D _LP 345 BK 6_IO 6_LP349 BK 6_IO 7_LP349 BK 6_IO 8_LP350 BK 6_IO 9_LP350 BK 6_IO 10_LP351 BK 6_IO 11_LP351 BK 6_IO 13_LP356 BK 6_IO 14_LP358 BK 6_IO 15_LP358 BK 6_IO 16_LP359 BK 6_IO 17_LP359 BK 6_IO 18_LP362 BK 6_IO 19_LP362 BK 6_IO 20_LP363 BK 6_IO 21_LP363 BK 6_IO 22_LP364 BK 6_IO 23_LP364 BK 6_IO 24_LP365 BK 6_IO 25_LP365 BK 6_IO 26_LP366 BK 6_IO 27_LP366 BK 6_IO 28_LP367 BK 6_IO 29_LP367 BK 6_IO 30_LP368 BK 6_IO 31_LP368 BK 6_IO 32_DAT A7_LP371 BK 6_IO 33_DAT A6_LP371 BK 6_IO 34_LP372 BK 6_IO 35_LP372 BK 6_IO 36_DAT A5_LP374 BK 6_IO 37_DAT A4_LP374 BK 6_IO 38_LP375 BK 6_IO 39_LP375 BK 6_IO 40_LP382 BK 6_IO 41_LP382 BK 6_IO 42_LP384 BK 6_IO 43_LP384 BK 6_IO 44_LP385 BK 6_IO 45_LP385 BK 6_IO 46_LP386 BK 6_IO 47_LP386 BK 6_IO 48_LP387 BK 6_IO 49_LP387 BK 6_IO 50_DAT A3_LP388 BK 6_IO 51_DAT A2_LP388 BK 6_IO 52_LP389 BK 6_IO 53_LP389 BK 6_IO 54_DAT A1_LP394 BK 6_IO 55_DAT A0_LP394 BK 6_IO 56_LP395 BK 6_IO 57_LP395 BK 6_IO 58_LP396 BK 6_IO 59_LP396 BK 6_IO 60_LP397 BK 6_IO 61_LP397 U11H 2 A15 B15 C15 D15 E15 F15 A14 B14 C14 D14 E14 F14 C13 D13 B13 A13 F13 G13 A12 B12 C12 D12 A11 B11 E12 F12 C11 D11 E11 F11 B10 A10 D10 E10 A9 B9 F10 G10 A8 B8 D9 E9 A7 B7 C8 D8 A6 E8 F8 C7 D7 E7 F7 A5 B5 C6 D6 D5 C5 B4 A4 BK 7_IO 34_LP430 BK 7_IO 35_LP430 BK 7_IO 36_LP432 BK 7_IO 37_LP432 BK 7_IO 38_LP433 BK 7_IO 39_LP433 BK 7_IO 40_LP434 BK 7_IO 41_LP434 R110 49.9 R111 49.9 R113 49.9 VC CO D R112 49.9 4 3 4 XPGA I/O Banks 6, 7 & Headers BK 7_IO 48_LP448 BK 7_IO 49_LP446 BK 7_IO 50_LP447 BK 7_IO 51_LP447 BK 7_IO 52_LP448 BK 7_IO 53_LP448 BK 7_IO 54_LP449 BK 7_IO 55_LP449 BK 7_IO 56_LP453 BK 7_IO 57_LP453 R106 24.9 R107 24.9 R108 24.9 R109 24.9 BK 7_IO 42_LP435 BK 7_IO 43_LP435 BK 7_IO 44_LP439 BK 7_IO 45_LP439 BK 7_IO 33_LP429 BK 7_IO 13_LCD 1 BK 7_IO 14_LCD 2 BK 7_IO 15_LCD 3 BK 7_IO 16_LCD 4 BK 7_IO 17_LCD 5 BK 7_IO 18_LCD 6 BK 7_IO 19_LCD 7 BK 7_IO 20_LCD 8 BK 7_IO 21_LCD 9 BK 7_IO 22_LC D A BK 7_IO 23_LCD B 3 PGM F CFG 0 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 P6 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 GC LK 6_DIFF BK 6_IO 0_IN ITB BK 6_IO 4_CSB BK 6_IO 8_LP350 BK 6_IO 10_LP351 BK 6_IO 32_DAT A7 BK 6_IO 36_DAT A5 BK 6_IO 50_DAT A3 BK 6_IO 54_DAT A1 PGM F CFG 0 BK 7_IO 34_LP430 BK 7_IO 36_LP432 BK 7_IO 38_LP433 BK 7_IO 40_LP434 BK 7_IO 42_LP435 BK 7_IO 44_LP439 BK 7_IO 48_LP448 BK 7_IO 50_LP447 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 J28 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 BK 6_IO 1_CCL K BK 6_IO 5_READ K6_IO 9_LP350 BK 6_IO 11_LP351 BK 6_IO 33_DATA6 BK 6_IO 37_DATA4 BK 6_IO 51_DATA2 BK 6_IO 55_DATA0 DO NE BK 7_IO 33_LP429 K7_IO 35_LP430 BK 7_IO 37_LP432 BK 7_IO 39_LP433 BK 7_IO 41_LP434 BK 7_IO 43_LP435 K7_IO 45_LP439 K7_IO 49_LP446 K7_IO 51_LP447 GC LK 7_DIFF 5 Date: File: B Size 6/18/2003 C :\wcn\.. \XPGA_Sheet09.SC HDO C Number Revision 6 Sheet9 of TB D D rawn By: Schemati c,XPGA Dem o Board DO NE GC LK 7_DIFF DO NE GC LK 7_DIFF K7_IO 35_LP430 K7_IO 37_LP432 K7_IO 39_LP433 K7_IO 41_LP434 K7_IO 43_LP435 K7_IO 45_LP439 K7_IO 49_LP446 K7_IO 51_LP447 K7_IO 53_LP448 K7_IO 55_LP449 K7_IO 57_LP453 *GCLK6_DIFF & GCLK7_DIFF are routed as a controlled impedance differential pair Titl e 6 BK 6_IO 1_CCL K BK 6_IO 5_READ K6_IO 9_LP350 BK 6_IO 11_LP351 BK 6_IO 33_DATA6 BK 6_IO 37_DATA4 BK 6_IO 51_DATA2 BK 6_IO 55_DATA0 DO NE BK 7_IO 33_LP429 GC LK 7_DIFF 2mm Header – I/O Banks 6, 7 BK 7_IO 34_LP430 BK 7_IO 36_LP432 BK 7_IO 38_LP433 BK 7_IO 40_LP434 BK 7_IO 42_LP435 BK 7_IO 44_LP439 BK 7_IO 48_LP448 BK 7_IO 50_LP447 BK 7_IO 52_LP448 BK 7_IO 54_LP449 BK 7_IO 56_LP453 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 TM M -125-01-G -D-SM Mictor Header – I/O Banks 6, 7 GC LK 6_DIFF PGM F CFG 0 GC LK 6_DIFF BK 6_IO 0_IN ITB BK 6_IO 4_CSB BK 6_IO 8_LP350 BK 6_IO 10_LP351 BK 6_IO 32_DAT A7 BK 6_IO 36_DAT A5 BK 6_IO 50_DAT A3 BK 6_IO 54_DAT A1 PGM F CFG 0 GC LK 6_DIFF 5 M IS-019-01-L-D G1 G2 G3 G4 G5 D C B A Lattice Semiconductor ispXPGA Evaluation Board User’s Guide Figure 13. Lattice ispXPGA Evaluation Board Schematic 20 D C B 1 R141 R142 R143 R144 R145 R146 R147 R148 R149 100 B B 100 100 100 100 100 100 100 100 K2_IO 1_LP116_LVD R K2_IO 3_LP117_LVD R BK 2_IO 5_LP 118_LV DR BK 2_IO 7_LP 121_LVD R BK 2_IO 9_LP122_LVD R BK 2_IO 11_LP123_LVDR BK 2_IO 15_LP129_LVDR BK 2_IO 17_LP134_LVDR BK 2_IO 19_LP135_LVDR 2 (Associated I/O Pins in Figure 11) Bank 2 LVDS RCVRS Termination BK 2_IO 0_LP116_LVD R BK 2_IO 2_LP117_LVD R BK 2_IO 4_LP 118_LV DR BK 2_IO 6_LP 121_LV DR BK 2_IO 8_LP 122_LV DR BK 2_IO 10_LP123_LVDR BK 2_IO 14_LP129_LVDR BK 2_IO 16_LP134_LVDR BK 2_IO 18_LP135_LVDR 2 165 R119 R120 BK 3_IO 5_LP 174_LVD T_B BK 3_IO 6_LP 175_LVD T_B 165 165 165 R129 R130 R131 BK 3_IO 15_LP182_LV DT _B BK 3_IO 16_LP187_LV DT _B BK 3_IO 17_LP187_LV DT _B R140 140 R139 140 R138 140 R137 140 R136 140 R135 140 R134 140 R133 140 R132 140 BK 3_IO 17_LP187_LV DT BK 3_IO 16_LP187_LV DT BK 3_IO 15_LP182_LV DT BK 3_IO 14_LP182_LV DT BK 3_IO 13_LP180_LVD T BK 3_IO 12_LP180_LVD T BK 3_IO 11_LP179_LVD T BK 3_IO 10_LP179_LV DT BK 3_IO 9_LP178_LVD T BK 3_IO 8_LP 178_LV DT BK 3_IO 7_LP 175_LVD T BK 3_IO 6_LP 175_LVD T BK 3_IO 5_LP174_LVD T BK 3_IO 4_LP174_LVD T BK 3_IO 3_LP173_LVD T BK 3_IO 2_LP173_LVD T BK 3_IO 1_LP172_LVD T BK 3_IO 0_LP 172_LV DT (Associated Pins in Figure 11) Bank 3 LVDS DRVRS Termination 165 165 R127 BK 3_IO 13_LP180_LV DT _B R128 165 R126 BK 3_IO 12_LP180_LV DT _B BK 3_IO 14_LP182_LVD T_B 165 R125 BK 3_IO 11_LP179_LV DT _B 165 165 R124 R123 BK 3_IO 9_LP 178_LV DT_B BK 3_IO 10_LP179_LV DT _B 165 R122 165 165 BK 3_IO 8_LP 178_LVD T_B R121 165 R118 BK 3_IO 4_LP174_LVD T_B BK 3_IO 7_LP 175_LVD T_B 165 R117 BK 3_IO 3_LP173_LVD T_B 165 R116 BK 3_IO 2_LP 173_LVD T_B 165 165 R115 R114 BK 3_IO 1_LP 172_LVD T_B BK 3_IO 0_LP 172_LV DT_B 4 3 4 LVDS Terminations and LCD Header 3 5 5 Date: File: B Size Titl e V5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 C68 0.1 P3 Number 6/18/2003 C :\wcn\.. \XPGA_SheetA .SCH DOC 6 C69 10 Revision 6 SheetA of TB D Drawn By: Schemati c,XPGA Dem o Board LCD Header BK 7_IO 13_LC D 1 BK 7_IO 14_LC D 2 BK 7_IO 15_LC D 3 BK 7_IO 16_LCD 4 BK 7_IO 17_LCD 5 BK 7_IO 18_LCD 6 BK 7_IO 19_LCD 7 BK 7_IO 20_LCD 8 BK 7_IO 21_LCD 9 BK 7_IO 22_LCD A BK 7_IO 23_LCD B R91 20K V5 TSM-114-03-L-SV-P A 1 D C B A Lattice Semiconductor ispXPGA Evaluation Board User’s Guide Figure 14. Lattice ispXPGA Evaluation Board Schematic VCCOD RUSERBOT R67 VCCOD RUSERTOP R64 C70 R81 C40 C38 C41 I/O BANKS 2,3 J26 1 2 19 20 P4 C31 C64 1 C39 C63 37 38 R55 R52 VCCOB RUSERTOP 50 49 39 VREF1 RUSERBOT R75 R73 VREF1 RUSERTOP VCCOB RUSERBOT 40 C34 C26 2 C37 C30 C61 VCCOC RUSERBOT C36 C62 C25 R61 C71 C28 C29 C60 C27 C59 C24 R58 R36 VCCOC RUSERTOP C35 C21 C22 C23 VREF2 RUSERBOT C20 RUSERTOP C19 R77 R46 C55 R49 VREF0 RUSERBOT VREF0 RUSERTOP VCCOA RUSERBOT VREF2 C56 RUSERTOP C57 VCCOA R71 R33 K L M N C58 C53 P R T U C54 V W Y AA AB AC AD AE AF AG AH AJ AK C32 C33 1.5V J 1.8V 127.0K R69 127.0K 110.0K H 110.0K 40.2K F 110.0K D 3.3V DNP DNP G B FIXED E 2.5V 127.0K C 1 A R C50 C65 FIXED 10 C52 49 127.0K 110.0K 20 39 TOP 110.0K DNP C44 C45 C46 37 38 50 BOT DNP R87 R43 C51 J28 I/O BANKS 6,7 40 R 1 2 P6 TOP DNP 200.OK 30 C49 C43 19 20 R USER BOT 1 2 C2 R40 R USER R84 C3 Appendix B. Bottom Silkscreen Drawing VCCOX LDO ADJUSTMENT VCCOX C68 C42