Certus-NX Family
Data Sheet
FPGA-DS-02078-1.0
November 2021
Certus-NX Family
Data Sheet
Disclaimers
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proprietary to Lattice Semiconductor, and Lattice reserves the right to make any changes to the information in this document or to any products at
any time without notice.
© 2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
2
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
Contents
Acronyms in This Document ............................................................................................................................................... 10
1. General Description .................................................................................................................................................... 11
1.1.
Features ............................................................................................................................................................ 11
2. Architecture ................................................................................................................................................................ 14
2.1.
Overview ........................................................................................................................................................... 14
2.2.
PFU Blocks ......................................................................................................................................................... 16
2.2.1. Slice ............................................................................................................................................................... 16
2.2.2. Modes of Operation...................................................................................................................................... 19
2.2.2.1.
Logic Mode ........................................................................................................................................... 19
2.2.2.2.
Ripple Mode ......................................................................................................................................... 19
2.2.2.3.
RAM Mode ........................................................................................................................................... 19
2.2.2.4.
ROM Mode ........................................................................................................................................... 19
2.3.
Routing .............................................................................................................................................................. 20
2.3.1. Clocking Structure ......................................................................................................................................... 20
2.3.2. Global PLL ..................................................................................................................................................... 20
2.3.3. Clock Distribution Network........................................................................................................................... 21
2.3.4. Primary Clocks .............................................................................................................................................. 22
2.3.5. Edge Clock ..................................................................................................................................................... 23
2.3.6. Clock Dividers................................................................................................................................................ 23
2.3.7. Clock Center Multiplexer Blocks ................................................................................................................... 24
2.3.8. Dynamic Clock Select .................................................................................................................................... 24
2.3.9. Dynamic Clock Control .................................................................................................................................. 25
2.3.10. DDRDLL ......................................................................................................................................................... 25
2.4.
SGMII Clock Data Recovery (CDR) ..................................................................................................................... 26
2.5.
sysMEM Memory .............................................................................................................................................. 27
2.5.1. sysMEM Memory Block ................................................................................................................................ 27
2.5.2. Bus Size Matching ......................................................................................................................................... 28
2.5.3. RAM Initialization and ROM Operation ........................................................................................................ 28
2.5.4. Memory Cascading ....................................................................................................................................... 28
2.5.5. Single, Dual and Pseudo-Dual Port Modes ................................................................................................... 28
2.5.6. Memory Output Reset .................................................................................................................................. 28
2.6.
Large RAM ......................................................................................................................................................... 29
2.7.
sysDSP ............................................................................................................................................................... 29
2.7.1. sysDSP Approach Compared to General DSP................................................................................................ 29
2.7.2. sysDSP Architecture Features ....................................................................................................................... 30
2.8.
Programmable I/O (PIO).................................................................................................................................... 32
2.9.
Programmable I/O Cell (PIC) ............................................................................................................................. 32
2.9.1. Input Register Block ...................................................................................................................................... 34
2.9.2.1.
Input FIFO ............................................................................................................................................. 34
2.9.2. Output Register Block ................................................................................................................................... 35
2.10. Tri-state Register Block ..................................................................................................................................... 36
2.11. DDR Memory Support ....................................................................................................................................... 37
2.11.1. DQS Grouping for DDR Memory ................................................................................................................... 37
2.11.2. DLL Calibrated DQS Delay and Control Block (DQSBUF) ............................................................................... 38
2.12. sysI/O Buffer...................................................................................................................................................... 40
2.12.1. Supported sysI/O Standards ......................................................................................................................... 40
2.12.2. sysI/O Banking Scheme ................................................................................................................................. 41
2.12.2.1. Typical sysI/O Behavior During Power-up ............................................................................................ 42
2.12.2.2. VREF1 and VREF2 ................................................................................................................................. 42
2.12.2.3. SysI/O Standards Supported by I/O Bank ............................................................................................ 42
2.12.2.4. Hot Socketing ....................................................................................................................................... 43
2.12.3. sysI/O Buffer Configurations......................................................................................................................... 43
© 2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02078-1.0
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Certus-NX Family
Data Sheet
2.13. Analog Interface ................................................................................................................................................44
2.13.1. Analog to Digital Converters .........................................................................................................................44
2.13.2. Continuous Time Comparators .....................................................................................................................44
2.13.3. Internal Junction Temperature Monitoring Diode........................................................................................44
2.14. IEEE 1149.1-Compliant Boundary Scan Testability ............................................................................................44
2.15. Device Configuration .........................................................................................................................................45
2.15.1. Enhanced Configuration Options ..................................................................................................................45
2.15.2.1. Dual-Boot and Multi-Boot Image Support ...........................................................................................45
2.16. Single Event Upset (SEU) Handling ....................................................................................................................46
2.17. On-Chip Oscillator .............................................................................................................................................46
2.18. User I²C IP ..........................................................................................................................................................47
2.19. Trace ID .............................................................................................................................................................47
2.20. Density Shifting .................................................................................................................................................47
2.21. Peripheral Component Interconnect Express (PCIe) .........................................................................................48
2.22. Cryptographic Engine ........................................................................................................................................49
3. DC and Switching Characteristics for Commercial and Industrial ...............................................................................50
3.1.
Absolute Maximum Ratings ..............................................................................................................................50
3.2.
Recommended Operating Conditions1, 2, 3.........................................................................................................51
3.3.
Power Supply Ramp Rates.................................................................................................................................52
3.4.
Power up Sequence ...........................................................................................................................................52
3.5.
On-Chip Programmable Termination ................................................................................................................52
3.6.
Hot Socketing Specifications .............................................................................................................................53
3.7.
ESD Performance...............................................................................................................................................53
3.8.
DC Electrical Characteristics ..............................................................................................................................54
3.9.
Supply Currents .................................................................................................................................................55
3.10. sysI/O Recommended Operating Conditions ....................................................................................................56
3.11. sysI/O Single-Ended DC Electrical Characteristics .............................................................................................57
3.12. sysI/O Differential DC Electrical Characteristics ................................................................................................59
3.12.1. LVDS ..............................................................................................................................................................59
3.12.2. LVDS25E (Output Only) .................................................................................................................................60
3.12.3. SubLVDS (Input Only) ....................................................................................................................................60
3.12.4. SubLVDSE/SubLVDSEH (Output Only) ...........................................................................................................61
3.12.5. SLVS ...............................................................................................................................................................62
3.12.6. Soft MIPI D-PHY ............................................................................................................................................63
3.12.7. Differential HSTL15D (Output Only)..............................................................................................................66
3.12.8. Differential SSTL135D, SSTL15D (Output Only) .............................................................................................66
3.12.9. Differential HSUL12D (Output Only) .............................................................................................................66
3.12.10. Differential LVCMOS25D, LVCMOS33D, LVTTL33D (Output Only)................................................................66
3.13. Certus-NX Maximum sysI/O Buffer Speed ........................................................................................................66
3.14. Typical Building Block Function Performance ...................................................................................................69
3.15. LMMI .................................................................................................................................................................70
3.16. Derating Timing Tables ......................................................................................................................................70
3.17. Certus-NX External Switching Characteristics ...................................................................................................70
3.18. Certus-NX sysCLOCK PLL Timing (VCC = 1.0 V) ....................................................................................................78
3.19. Certus-NX Internal Oscillators Characteristics ..................................................................................................80
3.20. Certus-NX User I2C Characteristics ....................................................................................................................80
3.21. Certus-NX Analog-Digital Converter (ADC) Block Characteristics......................................................................80
3.22. Certus-NX Comparator Block Characteristics ....................................................................................................81
3.23. Certus-NX Digital Temperature Readout Characteristics ..................................................................................81
3.24. Certus-NX Hardened PCIe Characteristics .........................................................................................................82
3.24.1. PCIe (2.5 Gbps) ..............................................................................................................................................82
3.24.2. PCIe (5 Gbps) .................................................................................................................................................83
3.25. Certus-NX Hardened SGMII Receiver Characteristics........................................................................................85
3.25.1. SGMII Rx Specifications .................................................................................................................................85
© 2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
3.26. Certus-NX sysCONFIG Port Timing Specifications ............................................................................................. 85
3.27. JTAG Port Timing Specifications ........................................................................................................................ 91
3.28. Switching Test Conditions ................................................................................................................................. 92
4. DC and Switching Characteristics for Automotive ...................................................................................................... 93
4.1.
Absolute Maximum Ratings .............................................................................................................................. 93
4.2.
Recommended Operating Conditions1, 2, 3 ........................................................................................................ 94
4.3.
Power Supply Ramp Rates ................................................................................................................................ 95
4.4.
Power up Sequence........................................................................................................................................... 95
4.5.
On-Chip Programmable Termination ................................................................................................................ 95
4.6.
Hot Socketing Specifications ............................................................................................................................. 96
4.7.
ESD Performance .............................................................................................................................................. 96
4.8.
DC Electrical Characteristics .............................................................................................................................. 97
4.9.
Supply Currents ................................................................................................................................................. 98
4.10. sysI/O Recommended Operating Conditions .................................................................................................... 99
4.11. sysI/O Single-Ended DC Electrical Characteristics3 .......................................................................................... 100
4.12. sysI/O Differential DC Electrical Characteristics .............................................................................................. 102
4.12.1. LVDS ............................................................................................................................................................ 102
4.12.2. LVDS25E (Output Only) ............................................................................................................................... 103
4.12.3. SubLVDS (Input Only) .................................................................................................................................. 104
4.12.4. SubLVDSE/SubLVDSEH (Output Only) ......................................................................................................... 104
4.12.5. SLVS............................................................................................................................................................. 105
4.12.6. Differential HSTL15D (Output Only) ........................................................................................................... 105
4.12.7. Differential SSTL135D, SSTL15D (Output Only)........................................................................................... 106
4.12.8. Differential HSUL12D (Output Only) ........................................................................................................... 106
4.12.9. Differential LVCMOS25D, LVCMOS33D, LVTTL33D (Output Only) ............................................................. 106
4.13. Certus-NX Maximum sysI/O Buffer Speed ...................................................................................................... 106
4.14. Typical Building Block Function Performance ................................................................................................. 108
4.15. LMMI ............................................................................................................................................................... 109
4.16. Derating Timing Tables.................................................................................................................................... 110
4.17. Certus-NX External Switching Characteristics ................................................................................................. 110
4.18. Certus-NX sysCLOCK PLL Timing (VCC = 1.0 V).................................................................................................. 118
4.19. Certus-NX Internal Oscillators Characteristics ................................................................................................ 119
4.20. Certus-NX User I2C Characteristics .................................................................................................................. 119
4.21. Certus-NX Analog-Digital Converter (ADC) Block Characteristics ................................................................... 120
4.22. Certus-NX Comparator Block Characteristics .................................................................................................. 121
4.23. Certus-NX Digital Temperature Readout Characteristics ................................................................................ 121
4.24. Certus-NX Hardened PCIe Characteristics ....................................................................................................... 121
4.24.1. PCIe (2.5 Gb/s) ............................................................................................................................................ 121
4.24.2. PCIe (5 Gb/s) ............................................................................................................................................... 123
4.25. Certus-NX Hardened SGMII Receiver Characteristics ..................................................................................... 124
4.25.1. SGMII Rx Specifications............................................................................................................................... 124
4.26. Certus-NX sysCONFIG Port Timing Specifications ........................................................................................... 125
4.27. JTAG Port Timing Specifications ...................................................................................................................... 131
4.28. Switching Test Conditions ............................................................................................................................... 132
5. Pinout Information ................................................................................................................................................... 133
5.1.
Signal Descriptions* ......................................................................................................................................... 133
5.2.
Pin Information Summary ............................................................................................................................... 139
6. Ordering Information ............................................................................................................................................... 142
6.1.
Certus-NX Part Number Description ............................................................................................................... 142
6.2.
Ordering Part Numbers ................................................................................................................................... 143
6.2.1. Commercial ................................................................................................................................................. 143
6.2.2. Industrial ..................................................................................................................................................... 143
6.2.3. Automotive ................................................................................................................................................. 143
References ........................................................................................................................................................................ 144
© 2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02078-1.0
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Certus-NX Family
Data Sheet
Revision History ................................................................................................................................................................145
Figures
Figure 2.1. Simplified Block Diagram, LFD2NX-40 Device (Top Level) ................................................................................15
Figure 2.2. Simplified Block Diagram, LFD2NX-17 Device (Top Level) ................................................................................15
Figure 2.3. PFU Diagram .....................................................................................................................................................16
Figure 2.4. Slice Diagram ....................................................................................................................................................17
Figure 2.5. Slice configuration for LUT4 and LUT5 ..............................................................................................................18
Figure 2.6. General Purpose PLL Diagram...........................................................................................................................21
Figure 2.7. Clocking .............................................................................................................................................................22
Figure 2.8. Edge Clock Sources per Bank ............................................................................................................................23
Figure 2.9. DCS_CMUX Diagram .........................................................................................................................................24
Figure 2.10. DCS Waveforms ..............................................................................................................................................25
Figure 2.11. DLLDEL Functional Diagram ............................................................................................................................26
Figure 2.12. Certus-NX DDRDLL Architecture .....................................................................................................................26
Figure 2.13. SGMII CDR IP ...................................................................................................................................................27
Figure 2.14. Memory Core Reset ........................................................................................................................................29
Figure 2.15. Comparison of General DSP and Certus-NX Approaches................................................................................30
Figure 2.16. Certus-NX DSP Functional Block Diagram .......................................................................................................31
Figure 2.17. Group of Two High Performance Programmable I/O Cells .............................................................................33
Figure 2.18. Wide Range Programmable I/O Cells..............................................................................................................33
Figure 2.19. Input Register Block for PIO on Top, Left, and Right Sides of the Device .......................................................34
Figure 2.20. Input Register Block for PIO on Bottom Side of the Device ............................................................................35
Figure 2.21. Output Register Block on Top, Left, and Right Sides ......................................................................................35
Figure 2.22. Output Register Block on Bottom Side ...........................................................................................................36
Figure 2.23. Tri-state Register Block on Top, Left, and Right Sides.....................................................................................36
Figure 2.24. Tri-state Register Block on Bottom Side .........................................................................................................37
Figure 2.25. DQS Grouping on the Bottom Edge ................................................................................................................38
Figure 2.26. DQS Control and Delay Block (DQSBUF) .........................................................................................................39
Figure 2.27. sysI/O Banking ................................................................................................................................................42
Figure 2.28. PCIe Core.........................................................................................................................................................48
Figure 2.29. PCIe Soft IP Wrapper.......................................................................................................................................49
Figure 2.30. Cryptographic Engine Block Diagram ..............................................................................................................49
Figure 3.1. On-Chip Termination ........................................................................................................................................52
Figure 3.2. LVDS25E Output Termination Example ............................................................................................................60
Figure 3.3. SubLVDS Input Interface ...................................................................................................................................61
Figure 3.4. SubLVDS Output Interface ................................................................................................................................61
Figure 3.5. SLVS Interface ...................................................................................................................................................62
Figure 3.6. MIPI Interface ...................................................................................................................................................63
Figure 3.7. Receiver RX.CLK.Centered Waveforms .............................................................................................................76
Figure 3.8. Receiver RX.CLK.Aligned and DDR Memory Input Waveforms .........................................................................76
Figure 3.9. Transmit TX.CLK.Centered and DDR Memory Output Waveforms ...................................................................76
Figure 3.10. Transmit TX.CLK.Aligned Waveforms..............................................................................................................77
Figure 3.11. DDRX71 Video Timing Waveforms..................................................................................................................77
Figure 3.12. Receiver DDRX71_RX Waveforms ...................................................................................................................78
Figure 3.13. Transmitter DDRX71_TX Waveforms ..............................................................................................................78
Figure 3.14. Master SPI POR/REFRESH Timing....................................................................................................................87
Figure 3.15. Slave SPI/I2C/I3C POR/REFRESH Timing ..........................................................................................................87
Figure 3.16. Master SPI PROGRAMN Timing ......................................................................................................................88
Figure 3.17. Slave SPI/I2C/I3C PROGRAMN Timing .............................................................................................................88
Figure 3.18. Master SPI Configuration Timing ....................................................................................................................89
Figure 3.19. Slave SPI Configuration Timing .......................................................................................................................89
Figure 3.20. I2C/I3C Configuration Timing ..........................................................................................................................89
© 2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
6
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
Figure 3.21. Master SPI Wake-Up Timing ........................................................................................................................... 90
Figure 3.22. Slave SPI/I2C/I3C Wake-Up Timing.................................................................................................................. 90
Figure 3.23. JTAG Port Timing Waveforms ......................................................................................................................... 91
Figure 3.24. Output Test Load, LVTTL and LVCMOS Standards .......................................................................................... 92
Figure 4.1. On-Chip Termination ........................................................................................................................................ 95
Figure 4.2. LVDS25E Output Termination Example .......................................................................................................... 103
Figure 4.3. SubLVDS Input Interface ................................................................................................................................. 104
Figure 4.4. SubLVDS Output Interface .............................................................................................................................. 104
Figure 4.5. Receiver RX.CLK.Centered Waveforms ........................................................................................................... 115
Figure 4.6. Receiver RX.CLK.Aligned and DDR Memory Input Waveforms....................................................................... 115
Figure 4.7. Transmit TX.CLK.Centered and DDR Memory Output Waveforms................................................................. 116
Figure 4.8. Transmit TX.CLK.Aligned Waveforms ............................................................................................................. 116
Figure 4.9. DDRX71 Video Timing Waveforms ................................................................................................................. 117
Figure 4.10. Receiver DDRX71_RX Waveforms................................................................................................................. 117
Figure 4.11. Transmitter DDRX71_TX Waveforms............................................................................................................ 118
Figure 4.12. Master SPI POR/REFRESH Timing ................................................................................................................. 126
Figure 4.13. Slave SPI/I2C/I3C POR/REFRESH Timing ........................................................................................................ 127
Figure 4.14. Master SPI PROGRAMN Timing .................................................................................................................... 127
Figure 4.15. Slave SPI/I2C/I3C PROGRAMN Timing ........................................................................................................... 128
Figure 4.16. Master SPI Configuration Timing .................................................................................................................. 128
Figure 4.17. Slave SPI Configuration Timing ..................................................................................................................... 129
Figure 4.18. I2C /I3C Configuration Timing ....................................................................................................................... 129
Figure 4.19. Master SPI Wake-Up Timing ......................................................................................................................... 130
Figure 4.20. Slave SPI/I2C/I3C Wake-Up Timing................................................................................................................ 130
Figure 4.21. JTAG Port Timing Waveforms ....................................................................................................................... 131
Figure 4.22. Output Test Load, LVTTL and LVCMOS Standards ........................................................................................ 132
© 2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02078-1.0
7
Certus-NX Family
Data Sheet
Tables
Table 1.1. Certus-NX Commercial/Industrial Family Selection Guide .................................................................................13
Table 1.2. Certus-NX Automotive Family Selection Guide ..................................................................................................13
Table 2.1. Resources and Modes Available per Slice ..........................................................................................................16
Table 2.2. Slice Signal Descriptions .....................................................................................................................................18
Table 2.3. Number of Slices Required to Implement Distributed RAM ..............................................................................19
Table 2.4. sysMEM Block Configurations ............................................................................................................................28
Table 2.5. Maximum Number of Elements in a sysDSP block .............................................................................................32
Table 2.6. Input Block Port Description ..............................................................................................................................34
Table 2.7. Output Block Port Description ...........................................................................................................................36
Table 2.8. Tri-state Block Port Description .........................................................................................................................37
Table 2.9. DQSBUF Port List Description.............................................................................................................................39
Table 2.10. Single-Ended I/O Standards .............................................................................................................................40
Table 2.11. Differential I/O Standards ................................................................................................................................41
Table 2.12. Single-Ended I/O Standards Supported on Various Sides ................................................................................43
Table 2.13. Differential I/O Standards Supported on Various Sides ...................................................................................43
Table 3.1. Absolute Maximum Ratings ...............................................................................................................................50
Table 3.2. Recommended Operating Conditions ................................................................................................................51
Table 3.3. Power Supply Ramp Rates .................................................................................................................................52
Table 3.4. Power-On Reset .................................................................................................................................................52
Table 3.5. On-Chip Termination Options for Input Modes .................................................................................................52
Table 3.6. Hot Socketing Specifications for GPIO ...............................................................................................................53
Table 3.7. DC Electrical Characteristics – Wide Range ........................................................................................................54
Table 3.8. DC Electrical Characteristics – High Speed .........................................................................................................54
Table 3.9. Capacitance – Wide Range .................................................................................................................................54
Table 3.10. Capacitance – High Performance .....................................................................................................................55
Table 3.11. Single Ended Input Hysteresis – Wide Range ...................................................................................................55
Table 3.12. Single Ended Input Hysteresis – High Performance .........................................................................................55
Table 3.13. sysI/O Recommended Operating Conditions ...................................................................................................56
Table 3.14. sysI/O DC Electrical Characteristics – Wide Range I/O.....................................................................................57
Table 3.15. sysI/O DC Electrical Characteristics – High Performance I/O ...........................................................................58
Table 3.16. I/O Resistance Characteristics ..........................................................................................................................58
Table 3.17. LVDS DC Electrical Characteristics1 ..................................................................................................................59
Table 3.18. LVDS25E DC Conditions ....................................................................................................................................60
Table 3.19. SubLVDS Input DC Electrical Characteristics ....................................................................................................60
Table 3.20. SubLVDS Output DC Electrical Characteristics .................................................................................................61
Table 3.21. SLVS Input DC Characteristics ..........................................................................................................................62
Table 3.22. SLVS Output DC Characteristics .......................................................................................................................62
Table 3.23. Soft D-PHY Input Timing and Levels .................................................................................................................64
Table 3.24. Soft D-PHY Output Timing and Levels ..............................................................................................................65
Table 3.25. Soft D-PHY Clock Signal Specification...............................................................................................................65
Table 3.26. Soft D-PHY Data-Clock Timing Specifications ...................................................................................................66
Table 3.27. Certus-NX Maximum I/O Buffer Speed1, 2, 3, 4, 7 .................................................................................................66
Table 3.28. Pin-to-Pin Performance ....................................................................................................................................69
Table 3.29. Register-to-Register Performance....................................................................................................................69
Table 3.30. LMMI FMAX Summary ........................................................................................................................................70
Table 3.31. Certus-NX External Switching Characteristics (VCC = 1.0 V) ..............................................................................70
Table 3.32. sysCLOCK PLL Timing (VCC = 1.0 V) ....................................................................................................................78
Table 3.33. Internal Oscillators (VCC = 1.0 V) .......................................................................................................................80
Table 3.34. User I2C Specifications (VCC = 1.0 V) ..................................................................................................................80
Table 3.35. ADC Specifications............................................................................................................................................80
Table 3.36. Comparator Specifications ...............................................................................................................................81
Table 3.37. DTR Specifications ............................................................................................................................................81
© 2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
8
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
Table 3.38. PCIe (2.5 Gbps) ................................................................................................................................................. 82
Table 3.39. PCIe (5 Gbps) .................................................................................................................................................... 83
Table 3.40. SGMII Rx ........................................................................................................................................................... 85
Table 3.41. Certus-NX sysCONFIG Port Timing Specifications ............................................................................................ 85
Table 3.42. JTAG Port Timing Specifications ....................................................................................................................... 91
Table 3.43. Test Fixture Required Components, Non-Terminated Interfaces .................................................................... 92
Table 4.1. Absolute Maximum Ratings ............................................................................................................................... 93
Table 4.2. Recommended Operating Conditions ................................................................................................................ 94
Table 4.3. Power Supply Ramp Rates ................................................................................................................................. 95
Table 4.4. Power-On Reset ................................................................................................................................................. 95
Table 4.5. On-Chip Termination Options for Input Modes ................................................................................................. 96
Table 4.6. Hot Socketing Specifications for GPIO ............................................................................................................... 96
Table 4.7. DC Electrical Characteristics – Wide Range........................................................................................................ 97
Table 4.8. DC Electrical Characteristics – High Speed ......................................................................................................... 97
Table 4.9. Capacitors – Wide Range ................................................................................................................................... 97
Table 4.10. Capacitors – High Performance ....................................................................................................................... 98
Table 4.11. Single Ended Input Hysteresis – Wide Range................................................................................................... 98
Table 4.12. Single Ended Input Hysteresis – High Performance ......................................................................................... 98
Table 4.13. sysI/O Recommended Operating Conditions ................................................................................................... 99
Table 4.14. sysI/O DC Electrical Characteristics – Wide Range I/O .................................................................................. 100
Table 4.15. sysI/O DC Electrical Characteristics – High Performance I/O3 ....................................................................... 101
Table 4.16. I/O Resistance Characteristics........................................................................................................................ 101
Table 4.17. LVDS DC Electrical Characteristics1 ................................................................................................................ 102
Table 4.18. LVDS25E DC Conditions.................................................................................................................................. 103
Table 4.19. SubLVDS Input DC Electrical Characteristics .................................................................................................. 104
Table 4.20. SubLVDS Output DC Electrical Characteristics ............................................................................................... 104
Table 4.21. SLVS Input DC Characteristics ........................................................................................................................ 105
Table 4.22. SLVS Output DC Characteristics ..................................................................................................................... 105
Table 4.23. Certus-NX Maximum I/O Buffer Speed1, 2, 3, 4, 7............................................................................................... 106
Table 4.24. Pin-to-Pin Performance.................................................................................................................................. 108
Table 4.25. Register-to-Register Performance ................................................................................................................. 108
Table 4.26. LMMI FMAX Summary ...................................................................................................................................... 109
Table 4.27. Certus-NX External Switching Characteristics (VCC = 1.0 V)............................................................................ 110
Table 4.28. sysCLOCK PLL Timing (VCC = 1.0 V).................................................................................................................. 118
Table 4.29. Internal Oscillators (VCC = 1.0 V)..................................................................................................................... 119
Table 4.30. User I2C Specifications (VCC = 1.0 V)................................................................................................................ 119
Table 4.31. ADC Specifications ......................................................................................................................................... 120
Table 4.32. Comparator Specifications ............................................................................................................................. 121
Table 4.33. DTR Specifications .......................................................................................................................................... 121
Table 4.34. PCIe (2.5 Gb/s) ............................................................................................................................................... 121
Table 4.35. PCIe (5 Gb/s) .................................................................................................................................................. 123
Table 4.36. SGMII Rx ......................................................................................................................................................... 124
Table 4.37. Certus-NX sysCONFIG Port Timing Specifications .......................................................................................... 125
Table 4.38. JTAG Port Timing Specifications ..................................................................................................................... 131
Table 4.39. Test Fixture Required Components, Non-Terminated Interfaces .................................................................. 132
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FPGA-DS-02078-1.0
9
Certus-NX Family
Data Sheet
Acronyms in This Document
A list of acronyms used in this document.
Acronym
Definition
AES
BGA
CDR
CRC
DCC
DCS
DDR
DLL
DSP
EBR
ECC
ECDSA
ECLK
FFT
FIFO
FIR
LC
LRAM
LVCMOS
LVDS
LVPECL
Advanced Encryption Standard
Ball Grid Array
Clock and Data Recovery
Cycle Redundancy Code
Dynamic Clock Control
Dynamic Clock Select
Double Data Rate
Delay Locked Loop
Digital Signal Processing
Embedded Block RAM
Error Correction Coding
Elliptic Curve Digital Signature Algorithm
Edge Clock
Fast Fourier Transform
First In First Out
Finite Impulse Response
Logic Cell
Large RAM
Low-Voltage Complementary Metal Oxide Semiconductor
Low-Voltage Differential Signaling
Low Voltage Positive Emitter Coupled Logic
LVTTL
LUT
MLVDS
PCI
PCS
PCLK
PDPR
PFU
PIC
Low Voltage Transistor-Transistor Logic
Look Up Table
Multipoint Low-Voltage Differential Signaling
Peripheral Component Interconnect
Physical Coding Sublayer
Primary Clock
Pseudo Dual Port RAM
Programmable Functional Unit
Programmable I/O Cells
PLL
POR
SCI
SER
SEU
SLVS
SPI
SPR
SRAM
TAP
TDM
Phase Locked Loop
Power On Reset
SerDes Client Interface
Soft Error Rate
Single Event Upset
Scalable Low-Voltage Signaling
Serial Peripheral Interface
Single Port RAM
Static Random-Access Memory
Test Access Port
Time Division Multiplexing
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10
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
1. General Description
The Certus™-NX family of low-power general purpose
FPGAs can be used in a wide range of applications
across multiple markets, and are optimized for bridging
and processing needs in Edge applications. It is built on
the Lattice Nexus™ FPGA platform, using low-power 28
nm FD-SOI technology. It combines the extreme
flexibility of an FPGA with the low power and high
reliability (due to extremely low SER) of FD-SOI
technology, and offers small footprint package options
with a high amount of I/O per mm2. Design security
features such as AES-256 encryption and ECDSA
authentication are also supported.
1.1. Features
Certus-NX supports a variety of interfaces including PCI
Express (Gen1, Gen2), SGMII (Gigabit Ethernet), LVDS,
LVCMOS (0.9–3.3 V), and more.
Processing features of Certus-NX include up to 39k
Logic Cells, 56 multipliers (18 x 18), 2.9 Mb of
embedded memory (consisting of EBR and LRAM
blocks), distributed memory, DRAM interfaces
(supporting DDR3, DDR3L, LPDDR2, and LPDDR3 up to
1066 Mbps × 16 bits data width).
Certus-NX FPGAs support fast configuration of the
reconfigurable SRAM-based logic fabric, and ultra-fast
configuration (under 3 ms) of its programmable
sysI/O™. In addition to the high reliability inherent to
FD-SOI technology (due to its extremely low SER),
active reliability features such as built-in frame-based
SED/SEC (for SRAM-based logic fabric), and ECC (for
EBR and LRAM) are also supported. Dual 12-bit ADCs
are available on-chip for system monitoring functions.
Lattice Radiant™ design software allows large complex
user designs to be efficiently implemented in the
Certus-NX FPGA family. Synthesis library support for
Certus-NX devices is available for popular logic
synthesis tools. Radiant tools use the synthesis tool
output along with constraints from floor planning tools
to place and route the user design for the Certus-NX
device. The tools extract timing from the routing and
back-annotate it into the design for timing verification.
Lattice provides many pre-engineered IP (Intellectual
Property) modules for the Certus-NX family. By using
these configurable soft IP cores as standardized blocks,
you are free to concentrate on the unique aspects of
your design, increasing your productivity.
Programmable architecture
17 k to 39 k logic cells
24 to 56 sysDSP™ blocks (18 x 18 multipliers)
2.5 to 2.9 Mb of embedded memory (EBR,
LRAM)
78 to 192 programmable sysI/O (High
Performance and Wide Range I/O)
Programmable sysI/O supports wide variety of
interfaces
High Performance (HP) I/O on bottom I/O
banks
Supports up to 1.8 V VCCIO
Mixed voltage support (1.0 V, 1.2 V, 1.5 V,
1.8 V)
High-speed differential up to 1.5 Gbps
Supports LVDS, Soft D-PHY (Tx/Rx), LVDS
7:1 (Tx/Rx), SLVS (Tx/Rx), subLVDS (Rx)
Supports SGMII (Gb Ethernet)
Two channels (Tx/Rx) at 1.25 Gbps
Dedicated DDR3/DDR3L and
LPDDR2/LPDDR3 memory support with
DQS logic, up to 1066 Mbps data rate and
x16 bits data width
Wide Range (WR) I/O on left, right, and top
I/O Banks
Supports up to 3.3 V VCCIO
Mixed voltage support (1.2 V, 1.5 V, 1.8 V,
2.5 V, 3.3 V)
Programmable slew rate (slow, med, fast)
Controlled impedance mode
Emulated LVDS support
Hot Socketing Support
Power modes – Low Power, High-Performance
User selectable
Low-Power mode for power and/or thermal
challenges
High-Performance mode for faster processing
Small footprint package options
6 mm × 6 mm package option in both
densities
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FPGA-DS-02078-1.0
11
Certus-NX Family
Data Sheet
*
Two channels of CDR up to 1.25 Gbps to support
SGMII on HP I/O
CDR for RX
10b/8b decoding
Independent Loss of Lock (LOL) detector for
each CDR block
Note: Except caBGA196.
sysCLOCK™ analog PLLs
Three in 39k LC and two in 17k LC device
Six outputs per PLL
Fractional N
Programmable and dynamic phase control
sysDSP enhanced DSP blocks
Hardened pre-adder
Dynamic shift for AI/ML support
Four 18 × 18, eight 9 × 9, two 18 × 36, or
36 × 36 multipliers per block
Advanced 18 × 36, two 18 × 18, or four 8 × 8
MACs per block
Flexible memory resources
Up to 1.5 Mb sysMEM™ Embedded Block RAM
Programmable width
ECC
FIFO
80k to 240k bits distributed RAM
Large RAM Blocks
0.5 Mbits per block
Up to five blocks (2.5 Mb total) per device
SerDes – PCIe Gen2 x1 channel (Tx/Rx) hard IP in
39k LC device
PCIe hard IP supports:
Gen1 and Gen2
Endpoint and Root complex
Multi-function up to four functions
x1 lane
Internal bus interface support
APB control bus
AHB-Lite for data bus
AXI4-streaming
Configuration – Fast, Secure
SPI – x1, x2, x4 up to 150 MHz
Master and Slave SPI support
JTAG
I2C and I3C
Ultrafast I/O configuration for instant-on
support (under 3 ms)
Less than 15 ms full device configuration for
LFD2NX-40
Cryptographic engine
Bitstream encryption – using AES-256
Bitstream authentication – using ECDSA
Hashing algorithms – SHA, HMAC
True Random Number Generator
AES 128/256 Encryption
Single Event Upset (SEU) Mitigation Support
Extremely low Soft Error Rate (SER) due to
FD-SOI technology
Soft Error Detect – Embedded hard macro
Soft Error Correction – Without stopping user
operation
Soft Error Injection – Emulate SEU event to
debug system error handling
Dual ADCs – 1 MSPS, 12-bit SAR, with
Simultaneous Sampling
Three Continuous-time Comparators
System level support
IEEE 1149.1 and IEEE 1532 compliant
Reveal Logic Analyzer
On-chip oscillator for initialization
1.0 V core power supply
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12
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
Table 1.1. Certus-NX Commercial/Industrial Family Selection Guide
Device
Logic Cells*
Embedded Memory (EBR) Blocks (18 kb)
Embedded Memory (EBR) Bits (kb)
Distributed RAM Bits (kb)
Large Memory (LRAM) Blocks
Large Memory (LRAM) Bits (kb) (512 kbits each)
18 X 18 Multipliers
ADC Blocks
450 MHz High Frequency Oscillator
128 kHz Low Power Oscillator
GPLL
PCIe Gen2 Hard IP
Packages (Size, Ball Pitch)
csfBGA121 (6 mm × 6 mm, 0.5 mm)
LFD2NX-17
17k
24
LFD2NX-40
39k
84
432
80
5
2560
24
2
1
1
2
—
1,512
240
2
1024
56
2
1
1
3
1
Wide Range (WR) GPIO (Top/Left/Right Banks)/High Performance
(HP) GPIO (Bottom Banks)/ADC/5G PCIe Lane
23/48/6/0
23/58/0/1
caBGA196 (12 mm × 12 mm, 0.8 mm)
—
92/58/6/0
caBGA256 (14 mm × 14 mm, 0.8 mm)
—
111/74/6/1
LFD2NX-17
17k
LFD2NX-40
39k
*Note:
Logic Cells = LUTs × 1.2 effectiveness.
Table 1.2. Certus-NX Automotive Family Selection Guide
Device
Logic Cells*
Embedded Memory (EBR) Blocks (18 kb)
Embedded Memory (EBR) Bits (kb)
Distributed RAM Bits (kb)
Large Memory (LRAM) Blocks
Large Memory (LRAM) Bits (kb)
18 X 18 Multipliers
ADC Blocks
450 MHz High Frequency Oscillator
128 kHz Low Power Oscillator
GPLL
PCIe Gen2 Hard IP
Packages (Size, Ball Pitch)
csfBGA121 (6 mm × 6 mm, 0.5 mm)
caBGA256 (14 mm × 14 mm, 0.8 mm)
*Note:
24
84
432
1,512
80
240
5
2
2560
1024
24
56
2
2
1
1
1
1
2
3
—
1
Wide Range (WR) GPIO (Top/Left/Right Banks)/High Performance
(HP) GPIO (Bottom Banks)/ADC/5G PCIe Lane
23/48/6/0
23/58/0/1
—
111/74/6/1
Logic Cells = LUTs × 1.2 effectiveness.
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FPGA-DS-02078-1.0
13
Certus-NX Family
Data Sheet
2. Architecture
2.1. Overview
Each Certus-NX device contains an array of logic blocks surrounded by Programmable I/O Cells (PIC). Interspersed
between the rows of logic blocks are rows of sysMEM Embedded Block RAM (EBR) and rows of sysDSP Digital Signal
Processing blocks, as shown in Figure 2.1. The LFD2NX-40 devices have two rows of DSP blocks and contain three rows
of sysMEM EBR blocks. In addition, LFD2NX-40 devices include two Large SRAM blocks. The sysMEM EBR blocks are
large, dedicated 18 kb fast memory blocks and have built-in ECC and FIFO support. Each sysMEM block can be
configured to a single, pseudo dual or true dual port memory in a variety of depths and widths as RAM or ROM. Each
DSP block supports a variety of multiplier and adder configurations with one 108-bit or two 54-bit accumulators
supported, which are the building blocks for complex signal processing capabilities.
Each PIC block encompasses two PIO (PIO pairs) with their respective sysI/O buffers. The sysI/O buffers of the CertusNX devices are arranged in seven banks allowing the implementation of a wide variety of I/O standards. The Wide
Range (WR) I/O banks that are located on the top, left and right sides of the device provide flexible ranges of general
purpose I/O configurations up to 3.3 V VCCIOs. The banks located on the bottom side of the device are dedicated to
High Performance (HP) interfaces such as LVDS, DDR3, LPDDR2, and LPDDR3 supporting up to 1.8 V VCCIOs.
The Programmable Functional Unit (PFU) contains the building blocks for logic, arithmetic, RAM and ROM functions.
The PFU block is optimized for flexibility, allowing complex designs to be implemented quickly and efficiently. Logic
Blocks are arranged in a two-dimensional array. The registers in the PFU and sysI/O blocks in Certus-NX devices can be
configured to be SET or RESET. After power up and device configuration, it enters into user mode with these registers
SET/RESET according to the user design, allowing the device to power up in a known state for predictable system
function.
In addition, Certus-NX devices provide various system level hard IP functional and interface blocks such as PCIe
(LFD2NX-40 only), I2C, SGMII/CDR, and ADC blocks. The PCIe hard IP supports PCIe Generation 2.0. Certus-NX devices
also provide security features to help protect user designs and deliver more robust reliability by offering enhanced
frame based SED/SEC functions.
Other blocks provided include PLLs, DLLs, and configuration functions. The PLL and DLL blocks are located at the
corners of each device. Certus-NX devices also include the Lattice Memory Mapped Interface (LMMI) which is a Lattice
standard to support simple read and write operations to control internal IP.
Every device in the family has a JTAG port. This family also provides an on-chip oscillator and soft error detect
capability. The Certus-NX devices use 1.0 V as their core voltage.
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14
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
PLL
OSC
I/O Bank (Bank 0)
PCIe
Configuration & Security
Large
RAM
I/O Bank
(Bank 7)
I/O Bank
(Bank 1)
Large
RAM
I/O Bank
(Bank 6)
I/O Bank
(Bank 2)
ADC
(2Ch)
CDR
(2Ch)
I/O Bank (Bank 5)
PLL
I/O Bank (Bank 4)
I/O Bank (Bank 3)
PLL
Figure 2.1. Simplified Block Diagram, LFD2NX-40 Device (Top Level)
OSC
I/O Bank (Bank 0)
Configuration and Security
Large
RAM
I/O Bank
(Bank 1)
Large
RAM
Large
RAM
Large
RAM
Large
RAM
ADC
(2Ch)
CDR
(2Ch)
PLL
I/O Bank (Bank 5)
I/O Bank (Bank 4)
I/O Bank (Bank 3)
PLL
Figure 2.2. Simplified Block Diagram, LFD2NX-17 Device (Top Level)
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FPGA-DS-02078-1.0
15
Certus-NX Family
Data Sheet
2.2. PFU Blocks
The core of the Certus-NX device consists of PFU blocks. Each PFU block consists of four interconnected slices
numbered 0–3 as shown in Figure 2.3. Each slice contains two LUTs. All the interconnections to and from PFU blocks
are from routing.
The PFU block can be used to perform Logical, Arithmetic, RAM or ROM functions. Table 2.1 shows the functions each
slice can perform in either Distributed SRAM or non-distributed SRAM modes.
From
Routing
LUT4 &
CARRY
LUT4 &
CARRY
LUT4 &
CARRY
Slice 0
LUT4 &
CARRY
Slice 1
D
FF
LUT4 &
CARRY
D
FF
LUT4 &
CARRY
D
D
FF
D
D
FF
LUT4 &
CARRY
Slice 3
Slice 2
D
FF
LUT4 &
CARRY
FF
FF
D
FF
To
Routing
Figure 2.3. PFU Diagram
2.2.1. Slice
Each slice contains two LUT4s feeding two registers. In Distributed SRAM mode, Slice 0 and Slice 1 are configured as
distributed memory and Slice 2 is not available as it is used to support Slice 0 and Slice 1, while Slice 3 is available as
Logic or ROM. Table 2.1 shows the capability of the slices along with the operation modes they enable. In addition,
each Slice contains logic that allows the LUTs to be combined to perform a LUT5 function. There is control logic to
perform set/reset functions (programmable as synchronous/asynchronous), clock select, chip-select, and wider
RAM/ROM functions.
Table 2.1. Resources and Modes Available per Slice
Slice
Slice 0
Slice 1
Slice 2
Slice 3
PFU (Used as Distributed SRAM)
Resources
Modes
2 LUT4s and 2 Registers
RAM
2 LUT4s and 2 Registers
RAM
2 LUT4s and 2 Registers
RAM
2 LUT4s and 2 Registers
Logic, Ripple, ROM
PFU (Not used as Distributed SRAM)
Resources
Modes
2 LUT4s and 2 Registers
Logic, Ripple, ROM
2 LUT4s and 2 Registers
Logic, Ripple, ROM
2 LUT4s and 2 Registers
Logic, Ripple, ROM
2 LUT4s and 2 Registers
Logic, Ripple, ROM
Figure 2.4 shows an overview of the internal logic of the slice. The registers in the slice can be configured for positive or
negative edge clocking.
Each slice has 17 input signals: 16 signals from routing and one from the carry-chain (from the adjacent slice or PFU).
Three of them are used for FF control and shared between two slices (0/1 or 2/3). There are five outputs: four to
routing and one to carry-chain (to the adjacent PFU). Table 2.2 and Figure 2.4 list the signals associated with all the
slices. Figure 2.5 shows the slice signals that support a LUT5 or two LUT5 functions. F0 can be configured to have a
LUT4 or LUT5 output while F1 is for a LUT4 output.
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16
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
LUT5
and
Carry
Figure 2.4. Slice Diagram
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FPGA-DS-02078-1.0
17
Certus-NX Family
Data Sheet
A1
F1
B1
LUT4
C1
D1
1
F0
0
SEL
A0
B0
LUT4
C0
D0
*Note: In RAM mode, LUT4s use the following signals:
QWD0/1
QWDN0/1
QWAS00~03, QWAS10~13
Figure 2.5. Slice configuration for LUT4 and LUT5
Table 2.2. Slice Signal Descriptions
Function
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
Output
Output
Type
Data signal
Data signal
Data signal
Control signal
Data signal
Control signal
Control signal
Control signal
Inter-PFU signal
Data signals
Data signals
Data signals
Inter-PFU signal
Signal Names
A0, B0, C0, D0
A1, B1, C1, D1
M0, M1
SEL
DI0, DI1
CE
LSR
CLKIN
FCI
F0
F1
Q0, Q1
FCO
Description
Inputs to LUT4
Inputs to LUT4
Direct input to FF from fabric
LUT5 mux control input
Inputs to FF from LUT4 F0/F1 outputs
Clock Enable
Local Set/Reset
System Clock
Fast Carry-in
LUT4/LUT5 output signal
LUT4 output signal
Register outputs
Fast carry chain output
Note: See Figure 2.4 for connection details.
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18
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
2.2.2. Modes of Operation
Slices 0-2 have up to four potential modes of operation: Logic, Ripple, RAM and ROM. Slice 3 is not needed for RAM
mode, it can be used in Logic, Ripple, or ROM modes.
2.2.2.1. Logic Mode
In this mode, the LUTs in each slice are configured as 4-input combinatorial lookup tables. A LUT4 can have 16 possible
input combinations. Any four input logic functions can be generated by programming this lookup table. Since there are
two LUT4s per slice, a LUT5 can be constructed within one slice.
2.2.2.2. Ripple Mode
Ripple mode supports the efficient implementation of small arithmetic functions. In ripple mode, the following
functions can be implemented by each slice:
Addition 2-bit
Subtraction 2-bit
Add/Subtract 2-bit using dynamic control
Up counter 2-bit
Down counter 2-bit
Up/Down counter with asynchronous clear 2-bit using dynamic control
Up/Down counter with preload (sync) 2-bit using dynamic control
Comparator functions of A and B inputs 2-bit
A greater-than-or-equal-to B
A not-equal-to B
A less-than-or-equal-to B
Up/Down counter with A greater-than-or-equal-to B comparator 2-bit using dynamic control
Up/Down counter with A less-than-or-equal-to B comparator 2-bit using dynamic control
Multiplier support Ai×Bj+1 + Ai+1×Bj in one logic cell with 2 logic cells per slice
Serial divider 2-bit mantissa, shift 1bit/cycle
Serial multiplier 2-bit, shift 1bit/cycle or 2bit/cycle
Ripple Mode includes an optional configuration that performs arithmetic using fast carry chain methods. In this
configuration (also referred to as CCU2 mode) two additional signals, Carry Generate and Carry Propagate, are
generated on a per slice basis to allow fast arithmetic functions to be constructed by concatenating Slices.
2.2.2.3. RAM Mode
In this mode, a 16 × 4-bit distributed single or pseudo dual port RAM can be constructed in one PFU using each LUT
block in Slice 0 and Slice 1 as a 16 × 2-bit memory in each slice. Slice 2 is used to provide memory address and control
signals. The Certus-NX devices support distributed memory initialization.
The Lattice design tools support the creation of a variety of different sized memories. Where appropriate, the software
constructs these using distributed memory primitives that represent the capabilities of the PFU. Table 2.3 lists the
number of slices required to implement different distributed RAM primitives. For more information about using RAM in
Certus-NX devices, refer to Memory Usage Guide for Nexus Platform (FPGA-TN-02094).
Table 2.3. Number of Slices Required to Implement Distributed RAM
Number of slices
Note: SPR = Single Port RAM, PDPR = Pseudo Dual Port RAM
SPR 16 X 4
3
PDPR 16 X 4
3
2.2.2.4. ROM Mode
ROM mode uses the LUT logic; hence, Slice 0 through Slice 3 can be used in ROM mode. Preloading is accomplished
through the programming interface during PFU configuration.
For more information, refer to Memory Usage Guide for Nexus Platform (FPGA-TN-02094).
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FPGA-DS-02078-1.0
19
Certus-NX Family
Data Sheet
2.3. Routing
There are many resources provided in the Certus-NX devices to route signals individually or as busses with related
control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) segments.
The Certus-NX family has an enhanced routing architecture that produces a compact design. The Radiant software tool
takes the output of the synthesis tool and places and routes the design.
2.3.1. Clocking Structure
The Certus-NX clocking structure consists of clock synthesis blocks (PLLs), balanced clock tree networks (PCLK & ECLK),
and efficient clock logic modules: Clock Dividers (PCLKDIV and ECLKDIV), Dynamic Clock Selection (DCS), Dynamic Clock
Control (DCC), and DDRDLLs. Each of these functions is described as follows.
2.3.2. Global PLL
The Global PLLs (GPLL) provide the ability to synthesize clock frequencies. The devices in the Certus-NX family support
two or three full-featured General Purpose GPLLs. The architecture of the GPLL is shown in Figure 2.6. A description of
the GPLL functionality follows.
REFCLK is the reference frequency input to the PLL and its source can come from external CLK inputs or from internal
routing. The CLKI input feeds into the input Clock Divider block.
CLKFB is the feedback signal to the GPLL which can come from a path internal to the PLL or from FPGA routing. The
feedback divider is used to multiply the reference frequency and thus synthesize a higher or lower frequency clock
output.
The PLL has six clock outputs CLKOP, CLKOS, CLKOS2, CLKOS3, CLKOS4, and CLKOS5. Each output has its own output
divider, thus allowing the GPLL to generate different frequencies for each output. The output dividers can have a value
from 1 to 128. Each GPLL output can be used to drive the primary clock or edge clock networks.
The setup and hold times of the device can be improved by programming a phase shift into the output clocks which
advances or delays the output clock with reference to the un-shifted output clock. This phase shift can be either
programmed during configuration or can be adjusted dynamically using the DIRSEL, DIR, DYNROTATE, and LOADREG
ports.
The LOCK signal is asserted when the GPLL determines it has achieved lock and de-asserted if a loss of lock is detected.
The lock signal is asynchronous to the PLL clock outputs.
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20
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
(To bypass muxes)
Figure 2.6. General Purpose PLL Diagram
For more details on the PLL, you can refer to the sysCLOCK PLL Design and Usage Guide for Nexus Platform (FPGA-TN02095).
2.3.3. Clock Distribution Network
There are two main clock distribution networks for any member of the Certus-NX product family, namely Primary Clock
(PCLK) and Edge Clock (ECLK). These clock networks can be driven from many different sources, such as Clock Pins, PLL
outputs, DLLDEL outputs, Clock Divider outputs, SerDes/PCS clocks and user logic. There are Clock Divider blocks
(ECLKDIV and PCLKDIV) to provide a slower clock from these clock sources.
Certus-NX supports glitchless Dynamic Clock Control (DCC) for the PCLK Clock to save dynamic power. There are also
Dynamic Clock Selection logic to allow glitchless selection between two clocks for the PCLK network (DCS).
An Overview of the Clocking Network is shown in Figure 2.7 for the Certus-NX device. The shaded blocks (PCIe and
upper left PLL) are not available in the 17k Logic Cell device.
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FPGA-DS-02078-1.0
21
Certus-NX Family
Data Sheet
PLL
BANK 0 PCLK
OSC
TMID
BANK 1 PCLK
RMID
LMID
16 DCC
12 DCC
BANK 2 PCLK
18 DCC
BMID
PLL
BANK 5 PCLK
ECLK
BANK 4 PCLK
ECLK
BANK 3 PCLK
ECLK
PLL
Figure 2.7. Clocking
2.3.4. Primary Clocks
The Certus-NX device family provides low-skew, high fan-out clock distribution to all synchronous elements in the FPGA
fabric through the Primary Clock Network. The Certus-NX PCLK clock network is a balanced clock structure which is
designed to minimize the clock skew across all destinations in the FPGA core.
The primary clock network is divided into two clock domains depending on the device density. Each of these domains
has 16 clocks that can be distributed to the fabric in the domain.
The Lattice Radiant software can automatically route each clock to one of the domains up to a maximum of 16 clocks
per domain. You can change how the clocks are routed by specifying a preference in the Lattice Radiant software to
locate the clock to a specific domain. The Certus-NX device provides you with a maximum of 64 unique clock input
sources that can be routed to the primary Clock network.
Primary clock sources are:
Dedicated clock input pins
PLL outputs
PCLKDIV, ECLKDIV outputs
Internal FPGA fabric entries (with minimum general routing)
SGMII-CDR, PCIe clocks
OSC clock
These sources are routed to each of four clock switches called a Mid Mux (LMID, RMID, TMID, BMID). The outputs of
the Mid MUX are routed to the center of the FPGA where additional clock switches (DSC_CMUX) are used to route the
primary clock sources to primary clock distribution to the Certus-NX fabric. These routing muxs are shown in
Figure 2.7. There are potentially 64 unique clock domains that can be used in the largest Certus-NX Device. For more
information about the primary clock tree and connections, refer to sysCLOCK PLL Design and Usage Guide for Nexus
Platform (FPGA-TN-02095).
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22
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
2.3.5. Edge Clock
Certus-NX FPGAs have a number of high-speed edge clocks that are intended for use with the PIO in the
implementation of high-speed interfaces. There are four (4) ECLK networks per bank I/O on the Bottom side of the
device. The Edge clock network is powered by a separate power domain (to reduce power noise injection from the core
and reduce overall noise induced jitter) while controlled by the same logic that gates the FPGA core and PCLK domains
for power management.
Each Edge Clock can be sourced from the following:
Dedicated PIO Clock input pins (PCLK)
DLLDEL output (PIO Clock delayed by 90°)
PLL outputs (CLKOP, CLKOS, CLKOS2, CLKOS3, CLKOS4, and CLKOS5)
Internal Nodes
Figure 2.8 illustrates the various ECLK sources. Bank 3 is shown in the example. Bank 4 and Bank 5 are similar.
Bank 3 PCLK Pin (even)
2
From Banks 4, 5
ECLKSYNC
DLLDEL
Bottom
Left GPLL
6
Bank 3 ECLK Tree
From Fabric
ECLKSYNC
ECLKDIV
Bottom
Right GPLL
Bank 3 PCLK Pin (odd)
BMID
6
2
To Banks 4,5 Muxes
Figure 2.8. Edge Clock Sources per Bank
The edge clocks have low injection delay and low skew. They are typically used for DDR Memory or Generic DDR
interfaces. For detailed information on Edge Clock connections, refer to sysCLOCK PLL Design and Usage Guide for
Nexus Platform (FPGA-TN-02095).
2.3.6. Clock Dividers
The Certus-NX devices have two distinct types of clock divider, Primary and Edge. There are from one (1) to eight (8)
Primary Clock Dividers (PCLKDIV) and which are located in the DCS_CMUX block(s) at the center of the device. There
are twelve (12) ECLKDIV dividers per device, locate near the bottom high-speed I/O banks.
The PCLKDIV supports ÷2, ÷4, ÷8, ÷16, ÷32, ÷64, ÷128, and ÷1 (bypass) operation. The PCLKDIV is fed from a DCSMUX
within the DCS_CMUX block. The clock divider output drives one input of the DCS Dynamic Clock Select within the
DSC_CMUX block. The Reset (RST) control signal is asynchronous and forces all outputs to low. The divider output starts
at next cycle after the reset is synchronously released. The PCLKDIV is shown in context in Figure 2.9.
The ECLKDIV is intended to generate a slower-speed system clock from a high-speed edge clock. The block operates in
a ÷2, ÷3.5, ÷4, or ÷5 mode and maintains a known phase relationship between the divided down clock and the highspeed clock based on the release of its reset signal. The ECLKDIV can be fed from selected PLL outputs, external primary
clock pins (with or without DLLDEL Delay) or from routing. The clock divider outputs feed into the Bottom Mid-mux
(BMID). The Reset (RST) control signal is asynchronous and forces all outputs to low. The divider output starts at next
cycle after the reset is synchronously released.
The ECLKDIV block is shown in context in Figure 2.8. For further information on clock dividers, refer to sysCLOCK PLL
Design and Usage Guide for Nexus Platform (FPGA-TN-02095).
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FPGA-DS-02078-1.0
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Certus-NX Family
Data Sheet
2.3.7. Clock Center Multiplexer Blocks
All clock sources are selected and combined for primary clock routing through the Dynamic Clock Selector Center
Multiplexer logic (DCS_CMUX). There are one (1) or two (2) DCS_CMUX blocks per device. Each DCS_CMUX block
contains 2 DCSMUX blocks, 1 PCLKDIV, 1 DCS block, and 1 or 2 CMUX blocks. See Figure 2.9 for a representative
DCS_CMUX block diagram.
The heart of the DCS_CMUX is the Center Multiplexer (CMUX) block. It can accept up to 64 input clock sources (Midmuxes (RMID, LMID, TMIC, BMID) and DCC) and to drive up to 16 primary clock trunk lines.
Up to two (2) clock inputs to the DCS_CMUX can be routed through a Dynamic Clock Select block then routed to the
CMUX. One (1) input to the DCS can be optionally divided by the Primary Clock Divider (PCLKDIV). For more information
about the DCS_CMUX, refer to sysCLOCK PLL Design and Usage Guide for Nexus Platform (FPGA-TN-02095).
16
16
16
16x (partial
16x (partial
(16/64):1)
(16/64):1)
CMUX
CMUX
16
DCS_CMUX
dcs2cmux0
DCS
62
dcs1
dcs0
PCLKDIV
DCMUX
(62:1)
DCMUX
(62:1)
62
62
62
62
62
Figure 2.9. DCS_CMUX Diagram
2.3.8. Dynamic Clock Select
The Dynamic Clock Select (DCS) is a smart multiplexer function available in the primary clock routing. It switches
between two independent input clock sources. Depending on the operational mode, it switches between two (2)
independent input clock sources either with or without any glitches. This is achieved regardless of when the select
signal is toggled. Both input clocks must be running to achieve a functioning glitchless DCS output clock, but running
clocks are not required when used as a non-glitchless normal clock multiplexer.
There are one (1) or two (2) DCS blocks per device that feed all clock domains. The DCS blocks are located in the
DCS_MUX block. The inputs to the DCS blocks come from MIDMUX outputs and user logic clocks via DCC elements. The
DCS elements are located at the center of the PLC array core. The output of the DCS is connected to the inputs of
Primary Clock Center MUXs (CMUX).
Figure 2.10 shows the timing waveforms of the default DCS operating mode. The DCS block can be programmed to
other modes. For more information about the DCS, refer to sysCLOCK PLL Design and Usage Guide for Nexus Platform
(FPGA-TN-02095).
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24
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
CLK0
clk0
pos
CLK1
clk1
pos
SEL
clk1
neg
clk0
neg
DCSOUT
Figure 2.10. DCS Waveforms
2.3.9. Dynamic Clock Control
The Dynamic Clock Control (DCC), Domain Clock enable/disable feature allows internal logic control of the domain
primary clock network. When a clock network is disabled, the clock signal is static and does not toggle. All the logic fed
by that clock also does not toggle, reducing the overall power consumption of the device. The disable function is
glitchless, and does not increase the clock latency to the primary clock network.
Four additional DCC elements control the clock inputs from the Certus-NX domain logic to the Center MUX elements
(DSC_CMUX).
This DCC controls the clock sources from the Primary CLOCK MIDMUX before they are fed to the Primary Center MUXs
that drive the domain clock network. For more information about the DCC, refer to sysCLOCK PLL Design and Usage
Guide for Nexus Platform (FPGA-TN-02095).
2.3.10. DDRDLL
Certus-NX has two identical DDRDLL blocks, located in the lower left and lower right corners of the device. Each
DDRDLL (master DLL block) can generate a 9 bit phase shift value corresponding to a 90-degree phase shift of the
reference clock input and provide this value to every DQS block and DLLDEL slave delay element. The reference clock
can be either from a PLL or an input pin. The DQSBUF uses this value to control the delay of the DQS inputs from a DDR
memory interface to achieve a 90-degree shift in order to clock DQ inputs at the center of the data eye.
The value is also sent to another slave DLL, DLLDEL, that takes a primary clock input and generates a 90-degree
shifted clock output to drive the clocking structure. This is useful in an edge-aligned Generic DDR interface, where
90-degree clocking needs to be created. Not all primary clock inputs have associated DLLDEL control. Figure 2.11
shows DDRDLL connectivity to a DLLDEL block (connectivity to DQSBUF blocks is similar).
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FPGA-DS-02078-1.0
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Certus-NX Family
Data Sheet
To both BMID and
ECLKINMUX
+
-
DLLDEL
Left DDRDLL
code2
code1
PCLK Input
9
Right DDRDLL
9
Figure 2.11. DLLDEL Functional Diagram
Each DDRDLL can generate a delay value based on the reference clock frequency. The slave DLLs (DQSBUF and DLLDEL)
use the value (code) to either create phase shifted inputs from the DDR memory or create a 90-degree shifted clock.
Figure 2.12 shows the connections between the DDRDLL and the slave DLLs.
Left
DDRDLL
Right
DDRDLL
Digital Delay Code (L)
Digital Delay Code (R)
Refclk Sel
DLLDEL
Refclk Sel
DLLDEL
BANK5 ECLK
DQS0
DQS1
BANK4 ECLK
DLLDEL
DQS0
DQS1
BANK3 ECLK
Figure 2.12. Certus-NX DDRDLL Architecture
2.4. SGMII Clock Data Recovery (CDR)
The Certus-NX device includes two hardened CDR (Clock & Data Recovery) components. The CDRs enable SGMII (Serial
Gigabit Media Independent Interface) solutions. There are three main blocks in each CDR: the CDR, deserializer, and
FIFO. Each CDR features two loops. The first loop is locked to the reference clock. Once locked, the loop switches to the
data path loop where the CDR tracks the data signals to generate the correcting signals needed to achieve and
maintain phase lock with the data. The data is then passed through a deserializer, which deserialize the data to 10-bit
parallel data. The 10-bit parallel data is then sent to the FIFO bridge, which allows the CDR to interface with the rest of
the FPGA.
Figure 2.13 shows a block diagram of the SGMII CDR IP.
The two hardened blocks are located at the bottom left of the chip and uses the high speed I/O Bank 5 for the
differential pair input. It is recommended that the reference clock should be entered through a GPIO that has
connection to the PLL on the lower left corner as well.
This feature is only available in the commercial and industrial grade devices.
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26
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
SGMII CDR IP
lmmi_dk
lmmi_request
lmmi_wrdn
lmmi_offset[3:0]
lmmi_rdata[7:0]
lmmi_rdata_valid
lmmi_ready
lmmi_wdata[7:0]
lmmi_reset
ip_ready
sgmii_cdr_icnst
sgmii_in
DUAL_LOOP
CDR
sgmii_rxd
rxd
rxd_des
DESERIALIZER
FIFO
rclk_des
dco_calib_rst
dco_facq_rst
rrst
sgmii_pclk
sgmii_refclk(125 MHz)
sgmii_rclk
Figure 2.13. SGMII CDR IP
2.5. sysMEM Memory
The Certus-NX devices contain a number of sysMEM Embedded Block RAM (EBR). The EBR consists of an 18 kb RAM
with memory core, dedicated input registers and output registers as well as optional pipeline registers at the outputs.
Each EBR includes functionality to support true dual-port, pseudo dual-port, single-port RAM, ROM and built in FIFO. In
Certus-NX, unused EBR blocks is powered down to minimize power consumption.
2.5.1. sysMEM Memory Block
The sysMEM block can implement single port, dual port or pseudo dual port memories. Each block can be used in a
variety of depths and widths as listed in Table 2.4. FIFOs can be implemented using the built in read and write address
counters and programmable full, almost full, empty and almost empty flags. The EBR block facilitates parity checking by
supporting an optional parity bit for each data byte. EBR blocks provide byte-enable support for configurations with 18bit and 36-bit data widths. For more information, refer to Memory Usage Guide for Nexus Platform (FPGA-TN-02094).
EBR also provides a build in ECC engine. The ECC engine supports a write data width of 32 bits and it can be cascaded
for larger data widths such as x64. The ECC parity generator creates and stores parity data for each 32-bit word written.
When a read operation is performed, it compares the data with its associated parity data and report back if any Single
Event Upset (SEU) event has disturbed the data. Any single bit data disturb is automatically corrected at the data
output. In addition, two dedicated error flags indicate if a single-bit or two-bit error has occurred.
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FPGA-DS-02078-1.0
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Certus-NX Family
Data Sheet
Table 2.4. sysMEM Block Configurations
Memory Mode
Single Port
Configurations
16,384 × 1
8,192 × 2
4,096 × 4
2,048 × 9
1,024 × 18
512 × 36
True Dual Port
16,384 × 1
8,192 × 2
4,096 × 4
2,048 × 9
1,024 × 18
Pseudo Dual Port
16,384 × 1
8,192 × 2
4,096 × 4
2,048 × 9
1,024 × 18
512 × 36
2.5.2. Bus Size Matching
All of the multi-port memory modes support different widths on each of the ports (except ECC mode which only
supports a write data width of 32 bits). The RAM bits are mapped LSB word 0 to MSB word 0, LSB word 1 to MSB word
1, and so on. Although the word size and number of words for each port varies, this mapping scheme applies to each
port.
2.5.3. RAM Initialization and ROM Operation
If desired, the contents of the RAM can be pre-loaded during device configuration. By preloading the RAM block during
the chip configuration cycle and disabling the write controls, the sysMEM block can also be utilized as a ROM.
2.5.4. Memory Cascading
Larger and deeper blocks of RAM can be created using EBR sysMEM Blocks. Typically, the Lattice design tools cascade
memory transparently, based on specific design inputs.
2.5.5. Single, Dual and Pseudo-Dual Port Modes
In all the sysMEM RAM modes, the input data and address for the ports are registered at the input of the memory
array. The output data of the memory is optionally registered at the output.
2.5.6. Memory Output Reset
The EBR utilizes latches at the A and B output ports. These latches can be reset asynchronously or synchronously. RSTA
and RSTB are local signals, which reset the output latches associated with Port A and Port B, respectively. The Global
Reset (GSRN) signal can reset both ports. The output data latches and associated resets for both ports are as shown in
Figure 2.14. The optional Pipeline Registers at the outputs of both ports are also reset in the same way.
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28
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
Memory Core
D
SET
Q
Port A[17:0]
LCLR
Output Data
Latches
D
SET
Q
Port B[17:0]
LCLR
RSTA
RSTB
GSRN
Programmable Disable
Figure 2.14. Memory Core Reset
For further information on the sysMEM EBR block, see the list of technical documentation in the References section.
2.6. Large RAM
The Certus-NX device includes additional memory resources in the form of Large Random-Access Memory (LRAM)
blocks.
The LRAM is designed to work as Single-Port RAM, Dual-Port RAM, Pseudo Dual-Port RAM, and ROM memories. It is
meant to function as additional memory resources for you beyond what is available in the EBR and PFU.
Each individual Large RAM block contains 0.5 Mbits or megabits of memory, and has a programmable data width of up
to 32 bits. Cascading Large RAM blocks allows data widths of up to 64 bits. Additionally, there is the ability to use either
Error Correction Coding (ECC) or byte enable.
2.7. sysDSP
The Certus-NX family provides an enhanced sysDSP architecture, making it ideally suited for low-cost, highperformance Digital Signal Processing (DSP) applications. Typical functions used in these applications are Finite Impulse
Response (FIR) filters, Fast Fourier Transforms (FFT) functions, Correlators, Reed-Solomon/Turbo/Convolution encoders
and decoders. These complex signal processing functions use similar building blocks such as multiply-adders and
multiply-accumulators.
2.7.1. sysDSP Approach Compared to General DSP
Conventional general-purpose DSP chips typically contain one to four (Multiply and Accumulate) MAC units with fixed
data-width multipliers; this leads to limited parallelism and limited throughput. Their throughput is increased by higher
clock speeds. In the Certus-NX device family, there are many DSP blocks that can be used to support different data
widths. This allows you to use highly parallel implementations of DSP functions. You can optimize DSP performance
versus area by choosing appropriate levels of parallelism. Figure 2.15 compares the fully serial implementation to the
mixed parallel and serial implementation.
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FPGA-DS-02078-1.0
29
Certus-NX Family
Data Sheet
Operand
A
Operand
A
Operand
B
Operand
A
Operand
B
Operand
B
Operand
B
X
Single
Multiplier
Operand
A
X
M loops
Multiplier
0
X
m/k
loops
X
Multiplier
1
Multiplier
k
Accumulator
(k adds)
Function Implemented in General
Purpose DSP
+
m/k
accumulate
Output
Function Implemented in
Certus-NX
Figure 2.15. Comparison of General DSP and Certus-NX Approaches
2.7.2. sysDSP Architecture Features
The Certus-NX sysDSP block contains two sysDSP slices. The Certus-NX sysDSP Slice has been significantly enhanced to
provide functions needed for advanced processing applications. These enhancements provide improved flexibility and
resource utilization.
The Certus-NX sysDSP block (two sysDSP slices) supports many functions that include the following:
Symmetry support. The primary target application is wireless. 1D Symmetry is useful for many applications that
use FIR filters when their coefficients have symmetry or asymmetry characteristics. The main motivation for using
1D symmetry is cost/size optimization. The expected size reduction is up to 2x.
Odd Mode – Filter with Odd number of taps
Even Mode – Filter with Even number of taps
Two dimensional (2D) Symmetry Mode – Supports 2D filters for mainly video applications
Dual-multiplier architecture. Lower accumulator overhead to half and the latency to half compared to single
multiplier architecture.
Fully cascadable DSP across slices. Support for symmetric, asymmetric and non-symmetric filters.
Multiply (36 × 36, two 18 × 36, four 18 × 18, or eight 9 × 9)
Multiply Accumulate (supports one 18 × 36 multiplier result accumulation, two 18 × 18 multiplier result
accumulation or four 9 × 9 multiplier result accumulation)
Two Multiplies feeding one Accumulate per cycle for increased processing with lower latency (two 18 × 18
Multiplies feed into an accumulator that can accumulate up to 54 bits)
Pipeline registers
1D Symmetry support. The coefficients of FIR filters have symmetry or negative symmetry characteristics.
Odd Mode – Filter with Odd number of taps
Even Mode – Filter with Even number of taps
2D Symmetry support. The coefficients of 2D FIR filters have symmetry or negative symmetry characteristics.
3 × 3 and 3 × 5 – Internal DSP Slice support
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30
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
5 × 5 and larger size 2D blocks – Semi internal DSP Slice support
Flexible saturation and rounding options to satisfy a diverse set of applications situations
Flexible cascading DSP blocks
Minimizes fabric use for common DSP functions
Enables implementation of FIR Filter or similar structures using dedicated sysDSP slice resources only
Provides matching pipeline registers
Can be configured to continue cascading from one row of sysDSP slices to another for longer cascade chains
RTL Synthesis friendly synchronous reset on all registers, while still supporting asynchronous reset for legacy users
Dynamic MUX selection to allow Time Division Multiplexing (TDM) of resources for applications that require
processor-like flexibility that enables different functions for each clock cycle
For most cases, as shown in Figure 2.16, the Certus-NX sysDSP block is backwards-compatible with the LatticeECP3™
sysDSP block, such that, legacy applications can be targeted to Certus-NX sysDSP. Figure 2.16 shows the diagram of
sysDSP block.
Input
B1
Input
C
Input
B2
9+9
Input
A1
REG
Input
A2
Input
B1
Input
C
Input
B2
9+9
Input
A1
REG
Input
A2
9x9
Input
B1
Input
C
Input
B2
9+9
Input
A1
REG
Input
A2
9x9
Input
C
Input
B2
9+9
Input
A1
REG
Input
A2
9x9
18 X 18
Input
B1
9x9
18 X 18
Input
B1
Input
C
Input
B2
9+9
Input
A1
REG
Input
A2
Input
B1
Input
C
Input
B2
9+9
Input
A1
REG
Input
A2
9x9
Input
B1
Input
C
Input
A1
REG
Input
A2
9x9
Input
C
9+9
Input
B2
9+9
Input
A1
REG
Input
A2
9x9
18 X 18
18 X 36 (CSA)
Input
B2
Input
B1
9x9
18 X 18
18 X 36 (CSA)
36 X 36 (CSA)
REG 18
REG 18
REG 18
REG 18
REG 18
REG 18
REG 18
ACC54
ACC54
Output Register
Output Register
REG 18
Note : All Registers inside the DSP Block are Bypassable via Configuration Setting
Figure 2.16. Certus-NX DSP Functional Block Diagram
The Certus-NX sysDSP block supports the following basic elements.
MULT (Multiply)
MAC (Multiply, Accumulate)
MULTADDSUB (Multiply, Addition/Subtraction)
MULTADDSUBSUM (Multiply, Addition/Subtraction, Summation)
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FPGA-DS-02078-1.0
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Certus-NX Family
Data Sheet
Table 2.5 shows the capabilities of Certus-NX sysDSP block versus the above functions.
Table 2.5. Maximum Number of Elements in a sysDSP block
Width of Multiply
MULT
MAC
MULTADDSUB
MULTADDSUBSUM
x9
8
2
2
2
x18
4
2
2
2
x36
1
—
—
—
Some options are available in the four elements. The input register in all the elements can be directly loaded or can be
loaded as a shift register from previous operand registers. By selecting dynamic operation, the following operations are
possible:
In the Add/Sub option, the Accumulator can be switched between addition and subtraction on every cycle.
The loading of operands can switch between parallel and serial operations.
For further information, refer to sysDSP Usage Guide for Nexus Platform (FPGA-TN-02096).
2.8. Programmable I/O (PIO)
The programmable logic associated with an I/O is called a PIO. The individual PIO are connected to their respective
sysI/O buffers and pads. In Certus-NX devices, the PIO are assembled into groups of two PIO cells called a
Programmable I/O Cell or PIC. The PICs are placed on all four sides of the device.
On all the Certus-NX devices, two adjacent PIO can be combined to provide a complementary output driver pair.
2.9. Programmable I/O Cell (PIC)
The programmable I/O cells (PIC) provides I/O function and necessary gearing logic associated with PIO. Certus-NX
consists of base PIC and gearing PIC.
Base PICs contain three blocks: an input register block, output register block, and tri-state register block. These blocks
contain registers for operating in a variety of modes along with the necessary clock and selection logic. Base PICs cover
the top and left/right bank. Gearing PICs contain gearing logic and edge monitor used for locating the center of data
window. Gearing PICs cover the bottom banks to support DDR operation.
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32
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
1 PIC
PIO A
Input
Register
Block
Output and
Tristate
Register
Block
Core
Logic/
Routing
Pin
A
Input and Output
Gearbox
PIO B
Input
Register
Block
Output and
Tristate
Register
Block
Pin
B
Figure 2.17. Group of Two High Performance Programmable I/O Cells
1 PIC
PIO A
Input
Register
Block
Output and
Tristate
Register
Block
Pin
A
Core
Logic/
Routing
PIO B
Input
Register
Block
Output and
Tristate
Register
Block
Pin
B
Figure 2.18. Wide Range Programmable I/O Cells
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FPGA-DS-02078-1.0
33
Certus-NX Family
Data Sheet
2.9.1. Input Register Block
The input register blocks for the PIO on all edges contain delay elements and registers that can be used to condition
high-speed interface signals before they are passed to the device core. In addition, the input register blocks for the PIO
on the bottom edges include built-in FIFO logic to interface to DDR and LPDDR memory.
The Input register block on the bottom side includes gearing logic and registers to implement IDDRX1, IDDRX2, IDDRX4,
IDDRX5 gearing functions. With two PICs sharing the DDR register path, it can also implement the IDDRX71 function
used for 7:1 LVDS interfaces. It uses three sets of registers – shift, update, and transfer to implement gearing and the
clock domain transfer. The first stage registers sample the high-speed input data by the high-speed edge clock on its
rising and falling edges. The second stage registers perform data alignment based on the control signals. The third
stage pipeline registers pass the data to the device core synchronized to the low-speed system clock. For more
information on gearing function, refer to Certus-NX High-Speed I/O Interface (FPGA-TN-02216).
2.9.2.1. Input FIFO
The Certus-NX PIO has a dedicated input FIFO per single-ended pin for input data register for DDR Memory interfaces.
The FIFO resides before the gearing logic. It transfers data from DQS domain to continuous ECLK domain. On the Write
side of the FIFO, it is clocked by DQS clock, which is the delayed version of the DQS Strobe signal from DDR memory. On
the Read side of FIFO, it is clocked by ECLK. ECLK may be any high-speed clock with identical frequency as DQS (the
frequency of the memory chip). Each DQS group has one FIFO control block. It distributes FIFO read/write pointers to
every PIC in same DQS group. DQS Grouping and the DQS Control Block is described in DDR Memory Support section.
Table 2.6. Input Block Port Description
Name
D
Q[1:0]/Q[3:0]/Q[6:0]/Q[7:0]/Q[9:0]
RST
SCLK
ECLK
DQS
ALIGNWD
Type
Input
Output
Input
Input
Input
Input
Input
Description
High Speed Data Input
Low Speed Data to the device core
Reset to the Output Block
Slow Speed System Clock
High Speed Edge Clock
Clock from DQS control Block used to clock DDR memory data
Data Alignment signal from device core.
Figure 2.19 shows the input register block for the PIO on the top, left, and right edges.
D
INCK
INFF
Programmable
Delay Cell
Q
INFF
SCLK
RST
IDDRX1
Q[1:0]
Figure 2.19. Input Register Block for PIO on Top, Left, and Right Sides of the Device
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34
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
Figure 2.20 shows the input register block for the PIO located on the bottom edge.
IN CK
IN FF
Programmable
D
Delay Cell
IN FF
Q
Generic
IDDRX1
IDDRX2
FIFO
IDDRX4
Delayed DQS
ECLK
Q[1:0]/
IDDRX5
Q[3:0]/
Q[6:0]*/
IDDRX71*
Q[7:0]/
Q[9:0]
ECLK
Memory
IDDRX2
SCLK
RST
ALIGNWD
*For 7:1 LVDS interface only. It is required to use PIO pair pins (PIOA/B or PIOC/D).
Figure 2.20. Input Register Block for PIO on Bottom Side of the Device
2.9.2. Output Register Block
The output register block registers signals from the core of the device before they are passed to the sysI/O buffers.
The Certus-NX output data path has programmable registers and output gearing logic. On the bottom side, the output
register block can support 1x, 2x, x4, x5, and 7:1 gearing enabling high speed DDR and DDR memory interfaces. On the
top, left, and right sides, the banks support 1x gearing. The Certus-NX output data path diagram is shown in Figure
2.21. The programmable delay cells are also available in the output data path.
For a detailed description of the output register block modes and usage, you can refer to Certus-NX High-Speed I/O
Interface (FPGA-TN-02216).
Programmable
Delay Cell
D
OUTFF
RST
SCLK
D[1:0]
Q
Generic
ODDRX1
Figure 2.21. Output Register Block on Top, Left, and Right Sides
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FPGA-DS-02078-1.0
35
Certus-NX Family
Data Sheet
Programmable
Delay Cell
D
Q
OUTFF
RST
Generic
ODDRX1/
ODDRX2/
ODDRX4
ODDRX5
ODDR71*
SCLK
ECLK
DQSW
DQSW270
Memory
Q[1:0]/
ODDRX2
OSHX2
Q[3:0]/
Q[6:0]*/
Q[7:0]/
Q[9:0]
*For 7:1 LVDS interface only. It is required to use PIO pair pins PIOA/B.
Figure 2.22. Output Register Block on Bottom Side
Table 2.7. Output Block Port Description
Name
Type
Description
Q
Output
D
Input
High Speed Data Output
Data from core to output SDR register
Q[1:0]/Q[3:0]/Q[6:0]/Q[7:0]/Q[9:0]
Input
Low Speed Data from device core to output DDR register
RST
Input
Reset to the Output Block
SCLK
Input
Slow Speed System Clock
ECLK
Input
High Speed Edge Clock
DQSW
Input
Clock from DQS control Block used to generate DDR memory DQS output
DQSW270
Input
Clock from DQS control Block used to generate DDR memory DQ output
2.10. Tri-state Register Block
The tri-state register block registers tri-state control signals from the core of the device before they are passed to the
sysI/O buffers. The block contains a register for SDR operation. In SDR, the TD input feeds one of the flip-flops that then
feeds the output. In DDR, operations used mainly for DDR memory interfaces can be implemented on the bottom side
of the device. Here, two inputs feed the tri-state registers clocked by both ECLK and SCLK.
Figure 2.23 and Figure 2.24 show the Tri-state Register Block functions on the device. For a detailed description of the
tri-state register block modes and usage, you can refer to Certus-NX High-Speed I/O Interface (FPGA-TN-02216).
TQ
TD
RST
SCLK
TSFF
Figure 2.23. Tri-state Register Block on Top, Left, and Right Sides
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36
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
TQ
TD
TSFF
RST
SCLK
ECLK
THSX2
DQSW
DQSW270
T[1:0]
Figure 2.24. Tri-state Register Block on Bottom Side
Table 2.8. Tri-state Block Port Description
Name
Type
Description
TD
Input
Tri-state Input to Tri-state SDR Register
RST
Input
Reset to the Tri-state Block
TD[1:0]
Input
Tri-state input to TSHX2 function
SCLK
Input
Slow Speed System Clock
ECLK
Input
High Speed Edge Clock
DQSW
Input
Clock from DQS control Block used to generate DDR memory DQS output
DQSW270
Input
Clock from DQS control Block used to generate DDR memory DQ output
TQ
Output
Output of the Tri-state block
2.11. DDR Memory Support
2.11.1. DQS Grouping for DDR Memory
Certain PICs have additional circuitry to allow the implementation of high-speed source synchronous and DDR3/DDR3L,
LPDDR2 or LPDDR3 memory interfaces. The support varies by the edge of the device as detailed below.
The Bottom bank PIC have fully functional elements supporting DDR3/DDR3L, LPDDR2, or LPDDR3 memory interfaces.
Every 16 PIO on the bottom side are grouped into one DQS group, as shown in Figure 2.25. Within each DQS group,
there are two pre-placed pins for DQS and DQS# signals. The rest of the pins in the DQS group can be used as DQ
signals and DM signal. The number of pins in each DQS group bonded out is package dependent. DQS groups with less
than 11 pins bonded out can only be used for LPDDR2/3 Command/ Address busses. In DQS groups with more than 11
pins bonded out, up to two pre-defined pins are assigned to be used as virtual VCCIO, by driving them high to make
extra connections to the VCCIO power supply. These soft connections to VCCIO help reduce SSO noise. For details, refer
to Certus-NX High-Speed I/O Interface (FPGA-TN-02216).
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FPGA-DS-02078-1.0
37
Certus-NX Family
Data Sheet
DQS
Pad A (T)
Pad A
sysIO Buffer
sysIO Buffer
Pad B
PIO A
PIO A
sysIO Buffer
Pad A (T)
Pad B (C)
PIO B
sysIO Buffer
Pad B (C)
sysIO Buffer
PIO A
sysIO Buffer
PIO B
PIO B
Pad A (T)
Pad A
sysIO Buffer
Pad B (C)
sysIO Buffer
sysIO Buffer
Pad A
PIO A
PIO A
sysIO Buffer
Pad B
Pad B
PIO B
sysIO Buffer
Pad A (T)
sysIO Buffer
PIO A
sysIO Buffer
Pad B (C)
PIO B
PIO B
sysIO Buffer
Pad A
Delay
PIO B
sysIO Buffer
Pad B
DQSBUF
PIO A
sysIO Buffer
PIO A
PIO B
Figure 2.25. DQS Grouping on the Bottom Edge
2.11.2. DLL Calibrated DQS Delay and Control Block (DQSBUF)
To support DDR memory interfaces (DDR3/DDR3L, LPDDR2/3), the DQS strobe signal from the memory must be used to
capture the data (DQ) in the PIC registers during memory reads. This signal is output from the DDR memory device
aligned to data transitions and must be time shifted before it can be used to capture data in the PIC. This time shift is
achieved by using the DQSBUF programmable delay line in the DQS Delay Block (DQS read circuit). The DQSBUF is
implemented as a slave delay line and works in conjunction with a master DDRDLL.
This block also includes a slave delay line to generate delayed clocks used during writes to generate DQ and DQS with
correct phases within one DQS group. There is a third delay line inside this block used to provide write leveling for DDR
write if needed.
Each of the read and write side delays can be dynamically shifted using margin control signals from the core logic.
The FIFO Control Block include here generates the Read and Write Pointers for the FIFO inside the Input Register Block.
These pointers are generated to control the DQS to ECLK domain crossing using the FIFO module.
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38
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
BURST_DET
DQS
Preamble/Postamble Management
READ[1:0]
READ_CLK_SEL[2:0]
FIFO Control and Data Valid
Generation
SCLK
ECLK
WRPNTR[2:0]
RDPNTR[2:0]
DATAVALID
Slave Delay Line (RD) with
Adjustment/Margin Test
RD_CODN, RD_DIRECTION, RD_MOVE
DQSR90
Rd_cout
WR_COUT
WRITE_LEVELING_LOADN
WRITE_LEVELING_DIRECTION
WRITE_LEVELING_MOVE
Slave Delay (WR) with
Adjustment/Margin Test and Write Leveling
DQSW270
DQSW
WR_LOADN, WR_DIRECTION, WR_MOVE
DELAY CODE[8:0]
RST
DONE_GWE
GSR
DELAY CODE[8:0]
Figure 2.26. DQS Control and Delay Block (DQSBUF)
Table 2.9. DQSBUF Port List Description
Name
Type
Description
DQS
Input
DDR memory DQS strobe
READ[1:0]
Input
Read Input from DDR Controller
READCLKSEL[2:0]
Input
Read pulse selection
SCLK
Input
Slow System Clock
ECLK
Input
High Speed Edge Clock (same frequency as DDR memory)
RDLOADN, RDMOVE, RDDIRECTION
Input
Dynamic Margin Control ports for Read delay
WRLOADN, WRMOVE, WRDIRECTION
Input
Dynamic Margin Control ports for Write delay
DELAYCODE_I[8:0]
Input
Dynamic Delay Control
WRITE_LEVELING_LOADN,
WRITE_LEVELING_DIRECTION,
WRITE_LEVELING_MOVE
Input
Write Leveling Control
DQSR90
Output
90 delay DQS used for Read
DQSW270
Output
90 delay clock used for DQ Write
DQSW
Output
Clock used for DQS Write
RDPNTR[2:0]
Output
Read Pointer for IFIFO module
WRPNTR[2:0]
Output
Write Pointer for IFIFO module
DATAVALID
Output
Signal indicating start of valid data
BURSTDET
Output
Burst Detect indicator
RD_COUT
Output
Read Count
WR_COUT
Output
Write Count
DELAYCODE_O[8:0]
Output
Dynamic Delay Control
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FPGA-DS-02078-1.0
39
Certus-NX Family
Data Sheet
2.12. sysI/O Buffer
Each I/O is associated with a flexible buffer referred to as a sysI/O buffer. These buffers are arranged around the
periphery of the device in groups referred to as banks. The sysI/O buffers allow you to implement a wide variety of
standards that are found in today’s systems including LVDS, HSUL, SSTL Class I and II, LVCMOS, and LVTTL.
The Certus-NX family contains multiple Programmable I/O Cell (PIC) blocks. Each PIC contains two Programmable I/O,
PIOA and PIOB. Each PIO includes a sysI/O buffer and I/O logic. Two adjacent PIO can be joined to provide a differential
I/O pair referred to as True and Comp, where True Pad is associated with the positive side of the differential I/O, and
the complement with the negative.
The top, left, and right side banks support I/O standards from 3.3 V to 1.0 V while the bottom supports I/O standards
from 1.8 V to 1.0 V. Every pair of I/O on the bottom bank also have a true LVDS and SLVS Tx Driver. In addition, the
bottom bank supports single-ended input termination. Both static and dynamic termination are supported. Dynamic
termination is used to support the DDR/LPDDR interface standards. For more information about DDR implementation
in I/O Logic and DDR memory interface support, refer to Certus-NX High-Speed I/O Interface (FPGA-TN-02216).
2.12.1. Supported sysI/O Standards
Certus-NX sysI/O buffers supports both single-ended differential and differential standards. Single-ended standards can
be further subdivided into internally ratioed standards such as LVCMOS, LVTTL, and externally referenced standards
such as HSUL and SSTL. The buffers support the LVTTL, LVCMOS 1.0 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V standards.
Differential standards supported include LVDS, SLVS, differential LVCMOS, differential SSTL, and differential HSUL. For
better support of video standards, subLVDS is also supported. Table 2.10 and Table 2.11 provide a list of sysI/O
standards supported in Certus-NX devices.
Table 2.10. Single-Ended I/O Standards
Standard
LVTTL33
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
LVCMOS10
HTSL15 I
SSTL 15 I
SSTL 135 I
HSUL12
LVCMOS18H
LVCMOS15H
LVCMOS12H
LVCMOS10H
LVCMOS10R
*Note: Output supported by LVCMOS10H.
Input
Yes
Yes
Output
Yes
Yes
Bi-directional
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
—
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes*
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40
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
Table 2.11. Differential I/O Standards
Standard
LVDS
SUBLVDS
Input
Yes
Yes
Output
Yes
No
Bi-directional
Yes
—
SLVS
SUBLVDSE
SUBLVDSEH
LVDSE
HSTL15D_I
SSTL15D_I
SSTL15D_II
SSTL135D_I
SSTL135D_II
HSUL12D
LVTTL33D
LVCMOS33D
LVCMOS25D
Yes
—
—
—
Yes
Yes
Yes
Yes
Yes
Yes
—
—
—
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
—
—
—
—
Yes
Yes
Yes
Yes
Yes
Yes
—
—
—
2.12.2. sysI/O Banking Scheme
Certus-NX devices have up to eight banks in total. For 40K device, there are one bank on top, two banks each at left
and right side of device, and three on the bottom side of device. For 17k device, one bank on top, one on right side and
three on the bottom side of device. The higher density Certus-NX device has more pins in each bank. Bank 0, Bank 1,
Bank 2, Bank 6, and Bank 7 support up to VCCIO 3.3 V while Bank 3, Bank 4, and Bank 5 support up to VCCIO 1.8 V. In
addition, Bank 3, Bank 4, and Bank 5 support two VREF inputs for flexibility to receive two different referenced input
levels on the same bank. Figure 2.27 shows the location of each bank.
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FPGA-DS-02078-1.0
41
Certus-NX Family
Data Sheet
VCCIO(0)
GND
Bank 0
GND
VCCIO(7)
GND
Bank 7*
Bank 1
Bank 6*
Bank 2*
GND
VCCIO(6)
VCCIO(1)
GND
Bank 4
Bank 5
GND
GND
VCCIO(2)
Bank 3
GND
VREF2(3)
VREF1(3)
VCCIO(3)
VREF2(4)
VREF1(4)
VCCIO(4)
VREF2(5)
VREF1(5)
VCCIO(5)
*Note: Bank not available in LFD2NX-17.
Figure 2.27. sysI/O Banking
2.12.2.1. Typical sysI/O Behavior During Power-up
The internal Power-On-Reset (POR) signal is deactivated when VCC and VCCAUX have reached satisfactory levels. After the
POR signal is deactivated, the FPGA core logic becomes active. It is your responsibility to ensure that all other VCCIO
banks are active with valid input logic levels to properly control the output logic states of all the I/O banks that are
critical to the application. For more information about controlling the output logic state with valid input logic levels
during power-up in Certus-NX devices, see the list of technical documentation in References section.
VCC and VCCAUX supply the power to the FPGA core fabric, whereas VCCIO supplies power to the I/O buffers. In order to
simplify the system design while providing consistent and predictable I/O behavior, it is recommended that the I/O
buffers be powered-up prior to the FPGA core fabric. For the different power supply voltage levels by the I/O banks,
refer to Certus-NX High-Speed I/O Interface (FPGA-TN-02216) for detailed information.
2.12.2.2. VREF1 and VREF2
Bank 3, Bank 4, and Bank 5 can support two separate VREF input voltages, VREF1, and VREF2. To assign a VREF driver,
use IO_Type = VREF1_DRIVER or VREF2_DRIVER. To assign VREF to a buffer, use VREF1_LOAD or VREF2_LOAD.
2.12.2.3. SysI/O Standards Supported by I/O Bank
All banks can support multiple I/O standards under the VCCIO rules discussed above. Table 2.12 and Table 2.13
summarize the I/O standards supported on various sides of the Certus-NX device.
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42
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
Table 2.12. Single-Ended I/O Standards Supported on Various Sides
Standard
LVTTL33
LVCMOS33
Top
Yes
Yes
LVCMOS25
Yes
LVCMOS18
Yes
LVCMOS15
Yes
LVCMOS12
Yes
LVCMOS10
Yes
LVCMOS18H
—
LVCMOS15H
—
LVCMOS12H
—
LVCMOS10H
—
LVCMOS10R
—
HTSL15 I
—
SSTL 15 I, II
—
SSTL 135 I, II
—
HSUL12
—
*Note: Left bank is not available in LFD2NX-17.
Left*
Yes
Yes
Right
Yes
Yes
Bottom
—
—
Yes
Yes
Yes
Yes
Yes
—
—
—
—
—
—
—
—
—
Yes
Yes
Yes
Yes
Yes
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Left*
—
—
—
Right
—
—
—
Bottom
Yes
Yes
Yes
Yes
—
Yes
—
—
—
—
—
—
Yes
Yes
Yes
Yes
—
Yes
—
—
—
—
—
—
Yes
Yes
Yes
—
Yes
—
Yes
Yes
Yes
Yes
Yes
Yes
—
—
—
Table 2.13. Differential I/O Standards Supported on Various Sides
Standard
LVDS
SUBLVDS
SLVS
Top
—
—
—
SUBLVDSE
Yes
SUBLVDSEH
—
LVDSE
Yes
HSTL15D_I
—
SSTL15D_I
—
SSTL15D_II
—
SSTL135D_I
—
SSTL135D_II
—
HSUL12D
—
LVTTL33D
Yes
LVCMOS33D
Yes
LVCMOS25D
Yes
*Note: Left bank is not available in LFD2NX-17.
2.12.2.4. Hot Socketing
The Certus-NX devices have been carefully designed to ensure predictable behavior during power-up and power-down.
During power-up and power-down sequences, the I/O remain in tri-state until the power supply voltage is high enough
to ensure reliable operation. In addition, leakage into I/O pins is controlled within specified limits. Bank 0, Bank 1,
Bank 2, Bank 6, and Bank 7 are fully hot hot socketable. Bank 3, Bank 4, and Bank 5 do not support hot socketing.
2.12.3. sysI/O Buffer Configurations
This section describes the various sysI/O features available on the Certus-NX device. Refer to Certus-NX High-Speed I/O
Interface (FPGA-TN-02216) for detailed information.
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FPGA-DS-02078-1.0
43
Certus-NX Family
Data Sheet
2.13. Analog Interface
The Certus-NX family provides an analog interface, consisting of two Analog to Digital Convertors (ADC), three
continuous time comparators and an internal junction temperature monitoring diode. The two ADCs can sample the
input sequentially or simultaneously.
2.13.1. Analog to Digital Converters
The Analog to Digital Convertor is a 12-bit, 1 MSPS SAR (Successive Approximation Register) architecture converter.
The ADC supports both continuous and single shot conversion modes.
The ADC input is selected among pre-selected GPIO input pairs, dedicated analog input pair, the internal junction
temperature sensing diode and internal voltage rails. The input signal can be converted in either uni-polar or bi-polar
mode.
The reference voltage is selectable between the 1.2 V internal reference generator and an external reference. The ADC
can convert up to a 1.8 V input signal with a 1.8 V external reference voltage. The ADC has an auto-calibration function
which calibrates the gain and offset.
2.13.2. Continuous Time Comparators
The continuous-time comparator can be used to monitor a dedicated input pair or a GPIO input pair. The output of the
comparator is provided as continuous and latched outputs.
2.13.3. Internal Junction Temperature Monitoring Diode
On-die junction temperature can be monitored using the internal junction temperature monitoring diode. The PTAT
(proportional to absolute temperature) diode voltage can be monitored by the ADC to provide a digital temperature
readout. Refer to ADC Usage Guide for Nexus Platform (FPGA-TN-02129) for more details.
2.14. IEEE 1149.1-Compliant Boundary Scan Testability
All Certus-NX devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant Test Access Port
(TAP). This allows functional testing of the circuit board on which the device is mounted through a serial scan path that
can access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in and loaded
directly onto test nodes, or test data to be captured and shifted out for verification. The test access port consists of
dedicated I/O: TDI, TDO, TCK, and TMS. The test access port uses VCCIO1 for power supply. The test access port is
supported for VCCIO1 = 1.8 V - 3.3 V.
For more information, refer to sysCONFIG Usage Guide for Nexus Platform (FPGA-TN-02099).
© 2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
44
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
2.15. Device Configuration
All Certus-NX devices contain various ports that can be used for configuration, including a Test Access Port (TAP). The
TAP supports both the IEEE Standard 1149.1 Boundary Scan specification and the IEEE Standard 1532 In-System
Configuration specification. JTAG_EN is the only dedicated configuration pin. PPROGRAMN/INITN/DONE are enabled by
default, but can be turned into GPIO. The remaining sysCONFIG pins are used as dual function pins. Refer to sysCONFIG
Usage Guide for Nexus Platform (FPGA-TN-02099) for more information about using the dual-use pins as general
purpose I/O.
There are various ways to configure a Certus-NX device:
JTAG (TAP)
Master Serial Peripheral Interface (SPI) – to load from external SPI flash using x1, x2, or x4 (QSPI) interfaces.
Inter-Integrated Circuit Bus (I2C)
Improved Inter-Integrated Circuit Bus (I3C)
Slave SPI from a system host
Lattice Memory Mapped Interface (LMMI), refer to sysI/O Usage Guide for Nexus Platform (FPGA-TN-02067) for
details.
JTAG, SSPI, MSPI, I2C, and I3C are supported for VCCIO = 1.8 V - 3.3 V
On power-up, based on the voltage level (high or low) of the PROGRAMN pin, the FPGA SRAM is configured by the
appropriate sysCONFIG port. If PROGRAMN pin is low, the FPGA is in the Slave configuration ports (Slave SPI, Slave I2C
or Slave I3C) and is waiting for the correct Slave Configuration port activation key. PROGRAMN must be driven high
within 50 ns of the end of transmission of the Slave Configuration port activation key, that is, the de-assertion of SCSN.
If no slave port is declared active before the PROGRAMN pin is sensed HIGH, the FPGA is in Master SPI booting mode.
In Master SPI booting mode, the FPGA boots from an external SPI flash. Once a configuration port is activated, it
remains active throughout that configuration cycle. The IEEE 1149.1 port can be activated any time after power-up by
enabling the JTAG_EN pin and sending the appropriate command through the TAP port.
2.15.1. Enhanced Configuration Options
Certus-NX devices have enhanced configuration features such as:
Early I/O release
Bitstream decryption
Decompression support
Watchdog Timer support
Dual and Multi-boot image support
Early I/O Release is a new configuration feature in which certain I/O banks are released earlier so that customer
systems have minimal disruption. For more details, refer to sysCONFIG Usage Guide for Nexus Platform (FPGA-TN02099).
Watchdog Timer is a new configuration feature that helps you add a programmable timer option for timeout
applications.
2.15.2.1. Dual-Boot and Multi-Boot Image Support
Dual-boot and multi-boot images are supported for applications requiring reliable remote updates of configuration
data for the system FPGA. After the system is running with a basic configuration, a new boot image can be downloaded
remotely and stored in a separate location in the configuration storage device. Any time after the update the Certus-NX
devices can be re-booted from this new configuration file. If there is a problem, such as corrupt data during download
or incorrect version number with this new boot image, the Certus-NX device can revert back to the original backup
golden configuration and try again. This all can be done without power cycling the system. For more information, refer
to sysCONFIG Usage Guide for Nexus Platform (FPGA-TN-02099).
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All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02078-1.0
45
Certus-NX Family
Data Sheet
2.16. Single Event Upset (SEU) Handling
Certus-NX devices are unique because the underlying technology used to build these devices is much more robust and
less prone to soft errors.
Certus-NX devices have an improved, hardware implemented, Soft Error Detection (SED) circuit which can be used to
detect SRAM errors so they can to be corrected. There are two layers of SED implemented in Certus-NX making it more
robust and reliable.
The SED hardware in Certus-NX devices is part of the Configuration block. The SED module in Certus-NX is an enhanced
version as compared to the SED modules implemented in other Lattice devices. The configuration data is divided into
frames so that the entire FPGA can be programmed precisely with ease. The SED hardware reads data from the FPGAs
configuration memory and performs an Error Correcting Code (ECC) calculation on every frame of configuration data
(see Figure 2.1). Once an error is detected, a notification is generated and SED resumes operation. For single bit errors,
the corrected value is rewritten to the particular frame using ECC information. If more than one bit error is detected
within one frame of configuration data, an error message is generated. Certus-NX devices also have dedicated logic to
perform Cycle Redundancy Code (CRC) checks for the entire bitstream, which runs in parallel along with ECC.
After the ECC is calculated on all frames of configuration data, CRC is calculated and checked for the entire bitstream.
ECC and CRC checks do not include the contents of RAMs (EBR, Large RAM, and distributed RAM).
For further information on SED support, refer to Soft Error Detection (SED)/Correction (SEC) Usage Guide for Nexus
Platform (FPGA-TN-02076).
2.17. On-Chip Oscillator
The Certus-NX device features two on board oscillators. Both Oscillators are controlled with internally generated
current.
The low frequency oscillator (LFOSC) is tailored for low power operation and runs at a nominal frequency of 128 kHz.
The LFOSC always runs and can be used to perform always on functions with the lowest possible power. The high
frequency oscillator (HFOSC) runs at a nominal frequency of 450 MHz, but can be divided down to a range of 256 MHz
to 2 MHz by user attributes.
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All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
46
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
2.18. User I²C IP
The Certus-NX device has one hard I²C interface, which can be configured either as a master (controller) or a slave
(responder). The pins for the I²C interface are pre-assigned.
The interface core has the option to delay the either the input or the output data (SDA), or both, by 50 ns nominal,
using dedicated on-chip delay elements. This provides an easier interface to any external I2C components. In addition,
50 ns glitch filters are available for both SDA and SCL.
When the interface is configured as master (controller), it is able to control other devices on the I2C bus through the
pre-assigned pins. When the core is configured as a slave (responder), the device is able to provide, for example, I/O
expansion to an I²C master (controller). The I²C core supports the following functionality:
Master (controller) and slave (responder) operation
7-bit and 10-bit addressing
Multi-master (controller) arbitration support
Clock stretching
Up to 1 MHz data transfer speed (Standard-Mode, Fast-Mode, Fast-Mode Plus)
General Call support
Optional receive and transmit data FIFOs with programmable sizes
Optional 50 ns delay on input or output data (SDA), or both
Hard-Connection and Programmable I/O Connection Support
Programmable to a mode compliant with I3C requirements on legacy I2C Slave Devices.
Fast-Mode and Fast-Mode Plus Support
Disabled Clock Stretching
50 ns SCL and SDA Glitch Filters
Programmable 7-bit Address
For further information on the User I²C, refer to I2C Hardened IP Usage Guide for Nexus Platform (FPGA-TN-02142).
2.19. Trace ID
Each Certus-NX device contains a unique (per device) TraceID that can be used for tracking purposes or for IP security
applications. The TraceID is 64 bits long. Eight out of 64 bits are user-programmable, the remaining 56 bits are factoryprogrammed. The TraceID is accessible through the SPI, I2C, or JTAG interfaces. For further information on TraceID,
refer to Using TraceID (FPGA-TN-02084).
2.20. Density Shifting
The Certus-NX family is designed to ensure that different density devices in the same family and in the same package
have the same pinout. Furthermore, the architecture ensures a high success rate when performing design migration
from lower density devices to higher density devices. In many cases, it is also possible to shift a low utilization design
targeted for a high-density device to a lower density device. However, the exact details of the final resource utilization
impact the likelihood of success in each case. An example is that some user I/O may become No Connects in smaller
devices in the same package. Refer to the Certus-NX Pin Migration Tables and Lattice Radiant software for specific
restrictions and limitations.
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All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02078-1.0
47
Certus-NX Family
Data Sheet
2.21. Peripheral Component Interconnect Express (PCIe)
The Certus-NX -40 Device features one lane of hardened PCIe block on the top side of the device. The PCIe block
implements all three layers defined by the PCI Express Specification: Physical, Data Link, and Transaction as shown in
Figure 2.28. Below is a summary of the features supported by the PCIe block:
Gen 1 (2.5 Gbps) and Gen 2 (5.0 Gbps) speed
PCIe Express Base Specification 3.0 compliant including compliance with earlier PCI Express Specifications
Multi-function support with up to four physical functions
Endpoint and Root Complex support
Type 0 Configuration Registers in Endpoint Mode
Complete Error-Handling Support
32 bit Core Data Width
Many power management features including power budgeting
PCI Express Core
PHY RX
PHY Interface (PIPE)
PHY TX
Tx
PHY
Layer
Tx
Data
Link
Layer
Tx
Trans
Layer
Rx
PHY
Layer
Rx
Data
Link
Layer
Rx
Trans
Layer
VC0_TX
VC0_RX
Power Management
Error Reporting (AER)
CLK, CONFIGURATION, AND MANAGEMENT
CONFIGURATION REGISTERS
LMMI
Figure 2.28. PCIe Core
The hardened PCIe block can be instantiated with the primitive PCIe through Lattice Radiant software however, it is not
recommended to directly instantiate the PCIe primitive itself. It is highly recommended to generate the PCIe Endpoint
Soft IP through the Radiant IP Catalog & IP Block Wizard instead. In Figure 2.29, the PCIe core is configured as an
Endpoint using a soft IP wrapper that provides useful functions such as bridging support for bus interfaces and DMA
applications. In addition to the standard Transaction Layer Packet (TLP) interface, the data interface can also be
configured to be AXI4 or AHB-Lite as well. The PCIe hardened block also features a register interface for LMMI and User
Configuration Space Register Interface (UCFG). The PCIe block has many registers which contain information about the
current status of the PCIe block as well as the capability to dynamically switch PCIe settings. One easy way to access
these registers is through the Reveal Controller Tool.
For more information about the PCIe soft IP, refer to the PCIe Endpoint IP Core document.
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All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
48
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
Top
Soft Logic
Data Interface Conversion
AHB-Lite
/APB
PCIe Hard IP
rxp_i/
rxpn_i
Rx TLP
AHB-Lite
/AXI-4
Tx TLP
LMMI
Register Interface Conversion
Transaction
Layer
Link Layer
PHY Layer
txp_o/
txpn_o
refclkp_i/
refclkn_i
UCFG
Figure 2.29. PCIe Soft IP Wrapper
2.22. Cryptographic Engine
The Certus-NX family of devices support several cryptographic features that helps customer secure their design. Some
of the key cryptographic features include Advanced Encryption Standard (AES) encryption, Hashing Algorithms, and
true random number generation (TRNG). The Certus-NX device also features bitstream encryption (AES-256), used for
protecting confidential FPGA bitstream data, and bitstream authentication (using ECDSA), which maintains bitstream
integrity and protects the FPGA design bitstream from copying and tampering.
The Cryptographic Engine (CRE) is the main block, which is responsible for bitstream encryption as well as
authentication of the Certus-NX device. Once the bitstream is authenticated and the device is ready for user functions,
the CRE is available to implement various cryptographic functions in your FPGA design. To enable specific cryptographic
functions, the CRE has to be configured by setting a few registers.
The Cryptographic Engine supports the below user-mode features:
True Random Number Generator (TRNG)
Secure Hashing Algorithm (SHA)-256 bit
Message Authentication Codes (MACs) – HMAC
Lattice Memory Mapped Interface (LMMI) to user logic
High Speed Port (HSP) for FIFO-based streaming data transfer
Cryptographic Engine (CRE)
Unique ID
Control Register
FPGA
Fabric
LMMI /
High Speed Port
True Random Number Generator (TRNG)
CRE Registers
Advanced Encryption Standard (AES)
Bitstream Encryption
Bitstream Authentication
SHA256
HMAC SHA256
Figure 2.30. Cryptographic Engine Block Diagram
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FPGA-DS-02078-1.0
49
Certus-NX Family
Data Sheet
3. DC and Switching Characteristics for Commercial and
Industrial
All specifications in this chapter are characterized within recommended operating conditions unless otherwise
specified.
3.1. Absolute Maximum Ratings
Table 3.1. Absolute Maximum Ratings
Symbol
VCC, VCCECLK
VCCAUX, VCCAUXA,
VCCAUXH3, VCCAUXH4,
VCCAUXH5
VCCIO0, 1, 2, 6, 7
VCCIO3, 4, 5
VCCPLL_DPHY0, 1
VCCPLLSD0
VCCA_DPHY0, 1
VCC_DPHY0, 1
VCCSD0
VCCADC18
VCCAUXSD
—
—
Parameter
Supply Voltage
Supply Voltage
I/O Supply Voltage
I/O Supply Voltage
Hardened D-PHY PLL Supply Voltage
SerDes Block PLL Supply Voltage
Analog Supply Voltage for Hardened D-PHY
Digital Supply Voltage for Hardened D-PHY
SerDes Supply Voltage
ADC Block 1.8 V Supply Voltage
SerDes and AUX Supply Voltage
Input or I/O Voltage Applied, Bank 0, Bank 1,
Bank 2, Bank 6, Bank 7
Input or I/O Voltage Applied, Bank 3, Bank 4,
Bank 5
Voltage Applied on SerDes Pins
Storage Temperature (Ambient)
Junction Temperature
Min
Max
Unit
–0.5
–0.5
1.10
1.98
V
V
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
3.63
1.98
1.10
1.98
1.98
1.10
1.10
1.98
1.98
3.63
V
V
V
V
V
V
V
V
V
V
–0.5
1.98
V
—
–0.5
1.98
V
TA
–65
+150
°C
TJ
—
+125
°C
Notes:
1. Stress above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. Functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is
not implied.
2. Compliance with the Lattice Thermal Management document is required.
3. All voltages referenced to GND.
4. All VCCAUX should be connected on PCB.
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50
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
3.2. Recommended Operating Conditions1, 2, 3
Table 3.2. Recommended Operating Conditions
Symbol
Parameter
Conditions
Min
Typ.
Max
Unit
VCC, VCCECLK
Core Supply Voltage
VCC = 1.0
0.95
1.00
1.05
V
VCCAUX
Auxiliary Supply Voltage
1.746
1.80
1.89
V
VCCAUXH3/4/5
Auxiliary Supply Voltage
Auxiliary Supply Voltage for
core logic.
1.746
1.80
1.89
V
1.746
1.80
1.89
V
3.135
3.30
3.465
V
2.375
2.50
2.625
V
1.71
1.425
1.80
1.50
1.89
1.575
V
V
1.2825
1.35
1.4175
V
1.14
1.20
1.26
V
0.95
1.00
1.05
V
—
1.71
1.80
1.89
V
—
0.95
1.00
1.05
V
—
1.71
1.80
1.89
V
—
1.71
1.80
1.89
V
—
0
—
85
°C
—
–40
—
100
°C
VCCAUXA
VCCIO
I/O Driver Supply Voltage
ADC External Power Supplies
VCCADC18
ADC 1.8 V Power Supply
SerDes Block External Power Supplies
Supply Voltage for SerDes
VCCSD0
Block and SerDes I/O
SerDes Block PLL Supply
Voltage
SerDes Block Auxiliary
VCCAUXSD
Supply Voltage
Operating Temperature
VCCPLLSD0
tJCOM
tJIND
Junction Temperature,
Commercial Operation
Junction Temperature,
Industrial Operation
Bank 0, Bank 1, Bank 2, Bank 6,
Bank 7
Bank 3, Bank 4, Bank 5
—
VCCIO = 3.3 V, Bank 0, Bank 1,
Bank 2, Bank 6, Bank 7
VCCIO = 2.5 V, Bank 0, Bank 1,
Bank 2, Bank 6, Bank 7
VCCIO = 1.8 V, All Banks
VCCIO = 1.5 V, All Banks4
VCCIO = 1.35 V, All Banks (For
DDR3L Only)
VCCIO = 1.2 V, All Banks4
VCCIO = 1.0 V, Bank 3, Bank 4,
Bank 5
Notes:
1. For correct operation, all supplies must be held in their valid operation voltage range.
2. All supplies with same voltage should be from the same voltage source. Proper isolation filters are needed to properly isolate
noise from each other.
3. Common supply rails must be tied together except SerDes.
4. MSPI (Bank 0) and JTAG, SSPI, I2C, and I3C (Bank 1) ports are supported for VCCIO = 1.8 V to 3.3 V.
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FPGA-DS-02078-1.0
51
Certus-NX Family
Data Sheet
3.3. Power Supply Ramp Rates
Table 3.3. Power Supply Ramp Rates
Symbol
Parameter
tRAMP
Power Supply ramp rates for all supplies
1
Min
Typ
Max
Unit
0.1
—
50
V/ms
Notes:
1. Assumes monotonic ramp rates.
2. All supplies need to be in the operating range as defined in Recommended Operating Conditions, when the device has
completed configuration and entering into User Mode. Supplies that are not in the operating range needs to be adjusted to
faster ramp rate, or you have to delay configuration or wake up.
3.4. Power up Sequence
Power-On-Reset (POR) puts the Certus-NX device into a reset state. There is no power up sequence required for the
Certus-NX device.
Table 3.4. Power-On Reset
Symbol
Parameter
VPORUP
VPORDN
Min
Typ
Max
Unit
Power-On-Reset ramp-up trip
point (Monitoring VCC, VCCAUX,
VCCI00, and VCCI01)
VCC
0.73
—
0.83
V
VCCAUX
1.34
—
1.71
V
VCCIO0,VCCI01
0.89
—
1.05
V
Power-On-Reset ramp-up trip
point (Monitoring VCC and VCCAUX)
VCC
0.51
—
0.81
V
VCCAUX
1.38
—
1.54
V
3.5. On-Chip Programmable Termination
The Certus-NX devices support a variety of programmable on-chip terminations options, including:
Dynamically switchable Single-Ended Termination with programmable resistor values of 40 Ω, 50 Ω, 60 Ω, or 75 Ω.
Common mode termination of 100 Ω for differential inputs.
Zo = 50
V CCI O
Zo = 40 , 50 , 60 , or 75
to VCCIO /2
TERM
control
Zo
Zo
Zo
+
-
VREF
OFF-chip
+
2Zo Zo
OFF-chip
ON-chip
Parallel Single-Ended Input
ON-chip
Differential Input
Figure 3.1. On-Chip Termination
See Table 3.5 for termination options for input modes.
Table 3.5. On-Chip Termination Options for Input Modes
IO_TYPE
subLVDS
SLVS
HSTL15D_I
SSTL15D_I
Differential Termination Resistor*
Terminate to VCCIO/2*
100, OFF
100, OFF
100, OFF
100, OFF
OFF
OFF
OFF
OFF
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52
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
IO_TYPE
Differential Termination Resistor*
Terminate to VCCIO/2*
SSTL135D_I
100, OFF
OFF
HSUL12D
100, OFF
OFF
LVCMOS15H
OFF
OFF
LVCMOS12H
OFF
OFF
LVCMOS10H
OFF
OFF
LVCMOS12H
OFF
OFF
LVCMOS10H
OFF
OFF
LVCMOS18H
OFF
OFF, 40, 50, 60, 75
HSTL15_I
OFF
50
SSTL15_I
OFF
OFF, 40, 50, 60, 75
SSTL135_I
OFF
OFF, 40, 50, 60, 75
HSUL12
OFF
OFF, 40, 50, 60, 75
*Notes:
TERMINATE to VCCIO/2 (Single-Ended) and DIFFRENTIAL TERMINATION RESISTOR when turned on can only have one setting per
bank. Only left and right banks have this feature.
Use of TERMINATE to VCCIO/2 and DIFFRENTIAL TERMINATION RESISTOR are mutually exclusive in an I/O bank. On-chip
termination tolerance –10%/+60%.
Refer to sysI/O Usage Guide for Nexus Platform (FPGA-TN-02067) for on-chip termination usage and value ranges.
3.6. Hot Socketing Specifications
Table 3.6. Hot Socketing Specifications for GPIO
Symbol
IDK
Parameter
Input or I/O Leakage Current for
Wide Range I/O (excluding
MCLK/MCSN/MOSI/INITN/DONE)
Condition
0 < Vin < Vih(max)
0 < Vcc < Vcc(max)
0 < Vccio < Vccio(max)
0 < Vccaux < Vccaux(max)
Min
-1.5
Typ
—
Max
1.5
Unit
mA
Notes:
1. IDK is additive to IPU, IPD, or IBH.
2. Hot socketing specs are defined at a device junction temperature of 85 °C or below. When the device junction temperature is
above 85 oC, the IDK current can exceed the above spec.
3. Going beyond the hot socketing range specified here causes exponentially higher leakage currents and potential reliability
issues. A total of 64 mA per 8 I/O should not be exceeded.
3.7. ESD Performance
Refer to the Certus-NX Product Family Qualification Summary for complete qualification data, including ESD
performance.
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FPGA-DS-02078-1.0
53
Certus-NX Family
Data Sheet
3.8. DC Electrical Characteristics
Table 3.7. DC Electrical Characteristics – Wide Range
Symbol
Parameter
Condition
Min
Typ
Max
Unit
0 ≤ VIN ≤ VCCIO
—
—
10
µA
VCCIO ≤ VIN ≤ VIH (max)
—
—
100
µA
0 ≤ VIN ≤ 0.7 × VCCIO
–30
—
–150
µA
VIL (max) ≤ VIN ≤ VCCIO
30
—
150
µA
VIN = VIL (max)
30
—
–30
—
—
—
VIL (max)
—
—
—
IBHLS
Input or I/O Leakage current
(Commercial/Industrial)
Input or I/O Leakage current
I/O Weak Pull-up Resistor
Current
I/O Weak Pull-down Resistor
Current
Bus Hold Low Sustaining Current
IBHHS
Bus Hold High Sustaining Current
VIN = 0.7 × VCCIO
IBHLO
IBHHO
VBHT
Bus hold low Overdrive Current
Bus hold high Overdrive Current
Bus Hold Trip Points
0 ≤ VIN ≤ VCCIO
0 ≤ VIN ≤ VCCIO
—
IIL, IIH1
IIH2
IPU
IPD
µA
µA
150
–150
VIH (min)
µA
µA
V
Notes:
1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output tri-stated. Bus
Maintenance circuits are disabled.
2. The input leakage current IIH is the worst case input leakage per GPIO when the pad signal is high and also higher than the bank
VCCIO. This is considered a mixed mode input.
Table 3.8. DC Electrical Characteristics – High Speed
Symbol
IIL, IIH*
IPU
Parameter
Input or I/O Leakage
I/O Weak Pull-up Resistor
Current
Condition
0 ≤ VIN ≤ VCCIO
Min
—
0 ≤ VIN ≤ 0.7 × VCCIO
–30
VIL (max) ≤ VIN ≤ VCCIO
30
VIN = VIL (max)
30
–30
IBHLS
I/O Weak Pull-down Resistor
Current
Bus Hold Low Sustaining Current
IBHHS
Bus Hold High Sustaining Current
VIN = 0.7 × VCCIO
IBHLO
IBHHO
Bus hold low Overdrive Current
Bus hold high Overdrive Current
0 ≤ VIN ≤ VCCIO
0 ≤ VIN ≤ VCCIO
IPD
Typ
—
—
—
—
—
Max
10
Unit
µA
–150
µA
150
µA
—
—
µA
µA
—
—
150
µA
—
—
–150
µA
VIL
VBHT
Bus Hold Trip Points
—
—
VIH (min)
V
(max)
*Note: Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output tri-stated. Bus
Maintenance circuits are disabled.
Table 3.9. Capacitance – Wide Range
Symbol
Parameter
Condition
Min
Typ
Max
Unit
C1 *
I/O Capacitance*
VCCIO = 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V,
VCC = typ., VIO = 0 to VCCIO + 0.2V
—
6
—
pF
C2 *
Dedicated Input Capacitance*
VCCIO = 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V,
VCC = typ., VIO = 0 to VCCIO + 0.2V
—
6
—
pF
*Note:
TA 25 oC, f = 1.0 MHz.
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54
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
Table 3.10. Capacitance – High Performance
Symbol
Parameter
Condition
C1 *
I/O Capacitance*
C2 *
C3 *
*Note:
Min
Typ
Max
Unit
VCCIO = 1.8 V, 1.5 V, 1.2 V, VCC = typ.,
VIO = 0 to VCCIO + 0.2V
—
6
—
pF
Dedicated Input Capacitance*
VCCIO = 1.8 V, 1.5 V, 1.2 V, VCC = typ.,
VIO = 0 to VCCIO + 0.2V
—
6
—
pF
SerDes I/O Capacitance
VCCSD0 = 1.0 V, VCC = typ., VIO = 0 to
VCCSD0 + 0.2 V
—
5
—
pF
TA 25 oC, f = 1.0 MHz.
Table 3.11. Single Ended Input Hysteresis – Wide Range
IO_TYPE
LVCMOS33
LVCMOS18
VCCIO
3.3 V
3.3 V
2.5 V
1.8 V
TYP Hysteresis
250 mV
200 mV
250 mV
180 mV
LVCMOS15
LVCMOS12
LVCMOS10
1.5 V
1.2 V
1.2 V
50 mV
0
0
VCCIO
1.8 V
1.8 V
1.5 V
1.2 V
1.0 V
TYP Hysteresis
180 mV
50 mV
150 mV
0
0
LVCMOS25
Table 3.12. Single Ended Input Hysteresis – High Performance
IO_TYPE
LVCMOS18H
LVCMOS15H
LVCMOS12H
LVCMOS10H
3.9. Supply Currents
For estimating and calculating current, use Power Calculator in Lattice Design software.
This operating and peak current is design dependent, and can be calculated in Lattice Design software. Some blocks can
be placed into low current standby modes. Refer to Certus-NX Power Usage Guide (FPGA-TN-02214).
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FPGA-DS-02078-1.0
55
Certus-NX Family
Data Sheet
3.10. sysI/O Recommended Operating Conditions
Table 3.13. sysI/O Recommended Operating Conditions
Standard
Single-Ended
LVCMOS33
LVTTL33
LVCMOS25¹, ²
LVCMOS18¹, ²
LVCMOS18H
LVCMOS15¹, ²
LVCMOS15H¹
LVCMOS12¹, ²
LVCMOS12H¹
LVCMOS10¹
LVCMOS10H¹
LVCMOS10R¹
SSTL135_I, SSTL135_II3
SSTL15_I, SSTL15_II3
HSTL15_I3
HSUL123
Differential
LVDS
LVDSE5
subLVDS
5
subLVDSE
Support Banks
VCCIO (Input)
VCCIO (Output)
Typ.
Typ.
0, 1, 2, 6, 7
0, 1, 2, 6, 7
0, 1, 2, 6, 7
0, 1, 2, 6, 7
3, 4, 5
0, 1, 2, 6, 7
3, 4, 5
0, 1, 2, 6, 7
3, 4, 5
3.3
3.3
2.5, 3.3
1.2, 1.5, 1.8, 2.5, 3.3
1.8
1.2, 1.5, 1.8, 2.5, 3.3
1.5, 1.8
1.2, 1.5, 1.8, 2.5, 3.3
1.2, 1.357, 1.5, 1.8
3.3
3.3
2.5
1.8
1.8
1.5
1.5
1.2
1.2
0, 1, 2, 6, 7
3, 4, 5
3, 4, 5
3, 4, 5
3, 4, 5
3, 4, 5
3, 4, 5
1.2, 1.5, 1.8, 2.5, 3.3
1.0, 1.2, 1.357, 1.5, 1.8
1.0, 1.2, 1.357, 1.5, 1.8
1.357
1.58
1.58
1.2
—
1.0
—
1.35
1.57
1.57
1.2
3, 4, 5
0, 1, 2, 6, 7
1.8
—
1.8
2.5
3, 4, 5
1.8
—
—
0, 1, 2, 6, 7
1.8
—
3, 4, 5
1.8
subLVDSEH5
SLVS6
3, 4, 5
1.0, 1.2, 1.356, 1.5, 1.84
1.2, 1.356, 1.5, 1.8 4
LVCMOS33D5
0, 1, 2, 6, 7
—
3.3
LVTTL33D5
0, 1, 2, 6, 7
—
3.3
5
LVCMOS25D
0, 1, 2, 6, 7
—
2.5
SSTL135D_I, SSTL135D_II5
3, 4, 5
—
1.356
SSTL15D_I, SSTL15D_II5
3, 4, 5
—
1.5
5
HSTL15D_I
3, 4, 5
—
1.5
HSUL12D5
3, 4, 5
—
1.2
Notes:
1. Single-ended input can mix into I/O Banks with VCCIO different from the standard requires due to some of these input standards
use internal supply voltage source (VCC, VCCAUX) to power the input buffer, which makes them to be independent of VCCIO
voltage. For more details, refer to sysI/O Usage Guide for Nexus Platform (FPGA-TN-02067). The following is a brief guideline to
follow:
a. Weak pull-up on the I/O must be set to OFF.
b. Bank 3, Bank 4, and Bank 5 I/O can only mix into banks with VCCIO higher than the pin standard, due to clamping diode on
the pin in these banks. Bank 0, Bank 1, Bank 2, Bank 6, and Bank 7 does not have this restriction.
c. LVCMOS25 uses VCCIO supply on input buffer in Bank 0, Bank 1, Bank 2, Bank 6, and Bank 7. It can be supported with VCCIO =
3.3 V to meet the VIH and VIL requirements, but there is additional current drawn on VCCIO. Hysteresis has to be disabled
when using 3.3 V supply voltage.
d. LVCMOS15 uses VCCIO supply on input buffer in Bank 3, Bank 4, and Bank 5. It can be supported with VCCIO = 1.8 V to meet
the VIH and VIL requirements, but there is additional current drawn on VCCIO.
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56
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
2.
3.
4.
5.
6.
7.
Single-ended LVCMOS inputs can mixed into I/O Banks with different VCCIO, providing weak pull-up is not used.
For additional information on Mixed I/O in Bank VCCIO, refer to sysI/O Usage Guide for Nexus Platform (FPGA-TN-02067).
These inputs use differential input comparator in Bank 3, Bank 4, and Bank 5. The differential input comparator uses VCCAUXH
power supply. These inputs require the VREF pin to provide the reference voltage in the Bank. Refer to sysI/O Usage Guide for
Nexus Platform (FPGA-TN-02067) for details.
All differential inputs use differential input comparator in Bank 3, Bank 4, and Bank 5. The differential input comparator uses
VCCAUXH power supply. There is no differential input signaling supported in Bank 0, Bank 1, Bank 2, Bank 6, and Bank 7.
These outputs are emulating differential output pair with single-ended output drivers with true and complement outputs
driving on each of the corresponding true and complement output pair pins. The common mode voltage, VCM, is ½ × VCCIO. Refer
to sysI/O Usage Guide for Nexus Platform (FPGA-TN-02067) for details.
VCCIO = 1.35 V is only supported in Bank 3, Bank 4, and Bank 5, for use with DDR3L interface in the bank. These Input and Output
standards can fit into the same bank with the VCCIO = 1.35 V.
LVCMOS15 input uses VCCIO supply voltage. If VCCIO is 1.8 V, the DC levels for LVCMOS15 are still met, but there could be increase
in input buffer current.
3.11. sysI/O Single-Ended DC Electrical Characteristics
Table 3.14. sysI/O DC Electrical Characteristics – Wide Range I/O
Input/Output
Standard
LVTTL33
LVCMOS33
LVCMOS25
Min (V)
—
—
VIL¹
Max (V)
VIH¹
Min (V)
Max (V)
VOL Max
(V)
VOH Min²
(V)
IOL(mA)
IOH(mA)
0.8
2.0
3.465
0.4
VCCIO – 0.4
2, 4, 8,
12, 16
0.7
1.7
2.625
0.4
VCCIO – 0.45
2, 4, 8, 10
-2, -4, -8,
-12, -16
-2, -4, -8,
-10
LVCMOS18
—
0.35 * VCCIO
0.65 * VCCIO
1.9
0.4
VCCIO – 0.45
2, 4, 8
LVCMOS15
—
0.35 * VCCIO
0.65 * VCCIO
1.575
0.4
VCCIO – 0.4
2, 4
-2, -4
2, 4
-2, -4, -8,
-12
LVCMOS12
LVCMOS10
—
—
0.35 * VCCIO
0.65 * VCCIO
1.26
0.3 * VCCIO
0.7 * VCCIO
1.05
0.4
VCCIO – 0.4
-2, -4, -8
No O/P Support
Notes:
1. VCCIO for input level refers to the supply rail level associated with a given input standard.
2. VCCIO for the output levels refer to the VCCIO of the Certus-NX device.
3. For electro-migration, the combined DC current sourced or sinked by I/O pads between two consecutive VCCIO or GND pad
connections, or between the last VCCIO or GND in an I/O bank and the end of an I/O bank, as shown in the Logic Signal
Connections table (also shown as I/O grouping) shall not exceed a maximum of n * 8 mA. n is the number of I/O pads between
the two consecutive bank VCCIO or GND connections or between the last VCCIO and GND in a bank and the end of a bank. I/O
Grouping can be found in the Data Sheet Pin Summary Tables, which can also be generated from the Lattice Radiant software.
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FPGA-DS-02078-1.0
57
Certus-NX Family
Data Sheet
Table 3.15. sysI/O DC Electrical Characteristics – High Performance I/O
Input/Output
Standard
VIL¹
Min (V)
Max (V)
VIH¹
Min (V)
Max (V)
VCCIO +
0.3
VCCIO +
0.3
VOL Max
(V)
VOH Min²
(V)
IOL (mA)
IOH (mA)
0.4
VCCIO – 0.45
2, 4, 8, 12
-2, -4, -8,
-12
0.4
VCCIO – 0.4
2, 4, 8
-2, -4, -8
LVCMOS18H
0.35 *
VCCIO
0.65 * VCCIO
LVCMOS15H
0.35 *
VCCIO
0.65 * VCCIO
LVCMOS12H
0.35 *
VCCIO
0.65 * VCCIO
1.26
0.4
VCCIO – 0.4
2, 4, 8
-2, -4, -8
LVCMOS10H
0.3 * VCCIO
0.7 * VCCIO
1.05
0.27 *
VCCIO
0.75 * VCCIO
2, 4
-2, -4
SSTL15_I
VREF – 0.10
VREF + 0.1
1.575
0.30
VCCIO – 0.30
7.5
–7.5
SSTL15_II
VREF – 0.10
VREF + 0.1
1.575
0.30
VCCIO – 0.30
8.8
–8.8
HSTL15_I
VREF – 0.10
VREF + 0.1
1.575
0.40
VCCIO – 0.40
8
–8
SSTL135_I
VREF – 0.09
VREF + 0.09
1.418
0.27
VCCIO – 0.27
6.75
–6.75
SSTL135_II
VREF – 0.09
VREF + 0.09
1.418
0.27
VCCIO – 0.27
8
–8
LVCMOS10R
VREF – 0.10
VREF + 0.10
1.05
—
—
—
—
HSUL12
VREF – 0.10
VREF + 0.10
1.26
0.3
VCCIO – 0.3
8.8, 7.5,
6.25, 5
-8.8, -7.5,
-6.25, -5
Notes:
1. VCCIO for input level refers to the supply rail level associated with a given input standard.
2. VCCIO for the output levels refer to the VCCIO of the Certus-NX device.
3. For electro-migration, the combined DC current sourced or sinked by I/O pads between two consecutive VCCIO or GND pad
connections, or between the last VCCIO or GND in an I/O bank and the end of an I/O bank, as shown in the Logic Signal
Connections table (also shown as I/O grouping) shall not exceed a maximum of n × 8 mA. n is the number of I/O pads between
the two consecutive bank VCCIO or GND connections or between the last VCCIO and GND in a bank and the end of a bank. I/O
Grouping can be found in the Data Sheet Pin Summary Tables, which can also be generated from the Lattice Radiant software.
Table 3.16. I/O Resistance Characteristics
Parameter
50RS
RDIFF
SE Input
Termination
Description
Output Drive Resistance when 50RS
Drive Strength Selected
Input Differential Termination
Resistance
Input Single Ended Termination
Resistance
Test Conditions
VCCIO = 1.8 V, 2.5 V, or 3.3 V
Min
Typ
Max
Unit
—
50
—
Ω
Bank 3, Bank 4, and Bank 5 for I/O
selected to be differential
Bank 3, Bank 4, and Bank 5 for I/O
selected to be Single Ended
100
36
46
56
71
40
50
60
75
Ω
64
80
96
120
Ω
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58
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
3.12. sysI/O Differential DC Electrical Characteristics
3.12.1. LVDS
LVDS input buffer on Certus-NX is operating with VCCAUX = 1.8 V and independent of Bank VCCIO voltage. LVDS output
buffer is powered by the Bank VCCIO at 1.8 V.
LVDS can only be supported in Bank 3, Bank 4, and Bank 5. LVDS25 output can be emulated with LVDS25E in Bank 0,
Bank 1, Bank 2, Bank 6, and Bank 7. This is described in LVDS25E (Output Only) section.
Table 3.17. LVDS DC Electrical Characteristics1
Parameter
VINP, VINM
VICM
VTHD
IIN
VOH
VOL
VOD
Test Conditions
—
Half the sum of the two Inputs
Difference between the two Inputs
Power On or Power Off
RT = 100 Ω
RT = 100 Ω
(VOP - VOM), RT = 100 Ω
VOCM
Description
Input Voltage
Input Common Mode Voltage
Differential Input Threshold
Input Current
Output High Voltage for VOP or VOM
Output Low Voltage for VOP or VOM
Output Voltage Differential
Change in VOD Between High and
Low
Output Common Mode Voltage
VOCM
Change in VOCM, VOCM(MAX) - VOCM(MIN)
—
ISAB
Output Short Circuit Current
VOD
—
(VOP + VOM)/2, RT = 100 Ω
VOD = 0 V Driver outputs shorted to
each other
—
Min
0
0.05
±100
—
—
0.9 V
250
Typ
—
—
—
—
1.425
1.075
350
Max
1.60
1.55 2
—
±10
1.60
—
450
Unit
V
V
mV
µA
V
V
mV
—
—
50
mV
1.125
1.25
1.375
V
—
—
50
mV
—
—
12
mA
Change in VOS between H and L
—
—
50
mV
VOS
Notes:
1. LVDS input or output are supported in Bank 3, Bank 4, and Bank 5. LVDS input uses VCCAUX on the differential input comparator,
and can be located in any VCCIO voltage bank. LVDS output uses VCCIO on the differential output driver, and can only be located in
bank with VCCIO = 1.8 V.
2. VICM is depending on VID, input differential voltage, so the voltage on pin cannot exceed VINP/INN(min/max) requirements. VICM(min) =
VINP/INN(min) + ½ VID, VICM(max) = VINP/INN(max) – ½ VID. Values in the table is based on minimum VID of +/- 100 mV.
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FPGA-DS-02078-1.0
59
Certus-NX Family
Data Sheet
3.12.2. LVDS25E (Output Only)
Three sides of the Certus-NX devices, Top, Left and Right, support LVDS25 outputs with emulated complementary
LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The scheme shown in Figure 3.2 is
one possible solution for point-to-point signals.
Table 3.18. LVDS25E DC Conditions
Parameter
Description
Typical
Unit
VCCIO
Output Driver Supply (±5%)
2.50
V
ZOUT
Driver Impedance
20
Ω
RS
Driver Series Resistor (±1%)
158
Ω
RP
Driver Parallel Resistor (±1%)
140
Ω
RT
Receiver Termination (±1%)
100
Ω
VOH
Output High Voltage
1.43
V
VOL
Output Low Voltage
1.07
V
VOD
Output Differential Voltage
0.35
V
VCM
Output Common Mode Voltage
1.25
V
ZBACK
Back Impedance
100.5
Ω
IDC
DC Output Current
6.03
mA
VCCIO = 2.5 V (± 5%)
RS = 158
(± 1%)
8 mA
LVCMOS25
VCCIO = 2.5 V (± 5%)
RP = 140
(± 1%)
RS = 158
(± 1%)
+
-
RT = 100
(± 1%)
8 mA
LVCMOS25
ON-chip
Transmission line, Zo = 100
differential
OFF-chip
OFF-chip ON-chip
Figure 3.2. LVDS25E Output Termination Example
3.12.3. SubLVDS (Input Only)
SubLVDS is a reduced-voltage form of LVDS signaling, very similar to LVDS. It is a standard used in many camera types
of applications, and follow the SMIA 1.0, Part 2: CCP2 Specification. Being similar to LVDS, the Certus-NX devices can
support the subLVDS input signaling with the same LVDS input buffer. The output for subLVDS is implemented in
subLVDSE/subLVDSEH with a pair of LVCMOS18 output drivers (see SubLVDSE/SubLVDSEH (Output Only) section).
Table 3.19. SubLVDS Input DC Electrical Characteristics
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
VID
Input Differential Threshold Voltage
Over VICM range
70
150
200
mV
VICM
Input Common Mode Voltage
Half the sum of the two Inputs
0.4
0.9
1.4
V
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60
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
Sub-LVDS Driver
PCB Traces, Connectors or Cables
Z0 = 50
+
+
100
RT = 100
± 1%*
differential
–
–
Z0 = 50
Off-chip
On-chip
Figure 3.3. SubLVDS Input Interface
3.12.4. SubLVDSE/SubLVDSEH (Output Only)
SubLVDS output uses a pair of LVCMOS18 drivers with True and Complement outputs. The VCCIO of the bank used for
subLVDSE or subLVDSEH needs to be powered by 1.8V. SubLVDSE is for Bank 0, Bank 1, Bank 2, Bank 6, and Bank 7; and
subLVDSEH is for Bank 3, Bank 4, and Bank 5.
Performance of the subLVDSE/subLVDSEH driver is limited to the performance of LVCMOS18.
Table 3.20. SubLVDS Output DC Electrical Characteristics
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
VOD
Output Differential Voltage Swing
VOCM
Output Common Mode Voltage
—
—
150
—
mV
Half the sum of the two Outputs
—
0.9
—
V
PCB Traces, Connectors or Cables
VCCIO = +1.8 V
Rs = 267
Z0 = 50
±1%
+
+
SubLVDS Output
SubLVDSE
SubLVDSEH
Rp = 121
–
Rs = 267
±1%
±1%
100
diff erential
RT = 100
±1%
Sub-LVDS Recev ier
–
Z0 = 50
0
On-chip
Off-chip
On-chip
Off-chip
Figure 3.4. SubLVDS Output Interface
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FPGA-DS-02078-1.0
61
Certus-NX Family
Data Sheet
3.12.5. SLVS
Scalable Low-Voltage Signaling (SLVS) is based on a point-to-point signaling method defined in the JEDEC JESD8-13
(SLVS-400) standard. This standard evolved from the traditional LVDS standard with smaller voltage swings and a lower
common-mode voltage. The 200 mV (400 mV p-p) SLVS swing contributes to a reduction in power.
The Certus-NX devices receive SLVS differential input with the LVDS input buffer. This LVDS input buffer is design to
cover wide input common mode range that can meet the SLVS input standard specified by the JEDEC standard.
Table 3.21. SLVS Input DC Characteristics
Parameter
Description
Test Conditions
Min
VID
Input Differential Threshold Voltage
Over VICM range
70
VICM
Input Common Mode Voltage
Half the sum of the two Inputs
70
Typ
Max
Unit
—
—
mV
200
330
mV
The SLVS output on the Certus-NX device is supported with the LVDS drivers found in Bank 3, Bank 4, and Bank 5. The
LVDS driver on the Certus-NX device is a current controlled driver. It can be configured as LVDS driver, or configured
with the 100 Ω differential termination with center-tap set to VOCM at 200 mV. This means the differential output driver
can be placed into bank with VCCIO = 1.2 V, 1.5 V, or 1.8 V, even if it is powered by VCCIO.
Table 3.22. SLVS Output DC Characteristics
Parameter
Description
Test Conditions
Min
VCCIO
Bank VCCIO
—
–5%
VOD
VOCM
ZOS
Output Differential Voltage Swing
Output Common Mode Voltage
Single-Ended Output Impedance
—
Half the sum of the two Outputs
—
140
150
40
Typ
1.2,
1.5,
1.8
200
200
50
Max
Unit
+ 5%
V
270
250
62.5
mV
mV
Ω
Figure 3.5. SLVS Interface
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62
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
3.12.6. Soft MIPI D-PHY
When Soft D-PHY is implemented inside the FPGA logic, the I/O interface needs to use sysI/O buffers to connect to
external D-PHY pins.
The Certus-NX sysI/O provides support for SLVS, as described in SLVS section, plus the LVCMOS12 input/output buffers
together to support the High Speed (HS) and Low Power (LP) mode as defined in MIPI Alliance Specification for D-PHY.
To support MIPI D-PHY with SLVS (LVDS) and LVCMOS12, the bank VCCIO cannot be set to 1.5 V or 1.8 V. It has to
connect to 1.2 V, or 1.1 V.
All other DC parameters are the same as listed in SLVS section. DC parameters for the LP driver and receiver are the
same as listed in LVCMOS12.
LVCMOS12
LP Data_P
LPenable
HSenable
MIPI Receiver
100
+
Diff
+
HS Data
Z0=50
-
-
SLVS
LPenable
LP Data_N
LVCMOS12
MIPI_LP_RX
On-Chip
RXLP_P
MIPI Driver
+
+
Z0=50
HS Data
-
-
LVDS
MIPI_LP_RX
RXLP_N
Figure 3.6. MIPI Interface
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FPGA-DS-02078-1.0
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Certus-NX Family
Data Sheet
Table 3.23. Soft D-PHY Input Timing and Levels
Symbol
Description
High Speed (Differential) Input DC Specifications
VCMRX(DC)
Common-mode Voltage in High Speed Mode
Conditions
Min
Typ
Max
Unit
VIDTH
Differential Input HIGH Threshold
VIDTL
Differential Input LOW Threshold
VIHHS
Input HIGH Voltage (for HS mode)
VILHS
Input LOW Voltage
VTERM-EN
Single-ended voltage for HS Termination Enable4
ZID
Differential Input Impedance
High Speed (Differential) Input AC Specifications
ΔVCMRX(HF)1
Common-mode Interference (>450 MHz)
ΔVCMRX(LF)2, 3
Common-mode Interference (50 MHz–450 MHz)
CCM
Common-mode Termination
Low Power (Single-Ended) Input DC Specifications
VIH
Low Power Mode Input HIGH Voltage
VIL
Low Power Mode Input LOW Voltage
VIL-ULP
Ultra Low Power Input LOW Voltage
VHYST
Low Power Mode Input Hysteresis
℮SPIKE
Input Pulse Rejection
TMIN-RX
Minimum Pulse Width Response
VINT
Peak Interference Amplitude
fINT
Interference Frequency
Contention Detector (LP-CD) DC Specifications
VIHCD
Contention Detect HIGH Voltage
—
70
—
330
mV
—
—
—
—
—
—
70
—
—
–40
—
80
—
—
—
—
—
100
—
-70
460
—
450
125
mV
mV
mV
mV
mV
Ω
—
—
—
—
–50
—
—
100
50
60
mV
mV
pF
—
—
—
—
—
—
—
—
740
—
—
25
—
20
—
450
—
—
—
—
—
—
—
—
—
550
300
—
300
—
200
—
mV
mV
mV
mV
V∙ps
ns
mV
MHz
—
450
—
—
mV
200
mV
VILCD
Contention Detect LOW Voltage
—
—
—
Notes:
1. This is peak amplitude of sine wave modulated to the receiver inputs.
2. Input common-mode voltage difference compared to average common-mode voltage on the receiver inputs.
3. Exclude any static ground shift of 50 mV.
4. High Speed Differential RTERM is enabled when both DP and DN are below this voltage.
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64
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
Table 3.24. Soft D-PHY Output Timing and Levels
Symbol
Description
High Speed (Differential) Output DC Specifications
VCMTX
Common-mode Voltage in High Speed Mode
|ΔVCMTX(1,0)|
VCMTX Mismatch Between Differential HIGH
and LOW
|VOD|
Output Differential Voltage
VOD Mismatch Between Differential HIGH and
LOW
VOHHS
Single-Ended Output HIGH Voltage
ZOS
Single Ended Output Impedance
ΔZOS
ZOS mismatch
High Speed (Differential) Output AC Specifications
ΔVCMTX(LF)
Common-Mode Variation, 50 MHz–450 MHz
ΔVCMTX(HF)
Common-Mode Variation, above 450 MHz
|ΔVOD|
Output 20%–80% Rise Time
Output 80%–20% Fall Time
tR
tF
Output Data Valid After CLK Output
Low Power (Single-Ended) Output DC Specifications
VOH
Low Power Mode Output HIGH Voltage
VOL
Low Power Mode Input LOW Voltage
ZOLP
Output Impedance in Low Power Mode
Low Power (Single-Ended) Output AC Specifications
tRLP
15%–85% Rise Time
tFLP
85%–15% Fall Time
tREOT
HS–LP Mode Rise and Fall Time, 30%–85%
TLP-PULSE-TX
Pulse Width of the LP Exclusive-OR Clock
TLP-PER-TX
CLOAD
Period of the LP Exclusive-OR Clock
Load Capacitance
Conditions
Min
Typ
Max
Unit
—
150
200
250
mV
—
—
5
mV
140
200
270
mV
—
—
10
mV
—
—
—
—
360
—
—
50
—
20
mV
Ω
%
—
—
—
—
—
—
25
15
mVRMS
mVRMS
—
—
0.30
UI
—
—
0.35
UI
—
—
0.30
UI
—
—
0.35
UI
0.08 Gbps–1.5 Gbps
1.1
1.2
1.3
V
—
—
–50
110
—
—
50
—
mV
Ω
—
—
—
—
—
—
25
25
35
ns
ns
ns
40
—
—
ns
20
90
0
—
—
—
—
—
70
ns
ns
pF
Min
Typ
Max
Unit
—
—
12.5
ns
—
–10%
—
10%
UI
—
–5%
—
5%
UI
—
|D-PHY-P – D-PHYN|
—
0.08 Gbps ≤ tR ≤ 1.00
Gbps
1.00 Gbps < tR ≤ 1.50
Gbps
0.08 Gbps ≤ tF ≤ 1.00
Gbps
1.00 Gbps < tF ≤ 1.50
Gbps
—
—
—
First LP XOR Clock
Pulse after STOP
State or Last Pulse
before STOP State
All Other Pulses
—
—
Table 3.25. Soft D-PHY Clock Signal Specification
Symbol
Description
Conditions
Clock Signal Specification
UI
Instantaneous
UIINST
UI Variation
∆UI
—
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FPGA-DS-02078-1.0
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Certus-NX Family
Data Sheet
Table 3.26. Soft D-PHY Data-Clock Timing Specifications
Symbol
Description
Conditions
Min
Typ
Max
Unit
0.08 Gbps ≤ TSKEW[TX]
≤ 1.00 Gbps
-0.15
—
0.15
UIINST
1.00 Gbps < TSKEW[TX]
≤ 1.50 Gbps
-0.20
—
0.20
UIINST
0.08 Gbps ≤ TSKEW[TLIS]
≤ 1.00 Gbps
-0.20
—
0.20
UIINST
1.00 Gbps < TSKEW[TLIS]
≤ 1.50 Gbps
-0.10
—
0.10
UIINST
0.08 Gbps ≤ TSETUP[RX]
≤ 1.00 Gbps
0.15
—
—
UI
1.00 Gbps < TSETUP[RX]
≤ 1.50 Gbps
0.20
—
—
UI
0.08 Gbps ≤ THOLD[RX]
≤ 1.00 Gbps
0.15
—
—
UI
1.00 Gbps < THOLD[RX]
≤ 1.50 Gbps
0.20
—
—
UI
Data-Clock Timing Specifications
TSKEW[TX]
Data to Clock Skew
TSKEW[TLIS]
Data to Clock Skew
TSETUP[RX]
Input Data Setup Before CLK
THOLD[RX]
Input Data Hold After CLK
3.12.7. Differential HSTL15D (Output Only)
Differential HSTL outputs are implemented as a pair of complementary single-ended HSTL outputs.
3.12.8. Differential SSTL135D, SSTL15D (Output Only)
Differential SSTL is used for differential clock in DDR3/DDR3L memory interface. All differential SSTL outputs are
implemented as a pair of complementary single-ended SSTL outputs. All allowable single-ended output classes (class I
and class II) are supported.
3.12.9. Differential HSUL12D (Output Only)
Differential HSUL is used for differential clock in LPDDR2/LPDDR3 memory interface. All differential HSUL outputs are
implemented as a pair of complementary single-ended HSUL12 outputs. All allowable single-ended drive strengths are
supported.
3.12.10. Differential LVCMOS25D, LVCMOS33D, LVTTL33D (Output Only)
Differential LVCMOS and LVTTL outputs are implemented as a pair of complementary single-ended outputs. All
allowable single-ended output drive strengths are supported.
3.13. Certus-NX Maximum sysI/O Buffer Speed
Table 3.27. Certus-NX Maximum I/O Buffer Speed1, 2, 3, 4, 7
Buffer
Description
Banks
Max
Unit
Maximum sysI/O Input Frequency
Single-Ended
LVCMOS33
LVCMOS33, VCCIO = 3.3 V
0, 1, 2, 6, 7
200
MHz
LVTTL33
LVTTL33, VCCIO = 3.3 V
0, 1, 2, 6, 7
200
MHz
LVCMOS25
LVCMOS25, VCCIO = 2.5 V
0, 1, 2, 6, 7
200
MHz
LVCMOS18, VCCIO = 1.8 V
0, 1, 2, 6, 7
200
MHz
LVCMOS18
5
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66
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
Buffer
Description
LVCMOS18H
LVCMOS15 5
LVCMOS15H
5
LVCMOS12 5
LVCMOS12H
5
LVCMOS10 5
LVCMOS10H
5
Banks
Max
Unit
LVCMOS18, VCCIO = 1.8 V
3, 4, 5
200
MHz
LVCMOS15, VCCIO = 1.5 V
0, 1, 2, 6, 7
100
MHz
LVCMOS15, VCCIO = 1.5 V
3, 4, 5
150
MHz
LVCMOS12, VCCIO = 1.2 V
0, 1, 2, 6, 7
50
MHz
LVCMOS12, VCCIO = 1.2 V
3, 4, 5
100
MHz
LVCMOS 1.0, VCCIO = 1.2 V
0, 1, 2, 6, 7
50
MHz
LVCMOS 1.0, VCCIO = 1.0 V
3, 4, 5
50
MHz
LVCMOS10R
LVCMOS 1.0, VCCIO independent
3, 4, 5
50
MHz
SSTL15_I, SSTL15_II
SSTL_15, VCCIO = 1.5 V
3, 4, 5
1066
Mbps
SSTL135_I, SSTL135_II
SSTL_135, VCCIO = 1.35 V
3, 4, 5
1066
Mbps
HSUL12
HSUL_12, VCCIO = 1.2 V
3, 4, 5
1066
Mbps
HSTL15
HSTL15, VCCIO = 1.5 V
3, 4, 5
1066
Mbps
LVDS, VCCIO independent QFN72, caBGA256,
csBGA289, and caBGA400
3, 4, 5
1250
Mbps
LVDS, VCCIO independent csfBGA121
3, 4, 5
1500
Mbps
subLVDS, VCCIO independent QFN72,
caBGA256, csBGA289, and caBGA400
3, 4, 5
1250
Mbps
subLVDS, VCCIO independent csfBGA121
3, 4, 5
1500
Mbps
SLVS similar to MIPI HS, VCCIO independent
QFN72, caBGA256, csBGA289, caBGA400
3, 4, 5
1250
Mbps
SLVS similar to MIPI HS, VCCIO independent
csfBGA121
3, 4, 5
1500
Mbps
SSTL15D
Differential SSTL15, VCCIO independent
3, 4, 5
1066
Mbps
SSTL135D
Differential SSTL135, VCCIO independent
3, 4, 5
1066
Mbps
HUSL12D
Differential HSUL12, VCCIO independent
3, 4, 5
1066
Mbps
HSTL15D
Differential HSTL15, VCCIO independent
3, 4, 5
250
Mbps
Differential
LVDS
subLVDS
SLVS
Maximum sysI/O Output Frequency
Single-Ended
LVCMOS33 (all drive strengths)
LVCMOS33, VCCIO = 3.3 V
0, 1, 2, 6, 7
200
MHz
LVCMOS33 (RS50)
LVCMOS33, VCCIO = 3.3 V, RSERIES = 50 Ω
0, 1, 2, 6, 7
200
MHz
LVTTL33 (all drive strengths)
LVTTL33, VCCIO = 3.3 V
0, 1, 2, 6, 7
200
MHz
LVTTL33 (RS50)
LVTTL33, VCCIO = 3.3 V, RSERIES = 50 Ω
0, 1, 2, 6, 7
200
MHz
LVCMOS25 (all drive strengths)
LVCMOS25, VCCIO = 2.5 V
0, 1, 2, 6, 7
200
MHz
LVCMOS25 (RS50)
LVCMOS25, VCCIO = 2.5 V, RSERIES = 50 Ω
0, 1, 2, 6, 7
200
MHz
LVCMOS18 (all drive strengths)
LVCMOS18, VCCIO = 1.8 V
0, 1, 2, 6, 7
200
MHz
LVCMOS18 (RS50)
LVCMOS18, VCCIO = 1.8 V, RSERIES = 50 Ω
0, 1, 2, 6, 7
200
MHz
LVCMOS18H (all drive strengths)
LVCMOS18, VCCIO = 1.8 V
3, 4, 5
200
MHz
LVCMOS18H (RS50)
LVCMOS18, VCCIO = 1.8 V, RSERIES = 50 Ω
LVCMOS15 (all drive strengths)
LVCMOS15, VCCIO = 1.5 V
LVCMOS15H (all drive strengths)
LVCMOS12 (all drive strengths)
3, 4, 5
200
MHz
0, 1, 2, 6, 7
100
MHz
LVCMOS15, VCCIO = 1.5 V
3, 4, 5
150
MHz
LVCMOS12, VCCIO = 1.2 V
0, 1, 2, 6, 7
50
MHz
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FPGA-DS-02078-1.0
67
Certus-NX Family
Data Sheet
Buffer
Description
Banks
Max
Unit
LVCMOS12H (all drive strengths)
LVCMOS12, VCCIO = 1.2 V
3, 4, 5
100
MHz
LVCMOS10H (all drive strengths)
LVCMOS12, VCCIO = 1.2 V
3, 4, 5
50
MHz
SSTL15_I, SSTL15_II
SSTL_15, VCCIO = 1.5 V
3, 4, 5
1066
Mbps
SSTL135_I, SSTL135_II
SSTL_135, VCCIO = 1.35 V
3, 4, 5
1066
Mbps
HSUL12 (all drive strengths)
HSUL_12, VCCIO = 1.2 V
3, 4, 5
1066
Mbps
HSTL15
HSTL15, VCCIO = 1.5 V
3, 4, 5
250
Mbps
LVDS, VCCIO = 1.8 V QFN72, caBGA256,
csBGA289, and caBGA400
LVDS, VCCIO = 1.8 V csfBGA121
3, 4, 5
1250
Mbps
3, 4, 5
1500
Mbps
Differential9
LVDS
LVDS25E6
LVDS25, Emulated, VCCIO = 2.5 V
0, 1, 2, 6, 7
400
Mbps
SubLVDSE6
subLVDS, Emulated, VCCIO = 1.8 V
0, 1, 2, 6, 7
400
Mbps
SubLVDSEH6
subLVDS, Emulated, VCCIO = 1.8 V
3, 4, 5
800
Mbps
SLVS
SLVS similar to MIPI, VCCIO = 1.2 V
QFN72, caBGA256, csBGA289, caBGA400
3, 4, 5
1250
SLVS similar to MIPI, VCCIO = 1.2 V
csfBGA121
3, 4, 5
1500
SSTL15D
Differential SSTL15, VCCIO = 1.5 V
3, 4, 5
1066
Mbps
SSTL135D
Differential SSTL135, VCCIO = 1.35 V
3, 4, 5
1066
Mbps
HUSL12D
Differential HSUL12, VCCIO = 1.2 V
3, 4, 5
1066
Mbps
HSTL15D
Differential HSTL15, VCCIO = 1.5 V
3, 4, 5
250
Mbps
Mbps
Mbps
Notes:
1. Maximum I/O speed is the maximum switching rate of the I/O operating within the guidelines of the defining standard. The
actual interface speed performance using the I/O also depends on other factors, such as internal and external timing.
2. These numbers are characterized but not test on every device.
3. Performance is specified in MHz, as defined in clock rate when the sysI/O is used as pin. For data rate performance, this can be
converted to Mbps, which equals to 2 times the clock rate.
4. LVCMOS and LVTTL are measured with load specified in Table 3.43.
5. These LVCMOS inputs can be placed in different VCCIO voltage. Performance may vary. Please refer to Lattice Design Software
6. These emulated outputs performance is based on externally properly terminated as described in LVDS25E (Output Only) and
SubLVDSE/SubLVDSEH (Output Only).
7. All speeds are measured with fast slew.
8. For maximum differential I/O performance only Differential I/O should be placed in the bottom I/O banks. If this is not possible,
the following will impact on maximum performance:
a. If Fast Slew Rate LVCMOS I/O are used, they should be limited to no more than nine I/O (adjacent), four I/O (same bank),
55 I/O (left/right banks) to keep degradation below 50%.
b. If non-Differential I/O (SLOW SLEW) are placed on the bottom but not within the same bank as differential I/O, then the
maximum Differential performance is degraded to 70% of original when 21 aggressors are toggling.
c. If non-Differential I/O (SLOW SLEW) are placed within the same bank as Differential I/O then the maximum performance is
degraded to 50% of original when 16 aggressor are toggling.
d. If Differential RX/TX I/O are both placed within the same bank then the maximum performance is degraded to 90%.
e. For DDR3/3L, LPDDR2/3 separate DQ/DQS groups from Address/Commands/CLK groups into separate banks.
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68
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
3.14. Typical Building Block Function Performance
These building block functions can be generated using Lattice Design Software Tool. Exact performance may vary with
the device and the design software tool version. The design software tool uses internal parameters that have been
characterized but are not tested on every device.
Table 3.28. Pin-to-Pin Performance
Typ. @ VCC =
1.0 V
Unit
16-bit Decoder (I/O configured with LVCMOS18, Left and Right Banks)
5.5
ns
16-bit Decoder (I/O configured with HSTL15_I, Bottom Banks)
5.1
ns
6
ns
6.1
ns
Function
16:1 Mux (I/O configured with LVCMOS18, Left and Right Banks)
16:1 Mux (I/O configured with HSTL15_I, Bottom Banks)
Note: These functions are generated using Lattice Radiant Design Software tool. Exact performance may vary with the device and
the design software tool version. The design software tool uses internal parameters that have been characterized but are not tested
on every device.
Table 3.29. Register-to-Register Performance
Typ. @ VCC =
1.0 V
Unit
16-bit Adder
5002
MHz
32-bit Adder
496
MHz
16-bit Counter
402
MHz
32-bit Counter
371
MHz
512 × 36 Single Port RAM, with Output Register
5002
MHz
1024 × 18 True-Dual Port RAM using same clock, with EBR Output Registers
5002
MHz
1024 × 18 True-Dual Port RAM using asynchronous clocks, with EBR Output Registers
5002
MHz
32 k × 32 Single Port RAM, with Output Register
1652
MHz
32 k × 32 Single Port RAM with ECC, with Output Register
1302
MHz
32 k × 32 True-Dual Port RAM using same clock, with Output Registers
340
MHz
16 × 4 Single Port RAM (One PFU)
5002
MHz
16 × 2 Pseudo-Dual Port RAM (One PFU)
5002
MHz
16 × 4 Pseudo-Dual Port (Two PFUs)
5002
MHz
9 × 9 Multiplier with Input Output Registers
351
MHz
9 × 9 Multiplier with Input/Pipelined/Output Registers
240
MHz
18 × 18 Multiplier with Input/Output Registers
214
MHz
18 × 18 Multiplier with Input/Pipelined/Output Registers
191
MHz
36 × 36 Multiplier with Input/Output Registers
201
MHz
36 × 36 Multiplier with Input/Pipelined/Output Registers
129
MHz
MAC 9 × 9 with Input/Output Registers
218
MHz
MAC 9 × 9 with Input/Pipelined/Output Registers
238
MHz
Function
Basic Functions
Embedded Memory Functions
Large Memory Functions
Distributed Memory Functions
DSP Functions
Notes:
1. The Clock port is configured with LVDS I/O type. Performance Grade: 9_High-Performance_1.0V.
2. Limited by the Minimum Pulse Width of the component
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FPGA-DS-02078-1.0
69
Certus-NX Family
Data Sheet
3.
4.
These functions are generated using Lattice Radiant Design Software tool. Exact performance may vary with the device and the
design software tool version. The design software tool uses internal parameters that have been characterized but are not
tested on every device.
For the Pipelined designs, the number of pipeline stages used are 2.
3.15. LMMI
Table 3.30 summarizes the performance of the LMMI interface with supported IPs. Additional timing requirement and
constraint can be identified through the Lattice Radiance design tools.
Table 3.30. LMMI FMAX Summary
IP
FMAX (MHz)
CDR0
73
CDR1
70
DPHY0
67
DPHY1
55
CRE
54
I2 C
38
PCIe
57
PLL_ULC
59
PLL_LLC
55
PLL_LRC
37
3.16. Derating Timing Tables
Logic timing provided in the following sections of this data sheet and the Lattice Radiant design tools are worst case
numbers in the operating range. Actual delays at nominal temperature and voltage for best case process, can be much
better than the values given in the tables. The Lattice Radiant design tool can provide logic timing numbers at a
particular temperature and voltage.
3.17. Certus-NX External Switching Characteristics
Over recommended commercial operating conditions.
Table 3.31. Certus-NX External Switching Characteristics (VCC = 1.0 V)
Parameter
Clocks
Primary Clock
fMAX_PRI
tW_PRI
tSKEW_PRI
Edge Clock
fMAX_EDGE
tW_EDGE
tSKEW_EDGE
Description
Frequency for Primary Clock
Clock Pulse Width for
Primary Clock
Primary Clock Skew Within a
Device
Frequency for Edge Clock
Tree
Clock Pulse Width for Edge
Clock
Edge Clock Skew Within a
Device
–9
–8
–7
Unit
Min
Max
Min
Max
Min
Max
—
400
—
325.2
—
276
MHz
1.125
—
1.384
—
1.63
—
ns
—
450
—
554
—
653
ps
—
800
—
650.4
—
551.7
MHz
0.537
—
0.661
—
0.779
—
ns
—
120
—
148
—
174
ps
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70
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
Parameter
Description
–9
Min
–8
Max
Min
–7
Unit
Max
Min
Max
—
6.64
—
7.83
ns
0
—
0
—
ns
3.32
—
3.92
—
ns
1.84
—
1.84
—
ns
0.16
—
0.16
—
ns
—
4.67
—
5.51
ns
1.23
—
1.23
—
ns
1.21
—
1.42
—
ns
4.74
—
4.74
—
ns
0
—
0
—
ns
Generic SDR Input
General I/O Pin Parameters Using Dedicated Primary Clock Input without PLL
Clock to Output - PIO
—
6.45
Output Register
Clock to Data Setup - PIO
tSU
0
—
Input Register
Clock to Data Hold - PIO
tH
2.94
—
Input Register
Clock to Data Setup - PIO
tSU_DEL
1.84
—
Input Register with Data
Input Delay
Clock to Data Hold - PIO
tH_DEL
0.16
—
Input Register with Data
Input Delay
General I/O Pin Parameters Using Dedicated Primary Clock Input with PLL
tCOPLL
Clock to Output - PIO
—
4.02
Output Register
tSUPLL
Clock to Data Setup - PIO
1.23
—
Input Register
tHPLL
Clock to Data Hold - PIO
0.98
—
Input Register
tSU_DELPLL
Clock to Data Setup - PIO
Input Register with Data
4.74
—
Input Delay
tH_DELPLL
Clock to Data Hold - PIO
Input Register with Data
0
—
Input Delay
Generic DDR Input/Output
tCO
Generic DDRX1 Inputs/Outputs with Clock and Data Centered at Pin (GDDRX1_RX/TX.SCLK.Centered) using PCLK Clock Input Figure 3.7 and Figure 3.9
0.550
—
0.550
—
0.648
—
ns
tSU_GDDR1
Input Data Setup Before CLK
0.275
—
0.275
—
0.275
—
UI
tHO_GDDR1
Input Data Hold After CLK
0.550
—
0.550
—
0.648
—
ns
0.700
—
0.631
—
0.744
—
ns
Output Data Valid After CLK
tDVB_GDDR1
Output
–0.300
—
–0.369
—
–0.435
—
ns + 1/2 UI
0.700
—
0.631
—
0.744
—
ns
Output Data Valid After CLK
tDQVA_GDDR1
Output
–0.300
—
–0.369
—
–0.435
—
ns + 1/2 UI
fDATA_GDDRX1
Input/Output Data Rate
—
500
—
500.0
—
424
Mbps
fMAX_GDDRX1
Frequency of PCLK
—
250
—
250
—
212
MHz
—
Half of Data Bit Time, or 90
½ UI
—
1.000
—
1.179
—
ns
degree
Output TX to Input RX Margin per Edge
0.150
—
0.081
—
0.095
—
ns
Generic DDRX1 Inputs/Outputs with Clock and Data Aligned at Pin (GDDRX1_RX/TX.SCLK.Aligned) using PCLK Clock Input Figure 3.8 and Figure 3.10
—
-0.550
—
–0.550
—
-0.648
ns + 1/2 UI
tDVA_GDDR1
Input Data Valid After CLK
—
0.450
—
0.450
—
0.530
ns
—
0.225
—
0.225
—
0.225
UI
tDVE_GDDR1
Input Data Hold After CLK
0.550
1.550
0.775
—
—
—
0.550
1.550
0.775
—
—
—
0.648
1.827
0.775
—
—
—
ns + 1/2 UI
ns
UI
© 2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02078-1.0
71
Certus-NX Family
Data Sheet
Parameter
Description
tDIA_GDDR1
–9
–8
–7
Unit
Min
Max
Min
Max
Min
Max
Output Data Invalid After
CLK Output
—
0.300
—
0.369
—
0.435
ns
tDIB_GDDR1
Output Data Invalid Before
CLK Output
—
0.300
—
0.369
—
0.435
ns
fDATA_GDDRX1
Input/Output Data Rate
—
500
—
500
—
424
Mbps
fMAX_GDDRX1
Frequency for PCLK
—
250
—
250
—
212
MHz
½ UI
Half of Data Bit Time, or 90
degree
1.000
—
1.000
—
1.179
—
ns
0.150
—
0.081
—
0.095
—
ns
Output TX to Input RX Margin per Edge
Generic DDRX2 Inputs/Outputs with Clock and Data Centered at Pin (GDDRX2_RX/TX.ECLK.Centered) using PCLK Clock Input Figure 3.7 and Figure 3.9
0.175
—
0.175
—
0.206
—
ns
tSU_GDDRX2
Data Setup before CLK Input
0.175
—
0.175
—
0.175
—
UI
tHO_GDDRX2
Data Hold after CLK Input
0.177
—
0.177
—
0.206
—
ns
0.380
—
0.352
—
0.415
—
ns
Output Data Valid Before
tDVB_GDDRX2
CLK Output
-0.120
—
–0.148
—
–0.174
—
ns + 1/2 UI
0.380
—
0.352
—
0.415
—
ns
Output Data Valid After CLK
tDQVA_GDDRX2
Output
-0.120
—
–0.148
—
–0.174
—
ns + 1/2 UI
fDATA_GDDRX2
Input/Output Data Rate
—
1000
—
1000
—
848
Mbps
fMAX_GDDRX2
Frequency for ECLK
—
500
—
500
—
424
MHz
Half of Data Bit Time, or 90
½ UI
0.500
—
0.500
—
0.589
—
ns
degree
fPCLK
PCLK frequency
—
250.0
—
250.0
—
212.1
MHz
Output TX to Input RX Margin per Edge
0.230
—
0.202
—
0.239
—
ns
Generic DDRX2 Inputs/Outputs with Clock and Data Aligned at Pin (GDDRX2_RX/TX.ECLK.Aligned) using PCLK Clock Input Figure 3.8 and Figure 3.10
—
–0.275
—
-0.275
—
–0.324
ns + 1/2 UI
—
0.225
—
0.225
—
0.265
ns
tDVA_GDDRX2
Input Data Valid After CLK
—
—
—
0.225
0.225
0.225
UI
tDVE_GDDRX2
Input Data Hold After CLK
Output Data Invalid After
CLK Output
Output Data Invalid Before
tDIB_GDDRX2
CLK Output
fDATA_GDDRX2
Input/Output Data Rate
fMAX_GDDRX2
Frequency for ECLK
Half of Data Bit Time, or 90
½ UI
degree
fPCLK
PCLK frequency
Output TX to Input RX Margin per Edge
tDIA_GDDRX2
0.275
0.775
0.775
—
—
—
0.275
0.775
0.775
—
—
—
0.324
0.914
0.775
—
—
—
ns + 1/2 UI
ns
UI
—
0.120
—
0.148
—
0.174
ns
—
0.120
—
0.148
—
0.174
ns
—
—
1000
500
—
—
1000
500
—
—
848
424
Mbps
MHz
0.500
—
0.500
—
0.589
—
ns
—
0.105
250.0
—
—
0.077
250.0
—
—
0.091
212.1
—
MHz
ns
Generic DDRX4 Inputs/Outputs with Clock and Data Centered at Pin (GDDRX4_RX/TX.ECLK.Centered) using PCLK Clock Input Figure 3.7 and Figure 3.9
0.168
—
0.210
—
0.244
—
ns
Input Data Set-Up Before
tSU_GDDRX4
CLK
0.252
—
0.252
—
0.252
—
UI
tHO_GDDRX4
Input Data Hold After CLK
0.174
—
0.210
—
0.244
—
ns
© 2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
72
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
Parameter
Description
tDVB_GDDRX4
Output Data Valid Before
CLK Output
tDQVA_GDDRX4
Input/Output Data Rate
fDATA_GDDRX4
fMAX_GDDRX4
Frequency for ECLK
PCLK frequency
Half of Data Bit Time, or 90
½ UI
degree
Input Data Set-Up Before
fPCLK
CLK
Output TX to Input RX Margin per Edge
–9
–8
–7
Unit
Min
0.213
-0.120
0.213
-0.120
—
—
Max
—
—
—
—
1500
750.0
Min
0.269
–0.148
0.269
–0.148
—
—
Max
—
—
—
—
1200
600
Min
0.309
–0.174
0.309
–0.174
—
—
Max
—
—
—
—
1034
517
Mbps
MHz
0.333
—
0.417
—
0.483
—
ns
—
187.5
—
150.0
—
129.3
MHz
0.080
—
0.102
—
0.116
—
ns
Generic DDRX4 Inputs/Outputs with Clock and Data Aligned at Pin (GDDRX4_RX/TX.ECLK.Aligned) using PCLK Clock Input, Left
and Right sides Only - Figure 3.8 and Figure 3.10
—
–0.183
—
–0.229
—
–0.266
ns + 1/2 UI
tDVA_GDDRX4
Input Data Valid After CLK
—
0.150
—
0.188
—
0.218
ns
—
0.225
—
0.225
—
0.225
UI
0.183
—
0.229
—
0.266
—
ns + 1/2 UI
tDVE_GDDRX4
Input Data Hold After CLK
0.517
—
0.646
—
0.749
—
ns
0.775
—
0.775
—
0.775
—
UI
—
—
—
Output Data Invalid After
tDIA_GDDRX4
0.120
0.148
0.17
ns
CLK Output
tDIB_GDDRX4
Output Data Invalid Before
CLK Output
—
fDATA_GDDRX4
fMAX_GDDRX4
Input/Output Data Rate
Frequency for ECLK
—
—
1500
750
—
—
1200
600
½ UI
Half of Data Bit Time, or 90
degree
0.333
—
0.417
fPCLK
PCLK frequency
—
187.5
—
0.120
—
0.148
—
0.174
ns
—
—
1034
517
Mbps
MHz
—
0.483
—
ns
150.0
—
129.3
MHz
Output TX to Input RX Margin per Edge
0.030
—
0.040
—
0.044
—
ns
Generic DDRX5 Inputs/Outputs with Clock and Data Centered at Pin (GDDRX5_RX/TX.ECLK.Centered) using PCLK Clock Input Figure 3.7 and Figure 3.9
0.179
—
0.187
—
0.224
—
ns
Input Data Set-Up Before
tSU_GDDRX5
CLK
0.224
—
0.224
—
0.224
—
UI
tHO_GDDRX5
Input Data Hold After CLK
0.181
—
0.187
—
0.224
—
ns
tWINDOW_GDDRX5C
Input Data Valid Window
0.36
—
0.374
—
0.448
—
ns
0.280
—
0.269
—
0.326
—
ns
Output Data Valid Before
tDVB_GDDRX5
CLK Output
–0.120
—
–0.148
—
–0.174
—
ns+1/2UI
0.280
—
0.269
—
0.326
—
ns
Output Data Valid After CLK
tDQVA_GDDRX5
Output
–0.120
—
–0.148
—
–0.174
—
ns+1/2UI
fDATA_GDDRX5
Input/Output Data Rate
—
1250
—
1200
—
1000
Mbps
fMAX_GDDRX5
Frequency for ECLK
—
625
—
600
—
500
MHz
Half of Data Bit Time, or 90
degree
PCLK frequency
½ UI
fPCLK
Output TX to Input RX Margin per Edge
0.400
—
0.417
—
0.500
—
ns
—
125.0
—
120.0
—
100.0
MHz
0.120
—
0.102
—
0.126
—
ns
© 2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02078-1.0
73
Certus-NX Family
Data Sheet
Parameter
Description
–9
Min
–8
Max
Min
–7
Max
Min
Max
Unit
Generic DDRX5 Inputs/Outputs with Clock and Data Aligned at Pin (GDDRX5_RX/TX.ECLK.Aligned) using PCLK Clock Input Figure 3.8 and Figure 3.10
—
–0.220
—
–0.229
—
–0.275
ns + 1/2 UI
tDVA_GDDRX5
Input Data Valid After CLK
—
0.180
—
0.188
—
0.225
ns
—
0.225
—
0.225
—
0.225
UI
0.220
—
0.229
—
0.275
—
ns + 1/2 UI
tDVE_GDDRX5
Input Data Hold After CLK
0.620
—
0.646
—
0.775
—
ns
0.775
—
0.775
—
0.775
—
UI
tWINDOW_GDDRX5A
Input Data Valid Window
0.440
—
0.458
—
0.550
—
ns
Output Data Invalid After
—
0.120
—
0.148
CLK Output
Output Data Invalid Before
tDIB_GDDRX5
—
0.120
—
0.148
CLK Output
fDATA_GDDRX5
Input/Output Data Rate
—
1250
—
1200
fMAX_GDDRX5
Frequency for ECLK
—
625
—
600
Half of Data Bit Time, or 90
½ UI
0.400
—
0.417
—
degree
fPCLK
PCLK frequency
—
125.0
—
120.0
Output TX to Input RX Margin per Edge
0.060
—
0.040
—
Soft D-PHY DDRX4 Inputs/Outputs with Clock and Data Centered at Pin, using PCLK Clock Input
0.133
—
0.167
—
Input Data Set-Up Before
tSU_GDDRX4_MP
CLK
0.2
—
0.2
—
tHO_GDDRX4_MP
Input Data Hold After CLK
0.133
—
0.167
—
0.133
—
0.167
—
Output Data Valid Before
tDVB_GDDRX4_MP
CLK Output
0.2
—
0.2
—
tDIA_GDDRX5
—
0.174
ns
—
0.174
ns
—
—
1000
500
Mbps
MHz
0.500
—
ns
—
0.051
100.0
—
MHz
ns
0.193
0.2
0.193
0.193
—
—
—
—
ns
UI
ns
ns
—
—
—
UI
ns
UI
1034
Mbps
tDQVA_GDDRX4_MP
Output Data Valid After CLK
Output
0.133
0.2
—
—
0.167
0.2
—
—
0.2
0.193
0.2
fDATA_GDDRX4_MP
Input Data Bit Rate for MIPI
PHY
—
1500
—
1200
—
Half of Data Bit Time, or 90
0.333
—
0.417
—
0.483
—
ns
degree
fPCLK
PCLK frequency
—
187.5
—
150.0
—
129.3
MHz
Output TX to Input RX Margin per Edge
0.067
0.083
0.097
ns
Video DDRX71 Inputs/Outputs with Clock and Data Aligned at Pin (GDDRX71_RX.ECLK) using PLL Clock Input - Figure 3.12 and
Figure 3.13
—
0.264
—
0.264
—
0.3
UI
Input Valid Bit "i" switch
tRPBi_DVA
from CLK Rising Edge ("i" = 0
—
—
—
–0.250
–0.250
–0.249 ns+(1/2+i)*UI
to 6, 0 aligns with CLK)
0.722
—
0.722
—
0.7
—
UI
Input Hold Bit "i" switch
tRPBi_DVE
from CLK Rising Edge ("i" = 0
—
—
—
0.235
0.235
0.249
ns+(1/2+i)*UI
to 6, 0 aligns with CLK)
Data Output Valid Bit "i"
switch from CLK Rising Edge
tTPBi_DOV
—
0.159
—
0.159
—
0.187
ns+i*UI
("i" = 0 to 6, 0 aligns with
CLK)
Data Output Invalid Bit "i"
switch from CLK Rising Edge
tTPBi_DOI
-0.159
—
-0.159
—
-0.187
—
ns+(i+ 1)*UI
("i" = 0 to 6, 0 aligns with
CLK)
tTPBi_skew_UI
TX skew in UI
—
0.150
—
0.150
—
0.150
UI
½ UI
© 2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
74
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
Parameter
Description
–9
Min
1.058
—
—
—
0.159
–8
Max
—
945
473
135.0
—
Min
1.058
—
—
—
0.159
–7
Max
—
945
473
135.0
—
Min
1.247
—
—
—
0.187
Max
—
802
401
114.5
—
Unit
tB
Serial Data Bit Time, = 1UI
ns
fDATA_TX71
DDR71 Serial Data Rate
Mbps
fMAX_TX71
DDR71 ECLK Frequency
MHz
fCLKIN
7:1 Clock (PCLK) Frequency
MHz
Output TX to Input RX Margin per Edge
ns
Memory Interface
DDR3/DDR3L/LPDDR2/LPDDR3 READ (DQ Input Data are Aligned to DQS) - Figure 3.8
tDVBDQ_DDR3
tDVBDQ_DDR3L
Data Input Valid before DQS
—
–0.235
—
–0.235
—
–0.277
ns + 1/2 UI
tDVBDQ_LPDDR2
Input
tDVBDQ_LPDDR3
tDVADQ_DDR3
tDVADQ_DDR3L
Data Input Valid after DQS
0.235
—
0.235
—
0.277
—
ns + 1/2 UI
tDVADQ_LPDDR2
Input
tDVADQ_LPDDR3
fDATA_DDR3 fDATA_DDR3L
fDATA_LPDDR2
DDR Memory Data Rate
—
1066
—
1066
—
904
Mb/s
fDATA_LPDDR3
fMAX_ECLK_DDR3
fMAX_ECLK_DDR3L
DDR Memory ECLK
—
533
—
533
—
452
MHz
fMAX_ECLK_LPDDR2
Frequency
fMAX_ECLK_LPDDR3
fMAX_SCLK_DDR3
fMAX_SCLK_DDR3L
DDR Memory SCLK
—
133.3
—
133.3
—
113
MHz
fMAX_SCLK_LPDDR2
Frequency
fMAX_SCLK_LPDDR3
DDR3/DDR3L/LPDDR2/LPDDR3 WRITE (DQ Output Data are Centered to DQS) - Figure 3.11
tDQVBS_DDR3
tDQVBS_DDR3L
Data Output Valid before
—
–0.235
—
–0.235
—
–0.277
ns + 1/2 UI
tDQVBS_LPDDR2
DQS Output
tDQVBS_LPDDR3
tDQVAS_DDR3
tDQVAS_DDR3L
Data Output Valid after DQS
0.235
—
0.235
—
0.277
—
ns + 1/2 UI
tDQVAS_LPDDR2
Output
tDQVAS_LPDDR3
fDATA_DDR3 fDATA_DDR3L
fDATA_LPDDR2
DDR Memory Data Rate
—
1066
—
1066
—
904
Mb/s
fDATA_LPDDR3
fMAX_ECLK_DDR3
fMAX_ECLK_DDR3L
DDR Memory ECLK
—
533
—
533
—
452
MHz
fMAX_ECLK_LPDDR2
Frequency
fMAX_ECLK_LPDDR3
fMAX_SCLK_DDR3
fMAX_SCLK_DDR3L
DDR Memory SCLK
—
133.3
—
133.3
—
113
MHz
fMAX_SCLK_LPDDR2
Frequency
fMAX_SCLK_LPDDR3
Notes:
1. Commercial timing numbers are shown. Industrial numbers are typically slower and can be extracted from the Lattice Radiant
software.
2. General I/O timing numbers are based on LVCMOS 1.8, 8 mA, Fast Slew Rate, 0 pf load.
Generic DDR timing are numbers based on LVDS I/O.
DDR3 timing numbers are based on SSTL15.
LPDDR2 and LPDDR3 timing numbers are based on HSUL12.
© 2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02078-1.0
75
Certus-NX Family
Data Sheet
3.
4.
5.
Uses LVDS I/O standard for measurements.
Maximum clock frequencies are tested under best case conditions. System performance may vary upon the user environment.
All numbers are generated with the Lattice Radiant software.
Rx CLK (in)
Rx DATA (in)
tSU/tDVBDQ
tSU/tDVBDQ
tHD/tDVADQ
tHD/tDVADQ
Figure 3.7. Receiver RX.CLK.Centered Waveforms
1/2 UI
Rx CLK (in)
or DQS Input
1/2 UI
1 UI
Rx DATA (in)
or DQ Input
tSU
tSU
tHD
tHD
Figure 3.8. Receiver RX.CLK.Aligned and DDR Memory Input Waveforms
1/2 UI
1/2 UI
1/2 UI
1/2 UI
Tx CLK (out)
or DQS Output
Tx DATA (out)
or DQ Output
tDVB/tDQVBS
tDVB/tDQVBS
tDVA/tDQVA
tDVA/tDQVAS
Figure 3.9. Transmit TX.CLK.Centered and DDR Memory Output Waveforms
© 2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
76
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
1 UI
Tx CLK (out)
Tx DATA (out)
tDIB
tDIB
tDIA
tDIA
Figure 3.10. Transmit TX.CLK.Aligned Waveforms
Receiver – Shown for one LVDS Channel
# of Bits
Data In
756 Mb/s
Clock In
108 MHz
For each Channel:
7-bit Output Words
to FPGA Fabric
Bit #
10 – 1
11 – 2
12 – 3
13 – 4
14 – 5
15 – 6
16 – 7
0x
0x
0x
0x
0x
0x
0x
Bit #
20 – 8
21 – 9
22 – 10
23 – 11
24 – 12
25 – 13
26 – 14
Bit #
30 – 15
31 – 16
32 – 17
33 – 18
34 – 19
35 – 20
36 – 21
Bit #
40 – 22
41 – 23
42 – 24
43 – 25
44 – 26
45 – 27
46 – 28
Transmitter – Shown for one LVDS Channel
# of Bits
Data Out
756 Mb/s
Clock Out
108 MHz
For each Channel:
7-bit Output Words
to FPGA Fabric
Bit #
00 – 1
00 – 2
00 – 3
00 – 4
00 – 5
00 – 6
00 – 7
Bit #
10 – 8
11 – 9
12 – 10
13 – 11
14 – 12
15 – 13
16 – 14
Bit #
20 – 15
21 – 16
22 – 17
23 – 18
24 – 19
25 – 20
26 – 21
Bit #
30 – 22
31 – 23
32 – 24
33 – 25
34 – 26
35 – 27
36 – 28
Figure 3.11. DDRX71 Video Timing Waveforms
© 2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02078-1.0
77
Certus-NX Family
Data Sheet
Bit 0
1/2 UI
CLK (in)
Bit i
1/2 UI
Bit 1
1 UI
DATA (in)
tSU_0
tHD_0
tSU_i
tHD_i
Figure 3.12. Receiver DDRX71_RX Waveforms
Bit 0
Bit i
Bit 1
1 UI
CLK (out)
DATA (out)
tDIB_0
tDIA_0
tDIB_i
tDIA_i
Figure 3.13. Transmitter DDRX71_TX Waveforms
3.18. Certus-NX sysCLOCK PLL Timing (VCC = 1.0 V)
Table 3.32. sysCLOCK PLL Timing (VCC = 1.0 V)
Parameter
Descriptions
Conditions
Min
Typ.
Max
Units
fIN
Input Clock Frequency (CLKI, CLKFB)
—
10
—
500
MHz
fOUT
Output Clock Frequency
—
6.25
—
800
MHz
fVCO
PLL VCO Frequency
—
800
—
1600
MHz
fPFD3
Phase Detector Input Frequency
Without FractionalN
Enabled
With
Fractional-N
10
—
500
MHz
10
—
100
MHz
AC Characteristics
Enabled
tDT
Output Clock Duty Cycle
—
45
—
tPH4
Output Phase Accuracy
—
–5
—
5
%
fOUT ≥ 200 MHz
—
—
250
ps p-p
fOUT < 200 MHz
—
—
0.05
UIPP
tOPJIT1
Output Clock Period Jitter
55
%
© 2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
78
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
Parameter
Descriptions
Conditions
Min
Typ.
Max
Units
fIN
Input Clock Frequency (CLKI, CLKFB)
—
10
—
500
MHz
fOUT
Output Clock Frequency
—
6.25
—
800
MHz
fVCO
PLL VCO Frequency
—
800
—
1600
MHz
fPFD3
Phase Detector Input Frequency
Without FractionalN
Enabled
With
Fractional-N
10
—
500
MHz
10
—
100
MHz
Output Clock Cycle-to-Cycle Jitter
Output Clock Phase Jitter
Enabled
fOUT ≥ 200 MHz
—
—
250
fOUT < 200 MHz
—
—
0.05
UIPP
fPFD ≥ 200 MHz
—
—
250
ps p-p
fPFD < 200 MHz
—
—
0.05
UIPP
fOUT ≥ 200 MHz
—
—
350
ps p-p
fOUT < 200 MHz
—
—
0.07
UIPP
fOUT ≥ 200 MHz
—
—
400
ps p-p
fOUT < 200 MHz
—
—
0.08
UIPP
13
MHz
10
ms
ps p-p
Output Clock Period Jitter (Fractional-N)
Output Clock Cycle-to-Cycle Jitter (Fractional-N)
fBW4
PLL Loop Bandwidth
—
0.45
tLOCK2
PLL Lock-in Time
—
—
—
tUNLOCK
PLL Unlock Time (from RESET goes HIGH)
—
—
—
50
ns
fPFD ≥ 20 MHz
—
—
500
ps p-p
tIPJIT
Input Clock Period Jitter
fPFD < 20 MHz
—
—
0.01
UIPP
tHI
Input Clock High Time
90% to 90%
0.5
—
—
ns
tLO
Input Clock Low Time
10% to 10%
0.5
—
—
ns
tRST
RST/ Pulse Width
—
1
—
—
ms
fSSC_MOD
Spread Spectrum Clock Modulation Frequency
—
20
—
200
kHz
fSSC_MOD_AMP
Spread Spectrum Clock Modulation Amplitude
Range
—
0.25
—
2.00
%
fSSC_MOD_STEP
Spread Spectrum Clock Modulation Amplitude
Step Size
—
—
0.25
—
%
Notes:
1. Jitter sample is taken over 10,000 samples for Period jitter, and 1,000 samples for Cycle-to-Cycle jitter of the primary PLL output
with clean reference clock with no additional I/O toggling.
2. Output clock is valid after tLOCK for PLL reset and dynamic delay adjustment.
3. Period jitter and cycle-to-cycle jitter numbers are guaranteed for fPFD > 10 MHz. For fPFD < 10 MHz, the jitter numbers may not
be met in certain conditions.
4. Result from Lattice Radiant software.
© 2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02078-1.0
79
Certus-NX Family
Data Sheet
3.19. Certus-NX Internal Oscillators Characteristics
Table 3.33. Internal Oscillators (VCC = 1.0 V)
Symbol
Parameter Description
fCLKHF
fCLKLF
DCHCLKHF
DCHCLKLF
Min
Typ
Max
Unit
HFOSC CLKK Clock Frequency
405
LFOSC CLKK Clock Frequency
25.6
450
495
MHz
32
38.4
kHz
HFOSC Duty Cycle (Clock High Period)
LFOSC Duty Cycle (Clock High Period)
45
50
55
%
45
50
55
%
3.20. Certus-NX User I2C Characteristics
Table 3.34. User I2C Specifications (VCC = 1.0 V)
Symbol
fscl
TDELAY
Parameter
Description
SCL Clock
Frequency
Optional delay
through delay block
STD Mode
FAST Mode Plus2
FAST Mode
Units
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
—
—
100
—
—
400
—
—
1000
kHz
—
62
—
—
62
—
—
62
—
ns
Notes:
1. Refer to the I2C Specification for timing requirements. User design should set constraints in Lattice Design Software to meet this
industrial I2C Specification.
2. Fast Mode Plus maximum speed may be achieved by using external pull up resistor on I2C bus. Internal pull up may not be
sufficient to support the maximum speed.
3.21. Certus-NX Analog-Digital Converter (ADC) Block Characteristics
Table 3.35. ADC Specifications
Symbol
NRES_ADC
ENOBADC
Description
ADC External Reference
Voltage (ADC_REFA or
ADC_REFB)
ADC Resolution
Effective Number of Bits
VSR_ADC
ADC Input Range
VREFEXT_ADC
Condition
—
—
—
Bipolar Mode
Uni-polar Mode
VCM_ADC
fCLK_ADC
DCCLK_ADC
fINPUT_ADC
FSADC
NTRACK_ADC
RIN_ADC
tCAL_ADC
LOUTput_ADC
DNLADC
INLADC
ADC Input Common Mode
Voltage (for fully differential
signals)
ADC Clock Frequency
ADC Clock Duty Cycle
ADC Input Frequency
ADC Sampling Rate
ADC Input Tracking Time
—
—
—
—
—
ADC Input Equivalent
Resistance
ADC Calibration Time
1 MS/s, Sampled @ 2 clock
cycles
—
ADC Conversion Time
ADC Differential
Nonlinearity
ADC Integral Nonlinearity
Min
Typ
Max
Unit
1.0
—
1.8
V
—
—
12
10.8
—
—
bits
bits
VCM_ADC ―
VREFEXT_ADC/4
0
VCM_ADC
—
VCM_ADC +
VREFEXT_ADC/4
VREFEXT_ADC
V
V
VREFEXT_ADC/4
VREFEXT_ADC/2
1
48
—
—
2
25
50
—
1
—
VREFEXT_ADC
–
VREFEXT_ADC/4
40
52
500
—
—
—
116
—
kΩ
—
—
6500
cycles
—
25
—
—
cycles
—
–0.9
—
0.9
LSB
—
–1.5
—
1.5
LSB
V
MHz
%
kHz
MS/s
cycles
© 2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
80
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
Symbol
SFDRADC
THDADC
SNRADC
SNDRADC
Description
ADC Spurious Free Dynamic
Range
ADC Total Harmonic
Distortion
ADC Signal to Noise Ratio
ADC Signal to Noise Plus
Distortion Ratio
Condition
Min
Typ
Max
Unit
—
74
77
—
dBc
—
—
–76
–73
dB
—
65.7
67.5
—
dB
—
65
67
—
dB
ERRGAIN_ADC
ADC Gain Error
—
—
0.5
1.0
ERROFFSET_ADC
ADC Offset Error
—
—
0.5
1.0
CIN_ADC
ADC Input Equivalent
Capacitance
—
—
2
—
%
FSADC
%
FSADC
pF
3.22. Certus-NX Comparator Block Characteristics
Table 3.36. Comparator Specifications
Symbol
Description
Min
Typ
Max
Unit
fIN_COMP
Comparator Input Frequency
—
—
10
MHz
VIN_COMP
Comparator Input Voltage
0
—
VCCADC18
V
VOFFSET_COMP
Comparator Input Offset
–23
—
24
mV
VHYST_COMP
Comparator Input Hysteresis
10
—
31
mV
VLATENCY_COMP
Comparator Latency
—
—
31
ns
3.23. Certus-NX Digital Temperature Readout Characteristics
Digital temperature Readout (DTR) is implemented in one of the channels of ADC1.
Table 3.37. DTR Specifications
Symbol
Description
DTRRANGE
DTR Detect Temperature
Range
Condition
—
Min
Typ
Max
Unit
–40
—
100
°C
with external voltage*
°C
DTRACCURACY
DTR Accuracy
–13
±4
13
reference range of 1.0 V
to 1.8 V
°C
with external voltage
DTRRESOLUTION DTR Resolution
–0.3
—
0.3
reference
*Note: External voltage reference (VREF) should be 0.1% accurate or better. DTR sensitivity to VREF is -4.1 °C per VREF per-cent (for
example, if the VREF is 1 % low, then the DTR will read +4.1 °C high).
© 2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02078-1.0
81
Certus-NX Family
Data Sheet
3.24. Certus-NX Hardened PCIe Characteristics
3.24.1. PCIe (2.5 Gbps)
Table 3.38. PCIe (2.5 Gbps)
Symbol
Transmitter1
UI
BWTX
VTX-DIFF-PP
VTX-DIFF-PP-LOW
VTX-DE-RATIO-3.5dB
TTX-RISE-FALL
TTX-EYE
TTX-EYE-MEDIAN-to-MAXJITTER
RLTX-DIFF
RLTX-CM
ZTX-DIFF-DC
VTX-CM-AC-P
ITX-SHORT
VTX-DC-CM
VTX-IDLE-DIFF-AC-p
VTX-RCV-DETECT
TTX-IDLE-MIN
TTX-IDLE-SET-TO-IDLE
TTX-IDLE-TO-DIFF-DATA
LTX-SKEW
Receiver2
UI
VRX-DIFF-PP
TRX-EYE3
TRX-EYE-MEDIAN-to-MAX3
JITTER
RLRX-DIFF
Description
Condition
Min.
Unit Interval
Tx PLL bandwidth
Differential p-p Tx voltage
swing
Low power differential p-p Tx
voltage swing
Tx de-emphasis level ratio at
3.5 dB
Transmitter rise and fall time
—
—
399.88
1.5
400
—
400.12
22
ps
MHz
—
0.8
—
1.2
Vp-p
—
0.4
—
1.2
Vp-p
—
3
—
4
dB
—
0.125
—
—
UI
—
0.75
—
—
UI
—
—
—
0.125
UI
10
—
—
dB
50 MHz < freq < 2.5 GHz
6
—
—
dB
—
80
—
120
—
—
—
20
Ω
mV,
RMS
—
—
—
90
mA
—
0
—
1.2
V
—
—
—
20
mV
—
—
—
600
mV
—
20
—
—
ns
—
—
—
8
ns
—
—
—
8
ns
—
—
500 ps
+ 2 UI
ps
—
399.88
400
400.12
ps
—
0.175
—
1.2
Vp-p
—
0.4
—
—
UI
—
—
—
0.3
UI
—
10
—
—
dB
Transmitter Eye, including all
jitter sources
Max. time between jitter
median and max deviation
from the median
Tx Differential Return Loss,
including pkg and silicon
Tx Common Mode Return Loss,
including pkg and silicon
DC differential Impedance
Tx AC peak common mode
voltage, RMS
Transmitter short-circuit
current
Transmitter DC common-mode
voltage
Electrical Idle Output peak
voltage
Voltage change allowed during
Receiver Detect
Min. time in Electrical Idle
Max. time from EI Order Set to
valid Electrical Idle
Max. time from Electrical Idle
to valid differential output
—
Lane-to-Lane output skew
Unit Interval
Differential Rx peak-peak
voltage
Receiver eye opening time
Max time delta between
median and deviation from
median
Receiver differential Return
Loss, package plus silicon
Typ.
Max.
Unit
© 2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
82
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
Symbol
RLRX-CM
ZRX-DC
ZRX-DIFF-DC
ZRX-HIGH-IMP-DC
VRX-CM-AC-P3
Description
Receiver common mode Return
Loss, package plus silicon
Receiver DC single ended
impedance
Receiver DC differential
impedance
Receiver DC single ended
impedance when powered
down
Rx AC peak common mode
voltage
Electrical Idle Detect Threshold
Receiver –lane-lane skew
Condition
Min.
Typ.
Max.
Unit
—
6
—
—
dB
—
40
—
60
Ω
—
80
—
120
Ω
—
200K
—
—
Ω
—
150
—
mV,
peak
mVp-p
ps
VRX-IDLE-DET-DIFF-PP
—
65
—
175
LRX-SKEW
—
20
Notes:
1. Refer to PCI Express Base Specification Revision 3.0 Table 4.18 test condition and requirement for respective parameters.
2. Refer to PCI Express Base Specification Revision 3.0 Table 4.24 test condition and requirement for respective parameters.
3. Spec compliant requirement
3.24.2. PCIe (5 Gbps)
Table 3.39. PCIe (5 Gbps)
Symbol
Transmit1
UI
BWTX-PKG-PLL1
BWTX-PKG-PLL2
PKGTX-PLL1
PKGTX-PLL2
VTX-DIFF-PP
VTX-DIFF-PP-LOW
VTX-DE-RATIO-3.5dB
VTX-DE-RATIO-6dB
TMIN-PULSE
TTX-RISE-FALL
TTX-EYE
TTX-DJ
Description
Test Conditions
Min
Unit Interval
—
199.94
200
200.06
ps
—
8
—
16
MHz
—
5
—
16
MHz
—
—
—
3
dB
—
—
—
1
dB
—
0.8
—
1.2
V, p-p
—
0.4
—
1.2
V, p-p
—
3
—
4
dB
—
5.5
—
6.5
dB
—
—
0.9
0.15
—
—
—
—
UI
UI
—
0.75
—
—
UI
—
—
—
0.15
UI
Tx PLL bandwidth
corresponding to PKGTX-PLL1
Tx PLL bandwidth
corresponding to PKGTX-PLL2
Tx PLL Peaking
corresponding to PKGTX-PLL1
Tx PLL Peaking
corresponding to PKGTX-PLL2
Differential p-p Tx voltage
swing
Low power differential p-p Tx
voltage swing
Tx de-emphasis level ratio at
3.5dB
Tx de-emphasis level ratio at
6dB
Instantaneous lone pulse width
Transmitter rise and fall time
Transmitter Eye, including all
jitter sources
Tx deterministic jitter > 1.5
MHz
Typ
Max
Unit
TTX-RJ
Tx RMS jitter < 1.5 MHz
—
—
—
3
TRF-MISMATCH
Tx rise/fall time mismatch
—
—
—
0.1
ps,
RMS
UI
RLTX-DIFF
Tx Differential Return Loss,
including package and silicon
50 MHz < freq < 1.25 GHz
1.25 GHz < freq < 2.5 GHz
10
8
—
—
—
—
dB
dB
© 2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02078-1.0
83
Certus-NX Family
Data Sheet
Symbol
RLTX-CM
ZTX-DIFF-DC
VTX-CM-AC-PP
ITX-SHORT
VTX-DC-CM
VTX-IDLE-DIFF-DC
VTX-IDLE-DIFF-AC-p
VTX-RCV-DETECT
TTX-IDLE-MIN
TTX-IDLE-SET-TO-IDLE
TTX-IDLE-TO-DIFF-DATA
Description
Tx Common Mode Return Loss,
including package and silicon
DC differential Impedance
Tx AC peak common mode
voltage, peak-peak
Transmitter short-circuit
current
Transmitter DC common-mode
voltage
Electrical Idle Output DC
voltage
Electrical Idle Differential
Output peak voltage
Voltage change allowed during
Receiver Detect
Min. time in Electrical Idle
Max. time from EI Order Set to
valid Electrical Idle
Max. time from Electrical Idle
to valid differential output
Test Conditions
Min
Typ
Max
Unit
50 MHz < freq < 2.5 GHz
6
—
—
dB
—
—
—
120
Ω
—
—
—
150
mV,
p-p
—
—
—
90
mA
—
0
—
1.2
V
—
0
—
5
mV
—
—
—
20
mV
—
—
—
600
mV
—
20
—
—
ns
—
—
—
8
ns
—
—
—
8
ns
Receive2
LTX-SKEW
Lane-to-Lane output skew
—
—
—
UI
Unit Interval
Differential Rx peak-peak
voltage
—
199.94
200
500 + 4
UI
200.06
—
0.343
—
1.2
V, p-p
Receiver random jitter
tolerance (RMS)
Receiver deterministic jitter
tolerance
1.5 MHz – 100 MHz
Random noise
—
—
4.2
ps,
RMS
—
—
—
88
ps
Receiver differential Return
Loss, package plus silicon
50 MHz < freq < 1.25 GHz
1.25 GHz < freq < 2.5 GHz
10
8
—
—
—
—
dB
dB
—
6
—
—
dB
—
40
—
60
Ω
—
200k
—
—
Ω
—
—
—
150
VRX-DIFF-PP
TRX-RJ-RMS
TRX-DJ
RLRX-DIFF
RLRX-CM
ZRX-DC
ZRX-HIGH-IMP-DC
VRX-CM-AC-P3
Receiver common mode
Return Loss, package plus
silicon
Receiver DC single ended
impedance
Receiver DC single ended
impedance when powered
down
Rx AC peak common mode
voltage
Electrical Idle Detect Threshold
Receiver –lane-lane skew
ps
ps
mV,
peak
mv, pp
ns
VRX-IDLE-DET-DIFF-PP
—
65
—
1753
LRX-SKEW
—
—
—
8
Notes:
1. Refer to PCI Express Base Specification Revision 3.0 Table 4.18 test condition and requirement for respective parameters.
2. Refer to PCI Express Base Specification Revision 3.0 Table 4.24 test condition and requirement for respective parameters.
3. Spec compliant requirement
© 2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
84
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
3.25. Certus-NX Hardened SGMII Receiver Characteristics
3.25.1. SGMII Rx Specifications
Table 3.40. SGMII Rx
Symbol
fDATA
Description
SGMII Data Rate
Test Conditions
—
fREFCLK
SGMII Reference Clock Frequency (Data
Rate / 10)
—
Jitter Tolerance, Deterministic
Periodic jitter
< 300 kHz
JTOL_Dj
JTOL_Tj
Jitter Tolerance, Total
Δf/f
Data Rate and Reference Clock Accuracy
Periodic jitter
< 300 kHz
—
Min
—
Typ
1250
Max
—
Unit
MHz
—
125
—
MHz
—
0.1*
UI
—
0.3*
UI
—
300
ppm
–300
*Note:
JTOT can meet the following jitter mask specification: 0 to 3.5 kHz: 10 UI; 3.5 to 700 kHz: log-log slope 10 UI to 0.05 UI; above
700 kHz: 0.05 UI.
3.26. Certus-NX sysCONFIG Port Timing Specifications
Table 3.41. Certus-NX sysCONFIG Port Timing Specifications
Symbol
Parameter
Device
Min
Typ.
Max
Unit
Master SPI POR / REFRESH Timing
REFRESH command executed, to the rising
edge of INITN (bulk-erase off)
tICFG
Time from rising edge of INITN to the valid
Master MCLK
Default MCLK frequency (Before MCLK
fMCLK_DEF
frequency selection in bitstream)
Time during POR, from VCC, VCCAUX, VCCIO0,
tICFG_POR
or VCCIO1 (whichever is the last) pass POR trip
to the rising
edge if INITN
Slave SPI/I2C/I3C voltage,
POR / REFRESH
Timing
tVMC
Time during POR, from VCC, VCCAUX, VCCIO0 or
VCCIO1 (whichever is the last) pass POR trip
tMSPI_INH
voltage, or REFRESH command executed, to
pull PROGRAMN LOW to prevent entering
MSPI mode
Minimum time driving PROGRAMN HIGH after
tACT_PROGRAMN_H
last activation clock
Minimum time to start driving CCLK (SSPI) after
tCONFIG_CCLK
PROGRAMN HIGH
Minimum time to start driving SCL (I2C/I3C)
tCONFIG_SCL
after PROGRAMN HIGH
PROGRAMN Configuration Timing
—
—
—
30
µs
—
—
—
5
µs
—
—
3.5
—
MHz
—
—
—
5
ms
—
—
—
1
µs
—
—
ns
—
—
ns
—
—
ns
—
—
—
50
50
50
tPROGRAMN
PROGRAMN LOW pulse accepted
—
50
—
—
ns
tPROGRAMN_RJ
PROGRAMN LOW pulse rejected
—
—
—
25
ns
tINIT_LOW
PROGRAMN LOW to INITN LOW
—
—
—
100
ns
LIFCL-40
—
30
—
µs
tINIT_HIGH
PROGRAMN LOW to INITN HIGH (bulk-erase
off)
LIFCL-17
—
30
—
µs
tDONE_LOW
PROGRAMN LOW to DONE LOW
—
—
—
55
µs
tDONE_HIGH
PROGRAMN HIGH to DONE HIGH
—
—
2
s
© 2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02078-1.0
85
Certus-NX Family
Data Sheet
Symbol
Parameter
Device
tIODISS
PROGRAMN LOW to I/O Disabled
—
fMCLK*
Max selected MCLK output frequency
fMCLK_DC
MCLK output clock duty cycle
tMCLKH
tMCLKL
Min
Typ.
Max
Unit
—
—
125
ns
—
—
150
165
MHz
—
40
—
60
%
MCLK output clock pulse width HIGH
—
3
—
—
ns
MCLK output clock pulse width LOW
—
3
—
—
ns
tSU_MSI
MSI to MCLK setup time
—
3
—
—
ns
tHD_MSI
MSI to MCLK hold time
—
0.5
—
—
ns
tCO_MSO
MCLK to MSO delay
—
—
—
12
ns
fCCLK
CCLK input clock frequency
—
—
—
135
MHz
tCCLKH
CCLK input clock pulse width HIGH
—
3.5
—
—
ns
tCCLKL
CCLK input clock pulse width LOW
—
3.5
—
—
ns
tVMC_SLAVE
Time from rising edge of INITN to Slave CCLK
driven
—
50
—
—
ns
tVMC_MASTER
CCLK input clock duty cycle
—
40
—
60
%
tSU_SSI
SSI to CCLK setup time
—
3.2
—
—
ns
tHD_SSI
SSI to CCLK hold time
—
1.9
—
—
ns
tCO_SSO
CCLK falling edge to valid SSO output
—
—
—
16
ns
tEN_SSO
CCLK falling edge to SSO output enabled
—
—
—
16
ns
tDIS_SSO
CCLK falling edge to SSO output disabled
—
—
—
16
ns
tHIGH_SCSN
SCSN HIGH time
—
74
—
—
ns
tSU_SCSN
SCSN to CCLK setup time
—
3.5
—
—
ns
tHD_SCSN
SCSN to CCLK hold time
—
1.6
—
—
ns
fSCL_I2C
SCL input clock frequency for I2C
—
—
—
1
MHz
fSCL_I3C
SCL input clock frequency for I3C
—
—
—
12
MHz
tSCLH_I2C
SCL input clock pulse width HIGH for
I 2C
—
400
—
—
ns
tSCLL_I2C
SCL input clock pulse width LOW for I2C
—
400
—
—
ns
Master SPI
Slave SPI
I2C/I3C
I 2C
tSU_SDA_I2C
SDA to SCL setup time for
—
250
—
—
ns
tHD_SDA_I2C
SDA to SCL hold time for I2C
—
50
—
—
ns
tSU_SDA_I3C
SDA to SCL setup time for I3C
—
30
—
—
ns
tHD_SDA_I3C
SDA to SCL hold time for I3C
—
30
—
—
ns
tCO_SDA
SCL falling edge to valid SDA output
—
—
—
200
ns
tEN_SDA
SCL falling edge to SDA output enabled
—
—
—
200
ns
tDIS_SDA
SCL falling edge to SDA output disabled
—
—
—
200
ns
Last configuration clock cycle to DONE going
HIGH
—
—
—
60
µs
LIFCL-40
—
6.245
M
cycles
LIFCL-17
—
2.321
Wake-Up Timing
tDONE_HIGH
tFIO_EN
User I/O enabled in Fast I/O Mode
tIOEN
Config clock to user I/O enabled
—
130
—
—
M
cycles
ns
tMCLKZ
Master MCLK to Hi-Z
—
—
—
2.5
µs
*Note:
fMCLK has a dependency on HFOSC and is 1/3 of fCLKHF.
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86
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
tICFG
REFRESH Command
VCC/VCCAUX/
VCCIO0/VCCIO1
tICFG_POR
INITN
DONE
PROGRAMN
fMCLK_DEF
tVMC
MCLK
MSI
Figure 3.14. Master SPI POR/REFRESH Timing
VCC/VCCAUX/
VCCIO0/VCCIO1
tICFG_POR
tICFG
REFRESH Command
INITN
DONE
tMSPI_INH
Slave Activation
PROGRAMN
tACT_CCLK
fCCLK
tACT_SCL
fSCL
tACT_CRESETB_N
tCONFIG_CCLK
CCLK
SSI
tACT_CRESETB_N
tCONFIG_SCL
SCL
SDA
Figure 3.15. Slave SPI/I2C/I3C POR/REFRESH Timing
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FPGA-DS-02078-1.0
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Certus-NX Family
Data Sheet
Figure 3.16. Master SPI PROGRAMN Timing
Figure 3.17. Slave SPI/I2C/I3C PROGRAMN Timing
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88
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
Figure 3.18. Master SPI Configuration Timing
fCCLK
tCCLKH
CCLK
tCCLKL
tSU_MOSI
tHD_MOSI
tSU_SCSN
tHD_SCSN
SSI
SCSN
tHIGH_SCSN
tCO_MISO
SSO
tEN_MISO
tDIS_MISO
SSO
Figure 3.19. Slave SPI Configuration Timing
Figure 3.20. I2C/I3C Configuration Timing
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FPGA-DS-02078-1.0
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Certus-NX Family
Data Sheet
CRESET_B
INITN
tDONE_HI GH
Device Wake-Up
DONE
CONFIG
Starts
tMWC
fMCLK_def
fMCLK
tMCLKZ
MCLK
tFIO_EN
USER I/O
(FAST I/Os)
tIOEN
tIOEN
USER I/O
Figure 3.21. Master SPI Wake-Up Timing
Figure 3.22. Slave SPI/I2C/I3C Wake-Up Timing
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All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
90
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
3.27. JTAG Port Timing Specifications
Table 3.42. JTAG Port Timing Specifications
Symbol
Parameter
Min
Typ.
Max
Units
fMAX
tBTCPH
tBTCPL
tBTS
tBTH
tBTRF
tBTCO
tBTCODIS
tBTCOEN
tBTCRS
tBTCRH
TCK clock frequency
TCK clock pulse width high
TCK clock pulse width low
TCK TAP setup time
TCK TAP hold time
TAP controller TDO rise/fall time*
TAP controller falling edge of clock to valid output
TAP controller falling edge of clock to valid disable
TAP controller falling edge of clock to valid enable
BSCAN test capture register setup time
BSCAN test capture register hold time
—
20
20
5
5
100
—
—
—
8
25
—
—
—
—
—
—
—
—
—
—
—
25
—
—
—
—
—
14
14
14
—
—
MHz
ns
ns
ns
ns
mV/ns
ns
ns
ns
ns
ns
—
—
—
—
—
—
25
25
25
ns
ns
ns
tBUTCO
BSCAN test update register, falling edge of clock to valid output
tBTUODIS
BSCAN test update register, falling edge of clock to valid disable
tBTUPOEN
BSCAN test update register, falling edge of clock to valid enable
*Note: Based on default IO setting of slow slew rate.
TMS
TDI
tBTS
tBTCPH
tBTH
tBTCP
tBTCPL
TCK
tBTCO
tBTCOEN
TDO
V a lid D a ta
tBTCRS
Data to be
Captured
from I/O
V a lid D a ta
tBTCRH
Data Captured
tBTUPOEN
Data to be
driven out
to I/O
tBTCODIS
tBUTCO
V a lid D a ta
tBTUODIS
V a lid D a ta
Figure 3.23. JTAG Port Timing Waveforms
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FPGA-DS-02078-1.0
91
Certus-NX Family
Data Sheet
3.28. Switching Test Conditions
Figure 3.24 shows the output test load that is used for AC testing. The specific values for resistance, capacitance,
voltage, and other test conditions are listed in Table 3.43.
VT
R1
Test Point
DUT
R2
CL*
*CL Includes Test Fixture and Probe Capacitance
Figure 3.24. Output Test Load, LVTTL and LVCMOS Standards
Table 3.43. Test Fixture Required Components, Non-Terminated Interfaces
Test Condition
LVTTL and other LVCMOS settings (L ≥ H, H ≥ L)
LVCMOS 2.5 I/O (Z ≥ H)
LVCMOS 2.5 I/O (Z ≥ L)
LVCMOS 2.5 I/O (H ≥ Z)
R1
R2
1 MΩ
1 MΩ
100
CL
0 pF
0 pF
0 pF
0 pF
Timing Ref.
LVCMOS 3.3 = 1.5 V
LVCMOS 2.5 = VCCIO/2
LVCMOS 1.8 = VCCIO/2
LVCMOS 1.5 = VCCIO/2
VT
—
—
—
—
LVCMOS 1.2 = VCCIO/2
VCCIO/2
VCCIO/2
VOH – 0.10
—
—
VCCIO
—
VOL + 0.10
VCCIO
LVCMOS 2.5 I/O (L ≥ Z)
100
0 pF
Note: Output test conditions for all other interfaces are determined by the respective standards.
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All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
92
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
4. DC and Switching Characteristics for Automotive
All specifications in this chapter are characterized within recommended operating conditions unless otherwise
specified.
4.1.
Absolute Maximum Ratings
Table 4.1. Absolute Maximum Ratings
Symbol
VCC, VCCECLK
VCCAUX, VCCAUXA,
VCCAUXH3, VCCAUXH4,
VCCAUXH5
VCCIO0, 1, 2, 6, 7
VCCIO3, 4, 5
VCCPLL_DPHY0, 1
VCCPLLSD0
VCCA_DPHY0, 1
VCC_DPHY0, 1
VCCSD0
VCCADC18
VCCAUXSD
—
—
Parameter
Supply Voltage
Supply Voltage
Min
–0.5
–0.5
Max
1.10
1.98
Unit
V
V
I/O Supply Voltage
I/O Supply Voltage
Hardened D-PHY PLL Supply Voltage
SerDes Block PLL Supply Voltage
Analog Supply Voltage for Hardened D-PHY
Digital Supply Voltage for Hardened D-PHY
SerDes Supply Voltage
ADC Block 1.8 V Supply Voltage
SerDes and AUX Supply Voltage
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
3.63
1.98
1.10
1.98
1.98
1.10
1.10
1.98
1.98
3.63
V
V
V
V
V
V
V
V
V
V
–0.5
1.98
V
Input or I/O Voltage Applied, Bank 0, Bank
1,Bank 2, Bank 6, Bank 7
Input or I/O Voltage Applied, Bank 3, Bank 4,
Bank 5
Voltage Applied on SerDes Pins
Storage Temperature (Ambient)
Junction Temperature
—
–0.5
1.98
V
TA
–65
150
°C
TJ
—
+125
°C
Notes:
1. Stress above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. Functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is
not implied.
2. Compliance with the Lattice Thermal Management document is required.
3. All voltages referenced to GND.
4. All VCCAUX should be connected on PCB.
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FPGA-DS-02078-1.0
93
Certus-NX Family
Data Sheet
4.2.
Recommended Operating Conditions1, 2, 3
Table 4.2. Recommended Operating Conditions
Symbol
Parameter
Conditions
Min
Typ.
Max
Unit
VCC, VCCECLK
Core Supply Voltage
VCC = 1.0
0.95
1.00
1.05
V
VCCAUX
Auxiliary Supply Voltage
1.746
1.80
1.89
V
VCCAUXH3/4/5
Auxiliary Supply Voltage
Auxiliary Supply Voltage for
core logic
1.746
1.80
1.89
V
1.746
1.80
1.89
V
3.135
3.30
3.465
V
2.375
2.50
2.625
V
1.71
1.425
1.80
1.50
1.89
1.575
V
V
1.2825
1.35
1.4175
V
1.14
1.20
1.26
V
0.95
1.00
1.05
V
—
1.71
1.80
1.89
V
—
0.95
1.00
1.05
V
—
1.71
1.80
1.89
V
—
1.71
1.80
1.89
V
—
–40
—
125
°C
VCCAUXA
VCCIO
I/O Driver Supply Voltage
ADC External Power Supplies
VCCADC18
ADC 1.8 V Power Supply
SerDes Block External Power Supplies
Supply Voltage for SerDes
VCCSD0
Block and SerDes I/O
SerDes Block PLL Supply
Voltage
SerDes Block Auxiliary
VCCAUXSD
Supply Voltage
Operating Temperature
VCCPLLSD0
tJAUTO
Junction Temperature,
Automotive Operation
Bank 0, Bank 1, Bank 2, Bank 6,
Bank 7
Bank 3, Bank 4, Bank 5
—
VCCIO = 3.3 V, Bank 0, Bank 1,
Bank 2, Bank 6, Bank 7
VCCIO = 2.5 V, Bank 0, Bank 1,
Bank 2, Bank 6, Bank 7
VCCIO = 1.8 V, All Banks
VCCIO = 1.5 V, All Banks4
VCCIO = 1.35 V, All Banks (For
DDR3L Only)
VCCIO = 1.2 V, All Banks4
VCCIO = 1.0 V, Bank 3, Bank 4,
Bank 5
Notes:
1. For correct operation, all supplies must be held in their valid operation voltage range.
2. All supplies with same voltage should be from the same voltage source. Proper isolation filters are needed to properly isolate
noise from each other.
3. Common supply rails must be tied together except SerDes.
4. MSPI (Bank 0) and JTAG, SSPI, I2C, and I3C (Bank 1) ports are supported for VCCIO = 1.8 V to 3.3 V.
5. Data in this section is in preliminary state, subject to change.
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All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
94
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
4.3.
Power Supply Ramp Rates
Table 4.3. Power Supply Ramp Rates
Symbol
Parameter
tRAMP
Power Supply ramp rates for all supplies
1
Min
Typ
Max
Unit
0.1
—
50
V/ms
Notes:
1. Assumes monotonic ramp rates.
2. All supplies need to be in the operating range as defined in Recommended Operating Conditions, when the device has
completed configuration and entering into User Mode. Supplies that are not in the operating range needs to be adjusted to
faster ramp rate, or you have to delay configuration or wake up.
4.4.
Power up Sequence
Power-On-Reset (POR) puts the Certus-NX device into a reset state. There is no power up sequence required for the
Certus-NX device.
Table 4.4. Power-On Reset
Symbol
Parameter
VPORUP
VPORDN
4.5.
Min
Typ
Max
Unit
Power-On-Reset ramp-up trip
point (Monitoring VCC, VCCAUX,
VCCI00, and VCCI01)
VCC
0.72
—
0.84
V
VCCAUX
1.30
—
1.71
V
VCCIO0,VCCI01
0.87
—
1.07
V
Power-On-Reset ramp-up trip
point (Monitoring VCC and VCCAUX)
VCC
0.48
—
0.85
V
VCCAUX
1.36
—
1.57
V
On-Chip Programmable Termination
The Certus-NX devices support a variety of programmable on-chip terminations options, including:
Dynamically switchable Single-Ended Termination with programmable resistor values of 40 Ω, 50 Ω, 60 Ω, or 75 Ω.
Common mode termination of 100 Ω for differential inputs.
Zo = 50
V CCI O
Zo = 40 , 50 , 60
to VCCIO /2
, or 75
TERM
control
Zo
Zo
Zo
+
-
VREF
OFF-chip
+
2Zo Zo
OFF-chip
ON-chip
Parallel Single-Ended Input
ON-chip
Differential Input
Figure 4.1. On-Chip Termination
See Table 4.5 for termination options for input modes.
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FPGA-DS-02078-1.0
95
Certus-NX Family
Data Sheet
Table 4.5. On-Chip Termination Options for Input Modes
IO_TYPE
subLVDS
SLVS
Terminate to VCCIO/2*
OFF
OFF
Differential Termination Resistor*
100, OFF
100, OFF
HSTL15D_I
100, OFF
OFF
SSTL15D_I
100, OFF
OFF
SSTL135D_I
100, OFF
OFF
HSUL12D
100, OFF
OFF
LVCMOS15H
OFF
OFF
LVCMOS12H
OFF
OFF
LVCMOS10H
OFF
OFF
LVCMOS12H
OFF
OFF
LVCMOS10H
OFF
OFF
LVCMOS18H
OFF
OFF, 40, 50, 60, 75
HSTL15_I
OFF
50
SSTL15_I
OFF
OFF, 40, 50, 60, 75
SSTL135_I
OFF
OFF, 40, 50, 60, 75
HSUL12
OFF
OFF, 40, 50, 60, 75
*Notes:
TERMINATE to VCCIO/2 (Single-Ended) and DIFFRENTIAL TERMINATION RESISTOR when turned on can only have one setting per
bank. Only left and right banks have this feature.
Use of TERMINATE to VCCIO/2 and DIFFRENTIAL TERMINATION RESISTOR are mutually exclusive in an I/O bank. On-chip
termination tolerance –10%/+60%.
Refer to Certus-NX High-Speed I/O Interface (FPGA-TN-02216) for on-chip termination usage and value ranges.
4.6.
Hot Socketing Specifications
Table 4.6. Hot Socketing Specifications for GPIO
Symbol
IDK
Parameter
Input or I/O Leakage Current for
Wide Range I/O (excluding
MCLK/MCSN/MOSI/INITN/DONE)
Condition
0 < Vin < Vih(max)
0 < Vcc < Vcc(max)
0 < Vccio < Vccio(max)
0 < Vccaux < Vccaux(max)
Min
-1.5
Typ
—
Max
1.5
Unit
mA
Notes:
IDK is additive to IPU, IPD, or IBH.
Hot socket specification defines when the hot socketed device's junction temperature is at 85 oC or below. When the hot
socketed device's junction temperature is above 85 oC, the IDK current can exceed the above spec.
Going beyond the hot socketing ranges specified here will cause exponentially higher Leakage currents and potential reliability
issues. A total of 64mA per 8 I/O should not be exceeded.
4.7.
ESD Performance
Refer to the Certus-NX Product Family Qualification Summary for complete qualification data, including ESD
performance.
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96
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
4.8.
DC Electrical Characteristics
Table 4.7. DC Electrical Characteristics – Wide Range
Symbol
IIL, IIH1
IIH2
IPU
IPD
Parameter
Input or I/O Leakage current
(Commercial/Industrial)
Input or I/O Leakage current
I/O Weak Pull-up Resistor
Current
I/O Weak Pull-down Resistor
Current
Bus Hold Low Sustaining Current
Bus Hold High Sustaining Current
Bus hold low Overdrive Current
Bus hold high Overdrive Current
Bus Hold Trip Points
Condition
Min
Typ
Max
Unit
0 ≤ VIN ≤ VCCIO
—
—
10
µA
VCCIO ≤ VIN ≤ VIH (max)
—
—
100
µA
0 ≤ VIN ≤ 0.7 × VCCIO
–30
—
–150
µA
VIL (max) ≤ VIN ≤ VCCIO
30
—
150
µA
IBHLS
VIN = VIL (max)
30
—
µA
IBHHS
VIN = 0.7 × VCCIO
–30
—
µA
IBHLO
0 ≤ VIN ≤ VCCIO
—
—
150
µA
IBHHO
0 ≤ VIN ≤ VCCIO
—
—
–150
µA
VBHT
—
VIL (max)
—
VIH (min)
V
Notes:
1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output tri-stated. Bus
Maintenance circuits are disabled.
2. The input leakage current IIH is the worst case input leakage per GPIO when the pad signal is high and also higher than the bank
VCCIO. This is considered a mixed mode input.
Table 4.8. DC Electrical Characteristics – High Speed
Symbol
IIL, IIH1
Parameter
Input or I/O Leakage
Condition
0 ≤ VIN ≤ VCCIO
Min
—
IPU
I/O Weak Pull-up Resistor
Current
0 ≤ VIN ≤ 0.7 × VCCIO
–30
VIL (max) ≤ VIN ≤ VCCIO
30
VIN = VIL (max)
VIN = 0.7 × VCCIO
0 ≤ VIN ≤ VCCIO
0 ≤ VIN ≤ VCCIO
30
–30
—
—
I/O Weak Pull-down Resistor
Current
Bus Hold Low Sustaining Current
Bus Hold High Sustaining Current
Bus hold low Overdrive Current
Bus hold high Overdrive Current
IPD
IBHLS
IBHHS
IBHLO
IBHHO
Typ
—
—
—
—
—
—
—
Max
10
Unit
µA
–150
µA
150
µA
—
—
150
–150
µA
µA
µA
µA
VIL
—
VIH (min)
V
(max)
Note: Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output tri-stated. Bus
Maintenance circuits are disabled.
VBHT
Bus Hold Trip Points
—
Table 4.9. Capacitors – Wide Range
Symbol
Parameter
Condition
C1 *
I/O Capacitance*
C2 *
Dedicated Input Capacitance*
*Note:
Min
Typ
Max
Unit
VCCIO = 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V,
VCC = typ., VIO = 0 to VCCIO + 0.2V
—
6
—
pf
VCCIO = 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V,
VCC = typ., VIO = 0 to VCCIO + 0.2V
—
6
—
pf
TA 25 oC, f = 1.0 MHz.
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FPGA-DS-02078-1.0
97
Certus-NX Family
Data Sheet
Table 4.10. Capacitors – High Performance
Symbol
Parameter
Condition
Min
Typ
Max
Unit
C1 *
I/O Capacitance*
VCCIO = 1.8 V, 1.5 V, 1.2 V, VCC = typ.,
VIO = 0 to VCCIO + 0.2V
—
6
—
pf
C2 *
Dedicated Input Capacitance*
VCCIO = 1.8 V, 1.5 V, 1.2 V, VCC = typ.,
VIO = 0 to VCCIO + 0.2V
—
6
—
pf
C3 *
D-PHY I/O Capacitance
VCCA_D-PHY = 1.8 V, VCC = typ., VIO = 0
to VCCA_D-PHY + 0.2V
—
5
—
pf
C4 *
SerDes I/O Capacitance
VCCSD0 = 1.0 V, VCC = typ., VIO = 0 to
VCCSD0 + 0.2 V
—
5
—
pf
*Note:
TA 25 oC, f = 1.0 MHz.
Table 4.11. Single Ended Input Hysteresis – Wide Range
IO_TYPE
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
LVCMOS10
VCCIO
3.3 V
3.3 V
2.5 V
1.8 V
1.5 V
1.2 V
1.2 V
TYP Hysteresis
250 mV
200 mV
250 mV
180 mV
50 mV
0
0
VCCIO
1.8 V
TYP Hysteresis
180 mV
1.8 V
1.5 V
1.2 V
1.0 V
50 mV
150 mV
0
0
Table 4.12. Single Ended Input Hysteresis – High Performance
IO_TYPE
LVCMOS18H
LVCMOS15H
LVCMOS12H
LVCMOS10H
4.9.
Supply Currents
For estimating and calculating current, use Power Calculator in Lattice Design software.
This operating and peak current is design dependent, and can be calculated in Lattice Design Software. Some blocks
can be placed into low current standby modes. Refer to Power Management and Calculation for Certus-NX (FPGA-TN02214).
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98
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
4.10. sysI/O Recommended Operating Conditions
Table 4.13. sysI/O Recommended Operating Conditions
Standard
Single-Ended
LVCMOS33
LVTTL33
LVCMOS25¹, ²
LVCMOS18¹, ²
LVCMOS18H
LVCMOS15¹, ²
LVCMOS15H¹
LVCMOS12¹, ²
LVCMOS12H¹
LVCMOS10¹
LVCMOS10H¹
LVCMOS10R¹
SSTL135_I, SSTL135_II3
SSTL15_I, SSTL15_II3
HSTL15_I3
HSUL123
Differential
LVDS
LVDSE5
subLVDS
subLVDSE
5
Support Banks
VCCIO (Input)
VCCIO (Output)
Typ.
Typ.
0, 1, 2, 6, 7
0, 1, 2, 6, 7
0, 1, 2, 6, 7
0, 1, 2, 6, 7
3, 4, 5
0, 1, 2, 6, 7
3, 4, 5
0, 1, 2, 6, 7
3, 4, 5
3.3
3.3
2.5, 3.3
1.2, 1.5, 1.8, 2.5, 3.3
1.8
1.2, 1.5, 1.8, 2.5, 3.3
1.5, 1.8
1.2, 1.5, 1.8, 2.5, 3.3
1.2, 1.356, 1.5, 1.8
3.3
3.3
2.5
1.8
1.8
1.5
1.5
1.2
1.2
0, 1, 2, 6, 7
3, 4, 5
3, 4, 5
3, 4, 5
3, 4, 5
3, 4, 5
3, 4, 5
1.2, 1.5, 1.8, 2.5, 3.3
1.0, 1.2, 1.356, 1.5, 1.8
1.0, 1.2, 1.356, 1.5, 1.8
1.356
1.57
1.57
1.2
—
1.0
—
1.35
1.57
1.57
1.2
3, 4, 5
0, 1, 2, 6, 7
1.8
—
1.8
2.5
3, 4, 5
1.8
—
—
0, 1, 2, 6, 7
1.8
—
3, 4, 5
1.8
subLVDSEH5
SLVS
3, 4, 5
1.0, 1.2, 1.356, 1.5, 1.84
1.2, 1.356, 1.5, 1.8 4
LVCMOS33D5
0, 1, 2, 6, 7
—
3.3
LVTTL33D5
0, 1, 2, 6, 7
—
3.3
5
LVCMOS25D
0, 1, 2, 6, 7
—
2.5
SSTL135D_I, SSTL135D_II5
3, 4, 5
—
1.356
SSTL15D_I, SSTL15D_II5
3, 4, 5
—
1.5
5
HSTL15D_I
3, 4, 5
—
1.5
HSUL12D5
3, 4, 5
—
1.2
Notes:
1. Single-ended input can mix into I/O Banks with VCCIO different from the standard requires due to some of these input standards
use internal supply voltage source (VCC, VCCAUX) to power the input buffer, which makes them to be independent of VCCIO
voltage. For more details, please refer to Certus-NX High-Speed I/O Interface (FPGA-TN-02216). The following is a brief
guideline to follow:
a. Weak pull-up on the I/O must be set to OFF.
b. Bank 3, Bank 4, and Bank 5 I/O can only mix into banks with VCCIO higher than the pin standard, due to clamping diode on
the pin in these banks. Bank 0, Bank 1, Bank 2, Bank 6, and Bank 7 does not have this restriction.
c. LVCMOS25 uses VCCIO supply on input buffer in Bank 0, Bank 1, Bank 2, Bank 6, and Bank 7. It can be supported with VCCIO =
3.3 V to meet the VIH and VIL requirements, but there is additional current drawn on VCCIO. Hysteresis has to be disabled
when using 3.3 V supply voltage.
d. LVCMOS15 uses VCCIO supply on input buffer in Bank 3, Bank 4, and Bank 5. It can be supported with VCCIO = 1.8 V to meet
the VIH and VIL requirements, but there is additional current drawn on VCCIO.
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FPGA-DS-02078-1.0
99
Certus-NX Family
Data Sheet
2.
3.
4.
5.
6.
7.
Single-ended LVCMOS inputs can mixed into I/O Banks with different VCCIO, providing weak pull-up is not used.
For additional information on Mixed I/O in Bank VCCIO, refer to Certus-NX High-Speed I/O Interface (FPGA-TN-02216).
These inputs use differential input comparator in Bank 3, Bank 4, and Bank 5. The differential input comparator uses VCCAUXH
power supply. These inputs require the VREF pin to provide the reference voltage in the Bank. Refer to Certus-NX High-Speed I/O
Interface (FPGA-TN-02216) for details.
All differential inputs use differential input comparator in Bank 3, Bank 4, and Bank 5. The differential input comparator uses
VCCAUXH power supply. There is no differential input signaling supported in Bank 0, Bank 1, Bank 2, Bank 6, and Bank 7.
These outputs are emulating differential output pair with single-ended output drivers with true and complement outputs
driving on each of the corresponding true and complement output pair pins. The common mode voltage, VCM, is ½ * VCCIO. Refer
Certus-NX High-Speed I/O Interface (FPGA-TN-02216) for details.
VCCIO = 1.35 V is only supported in Bank 3, Bank 4, and Bank 5, for use with DDR3L interface in the bank. These Input and Output
standards can fit into the same bank with the VCCIO = 1.35 V.
LVCMOS15 input uses VCCIO supply voltage. If VCCIO is 1.8 V, the DC levels for LVCMOS15 are still met, but there could be increase
in input buffer current.
4.11. sysI/O Single-Ended DC Electrical Characteristics3
Table 4.14. sysI/O DC Electrical Characteristics – Wide Range I/O
Input/Output
Standard
LVTTL33
LVCMOS33
LVCMOS25
Min (V)
—
—
VIL¹
Max (V)
VIH¹
Min (V)
Max (V)
VOL Max
(V)
VOH Min²
(V)
IOL(mA)
IOH(mA)
0.8
2.0
3.465
0.4
VCCIO – 0.4
2, 4, 8,
12, 16
0.7
1.7
2.625
0.4
VCCIO – 0.45
2, 4, 8, 10
-2, -4, -8,
-12, -16
-2, -4, -8,
-10
1.9
0.4
VCCIO – 0.45
2, 4, 8
0.4
VCCIO – 0.4
2, 4
-2, -4
2, 4
-2, -4, -8,
-12
LVCMOS18
—
0.35 × VCCIO
0.65 × VCCIO
LVCMOS15
—
0.35 × VCCIO
0.65 × VCCIO
LVCMOS12
LVCMOS10
—
—
1.575
0.35 × VCCIO
0.65 × VCCIO
1.26
0.3 × VCCIO
0.7 × VCCIO
1.05
0.4
VCCIO – 0.4
-2, -4, -8
No O/P Support
Notes:
1. VCCIO for input level refers to the supply rail level associated with a given input standard or the upstream driver VCCIO rail
levels.
2. VCCIO for the output levels refer to the VCCIO of the Certus-NX device.
3. For electro-migration, the combined DC current sourced or sinked by I/O pads between two consecutive VCCIO or GND pad
connections, or between the last VCCIO or GND in an I/O bank and the end of an I/O bank, as shown in the Logic Signal
Connections table (also shown as I/O grouping) shall not exceed a maximum of n × 8 mA. n is the number of I/O pads between
the two consecutive bank VCCIO or GND connections or between the last VCCIO and GND in a bank and the end of a bank. I/O
Grouping can be found in the Data Sheet Pin Summary Tables, which can also be generated from the Lattice Radiant software.
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100
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
Table 4.15. sysI/O DC Electrical Characteristics – High Performance I/O3
VIL¹
Min (V)
Max (V)
Input/Output
Standard
VIH¹
Min (V)
Max (V)
VCCIO +
0.3
VCCIO +
0.3
VOL Max
(V)
VOH Min²
(V)
IOL (mA)
IOH (mA)
0.4
VCCIO – 0.45
2, 4, 8, 12
-2, -4, -8,
-12
0.4
VCCIO – 0.4
2, 4, 8
-2, -4, -8
LVCMOS18H
0.35 *
VCCIO
0.65 * VCCIO
LVCMOS15H
0.35 *
VCCIO
0.65 * VCCIO
LVCMOS12H
0.35 *
VCCIO
0.65 * VCCIO
1.26
0.4
VCCIO – 0.4
2, 4, 8
-2, -4, -8
LVCMOS10H
0.3 * VCCIO
0.7 * VCCIO
1.05
0.27 *
VCCIO
0.75 * VCCIO
2, 4
-2, -4
SSTL15_I
VREF – 0.10
VREF + 0.1
1.575
0.30
VCCIO – 0.30
7.5
–7.5
SSTL15_II
VREF – 0.10
VREF + 0.1
1.575
0.30
VCCIO – 0.30
8.8
–8.8
HSTL15_I
VREF – 0.10
VREF + 0.1
1.575
0.40
VCCIO – 0.40
8
–8
SSTL135_I
VREF – 0.09
VREF + 0.09
1.418
0.27
VCCIO – 0.27
6.75
–6.75
SSTL135_II
VREF – 0.09
VREF + 0.09
1.418
0.27
VCCIO – 0.27
8
–8
LVCMOS10R
VREF – 0.10
VREF + 0.10
1.05
—
—
—
—
HSUL12
VREF – 0.10
VREF + 0.10
1.26
0.3
VCCIO – 0.3
8.0, 7.5,
6.25, 5
-8.0, -7.5,
-6.25, -5
Notes:
1. VCCIO for input level refers to the supply rail level associated with a given input standard or the upstream driver VCCIO rail
levels.
2. VCCIO for the output levels refer to the VCCIO of the Certus-NX device.
3. For electro-migration, the combined DC current sourced or sinked by I/O pads between two consecutive VCCIO or GND pad
connections, or between the last VCCIO or GND in an I/O bank and the end of an I/O bank, as shown in the Logic Signal
Connections table (also shown as I/O grouping) shall not exceed a maximum of n × 8 mA. n is the number of I/O pads between
the two consecutive bank VCCIO or GND connections or between the last VCCIO and GND in a bank and the end of a bank. I/O
Grouping can be found in the Data Sheet Pin Summary Tables, which can also be generated from the Lattice Radiant software.
Table 4.16. I/O Resistance Characteristics
Parameter
50RS
RDIFF
SE Input
Termination
Description
Output Drive Resistance when 50RS
Drive Strength Selected
Input Differential Termination
Resistance
Test Conditions
Input Single Ended Termination
Resistance
Bank 3, Bank 4, and Bank 5 for I/O
selected to be Single Ended
VCCIO = 1.8 V, 2.5 V, or 3.3 V
Min
Typ
Max
Unit
—
50
—
Ω
Bank 3, Bank 4, and Bank 5 for I/O
selected to be differential
100
36
46
56
71
40
50
60
75
Ω
64
80
96
120
Ω
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FPGA-DS-02078-1.0
101
Certus-NX Family
Data Sheet
4.12. sysI/O Differential DC Electrical Characteristics
4.12.1. LVDS
LVDS input buffer on Certus-NX is operating with VCCAUX = 1.8 V and independent of Bank VCCIO voltage. LVDS output
buffer is powered by the Bank VCCIO at 1.8 V.
LVDS can only be supported in Bank 3, Bank 4, and Bank 5. LVDS25 output can be emulated with LVDS25E in Bank 0,
Bank 1, Bank 2, Bank 6, and Bank 7. This is described in LVDS25E (Output Only) section.
Table 4.17. LVDS DC Electrical Characteristics1
Parameter
VINP, VINM
VICM
VTHD
IIN
VOH
VOL
VOD
Test Conditions
—
Half the sum of the two Inputs
Difference between the two Inputs
Power On or Power Off
RT = 100 Ω
RT = 100 Ω
(VOP - VOM), RT = 100 Ω
VOCM
Description
Input Voltage
Input Common Mode Voltage
Differential Input Threshold
Input Current
Output High Voltage for VOP or VOM
Output Low Voltage for VOP or VOM
Output Voltage Differential
Change in VOD Between High and
Low
Output Common Mode Voltage
VOCM
Change in VOCM, VOCM(MAX) - VOCM(MIN)
—
ISAB
Output Short Circuit Current
VOD
—
(VOP + VOM)/2, RT = 100 Ω
VOD = 0 V Driver outputs shorted to
each other
—
Min
0
0.05
±100
—
—
0.9
250
Typ
—
—
—
—
1.425
1.075
350
Max
1.60
1.55 2
—
±10
1.60
—
450
Unit
V
V
mV
µA
V
V
mV
—
—
50
mV
1.125
1.25
1.375
V
—
—
50
mV
—
—
12
mA
Change in VOS between H and L
—
—
50
mV
VOS
Notes:
1. LVDS input or output are supported in Bank 3, Bank 4, and Bank 5. LVDS input uses VCCAUX on the differential input
comparator, and can be located in any VCCIO voltage bank. LVDS output uses VCCIO on the differential output driver, and can
only be located in bank with VCCIO = 1.8 V.
2. VICM is depending on VID, input differential voltage, so the voltage on pin cannot exceed VINP/INN(min/max) requirements. VICM(min) =
VINP/INN(min) + ½ VID, VICM(max) = VINP/INN(max) – ½ VID. Values in the table is based on minimum VID of +/- 100 mV.
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102
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
4.12.2. LVDS25E (Output Only)
Three sides of the Certus-NX devices, Top, Left and Right, support LVDS25 outputs with emulated complementary
LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The scheme shown in Figure 4.2 is
one possible solution for point-to-point signals.
Table 4.18. LVDS25E DC Conditions
Parameter
Description
Typical
Unit
VCCIO
Output Driver Supply (±5%)
2.50
V
ZOUT
Driver Impedance
20
Ω
RS
Driver Series Resistor (±1%)
158
Ω
RP
Driver Parallel Resistor (±1%)
140
Ω
RT
Receiver Termination (±1%)
100
Ω
VOH
Output High Voltage
1.43
V
VOL
Output Low Voltage
1.07
V
VOD
Output Differential Voltage
0.35
V
VCM
Output Common Mode Voltage
1.25
V
ZBACK
Back Impedance
100.5
Ω
IDC
DC Output Current
6.03
mA
Figure 4.2. LVDS25E Output Termination Example
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FPGA-DS-02078-1.0
103
Certus-NX Family
Data Sheet
4.12.3. SubLVDS (Input Only)
SubLVDS is a reduced-voltage form of LVDS signaling, very similar to LVDS. It is a standard used in many camera types
of applications, and follow the SMIA 1.0, Part 2: CCP2 Specification. Being similar to LVDS, the Certus-NX devices can
support the subLVDS input signaling with the same LVDS input buffer. The output for subLVDS is implemented in
subLVDSE/subLVDSEH with a pair of LVCMOS18 output drivers (see SubLVDSE/SubLVDSEH (Output Only) section).
Table 4.19. SubLVDS Input DC Electrical Characteristics
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
VID
Input Differential Threshold Voltage
Over VICM range
70
150
200
mV
VICM
Input Common Mode Voltage
Half the sum of the two Inputs
0.4
0.9
1.4
V
Figure 4.3. SubLVDS Input Interface
4.12.4. SubLVDSE/SubLVDSEH (Output Only)
SubLVDS output uses a pair of LVCMOS18 drivers with True and Complement outputs. The VCCIO of the bank used for
subLVDSE or subLVDSEH needs to be powered by 1.8V. SubLVDSE is for Bank 0, Bank 1, Bank 2, Bank 5, and Bank 6; and
subLVDSEH is for Bank 3, Bank 4, and Bank 5.
Performance of the subLVDSE/subLVDSEH driver is limited to the performance of LVCMOS18.
Table 4.20. SubLVDS Output DC Electrical Characteristics
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
VOD
Output Differential Voltage Swing
—
—
150
—
mV
VOCM
Output Common Mode Voltage
Half the sum of the two Outputs
—
0.9
—
V
Figure 4.4. SubLVDS Output Interface
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104
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
4.12.5. SLVS
Scalable Low-Voltage Signaling (SLVS) is based on a point-to-point signaling method defined in the JEDEC JESD8-13
(SLVS-400) standard. This standard evolved from the traditional LVDS standard with smaller voltage swings and a lower
common-mode voltage. The 200 mV (400 mV p-p) SLVS swing contributes to a reduction in power.
The Certus-NX devices receive SLVS differential input with the LVDS input buffer. This LVDS input buffer is design to
cover wide input common mode range that can meet the SLVS input standard specified by the JEDEC standard.
Table 4.21. SLVS Input DC Characteristics
Parameter
Description
Test Conditions
Min
VID
Input Differential Threshold Voltage
Over VICM range
70
VICM
Input Common Mode Voltage
Half the sum of the two Inputs
70
Typ
Max
Unit
—
—
mV
200
330
mV
The SLVS output on Certus-NX is supported with the LVDS drivers found in Bank 3, Bank 4, and Bank 5. The LVDS driver
on Certus-NX is a current controlled driver. It can be configured as LVDS driver, or configured with the 100 Ω
differential termination with center-tap set to VOCM at 200 mV. This means the differential output driver can be placed
into bank with VCCIO = 1.2 V, 1.5 V, or 1.8 V, even if it is powered by VCCIO.
Table 4.22. SLVS Output DC Characteristics
Parameter
Description
Test Conditions
Min
VCCIO
Bank VCCIO
—
–5%
VOD
VOCM
ZOS
Output Differential Voltage Swing
Output Common Mode Voltage
Single-Ended Output Impedance
—
Half the sum of the two Outputs
—
140
150
37.5
Typ
1.2,
1.5,
1.8
200
200
50
Max
Unit
+ 5%
V
270
250
62.5
mV
mV
Ω
4.12.6. Differential HSTL15D (Output Only)
Differential HSTL outputs are implemented as a pair of complementary single-ended HSTL outputs.
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FPGA-DS-02078-1.0
105
Certus-NX Family
Data Sheet
4.12.7. Differential SSTL135D, SSTL15D (Output Only)
Differential SSTL is used for differential clock in DDR3/DDR3L memory interface. All differential SSTL outputs are
implemented as a pair of complementary single-ended SSTL outputs. All allowable single-ended output classes (class I
and class II) are supported.
4.12.8. Differential HSUL12D (Output Only)
Differential HSUL is used for differential clock in LPDDR2/LPDDR3 memory interface. All differential HSUL outputs are
implemented as a pair of complementary single-ended HSUL12 outputs. All allowable single-ended drive strengths are
supported.
4.12.9. Differential LVCMOS25D, LVCMOS33D, LVTTL33D (Output Only)
Differential LVCMOS and LVTTL outputs are implemented as a pair of complementary single-ended outputs. All
allowable single-ended output drive strengths are supported.
4.13. Certus-NX Maximum sysI/O Buffer Speed
Table 4.23. Certus-NX Maximum I/O Buffer Speed1, 2, 3, 4, 7
Buffer
Description
Banks
Max
Unit
Maximum sysI/O Input Frequency
Single-Ended
LVCMOS33
LVCMOS33, VCCIO = 3.3 V
0, 1, 2, 6, 7
200
MHz
LVTTL33
LVTTL33, VCCIO = 3.3 V
0, 1, 2, 6, 7
200
MHz
LVCMOS25
LVCMOS25, VCCIO = 2.5 V
0, 1, 2, 6, 7
200
MHz
5
LVCMOS18, VCCIO = 1.8 V
0, 1, 2, 6, 7
200
MHz
LVCMOS18H
LVCMOS18, VCCIO = 1.8 V
3, 4, 5
200
MHz
5
LVCMOS15, VCCIO = 1.5 V
0, 1, 2, 6, 7
100
MHz
LVCMOS15, VCCIO = 1.5 V
3, 4, 5
150
MHz
LVCMOS12, VCCIO = 1.2 V
0, 1, 2, 6, 7
50
MHz
LVCMOS12, VCCIO = 1.2 V
3, 4, 5
100
MHz
LVCMOS18
LVCMOS15
LVCMOS15H 5
LVCMOS12
5
LVCMOS12H 5
LVCMOS10
5
LVCMOS 1.0, VCCIO = 1.2 V
0, 1, 2, 6, 7
50
MHz
LVCMOS10H 5
LVCMOS 1.0, VCCIO = 1.0 V
3, 4, 5
50
MHz
LVCMOS10R
LVCMOS 1.0, VCCIO independent
3, 4, 5
50
MHz
SSTL15_I, SSTL15_II
SSTL_15, VCCIO = 1.5 V
3, 4, 5
1066
Mbps
SSTL135_I, SSTL135_II
SSTL_135, VCCIO = 1.35 V
3, 4, 5
1066
Mbps
HSUL12
HSUL_12, VCCIO = 1.2 V
3, 4, 5
1066
Mbps
HSTL15
HSTL15, VCCIO = 1.5 V
3, 4, 5
250
Mbps
LVDS, VCCIO independent QFN72, caBGA256,
csBGA289, and caBGA400
3, 4, 5
1250
Mbps
LVDS, VCCIO independent csfBGA121
3, 4, 5
1500
Mbps
subLVDS, VCCIO independent QFN72,
caBGA256, csBGA289, and caBGA400
3, 4, 5
1250
Mbps
subLVDS, VCCIO independent csfBGA121
3, 4, 5
1500
Mbps
SLVS similar to MIPI HS, VCCIO independent
QFN72, caBGA256, csBGA289, caBGA400
3, 4, 5
1250
Mbps
Differential
LVDS
subLVDS
SLVS
© 2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
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106
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
Buffer
Description
Banks
Max
Unit
SLVS similar to MIPI HS, VCCIO independent
csfBGA121
3, 4, 5
1500
Mbps
SSTL15D
Differential SSTL15, VCCIO independent
3, 4, 5
1066
Mbps
SSTL135D
Differential SSTL135, VCCIO independent
3, 4, 5
1066
Mbps
HUSL12D
Differential HSUL12, VCCIO independent
3, 4, 5
1066
Mbps
HSTL15D
Differential HSTL15, VCCIO independent
3, 4, 5
250
Mbps
Maximum sysI/O Output Frequency
Single-Ended
LVCMOS33 (all drive strengths)
LVCMOS33, VCCIO = 3.3 V
0, 1, 2, 6, 7
200
MHz
LVCMOS33 (RS50)
LVCMOS33, VCCIO = 3.3 V, RSERIES = 50 Ω
0, 1, 2, 6, 7
200
MHz
LVTTL33 (all drive strengths)
LVTTL33, VCCIO = 3.3 V
0, 1, 2, 6, 7
200
MHz
LVTTL33 (RS50)
LVTTL33, VCCIO = 3.3 V, RSERIES = 50 Ω
0, 1, 2, 6, 7
200
MHz
LVCMOS25 (all drive strengths)
LVCMOS25, VCCIO = 2.5 V
0, 1, 2, 6, 7
200
MHz
LVCMOS25 (RS50)
LVCMOS25, VCCIO = 2.5 V, RSERIES = 50 Ω
0, 1, 2, 6, 7
200
MHz
LVCMOS18 (all drive strengths)
LVCMOS18, VCCIO = 1.8 V
0, 1, 2, 6, 7
200
MHz
LVCMOS18 (RS50)
LVCMOS18, VCCIO = 1.8 V, RSERIES = 50 Ω
0, 1, 2, 6, 7
200
MHz
LVCMOS18H (all drive strengths)
LVCMOS18, VCCIO = 1.8 V
3, 4, 5
200
MHz
LVCMOS18H (RS50)
LVCMOS18, VCCIO = 1.8 V, RSERIES = 50 Ω
3, 4, 5
200
MHz
LVCMOS15 (all drive strengths)
LVCMOS15, VCCIO = 1.5 V
0, 1, 2, 6, 7
100
MHz
LVCMOS15H (all drive strengths)
LVCMOS15, VCCIO = 1.5 V
3, 4, 5
150
MHz
LVCMOS12 (all drive strengths)
LVCMOS12, VCCIO = 1.2 V
0, 1, 2, 6, 7
50
MHz
LVCMOS12H (all drive strengths)
LVCMOS12, VCCIO = 1.2 V
3, 4, 5
100
MHz
LVCMOS10H (all drive strengths)
LVCMOS12, VCCIO = 1.2 V
3, 4, 5
50
MHz
SSTL15_I, SSTL15_II
SSTL_15, VCCIO = 1.5 V
3, 4, 5
1066
Mbps
SSTL135_I, SSTL135_II
SSTL_135, VCCIO = 1.35 V
3, 4, 5
1066
Mbps
HSUL12 (all drive strengths)
HSUL_12, VCCIO = 1.2 V
3, 4, 5
1066
Mbps
HSTL15
HSTL15, VCCIO = 1.5 V
3, 4, 5
250
Mbps
LVDS, VCCIO = 1.8 V QFN72, caBGA256,
csBGA289, and caBGA400
LVDS, VCCIO = 1.8 V csfBGA121
3, 4, 5
1250
Mbps
3, 4, 5
1500
Mbps
Differential
LVDS
LVDS25E6
LVDS25, Emulated, VCCIO = 2.5 V
0, 1, 2, 6, 7
400
Mbps
SubLVDSE6
subLVDS, Emulated, VCCIO = 1.8 V
0, 1, 2, 6, 7
400
Mbps
SubLVDSEH6
subLVDS, Emulated, VCCIO = 1.8 V
3, 4, 5
800
Mbps
SLVS
SLVS similar to MIPI, VCCIO = 1.2 V
QFN72, caBGA256, csBGA289, caBGA400
3, 4, 5
1250
SLVS similar to MIPI, VCCIO = 1.2 V
csfBGA121
3, 4, 5
1500
SSTL15D
Differential SSTL15, VCCIO = 1.5 V
3, 4, 5
1066
Mbps
SSTL135D
Differential SSTL135, VCCIO = 1.35 V
3, 4, 5
1066
Mbps
HUSL12D
Differential HSUL12, VCCIO = 1.2 V
3, 4, 5
1066
Mbps
HSTL15D
Differential HSTL15, VCCIO = 1.5 V
3, 4, 5
250
Mbps
Mbps
Mbps
Notes:
1. Maximum I/O speed is the maximum switching rate of the I/O operating within the guidelines of the defining standard. The
actual interface speed performance using the I/O also depends on other factors, such as internal and external timing.
© 2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
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FPGA-DS-02078-1.0
107
Certus-NX Family
Data Sheet
2.
3.
4.
5.
6.
7.
8.
These numbers are characterized but not test on every device.
Performance is specified in MHz, as defined in clock rate when the sysI/O is used as pin. For data rate performance, this can be
converted to Mbps, which equals to 2 times the clock rate.
LVCMOS and LVTTL are measured with load specified in Table 3.43.
These LVCMOS inputs can be placed in different VCCIO voltage. Performance may vary. Please refer to Lattice Design Software
These emulated outputs performance is based on externally properly terminated as described in LVDS25E (Output Only) and
SubLVDSE/SubLVDSEH (Output Only).
All speeds are measured with fast slew.
For maximum differential I/O performance only Differential I/O should be placed in the bottom I/O banks. If this is not possible,
the following will impact on maximum performance:
a. If Fast Slew Rate LVCMOS I/O are used, they should be limited to no more than nine I/O (adjacent), four I/O (same bank),
55 I/O (left/right banks) to keep degradation below 50%.
b. If non-Differential I/O (SLOW SLEW) are placed on the bottom but not within the same bank as differential I/O, then the
maximum Differential performance is degraded to 70% of original when 21 aggressors are toggling.
c. If non-Differential I/O (SLOW SLEW) are placed within the same bank as Differential I/O then the maximum performance is
degraded to 50% of original when 16 aggressor are toggling.
d. No performance impact if MIPI LP and MIPI HS are in the same bank.
e. If Differential RX/TX I/O are both placed within the same bank then the maximum performance is degraded to 90%.
f. For DDR3/3L, LPDDR2/3 separate DQ/DQS groups from Address/Commands/CLK groups into separate banks.
4.14. Typical Building Block Function Performance
These building block functions can be generated using Lattice Design Software Tool. Exact performance may vary with
the device and the design software tool version. The design software tool uses internal parameters that have been
characterized but are not tested on every device.
Table 4.24. Pin-to-Pin Performance
Typ. @ VCC =
1.0 V
Unit
16-bit Decoder (I/O configured with LVCMOS18, Left and Right Banks)
5.5
ns
16-bit Decoder (I/O configured with HSTL15_I, Bottom Banks)
5.1
ns
6
ns
6.1
ns
Function
16:1 Mux (I/O configured with LVCMOS18, Left and Right Banks)
16:1 Mux (I/O configured with HSTL15_I, Bottom Banks)
Note: These functions are generated using Lattice Radiant Design Software tool. Exact performance may vary with the device and
the design software tool version. The design software tool uses internal parameters that have been characterized but are not tested
on every device.
Table 4.25. Register-to-Register Performance
Typ. @ VCC =
1.0 V
Unit
16-bit Adder
5002
MHz
32-bit Adder
496
MHz
16-bit Counter
402
MHz
32-bit Counter
371
MHz
512 × 36 Single Port RAM, with Output Register
5002
MHz
1024 × 18 True-Dual Port RAM using same clock, with EBR Output Registers
5002
MHz
1024 × 18 True-Dual Port RAM using asynchronous clocks, with EBR Output Registers
5002
MHz
Function
Basic Functions
Embedded Memory Functions
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108
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
Typ. @ VCC =
1.0 V
Unit
32 k × 32 Single Port RAM, with Output Register
1652
MHz
32 k × 32 Single Port RAM with ECC, with Output Register
1302
MHz
32 k × 32 True-Dual Port RAM using same clock, with Output Registers
340
MHz
16 × 4 Single Port RAM (One PFU)
5002
MHz
16 × 2 Pseudo-Dual Port RAM (One PFU)
5002
MHz
16 × 4 Pseudo-Dual Port (Two PFUs)
5002
MHz
9 × 9 Multiplier with Input Output Registers
351
MHz
9 × 9 Multiplier with Input/Pipelined/Output Registers
240
MHz
18 × 18 Multiplier with Input/Output Registers
214
MHz
18 × 18 Multiplier with Input/Pipelined/Output Registers
191
MHz
36 × 36 Multiplier with Input/Output Registers
201
MHz
36 × 36 Multiplier with Input/Pipelined/Output Registers
129
MHz
MAC 9 × 9 with Input/Output Registers
218
MHz
MAC 9 × 9 with Input/Pipelined/Output Registers
238
MHz
Function
Large Memory Functions
Distributed Memory Functions
DSP Functions
Notes:
1. The Clock port is configured with LVDS I/O type. Performance Grade: 9_High-Performance_1.0V.
2. Limited by the Minimum Pulse Width of the component
3. These functions are generated using Lattice Radiant Design Software tool. Exact performance may vary with the device and the
design software tool version. The design software tool uses internal parameters that have been characterized but are not
tested on every device.
4. For the Pipelined designs, the number of pipeline stages used are 2.
4.15. LMMI
Table 4.26 summarizes the performance of the LMMI interface with supported IPs. Additional timing requirement and
constraint can be identified through the Lattice Radiance design tools.
Table 4.26. LMMI FMAX Summary
IP
FMAX (MHz)
CDR0
73
CDR1
70
DPHY0
67
DPHY1
55
CRE
54
I2 C
38
PCIe
57
PLL_ULC
59
PLL_LLC
55
PLL_LRC
37
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FPGA-DS-02078-1.0
109
Certus-NX Family
Data Sheet
4.16. Derating Timing Tables
Logic timing provided in the following sections of this data sheet and the Lattice Radiant design tools are worst case
numbers in the operating range. Actual delays at nominal temperature and voltage for best case process, can be much
better than the values given in the tables. The Lattice Radiant design tool can provide logic timing numbers at a
particular temperature and voltage.
4.17. Certus-NX External Switching Characteristics
Over recommended commercial operating conditions.
Table 4.27. Certus-NX External Switching Characteristics (VCC = 1.0 V)
Parameter
Clocks
Primary Clock
fMAX_PRI
tW_PRI
tSKEW_PRI
Description
Frequency for Primary Clock
Clock Pulse Width for Primary
Clock
Primary Clock Skew Within a
Device
–8 Auto
Min
Max
Min
–7 Auto
Max
Unit
—
325.2
—
276
MHz
1.35
—
1.59
—
ns
—
554
—
653
ps
—
0.761
—
551.7
—
174
MHz
ns
ps
—
7.91
ns
0
—
ns
3.95
—
ns
1.86
—
ns
0.26
—
ns
—
5.57
ns
1.31
—
ns
1.44
—
ns
4.99
—
ns
0
—
ns
Edge Clock
fMAX_EDGE
Frequency for Edge Clock Tree
—
650.4
tW_EDGE
Clock Pulse Width for Edge Clock
0.646
—
tSKEW_EDGE
Edge Clock Skew Within a Device
—
148
Generic SDR Input
General I/O Pin Parameters Using Dedicated Primary Clock Input without PLL
Clock to Output – PIO Output
tCO
—
6.91
Register
Clock to Data Setup – PIO Input
tSU
0
—
Register
Clock to Data Hold – PIO Input
tH
3.35
—
Register
Clock to Data Setup – PIO Input
tSU_DEL
1.86
—
Register with Data Input Delay
Clock to Data Hold – PIO Input
tH_DEL
0.26
—
Register with Data Input Delay
General I/O Pin Parameters Using Dedicated Primary Clock Input with PLL
tCOPLL
Clock to Output – PIO Output
—
4.72
Register
tSUPLL
Clock to Data Setup – PIO Input
1.31
—
Register
tHPLL
Clock to Data Hold - PIO Input
1.22
—
Register
tSU_DELPLL
Clock to Data Setup - PIO Input
4.99
—
Register with Data Input Delay
tH_DELPLL
Clock to Data Hold - PIO Input
0
—
Register with Data Input Delay
Generic DDR Input/Output
Generic DDRX1 Inputs/Outputs with Clock and Data Centered at Pin (GDDRX1_RX/TX.SCLK.Centered) using PCLK Clock Input –
Figure 4.5 and Figure 4.7
0.917
—
0.917
—
Ns
tSU_GDDR1
Input Data Setup Before CLK
0.275
—
0.275
—
UI
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110
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
–8 Auto
–7 Auto
Unit
Min
Max
Min
Max
0.917
—
0.917
—
ns
tHO_GDDR1
Input Data Hold After CLK
0.275
—
0.275
—
UI
1.108
—
1.008
—
ns
Output Data Valid After CLK
tDVB_GDDR1
Output
–0.559
—
–0.659
—
ns + 1/2 UI
1.108
—
1.008
—
ns
Output Data Valid After CLK
tDQVA_GDDR1
Output
–0.559
—
–0.659
—
ns + 1/2 UI
fDATA_GDDRX1
Input/Output Data Rate
—
300
—
300
Mbps
fMAX_GDDRX1
Frequency of PCLK
—
150
—
150
MHz
½ UI
Half of Data Bit Time, or 90 degree
1.667
—
1.667
—
ns
Output TX to Input RX Margin per Edge
0.191
—
0.091
—
ns
Generic DDRX1 Inputs/Outputs with Clock and Data Aligned at Pin (GDDRX1_RX/TX.SCLK.Aligned) using PCLK Clock Input –
Figure 4.6 and Figure 4.8
—
–0.917
—
-0.917
ns + 1/2 UI
tDVA_GDDR1
Input Data Valid After CLK
—
0.75
—
0.75
ns
—
0.225
—
0.225
UI
0.917
—
0.917
—
ns + 1/2 UI
tDVE_GDDR1
Input Data Hold After CLK
2.583
—
2.583
—
ns
0.775
—
0.775
—
UI
Parameter
tDIA_GDDR1
tDIB_GDDR1
Description
Output Data Invalid After CLK
Output
Output Data Invalid Before CLK
Output
—
0.559
—
0.659
ns
—
0.559
—
0.659
ns
fDATA_GDDRX1
Input/Output Data Rate
—
300
—
300
Mbps
fMAX_GDDRX1
Frequency for PCLK
—
150
—
150
MHz
½ UI
Half of Data Bit Time, or 90 degree
1.667
—
1.667
—
ns
0.191
—
0.091
—
ns
Output TX to Input RX Margin per Edge
Generic DDRX2 Inputs/Outputs with Clock and Data Centered at Pin (GDDRX2_RX/TX.ECLK.Centered) using PCLK Clock Input –
Figure 4.5 and Figure 4.7
0.270
—
0.270
—
ns
tSU_GDDRX2
Data Setup before CLK Input
0.162
—
0.162
—
UI
tHO_GDDRX2
Data Hold after CLK Input
0.270
—
0.270
—
ns
0.684
—
0.658
—
ns
Output Data Valid Before CLK
tDVB_GDDRX2
Output
–0.149
—
–0.176
—
ns + 1/2 UI
0.684
—
0.658
—
ns
Output Data Valid After CLK
tDQVA_GDDRX2
Output
–0.149
—
–0.176
—
ns + 1/2 UI
fDATA_GDDRX2
Input/Output Data Rate
—
600
—
600
Mbps
fMAX_GDDRX2
Frequency for ECLK
—
300
—
300
MHz
½ UI
Half of Data Bit Time, or 90 degree
0.833
—
0.833
—
ns
fPCLK
PCLK frequency
—
247.52
—
209.97
MHz
Output TX to Input RX Margin per Edge
0.434
—
0.408
—
ns
Generic DDRX2 Inputs/Outputs with Clock and Data Aligned at Pin (GDDRX2_RX/TX.ECLK.Aligned) using PCLK Clock Input –
Figure 4.6 and Figure 4.8
tDVA_GDDRX2
Input Data Valid After CLK
—
—
—
–0.458
0.375
0.225
—
—
—
–0.458
0.375
ns + 1/2 UI
ns
0.225
UI
© 2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02078-1.0
111
Certus-NX Family
Data Sheet
Parameter
Description
tDVE_GDDRX2
Input Data Hold After CLK
–8 Auto
Min
Max
0.458
—
1.292
—
0.775
—
–7 Auto
Min
Max
0.458
—
1.292
—
0.775
—
Unit
ns + 1/2 UI
ns
UI
Output Data Invalid After CLK
—
0.149
—
0.176
ns
Output
Output Data Invalid Before CLK
tDIB_GDDRX2
—
0.149
—
0.176
ns
Output
fDATA_GDDRX2
Input/Output Data Rate
—
600
—
600
Mbps
fMAX_GDDRX2
Frequency for ECLK
—
300
—
300
MHz
½ UI
Half of Data Bit Time, or 90 degree
0.833
—
0.589
—
ns
fPCLK
PCLK frequency
—
247.5
—
209.97
MHz
Output TX to Input RX Margin per Edge
0.266
—
0.091
—
ns
Generic DDRX4 Inputs/Outputs with Clock and Data Centered at Pin (GDDRX4_RX/TX.ECLK.Centered) using PCLK Clock Input –
Figure 4.5 and Figure 4.7
0.220
—
0.220
—
ns
tSU_GDDRX4
Input Data Set-Up Before CLK
0.220
—
0.220
—
UI
tHO_GDDRX4
Input Data Hold After CLK
0.220
—
0.220
—
ns
0.351
—
0.324
—
Output Data Valid Before CLK
tDVB_GDDRX4
Output
–0.148
—
–0.176
—
0.351
—
0.324
—
tDQVA_GDDRX4
Input/Output Data Rate
–0.148
—
–0.176
—
fDATA_GDDRX4
Input/Output Data Rate
—
1000
—
1000
Mbps
fMAX_GDDRX4
PCLK frequency
—
500
—
500
MHz
½ UI
Half of Data Bit Time, or 90 degree
0.5
—
0.5
—
ns
fPCLK
Input Data Set-Up Before CLK
—
125
—
125
MHz
Output TX to Input RX Margin per Edge
0.151
—
0.124
—
ns
Generic DDRX4 Inputs/Outputs with Clock and Data Aligned at Pin (GDDRX4_RX/TX.ECLK.Aligned) using PCLK Clock Input, Left
and Right sides Only – Figure 4.6 and Figure 4.8
—
–0.275
—
–0.275
ns + 1/2 UI
tDVA_GDDRX4
Input Data Valid After CLK
—
0.225
—
0.225
ns
—
0.225
—
0.225
UI
0.275
—
0.275
—
ns + 1/2 UI
tDVE_GDDRX4
Input Data Hold After CLK
0.775
—
0.775
—
ns
0.775
—
0.775
—
UI
—
—
Output Data Invalid After CLK
tDIA_GDDRX4
0.149
0.176
ns
Output
tDIA_GDDRX2
tDIB_GDDRX4
Output Data Invalid Before CLK
Output
—
fDATA_GDDRX4
fMAX_GDDRX4
Input/Output Data Rate
Frequency for ECLK
—
—
1000
500
½ UI
Half of Data Bit Time, or 90 degree
0.5
fPCLK
PCLK frequency
Output TX to Input RX Margin per Edge
0.149
—
0.176
ns
—
—
1000
500
Mbps
MHz
—
0.5
—
ns
—
125
—
125
MHz
0.076
—
0.049
—
ns
© 2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
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112
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
Parameter
Description
–8 Auto
Min
Max
Min
–7 Auto
Max
Unit
Generic DDRX5 Inputs/Outputs with Clock and Data Centered at Pin (GDDRX5_RX/TX.ECLK.Centered) using PCLK Clock Input –
Figure 4.5 and Figure 4.7
0.22
—
0.22
—
ns
tSU_GDDRX5
Input Data Set-Up Before CLK
0.22
—
0.22
—
UI
tHO_GDDRX5
Input Data Hold After CLK
0.22
—
0.22
—
ns
tWINDOW_GDDRX5C
Input Data Valid Window
0.44
—
0.44
—
ns
0.351
—
0.324
—
ns
Output Data Valid Before CLK
tDVB_GDDRX5
Output
–0.149
—
–0.176
—
ns+1/2UI
0.351
—
0.324
—
ns
Output Data Valid After CLK
tDQVA_GDDRX5
Output
–0.149
—
–0.176
—
ns+1/2UI
fDATA_GDDRX5
Input/Output Data Rate
—
1000
—
1000
Mbps
fMAX_GDDRX5
Frequency for ECLK
—
500
—
500
MHz
½ UI
Half of Data Bit Time, or 90 degree
0.5
—
0.5
—
ns
fPCLK
PCLK frequency
—
100
—
100
MHz
Output TX to Input RX Margin per Edge
0.151
—
0.124
—
ns
Generic DDRX5 Inputs/Outputs with Clock and Data Aligned at Pin (GDDRX5_RX/TX.ECLK.Aligned) using PCLK Clock Input, Left
and Right sides Only – Figure 4.6 and Figure 4.8
—
–0.275
—
–0.275
ns + 1/2 UI
tDVA_GDDRX5
Input Data Valid After CLK
—
0.225
—
0.225
ns
—
0.225
—
0.225
UI
0.275
—
0.275
—
ns + 1/2 UI
tDVE_GDDRX5
Input Data Hold After CLK
0.775
—
0.775
—
ns
0.775
—
0.775
—
UI
tWINDOW_GDDRX5A
Input Data Valid Window
0.55
—
0.55
—
ns
Output Data Invalid After CLK
—
0.149
—
Output
Output Data Invalid Before CLK
tDIB_GDDRX5
—
0.149
—
Output
fDATA_GDDRX5
Input/Output Data Rate
—
1000
—
fMAX_GDDRX5
Frequency for ECLK
—
500
—
½ UI
Half of Data Bit Time, or 90 degree
0.5
—
0.5
fPCLK
PCLK frequency
—
100
—
Output TX to Input RX Margin per Edge
0.076
—
0.049
Soft D-PHY DDRX4 Inputs/Outputs with Clock and Data Centered at Pin, using PCLK Clock Input
0.21
—
0.21
tSU_GDDRX4_MP
Input Data Set-Up Before CLK
0.21
—
0.21
0.2
—
0.2
tHO_GDDRX4_MP
Input Data Hold After CLK
0.2
—
0.2
0.3
—
0.3
Output Data Valid Before CLK
tDVB_GDDRX4_MP
Output
0.3
—
0.3
0.3
—
0.3
Output Data Valid After CLK
tDQVA_GDDRX4_MP
Output
0.3
—
0.3
tDIA_GDDRX5
fDATA_GDDRX4_MP
Input Data Bit Rate for MIPI PHY
½ UI
Half of Data Bit Time, or 90 degree
fPCLK
PCLK frequency
Output TX to Input RX Margin per Edge
0.176
ns
0.176
ns
1000
500
—
100
—
Mbps
MHz
ns
MHz
ns
—
—
—
—
—
—
—
—
ns
UI
ns
UI
ns
UI
ns
UI
—
1000
—
1000
Mbps
0.5
—
0.1
—
125
—
0.5
—
0.1
—
125
—
ns
MHz
ns
© 2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02078-1.0
113
Certus-NX Family
Data Sheet
Parameter
Description
–8 Auto
Min
Max
Min
–7 Auto
Max
Unit
Video DDRX71 Inputs/Outputs with Clock and Data Aligned at Pin (GDDRX71_RX.ECLK) using PLL Clock Input – Figure 4.10 and
Figure 4.11
—
0.237
—
0.277
UI
Input Valid Bit "i" switch from CLK
tRPBi_DVA
Rising Edge ("i" = 0 to 6, 0 aligns
—
—
–0.278
–0.278
ns+(1/2+i)*UI
with CLK)
0.748
—
0.711
—
UI
Input Hold Bit "i" switch from CLK
tRPBi_DVE
Rising Edge ("i" = 0 to 6, 0 aligns
—
—
0.263
0.263
ns+(1/2+i)*UI
with CLK)
Data Output Valid Bit "i" switch
tTPBi_DOV
from CLK Rising Edge ("i" = 0 to 6,
—
0.159
—
0.187
ns+i*UI
0 aligns with CLK)
Data Output Invalid Bit "i" switch
tTPBi_DOI
from CLK Rising Edge ("i" = 0 to 6,
-0.159
—
-0.187
—
ns+(i+ 1)*UI
0 aligns with CLK)
tTPBi_skew_UI
TX skew in UI
—
0.150
—
0.150
UI
tB
Serial Data Bit Time, = 1UI
1.058
—
1.247
—
ns
fDATA_TX71
DDR71 Serial Data Rate
—
945
—
802
Mbps
fMAX_TX71
DDR71 ECLK Frequency
—
472.5
—
401
MHz
fCLKIN
7:1 Clock (PCLK) Frequency
—
133.7
—
113.4
MHz
Output TX to Input RX Margin per Edge
0.159
—
0.187
—
ns
Memory Interface
DDR3/DDR3L/LPDDR2/LPDDR3 READ (DQ Input Data are Aligned to DQS) – Figure 4.6
tDVBDQ_DDR3 tDVBDQ_DDR3L
Data Input Valid before DQS Input
—
–0.235
—
tDVBDQ_LPDDR2 tDVBDQ_LPDDR3
tDVADQ_DDR3 tDVADQ_DDR3L
Data Input Valid after DQS Input
0.235
—
0.277
tDVADQ_LPDDR2 tDVADQ_LPDDR3
fDATA_DDR3 fDATA_DDR3L
DDR Memory Data Rate
—
1066
—
fDATA_LPDDR2 fDATA_LPDDR3
fMAX_ECLK_DDR3
fMAX_ECLK_DDR3L
DDR Memory ECLK Frequency
—
533
—
fMAX_ECLK_LPDDR2
fMAX_ECLK_LPDDR3
fMAX_SCLK_DDR3
fMAX_SCLK_DDR3L
DDR Memory SCLK Frequency
—
133.3
—
fMAX_SCLK_LPDDR2
fMAX_SCLK_LPDDR3
DDR3/DDR3L/LPDDR2/LPDDR3 WRITE (DQ Output Data are Centered to DQS) – Figure 4.9
tDQVBS_DDR3 tDQVBS_DDR3L
Data Output Valid before DQS
—
–0.235
—
tDQVBS_LPDDR2 tDQVBS_LPDDR3 Output
tDQVAS_DDR3 tDQVAS_DDR3L
Data Output Valid after DQS
0.235
—
0.277
tDQVAS_LPDDR2 tDQVAS_LPDDR3 Output
fDATA_DDR3 fDATA_DDR3L
DDR Memory Data Rate
—
1066
—
fDATA_LPDDR2 fDATA_LPDDR3
fMAX_ECLK_DDR3
fMAX_ECLK_DDR3L
DDR Memory ECLK Frequency
—
533
—
fMAX_ECLK_LPDDR2
fMAX_ECLK_LPDDR3
fMAX_SCLK_DDR3
fMAX_SCLK_DDR3L
DDR Memory SCLK Frequency
—
133.3
—
fMAX_SCLK_LPDDR2
fMAX_SCLK_LPDDR3
–0.277
ns + 1/2 UI
—
ns + 1/2 UI
904
Mb/s
452
MHz
113
MHz
–0.277
ns + 1/2 UI
—
ns + 1/2 UI
904
Mb/s
452
MHz
113
MHz
© 2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
114
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
Notes:
1. Commercial timing numbers are shown. Industrial numbers are typically slower and can be extracted from the Lattice Radiant
software.
2. General I/O timing numbers are based on LVCMOS 1.8, 8 mA, Fast Slew Rate, 0 pf load.
Generic DDR timing are numbers based on LVDS I/O.
DDR3 timing numbers are based on SSTL15.
LPDDR2 and LPDDR3 timing numbers are based on HSUL12.
3. Uses LVDS I/O standard for measurements.
4. Maximum clock frequencies are tested under best case conditions. System performance may vary upon the user environment.
5. All numbers are generated with the Lattice Radiant software.
Rx CLK (in)
Rx DATA (in)
tSU
tSU
tHD
tHD
Figure 4.5. Receiver RX.CLK.Centered Waveforms
½ UI
½ UI
1 UI
Rx CLK (in)
or DQS input
Rx DATA (in)
or DQS input
tDVA/tDVADQ
tDVA/tDVADQ
tDVE/tDVEDQ
tDVE/tDVEDQ
Figure 4.6. Receiver RX.CLK.Aligned and DDR Memory Input Waveforms
© 2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02078-1.0
115
Certus-NX Family
Data Sheet
1/2 UI
1/2 UI
1/2 UI
1/2 UI
Tx CLK (out)
or DQS Output
Tx DATA (out)
or DQ Output
tDVB/tDQVBS
tDVB/tDQVBS
tDVA/tDQVAS
tDVA/tDQVA
Figure 4.7. Transmit TX.CLK.Centered and DDR Memory Output Waveforms
1 UI
Tx CLK (out)
Tx DATA (out)
tDIB
tDIB
tDIA
tDIA
Figure 4.8. Transmit TX.CLK.Aligned Waveforms
© 2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
116
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
Receiver – Shown for one LVDS Channel
# of Bits
Data In
756 Mb/s
Clock In
108 MHz
For each Channel:
7-bit Output Words
to FPGA Fabric
Bit #
10 – 1
11 – 2
12 – 3
13 – 4
14 – 5
15 – 6
16 – 7
0x
0x
0x
0x
0x
0x
0x
Bit #
20 – 8
21 – 9
22 – 10
23 – 11
24 – 12
25 – 13
26 – 14
Bit #
30 – 15
31 – 16
32 – 17
33 – 18
34 – 19
35 – 20
36 – 21
Bit #
40 – 22
41 – 23
42 – 24
43 – 25
44 – 26
45 – 27
46 – 28
Transmitter – Shown for one LVDS Channel
# of Bits
Data Out
756 Mb/s
Clock Out
108 MHz
For each Channel:
7-bit Output Words
to FPGA Fabric
Bit #
00 – 1
00 – 2
00 – 3
00 – 4
00 – 5
00 – 6
00 – 7
Bit #
10 – 8
11 – 9
12 – 10
13 – 11
14 – 12
15 – 13
16 – 14
Bit #
20 – 15
21 – 16
22 – 17
23 – 18
24 – 19
25 – 20
26 – 21
Bit #
30 – 22
31 – 23
32 – 24
33 – 25
34 – 26
35 – 27
36 – 28
Figure 4.9. DDRX71 Video Timing Waveforms
Bit 0
1/2 UI
CLK (in)
Bit i
1/2 UI
Bit 1
1 UI
DATA (in)
tSU_0
tHD_0
tSU_i
tHD_i
Figure 4.10. Receiver DDRX71_RX Waveforms
© 2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02078-1.0
117
Certus-NX Family
Data Sheet
Bit 0
Bit i
Bit 1
1 UI
CLK (out)
DATA (out)
tDIB_0
tDIA_0
tDIB_i
tDIA_i
Figure 4.11. Transmitter DDRX71_TX Waveforms
4.18. Certus-NX sysCLOCK PLL Timing (VCC = 1.0 V)
Table 4.28. sysCLOCK PLL Timing (VCC = 1.0 V)
Parameter
Descriptions
Conditions
Min
Typ.
Max
Units
fIN
Input Clock Frequency (CLKI, CLKFB)
—
10
—
500
MHz
fOUT
Output Clock Frequency
—
6.25
—
800
MHz
fVCO
PLL VCO Frequency
—
800
—
1600
MHz
Without FractionalN Enabled
10
—
500
MHz
With Fractional-N
Enabled
10
—
100
MHz
55
%
fPFD
3
Phase Detector Input Frequency
AC Characteristics
tDT
Output Clock Duty Cycle
—
45
—
tPH4
Output Phase Accuracy
—
–5
—
5
%
fOUT ≥ 200 MHz
—
—
250
ps p-p
fOUT < 200 MHz
—
—
0.05
UIPP
fOUT ≥ 200 MHz
—
—
250
ps p-p
fOUT < 200 MHz
—
—
0.05
UIPP
fPFD ≥ 200 MHz
—
—
250
ps p-p
fPFD < 200 MHz
—
—
0.05
UIPP
fOUT ≥ 200 MHz
—
—
350
ps p-p
fOUT < 200 MHz
—
—
0.07
UIPP
fOUT ≥ 200 MHz
—
—
400
ps p-p
fOUT < 200 MHz
—
—
0.08
UIPP
13
MHz
10
ms
Output Clock Period Jitter
Output Clock Cycle-to-Cycle Jitter
Output Clock Phase Jitter
tOPJIT1
Output Clock Period Jitter (Fractional-N)
Output Clock Cycle-to-Cycle Jitter (Fractional-N)
fBW4
2
tLOCK
PLL Loop Bandwidth
—
0.45
PLL Lock-in Time
—
—
—
© 2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
118
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
Parameter
Descriptions
Conditions
Min
Typ.
tUNLOCK
PLL Unlock Time (from RESET goes HIGH)
Max
Units
—
—
—
50
ns
fPFD ≥ 20 MHz
—
—
500
ps p-p
tIPJIT
Input Clock Period Jitter
fPFD < 20 MHz
—
—
0.01
UIPP
tHI
Input Clock High Time
90% to 90%
0.5
—
—
ns
tLO
Input Clock Low Time
10% to 10%
0.5
—
—
ns
tRST
RST/ Pulse Width
—
1
—
—
ms
fSSC_MOD
Spread Spectrum Clock Modulation Frequency
—
20
—
200
kHz
fSSC_MOD_AMP
Spread Spectrum Clock Modulation Amplitude
Range
—
0.25
—
2.00
%
fSSC_MOD_STEP
Spread Spectrum Clock Modulation Amplitude
Step Size
—
—
0.25
—
%
Notes:
1. Jitter sample is taken over 10,000 samples for Period jitter, and 1,000 samples for Cycle-to-Cycle jitter of the primary PLL output
with clean reference clock with no additional I/O toggling.
2. Output clock is valid after tLOCK for PLL reset and dynamic delay adjustment.
3. Period jitter and cycle-to-cycle jitter numbers are guaranteed for fPFD > 10 MHz. For fPFD < 10 MHz, the jitter numbers may not
be met in certain conditions.
4. Result from Lattice Radiant software.
4.19. Certus-NX Internal Oscillators Characteristics
Table 4.29. Internal Oscillators (VCC = 1.0 V)
c
Parameter Description
fCLKHF
fCLKLF
DCHCLKHF
DCHCLKLF
Min
Typ
Max
Unit
HFOSC CLKK Clock Frequency
418.5
450
481.5
MHz
LFOSC CLKK Clock Frequency
18.2
32
45.8
kHz
HFOSC Duty Cycle (Clock High Period)
43
50
57
%
LFOSC Duty Cycle (Clock High Period)
45
50
55
%
4.20. Certus-NX User I2C Characteristics
Table 4.30. User I2C Specifications (VCC = 1.0 V)
Symbol
fscl
Parameter Description
SCL Clock Frequency
STD Mode
FAST Mode Plus2
FAST Mode
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
—
—
100
—
—
400
—
—
1000
Units
kHz
1
Optional delay through
TDELAY
—
—
62
—
—
62
—
—
62
ns
delay block
Notes:
1. Refer to the I2C Specification for timing requirements. User design should set constraints in Lattice Design Software to meet this
industrial I2C Specification.
2. Fast Mode Plus maximum speed may be achieved by using external pull up resistor on I2C bus. Internal pull up may not be
sufficient to support the maximum speed.
© 2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
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FPGA-DS-02078-1.0
119
Certus-NX Family
Data Sheet
4.21. Certus-NX Analog-Digital Converter (ADC) Block Characteristics
Table 4.31. ADC Specifications
Symbol
VREFINT_ADC
VREFEXT_ADC
NRES_ADC
ENOBADC
Description
Condition
ADC Internal Reference
Voltage
ADC External Reference
Voltage
ADC Resolution
Effective Number of Bits
—
—
—
—
Bipolar Mode, Internal VREF
Bipolar Mode, External VREF
VSR_ADC
VCM_ADC
fCLK_ADC
DCCLK_ADC
fINPUT_ADC
FSADC
NTRACK_ADC
RIN_ADC
tCAL_ADC
LOUTput_ADC
DNLADC
INLADC
SFDRADC
THDADC
SNRADC
SNDRADC
ADC Input Range
ADC Input Common Mode
Voltage (for fully differential
signals)
ADC Clock Frequency
ADC Clock Duty Cycle
ADC Input Frequency
ADC Sampling Rate
ADC Input Tracking Time
ADC Input Equivalent
Resistance
ADC Calibration Time
ADC Conversion Time
ADC Differential
Nonlinearity
ADC Integral Nonlinearity
ADC Spurious Free Dynamic
Range
ADC Total Harmonic
Distortion
ADC Signal to Noise Ratio
ADC Signal to Noise Plus
Distortion Ratio
Uni-polar Mode, Internal
VREF
Min
Typ
Max
Unit
—
1.2
—
V
1.0
—
1.8
V
—
9.9
12
10.8
—
—
bits
bits
VCM_ADC ―
VREFINT_ADC/4
VCM_ADC ―
VREFEXT_ADC/4
VCM_ADC
VREFEXT_ADC
VCM_ADC +
VREFINT_ADC/4
VCM_ADC +
VREFEXT_ADC/4
V
V
0
—
VREFINT_ADC
V
Uni-polar Mode, External
VREF
Internal VREF
0
—
VREFEXT_ADC
V
—
VREFINT_ADC/2
—
V
External VREF
—
VREFEXT_ADC/2
—
V
—
—
—
—
—
—
48
—
—
2
25
50
—
1
—
40
52
500
—
—
MHz
%
kHz
MS/s
cycles
—
116
—
kΩ
—
25
—
—
6500
—
cycles
cycles
–1
—
1
LSB
–2.18
—
2.29
LSB
65.9
77
—
dBc
—
–76
–66.4
dB
61.66
67.5
—
dB
61.55
67
—
dB
–0.5
—
0.5
1 MS/s, Sampled @ 2 clock
cycles
—
—
—
—
—
—
—
—
ERRGAIN_ADC
ADC Gain Error
—
ERROFFSET_ADC
ADC Offset Error
—
–4
—
4
%
FSADC
LSB
CIN_ADC
ADC Input Equivalent
Capacitance
—
—
2
—
pF
© 2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
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120
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
4.22. Certus-NX Comparator Block Characteristics
Table 4.32. Comparator Specifications
Symbol
Description
Min
Typ
Max
Unit
fIN_COMP
Comparator Input Frequency
—
—
10
MHz
VIN_COMP
Comparator Input Voltage
0
—
VCC_ADC18
V
VOFFSET_COMP
Comparator Input Offset
–34.3
—
36.44
mV
VHYST_COMP
Comparator Input Hysteresis
10
—
31.62
mV
tLATENCY_COMP
Comparator Latency
—
—
31.24
ns
4.23. Certus-NX Digital Temperature Readout Characteristics
Digital temperature Readout (DTR) is implemented in one of the channels of ADC1.
Table 4.33. DTR Specifications
Symbol
Description
DTRRANGE
DTR Detect Temperature
Range
DTRACCURACY
DTR Accuracy
DTRRESOLUTION
DTR Resolution
Condition
—
with external voltage
reference range of 1.0 V
to 1.8 V
with external voltage
reference
Min
Typ
Max
Unit
–40
—
125
°C
–16
±6
16
°C
–0.3
—
0.3
°C
4.24. Certus-NX Hardened PCIe Characteristics
4.24.1. PCIe (2.5 Gb/s)
Table 4.34. PCIe (2.5 Gb/s)
Symbol
Transmitter1
UI
BWTX
VTX-DIFF-PP
VTX-DIFF-PP-LOW
VTX-DE-RATIO-3.5dB
TTX-RISE-FALL
TTX-EYE
TTX-EYE-MEDIAN-to-MAXJITTER
RLTX-DIFF
RLTX-CM
ZTX-DIFF-DC
Description
Condition
Min.
Unit Interval
Tx PLL bandwidth
Differential p-p Tx voltage
swing
Low power differential p-p Tx
voltage swing
Tx de-emphasis level ratio at
3.5dB
Transmitter rise and fall time
—
—
399.88
1.5
400
—
400.12
22
ps
MHz
—
0.8
—
1.2
Vp-p
—
0.4
—
1.2
Vp-p
—
3
—
4
dB
—
0.125
—
—
UI
—
0.75
—
—
UI
—
—
—
0.125
UI
10
—
—
dB
50 MHz < freq < 2.5 GHz
6
—
—
dB
—
80
—
120
Ω
Transmitter Eye, including all
jitter sources
Max. time between jitter
median and max deviation
from the median
Tx Differential Return Loss,
including pkg and silicon
Tx Common Mode Return Loss,
including pkg and silicon
DC differential Impedance
—
Typ.
Max.
Unit
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FPGA-DS-02078-1.0
121
Certus-NX Family
Data Sheet
Symbol
VTX-CM-AC-P
ITX-SHORT
VTX-DC-CM
VTX-IDLE-DIFF-AC-p
VTX-RCV-DETECT
TTX-IDLE-MIN
TTX-IDLE-SET-TO-IDLE
TTX-IDLE-TO-DIFF-DATA
LTX-SKEW
Receiver2
UI
VRX-DIFF-PP
TRX-EYE3
TRX-EYE-MEDIAN-to-MAX3
JITTER
RLRX-DIFF
RLRX-CM
ZRX-DC
ZRX-DIFF-DC
ZRX-HIGH-IMP-DC
VRX-CM-AC-P3
Description
Tx AC peak common mode
voltage, RMS
Transmitter short-circuit
current
Transmitter DC common-mode
voltage
Electrical Idle Output peak
voltage
Voltage change allowed during
Receiver Detect
Min. time in Electrical Idle
Max. time from EI Order Set to
valid Electrical Idle
Max. time from Electrical Idle
to valid differential output
Condition
Max time delta between
median and deviation from
median
Receiver differential Return
Loss, package plus silicon
Receiver common mode Return
Loss, package plus silicon
Receiver DC single ended
impedance
Receiver DC differential
impedance
Receiver DC single ended
impedance when powered
down
Rx AC peak common mode
voltage
Electrical Idle Detect Threshold
Receiver –lane-lane skew
Typ.
Max.
Unit
—
—
—
20
mV,
RMS
—
—
—
90
mA
—
0
—
1.2
V
—
—
—
20
mV
—
—
—
600
mV
—
20
—
—
ns
—
—
—
8
ns
—
—
—
8
ns
—
—
500 ps
+ 2 UI
ps
—
399.9
400
400.12
ps
—
0.175
—
1.2
Vp-p
—
0.4
—
—
UI
—
—
—
0.3
UI
—
10
—
—
dB
—
6
—
—
dB
—
40
—
60
Ω
—
80
—
120
Ω
—
200
—
—
kΩ
—
150
Lane-to-Lane output skew
Unit Interval
Differential Rx peak-peak
voltage
Receiver eye opening time
Min.
—
mV,
peak
mVp-p
ps
VRX-IDLE-DET-DIFF-PP
—
65
—
175
LRX-SKEW
—
20
Notes:
1. Refer to PCI Express Base Specification Revision 3.0 Table 4.18 test condition and requirement for respective parameters.
2. Refer to PCI Express Base Specification Revision 3.0 Table 4.24 test condition and requirement for respective parameters.
3. Spec compliant requirement
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122
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
4.24.2. PCIe (5 Gb/s)
Table 4.35. PCIe (5 Gb/s)
Symbol
Transmit1
Description
Test Conditions
UI
Unit Interval
BWTX-PKG-PLL1
BWTX-PKG-PLL2
PKGTX-PLL1
PKGTX-PLL2
VTX-DIFF-PP
VTX-DIFF-PP-LOW
VTX-DE-RATIO-3.5dB
VTX-DE-RATIO-6dB
TMIN-PULSE
TTX-RISE-FALL
TTX-EYE
TTX-DJ
Tx PLL bandwidth
corresponding to PKGTX-PLL1
Tx PLL bandwidth
corresponding to PKGTX-PLL2
Tx PLL Peaking
corresponding to PKGTX-PLL1
Tx PLL Peaking
corresponding to PKGTX-PLL2
Differential p-p Tx voltage
swing
Low power differential p-p Tx
voltage swing
Tx de-emphasis level ratio at
3.5dB
Tx de-emphasis level ratio at
6dB
Instantaneous lone pulse width
Transmitter rise and fall time
Transmitter Eye, including all
jitter sources
Tx deterministic jitter > 1.5
MHz
Min
Typ
Max
Unit
—
199.94
200
200.06
ps
—
8
—
16
MHz
—
5
—
16
MHz
—
—
—
3
dB
—
—
—
1
dB
—
0.8
—
1.2
V, p-p
—
0.4
—
1.2
V, p-p
—
3
—
4
dB
—
5.5
—
6.5
dB
—
—
0.9
0.15
—
—
—
—
UI
UI
—
0.75
—
—
UI
—
—
—
0.15
UI
TTX-RJ
Tx RMS jitter < 1.5 MHz
—
—
—
3
TRF-MISMATCH
Tx rise/fall time mismatch
RLTX-DIFF
Tx Differential Return Loss,
including package and silicon
—
50 MHz < freq < 1.25 GHz
1.25 GHz < freq < 2.5 GHz
—
10
8
—
—
—
0.1
—
—
ps,
RMS
UI
dB
dB
50 MHz < freq < 2.5 GHz
6
—
—
dB
—
—
—
120
—
—
—
150
Ω
mV,
p-p
—
—
—
90
mA
—
0
—
1.2
V
—
0
—
5
mV
—
—
—
20
mV
—
—
—
600
mV
—
20
—
—
ns
—
—
—
8
ns
—
—
—
8
ns
RLTX-CM
ZTX-DIFF-DC
VTX-CM-AC-PP
ITX-SHORT
VTX-DC-CM
VTX-IDLE-DIFF-DC
VTX-IDLE-DIFF-AC-p
VTX-RCV-DETECT
TTX-IDLE-MIN
TTX-IDLE-SET-TO-IDLE
TTX-IDLE-TO-DIFF-DATA
Tx Common Mode Return Loss,
including package and silicon
DC differential Impedance
Tx AC peak common mode
voltage, peak-peak
Transmitter short-circuit
current
Transmitter DC common-mode
voltage
Electrical Idle Output DC
voltage
Electrical Idle Differential
Output peak voltage
Voltage change allowed during
Receiver Detect
Min. time in Electrical Idle
Max. time from EI Order Set to
valid Electrical Idle
Max. time from Electrical Idle
to valid differential output
© 2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
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FPGA-DS-02078-1.0
123
Certus-NX Family
Data Sheet
Symbol
Description
LTX-SKEW
Test Conditions
Min
Typ
Max
Unit
ps
Lane-to-Lane output skew
—
—
—
500 + 4
UI
Unit Interval
Differential Rx peak-peak
voltage
Receiver random jitter
tolerance (RMS)
Receiver deterministic jitter
tolerance
—
199.94
200
200.06
ps
—
0.343
—
1.2
V, p-p
1.5 MHz – 100 MHz
Random noise
—
—
4.2
ps,
RMS
—
—
—
88
ps
Receiver differential Return
Loss, package plus silicon
50 MHz < freq < 1.25 GHz
1.25 GHz < freq < 2.5 GHz
10
8
—
—
—
—
dB
dB
—
6
—
—
dB
—
40
—
60
Ω
—
200
—
—
kΩ
—
—
—
150
Receive2
UI
VRX-DIFF-PP
TRX-RJ-RMS
TRX-DJ
RLRX-DIFF
Receiver common mode
Return Loss, package plus
silicon
Receiver DC single ended
impedance
Receiver DC single ended
impedance when powered
down
Rx AC peak common mode
voltage
Electrical Idle Detect Threshold
Receiver –lane-lane skew
RLRX-CM
ZRX-DC
ZRX-HIGH-IMP-DC
VRX-CM-AC-P3
mV,
peak
mv, pp
ns
VRX-IDLE-DET-DIFF-PP
—
65
—
1753
LRX-SKEW
—
—
—
8
Notes:
1. Refer to PCI Express Base Specification Revision 3.0 Table 4.18 test condition and requirement for respective parameters.
2. Refer to PCI Express Base Specification Revision 3.0 Table 4.24 test condition and requirement for respective parameters.
3. Spec compliant requirement
4.25. Certus-NX Hardened SGMII Receiver Characteristics
4.25.1. SGMII Rx Specifications
Table 4.36. SGMII Rx
Symbol
fDATA
fREFCLK
JTOL_Rj
JTOL_Dj
Description
SGMII Data Rate
SGMII Reference Clock Frequency (Data
Rate / 10)
Jitter Tolerance, Random (RMS)
Jitter Tolerance, Deterministic
JTOL_Tj
Jitter Tolerance, Total
Δf/f
Data Rate and Reference Clock Accuracy
Test Conditions
—
Min
—
Typ
1.25
Max
—
Unit
Gb/s
—
—
125
—
MHz
—
Periodic jitter
1 kHz–22 MHz
Periodic jitter
1 kHz–22 MHz
—
—
—
15
mUIrms
—
0.05*
UI
—
0.26*
UI
—
300
ppm
–300
*Note:
JTOT can meet the following deterministic jitter mask specification: 0 to 3.5 kHz: 10 UI; 3.5 to 700 kHz: log-log slope 10 UI to
0.05 UI; above 700 kHz: 0.05 UI.
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124
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
4.26. Certus-NX sysCONFIG Port Timing Specifications
Table 4.37. Certus-NX sysCONFIG Port Timing Specifications
Symbol
Parameter
Device
Min
Typ.
Max
Unit
—
—
—
5
ms
—
—
—
5
µs
—
—
3.5
—
MHz
—
—
—
1
µs
—
—
ns
—
—
ns
—
—
ns
Master SPI POR / REFRESH Timing
Time during POR, from VCC, VCCAUX, VCCIO0 or
VCCIO1 (whichever is the last) pass POR trip
voltage, or REFRESH command executed, to
the last rising edge of INITN
tICFG
Time from last rising edge of INITN to the valid
Master MCLK
Default MCLK frequency (Before MCLK
fMCLK_DEF
frequency selection in bitstream)
Slave SPI/I2C/I3C POR / REFRESH Timing
tVMC
Time during POR, from VCC, VCCAUX, VCCIO0 or
VCCIO1 (whichever is the last) pass POR trip
tMSPI_INH
voltage, or REFRESH command executed, to
pull PROGRAMN LOW to prevent entering
MSPI mode
Minimum time driving PROGRAMN HIGH after
tACT_PROGRAMN_H
last activation clock
Minimum time to start driving CCLK (SSPI) after
tCONFIG_CCLK
PROGRAMN HIGH
Minimum time to start driving SCL (I2C/I3C)
tCONFIG_SCL
after PROGRAMN HIGH
PROGRAMN Configuration Timing
—
—
—
50
50
50
tPROGRAMN
PROGRAMN LOW pulse accepted
—
50
—
—
ns
tPROGRAMN_RJ
PROGRAMN LOW pulse rejected
—
—
—
25
ns
tINIT_LOW
PROGRAMN LOW to INITN LOW
—
—
—
100
ns
LIFCL-40
—
30
—
µs
tINIT_HIGH
PROGRAMN LOW to INITN HIGH
LIFCL-17
—
30
—
µs
tDONE_LOW
PROGRAMN LOW to DONE LOW
—
—
—
55
µs
tDONE_HIGH
PROGRAMN HIGH to DONE HIGH
—
—
2
s
tIODISS
PROGRAMN LOW to I/O Disabled
—
—
—
125
ns
fMCLK*
Max selected MCLK output frequency
—
—
112.5
124
MHz
fMCLK_DC
MCLK output clock duty cycle
—
40
—
60
%
tMCLKH
MCLK output clock pulse width HIGH
—
3.5
—
—
ns
tMCLKL
MCLK output clock pulse width LOW
—
3.5
—
—
ns
tSU_MSI
MSI to MCLK setup time
—
3
—
—
ns
tHD_MSI
MSI to MCLK hold time
—
0.5
—
—
ns
tCO_MSO
MCLK to MSO delay
—
—
—
12
ns
fCCLK
CCLK input clock frequency
—
—
—
120
MHz
tCCLKH
CCLK input clock pulse width HIGH
—
3.5
—
—
ns
tCCLKL
CCLK input clock pulse width LOW
—
3.5
—
—
ns
tVMC_SLAVE
Time from rising edge of INITN to Slave CCLK
driven
—
50
—
—
ns
tVMC_MASTER
CCLK input clock duty cycle
—
40
—
60
%
tSU_SSI
SSI to CCLK setup time
—
3.2
—
—
ns
tHD_SSI
SSI to CCLK hold time
—
1.9
—
—
ns
Master SPI
Slave SPI
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FPGA-DS-02078-1.0
125
Certus-NX Family
Data Sheet
Symbol
Parameter
Device
Min
Typ.
Max
Unit
tCO_SSO
tEN_SSO
CCLK falling edge to valid SSO output
—
—
—
30
ns
CCLK falling edge to SSO output enabled
—
—
—
30
ns
tDIS_SSO
CCLK falling edge to SSO output disabled
—
—
—
30
ns
tHIGH_SCSN
SCSN HIGH time
—
74
—
—
ns
tSU_SCSN
SCSN to CCLK setup time
—
3.5
—
—
ns
tHD_SCSN
SCSN to CCLK hold time
—
1.6
—
—
ns
fSCL_I2C
SCL input clock frequency for I2C
—
—
—
1
MHz
fSCL_I3C
SCL input clock frequency for I3C
—
—
—
12
MHz
tSCLH_I2C
SCL input clock pulse width HIGH for I2C
—
400
—
—
ns
tSCLL_I2C
SCL input clock pulse width LOW for
I 2C
—
400
—
—
ns
tSU_SDA_I2C
SDA to SCL setup time for I2C
—
250
—
—
ns
I2C/I3C
I 2C
tHD_SDA_I2C
SDA to SCL hold time for
—
50
—
—
ns
tSU_SDA_I3C
SDA to SCL setup time for I3C
—
30
—
—
ns
tHD_SDA_I3C
SDA to SCL hold time for I3C
—
30
—
—
ns
tCO_SDA
SCL falling edge to valid SDA output
—
—
—
200
ns
tEN_SDA
SCL falling edge to SDA output enabled
—
—
—
200
ns
tDIS_SDA
SCL falling edge to SDA output disabled
—
—
—
200
ns
Last configuration clock cycle to DONE going
HIGH
—
—
—
60
µs
LIFCL-40
—
6.245
M
cycles
LIFCL-17
—
2.321
Config clock to user I/O enabled
—
150
—
—
M
cycles
ns
Master MCLK to Hi-Z
—
—
—
2.5
µs
Wake-Up Timing
tDONE_HIGH
tFIO_EN
tIOEN
tMCLKZ
*Note:
User I/O enabled in Fast I/O Mode
fMCLK has a dependency on HFOSC and is 1/3 of fCLKHF.
PROGRAMN
Figure 4.12. Master SPI POR/REFRESH Timing
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126
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
PROGRAMN
Figure 4.13. Slave SPI/I2C/I3C POR/REFRESH Timing
Figure 4.14. Master SPI PROGRAMN Timing
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FPGA-DS-02078-1.0
127
Certus-NX Family
Data Sheet
Figure 4.15. Slave SPI/I2C/I3C PROGRAMN Timing
Figure 4.16. Master SPI Configuration Timing
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128
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
Figure 4.17. Slave SPI Configuration Timing
Figure 4.18. I2C /I3C Configuration Timing
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FPGA-DS-02078-1.0
129
Certus-NX Family
Data Sheet
Figure 4.19. Master SPI Wake-Up Timing
Figure 4.20. Slave SPI/I2C/I3C Wake-Up Timing
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130
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
4.27. JTAG Port Timing Specifications
Table 4.38. JTAG Port Timing Specifications
Symbol
Parameter
Min
Typ.
Max
Units
fMAX
tBTCPH
tBTCPL
tBTS
tBTH
tBTRF
tBTCO
tBTCODIS
tBTCOEN
tBTCRS
tBTCRH
TCK clock frequency
TCK clock pulse width high
TCK clock pulse width low
TCK TAP setup time
TCK TAP hold time
TAP controller TDO rise/fall time*
TAP controller falling edge of clock to valid output
TAP controller falling edge of clock to valid disable
TAP controller falling edge of clock to valid enable
BSCAN test capture register setup time
BSCAN test capture register hold time
—
20
20
5
5
100
—
—
—
8
25
—
—
—
—
—
—
—
—
—
—
—
25
—
—
—
—
—
14
14
14
—
—
MHz
ns
ns
ns
ns
mV/ns
ns
ns
ns
ns
ns
—
—
—
—
—
—
25
25
25
ns
ns
ns
tBUTCO
BSCAN test update register, falling edge of clock to valid output
tBTUODIS
BSCAN test update register, falling edge of clock to valid disable
tBTUPOEN
BSCAN test update register, falling edge of clock to valid enable
*Note: Based on default I/O setting of slow slew rate.
TMS
TDI
tBTS
tBTCPH
tBTH
tBTCP
tBTCPL
TCK
tBTCO
tBTCOEN
TDO
V a lid D a ta
tBTCRS
Data to be
Captured
from I/O
V a lid D a ta
tBTCRH
Data Captured
tBTUPOEN
Data to be
driven out
to I/O
tBTCODIS
tBUTCO
V a lid D a ta
tBTUODIS
V a lid D a ta
Figure 4.21. JTAG Port Timing Waveforms
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FPGA-DS-02078-1.0
131
Certus-NX Family
Data Sheet
4.28. Switching Test Conditions
Figure 4.22 shows the output test load that is used for AC testing. The specific values for resistance, capacitance,
voltage, and other test conditions are listed in Table 4.39.
VT
R1
Test Point
DUT
R2
CL*
*CL Includes Test Fixture and Probe Capacitance
Figure 4.22. Output Test Load, LVTTL and LVCMOS Standards
Table 4.39. Test Fixture Required Components, Non-Terminated Interfaces
Test Condition
LVTTL and other LVCMOS settings (L ≥ H, H ≥ L)
LVCMOS 2.5 I/O (Z ≥ H)
R1
R2
CL
0 pF
1 MΩ
1 MΩ
0 pF
Timing Ref.
LVCMOS 3.3 = 1.5 V
LVCMOS 2.5 = VCCIO/2
LVCMOS 1.8 = VCCIO/2
LVCMOS 1.5 = VCCIO/2
LVCMOS 1.2 = VCCIO/2
VCCIO/2
0 pF
100
0 pF
LVCMOS 2.5 I/O (L ≥ Z)
100
0 pF
Note: Output test conditions for all other interfaces are determined by the respective standards.
LVCMOS 2.5 I/O (Z ≥ L)
LVCMOS 2.5 I/O (H ≥ Z)
VT
—
—
—
—
—
—
VCCIO/2
VOH – 0.10
VCCIO
—
VOL + 0.10
VCCIO
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132
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
5. Pinout Information
5.1. Signal Descriptions*
Signal Name
Power and GND
VSS
VSSSD
VSSADC
VCC, VCCECLK
Bank
Type
Description
—
—
—
—
GND
GND
GND
Power
Ground for internal FPGA logic and I/O
Ground for the SerDes block
Ground for ADC block
VCCAUXA
—
Power
VCCAUX
—
Power
VCCAUXHx
3–5
Power
VCCIOx
0–7
Power
—
—
—
—
Power
Power
Power
Power
1
Input
LVCMOS input pin. This input selects the JTAG shared GPIO to be used
for JTAG
0 = GPIO
1 = JTAG
ADC_REFA, ADC_REFB
—
Input
ADC reference voltage, for each of the 2 ADC converters. If not used,
tie to ground.
ADC_DP/NA, ADC_DP/NB
—
Input
Dedicated ADC input pairs, for each of the 2 ADC converters. If not
used, tie to ground.
VCCADC18
VCCSD0
VCCPLLSD0
VCCAUXSD
Dedicated Pins
Dedicated Configuration I/O Pin
JTAG_EN
Power supply pins for core logic. VCC is connected to 1.0 V (nom.)
supply voltage. Power On Reset (POR) monitors this supply voltage.
Auxiliary power supply pin for internal analog circuitry. This supply is
connected to 1.8 V (nom.) supply voltage. POR monitors this supply
voltage.
Auxiliary power supply pin for I/O Bank 0, Bank 1, Bank 2, Bank 6, and
Bank 7. This supply is connected to 1.8 V (nom.) supply voltage, and is
used for generating stable drive current for the I/O.
Auxiliary power supply pin for I/O Bank 3, Bank 4, and Bank 5. This
supply is connected to 1.8 V (nom.) supply voltage, and is used for
generating stable current for the differential input comparators and
stable drive current for the I/O.
Power supply pins for I/O bank x.
For x = 0, 1, 2, 6, and 7, VCCIO can be connected to (nom.) 1.2 V, 1.5 V,
1.8 V, 2.5 V, or 3.3 V.
For x = 3, 4, and 5, VCCIO can be connected to (nom.) 1.0 V, 1.2 V, 1.35
V, 1.5 V, or 1.8 V.
There are dedicated and shared configuration pins in banks 0 and 1.
POR monitors these banks supply voltages.
1.8 V (nom.) power supply for the ADC block.
1.0 V (nom.) power supply for the SerDes block.
1.8 V (nom.) power supply for the PLL in the SerDes block.
1.8 V (nom.) auxiliary power supply for the SerDes block.
Dedicated ADC I/O Pins
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FPGA-DS-02078-1.0
133
Certus-NX Family
Data Sheet
Signal Name
Dedicated SerDes I/O Pins
Bank
Type
Description
SD0_RXDP/N
—
Input
SerDes Data Differential Input Pairs
SD0_TXDP/N
—
Output
SD0_REFCLKP/N
—
Input
SerDes Reference Clock Differential Input Pairs
SD0_REXT
—
Input
SerDes External Reference Resistor Input. Resistor connects between
to this pin and SD0_REFRET pin. This is used to adjust the on-chip
differential termination impedance, based on the external resistance
value:
REXT = 909 Ω, RDIFF = 80 Ω
REXT = 976 Ω, RDIFF = 85 Ω
REXT = 1.02 kΩ, RDIFF = 90 Ω
REXT = 1.15 kΩ, RDIFF = 100 Ω
SD0_REFRET
—
Input
SerDes Reference Return Input. These pins should be AC coupled to the
VCCPLLSD0 supply.
SerDes Data Differential Output Pairs
Misc Pins
NC
—
No connect.
RESERVED
—
This pin is reserved and should not be connected to anything on the
board.
General Purpose I/O Pins
P[T/B/L/R] [Number]_[A/B]
T=0
R = 1, 2
B = 3, 4, 5
L = 6. 7
Input,
Output,
Bi-Dir
Programmable User I/O:
[T/B/L/R] indicates the package pin/ball is in T (Top), B (Bottom), L
(Left), or R (Right) edge of the device.
[Number] identifies the PIO [A/B] pair.
[A/B] shows the package pin/ball is A or B signal in the pair. PIO A and
PIO B are grouped as a pair.
Each A/B pair in the bottom banks supports true differential input and
output buffers. When configured as differential input, differential
termination of 100 Ω can be selected.
Each A/B pair in the top, left and right banks does not support true
differential input or output buffer. It supports all single-ended inputs
and outputs, and can be used for emulated differential output buffer.
Some of these user-programmable I/O are used during configuration,
depending on the configuration mode. You need to make appropriate
connection on the board to isolate the 2 different functions
before/after configuration.
Some of these user-programmable I/O are shared with special function
pins. These pins, when not used as special purpose pins, can be
programmed as I/O for user logic.
During configuration the user-programmable I/O are tri-stated with an
internal weak pull-down resistor enabled. If any pin is not used (or not
bonded to a package pin), it is tri-stated and default to have weak pulldown enabled after configuration.
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134
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
Signal Name
Bank
Type
Description
Shared Configuration Pins1, 2
1. These pins can be used for configuration during configuration mode. When configuration is completed, these pins can be
used as GPIO, or shared function in GPIO. When these pins are used in dual function, you need to isolate the signal paths for
the dual functions on the board.
2. The pins used are defined by the configuration modes detected. Slave SPI or I2C/I3C modes are detected during slave
activation. Pins that are not used in the configuration mode selected are tri-stated during configuration, and can connect
directly as GPIO in user’s function.
PRxxx/SDA/USER_SDA
1
Input,
Output,
Bi-Dir
Configuration:
I2C/I3C Mode: SDA signal
User Mode:
PRxxx: GPIO
User_SDA: SDA signal for I2C/I3C interface
PRxxx/SCL/USER_SCL
1
Input,
Output,
Bi-Dir
Configuration:
I2C/I3C Mode: SCL signal
User Mode:
PRxxx: GPIO
User_SDA: SCL signal for I2C/I3C interface
PRxxx/TDO/SSO
1
Input,
Output,
Bi-Dir
Configuration:
Slave SPI Mode: Slave Serial Output
User Mode:
PRxxx: GPIO
TDO: When JTAG_EN = 1, used as TDO signal for JTAG
PRxxx/TDI/SSI
1
Input,
Output,
Bi-Dir
Configuration:
Slave SPI Mode: Slave Serial Input
User Mode:
PRxxx: GPIO
TDI: When JTAG_EN = 1, used as TDI signal for JTAG
PRxxx/TMS/SCSN
1
Input,
Output,
Bi-Dir
PRxxx/TCK/SCLK
1
Input,
Output,
Bi-Dir
PTxxx/MCSNO
0
Input,
Output,
Bi-Dir
Configuration:
Slave SPI Mode: Slave Chip Select
User Mode:
PRxxx: GPIO
TMS: When JTAG_EN = 1, used as TMS signal for JTAG
Configuration:
Slave SPI Mode: Slave Clock Input
User Mode:
PRxxx: GPIO
TCK: When JTAG_EN = 1, used as TCK signal for JTAG
Configuration:
Master SPI Mode: Chip Select Output
User Mode:
PTxxx: GPIO
PTxxx/MD3
0
Input,
Output,
Bi-Dir
Configuration:
Master Quad SPI Mode: I/O3
User Mode:
PTxxx: GPIO
PTxxx/MD2
0
Input,
Output,
Bi-Dir
Configuration:
Master Quad SPI Mode: I/O2
User Mode:
PTxxx: GPIO
© 2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02078-1.0
135
Certus-NX Family
Data Sheet
Signal Name
PTxxx/MSI/MD1
Bank
0
Type
PTxxx/MSO/MD0
0
Input,
Output,
Bi-Dir
Configuration:
Master SPI Mode: Master Serial Output
Master Quad SPI Mode: I/O0
User Mode:
PTxxx: GPIO
PTxxx/MCSN/PCLKT0_1
0
Input,
Output,
Bi-Dir
Configuration:
Master SPI Mode: Master Chip Select Output
User Mode:
PTxxx: GPIO
PCLKT0_0: Top PCLK Input
PTxxx/MCLK/PCLKT0_0
0
Input,
Output,
Bi-Dir
Configuration:
Master SPI Mode: Master Clock Output
User Mode:
PTxxx: GPIO
PCLKT0_1: Top PCLK Input
PTxxx/PROGRAMN
0
Input,
Output,
Bi-Dir
Configuration:
PROGRAMN: Initiate configuration sequence when asserted LOW.
User Mode:
PTxxx: GPIO
PTxxx/INITN
0
Input,
Output,
Bi-Dir
Configuration:
INITN: Open Drain I/O pin. This signal is driven to LOW when
configuration sequence is started, to indicate the device is in
initialization state. This signal is released after initialization is
completed, and the configuration download can start. You can keep
drive this signal LOW to delay configuration download to start.
User Mode:
PTxxx: GPIO
PTxxx/DONE
0
Input,
Output,
Bi-Dir
Configuration:
DONE: Open Drain I/O pin. This signal is driven to LOW during
configuration time. It is released to indicate the device has completed
configuration. You can keep drive this signal LOW to delay the device to
wake up from configuration.
User Mode:
PTxxx: GPIO
Input,
Output,
Bi-Dir
Description
Configuration:
Master SPI Mode: Master Serial Input
Master Quad SPI Mode: I/O1
User Mode:
PTxxx: GPIO
Shared User GPIO Pins1, 2, 3, 4
1. Shared User GPIO pins are pins that can be used as GPIO, or functional pins that connect directly to specific functional
blocks, when device enters into User Mode.
2. Declaring on assigning the pin as GPIO or specific functional pin is done by configuration bitstream, except JTAG pins.
3. JTAG pins are controlled by JTAG_EN signal. When JTAG_EN = 1, the pins are used for JTAG interface. When JTAG = 0, the
pins are used as GPIO or specific functional pin defined by configuration bitstream.
4. Refer to package pin file.
Shared JTAG Pins
PRxxx/TDO/ yyyy
1
Input,
Output,
Bi-Dir
User Mode:
PRxxx: GPIO
TDO: When JTAG_EN = 1, used as TDO signal for JTAG
yyyy: Other possible selectable specific functional
© 2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
136
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
Signal Name
PRxxx/TDI/yyyy
Bank
1
Type
Input,
Output,
Bi-Dir
Description
User Mode:
PRxxx: GPIO
TDI: When JTAG_EN = 1, used as TDI signal for JTAG
yyyy: Other possible selectable specific functional
PRxxx/TMS/ yyyy
1
Input,
Output,
Bi-Dir
User Mode:
PRxxx: GPIO
TMS: When JTAG_EN = 1, used as TMS signal for JTAG
yyyy: Other possible selectable specific functional
PRxxx/TCK/ yyyy
1
Input,
Output,
Bi-Dir
User Mode:
PRxxx: GPIO
TCK: When JTAG_EN = 1, used as TCK signal for JTAG
Yyyy: Other possible selectable specific functional
Shared CLOCK Pins 1
1. Some PCLK pins can also be used as GPLL reference clock input pin. Refer to Nexus sysCLOCK PLL Design and Usage Guide
(FPGA-TN-02095).
PBxxx/PCLK[T,C][3,4,5]_[03]/yyyy
3, 4, 5
Input,
Output,
Bi-Dir
User Mode:
PBxxx: GPIO
PCLK: Primary Clock or GPLL Refclk signal
[T,C] = True/Complement when using differential signaling
[3,4,5] = Bank
[0-3] Up to 4 signals in the bank
yyyy: Other possible selectable specific functional
User Mode:
PTxxx: GPIO
PCLKT: Primary Clock or GPLL Refclk signal (Only Single Ended)
[0-1] Up to 2 signals in the bank
yyyy: Other possible selectable specific functional
PTxxx/PCLKT0_[0-1]/yyyy
0
Input,
Output,
Bi-Dir
PRxxx/PCLKT[1,2]_[0-2]/yyyy
1, 2
Input,
Output,
Bi-Dir
User Mode:
PRxxx: GPIO
PCLKT: Primary Clock or GPLL Refclk signal (Only Single Ended)
[0-2] Up to 3 signals in the bank
yyyy: Other possible selectable specific functional
PLxxx/PCLKT[6,7]_[0-2]/yyyy
6, 7
Input,
Output,
Bi-Dir
User Mode:
PLxxx: GPIO
PCLKT: Primary Clock or GPLL Refclk signal (Only Single Ended)
[0-2] Up to 3 signals in the bank
yyyy: Other possible selectable specific functional
PBxxx/LRC_GPLL[T,C]_IN/yyyy
3
Input,
Output,
Bi-Dir
User Mode:
PBxxx: GPIO
LRC_GPLL: Lower Right GPLL Refclk signal (PLLCK)
[T,C] = True/Complement when using differential signaling
yyyy: Other possible selectable specific functional
PBxxx/LLC_GPLL[T,C]_IN/yyyy
5
Input,
Output,
Bi-Dir
User Mode:
PBxxx: GPIO
LLC_GPLL: Lower Left GPLL Refclk signal (PLLCK)
[T,C] = True/Complement when using differential signaling
yyyy: Other possible selectable specific functional
© 2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02078-1.0
137
Certus-NX Family
Data Sheet
Signal Name
PLxxx/ULC_GPLLT_IN/yyyy
Input,
Output,
Bi-Dir
Description
User Mode:
PLxxx: GPIO
ULC_GPLL: Upper Left GPLL Refclk signal (Only Single Ended) (PLLCK)
yyyy: Other possible selectable specific functional
1
Input,
Output,
Bi-Dir
User Mode:
PRxxx: GPIO
yyyy: Other possible selectable specific functional
Shared VREF Pins
PBxxx/VREF[3,4,5]_[1-2]/yyyy
3, 4, 5
Input,
Output,
Bi-Dir
User Mode:
PBxxx: GPIO
VREF: Reference Voltage for DDR memory function
[3,4,5] = Bank
[1-2] Up to VREFs for each bank
yyyy: Other possible selectable specific functional
Shared ADC Pins
PBxxx/ADC_C[P,N]nn/yyyy
3, 4, 5
Input,
Output,
Bi-Dir
User Mode:
PBxxx: GPIO
ADC_C: ADC Channel Inputs
[P,N] = Positive or Negative Input
nn = ADC Channel number (0 – 15)
yyyy: Other possible selectable specific functional
3, 5
Input,
Output,
Bi-Dir
User Mode:
PBxxx: GPIO
COMP: Differential Comparator Input
[P,N] = Positive or Negative Input
[1-3] = Input to Comparators 1-3
yyyy: Other possible selectable specific functional
3, 5
Input,
Output,
Bi-Dir
User Mode:
PBxxx: GPIO
SGMII_RX: Differential SGMII RX Inputs
[P,N] = Positive or Negative Input
[0-1] = Input to SGMII RX0 or RX1
yyyy: Other possible selectable specific functional
PRxxx/yyyy
Shared Comparator Pins
PBxxx/COMP[1-3][P,N]/yyyy
Shared SGMII Pins
PBxxx/SGMII_RX[P,N][01]/yyyy
*Note:
Bank
7
Type
Not all signals are available as external pins in all packages. Refer to the Pinout List file for various package details.
© 2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
138
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
5.2. Pin Information Summary
Certus-NX Family
Pin Information Summary
LFD2NX-17
LFD2NX-40
csfBGA121
csfBGA121
caBGA196
caBGA256
Bank 0
Bank 1
Bank 2
General
Bank 3
Purpose
Inputs/Outputs
Bank 4
per Bank
Bank 5
Bank 6
Bank 7
Total Single-Ended User I/O
—
—
—
—
—
—
—
—
—
12
11
—
32
16
10
—
—
81
12
17
20
32
16
10
25
18
150
12
21
28
32
32
10
28
22
185
Bank 0
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
Bank 6
Bank 7
0
0
0
—
—
—
0
0
—
0
0
0
32
16
10
0
0
58
0
0
0
32
16
10
0
0
58
0
0
0
32
32
10
0
0
74
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3
1
1
3
1
1
1
1
2
1
1
—
—
1
1
—
18
5
1
2
3
—
1
1
1
2
1
1
1
1
—
—
1
21
5
1
2
3
1
1
1
1
1
1
1
1
1
1
1
1
23
User I/O Pins
Differential
Input / Output
Pairs
Total Differential I/O
Power Pins
VCC, VCCECLK
VCCAUXA
VCCAUX
VCCAUXHx
VCCAUXSD
VCCIO
VCCSD0
VCCPLLSD0
VCCADC18
Total Power Pins
Bank 0
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
Bank 6
Bank 7
© 2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02078-1.0
139
Certus-NX Family
Data Sheet
Pin Information Summary
GND Pins
VSS
VSSADC
VSSSD
Total GND Pins
Dedicated Pins
Dedicated ADC Channels
(pairs)
Dedicated ADC Reference
Voltage Pins
Dedicated Misc Pins
JTAGEN
NC
RESERVED
Total Dedicated Pins
Shared Pins
Bank 0
Bank 1
Bank 2
Shared
Bank 3
Configuration
Bank 4
Pins
Bank 5
Bank 6
Bank 7
Bank 0
Bank 1
Bank 2
Bank 3
Shared JTAG
Pins
Bank 4
Bank 5
Bank 6
Bank 7
Bank 0
Bank 1
Bank 2
Bank 3
Shared PCLK
Pins
Bank 4
Bank 5
Bank 6
Bank 7
LFD2NX-17
csfBGA121
csfBGA121
LFD2NX-40
caBGA196
caBGA256
—
—
—
—
9
—
5
14
17
1
—
18
27
1
5
33
—
—
—
0
—
—
—
0
1
—
—
—
1
—
—
1
1
—
—
1
1
—
—
1
—
—
0
0
0
0
0
0
0
4
0
0
0
0
0
0
—
—
—
—
—
—
—
—
10
6
0
0
0
0
0
0
0
4
0
0
0
0
0
0
2
3
—
8
4
8
—
—
10
6
0
0
0
0
0
0
0
4
0
0
0
0
0
0
2
3
3
8
4
8
3
3
10
6
0
0
0
0
0
0
0
4
0
0
0
0
0
0
2
3
3
8
8
8
3
3
© 2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
140
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
Pin Information Summary
Shared GPLL
Pins
Shared VREF
Pins
Shared ADC
Channels (pairs)
Shared
Comparator
Channels (pairs)
Shared SGMII
Channels (pairs)
LFD2NX-17
csfBGA121
csfBGA121
LFD2NX-40
caBGA196
caBGA256
Bank 0
0
0
0
0
Bank 1
—
—
—
0
Bank 2
0
0
0
0
Bank 3
—
2
2
2
Bank 4
—
—
—
0
Bank 5
—
2
2
2
Bank 6
0
0
0
0
Bank 7
—
—
2
2
Bank 0
0
0
0
0
Bank 1
0
0
0
0
Bank 2
0
0
0
0
Bank 3
—
2
2
2
Bank 4
—
1
1
2
Bank 5
—
2
2
2
Bank 6
0
0
0
0
Bank 7
0
0
0
0
Bank 0
0
0
0
0
Bank 1
0
0
0
0
Bank 2
0
0
0
0
Bank 3
—
12
12
12
Bank 4
—
—
—
0
Bank 5
—
4
4
4
Bank 6
0
0
0
0
Bank 7
0
0
0
0
Bank 0
0
0
0
0
Bank 1
0
0
0
0
Bank 2
0
0
0
0
Bank 3
—
3
3
3
Bank 4
—
—
—
0
Bank 5
—
3
3
3
Bank 6
0
0
0
0
Bank 7
0
0
0
0
Bank 0
0
0
0
0
Bank 1
0
0
0
0
Bank 2
0
0
0
0
Bank 3
—
—
—
0
Bank 4
0
0
0
0
Bank 5
—
1
1
1
Bank 6
0
0
0
0
Bank 7
0
0
0
0
© 2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02078-1.0
141
Certus-NX Family
Data Sheet
6. Ordering Information
Lattice provides a wide variety of services for its products including custom marking, factory programming, known good
die, and application specific testing. Contact your local sales representatives for more details.
6.1. Certus-NX Part Number Description
LFD2NX - 40 - X XXXX X
Grade
C = Commercial
I = Industrial
A = Automotive
Device Family
Certus-NX FPGA
Logic Capacity
40 = 39k Logic Cells
Package
MG121 = 121-ball csfBGA
BG196 = 196-ball caBGA
BG256 = 256-ball caBGA
Speed (same number for HP and LP)
7 = Slowest
8
9 = Fastest
LFD2NX - 17 - X XXXX X
Device Family
Certus-NX FPGA
Logic Capacity
17 = 17k Logic Cells
Grade
C = Commercial
I = Industrial
Package
MG121 = 121-ball csfBGA
Speed (same number for HP and LP)
7 = Slowest
8
9 = Fastest
© 2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
142
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
6.2. Ordering Part Numbers
6.2.1. Commercial
Part Number
Speed
Package
Pins
Temp.
Logic Cells (k)
–7
–8
–9
–7
–8
–9
–7
–8
–9
–7
–8
–9
Lead free csfBGA
Lead free csfBGA
Lead free csfBGA
Lead free csfBGA
Lead free csfBGA
Lead free csfBGA
Lead free caBGA
Lead free caBGA
Lead free caBGA
Lead free caBGA
Lead free caBGA
Lead free caBGA
121
121
121
121
121
121
196
196
196
256
256
256
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
17
17
17
39
39
39
39
39
39
39
39
39
Part Number
LFD2NX-17-7MG121I
LFD2NX-17-8MG121I
LFD2NX-17-9MG121I
LFD2NX-40-7MG121I
LFD2NX-40-8MG121I
Speed
–7
–8
–9
–7
–8
Package
Lead free csfBGA
Lead free csfBGA
Lead free csfBGA
Lead free csfBGA
Lead free csfBGA
Pins
121
121
121
121
121
Temp.
Industrial
Industrial
Industrial
Industrial
Industrial
Logic Cells (k)
17
17
17
39
39
LFD2NX-40-9MG121I
LFD2NX-40-7BG196I
LFD2NX-40-8BG196I
LFD2NX-40-9BG196I
LFD2NX-40-7BG256I
LFD2NX-40-8BG256I
LFD2NX-40-9BG256I
–9
–7
–8
–9
–7
–8
–9
Lead free csfBGA
Lead free caBGA
Lead free caBGA
Lead free caBGA
Lead free caBGA
Lead free caBGA
Lead free caBGA
121
196
196
196
256
256
256
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
39
39
39
39
39
39
39
Speed
–7
–7
–7
Package
Lead free csfBGA
Lead free csfBGA
Lead free caBGA
Pins
121
121
256
Temp.
Automotive
Automotive
Automotive
Logic Cells (k)
17
39
39
LFD2NX-17-7MG121C
LFD2NX-17-8MG121C
LFD2NX-17-9MG121C
LFD2NX-40-7MG121C
LFD2NX-40-8MG121C
LFD2NX-40-9MG121C
LFD2NX-40-7BG196C
LFD2NX-40-8BG196C
LFD2NX-40-9BG196C
LFD2NX-40-7BG256C
LFD2NX-40-8BG256C
LFD2NX-40-9BG256C
6.2.2. Industrial
6.2.3. Automotive
Part Number
LFD2NX-17-7MG121A
LFD2NX-40-7MG121A
LFD2NX-40-7BG256A
© 2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02078-1.0
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Data Sheet
References
For more information, refer to the following documents:
sysCLOCK PLL Design and Usage Guide for Nexus Platform (FPGA-TN-02095)
sysDSP Usage Guide for Nexus Platform (FPGA-TN-02096)
sysCONFIG Usage Guide for Nexus Platform (FPGA-TN-02099)
sysI/O Usage Guide for Nexus Platform (FPGA-TN-02067)
Soft Error Detection (SED)/Correction (SEC) Usage Guide for Nexus Platform (FPGA-TN-02076)
Memory Usage Guide for Nexus Platform (FPGA-TN-02094)
ADC Usage Guides for Nexus Platform (FPGA-TN-02129)
Certus-NX High-Speed I/O Interface (FPGA-TN-02216)
Power Management and Calculation for Certus-NX Devices (FPGA-TN-02214)
Certus-NX 40K Pinout File (FPGA-SC-02004)
Lattice Memory Mapped Interface and Lattice Interrupt Interface User Guide (FPGA-UG-02039)
sub-LVDS Signaling Using Lattice Devices (FPGA-TN-02028)
Multi-Boot Usage Guide for Nexus Platform (FPGA-TN-02145)
TransFR Usage Guide for Nexus Platform (FPGA-TN-02173)
I2C Hardened IP Usage Guide for Nexus Platform (FPGA-TN-02142)
For package information, refer to the following documents:
PCB Layout Recommendations for BGA Packages (FPGA-TN-02024)
Solder Reflow Guide for Surface Mount Devices (FPGA-TN-02041)
Thermal Management (FPGA-TN-02044)
Package Diagrams (FPGA-DS-02053)
High Speed PCB Design Considerations (FPGA-TN-02148)
Advanced Configuration Security Usage Guide for Nexus Platform (FPGA-TN-02176)
Hardware Checklist (FPGA-TN-02151)
For further information on interface standards, refer to the following websites:
JEDEC Standards (LVTTL, LVCMOS, SSTL) – www.jedec.org
PCI – www.pcisig.com
© 2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
144
FPGA-DS-02078-1.0
Certus-NX Family
Data Sheet
Revision History
Revision 1.0, November 2021
Section
Change Summary
All
Production release.
© 2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02078-1.0
145
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