LFE3-35EA-VERSA-EVN

 LatticeECP3 Versa Evaluation Board User’s Guide July 2013 Revision: EB62_01.6  LatticeECP3 Versa Evaluation Board User’s Guide Introduction The LatticeECP3™ Versa Evaluation Board allows designers to investigate and experiment with the features of the LatticeECP3 Field-Programmable Gate Array. The features of the LatticeECP3 Versa Evaluation Board can assist engineers with rapid prototyping and testing of their specific designs. The LatticeECP3 Versa Evaluation Board is part of the LatticeECP3 Versa Development Kit. The guide is intended to be referenced in conjunction with demo user’s guides to demonstrate the LatticeECP3 FPGA. Figure 1. LatticeECP3 Versa Evaluation Board, Top Side GSRn & LED PROGRAMn Push-buttons Display SERDES Test DDR3 SMA Connectors Memory Expansion Connectors User Switches Status LEDs USB Programming J3 – JTAG Interface J13 – JTAG Interface 10/100/1000 RJ-45 Connections On-Board Clock Management SPI Flash Configuration Memory PCI Express x1 Features • Half-length PCI Express form-factor – Allows demonstration of PCI Express x1 interconnection • Electrical testing of one full-duplex SERDES channel via SMA connections • USB-B connection for UART and device programming • Two RJ45 interfaces to 10/100/1000 Ethernet to GMII • On-board Boot Flash – 64M Serial SPI Flash • DDR3-1333 memory components (64Mb/x16) • Expansion mezzanine interconnection for prototyping • 14-segment alpha-numeric display • Switches, LEDs and displays for demo purposes • ispVM™ programming support • On-board reference clock sources 2 12V DC Power Input LatticeECP3 Versa Evaluation Board User’s Guide The contents of this user’s guide include top-level functional descriptions of the various portions of the evaluation board, descriptions of the on-board connectors, diodes and switches and a complete set of schematics. Caution: The LatticeECP3 Versa Evaluation Board contains ESD-sensitive components. ESD safe practices should be followed while handling and using the evaluation board. LatticeECP3 Device This board features a LatticeECP3 FPGA with a 1.2V core supply. It can accommodate all pin-compatible LatticeECP3 devices in the 484-ball fpBGA (1mm pitch) package. A complete description of this device can be found in the LatticeECP3 Family Data Sheet. Note: The connections referenced in this document refer to the LFE3-35EA-8FN484C device. Applying Power to the Board The LatticeECP3 Versa Evaluation Board is ready to power on. The board can be supplied with power from a PCI Express host system or standalone with an external wall power module. The 12V DC input power source is fused with a surface mounted fuse, as noted in Table 1. Table 1. Board Power Supply Fuses – (See Appendix B, Figure 12) Fuse Designator F1 Description 12V Input Supply Fuse The board may be plugged into a host PC. Only plug the board into a PCI Express slot when the system is powered off. Once inserted, the PC can be safely powered on. Using the evaluation board outside of a PC chassis supply requires the factory-supplied wall supply module. Use of other supplies is not suggested. GME Technology’s GFP181DA-1215B-1 (or equivalent) is provided with the LatticeECP3 Versa Development Kit. Figure 2. Power Distribution Scheme – (See Appendix B, Figure 12) EN LDO SW 12_0V (5A fused) Power Status LED D13 SERDES 1_2V, +1.2V, 1A, Power Status LED D12 2_5V, +2.5V, 1.1 A, Power Status LED D31 EN SW 3_3V, +3.3V, 1.35 A, Power Status LED D9 SW 1_5V, +1.5V, 1.1 A, Power Status LED D11 EN SW VCC_CORE, +1.2V, 1.35 A, Power Status LED D10 Programming/FPGA Configuration The LatticeECP3 Versa Evaluation Board has a built-in download controller for programming the LatticeECP3 FPGA. The built-in module consists of a USB Type-B connector and a USB UART device. To use the built-in download cable, simply connect a standard USB cable (a USB-B to USB-A cable is included with the LatticeECP3 Versa Development Kit) from J2 to your PC (with ispVM System software installed). The USB hub on the PC will detect the addition of the USB function, making the built-in cable available for use with the ispVM System software. The USB cable is connected in parallel to J3. 3 LatticeECP3 Versa Evaluation Board User’s Guide Alternate ispVM Download Interface J3 is a 1x10 100mil header that is provided for use with an external Lattice download cable (available separately). A USB download cable can be attached to the board using J3 to interface with the FPGA (U1). Note: Resistors R38, R33, R32 and R36 need to be removed. A separate header is provided to interface to a download cable for the ispClock™5406A clock device (U13). U13 is not interfaced to the built-in download interface. U13 is factory-programmed for use with the reference designs and should only be altered for customized designs. A 10-pin JTAG connector is used in conjunction with the ispVM USB download cable to program and control the device. A separate 10-pin header (J14) is provided for programming U13. Table 2. ispVM JTAG Connector Pinout (J3 and J14) – (See Appendix B, Figure 5) Pin Function Color 1 PWR Red 2 TDO Brown 3 TDI Orange 4 N/C — 5 N/C — 6 TMS Purple 7 GND Black 8 TCK White 9 N/C — 10 N/C — ispVM Requirements Note: An ispDOWNLOAD™ cable is included with Lattice Diamond® design software. This cable is not needed for the typical use of this board since it includes the built-in download module and only requires the USB cable included with the board. Standalone ispVM download cables may be purchased separately from Lattice. After initial board setup, use the following procedure to program the board. Instructions assume that ispVM software has been installed on a local PC. Requirements: • PC with ispVM System 18.0 (or later) programming software, installed with appropriate drivers (USB driver for USB cable, Windows 7/XP/2000/NT parallel port driver for ispDOWNLOAD cable). Note: An option to install these drivers is included as part of the ispVM System setup. • ispDOWNLOAD cable (pDS4102-DL2A, HW7265-DL3A, HW-USB-1A, etc.). Required only for alternative FPGA programming and ispClock5406A reprogramming. 4 LatticeECP3 Versa Evaluation Board User’s Guide Board Programming Configuration Status Indicators (see Appendix B, Figure 13) Figure 3. LatticeECP3 Status LEDs and Push-button Controls The LEDs indicate the configuration status of the LatticeECP3 FPGA. • D17 (red) illuminated indicates that programming was aborted or reinitialized, driving the INITN output low. • D20 (green) illuminated indicates the successful completion of configuration by releasing the open collector DONE output pin. • D19 (red) illuminated indicates that PROGRAMN is low. • D18 (red) illuminated indicates that GSRN is low. PROGRAMN and GSRN These push-button switches assert/de-assert the logic levels on PROGRAMN (SW2) and GSRN (SW1). Depressing the button drives a logic level “0” to the device. Programming Serial SPI Flash Memory A serial SPI (16-pin TSSOP, 64M) Flash memory device (U8) is on-board for non-volatile configuration memory storage. A STMicro M25P64VMF16 device is populated on-board. The Serial SPI Flash memory device can be configured easily via its JTAG port. This mode enables the FPGA to be programmed at power-up or assertion of PROGRAMN with a bitstream stored in the memory device. 1. Connect the LatticeECP3 Versa Evaluation Board. 2. In the dialog box, select SPI Flash Programming Mode in the Device Access Option pull-down menu. 5 LatticeECP3 Versa Evaluation Board User’s Guide Figure 4. Device Information Dialog Screen 3. The SPI Serial Flash Device dialog box will open. In this box, select SPI Flash Erase, Program, Verify in the Operation pull-down menu. 4. Select SPI Serial Flash in the Device Family pull-down menu, STMicro under the Vendor pull-down menu, SPI-M2564 under the Device pull-down menu, and 16-lead SOIC under the Package submenu. Figure 5. Select Device Dialog Box 6 LatticeECP3 Versa Evaluation Board User’s Guide Figure 6. Sample SPI Serial Flash Device Dialog Box 5. Click OK in the SPI Serial Flash Device dialog box. Then click OK in the Select Device dialog box. You will return to the main configuration screen 6. From the main programming window, select Go from the top toolbar. This will begin the SPI Serial Flash programming. On-Board Clock Capabilities (See Appendix B, Figure 19) The LatticeECP3 Versa Evaluation Board allows for several clock source options. Some of these options are controlled via the ispClock5406A programmable clock manager device. The ispClock5406A enables the reference clock from the PCI Express interface to provide a reference clock to the SERDES. This is true only when the board is in a PCI Express host socket. When the board is not in a PCI Express host socket, the clock will be supplied by a 156.25 MHz clock on-board oscillator. Both clock inputs can be fanned out to the dedicated SERDES reference inputs, FPGA inputs, and to the expansion connectors. The factory default programming only connects the SERDES reference clock inputs. Factory-defined demonstration designs will control and manage the clock. Figure 7. Clock Controller Scheme FPGA Clock Clock Select PCI Express 156.25 MHz On-board Oscillator SERDES Reference Clock PCLKT0 F11 PCLKC0 F12 REFCLKP V12 Factory Default Clock Programming REFCLKN V11 SERDES Reference Clock Only Expansion Interface Clock 7 LatticeECP3 Versa Evaluation Board User’s Guide General Purpose Clock Source An on-board 100MHz LVDS oscillator is provided for general purpose use. This clock source is connected to differential inputs L5 and K6 and must be used as LVDS inputs to the FPGA. This pin pair also provides optimal interface to the FPGA PLL for customized use. The PCI Express add-in card specification requires add-in boards to include capabilities to tell the host of its presence. The LatticeECP3 Versa Evaluation Board allows this optional connection via a board jumper. The factory default will have two jumpers installed as shown below for the PRSNT connection to the PCI Express host. Figure 8. PCI Express PRSNT Control Connection J4 1 2 3 4 5 6 PCI Express PRSNT Jumper Selector SERDES The LatticeECP3 quad-based SERDES FPGA is utilized on the board for several purposes. The PCSA quad is provisioned to provide a single, full-duplex PCI Express channel. The high-speed signals are connected to the PCI Express edge connection. Table 3. PCI Express Channel Interconnections PETp0 HDINP0 Y15 PETn0 HDINN0 Y14 PERp0 HDOUTP0 AB15 PERn0 HDOUTN0 AB14 J5 HDINP3 Y8 Table 4. SMA Test Interconnections J6 HDINN0 Y9 J7 HDOUTP3 AB8 J8 HDOUTN3 AB9 FPGA Test Pins (see Appendix B, Figure 18) General Purpose DIP Switches General purpose FPGA pins are available for user applications. FPGA pins are connected to switch SW3, a SPST slide-actuated DIP switch. The switches are connected to logic level 0 when moved to the ON position. Switch position 1 is indicated with a dot. These inputs are within a bank connected to 1.5V. The user must program these inputs to be the LVCMOS15 type in the design. 8 LatticeECP3 Versa Evaluation Board User’s Guide Figure 9. LatticeECP3 Versa Evaluation Board LEDs and Switches The designated pins are connected according to Table 5. Table 5. FPGA Ball to DIP Switch Position FPGA Ball Number SW3 DIP Switch Position J7 1 J6 2 H2 3 H3 4 J3 5 K3 6 J2 7 J1 8 General Purpose LEDs (See Appendix B, Figure 18) The LEDs provided on the LatticeECP3 Versa Evaluation Board are connected to general purpose FPGA I/Os. These LEDs provide status for user designs and must be included in the design. The LEDs illuminate when the FPGA output is driven LOW. Table 6 shows the LED and associated FPGA pins. These pins are within an I/O bank connected to 3.3V and the user should program these to be LVCMOS33 type outputs in the design. Table 6. LED Definitions LED Number FPGA Ball Number PCB Designator LED Color LED0 U19 D21 Green LED1 U18 D22 Green LED2 AA21 D24 Yellow LED3 Y20 D25 Yellow LED4 W19 D26 Red LED5 V19 D27 Red LED6 AA20 D29 Blue LED7 AB20 D28 Blue 9 LatticeECP3 Versa Evaluation Board User’s Guide Alpha-numeric LED Display (see Appendix A, Figure 18) A 14-segment alpha-numeric display is provided on the board (D23). These LED segments are connected to general-purpose FPGA I/Os. The LEDs must be included in the FPGA design. The LEDs illuminate when the FPGA output is driven LOW. Table 7 shows the LED and associated FPGA pins. These pins are within an I/O bank connected to 3.3V and the user should program these to be LVCMOS33 outputs in the design. Figure 10. 14-Segment Display Table 7. Alpha-numeric LED Definitions Display fpBGA Ball Number Display fpBGA Ball Number A V6 J AB3 B U7 K AB4 C Y6 L W4 D Aa6 M Y5 E U8 N AA4 F T8 P AA5 G R9 DP W5 H T9 DDR3 Memory Device (see Appendix B, Figure 17) • The LatticeECP3 Versa Evaluation Board is equipped with a SDRAM memory device (1.5V, 64Mb/x16, 96-ball FBGA, 667 MHz, DDR3-1333) such as the Micron MT41J64M16JT-15E:G device. • The DDR3 memory includes a 16-bit wide memory controller interface. • The board includes termination of data, address and command signals. It includes all power and external components needed to demonstrate the memory controller of the LatticeECP3 device. • A 100 MHz on-board clock oscillator is available to provide a DDR3 reference clock. 10 LatticeECP3 Versa Evaluation Board User’s Guide Table 8. DDR3 Memory Controller Interconnections NETNAME 484 fpBGA Ball Number NETNAME 484 fpBGA Ball Number DQ0 E5 A0 C8 DQ1 E4 A1 C7 DQ2 D2 A2 B7 DQ3 D1 A3 D8 DQ4 C2 A4 F9 DQ5 B2 A5 E9 DQ6 G5 A6 A3 DQ7 G4 A7 D7 DQ8 G2 A8 A7 DQ9 F1 A9 B8 DQ10 H4 A10 C9 DQ11 E2 A11 C10 DQ12 J4 K_0 K4 DQ13 B1 K_0# K5 DQ14 C1 CAS# A4 DQ15 G3 BA0 B4 DQS0 F5 BA1 E6 DQS0# F4 BA2 D5 DQS1 H5 ODT E7 DQS1# H6 CS0# C6 CEO G8 WE# D6 RAS# A6 VREF E1 CLKP L5 DM0 E3 CLKN K6 DM1 F3 Ethernet Interfaces (see Appendix B, Figure 18) Two Marvell 88E1119R Gigabit Ethernet transceiver devices (U17) are included on the board. This physical layer device supports 1000BASE-T, 100BASE-TX, and 10BASE-T applications via a standard media interface to a dual RJ45 connection. The RJ45 connection includes network magnetics providing the proper signal conditioning, electro-magnetic interference suppression and signal isolation. This connector includes two LEDs and the board includes four status LEDs from the Marvell device. The LEDs are register-programmed and detailed descriptions are available in the Marvell device data sheet. Table 9. PHY Status Indicators LED Status Description RJ45 (Yellow) LED RX RJ45 (Yellow) LED TX Each Marvell 88E1119R device communicates via a GMII interface to the LatticeECP3 device. 11 LatticeECP3 Versa Evaluation Board User’s Guide Table 10. FPGA GPIO to GMII Interfaces Signal PHY#1 PHY#2 RSTN L3 R21 MDIO L2 U16 MDC: V4 Y18 RXC L4 N19 RX_ER M4 V20 RX_DV M1 U15 RX_D0 M5 AB17 RX-D1 N1 AA17 RX_D2 N6 R19 RX_D3 P6 V21 RX_D4 T2 T17 RX_D5 R2 R18 RX_D6 P5 W21 RX_D7 P3 Y21 TXC C12 M21 TX_EN V3 V22 TX_D0 V1 W22 TX_D1 U1 R16 TX_D2 R3 P17 TX_D3 P1 Y22 TX_D4 N5 T21 TX_D5 N3 U22 TX_D6 N4 P20 TX_D7 N2 U20 GTXCLK M2 M19 CRS P4 P19 COL R1 N18 COMA R41 T151 125CLK T3 R17 1. Each PHY device includes a header dedicated to the COMA connection to the device. The header is populated with a jumper that disables and places the PHY in a low power configuration. Headers J10 and J12 are used for this purpose. It is assigned to PHYs U9 and U10, respectively. 12 LatticeECP3 Versa Evaluation Board User’s Guide Table 11. Expansion Connections x3 Expansion Connector x4 Expansion Connector Pin Signal 484-Ball fpBGA Pin Signal 484-Ball fpBGA 1 GND GND 1 HPE-RST# J20 2 NC NC 2 GND GND 3 2.5V 2.5V 3 IO0 B11 4 IO29 D17 4 IO1 B12 5 IO30 J22 5 IO2 A12 6 IO31 K22 6 IO3 A13 7 IO32 L18 7 IO4 E12 8 IO33 L19 8 IO5 E13 9 IO34 L22 9 IO6 C13 10 IO35 M22 10 IO7 C14 11 IO36 K18 11 IO8 D13 12 IO37 K17 12 IO9 D14 13 IO38 H22 13 IO10 A14 14 IO39 H21 14 IO11 B14 15 IO40 G22 15 IO12 F13 16 IO41 G21 16 IO13 F14 17 IO42 J18 17 IO14 A15 18 IO43 J17 18 IO15 B15 19 IO44 F22 19 GND GND 20 IO45 E22 20 3.3V 3.3V 21 5VIN 5VIN 21 IO16 C15 22 GND GND 22 GND GND 23 2.5V 2.5V 23 IO17 D15 24 GND GND 24 GND GND 25 3.3V 3.3V 25 IO18 G15 26 GND GND 26 GND GND 27 3.3V 3.3V 27 IO19 G14 28 GND GND 28 IO20 A16 29 OSC U13 PIN27 29 IO21 B16 30 GND GND 30 GND GND 31 CLKIN E15 31 IO22 F15 32 GND GND 32 IO23 F16 33 CLKOUT D12 33 IO24 A17 34 GND GND 34 GND GND 35 3.3V 3.3V 35 IO25 B18 36 GND GND 36 IO26 A18 37 3.3V 3.3V 37 IO27 A19 38 GND GND 38 CARDSEL# J19 39 3.3V 3.3V 39 IO28 D16 40 GND GND 40 GND GND 13 LatticeECP3 Versa Evaluation Board User’s Guide References • DS1021, LatticeECP3 Family Data Sheet • HB1009, LatticeECP3 Family Handbook • QS013, LatticeECP3 Versa Evaluation Board Quick Start Guide • UG46, PCI Express Demos for the LatticeECP3 Versa Evaluation Board • UG45, DDR3 Demo for the LatticeECP3 Versa Evaluation Board • UG44, SERDES Eye/Backplane Demo for the LatticeECP3 Versa Evaluation Board Ordering Information Description LatticeECP3 Versa Evaluation Board Ordering Part Number LFE3-35EA-VERSA-EVN 14 China RoHS Environment-Friendly Use Period (EFUP) LatticeECP3 Versa Evaluation Board User’s Guide Technical Support Assistance e-mail: techsupport@latticesemi.com Internet: www.latticesemi.com Revision History Date Version Change Summary April 2011 01.0 Initial release. August 2011 01.1 Updated LatticeECP3 Versa Evaluation Board, Top Side diagram. Corrected ispVM System software version number in the ispVM Requirements text section. Corrected ispVM JTAG Connector Pinout table caption information. November 2011 01.2 Corrected error in the column headings of the Expansion Connections table. February 2012 01.3 Updated document with new corporate logo. February 2012 01.4 Expansion Connections table – Updated information for pins 31 and 33. August 2012 01.5 Added alternate Abracon part numbers for Discera oscillators in Bill of Materials. July 2013 01.6 Added note in the Alternate ispVM Download Interface section. Updated Technical Support Assistance information. © 2013 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 15 16 A B C 5 RefClk 156.25M OSC PCIe CLK5406 LED SEGMENT ARRAY 4 100.00M DIFF OSC USER DIP SWITCH Device Power Pins Power DDR3 1.5V 16-Bit Expansion Clk General Clk PCSA RefClk 3.3V GMII PHY#1 PLL 4 REFERENCE CLOCKS 3 PCIe CH#0 Bank 6 Bank 7 X1 Bank 8 SMA Test CH#3 SERDES Bank 3 Bank 2 Bank 1 ECP3 FPGA Bank 0 Expansion Port- 3.3V Designator U1 is the FPGA DUT. 3 2 Revision History: February 9, 2011 February 24, 2011 USER LEDS 2 Date: Size B Title Monday, March 14, 2011 JPS JPS 1 Sheet 1 of 11 Rev B 1605 Valley Center Parkway Bethlehem, PA 18017 ECP3 VERSA Eval Board Project 1 Rev A Final Design Rev B Cover Page 3.3V Programming SPI 3.3V GMII PHY#2 Expansion Port-3.3V PCSA D 5 A B C D LatticeECP3 Versa Evaluation Board User’s Guide Appendix A. Schematics Figure 11. Cover Page A B C R5 10K-0402SMT 12_0V (5A fused) POWER INPUT +11v to +16v 5 C21 10NF-0402SMT VCCPLL 12_0V TP4 F1251CT-ND F1 C20 10NF-0402SMT 5A Fast-Blo SMT Socketed Fuse 12_0VIN 1 J1 TP1 D14 SCHOTTKY/VISHAY-V12P10 12_0VIN Male Power Jack 2.1mm 3 PJ-032A TP3 TP2 Data Sheet Version = 1.0 LFE3-35E-FN484CES AB2 AA3 N15 K9 N9 K14 N14 M8 R11 H11 M15 R12 H12 L8 L15 VCCA 10NF-0402SMT 10NF-0402SMT C22 C3 C23 C4 C33 C34 100NF-0402SMT + 3_3V C7 C25 C6 C24 C32 C5 C35 C8 100NF-0402SMT 10NF-0402SMT + C36 C9 3_3V R25 12_0V 1_8K-1206SMT LED_GREEN_0603 D13 12VIN GOOD SW 4 1_8K-1206SMT R22 Q1 2N2222/SOT23 2_5V R27 1 10K-0603SMT VCC_CORE 3 R28 1 10K-0603SMT LED_GREEN_0603 D11 C52 220NF-0402SMT 16V 1_5V 12_0V Q3 2N2222/SOT23 3_3V R29 1 10K-0603SMT 1000pF-0402SMT 22 23 24 2 1 8 7 C37 10uF,25V-1206SMT RLP-134 RT/SYNC PG1 VC1 TRACK/SS1 FB1 SW1 R6 51K-0402SMT R14 51K-0402SMT RT/SYNC PG1 VC1 TRACK/SS1 FB1 SW1 BOOST1 C27 2 3.3V R26 220R-0603SMT R179 220R-0603SMT D9 LED_GREEN_0603 3_3V PG2 VC2 TRACK/SS2 FB2 SW2 BOOST2 20 19 17 18 11 12 20 19 17 18 11 12 U4 LT3508EUF 12_0V PG2 VC2 TRACK/SS2 FB2 SW2 BOOST2 U3 LT3508EUF 12_0V DNI 3_3V C44 1000pF-0402SMT VCCA C19 PCSA_VCCOB C14 PCSA_VCCIB C31 D2 1N4448W C29 C28 + C13 + C18 FB2 2.5V D31 + C26 BOOST1 LED_GREEN_0603 2_5V 1% 22 23 24 2 1 8 7 C51 10uF,25V-1206SMT RLP-134 DNI FB1 BLM41PG600SN1 +1.2 v 500 mA BLM41PG600SN1 C17 10uF,25V-1206SMT VOUT2 R4 OPEN-0603SMT 2.3v minimum input voltage 0.46 v drop at 500 mA max C56 1000pF-0402SMT D5 1N4448W LED_GREEN_0603 D12 VCCA 1.2V Analog R21 10K-0402SMT 1% 100pF-0402SMT C245 R15 5_11K-0402SMT 1% D7 DFLS220L R24 1_8K-1206SMT C63 22uF,6.3V-0805SMT RLP-133 1.5V C43 C12 3_3UF-10V-0805SMT 10V 2 R2 0R-0603SMT 10NF-0402SMT C16 D1 1N4448W 8 9 7 6 10 3_3V BYP2 ADJ2 C38 16V 220NF-0402SMT R9 10K-0402SMT 1% L3 4.7uH-SPD62R-472M 22uF,6.3V-0805SMT RLP-133 C55 VCC_CORE R23 1_8K-1206SMT 12_0V Q2 2N2222/SOT23 D3 DFLS220L R7 21_5K-0402SMT 1% EN2 VOUT2 VOUT2_6 2_5V Vout = 0.8*(R7/R9+1) = 2.52 v C49 22uF,6.3V-0805SMT RLP-133 BYP1 ADJ1 VOUT1 VOUT1_3 EN U2 LT3029EDE 1 16 L1 4.7uH-SPD62R-472M 22uF,6.3V-0805SMT RLP-133 C41 2.5V Core Power C54 22uF,6.3V-0805SMT RLP-133 1.2v/ms +1.2 v 1.35 A C40 22uF,6.3V-0805SMT RLP-133 1.2v/ms BLM41PG600SN1 FB3 R3 OPEN-0603SMT R1 0R-0603SMT 4 3 15 2_5V Voltage Regulators C15 10NF-0402SMT C10 3_3UF-10V-0805SMT 10V Vout = 0.8*(R15/R21+1) = 1.21 v LED_GREEN_0603 D10 12_0V VCC_CORE, +1.2 V, 1.35 A 1_5V, +1.5 V, 1.1 A SW EN 3_3V, +3.3 V, 1.35 A 3 VOUT1 +2.5v 1.1 A C30 10uF,25V-1206SMT 6.3V 0805 +1.2 v 500 mA 1.2V VCC_CORE SERDES 1_2V, +1.2 V, 1A FB4 BLM41PG600SN1 2_5V, +2.5V, 1.1 A LDO EN C11 VCC_CORE 100NF-0402SMT SW EN SW Power Supply Block Diagram 100NF-0402SMT V13 U12 U11 V10 C2 10NF-0402SMT 1NF-0402SMT 100NF-0402SMT 10NF-0402SMT 1UF-16V-0805SMT 10NF-0402SMT C1 100NF-0402SMT 22UF-16V-TANTBSMT 22UF-16V-TANTBSMT 4 1UF-16V-0805SMT 100NF-0402SMT 22UF-16V-TANTBSMT 14 13 VIN1 VIN1_13 12 11 VIN2 VIN2_11 NC GND GND_PAD J11 J9 P11 P12 J14 J13 M14 M9 P9 L9 P14 P10 J12 J10 L14 P13 1UF-16V-0805SMT D GND VCC GND VCC VCC GND VCC GND VCC GND GND VCC GND VCC GND VCC GND VCC VCC GND GND VCC GND VCC VCC GND VCC GND GND VCC VCC GND GND GND GND VCCA GND VCCA GND VCCA VCCA GND GND GND VCCAUX GND VCCAUX VCCAUX GND GND VCCAUX GND VCCAUX GND VCCAUX GND VCCAUX GND VCCAUX GND VCCPLL_L GND GND VCCPLL_L GND VCCPLL_R GND VCCPLL_R GND XRES GND GND GND RESERVE-AB2 GND RESERVE-AA3 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 2 1 2 100NF-0402SMT G 2 1 2 5 17 C45 330pF-0402SMT 1NF-0402SMT 5 G 3 2 G 3 2 1 2 G 3 2 C46 10pF-0402SMT C60 10pF-0402SMT 2 1 C59 330pF-0402SMT 1% 22UF-16V-TANTBSMT GND1 GND2 GND3 GND4 R11 34K-0402SMT R18 63_4K-0402SMT 21 SHDN 3 4 5 6 21 SHDN 9 VIN1 GND5 25 GND1 GND2 GND3 GND4 3 4 5 6 R10 51K-0402SMT R19 30_1K-0402SMT 100NF-0402SMT 10 VIN2 GND6 GND7 GND8 GND9 13 14 15 16 10 VIN2 2 1 22UF-16V-TANTBSMT 1UF-16V-0805SMT Date: Size C Title R20 20K-0402SMT 1% R13 11_5K-0402SMT 1% R8 35_7K-0402SMT D4 DFLS220L 3.3V C39 220NF-0402SMT 16V L2 4.7uH-SPD62R-472M 1 3_3V C50 22uF,6.3V-0805SMT RLP-133 C42 22uF,6.3V-0805SMT RLP-133 1.2v/ms +3.3 v 1.35 A 3_3V 1_5V 1.1 A C64 22uF,6.3V-0805SMT RLP-133 C58 22uF,6.3V-0805SMT RLP-133 1.2v/ms 1 Wednesday, February 09, 2011 Sheet ECP3- VERSA Eval Board Project Power 2 of 11 Rev B 1605 Valley Center Parkway Bethlehem, PA 18017 Vout = 0.8*(R16/R17+1) = 1.51 v 100pF-0402SMT R17 16_9K-0402SMT 1% C246 15K-0402SMT R16 1% D8 DFLS220L C53 220NF-0402SMT 16V L4 4.7uH-SPD62R-472M DDR3 1.5V Power +1.5v Vout = 0.8*(R8/R13+1) = 3.28 v C57 1000pF-0402SMT D6 1N4448W R12 51K-0402SMT 1UF-16V-0805SMT U1A G C62 330pF-0402SMT 9 VIN1 GND5 25 G 2 1 C47 10pF-0402SMT C61 10pF-0402SMT 1 2 10NF-0402SMT GND6 GND7 GND8 GND9 C48 330pF-0402SMT SERDES Power 1 2 17 13 14 15 16 N11 K13 B9 G12 V2 K8 M16 Y4 N12 AA7 U13 AA10 AA15 D3 M13 AB1 AA13 T10 U9 L12 AA18 K12 R10 K2 Y7 F2 U10 E14 N10 H8 AB22 W16 R5 M12 H18 AA16 V14 Y16 AA12 C11 E21 P2 T12 AA9 V15 M7 W20 M11 H10 L7 AB7 B5 B13 AA8 W7 V16 J5 A22 L16 H13 L20 K15 J21 U21 N8 U6 P16 V8 AA14 R15 A1 B17 R8 T11 F17 L13 F6 H15 V9 L10 M3 V7 AA11 P18 K11 T13 C19 K10 G11 N21 AB16 N13 U14 U17 E8 M10 L11 R13 A B C D LatticeECP3 Versa Evaluation Board User’s Guide Figure 12. Power A B C 8 8 7 9 9 100NF-0402SMT J2 C82 5 C83 3_3V SW2 FPGA_CSSPI0N_DI SPI0_Q PROGRAMN SW1 3_3V C77 100NF-0402SMT FLASH_DIS PROGRAMN & GSRN Pushbuttons FPGA GSRN L5 1UH-1206SMT 4_7K-0402SMT R51 7 6 R66 10K-0402SMT R34 4_7K-0402SMT CS CLK DI DO 93LC56-SO8 VCC NU ORG VSS 3 1 3_3V OUT1 OUT2 MAX6817 IN2 IN1 U7 1 2 3 4 5 6 7 8 U8 M25P64-FLASH HOLD# CK VCC D DU1 DU8 DU2 DU7 DU3 DU6 DU4 DU5 S# VSS Q W# R39 27R-0603SMT USB1_CS USB1_SK USB1_D USB1_Q 1 12 MHz 2 C80 12PF-0603SMT DI Y1 ATS120SM-1 HC-49/US-SM DI 1 2 3 4 16 15 14 13 12 11 10 9 6 GSRN PROGRAMN NW FPGA_MCLK FPGA_SISPI 4 3_3V 4 + R48 C76 DI LFE3-35E-FN484CES VCCIO8 VCCIO8 H16 G16 13 3 2 63 62 61 6 14 7 8 49 50 FPGA_CSSPI0N_DI FPGA_CS1N FPGA_CSN GSRN FPGA_MCLK PROGRAMN TXD_UART RXD_UART SPI0_Q FPGA_SISPI DONE INITN FPGA_WRITEN SPIFASTN FTVCC1_8V FT2232H CLK_RESETn 156MHz_EN SCL [9] SDA [9] PCIE_PERSTN BCBUS0 BCBUS1 BCBUS2 BCBUS3 BCBUS4 BCBUS5 BCBUS6 BCBUS7 BDBUS0 BDBUS1 BDBUS2 BDBUS3 BDBUS4 BDBUS5 BDBUS6 BDBUS7 ACBUS0 ACBUS1 ACBUS2 ACBUS3 ACBUS4 ACBUS5 ACBUS6 ACBUS7 ADBUS0 ADBUS1 ADBUS2 ADBUS3 ADBUS4 ADBUS5 ADBUS6 ADBUS7 3_3V C85 [9] [9] [4] 16 17 18 19 21 22 23 24 TP5 36 60 48 52 53 54 55 57 58 59 38 39 40 41 43 44 45 46 26 27 28 29 30 32 33 34 C69 100NF-0402SMT 3_3V C70 R67 R62 OPEN-0402SMT R68 R71 R69 10K-0402SMT 10K-0402SMT 10K-0402SMT 3_3V FPGA_TMS R54 10K-0402SMT FPGA_TCK 10K-0402SMT FPGA_CCLK TXD_UART RXD_UART UART_ACT R36 0R-0603SMT R32 0R-0603SMT R33 0R-0603SMT R38 0R-0603SMT JTAG_ACT C68 100NF-0402SMT FPGA_TDI C67 PWREN# C84 R52 0R-0402SMT 3 3_3V 3_3V 3_3V VCCJ TCK TDI TDO TMS U1I R57 R58 R59 4_7K-0603SMT 3_3V 2 TCK TMS NC VCC 7 1 3_3V D16 3_3V INITN R65 10K-0603SMT DONE 1 Date: Size C Title DONE TMS GND TCK DONE INITn 680R-0603SMT R55 1 3_3V GSRN D18 LED_RED_0603 +3.3V TDO TDI PROGRAMn Local JTAG header (ispVM) Friday, March 18, 2011 1 Sheet ECP3 VERSA Eval Board Project Programming 3_3V PROGRAMN D19 LED_RED_0603 680R-0603SMT R56 3 of 11 Rev B 1605 Valley Center Parkway Bethlehem, PA 18017 CONFIG Status LEDs DONE indicator will light when configuration is successfully completed INITN LED_RED_0603 R60 D17 680R-0603SMT R INITN indicator will light if an error occurs during configuration programming HEADER 10 INITN GND ispEN_N TDI TDO R30 LED_GREEN_0603 DONE J3 2 3 4 5 6 8 9 10 D15 3_3V Q4 2N2222/SOT23 D20 R49 1K-0603SMT R45 R46 R47 4_7K-0603SMT 4_7K-0603SMT 4_7K-0603SMT LFE3-35E-FN484CES 3_3V H7 G7 G6 C3 C4 100NF-0402SMT C73 3_3V 220R-0603SMT G 100NF-0402SMT SUSPEND# FTDI High-Speed USB TEST OSCO OSCI EECS EECLK EEDATA REF RESET# DM DP VREGOUT VREGIN U5 FT2232HL FPGA_CCLK R44 12K-0603SMT R40 4_7K-0402SMT F20 E20 E19 B21 F21 D20 J16 H17 C22 D22 G17 G18 G19 G20 H19 H20 C21 D21 F19 F18 A21 B22 C20 C18 B19 E18 E17 A20 B20 D18 D19 2_2K-0603SMT CCLK CFG0 CFG1 CFG2 DONE INITN PR11A/WRITEN PR11B/D0/SPIFASTN PR12A/D1 PR12B/D2 PR14A/D3/SI PR14B/D4/SO PR15A/D5 PR15B/D6/SPID1 PR17A/D7/SPID0 PR17B/BUSY/SISPI PR6A PR6B/DI/CSSPI0N/CSSPIN PR8A/CS1N/HOLDN/CONT2N PR8B/CSN/SN/CONT1N PR9A/DOUT/CSON/CSSPI1N PR9B/MCLK PROGRAMN PT68A PT68B PT70A PT70B PT71A PT71B PT73A PT73B U1H R50 1M-0603SMT DI C75 USB_N_i USB_P_i C74 3_3UF-10V-SMT 3_3V C72 100NF-0402SMT C71 4_7UF-10V-SMT 2 FB6 MPZ1608Y600B + DI 1 33pF-0402SMT-DNI FTVCC1_8V C66 100NF-0402SMT C65 4_7UF-10V-SMT 2 FB5 MPZ1608Y600B + DI 1 R31 LED_GREEN_0603 3_3V R35 27R-0603SMT 18pF = 12pF + Ground Plane ( 6pF ) DI USB_N USB_P R42 R41 R43 10K-0402SMT 10K-0402SMT 10K-0402SMT C79 12PF-0603SMT 8 7 6 5 U6 SPI FLASH R53 6 1 2 3 4 5 4_7K-0402SMT 1 2 3 4 5 C81 USB Download 10NF-0402SMT 5 VCC 2 GND 100NF-0402SMT R37 10K-0603SMT R64 10K-0402SMT 10 33pF-0402SMT-DNI 12 37 64 VCORE VCORE VCORE 20 31 42 56 D R63 10K-0402SMT 100NF-0603SMT 220R-0603SMT G UART_ACT 100NF-0402SMT VCCIO VCCIO VCCIO VCCIO 4 9 VPHY VPLL AGND USB_MINI_AB R70 10K-0402SMT SPIFASTN 2 FPGA_CSN 3 FPGA_WRITEN 4 FPGA_CS1N C78 JTAG_ACT R61 LED_GREEN_0603 GND GND GND GND GND GND GND GND 100NF-0603SMT Y 1 5 11 15 25 35 47 51 10NF-0402SMT 220R-0603SMT G 3 2 Y GSRN 18 PROGRAMN 5 A B C D LatticeECP3 Versa Evaluation Board User’s Guide Figure 13. Programming PROGRAMN DONE INITN FPGA_TDO A B 2 3 4 5 J6 SMA PCSA_HDOUTP3 2 3 4 5 SMA 1 J8 1 SMA 1 J7 PCSA_HDINP3 SMA 1 J5 PCSA_HDOUTN3 PCSA_HDINN3 C93 C92 C91 C90 C89 C88 PCSA_VCCIB PCSA_VCCOB 100NF-0402SMT 4 [9] [9] PRSNT1# PRSNT3# 5 4 All Nets to SMAs are 100-ohm differential pairs. The P and N traces shall be