LatticeECP3 PCI Express Solutions Board – Revision A
User’s Guide
August 2012
Revision: EB43_01.2
LatticeECP3 PCI Express Solutions Board – Revision A
User’s Guide
Introduction
As PCI Express applications have emerged, the LatticeECP3™ FPGA family has become a well-suited solution for
many system designs. The features of the LatticeECP3 PCI Express Solutions Board can assist engineers with
rapid-prototyping and testing their designs. The board is an enhanced form-factor of the PCI Express add-in card
specification. It allows for full x1 form-factor compliance and x4 is available for demonstration purposes with some
non-standard form-factor issues. The flexibility to use the same board to demonstrate both x1 and x4 configurations
is accomplished by simply changing the mounting hardware. The board has several debugging and analyzing features for complete evaluation of the LatticeECP3 device. This guide is intended to be referenced in conjunction with
evaluation design tutorials to demonstrate the LatticeECP3 FPGA.
This user’s guide describes the LatticeECP3 PCI Express Solutions Board featuring the LatticeECP3 LFE3-95EAFN672 FPGA. The stand-alone evaluation board provides a functional platform for development and rapid prototyping of applications that require high-speed SERDES interfaces to demonstrate PCI Express capabilities using an
add-on card form-factor. The board is manufactured using standard FR4 dielectric and through-hole vias. The nominal impedance is 50-ohm for single-ended traces and 85-ohm for differential traces.
Important: This document (including the schematics in the appendix) describes LatticeECP3 PCI Express Solutions Boards marked as Rev A. This marking can be seen on the silkscreen of the printed circuit board, under the
Lattice Semiconductor logo.
Figure 1. LatticeECP3 PCI Express Solutions Board
2
LatticeECP3 PCI Express Solutions Board – Revision A
User’s Guide
Features
• PCI Express x1 and x4 edge connector interfaces
• Allows demonstration of PCI Express (x 1and x4) interfaces
– x1 is form-factor compliant and will fit a standard PC-equipped PCI Express motherboard socket
– x4 is non-compliant but will demonstrate x4 functionality by a simple change to the hardware
• Allows control of SERDES PCS registers using the Serial Client Interface (ORCAstra)
• On-board Boot Flash
– Both Serial SPI Flash and Parallel Flash via MachXO™ programming bridge
• Shows interoperation with a high performance DDR2 memory component
• Includes driver based “run-time” device configuration capability via ORCAstra or PCI Express
• Switches, LEDs, displays for demo purposes
• Input connection for lab-power supply
• Power connections and power sources
• ispVM™ programming support
• On-board and external reference clock sources
The contents of this user’s guide include top-level functional descriptions of the various portions of the evaluation
board, descriptions of the on-board connectors, diodes and switches and a complete set of schematics of the
board.
Figure 2. PCI Express Solutions Board Outline Drawing, Top Side
3
LatticeECP3 PCI Express Solutions Board – Revision A
User’s Guide
Figure 3. PCI Express Solutions Board Outline Drawing, Bottom Side
x1 and x4 PCI Express Support
PCI Express x1 and x4 is supported with the same PCB. This add-in PCB is designed to work in both types of
motherboard slots. The PCB complies with the width and length dimensions of the PCI Express Card Electromechanical (CEM) Specification Revision 1.1. The only exclusion of the CEM specification is the component and back
side of the add-in board may interfere with other boards in a fully-populated motherboard.
This board is easily interchanged from x1 to x4 configurations by removing the back-panel bracket and reinstalling
it on the opposite side. This permits plug-in into PCI Express sockets on the motherboard and securing it in the
chassis if desired. The back-panel bracket is shown below.
Figure 4. Back Panel Drawing
4
LatticeECP3 PCI Express Solutions Board – Revision A
User’s Guide
LatticeECP3 Device
This board features a LatticeECP3 FPGA with a 1.2V core supply. It can accommodate all pin compatible
LatticeECP3 devices in the 672-ball fpBGA (1mm pitch) package. A complete description of this device can be
found in the LatticeECP3 Family Data Sheet on the Lattice website at www.latticesemi.com.
Note: The connections referenced in this document refer to the LFE3-95EA-FN672 device. Available I/Os and
associated sysI/O™ banks may differ for other densities within this device family.
Applying Power to the Board
The LatticeECP3 PCI Express Solutions Board is ready to power on. The board can be supplied with power from
an AC wall-type transformer power supply shipped with the board. Or it can be supplied from a benchtop supply via
terminal screw connections. It also has provisions to be supplied from the PCI Express edge fingers from a host
board.
To supply power from the factory-supplied wall transformer, simply connect the output connection of the power cord
to J1 and plug the wall-transformer into an AC wall-outlet.
Power Supplies
(see Appendix A, Figure 21)
The evaluation board incorporates an alternate scheme to provide power to the board. The board is equipped to
accept a main supply via the TB1 connection. This connection is provided to use with a benchtop supply adjusted
to provide a nominal +12V DC.
All input power sources and on-board power supplies are fused with surface-mounted fuses and have green LEDs
to indicate power GOOD status of the intermediate supplies
Table 1. Board Power Supply Fuses (see Appendix A, Figure 21)
F1
12V Fuse
F2
1.2V Core Fuse
F3
3.3V Fuse
F4
1.8V Fuse
F5
1.2V Analog Supply
Table 2. Board Power Supply Indicators (see Appendix A, Figure 21)
D1
3.3V Source Good Indicator
D2
1.2V VCC Core Source Good Indicator
D3
1.8V Source Good Indicator
D4
1.2V Analog Source Good Indicator
D5
12V Input Good Indicator
External power can be alternatively connected rather than the wall transformer power pack.
Table 3. External Board Supply Input Terminal (see Appendix A, Figure 21)
TB1
Screw terminal for +12V DC
Pin1 (square PCB pad): +12V DC
Pin2: Ground
5
LatticeECP3 PCI Express Solutions Board – Revision A
User’s Guide
PCI Express Power Interface
Power can be sourced to the board via the PCB edge-fingers (CN1 and CN2). This interface allows the user to provide power from a PCI Express Host board.
Programming/FPGA Configuration
(see Appendix A, Figure 23)
A programming header is provided on the evaluation board, providing access to the LatticeECP3 JTAG port.
ispVM Download Interface
J4 and J8 are 6-pin JTAG connectors used in conjunction with the ispVM USB download cable to program and control the device. These connectors are available through the back-panel bracket as needed for x1 or x4 PCI Express
configurations. These connectors are used in conjunction with the ispVM programming cable and software to program the configuration memory or FPGA directly.
Table 4. Standard ispVM Programming Cable Configuration
Pin 1
VCC
Pin 2
TDO
Pin 3
TDI
Pin 4
TMS
Pin 5
GND
Pin 6
TCK
After initial board setup, use the following procedure to program the evaluation board. Instructions assume ispVM
software has been installed on a local PC.
Connect the ispDOWNLOAD cable rainbow colored flywires to the connector J4.
6
LatticeECP3 PCI Express Solutions Board – Revision A
User’s Guide
Table 5. ispVM JTAG Connector (see Appendix A, Figure 21)
6
5
4
3
2
1
Note: A dot denotes PIN 1 on the both the
PCB or back-panel bracket.
Pin
Function
Color
1
PWR
Red
2
TDO
Brown
3
TDI
Orange
4
TMS
Purple
5
GND
Black
6
TCK
White
Figure 5. ispVM Programming Cable Connector
Programming the Daisy Chain
This board includes two Lattice Semiconductor programmable (U1=LFE3-95, U12=LCMXO1200) devices that can
be programmed in a daisy chain.
Figure 6. JTAG Chain
TCK
TMS
TDI
TDO
TCK
LatticeECP3
FPGA
(U1)
7
TMS
TDO
TDI
MachXO1200
CPLD
(U13)
LatticeECP3 PCI Express Solutions Board – Revision A
User’s Guide
Download Procedures
Requirements:
• PC with ispVM System v.17.7 (or later) programming management software, installed with appropriate drivers
(USB driver for USB Cable, Windows NT/2000/XP parallel port driver for ispDOWNLOAD Cable).
Note: An option to install these drivers is included as part of the ispVM System setup.
• ispDOWNLOAD Cable (pDS4102-DL2A, HW7265-DL3A, HW-USB-1A, etc.)
JTAG Download
The LatticeECP3 device can be configured easily via its JTAG port. The device is SRAM-based; it must remain
powered on to retain its configuration when programmed in this fashion.
1. Connect the LatticeECP3 PCI Express Solutions Board to the appropriate power sources and power up board.
2. Connect the ispDOWNLOAD cable to the appropriate header. J4 is used for the 1x6 connection. J8 is used in
the same manner for x4 configurations.
3. Start the ispVM System software.
4. Press the SCAN button located in the toolbar. The LatticeECP3 and the MachXO1200 devices should be automatically detected.
Figure 7. ispVM Main Window
5. Double-click the device to open the device information dialog. In the device information dialog, click the Browse
button located under Data File. Locate the desired bitstream file (.bit). Click OK to both dialog boxes.
6. To program only the LatticeECP3-95, place the LCMXO1200C device into BYPASS and the LFE3-95 should be
in FAST PROGRAM mode.
8
LatticeECP3 PCI Express Solutions Board – Revision A
User’s Guide
Figure 8. ispVM Fast Programming Mode
Figure 9. ispVM Device Information Dialog Box
7. Add Data File.
8. Click the green GO button. This will begin the download process into the device. Upon successful download, the
device will be operational.
Configuration Status Indicators
(see Appendix A, Figure 23)
These LEDs indicate the status of configuration to the FPGA.
• D6 (red) illuminated, this indicates that the programming was aborted or reinitialized driving the INITN output low.
• D9 (green) is illuminated, this indicates the successful completion of configuration by releasing the open collector
DONE output pin.
9
LatticeECP3 PCI Express Solutions Board – Revision A
User’s Guide
• D10 (green) will flash indicating TDI activity.
• D8 (red) illuminated, this indicates that PROGRAMN is low.
• D7 (red) illuminated, this indicates that GSRN is low.
PROGRAMN & GSRN
(see Appendix A, Figure 23)
• These push-button switches assert/de-assert the logic levels on the PROGRAMN (SW3 or SW7) and GSRN
(SW1 or SW6). Depressing the button drives a logic level “0” to the device.
• These push-buttons are accessible from the back panel if the evaluation board is mounted in a PCI Express slot
of a PC.
CFG [2:0]
(see Appendix A, Figure 23)
• The FPGA CFG pins are set on the board for a particular programming mode via the SW2 DIP switch.
• JTAG programming is independent of the MODE pins and is always available to the user.
• Pushing in (depressing) the switch is ON and sets the value to 0.
Table 6. CFG Mode Selections
CFG2
CFG1
CFG0
Configuration Mode
SPI Flash
0 (ON)
0 (ON)
0 (ON)
0 (ON)
1 (OFF)
0 (ON)
SPIm
1 (OFF)
0 (ON)
1 (OFF)
Slave Serial
1 (OFF)
1 (OFF)
1 (OFF)
Slave Parallel
X
(don’t care)
X
(don’t care)
X
(don’t care)
ispJTAG™
On-Board Serial SPI Flash Memory
(see Appendix A, Figure 23)
• One Serial SPI (16-pin tssop 64M) Flash memory device (U6) is on-board for non-volatile configuration memory
storage. Either a STMicro M25P64VMF16 or Macronix MX25L6405 device is populated on-board.
• All CFG [2:0] need to be [000] depressed to read the Flash memory at power-up or after toggling the PROGRAMN pin.
• Install jumper across pins 2 and 4 on J2.
Programming Serial SPI Flash Memory
The Serial SPI Flash memory device can be configured easily via its JTAG port. This mode enables the FPGA to
be programmed at power-up or assertion of PROGRAMN with a bitstream stored in the memory device.
1. Connect the LatticeECP3 PCI Express Solutions Board to the appropriate power sources and power-up board.
2. Connect the ispDOWNLOAD cable to the appropriate header. J4 is used with the cable.
3. Start the ispVM System software.
4. Press the SCAN button located in the toolbar. The LFE3-95 and the LCMXO1200C devices should be automatically detected.
10
LatticeECP3 PCI Express Solutions Board – Revision A
User’s Guide
Figure 10. Results of Scanning Board via ispVM
5. Double-click the Operation column for the LFE3-95 and the Device Dialog box shown below will open.
6. In the dialog box, select the SPI Flash Programming mode in the Device Access Options pull-down menu.
This will open the SPI Serial Flash Dialog box.
Figure 11. Device Information Dialog Screen
11
LatticeECP3 PCI Express Solutions Board – Revision A
User’s Guide
Figure 12. SPI Serial Flash Dialog Screen
7. The SPI Serial Flash Device dialog box will open. In this box select SPI Flash Erase, Program, Verify in the
Operation pull-down menu.
8. Select SPI Serial Flash in the Device Family pull-down menu, STMicro under the Vendor pull-down menu,
SPI-M2564 under the Device pull-down menu, and 16-lead SOIC under the Package submenu.
Figure 13. Select Device Dialog Box
12
LatticeECP3 PCI Express Solutions Board – Revision A
User’s Guide
Figure 14. Sample SPI Serial Flash Device Dialog Box
9. Click OK in the SPI Flash Device dialog box. Then click OK in the Select Device dialog box. You will then
return to the main configuration screen. If you do not desire to load the LCMXO1200C device, this device
should be placed in Flash Bypass mode by double-clicking the Operation column and selecting the Bypass
operation shown below.
Figure 15. FLASH Bypass for LCMXO1200C Device
13
LatticeECP3 PCI Express Solutions Board – Revision A
User’s Guide
Figure 16. Programming Main Window
10.From the main programming window, select GO in the top toolbar. This will begin the SPI Serial Flash programming.
Figure 17. SPI Serial Flash Programming Status Window
14
LatticeECP3 PCI Express Solutions Board – Revision A
User’s Guide
Figure 18. Successful SPI Serial Flash Programming Session
On-Board Parallel SPI Flash Memory
(see Appendix A, Figure 24)
• A 16-bit parallel Flash device is also available. This board uses a Lattice MachXO CPLD device to act as a programming bridge from the Flash device.
• The CFG [2:0] need to be [111], all up.
• Lattice ispVM programming software can be used to program either the serial SPI Flash or the parallel Flash
devices. Application note AN8077, Parallel Flash Programming and FPGA Configuration, addresses the use of
the parallel Flash implementation. Note: For parallel Flash loading, the board needs the appropriate connections
of J2. J2 requires a jumper be installed between pins 1 and 3.
User-Defined General Purpose Clock Oscillator
(see Appendix A, Figure 27, Y1)
A 100MHz oscillator is included on-board. It is fanned-out to several destinations on the board, as described in
Table 7.
15
LatticeECP3 PCI Express Solutions Board – Revision A
User’s Guide
Table 7. 100MHz Clock Destinations
Clock Destination
PCB Designation
Destination Pin
CPLD
U12
A8
FPGA
U1
P21-PCLKT2_0
FPGA
U1
K3-LLUM0-GDLLT_IN
FPGA
U1
M4-PCLKT7_0
SERDES
(see Appendix A, Figure 25)
SERDES/FPGA Reference Clocks
The 50-ohm terminated SMA connectors are optionally provided to supply reference clocks directly to the
LatticeECP3 device. Please contact the factory for information to populate the PCB with SMA connectors.
Table 8. SMA Inputs for External Clock Source
Connector
SERDES Signal
FPGA Pin
J6
FPGA_SMA_REFCLKP
V20
J7
FPGA_SMA_REFCLKN
W19
SERDES PCI Express Channels
(see Appendix A, Figure 25)
This board is equipped to communicate directly as an add-on card to a PCI Express host. It is designed with edgefingers (CN1 or CN2) that fit directly into a PCI Express host receptacle. Power can be supplied directly from the
PCI Express host via the edge-finger connections.
Table 9. x1 PCI Express Connections
CML Pin Name
FPGA Pin
PCIE
PCI Express Edge
PCSA_HDOUTP_0
AF21
PERp0
A16
PCSA_HDOUTN_0
AF20
PERn0
A17
PCSA_HDINP_0
AD21
PETp0
B14
PCSA_HDINN_0
AD20
PETn0
B15
PCSA_REFCLKP
AC17
PCIe_CLKp
A13
PCSA_REFCLKN
AC18
PCIe_CLKn
A14
PCIE_PERSETN
U20
PERSTN
A11
Description
Integrated endpoint block transmit pair
Integrated endpoint block receive pair
Integrated endpoint block differential clock pair
Fundamental PCI Express reset
Table 10. x4 PCI Express Connections
CML Pin Name
FPGA Pin
PCIE
PCI Express Edge
PCSB_HDOUTP_0
AF13
PERp0
A16
PCSB_HDOUTN_0
AF12
PERn0
A17
PCSB_HDINP_0
AD13
PETp0
B14
PCSB_HDINN_0
AD12
PETn0
B15
PCSB_HDOUTP_1
AF10
PERp1
A21
PCSB_HDOUTN_1
AF11
PERn1
A22
PCSB_HDINP_1
AD10
PETp1
B19
PCSB_HDINN_1
AD11
PETn1
B20
16
Description
Integrated endpoint block transmit pair
Integrated endpoint block receive pair
Integrated endpoint block transmit pair
Integrated endpoint block receive pair
LatticeECP3 PCI Express Solutions Board – Revision A
User’s Guide
Table 10. x4 PCI Express Connections (Continued)
CML Pin Name
FPGA Pin
PCIE
PCI Express Edge
PCSB_HDOUTP_2
AF9
PERp2
A25
PCSB_HDOUTN_2
AF8
PERn2
A26
PCSB_HDINP_2
AD9
PETp2
B23
PCSB_HDINN_2
AD8
PETn2
B24
PCSB_HDOUTP_3
AF6
PERp3
A29
PCSB_HDOUTN_3
AF7
PERn3
A30
PCSB_HDINP_3
AD6
PETp3
B27
PCSB_HDINN_3
AD7
PETn3
B28
PCSB_REFCLKP
AC9
PCIe_CLKp
A13
PCSB_REFCLKN
AC10
PCIe_CLKn
A14
PCIE_PERSETN
U20
PERSTN
A11
Description
Integrated endpoint block transmit pair
Integrated endpoint block receive pair
Integrated endpoint block transmit pair
Integrated endpoint block receive pair
Integrated endpoint block differential clock pair
Fundamental PCI Express reset
FPGA Test Pins
(see Appendix A, Figure 27)
General Purpose DIP Switch
(see Appendix A, Figure 27, SW5)
General-purpose FPGA pins are available for user applications. FPGA pins are connected to a switch (SW5) which
is an SPST side actuated DIP switch. The switch is physically located on the secondary side of the PCB along the
back-panel edge. The switches are connected to a logic level 0 when depressed toward the board and a 1 when
away from the board. The designated pins are connected according to Table 11.
Table 11. FPGA Test Pins (See Appendix A, Figure 26)
FPGA BGA
SW5 Switch Position
D9
1
F9
2
G8
3
A6
4
A5
5
E9
6
E8
7
A7
8
Logic 1
PCB
Logic 0
17
1
2
3
4
5
6
7
8
LatticeECP3 PCI Express Solutions Board – Revision A
User’s Guide
Figure 19. 8-position DIP Switch (SW5) on Secondary PCB Side
General Purpose LEDs
(see Appendix A, Figure 27)
LEDs are provided along the back panel edge of the PCB. These LEDs are connected to general-purpose FPGA
I/Os. The LEDs are illuminated by the associated FPGA outputs being driven to a valid LOW level. The use of these
LEDs is defined for PCI Express applications to observe the status of the PCI Express link during operation. The
LEDs must be included in the FPGA design. These status LEDs are available in both x1 or x4 configurations. The
back panel marking reflects PCI Express specific status.
Table 12. LED Definitions
PCI Express x1
PCI Express x4
FPGA Pin#
PCB Designator
FPGA Pin#
PCB Designator
Description
H11
D19
C10
D20
User defined
H10
D21
A9
D22
User defined
F11
D26
A10
D27
User defined
G11
D24
B10
D25
User defined
D10
D11
D10
D12
Data link up active
F10
D13
A8
D14
L0 state active
G9
D15
B8
D16
Polling state inactive
G10
D17
C9
D18
PLL locked
18
LatticeECP3 PCI Express Solutions Board – Revision A
User’s Guide
General-Purpose Header
(see Appendix A, Figure 27, J5)
A 2x9 header (J5) provides a general-purpose connection to communicate with general purpose FPGA I/Os.
Table 13. General Purpose Header Connections
Header Pin
FPGA Pin
Header Pin
FPGA Pin
1
GND
2
GND
3
C15
4
E15
5
B15
6
E14
7
C14
8
A20
9
D14
10
A19
11
B16
12
C17
13
C16
14
B17
15
F13
16
A18
17
F14
18
A17
17-Segment LED Display
(see Appendix A, Figure 27, D13)
General-purpose FPGA pins are connected to a 17-segment display according to Table 14. These pins can be
driven low to illuminate the display segments.
Table 14. 17-Segment LED Display
Segment
BGA
A
B7
B
F8
C
F7
D
A4
E
A3
F
H8
G
G7
H
C8
K
D8
M
B4
N
C5
P
C6
R
D6
S
C4
T
D5
U
C7
DP
B6
A
H
B
K M N
U
G
P
T S
F
C
R
E
D
DP
Logic Analyzer Probe
(see Appendix A, Figure 27, LA1)
An AMP/TYCO 767004 38-position .025 VERT SMD logic analyzer probe connection is provided for the user to utilize for test points. This connection provides 34 general I/O signals to be observed on a Logic Analyzer probe using
Mictor connections such as the Agilent 5346A.
19
LatticeECP3 PCI Express Solutions Board – Revision A
User’s Guide
Table 15. Logic Analyzer To FPGA Pin Reference
Signal
FPGA Pin
Signal
FPGA Pin
LA1
AA25
LA2
Y24
LA3
W23
LA4
W22
LA5
AA26
LA6
AB26
LA7
W21
LA8
W20
LA9
AD26
LA10
AD25
LA11
AA24
LA12
AA23
LA13
AC26
LA14
AC25
LA15
Y19
LA16
Y20
LA17
AB24
LA18
AC24
LA19
Y22
LA20
AA22
LA21
AE25
LA22
AF24
LA23
AD24
LA24
AE24
LA25
AD23
LA26
AC23
LA27
AB20
LA28
AB21
LA29
AF23
LA30
AE23
LA31
W17
LA32
AB23
LA33
AB22
LA34
Y21
DDR2 Memory Devices
(see Appendix A, Figure 26, U14)
• The LatticeECP3 PCI Express Solutions Board is equipped with a 84-ball BGA DDR2 SDRAM memory device
such as a Micron MT47H16M16BG-3 device.
• The DDR2 memory interfaces include a 16-bit wide device.
• The evaluation board includes termination of address and command signals. It includes all power and external
components needed to demonstrate the memory controller of the LatticeECP3 device.
CPLD Device
(see Appendix A, Figure 24, U12)
The board includes a Lattice Semiconductor LCMXO-1200C CPLD. This device is used in conjunction with the parallel Flash device for loading the configuration memory of the FPGA. It is also used for general-purpose board
management functions. It has several connections to the FPGA and other devices on the PCB. It includes an active
high, push-button (SW4) if needed for a user design.
Generic user-defined interconnections are defined in Table 16.
20
LatticeECP3 PCI Express Solutions Board – Revision A
User’s Guide
Table 16. CPLD TO FPGA Interconnections
CPLD Pin
FPGA Pin
M1
B2
P13
B3
P10
D4
N7
E4
N8
C3
P11
D3
N13
G5
N1
G6
N3
E3
N4
F4
P1
H6
M12
J6
M2
C2
M3
D2
M4
K8
M6
J7
Ordering Information
Description
Ordering Part Number
LatticeECP3 PCI Express Development Kit
(Includes LatticeECP3 PCI Express Solutions
Board)
China RoHS Environment-Friendly
Use Period (EFUP)
LFE3-95EA-PCIE-DKN
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
+1-503-268-8001 (Outside North America)
e-mail:
techsupport@latticesemi.com
Internet: www.latticesemi.com
Revision History
Date
Version
Change Summary
March 2010
01.0
Initial release.
December 2010
01.1
LED definitions table, L0 state changed from active to inactive.
Download Procedures section, changed ispVM requirement from ispVM
v.17.4 (or later) to ispVM v.17.7 (or later).
August 2012
01.2
Updated document with new corporate logo.
Replaced Programming schematic.
© 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as
listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of
their respective holders. The specifications and information herein are subject to change without notice.
21
22
A
B
C
5
CH0
PCIe-X1
LOOPS
CH1, CH2
CH3
PCIe-X4
PCIE_CLOCK
PCSA
PCSB
PCIE_CLOCK
STATUS LEDs
100MHZ
GENERAL
OSC.
DIP SWITCH
4
LOGIC ANALYZER PROBE
16- GPIO HEADER
SMA CLOCK
4
16-bit DDR2
D
5
JTAG/ISPVM
16-SEGMENT DISPLAY
3
3
2
2
Date:
Size
C
Title
Thursday, May 21, 2009
1
Sheet
1
ECP3 PCIe DevKit Eval Board
Project
Cover Page
of
9
Rev
1.0
1605 Valley Center Parkway
Bethlehem, PA 18017
1
A
B
C
D
LatticeECP3 PCI Express Solutions Board – Revision A
User’s Guide
Appendix A. Schematic
Figure 20. Cover Page
A
B
C
D
TestPoint
TestPoint
TestPoint
TestPoint
TestPoint
TestPoint
LP2
1
1
1
LP3
1
5016
5
1
5016
1
1
5016
LP5
1
1_2V_A
1_8V
TestPoint
TestPoint
TestPoint
TestPoint
TestPoint
TestPoint
1
1
TP12
1
TP10
1
1
TP8
TP6
1
TP4
1
TP2
1
5016
LP4
1
1
5016
LP1
1
1
1
TP11
1
TP9
TP7
TP5
TP3
TP1
VCC_CORE
3_3V
GND Pads
Distributed around the board
8
R1
1_8K-1206SMT
G
1.2V
VCC_CORE
1
2
3
4
5
6
7
GND
VIN
3.3V
R21
10K-0603SMT
SENSE
VOUT
4
C7
F3
Q1
2N2222/SOT23
R3
1_8K-1206SMT
+
+
8
330UF-FKSMT
C3
C6
+
10UF-16V-TANTBSMT
3_3V
R8
1
10K-0603SMT
1_2V_A
LED-SMT1206_GREEN
D4
1.2V
Analog
F4
F1228CT-ND
5A Fast-Blo SMT Socketed Fuse
330UF-FKSMT
C8
+
1_8V
R10 0R-0603SMT
F1228CT-ND
5A Fast-Blo SMT Socketed Fuse
1.8V
3_3VIN
806R-0603SMT
R18
3_3V
5
6
R7
1
10K-0603SMT
LED-SMT1206_GREEN
D3
1_8V
1.8V
R2
1_8K-1206SMT
10UF-16V-TANTBSMT
1K-0603SMT
R17
12_0V
G
Q3
2N2222/SOT23
R14
2K-0603SMT
PTH12060W
1_8V
1_8_TRIM
R15
100R-0805SMT
GND
R12
OPEN-0805SMT
1
2
U3
R6
1
10K-0603SMT
LED-SMT1206_GREEN
D2
VCC_CORE
12_0V
ILIM
IN
CNTL
GND
OUT
SENSE
EN
SC1592
TAB
U4
Q2
2N2222/SOT23
3
2
G
3
2
3
2
12_0V
3
ILIM
IN
CNTL
GND
OUT
SENSE
EN
1
2
3
4
5
6
7
R5
220R-0603SMT
3.3V
D1
R22
10K-0603SMT
1
2
U2
12_0V
GND
VIN
+
1.2V
Analog
C9
5
2
12_0VIN
VCC_CORE
1
+
F5
F1228CT-ND
5A Fast-Blo SMT Socketed Fuse
330UF-FKSMT
C10
+
1_2V_A
J1
330UF-FKSMT
C5
+
C1
Date:
Size
C
Title
GND
+12VDC
+
100UF-FKSMT
12_0V
F1
F1251CT-ND
10A Fast-Blo SMT Socketed Fuse
Thursday, March 26, 2009
1
Sheet
2
of
9
Rev
1.0
1605 Valley Center Parkway
Bethlehem, PA 18017
1
ECP3 PCIe DevKit Eval Board
Project
Power Generation
C2
12_0V
Terminal Block/ED1202DS
TB1
470UF-FKSMT
+
12_0V
2
1
12_0VIN
POWER INPUT
D33
SCHOTTKY/VISHAY-V12P10
F1228CT-ND
5A Fast-Blo SMT Socketed Fuse
R9
F2
0R-0603SMT
C4
10UF-16V-TANTBSMT
SENSE
6
1.2V
Core
Male Power Jack 2.1mm
22HP037-2.1mm 3
R13
12_1K-0603SMT
PTH12060L
2K-0603SMT
R20
3_3V
R4
VOUT
LED-SMT1206_GREEN
D5
12VIN GOOD
2
12_0V
1_8K-1206SMT
10UF-16V-TANTBSMT
1K-0603SMT
R19
VCCA_TRIM
12_0V
R11
OPEN-0805SMT
1_2V_A
R16
100R-0805SMT
GND
LED-SMT1206_GREEN
SC1592
TAB
U5
G
3_3V
9
12_0V
3
MUP
4
G
POWER RAIL GOOD INDICATORS
MUP
10
INHIBIT#
3
8
TRACK
9
MDWN
ADJUST
4
GND
7
10
INHIBIT#
3
MDWN
ADJUST
4
8
TRACK
12_0V
3_3V
23
3_3V
GND
7
2
5
A
B
C
D
LatticeECP3 PCI Express Solutions Board – Revision A
User’s Guide
Figure 21. Power Generation
A
B
C
5
C32
VCC_CORE
K11
K12
K13
K14
K15
K16
L10
L11
L12
L15
L16
L17
M11
M16
N10
N17
P10
P17
R11
R16
T10
T11
T12
T15
T16
T17
U11
U12
U13
U14
U15
U16
VCCA
VCCA
VCCA
VCCA
VCCA
VCCA
VCCA
VCCA
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCPLL_L
VCCPLL_L
VCCPLL_R
VCCPLL_R
C28
C35
ECP3-672fpBGA
U1J
C49
C50
C51
C52
C33
1_2V_A
V13
V14
W12
W13
W14
W15
Y13
Y14
J11
J16
J18
J9
L18
L9
T18
T9
V11
V16
V18
V9
M10
R10
M17
R17
VCC_PLL
3_3V
C62
C63
C64
C65
C53
C66
10NF-0603SMT
C54
C67
10NF-0603SMT
C34
C68
10NF-0603SMT
C55
+ C29
22UF-16V_TANTBSMT
C79
C82
C80
C84
C85
C86
+ C81
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
C83
100NF-0603SMT
100NF-0603SMT
10NF-0603SMT
10NF-0603SMT
C78
MH2
M HOLE2
MH1
M HOLE2
4
C77
VCC_PLL
M HOLE2
MH3
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
C61
10NF-0603SMT10NF-0603SMT
10NF-0603SMT
10NF-0603SMT
FB1
BLM41PG600SN1
3_3V
C31
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
100NF-0603SMT
100NF-0603SMT 100NF-0603SMT 100NF-0603SMT
100NF-0603SMT
100NF-0603SMT
C30
VCC_CORE
ECP3-672fpBGA
U1I
22UF-16V_TANTBSMT
ECP3-672fpBGA
U1K
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
3
3
A2
A25
AA13
AA14
AA18
AA19
AA21
AA6
AA8
AA9
AB19
AB2
AB25
AB8
AC11
AC12
AC13
AC14
AC15
AC16
AC19
AC20
AC21
AC22
AC5
AC6
AC7
AC8
AD22
AD5
AE1
AE10
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE26
AE5
AE6
AE7
AE8
AE9
AF2
AF22
AF25
AF5
B1
B14
B18
B22
B26
B5
B9
D11
D16
D20
D7
E2
E25
F21
F6
G12
G15
G23
G4
H18
H9
J12
J15
J19
J2
J25
J8
K10
K17
L13
L14
L23
L4
M12
M13
M14
M15
M18
M20
M7
M9
N11
N12
N13
N14
N15
N16
N2
P11
P12
P13
P14
P15
P16
P25
R12
R13
R14
R15
R20
R7
R9
T13
T14
T19
T23
T4
U17
V12
V15
V19
V2
V25
W11
W16
Y10
Y11
Y12
Y15
Y16
Y17
Y18
Y23
Y4
Y9
C20
C12
C13
3_3V
1_8V
C15
C21
C22
C37
C38
C39
C23
C40
10NF-0603SMT
C41
C46
C47
C57
C58
C59
C60
C73
C74
C70
2
100NF-0603SMT
100NF-0603SMT
10NF-0603SMT
10NF-0603SMT
C72
C24
C17
C43
C25
C76
100NF-0603SMT 10NF-0603SMT
C75
+ C69
+ C44
10NF-0603SMT
100NF-0603SMT 10NF-0603SMT
C42
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
C56
100NF-0603SMT
100NF-0603SMT
10NF-0603SMT
10NF-0603SMT
C45
C16
10NF-0603SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
C36
C14
C18
Date:
Size
C
Title
C71
C48
C26
22UF-16V_TANTBSMT
Monday, February 23, 2009
1
Sheet
3
of
9
Rev
1.0
1605 Valley Center Parkway
Bethlehem, PA 18017
1
ECP3 PCIe DevKit Eval Board
Project
Power Supplies
+ C27
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
C11
10NF-0603SMT 10NF-0603SMT
10NF-0603SMT
10NF-0603SMT
C19
1_2V_A
2
1UF-16V-0805SMT
1UF-16V-0805SMT
4
1UF-16V-0805SMT
22UF-16V_TANTBSMT
22UF-16V_TANTBSMT
24
1UF-16V-0805SMT
D
5
A
B
C
D
LatticeECP3 PCI Express Solutions Board – Revision A
User’s Guide
Figure 22. Power Supplies
1UF-16V-0805SMT
A
B
C
Q4
2N2222/SOT23
D9
220R-0603SMT
G
3
C87
2
R31
10K-0603SMT
DONE
[5] GSRN
C88
3_3V
PROGRAMN
SW1
FPGA GSRN
5
6
3
SW PUSHBUTTON-SPST
SW3
PROGRAMN
SW PUSHBUTTON-SPST
SW7
SW PUSHBUTTON-SPST
SW1 and SW3 on Primary Side
SW6 and SW7 on Secondary Side
GSRN
SW6
SW PUSHBUTTON-SPST
PROGRAMN
& GSRN
Pushbuttons
FPGA_CSSPI0N_DI
SPI0_Q
FLASH_DIS
D8
2Y
1Y
1
2
3
4
5
6
7
8
U6
5
4
2
1
3
1
SN74LVC125A/SO14
2A
2OE_N
1A
1OE_N
U9A
3_3V
M25P64-FLASH
HOLD# CK
VCC
D
DU8
DU1
DU2
DU7
DU6
DU3
DU4
DU5
S#
VSS
Q
W#
OUT2
OUT1
MAX6817
IN2
IN1
U7
16
15
14
13
12
11
10
9
4
6
SPI_CLK
FPGA_SISPI
R32
R33
R34
10K-0603SMT
10K-0603SMT
10K-0603SMT
3_3V
680R-0603SMT
R24
LED-SMT1206_RED
SPI FLASH
CONFIG
Status LEDs
1
D7
Y
PROGRAMN
LED-SMT1206_RED
DONE indicator will light when
configuration is successfully
completed
R39
10K-0603SMT
D
100NF-0603SMT
R26
LED-SMT1206_GREEN
10NF-0603SMT
LED-SMT1206_RED
R44
INITN
C89
11
8
3_3V
4Y
3Y
3_3V
4
CFG1
CFG0
R48
10K-0603SMT
R49
10K-0603SMT
0(ON)
1(OFF)
1(OFF)
X
0(ON)
1(OFF)
0(ON)
1(OFF)
X
ON
CFG2
CFG1
1(OFF)
1(OFF)
0(ON)
0(ON)
CFG0
X
[5]
R27
10K-0603SMT
3_3V
SW2INS38259285
SW DIP-3 CTS 194-3MST
ispJTAG
3
Slave Parallel
Slave Serial
SPIm
SPI Flash
Configuration Mode
R35
10K-0603SMT
R28
10K-0603SMT
FPGA_WRITEN
R29
10K-0603SMT
4
6
OUT Y2
OUT Y1
[5] TCK_BUF
TCK_BUF
TMS_BUF
4
6
OUT Y2
OUT Y1
NC7WZ16-MACO6A/Fairchild TinyLogic
R47
220R-0603SMT
D10
LED-SMT1206_GREEN
This LED
indicates activity
on TDI.
TDI_BUF
NC7WZ16-MAAO6A/Fairchild TinyLogic
JTAG
3_3V
[5] TMS_BUF
FPGA_SISPI
FPGA_D7
SPI0_Q
FPGA_D7
FPGA_D6
FPGA_D5
FPGA_D4
FPGA_D3
FPGA_D2
FPGA_D1
FPGA_D[0..7] [5]
FPGA_D0
FPGA_MCLK
FPGA_WRITEN
FPGA_WRITEN [5]
FPGA_CSSPI1N_DOUT
FPGA_CSSPI0N_DI
FPGA_CSN
FPGA_CSN [5]
FPGA_CS1N
FPGA_CS1N [5]
GSRN
DONE
DONE [5]
FPGA_CCLK
INITN
INITN [5]
PROGRAMN
PROGRAMN [5]
CFG0
CFG1
CFG[0..2] [5]
CFG2
FPGA_D15
FPGA_D14
FPGA_D[8..15] [5]
FPGA_D13
FPGA_D12
FPGA_D11
FPGA_D10
FPGA_D9
FPGA_D8
TMS_BUF
TDI_XO
TDI_XO [5]
TCK_BUF
TDI_BUF
FPGA_XRES
R46
10K-0603SMT
K21
K20
C26
B25
J22
J21
D26
D25
D23
C25
E24
D24
C24
H22
G22
C23
B24
A24
H21
J20
B23
A23
E21
F22
F23
E22
E23
G21
G20
D21
D22
E6
E7
E5
F5
R18
U10
V8
H19
H20
H7
FPGA_CCLK
CONFIG
CFG Switches
0(ON)
CFG2
3_3V
ECP3-672fpBGA
13
R45
10K-0603SMT
R43
4_7K-0603SMT
U1G
FPGA_CCLK
FPGA_MCLK
PR16B/BUSY/SISPI/AVDN
PR16A/D7/SPID0
PR14B/D6/SPID1
PR14A/D5
PR13B/D4/SO
PR13A/D3/SI
PR11B/D2
PR11A/D1
PR10B/D0/SPIFASTN
PR8B/MCLK
PR10A/WRITEN/OEN
PR8A/DOUT/CSON/CSSPI1N
PR5B/DI/CSSPI0N/CEN
PR7B/CSN/SN/CONT1N
PR7A/CS1N/HOLD/CONT2N
PR5A
DONE
CCLK
INITN
PROGRAMN
CFG0
CFG1
CFG2
PT145B
PT145A
PT143B
PT143A
PT142B
PT142A
PT140B
PT140A
TMS
TDO
TCK
TDI
XRES
TEMPSENSE
TEMPVSS
VCCIO8
VCCIO8
VCCJ
1
2
J2
HEADER 2X2
3
4
12
9
10
SN74LVC125A/SO14
4A
4OE_N
3A
3OE_N
U9B
FPGA_XRES
FPGA_CCLK
[5] LOADER_CK
[5] SPI_CLK
LOADER_CK
SPI_CLK
3_3V
FPGA_CS1N
R25
D6
680R-0603SMT
R
100NF-0603SMT
R38
10K-0603SMT
Y
GSRN
3_3V
R37
10K-0603SMT
3_3V
R41
OPEN-0603SMT
R36
10K-0603SMT
R42
OPEN-0603SMT
3
3_3V
3_3V
U8
IN A2
IN A1
2
IN A2
2
U10
IN A1
3
1
3
1
1
2
HEADER 2
J3
C90
100NF-0603SMT
4
[5] TDO_XO
SPIFASTN
R30
FPGA_D0
3
EXBV8V472JV
Date:
Size
C
5
1
1
5
+3.3V
TDO
TDI
TMS
GND
TCK
Primary
Component
HEADER 6 Side
J4
Secondary
Component
Side
100NF-0603SMT
C91
3_3V
Thursday, August 09, 2012
1
Sheet
4
ECP3 PCIe DevKit Eval Board
of
9
Rev
1.0
1605 Valley Center Parkway
Bethlehem, PA 18017
FROM ISPVM CABLE
Progamming
Project
J8
1
HEADER 6
6
2
3
4
6
4.7K
LOCAL_TCK
4.7K
4
2
3
4
Title
4.7K
RN1D
LOCAL_TDI
LOCAL_TMS
4.7K
3_3V
10K-0603SMT
2
680R-0603SMT
R23
4_7K-0603SMT
5
VCC
RN1B
INITN indicator will light
if an error occurs during
configuration programming
R50
GND
2
R51
100R-0603SMT
5
FPGA_CSN
R
RN1C
3_3V
100R-0603SMT
6
5
4
1
2
3
4_7K-0603SMT
R40
GND
7
14
VCC
C92
VCC
GND
2
5
VCC
GND
2
FPGA_D[8..15]
100NF-0603SMT
1
RN1A
25
8
INITN
7
DONE
6
PROGRAMN
5
5
A
B
C
D
LatticeECP3 PCI Express Solutions Board – Revision A
User’s Guide
Figure 23. Programming
A
B
C
5
4
2
Momentary Switch
B3F-1150
3
1
SW4
CPLD RESET
3_3V
R53
0R-0603SMT
3_3V
[4] FPGA_D[8..15]
[8] FPGA_[0:15]
3_3V
[4] SPI_CLK
[4] FPGA_CCLK
[4] CFG[0..2]
R55
2_2K-0603SMT
[4] LOADER_CK
[4] PROGRAMN
[4] FPGA_D[0..7]
R52
OPEN-0603SMT
C101
100NF-0603SMT
FPGA_D[8..15]
[4] TCK_BUF
[4] TDI_XO
[4] TDO_XO
[4] TMS_BUF
[4] GSRN
[4] DONE
4
N14
GSRN
CFG0
CFG1
CFG2
FPGA_0
FPGA_1
FPGA_2
FPGA_3
FPGA_4
FPGA_5
FPGA_6
FPGA_7
FPGA_8
FPGA_9
FPGA_10
FPGA_11
FPGA_12
FPGA_13
FPGA_14
FPGA_15
TMS_BUF
R57
1K-0603SMT
TCK_BUF
TDI_XO
A4
M7
M1
P13
P10
N7
N8
P11
N13
N1
N3
N4
P1
M12
M2
M3
M4
M6
H12
H13
M13
N6
M14
B1
L3
A3
A2
M9
P4
M5
N5
P3
N12
K12
A1
INITN
DONE
J2
G1
A5
P8
M8
J3
K1
E3
B7
P5
H2
FPGA_D0
FPGA_D1
FPGA_D2
FPGA_D3
FPGA_D4
FPGA_D5
FPGA_D6
FPGA_D7
LOADER_CK
PROGRAMN
[4] INITN
C6
C2
K14
P12
L14
M11
G2
E2
FPGA_D15
FPGA_D14
FPGA_D13
FPGA_D12
FPGA_D11
FPGA_D10
FPGA_D9
FPGA_D8
4
U12
G12
VCC
H3
VCC
NC
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
SPI_CLK
FPGA_CLK
CFG0
CFG1
CFG2
TCK
TDI
TDO
TMS
SLEEPN
FUNC_RESET
FPGA_RESETN
FPGA_DONE
FPGA_INITN
TSALL
FPGA_DATA_0
FPGA_DATA_1
FPGA_DATA_2
FPGA_DATA_3
FPGA_DATA_4
FPGA_DATA_5
FPGA_DATA_6
FPGA_DATA_7
FPGA_CCLK
FPGA_PROGRAMN
FPGA_D15
FPGA_D14
FPGA_D13
FPGA_D12
FPGA_D11
FPGA_D10
FPGA_D9
FPGA_D8
C7
VCC
C93
A7
VCCAUX
P6
VCC
C94
10NF-0603SMT
C95
100NF-0603SMT
Lattice
FPGA
Loader
LCMXO1200C-CSBGA132
C96
3
C97
100NF-0603SMT
FLASH_DQ_15
FLASH_DQ_14
FLASH_DQ_13
FLASH_DQ_12
FLASH_DQ_11
FLASH_DQ_10
FLASH_DQ_9
FLASH_DQ_8
FLASH_DQ_7
FLASH_DQ_6
FLASH_DQ_5
FLASH_DQ_4
FLASH_DQ_3
FLASH_DQ_2
FLASH_DQ_1
FLASH_DQ_0
CLOCK
FLASH_WE_N
FLASH_WP_N_ACC
FLASH_RESET_N
FLASH_OE_N
FLASH_CEm
FLASH_RD/BY
FLASH_BYTEn
FLASH_CE1_N
FLASH_CE0_N
FLASH_ADDRESS_0
FLASH_ADDRESS_1
FLASH_ADDRESS_2
FLASH_ADDRESS_3
FLASH_ADDRESS_4
FLASH_ADDRESS_5
FLASH_ADDRESS_6
FLASH_ADDRESS_7
FLASH_ADDRESS_8
FLASH_ADDRESS_9
FLASH_ADDRESS_10
FLASH_ADDRESS_11
FLASH_ADDRESS_12
FLASH_ADDRESS_13
FLASH_ADDRESS_14
FLASH_ADDRESS_15
FLASH_ADDRESS_16
FLASH_ADDRESS_17
FLASH_ADDRESS_18
FLASH_ADDRESS_19
FLASH_ADDRESS_20
FLASH_ADDRESS_21
FPGA_CSN
FPGA_CS1N
FPGA_WRITEN
10NF-0603SMT
K3
100NF-0603SMT
N2
3
D2
VCCIO7
3_3V
P7
VCCAUX
GND
D13
FPGA_D[0..7]
C5
VCCIO0
GND
E1
GND
B4
B11
VCCIO1
GND
F1
GND
A10
E12
VCCIO2
GND
J14
GND
C9
L12
VCCIO3
GND
L2
VCCIO5
GND
M10
VCCIO4
GND
L13
VCCIO6
GND
P2
GND
P9
26
N11
D
5
C98
FLASH_D15
FLASH_D14
FLASH_D13
FLASH_D12
FLASH_D11
FLASH_D10
FLASH_D9
FLASH_D8
FLASH_D7
FLASH_D6
FLASH_D5
FLASH_D4
FLASH_D3
FLASH_D2
FLASH_D1
FLASH_D0
FLASH_CLK
FLASH_WE_N
FLASH_WP_N_ACC
FLASH_RESET_N
FLASH_OE_N
FLASH_CEm
FLASH_RD/BY
FLASH_BYTEn
E14
D12
J12
G14
J13
F14
F13
E13
D3
C4
J1
H1
N9
K13
G13
G3
A8
K2
L1
P14
C1
B2
D1
F2
F3
C3
FLASH_CLK
[9]
FLASH_A[0..21]
FPGA_CSN [4]
FPGA_CS1N [4]
FPGA_WRITEN [4]
FLASH_A0
FLASH_A1
FLASH_A2
FLASH_A3
FLASH_A4
FLASH_A5
FLASH_A6
FLASH_A7
FLASH_A8
FLASH_A9
FLASH_A10
FLASH_A11
FLASH_A12
FLASH_A13
FLASH_A14
FLASH_A15
FLASH_A16
FLASH_A17
FLASH_A18
FLASH_A19
FLASH_A20
FLASH_A21
B6
A6
B3
B5
A9
B9
C10
B10
C11
A11
D14
C8
A14
B8
C14
B12
C13
A13
B13
A12
C12
B14
F12
H14
N10
10NF-0603SMT
2
FLASH_A21
FLASH_A20
FLASH_A19
FLASH_A18
FLASH_A17
FLASH_A16
FLASH_A15
FLASH_A14
FLASH_A13
FLASH_A12
FLASH_A11
FLASH_A10
FLASH_A9
FLASH_A8
FLASH_A7
FLASH_A6
FLASH_A5
FLASH_A4
FLASH_A3
FLASH_A2
FLASH_A1
FLASH_A0
2
H6
H1
C4
D3
D4
C3
B2
E6
D6
C6
A6
B6
D5
C5
A5
B5
A2
C2
D2
B1
A1
C1
D1
E1
U11
VCC
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
CEn
OEn
WEn
RD/BY
BYTEn
WPn
RESETn
FLASH_D[0..15]
S29GL064A
GND
GND
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
G4
G6
F5
G5
F4
G3
F3
G2
F2
E5
H5
E4
H4
H3
E3
H2
E2
F1
G1
A4
A3
F6
B3
B4
Date:
Size
C
Title
3_3V
C99
C100
Monday, February 23, 2009
1
Sheet
5
ECP3 PCIe DevKit Eval Board
Project
of
9
Rev
1.0
1605 Valley Center Parkway
Bethlehem, PA 18017
R54
10K-0603SMT
3_3V
FLASH_D[0..15]
10NF-0603SMT
Parallel FPGA Loader
FLASH_D15
FLASH_D14
FLASH_D13
FLASH_D12
FLASH_D11
FLASH_D10
FLASH_D9
FLASH_D8
FLASH_D7
FLASH_D6
FLASH_D5
FLASH_D4
FLASH_D3
FLASH_D2
FLASH_D1
FLASH_D0
FLASH_CEm
FLASH_OE_N
FLASH_WE_N
FLASH_RD/BY
FLASH_BYTEn
FLASH_WP_N_ACC
FLASH_RESET_N
100NF-0603SMT
1
A
B
C
D
LatticeECP3 PCI Express Solutions Board – Revision A
User’s Guide
Figure 24. Parallel FPGA Loader
R56
1K-0603SMT
27
A
B
C
[8] PCIE_PERSTN
PCSA_HDOUTP0
PRSNT1#
+12V
+12V
GND
JTAG2
JTAG3
JTAG4
JTAG5
+3.3V
+3.3V
PERST#
GND
REFCLK+
REFCLKGND
PERp0
PERn0
GND
CN2
+12V
+12V
RSVD_B3
GND
SMCLK
SMDAT
GND
+3.3V
JTAG1
3.3Vaux
WAKE#
RSVD_B12
GND
PETp0
PETn0
GND
PRSNT3#
GND
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
C127
x1_PETp0
x1_PETn0
PCIE_3V3
x1_PERn0
x1_PERp0
X1 PCIe Board Fingers
PCI Express x1 Edge Finger Conn.
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
C126
100NFX5R-0402SMT
100NFX5R-0402SMT
1
5
AD21
AD20
AD18
AD19
AD17
AD16
AD14
AD15
AF21
AF20
AF18
AF19
AF17
AF16
AF14
AF15
AC17
AC18
AB18
AA16
AA15
AB14
AA17
AB17
AB16
AB15
AD13
AD12
AD10
AD11
AD9
AD8
AD6
AD7
AF13
AF12
AF10
AF11
AF9
AF8
AF6
AF7
AC9
AC10
AB13
AB11
AA11
AB9
AB12
AA12
AB10
AA10
TP14
TESTPOINT
PCSB_VCCOB
PCSB_VCCIB
x1_PRSNTn
x4_PETp0
x4_PETn0
x4_PETp1
x4_PETn1
x4_PETp2
x4_PETn2
x4_PETp3
x4_PETn3
PCSB_HDOUTP0
PCSB_HDOUTN0
PCSB_HDOUTP1
PCSB_HDOUTN1
PCSB_HDOUTP2
PCSB_HDOUTN2
PCSB_HDOUTP3
PCSB_HDOUTN3
x4_PCIE_CLKP
x4_PCIE_CLKN
PCSA_VCCOB
PCSA_VCCIB
x1_PETp0
x1_PETn0
LOOP1_P
LOOP1_N
LOOP2_P
LOOP2_N
LOOP3_P
LOOP3_N
PCSA_HDOUTP0
PCSA_HDOUTN0
LOOP1_P
LOOP1_N
LOOP2_P
LOOP2_N
LOOP3_P
LOOP3_N
x1_PCIE_CLKP
x1_PCIE_CLKN
[8]
PRSNT1#
+12V
+12V
GND
JTAG2
JTAG3
JTAG4
JTAG5
+3.3V
+3.3V
PERST#
GND
REFCLK+
REFCLKGND
PERp0
PERn0
GND
RSVD_A19
GND
PERp1
PERn1
GND
GND
PERp2
PERn2
GND
GND
PERp3
PERn3
GND
RSVD_A32
CN1
4
C113
C119
PCSB_VCCIB
C120
C121
+12V
+12V
RSVD_B3
GND
SMCLK
SMDAT
GND
+3.3V
JTAG1
3.3Vaux
WAKE#
RSVD_B12
GND
PETp0
PETn0
GND
PRSNT3#
GND
PETp1
PETn1
GND
GND
PETp2
PETn2
GND
GND
PETp3
PETn3
GND
RSVD_B30
PRSNT4#
GND
x4_PETp3
x4_PETn3
x4_PETp2
x4_PETn2
x4_PETp1
x4_PETn1
x4_PETp0
x4_PETn0
PCIE_3V3
X4 PCIe Board Fingers
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
1
TP13
TESTPOINT
100NF-0603SMT
100NF-0603SMT
10NF-0603SMT
10NF-0603SMT
C118
PCI Express x4 Edge Finger Conn.
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
C112
C107
PCSA_VCCOB
C103
x4_PRSNTn
3
2
100NF-0603SMT
C124
PCSB_HDOUTN3
PCSB_HDOUTP3
PCSB_HDOUTN2
PCSB_HDOUTP2
PCSB_HDOUTN1
PCSB_HDOUTP1
PCSB_HDOUTN0
PCSB_HDOUTP0
10NF-0603SMT
C123
100NF-0603SMT
C116
C109
PCSB_VCCOB
C105
PCSB_VCCIB
10NF-0603SMT
C115
+ C108
+ C104
[8]
100NF-0603SMT
C122
PCSB_VCCOB
100NF-0603SMT
C114
PCSA_VCCOB
FB5
BLM41PG600SN1
1_2V_A
FB3
BLM41PG600SN1
1_2V_A
2
B side = Secondary Component Side(BOTTOM)
A side = PRIMARY Component Side(TOP)
x4_PERp3
x4_PERn3
x4_PERp2
x4_PERn2
x4_PERp1
x4_PERn1
x4_PERp0
x4_PERn0
x4_PCIE_CLKP
x4_PCIE_CLKN
PCIE_PERSTN
PCIE_3V3
12_0V
C111
PCSA_VCCIB
+ C106
+ C102
PCSA_VCCIB
100NF-0603SMT
100NF-0603SMT
10NF-0603SMT
10NF-0603SMT
C110
FB4
BLM41PG600SN1
1_2V_A
FB2
BLM41PG600SN1
1_2V_A
All Nets are 85-ohm differential pairs.
The P and N traces shall be
工商网监
湘ICP备2023018690号