LFE3-ADC-DAC-EVN

 LatticeECP3™ I/O Protocol Board – Revision C User’s Guide March 2012 Revision: EB48_01.4  LatticeECP3 I/O Protocol Board – Revision C User’s Guide Introduction The LatticeECP3™ I/O Protocol Board provides a convenient platform to evaluate, test and debug user designs and IP cores targeted for the LatticeECP3-150 FPGA. The board features a LatticeECP3-150 FPGA in the 1156 fpBGA package. The LatticeECP3 I/Os are connected to a rich variety of both generic and application-specific interfaces described later in this document. Important: This document (including the schematics in the appendix) describes LatticeECP3 I/O Protocol Boards marked as Rev C. This marking can be seen on the silkscreen of the printed circuit board, under the Lattice Semiconductor logo. The LatticeECP3 is a third-generation device utilizing reconfigurable SRAM logic technology optimized to deliver high performance features such as an enhanced DSP architecture, high speed SERDES and high speed source synchronous interfaces in an economical FPGA fabric. The LatticeECP3 devices also provide popular building blocks such as LUT-based logic, distributed and embedded memory, Phase Locked Loops (PLLs), Delay Locked Loops (DLLs), and advanced configuration support, including encryption, multi-boot capabilities and TransFR™ field upgrade features. The LatticeECP3 SERDES dedicated PCS functions, high jitter tolerance and low transmit jitter allow the SERDES plus PCS blocks to be configured to support an array of popular data protocols including PCI Express, SMPTE, Ethernet (XAUI, GbE, and SGMII), SATA I/II, OBSAI and CPRI. Transmit Pre-emphasis and Receive Equalization settings make the SERDES suitable for transmission and reception over various forms of media. For a full description of the LatticeECP3 FPGA, see the Lattice website at www.latticesemi.com for the LatticeECP3 Family Data Sheet, technical notes and more. Some common uses for the LatticeECP3 I/O Protocol Board include: • Applications requiring large DDR3 memory width and depth • High-speed parallel ADC/DAC Interface • SERDES data transfer with external devices • 1000base-T PHY/RJ45 networking • A single-board computer system • A platform for evaluating the Input/Output (I/O) characteristics of the FPGA • A platform for evaluation and development with Lattice IP cores Features Key features of the LatticeECP3 I/O Protocol Board include: • SPI Serial Flash device included for low-cost, non-volatile LatticeECP3 configuration storage • Two 64-bit DDR3 DIMM module sockets • Tri-speed (10/100/1000 Mbit) Ethernet PHY with RJ-45 (includes 12 core magnetics) • USB 2.0 transceiver • Built-in USB 2.0 download for LatticeECP3 and ispPAC® bitstreams. • Also includes ispDOWNLOAD™ JTAG headers for LatticeECP3, ispPAC, and MachXO™ bitstreams • High-speed HMZD connector with 80 differential pair connections and selectable VTT voltage • 8-pin DIP switch and three user-definable debounced pushbuttons • Discrete LEDs and 7-segment LED • LCD module connector 2 LatticeECP3 I/O Protocol Board – Revision C User’s Guide • Prototyping areas with 125 spare test point I/O pins • 1 selectable user I/O bank voltage with access to 2 VREF test points • Logic analyzer probe connection • 5 pairs of high-speed differential I/O using SMA connectors • 5 crystal oscillators • 2 selectable high-speed differential external clock sources with PLL feed back inputs • 4 channels (1 quad) of differential SERDES (TX and RX) using SMA connectors • 1 high-current high-speed I/O connection using an SMA connector • 3.3V, 2.5V, 1.5V, 1.2V and DDR3 voltages are generated from a single 12V power source • 3 fixed or adjustable DDR3 reference voltages • 1 Mbit serial EEPROM for general data storage over I2C bus • Power Manager II ispPAC-POWR1220AT8 chip for monitoring input power and regulator outputs to be within nominal tolerance with programmable trims • ispVM™ System programming support • Multi-board JTAG programming capability and sysCONFIG™ connector General Description The heart of the board is the LatticeECP3 FPGA. The board also provides several different interconnections and support devices that permit it to be used for a variety of purposes. The DDR3 sockets, and Tri-speed Ethernet PHY are useful for applications using Lattice IP cores. A number of connectors are useful for general purpose LatticeECP3 I/O capability. These include the SMA, USB, Ethernet PHY, LCD connector, and the various generic prototype access points. Other features on the board help in evaluating the capabilities and performance of the LatticeECP3. The 4 channels of SERDES PCS allow straight forward, flexible, high data rate connections to external devices. The various SMA connectors permit the evaluation of high-speed differential signals, and protocols. The HMZD connector provides a wide parallel data path for up to 80 high-speed differential signal connections with easy bench top board to board plug in expansion with low signal skew. The SPI memory showcases the fail-safe capabilities of the LatticeECP3. The board also acts as a showcase for the ispPAC-POWR1220 Power Manager. The ispPAC-POWR1220 is a programmable device useful for safely managing the power supply system on the board. It can be programmed to sequence, monitor, and adjust the voltages on the LatticeECP3 I/O Protocol Board. Additional resources for the LatticeECP3 I/O Protocol Board, such as updates to this document, sample programs and links to demos can be found on the Lattice web site. Go to www.latticesemi.com/boards, and navigate to the appropriate page for this board. Initial Setup and Handling The following is recommended reading prior to removing the evaluation board from the static shielding bag and may or may not apply to your particular use of the board. CAUTION: The devices on the board can be damaged by improper handling. The devices on the evaluation board contain fairly robust ESD (Electro Static Discharge) protection structures within them, able to withstand typical static discharges (see the “Human Body Model” specification for an example of ESD characterization requirements). Even so, the devices are static sensitive to conditions that exceed their 3 LatticeECP3 I/O Protocol Board – Revision C User’s Guide designed-in protection. For example: higher static voltages, as well as lower voltages with lower series resistance or larger capacitance than the respective ESD specifications require can potentially damage or degrade the devices on the evaluation board. As such, it is recommended that you wear an approved and functioning grounded wrist strap at all times while handling the evaluation board when it is removed from the static shielding bag. If you will not be using the board for a while, it’s best to put it back in the static shielding bag. Please save the static shielding bag and packing box for future storage of the board when it is not in use. When reaching for the board, it is recommended that you first touch the outside threaded portion of one of the gold SMA connectors. This will neutralize any static voltage difference between your body and the board prior to any contact with signal I/O. CAUTION: To minimize the possibility of ESD damage, the first and last electrical connection to the board, should be always be from test equipment chassis ground to GND on the board (left side post of TB1 labeled GND on the board). Before connecting signals or power to the board, attach a cable from chassis ground on grounded test equipment to the GND on the board. Connecting the board ground to test equipment chassis ground will decrease the risk of ESD damage to the I/O on the board as the initial connections to the board are made. Likewise, when unplugging cables from the evaluation board, the last connection unplugged, should be the chassis GND connection to the evaluation board GND. If you have a signal source that is floating with respect to chassis GND, attempt to neutralize any static charge on that signal source prior to attaching it to the evaluation board. If you are holding or carrying the board when it is not in a static shielding bag, please keep one finger on the threaded portion of one of the gold SMA connectors. This will keep the board at the same voltage potential as your body until you can pick up the static shielding bag and put the board back inside. Electrical, Mechanical, and Environmental Specifications The nominal board dimensions are 8 inches by 8 inches. The environmental specifications are as follows: • Operating temperature: 0°C to 55°C • Storage temperature: -40°C to 75°C • Humidity: 3.3V 2-4 -> 2.5V 3-5 -> 1.5V 4-6 -> 1.2V None -> External 1 Table 6. sysIO Bank Voltages sysIO Bank Bank Voltage 0 1.5V 1 (J41 selects) 2 2.5V 3 2.5V SERDES 1.2V or 1.5V 6 1.5V 7 1.5V 8 3.3V Depending on the optional devices installed, some sysIO™ banks may have restrictions. For J41 only select one bank voltage position at the jumper. For example, attaching more than one jumper to J41’s 6 square pins could short supplies. You can also remove the jumper on J41 and apply an external voltage to pins 3 and 4 of J41. When applying an external voltage to J41, do not exceed the LatticeECP3 Family Data Sheet-specified absolute maximum rating for Output Supply Voltage VCCIO range of -0.5V to +3.75V, or damage to the device may occur. Table 7. sysIO Bank Considerations Bank Setting 1 Selectable, LCD may require 3.3V. The following tables detail the various I/O standards supported by the LatticeECP3 sysIO structures. More information can be found in TN1177, LatticeECP3 sysIO Usage Guide. Table 8. Mixed Voltage I/O Support Input sysIO Standards VCCIO 1.2V 1.2V Yes 1.5V Yes 1.8V Yes 2.5V Yes 3.3V Yes 1.5V 1.8V Yes Yes Output sysIO Standards 2.5V 3.3V 1.2V Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 1.5V 1.8V 2.5V 3.3V Yes Yes Yes Yes For example, if VCCIO is 3.3V then signals from devices powered by 1.2V, 2.5V, or 3.3V can be input and the thresholds will be correct, assuming the user has selected the desired input level using ispLEVER® software. Output levels are tied directly to VCCIO. 8 LatticeECP3 I/O Protocol Board – Revision C User’s Guide Table 9. sysIO Standards Supported per Bank Top Side Banks 0-1 Description Right Side Banks 2-3 Bottom Side Banks 4-5 Left Side Banks 6-7 Types of I/O Buffers Single-ended Single-ended and Differential Single-ended Single-ended and Differential Single-Ended Standards Outputs LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 SSTL15 SSTL18 Class I, II SSTL25 Class I, II SSTL33 Class I, II HSTL15 Class I HSTL18_I, II LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 SSTL15 SSTL18 Class I, II SSTL25 Class I, II SSTL33 Class I, II HSTL15 Class I HSTL18 Class I, II LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 SSTL15 SSTL18 Class I, II SSTL2 Class I, II SSTL3 Class I, II HSTL15 Class I HSTL18 Class I, II LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 SSTL15 SSTL18 Class I, II SSTL2 Class I, II SSTL3 Class I, II HSTL15 Class I HSTL18 Class I, II Differential Standards Outputs LVCMOS33D LVCMOS33D LVCMOS33D LVCMOS33D SSTL15D SSTL18D Class I, II SSTL25D Class I, II SSTL33D Class I, II HSTL15D Class I HSTL18D Class I, II SSTL15D SSTL18D Class I, II SSTL25D Class I, II SSTL33D Class I, II HSTL15D Class I HSTL18D Class I, II SSTL15D SSTL18D Class I, II SSTL25D Class I, II, SSTL33D Class I, II HSTL15D Class I HSTL18D Class I, II SSTL15D SSTL18D Class I, II SSTL25D Class I, II, SSTL33D_I, II HSTL15D Class I HSTL18D Class I, II LVDS25E1 LVPECL1 BLVDS1 RSDSE1 LVDS2 RSDS2 Mini-LVDS2 PPLVDS2 (point-to-point) LVDS25E1 LVPECL1 BLVDS1 RSDSE1 LVDS25E1 LVPECL1 BLVDS1 RSDSE1 LVDS2 RSDS2 Mini-LVDS2 PPLVDS2 (point-to-point) LVDS25E1 LVPECL1 BLVDS1 RSDSE1 Inputs All Single-ended and Differential TRLVDS (Transition Reduced LVDS) All Single-ended, Differential All Single-ended, Differential All Single-ended, Differential Clock Inputs All Single-ended, Differential All Single-ended, Differential All Single-ended, Differential All Single-ended, Differential Hot Socketing Yes Only on Bank 8 Yes No Equalization on Inputs No Yes No Yes ISI Correction For DDR3 memory For DDR3 memory For DDR3 memory For DDR3 memory On Chip Termination No On-Chip Parallel Termina- No tion On-Chip Parallel Termination On-Chip Differential  Termination On-Chip Differential  Termination PCI Support PCI33 with or without clamp PCI33 with clamp PCI33 with clamp PCI33 with clamp 1. These differential standards are implemented by using a complementary LVCMOS driver with the external resistor pack. 2. Available on 50% of the I/Os in the bank. Prototype Areas For general purpose I/O testing or monitoring, numerous test points are provided for direct access. Some test points are grouped together and arranged in a grid pattern according to their associated I/O bank and are labeled with the pin locations on the silkscreen of the board. Most test point I/Os are brought out to IDC connectors J54, 9 LatticeECP3 I/O Protocol Board – Revision C User’s Guide J55 and J57 with both source and end type termination resistors available for high-speed signal transmission over ribbon cables. Differential Signal Connections There are 17 pairs of SMA connectors and one HMZD connector that provide general purpose high-speed differential signal paths to the LatticeECP3. The SMA connectors are provided for SERDES, clocks and general purpose user-definable signals. The HMZD connector allows quick connection of 80 high-speed differentially paired signals to an external application PCB with low signal skew and good mechanical stability. Table 10 details the I/O pins to which each SMA connector is wired. Table 10. SMA Connectors Location LatticeECP3 I/O Polarity sysIO Bank J39 J45 Description E19 P 1 PT76A/PT94A/PCLKT1_0 E20 N 1 PT76B/PT94B/PCLKC1_0 J50 AA34 P 3 PR61E_A/PR79E_A/RLM1_GPLLT_FB_A J42 AA33 N 3 PR61E_B/PR79E_B/RLM1_GPLLT_FB_B J6 U5 P 7 PL43E_A/PL61E_A//LUM0_GPLLT_FB_A J12 U4 N 7 PL43E_B/PL61E_B//LUM0_GPLLT_FB_B J21 AH15 (from U8) P Quad B PCSB_REFCLKP J26 AH16 (from U8) N Quad B PCSB_REFCLKN J33 Y28 (from U8) U6 (from U8) P 3 7 PR61E_C/PR79E_C/RLM1_GPLLT_IN_A PL43E_C/PL61E_C/LUM0_GPLLT_IN_A J36 Y27 (from U8) U7 (from U8) N 3 7 PR61E_D/PR79E_D/RLM1_GPLLT_IN_B PL43E_D/PL61E_D/LUM0_GPLLT_IN_B J7 AL17 P Quad B PCSB_HDINP0 J13 AK17 N Quad B PCSB_HDINN0 J22 AL16 P Quad B PCSB_HDINP1 J27 AK16 N Quad B PCSB_HDINN1 J34 AP17 P Quad B PCSB_HDOUTP0 J37 AN17 N Quad B PCSB_HDOUTN0 J43 AP16 P Quad B PCSB_HDOUTP1 J51 AN16 N Quad B PCSB_HDOUTN1 J8 AL15 P Quad B PCSB_HDINP2 J14 AK15 N Quad B PCSB_HDINN2 J23 AL14 P Quad B PCSB_HDINP3 J28 AK14 N Quad B PCSB_HDINN3 J35 AP15 P Quad B PCSB_HDOUTP2 J38 AN15 N Quad B PCSB_HDOUTN2 J44 AP14 P Quad B PCSB_HDOUTP3 J52 AN14 N Quad B PCSB_HDOUTN3 J71 L26 P 2 NC/PR19A* J72 M25 N 2 NC/PR19B* J69 L32 P 2 NC/PR20A* J70 L31 N 2 NC/PR20B* J66 L34 P 2 NC/PR23A J67 L33 N 2 NC/PR23B 10 LatticeECP3 I/O Protocol Board – Revision C User’s Guide Table 10. SMA Connectors (Continued) Location LatticeECP3 I/O Polarity sysIO Bank Description J47 K29 P 2 NC/PR25A* J48 K30 N 2 NC/PR25B* HMZD Connector J58 is a high-speed HMZD header with 80 differential signal connections for interfacing the LatticeECP3 device to an external application PCB such a high-speed ADC/DAC. The signal path as been verified to operate at the 500 MT/s data rate. I/Os connected as LVDS inputs can be terminated to a 1.25V VTT voltage provided by U10 when header J31 pins 1 and 2 are shorted. When pins 2 and 3 of J31 are shorted, the VTT voltage is 0V. You can also apply external VTT voltages to pin 2 of J31. Differentially paired I/Os may also be used in the single-ended mode with some increase in SSO crosstalk. The connections for J58 are listed in Table 11. Table 11. HMZD Connectors J58 Pin LatticeECP3 I/O Polarity sysIO Bank Description A1 B1 AA31 P 3 PR65A/PR83A* AA30 N 3 PR65A/PR83B* A2 B2 AD33 P 3 NC/PR97A* AD34 N 3 NC/PR97B* A3 AE30 P 3 PR74A/PR101A* B3 AE29 N 3 PR74B/PR101B* A4 AD26 P 3 NC/PR106A* B4 AD25 N 3 NC/PR106B* A5 AP33 P 3 PR83A/PR110A* B5 AP32 N 3 PR83B/PR110B* A6 K31 P 2 NC/PR32A B6 K32 N 2 NC/PR32B A7 T32 P 2 PR35A/PR53A B7 T31 N 2 PR35B/PR53B A8 R28 P 2 PR28A*/PR46A* B8 R27 N 2 PR28B*/PR46B* A9 R31 P 2 PR29A/PR47A* B9 R30 N 2 PR29B/PR47B* A10 N32 P 2 PR20A/PR38A* B10 N31 N 2 PR20B/PR38B* C1 W27 P 3 PR55A*/PR73A* D1 W26 N 3 PR55B*/PR73B* C2 Y26 P 3 PR61A*/PR79A* D2 Y25 N 3 PR61B*/PR79B* C3 AE34 P 3 NC/PR92A* D3 AE33 N 3 NC/PR92B* C4 AL30 P 3 PR91A*/PR118A* D4 AM30 N 3 PR91B*/PR118B* C5 AJ31 P 3 PR88A*/PR115A* D5 AK31 N 3 PR88B*/PR115B* C6 V29 P 3 PR52A*/PR70A*/VREF1_3 11 LatticeECP3 I/O Protocol Board – Revision C User’s Guide Table 11. HMZD Connectors (Continued) J58 Pin LatticeECP3 I/O Polarity sysIO Bank Description D6 W28 N 3 PR52B*/PR70B*/VREF2_3 C7 U32 P 2 PR41A/PR59A D7 U31 N 2 PR41B/PR59B C8 W34 P 3 PR47A/PR65A* D8 W33 N 3 PR47B/PR65B* C9 L30 N 2 NC/PR34B* D9 M29 P 2 NC/PR34A* C10 N26 P 2 PR19A*/PR37A* D10 P26 N 2 PR19B*/PR37B* E1 AA25 P 3 PR64A*/PR82A* F1 AA26 N 3 PR64B*/PR82B* E2 AA28 P 3 PR70A*/PR88A* F2 AA27 N 3 PR70B*/PR88B* E3 AD31 P 3 NC/PR91A* F3 AD30 N 3 NC/PR91B* E4 AC28 P 3 NC/PR100A* F4 AB27 N 3 NC/PR100B* E5 AM29 P 3 PR97A*/PR124A* F5 AN29 N 3 PR97B*/PR124B* E6 U28 P 3 PR46A*/PR64A*/PCLKT3_0 F6 V28 N 3 PR46B*/PR64B*/PCLKC3_0 E7 V31 P 3 PR44A/PR62A F7 V30 N 3 PR44B/PR62B E8 P28 P 2 PR25A*/PR43A* F8 P27 N 2 PR25B*/PR43B* E9 T29 P 2 PR34A*/PR52A*/VREF1_2 F9 T28 N 2 PR34B*/PR52B*/VREF2_2 E10 N34 P 2 PR23A/PR41A F10 N33 N 2 PR23B/PR41B G1 U33 N 2 PR43E_B/PR61E_B/RUM0_GPLLT_FB_B H1 U34 P 2 PR43E_A/PR61E_A/RUM0_GPLLT_FB_A G2 Y34 P 3 PR56A/PR74A* H2 Y33 N 3 PR56B/PR74B* G3 U26 P 2 PR43A*/PR61A*/PCLKT2_0 H3 U27 N 2 PR43A*/PR61B*/PCLKC2_0 G4 AH33 P 3 PR82A*/PR109A* H4 AJ33 N 3 PR82B*/PR109B* G5 AP31 P 3 PR92A/PR119A* H5 AN31 N 3 PR92B/PR119B* G6 W32 P 3 PR50A/PR68A H6 W31 N 3 PR50B/PR68B G7 R34 P 2 PR32A/PR50A H7 R33 N 2 PR32B/PR50B 12 LatticeECP3 I/O Protocol Board – Revision C User’s Guide Table 11. HMZD Connectors (Continued) J58 Pin LatticeECP3 I/O Polarity sysIO Bank Description G8 T26 P 2 PR37A*/PR55A*/RUM0_GDLLT_IN_A H8 T27 N 2 PR37B*/PR55B*/RUM0_GDLLT_IN_B G9 N30 P 2 PR17A/PR35A H9 N29 N 2 PR17B/PR35B G10 P34 P 2 PR26A/PR44A H10 P33 N 2 PR26B/PR44B Crystal Oscillators and External Clock Sources The evaluation board provides 5 dedicated clock sources available for use by a design loaded into the LatticeECP3: 3 crystal oscillators, and 2 pairs of external differential clocks applied through SMA connectors. The selection of internal or external clock sources is done with U8, a high-speed LVPECL multiplexer (MC100LV100VEL56) using the control signals CLK_SEL and PCSB_CLK_SEL. Figure 2 shows how the 5 dedicated clock sources connect to the LatticeECP3. Figure 2. Dedicated Clock Sources PCSB CLK SEL Y2 LatticeECP3 SEL EN 156.25 MHz 1 AH15 PCSB Ref Clock AH16 MUX0 J21, J26 EXT PCSB CLK 0 J33, J36 EXT CLK 0 100.00 MHz EN 1 Clock Source AN27 U8 Y28 Y27 General Purpose Clock U6 U7 DDR3 Clock MUX1 SEL Y3 CLK SEL AH26 Y4 AH19 PCSA Ref Clock AH20 125.00 MHz EN J40 (open enables) U7 The CLK_SEL signal sourced from the LatticeECP3 pin AH26 controls U8 to select whether the internal or external clock source will drive the general-purpose and DDR3 clock inputs to the LatticeECP3 device. The PCSB_CLK_SEL signal sourced from the LatticeECP3 pin AN27 controls U8 to select whether the internal or external PCSB clock source will drive the SERDES PCSB reference clock input to the LatticeECP3 device. If either of the control signals CLK_SEL or PCSB_CLK_SEL are un-programmed, the default selections for the U8 mux are to forward the internal clocks Y2 and Y3 to the ECP3. Tables 12 and 13 detail the clock source selections. Table 12. PSCB SERDES Clock Source Selection U8 Mux0 Input Source J21 + J26 – Y2 Oscillator LatticeECP3 Input Clock Description LatticeECP3 EXT PCSB CLK AN27 = 0 LVCMOS25 156.25 MHz AN27 = 1 LVCMOS25 13 I/O Pins Bank Usage IO_Type AH15, AH16 SERDES Reference CML 50 ohm LatticeECP3 I/O Protocol Board – Revision C User’s Guide Table 13. General-Purpose and DDR3 Clock Source Selection U8 Mux1 Input Source J33 + J36 – Y3 Oscillator LatticeECP3 Input Clock Description LatticeECP3 I/O Pins Bank Usage IO_Type EXT CLK AH26 = 0 LVCMOS25 Y28, Y27 3 General LVDS No term 100 MHz AH26 = 1 LVCMOS25 U6, U7 7 DDR3 SSTL15D No term The internal clock sources Y2 and Y3 are crystal oscillators with +/- 50 ppm accuracy that are individually enabled only while the U8 multiplexer is selecting them. The external clock sources are user supplied through SMA connectors at J21, J26, J33, and J36, after which they are AC coupled and 50 ohm terminated at the inputs of the U8 multiplexer. The external clock sources can be applied either single ended or differentially and should have an amplitude in the range of 0.15v to 1.0v p-p (max, into 50 ohm loads, 1 MHz to 1 GHz) for U8 to function normally. Note that if U8 is set to select an external source when no external clock signal is attached, it is possible for residual crosstalk and thermal noise to be amplified by the U8 multiplexer, resulting in a relatively random clock signal, or no clock signal, to be output from the U8 multiplexer. For best performance, when the U8 multiplexer is selecting an internal clock source, the corresponding external de-selected clock source should be either shut off or disconnected for lowest output clock jitter from the U8 multiplexer. The U8 multiplexer outputs drive the LatticeECP3 input I/O at pins Y28, Y27, U6, U7, AH15 and AH16. The Y28 and Y27 pins are the general-purpose differential clock source applied to bank 3. They should be set for LVDS input levels, and they do not require turning on the internal termination at the LatticeECP3. The U6 and U7 signals are used for the DDR3 clock in bank 7. They should be set for SSTL15D input type, and they do not require internal termination at the LatticeECP3. The general purpose clock and DDR3 clock signals are essentially the same clock signal from U8 applied to both banks 3 and 7, but with different IO_TYPE setting requirements. The AH15 and AH16 signals are the PCSB reference clock inputs and are terminated as CML 50 ohm loads. The crystal oscillator Y4 generates a 125 MHz clock signal with +/- 50 ppm accuracy that directly drives the PCSA reference clock inputs at AH19 and AH20. Y4 can be disabled by adding a jumper on J40. SPI Serial Flash SPI Serial Flash are available in three package styles. The device used on this board is a 16-pin, 64 Mbit, sufficient to store two bitstreams simultaneously in order to support SPIm mode. Configuration/Programming Headers Four programming headers are provided on the evaluation board, providing JTAG access to the LatticeECP3, MachXO, and ispPAC-POWR1220AT8 as well as sysCONFIG™ port access to the LatticeECP3. See Figure 3 and Table 14 for the locations and usage of the programming headers. 14 LatticeECP3 I/O Protocol Board – Revision C User’s Guide Figure 3. Configuration/Programming Headers Table 14. Programming Header Access to Devices Header Function Device Programmed J10 Local JTAG LatticeECP3, ispPAC J11 Multi-board JTAG External J4 XO JTAG MachXO J5 sysCONFIG LatticeECP3 The “Local JTAG” 1x10 header J10 is used for programming access to the LatticeECP3 and ispPACPOWR1220AT8 devices. The “XO JTAG” 1x8 header J4 is used to program the MachXO device which is pre-programmed to create an on-board USB 2.0 download cable capability that can also program the LatticeECP3 and ispPAC-POWR1220AT8 devices. The JTAG ports for the LatticeECP3 and ispPAC-POWR1220AT8 devices can be configured as loop-through connectors to allow for easy daisy chaining of multiple boards connected to the “Multiboard” JTAG 1x10 header J11. With proper jumper selection (see the next section) standard IDC ribbon cable can be used without the need to swap any wires on the cable. The sysCONFIG 2x17 header J5 provides connections for 7 additional modes of configuring the LatticeECP3 device: Slave SPI, Single SPI, Multiple SPI, Burst Flash, Slave SCM, Slave PCM, and Master PCM. See TN1169 LatticeECP3 sysCONFIG Usage Guide for more information on the LatticeECP3 configuration modes. Figure 3 shows the 4 configuration headers with pin 1 on each header being the left-most (and lowest) pin on the connectors. Lattice ispDOWNLOAD Cable A Lattice parallel port or USB ispDOWNLOAD cable can be used with the LatticeECP3 I/O Protocol Board. When using the 1x8 cable adapter, connect pin 1 of the cable to pin 1 of the 1x10 Local JTAG header J10. J10 is the “Local JTAG” connection, a 1x10 100mil header that is provided for use with an external Lattice download cable with fly-wire style JTAG connections. Important: The board must be un-powered when connecting, disconnecting or reconnecting the ispDOWNLOAD Cable or USB cable. Always connect an ispDOWNLOAD Cable’s GND pin (black wire), before connecting any other JTAG pins. Failure to follow these procedures can in result in damage to the LatticeECP3 FPGA and render the board inoperable. 15 LatticeECP3 I/O Protocol Board – Revision C User’s Guide Built-in USB 2.0 Download Cable A standard USB cable is included that allows configuring the LatticeECP3 and ispPAC devices using the LatticeECP3 I/O Protocol Board built-in USB download cable feature. The built-in cable consists of a USB Type-B connector (J2), a USB microcontroller (U3), and a MachXO device (U5). To use the built-in USB 2.0 download cable, simply connect a standard USB cable from J2 to your PC (with ispVM System installed and set to use the USB I/O port), set J20 as shown in Figure 4 and Table 15, and check that there are no cable connections on the Local JTAG connector J10. The USB Hub on the PC will detect the addition of the USB function making the built-in USB 2.0 download cable available for use with Lattice’s ispVM System software. Figure 4. Built-in USB 2.0 Enabled as Local JTAG Source at J2 Table 15. Built-in USB vs. External Download Cable Selection Local JTAG Connector Attach Download Cable Shunt pins 1-2 J20 Position Up J10 1x10 header Lattice ispDOWNLOAD Shunt pins 2-3 Down J2 USB Type B Standard USB cable Use of the built-in USB 2.0 download cable through J2 must be mutually exclusive to the use of an external download cable on the Local JTAG connector J10. When using an external download cable on J10 rather than the built in USB 2.0 download cable on J2, the jumper on J20 must be moved upwards to shunt pins 1-2, this tri-states the MachXO device I/O, preventing it from interfering with the external Lattice ispDOWNLOAD cable connected to J10. LatticeECP3 Configuration Using JTAG Two programming headers, J10 and J11, are provided on the evaluation board for access to the LatticeECP3 JTAG port and the ispPAC-POWR1220AT8 JTAG port. Note that in this discussion, the built-in USB 2.0 download cable can be enabled as described in the previous section to directly access the J10 signals. The pinouts for the J10 and J11 headers are provided in Table 16. Table 16. JTAG Programming Headers Local Programming Multi-Board Programming Pin J10 Function J11 Function J10 Function J11 Function 1 3_3V Not used 3_3V NC 2 TDO (from J9) Not used TDO (from J9) TDO (to J9) 3 TDI Not used TDI TDI (from J9) 4 PROGRAMN Not used PROGRAMN PROGRAMN (from J18) 5 NC Not used NC NC 6 TMS Not used TMS TMS (buffered Local) 7 GND Not used GND GND 8 TCK Not used TCK TCK (buffered Local) 16 LatticeECP3 I/O Protocol Board – Revision C User’s Guide Table 16. JTAG Programming Headers (Continued) Local Programming Multi-Board Programming Pin J10 Function J11 Function J10 Function J11 Function 9 DONE Not used DONE DONE 10 INIT Not used INIT INIT (from J24) J9 is a 6-pin header that controls the functions of the local and multi-board programming headers as shown in Figure 5 and Table 17. Figure 5. Selecting JTAG Configuration at J9 Local Multi-Board LatticeECP3 Table 17. Selecting JTAG Configuration at J9 J9 Position J10 and J11 Usage Shunt pins 1-3 Local JTAG Shunt pins 1-2, 3-4 Multi-board JTAG Shunt pins 3-5 LatticeECP3-Only JTAG Typical use of the evaluation board is the LatticeECP3-only JTAG configuration where only the LatticeECP3 device is visible for programming in ispVM. The Multi-board setting allows daisy chaining additional JTAG devices external to the evaluation board. The Local JTAG setting allows programming both the LatticeECP3 and ispPAC-POWR1220AT8 devices during the same configuration session in ispVM. While in the Local JTAG setting of J9, you can apply a jumper to header J17 to bypass the LatticeECP3 device to only program the ispPAC-POWR1220AT8 device as shown in Table 18. Table 18. Local JTAG Device Programming J17 Position Local JTAG Programming Shunt pins 1-2 ispPAC only Open pins 1-2 LatticeECP3 and ispPAC The header J59 provides a means to enable the ispPAC device in the JTAG chain. Likewise for J60 enabling the LatticeECP3 device in the JTAG chain. Being able to selectively enable either device is of use for cases where configuration headers J9 and J17 have set up an instance that both the ispPAC and LatticeECP3 are listening in parallel at the same point in the JTAG chain. In such an instance, the device that is not driving the remainder of the JTAG chain should be disabled so it will ignore the JTAG signals passing by its JTAG inputs and the device’s configuration will remain intact. The configuration procedures near the end of this user’s guide describe how to properly set the evaluation board programming headers to easily download bitstreams into each of the Lattice devices on the evaluation board. Configuration CFG Switches The LatticeECP3 power-up configuration mode is controlled by the setting of SW5. Table 19 shows the how to set SW5 for the various configurations. 17 LatticeECP3 I/O Protocol Board – Revision C User’s Guide Table 19. CFG Configuration at SW5 CFG2 SW5-1 CFG1 SW5-2 CFG0 SW5-3 Configuration Mode DOWN DOWN DOWN SPI Flash DOWN UP DOWN SPIm UP DOWN UP Slave Serial UP UP UP Slave Parallel X X X ispJTAG™ Additional instructions and recommendations for programming this board are provided in the Configuring/Programming the Board section of this document. Switches There is one 8-position switch (SW4) and 2 push-button switches (PB1 and PB2) for implementing basic userassigned input functions. Additionally, there are two 3-position switches (SW5 and S1) and 3 push-buttons (SW1, SW2, and SW3) for Power Manager and LatticeECP3 configuration. Switches PB1, PB2, SW1, SW2, and SW3 are momentary switches. The pull-up resistors associated with these switches are wired to 3.3V. Pushing the switches down produces a low (0), otherwise it produces a high (1). The signals controlled by PB1, PB2, SW1, and SW2 are debounced by MAX6817 devices (U23 and U24) before connecting to an LatticeECP3 I/O pin. Table 20 shows the control relationship between the switches, LatticeECP3 I/O pins, and USB controller U3. Table 20. Momentary Switches User Definable Debounced PB1 AM34 of LatticeECP3 Connection Yes Yes PB2 AM33 of LatticeECP3 Yes Yes SW1 B34 of LatticeECP3 (PROGRAMN) No Yes SW2 D33 of LatticeECP3 (GSRN) Yes Yes SW3 Pin 9 of U3 (USB_RESETn) No No SW4 on the lower side of the board is an 8-pin DIP switch with pull-up resistors to the DDR3_VDD (1.5V) supply. SW3 and S1 are 3-pin DIP switches with pull up resistors to 3.3V. A switch in the down position produces a low (0), the up position produces a high (1). Table 21 shows the SW4 connections to the LatticeECP3, Table 19 shows the S1 connections to ispPAC-POWR1220AT8 I/O pins, and Table 20 shows the SW3 connections to the LatticeECP3. Table 21. 8-Position Switch SW4 Switch (Position#) LatticeECP3 I/O sysIO Bank SW4 (position#1) A9 0 SW4 (position#2) A8 0 SW4 (position#3) A6 0 SW4 (position#4) B6 0 SW4 (position#5) A7 0 SW4 (position#6) B7 0 SW4 (position#7) A5 0 SW4 (position#8) A4 0 18 LatticeECP3 I/O Protocol Board – Revision C User’s Guide Table 22. 3-Position Switch S1 Switch (Position#) POWR1220AT8 I/O Pin Pin Name S1 (position#1) 4 IN1 S1 (position#2) 6 IN2 S1 (position#3) 7 IN3 Table 23. 3-Position Switch SW3 Switch (Position#) LatticeECP3 I/O Pin Name sysIO Bank 8 SW3 (position#1) D32 CFG2 SW3 (position#2) F30 CFG1 8 SW3 (position#3) B33 CFG0 8 LEDs There are eight user-definable LEDs located at the upper center of the board. These LEDs are each controlled by a separate general purpose I/O as defined in Table 24. The LEDs will light when their associated I/O is high and will have a current flowing through them of approximately 3 mA, the value of which is set by the NPN current source connected transistors (Q6, Q12, Q13, Q14, Q15, Q16, Q17, Q18) and resistors (R155, R162, R164, R177, R189, R193, R195, R199). The LEDs are off when the I/Os are set low. Table 24. Connection Between LEDs and LatticeECP3 Signal LED LatticeECP3 IO Bank LED0 D6 C3 0 LED1 D9 C4 0 LED2 D10 D3 0 LED3 D12 C2 0 LED4 D14 B1 0 LED5 D11 B2 0 LED6 D8 E4 0 LED7 D7 D4 0 Table 25 describes the three LEDs associated with the dedicated programming pins. Table 25. Programming LEDs LED Pin Color D4 PROGRAMN Red Function On when signal is low D2 INIT Red D5 DONE Green On when initializing D3 GSRN Red On when signal is low D1 TDI Green On when TDI is active On when config is complete 7-Segment Display The 7-segment LED is controlled by LatticeECP3 bank 0 I/O pins. The connections of the segments are shown in Figure 6. 19 LatticeECP3 I/O Protocol Board – Revision C User’s Guide Figure 6. Seven Segment Display The LED digit segments will light when their associated I/O is high and will have a current flowing through them of approximately 5 mA, the value of which is set by the NPN current source connected transistors (Q2, Q3, Q5, Q7, Q8, Q9, Q10, Q11) and resistors (R126, R133, R148, R150, R151, R152, R153, R154). The LED digit segments are off when the I/Os are set low. LCD The LCD module connector (J32) is a 2x9 header. This 18-pin header is compatible with some character LCD modules. Table 26 shows the pin function of the header and the connections to bank 1 of the LatticeECP3 FPGA. The bank 1 supply voltage (VCCIO_1) must be set using J41 to select the proper voltage level expected by the LCD module. Table 26. LCD Header Connection Pin # Function LatticeECP3 I/O Pin # Function LatticeECP3 I/O 1 Anode — 2 Cathode (GND) — 3 VSS (GND) — 4 VDD (5V) — 5 VO — 6 RS D23 7 R/W A23 8 E K22 9 DB0 B23 10 DB1 K21 11 DB2 E22 12 DB3 A24 13 DB4 E23 14 DB5 B24 15 DB6 C23 16 DB7 G23 17 Anode — 18 Cathode (GND) — The VR1 potentiometer is used to limit the current that flows through the backlight LED on the LCD module. The VR2 potentiometer is used to adjust the VO voltage that controls the LCD contrast. When the following LCD modules are used, connect pins 1 through 16 to the backlight LCD module or connect pins 1 through 14 to the non-backlight LCD module. Optrex: • C-51505 Series: 20 characters x 2 lines When the following LCD modules are used, connect pin 3 to 18 to the backlight LCD module or connect pin 3 to 16 to the non-backlight LCD module. 20 LatticeECP3 I/O Protocol Board – Revision C User’s Guide Lumex: • LCM-S01601 Series: 16 characters x 1 line • LCM-S00802 Series: 8 characters x 2 lines • LCM-S01602 Series: 16 characters x 2 lines • LCM-S02002 Series: 20 characters x 2 lines • LCM-S02402 Series: 24 characters x 2 lines • LCM-S04002 Series: 40 characters x 2 lines • LCM-S02004 Series: 20 characters x 4 lines • LCM-S02404 Series: 24 characters x 4 lines Varitronix: • MDLS-20189 Series: 20 characters x 1 line • MDLS-20265 Series: 20 characters x 2 lines • MDLS-24265 Series: 24 characters x 2 lines • MDLS-40266 Series: 40 characters x 2 lines 21 LatticeECP3 I/O Protocol Board – Revision C User’s Guide Logic Analyzer Probe Connector LA1 is configured for use with the Agilent 16760A Logic Analyzer probe. All the signal pins at LA1 are connected to the LatticeECP3 bank 1 I/Os, and to the test point header J54. The bank 1 supply voltage (VCCIO_1) must be set using J41 to select the proper voltage level expected by the logic analyzer. Series 33 ohm resistors are installed on the board to reduce reflection overshoot and undershoot for un-terminated receivers attached to J54. See Table 27 for the Logic Analyzer probe connections to the LatticeECP3 I/O pins. Table 27. LA1 Logic Analyzer and J54 Test Points LA1 Pin J54 Pin Signal LatticeECP3 I/O 5 2 LA1 A17 6 3 LA2 B17 7 4 LA3 A18 8 5 LA4 B18 9 6 LA5 J18 10 7 LA6 H18 11 8 LA7 D18 12 9 LA8 E18 13 10 LA9 G19 14 11 LA10 H19 15 12 LA11 A19 16 13 LA12 B19 17 14 LA13 K20 18 15 LA14 L19 19 16 LA15 C19 20 17 LA16 D19 21 18 LA17 J19 22 19 LA18 K19 23 20 LA19 A20 24 21 LA20 B20 25 22 LA21 G20 26 23 LA22 G21 27 24 LA23 C20 28 25 LA24 D20 29 26 LA25 H20 30 27 LA26 J20 31 28 LA27 A22 32 29 LA28 B22 33 30 LA29 J22 34 31 LA30 J23 35 32 LA31 C22 36 33 LA32 D22 37 34 LA33 J21 38 35 LA34 H22 22 LatticeECP3 I/O Protocol Board – Revision C User’s Guide High-Speed Test Points Additional high-speed test points are provided at the connectors shown in Table 28. Table 28. Additional High-Speed Test Points Connector Pin Signal LatticeECP3 I/O VCCIO Type J68 1 Y32 Y32 2.5 I/O J63 1 C8 C8 1.5 I/O J64 1 V5 V5 1.5 I/O J65 1 K4 K4 1.5 I/O J57 J55 3 IDC0 H23 I/O 5 IDC1 D24 I/O 7 IDC2 E24 I/O 9 IDC3 K23 I/O 11 IDC4 K24 I/O 13 IDC5 A25 I/O 15 IDC6 B25 I/O 17 IDC7 C28 19 IDC8 D28 21 IDC9 C25 I/O 23 IDC10 D25 I/O 25 IDC11 G26 I/O 27 IDC12 G25 I/O 29 IDC13 B28 I/O 31 IDC14 A28 I/O 33 IDC15 A26 I/O 33 TEST0 N27 I/O 31 TEST1 N28 I/O 29 TEST2 AJ27 I/O 27 TEST3 AK28 I/O 25 TEST4 AJ28 I/O 23 TEST5 AH27 I/O 21 TEST6 R26 19 TEST7 R25 17 TEST8 T34 I 15 TEST9 T33 I 13 TEST10 T30 I/O 11 TEST11 U30 I/O VCCIO1 (Set by J41) I/O I/O I/O 2.5V I/O 9 TEST12 AH28 I/O 7 TEST13 AL29 I/O 5 TEST14 AG26 I/O High Current I/O The High Current I/O connector J46 provides a means to evaluate multiple I/Os connected in parallel to produce a higher combined output I/O current exceeding that of a single I/O. The three series resistors R37, R38, and R157, are placed physically close to the LatticeECP3 pins and a 50 ohm signal trace connects the parallel side of the resistors to the SMA connector J46. For best results, the three output I/Os at pins H25, H26, and A31 should be set for the FAST setting and driven by the same signal within the LatticeECP3 internal routing. 23 LatticeECP3 I/O Protocol Board – Revision C User’s Guide The high current I/O output can also be used to implement a simple 3-bit DAC by replacing the 3 series resistors R37, R38, and R157 with higher scaled resistor values. Suggested values for the three resistors would be 487 ohm, 1.0K ohm, and 2K ohm. J46 will then output 8 monotonic voltage values between the VCCIO1 and GND potentials dependent on the output states of the signals at the LatticeECP3 I/Os located at H25, H26 and A31. For the DAC configuration just described, the fastest signal response will be had if the J46 output is driving a 50 ohm load. The largest output voltage range will occur when the J46 load is a high impedance. Be aware that simple DACs of this type can pass residual power supply noise (SSO) from other I/Os switching in the same bank. So if an application is noise-sensitive, either filter the DAC output at J46 or use an external DAC. DDR3 The two 240-pin DIMM sockets provide a built-in 64-bit interface to standard 1.5V DDR3 SDRAM UDIMM memory modules. The required VREF and VTT voltages, as well as termination of each signal to VTT are provided. Performance has been verified at above the 800 MT/s data rate. See TN1180, LatticeECP3 High-Speed I/O Interface for further information about DDR3 design considerations and recommendations. The connections between the connector pins and LatticeECP3 balls are shown in Table 29. Table 29. DDR3 Interface to DIMM Sockets Description LatticeECP3 I/O Pin sysIO Bank J1 & J3 Pin DDR3_DQ0 AN3 6 3 DDR3_DQ1 AM3 6 4 DDR3_DQ2 AJ5 6 9 DDR3_DQ3 AJ6 6 10 DDR3_DQ4 AL5 6 122 DDR3_DQ5 AM5 6 123 DDR3_DQ6 AL4 6 128 DDR3_DQ7 AM4 6 129 DDR3_DM0 AP5 6 125 DDR3_DQS0_P AM6 6 7 DDR3_DQS0_N AN6 6 6 DDR3_DQ8 AN1 6 12 DDR3_DQ9 AN2 6 13 DDR3_DQ10 AD9 6 18 DDR3_DQ11 AD8 6 19 DDR3_DQ12 AP2 6 131 DDR3_DQ13 AP3 6 132 DDR3_DQ14 AL3 6 137 DDR3_DQ15 AK3 6 138 DDR3_DM1 AJ4 6 134 DDR3_DQS1_P AJ2 6 16 DDR3_DQS1_N AJ3 6 15 DDR3_DQ16 AA2 6 21 DDR3_DQ17 AA1 6 22 DDR3_DQ18 Y7 6 27 DDR3_DQ19 AA7 6 28 DDR3_DQ20 AA4 6 140 DDR3_DQ21 AA3 6 141 DDR3_DQ22 AB2 6 146 DDR3_DQ23 AB1 6 147 24 LatticeECP3 I/O Protocol Board – Revision C User’s Guide Table 29. DDR3 Interface to DIMM Sockets (Continued) Description LatticeECP3 I/O Pin sysIO Bank J1 & J3 Pin DDR3_DM2 AA5 6 143 DDR3_DQS2_P AA10 6 25 DDR3_DQS2_N AB9 6 24 DDR3_DQ24 W2 6 30 DDR3_DQ25 W1 6 31 DDR3_DQ26 W8 6 36 DDR3_DQ27 W9 6 37 DDR3_DQ28 W4 6 149 DDR3_DQ29 W3 6 150 DDR3_DQ30 Y2 6 155 DDR3_DQ31 Y1 6 156 DDR3_DM3 Y8 6 152 DDR3_DQS3_P W6 6 34 DDR3_DQS3_N Y6 6 33 DDR3_DQ32 T6 7 81 DDR3_DQ33 T5 7 82 DDR3_DQ34 R8 7 87 DDR3_DQ35 T7 7 88 DDR3_DQ36 T4 7 200 DDR3_DQ37 T3 7 201 DDR3_DQ38 T2 7 206 DDR3_DQ39 T1 7 207 DDR3_DM4 U9 7 203 DDR3_DQS4_P T9 7 85 DDR3_DQS4_N T8 7 84 DDR3_DQ40 R7 7 90 DDR3_DQ41 R5 7 91 DDR3_DQ42 P9 7 96 DDR3_DQ43 P10 7 97 DDR3_DQ44 R2 7 209 DDR3_DQ45 R1 7 210 DDR3_DQ46 R4 7 215 DDR3_DQ47 R3 7 216 DDR3_DM5 R10 7 212 DDR3_DQS5_P P7 7 94 DDR3_DQS5_N P6 7 93 DDR3_DQ48 N3 7 99 DDR3_DQ49 M5 7 100 DDR3_DQ50 N5 7 105 DDR3_DQ51 N2 7 106 DDR3_DQ52 N1 7 218 DDR3_DQ53 P5 7 219 DDR3_DQ54 P4 7 224 DDR3_DQ55 N8 7 225 25 LatticeECP3 I/O Protocol Board – Revision C User’s Guide Table 29. DDR3 Interface to DIMM Sockets (Continued) Description LatticeECP3 I/O Pin sysIO Bank J1 & J3 Pin DDR3_DM6 P8 7 221 DDR3_DQS6_P M10 7 103 DDR3_DQS6_N N10 7 102 DDR3_DQ56 F2 7 108 DDR3_DQ57 F1 7 109 DDR3_DQ58 F3 7 114 DDR3_DQ59 E3 7 115 DDR3_DQ60 G2 7 227 DDR3_DQ61 G1 7 228 DDR3_DQ62 H1 7 233 DDR3_DQ63 J1 7 234 DDR3_DM7 J3 7 230 DDR3_DQS7_P G3 7 112 DDR3_DQS7_N H3 7 111 DDR3_A0 E13 0 188 DDR3_A1 F13 0 181 DDR3_A2 G13 0 61 DDR3_A3 H14 0 180 DDR3_A4 A13 0 59 DDR3_A5 B13 0 58 DDR3_A6 C13 0 178 DDR3_A7 D13 0 56 DDR3_A8 J15 0 177 DDR3_A9 H15 0 175 DDR3_A10 A14 0 70 DDR3_A11 B14 0 55 DDR3_A12 G16 0 174 DDR3_A13 G17 0 196 DDR3_A14 A15 0 172 DDR3_A15 B15 0 171 DDR3_BA0 B12 0 71 DDR3_BA1 A12 0 190 DDR3_BA2 D12 0 52 DDR3_1_CK0_P U2 6 J1-184 DDR3_1_CK0_N U1 6 J1-185 DDR3_1_CK1_P V9 6 J1-63 DDR3_1_CK1_N V8 6 J1-64 DDR3_2_CK0_P V2 6 J3-184 DDR3_2_CK0_N V1 6 J3-185 DDR3_2_CK1_P V4 6 J3-63 DDR3_2_CK1_N V3 6 J3-64 DDR3_1_CKE0 E11 0 J1-50 DDR3_1_CKE1 F12 0 J1-169 26 LatticeECP3 I/O Protocol Board – Revision C User’s Guide Table 29. DDR3 Interface to DIMM Sockets (Continued) Description LatticeECP3 I/O Pin sysIO Bank J1 & J3 Pin DDR3_2_CKE0 F10 0 J3-50 DDR3_2_CKE1 E10 0 J3-169 DDR3_1_S0_N K12 0 J1-193 DDR3_1_S1_N C11 0 J1-76 DDR3_2_S0_N J12 0 J3-193 DDR3_2_S1_N B10 0 J3-76 DDR3_RASN H12 0 192 DDR3_CASN H11 0 74 DDR3_WEN D9 0 73 DDR3_1_ODT0 A11 0 J1-195 DDR3_1_ODT1 B11 0 J1-77 DDR3_2_ODT0 J13 0 J3-195 DDR3_2_ODT1 K13 0 J3-77 I2C_SDA AA2 8 238 I2C_SCL Y2 8 118 Ethernet PHY In the lower-right portion of the board is U18, a Marvell Gigabit Ethernet PHY (88E1111). The LatticeECP3 FPGA interacts with the PHY over a Serial Gigabit Media Independent Interface (SGMII). The PHY is connected to an RJ45 connector J53 on the Media Dependent Interface (MDI). The RJ45 connector J53 has built in magnetics and spark-gap capacitor. The PHY is available on the board to demonstrate the Lattice Ethernet Media Access (MAC) IP core. However, it is also possible to use the PHY to evaluate a custom MAC solution. Typically J40 will have the jumper removed to enable the 125 MHz crystal oscillator Y4 as the PCSA SERDES reference clock for use with the SGMII interface signals. Refer to the schematic and the Marvell 88E1111 Data Sheet for detailed information about the operation of the Ethernet PHY interface on this device. Refer to Table 30 for a description of the Ethernet PHY SGMII connections to the LatticeECP3. Table 30. 10/100/1000 Ethernet PHY Connection Summary Description LatticeECP3 I/O 88E1111 Pin ETH_SIN_P AP21 A3 ETH_SIN_N AN21 A4 ETH_SOUT_P AL21 A7 ETH_SOUT_N AK21 A8 The Ethernet PHY will power up with the default configuration set by binary patterns applied to the ETH_CFG[0..6] signals at TP40-46. To change the default Ethernet PHY configuration, add wire straps from TP40-46 (the configuration inputs), to TP69-76 (the binary pattern sources). See Table 31 and the Marvell 88E1111 data sheet for further details about how to change the configuration of the Ethernet PHY on power up. 27 LatticeECP3 I/O Protocol Board – Revision C User’s Guide Table 31. Ethernet Power-Up Configuration Test Points ETH CFG Input ETH CFG Test Point CFG Pattern Signal CFG Pattern Test Point ETH_CFG0 TP40 111 TP76 ETH_CFG1 TP41 110 TP75 ETH_CFG2 TP42 101 TP74 ETH_CFG3 TP43 100 TP73 ETH_CFG4 TP44 011 TP72 ETH_CFG5 TP45 010 TP71 ETH_CFG6 TP46 001 TP69 — — 000 TP70 Configuring/Programming the LatticeECP3 Requirements • PC with Lattice ispVM System version 17.7 (or later) programming software, installed with appropriate drivers (USB driver for USB Cable, Windows NT/2000/XP parallel port driver for ispDOWNLOAD Cable). Note: An option to install these drivers is included as part of the ispVM System setup. The ispVM System software is available within the ispLEVER software, or as a stand-alone application available for download at the Lattice web site. • A standard USB cable connected to the built in USB download connector J2, or a Lattice ispDOWNLOAD cable (HW-USBN-2A or HW-DLN-3C) using flywire connections to J10. Most users of the LatticeECP3 I/O Protocol Board will initially be interested in programming the LatticeECP3 device. There are two other programmable Lattice devices on the evaluation board: an ispPAC-POWR1220AT8 device and a MachXO device, both of which contain non-volatile Flash memory that has been programmed during board test at the manufacturer. The ispPAC-POWR1220AT8 device must be programmed and operational for the power supplies to be at nominal levels, and the MachXO must be programmed and operational for the built-in USB download circuitry to be functional. If in the course of using the evaluation board, either the ispPAC-POWR1220AT8 or MachXO internal programming is overwritten or erased, a simple LatticeECP3 reference design is available on the Lattice web site that includes the default design and bitstream for the ispPAC-POWR1220AT8 and the bitstream for the MachXO. Download instructions are included in the file set and programming must be done using an ispDOWNLOAD cable at connector J10. For a complete discussion of the LatticeECP3’s configuration and programming options, refer to TN1169, LatticeECP3 sysCONFIG Usage Guide. Download Procedures for the LatticeECP3 I/O Protocol Board The download instructions described below show how to download bitstreams into the LatticeECP3 SRAM using the ispVM System software. Downloads can be either direct through a cable connection to a PC, or indirect by first programming the on-board SPI Flash and then downloading the bitstream to the LatticeECP3 SRAM from SPI Flash. You can download bitstreams through a download cable to the LatticeECP3 SRAM at any time. After a bitstream has been downloaded to SPI Flash, you can download the bitstream from SPI Flash to the LatticeECP3 SRAM by either pushing the PROGRAMN button or by cycling the power to the evaluation board. Downloading into the LatticeECP3 using SPI Flash also requires setting the CFGx pins appropriately and this is covered in the procedures. The LatticeECP3 I/O Protocol Board provides support for two types of download cable connections: a standard USB cable at J2, or a Lattice ispDOWNLOAD cable (USB type or parallel port type with flywire connections) at J10. Given that you might want to download to either the SRAM or the SPI Flash, using either a standard USB cable or an ispDOWNLOAD cable, separate LatticeECP3 download procedures covering each of the four possible types of 28 LatticeECP3 I/O Protocol Board – Revision C User’s Guide downloads is shown, followed by additional instructions for downloading to the ispPAC-POWR1220AT8 and MachXO. Note that the first two download procedures show the menus as viewed on a Windows XP operating system. The remainder of the download procedures are very similar and do not show the menus. Default Jumper Settings Used within the Download Procedures The board is shipped with default jumper positions as shown in Figure 7. Each procedure that follows will refer back to the default jumper positions near the start of the procedure with changes made after that to enable the proper configuration signal flow. Figure 7. Default Jumper Settings Note: During the procedures below, if you see the vertical column of 10 LEDS at the left side of the ispPACPOWR1220AT8 device blinking, this indicates that the 12V input power is outside the 12V +/- 10% input range. Damage can occur to the 12V switching regulators when operating at higher than the recommended input voltages. You can turn off the blink warning by pushing down on the topmost lever of S1. If you see all LEDs on the board flickering at about a 5Hz rate even when the topmost lever of S1 is down, then check and replace the topmost fuse F2 if it is blown. If the vertical column of 10 LEDS is not lit up, then it is likely that the ispPACPOWR1220AT8 device is not yet programmed, or the input 12V power supply is less than about 9V, which is not 29 LatticeECP3 I/O Protocol Board – Revision C User’s Guide sufficient to drive the 12V switching modules. If the ispPAC-POWR1220AT8 is not yet programmed, go to the Lattice web site and download the simple reference design for this board. Go to the PAC directory in the reference design and follow the download instructions in that directory to program the device with the factory default ispPAC bitstream. LatticeECP3 SRAM Configuration Using a Standard USB Cable at J2 The LatticeECP3 SRAM can be configured easily using the ispVM System software to download a bitstream via a standard USB cable connected to the built in USB download at J2. The LatticeECP3 device is SRAM based, so it must remain powered on to retain its configuration when programming the SRAM. 1. Attach a ground connection from test equipment chassis ground to the GND side of terminal block TB1. 2. Connect a standard USB cable from your PC’s USB connector to J2 on the board. 3. Check that the jumpers are installed as shown in Figure 7. 4. Add a jumper on J18 and move the jumper at J20 to the down position (lower 2 pins position of J20). 5. Check that all levers of S1 and S4 are in the up position. 6. Connect the 12V wall power adaptor cable to J56. Check to see that the wall power adapter is plugged in to a 120 VAC source and the “12VIN GOOD” LED is lit up. The vertical column of 10 LEDs to the left of the ispPACPOWR1220AT8 device should also be lit. LEDs near the ispPAC-POWR1220AT8 device that are on indicate that those power supplies are within the proper voltage range. If any of them are off, those supplies are either off, or outside the normal operation range. 7. Start the ispVM System software. Select the menu items Options >Autoscan Options > Custom Scan as shown in Figure 8. Figure 8. Setting the ispVM Custom Scan Option 8. Select Options > Cable and I/O Port Setup. For the Cable Type, select USB. In the lower section of the Cable and I/O Port setup menu, you will see checkboxes. Select the ispEN/BSCAN Pin Connected checkbox and then select the Set High checkbox as shown in Figure 9. Push the OK button. 30 LatticeECP3 I/O Protocol Board – Revision C User’s Guide Figure 9. Setting the Cable Type to USB with ispEN Set High 9. Push the Scan button. You should now see the LFE3-150EA_ES device listed in the New Scan Configuration Setup window. In the device list, left-click on the LatticeECP3 device to select it. If offered other selections, select LFE3-150EA_ES. See Figure 10. Figure 10. ispVM New Scan Configuration Setup 10. Click Edit > Edit Device to edit the device. A Device Information window will be opened. Click the Select button and select the package type 1156-ball fpBGA as shown in Figure 11, then click OK. 31 LatticeECP3 I/O Protocol Board – Revision C User’s Guide Figure 11. LatticeECP3 Package Size Selection 11. Check that the Device Access Options drop-down menu control selects the JTAG 1532 Mode. Check that the Operation drop-down menu selects Fast Program. 12. Click data file Browse button and select the path to the LatticeECP3 “.BIT” bitstream file as shown in Figure 12, then click OK. 32 LatticeECP3 I/O Protocol Board – Revision C User’s Guide Figure 12. Bitstream Ready to Download into LatticeECP3 SRAM 13. Click Project >Download or the green Go button to download the bitstream into the LatticeECP3 device (U7). A small window will appear as shown in Figure 13. It will take about 40 seconds to download the bitstream for a PC with USB 2.0 ports. You should see the D1 LED blinking as the bitstream loads in. When the ECP3 has loaded in correctly, the ispVM status window will report “Operation Successful” as shown in Figure 14. Figure 13. Bitstream Downloading into LatticeECP3 33 LatticeECP3 I/O Protocol Board – Revision C User’s Guide Figure 14. Bitstream Download Operation Successful LatticeECP3 SRAM Configuration Using SPI Flash and a Standard USB Cable at J2 The LatticeECP3 SRAM can be configured easily using the ispVM System software to program the on-board SPI Flash via a standard USB cable connected to the built in USB download at J2. The LatticeECP3 device is SRAMbased, so it must remain powered on to retain its configuration when programming the SRAM. The on-board SPI Flash retains its programmed bitstreams when power is off, and can quickly load programmed bitstreams into the LatticeECP3 device when power is applied. 1. Attach a ground connection from test equipment chassis ground to the GND side of terminal block TB1. 2. Connect a standard USB cable from your PC’s USB connector to J2 on the board. 3. Check that the jumpers are installed as shown in Figure 7. 4. Add a jumper on J18 and move the jumper at J20 to the down position (lower 2 pins position of J20). 5. Check that all levers of S1 and S4 are in the up position and all levers of SW5 are in the down position. 6. Connect the 12V wall power adaptor cable to J56. Check to see that the wall power adapter is plugged in to a 120 VAC source and the “12VIN GOOD” LED is lit. The vertical column of 10 LEDs to the left of the ispPACPOWR1220AT8 device should also be lit. LEDs near the ispPAC-POWR1220AT8 device that are on indicate that those power supplies are within the proper voltage range. If any of them are off, those supplies are either off, or outside the normal operation range. 7. Start the ispVM System software. Select the menu items Options > Autoscan Options > Custom Scan. 8. Select Options > Cable and I/O Port Setup. For the Cable Type, select USB. In the lower section of the Cable and I/O Port setup menu, you will also see checkboxes. Select the ispEN/BSCAN Pin Connected checkbox and then select the Set High check box. Push the OK button. 34 LatticeECP3 I/O Protocol Board – Revision C User’s Guide 9. Push the SCAN button, you should now see the LFE3-150EA_ES device listed in the New Scan Configuration Setup* window. In the device list, left-click on the LatticeECP3 device to select it. If offered other selections, select LFE3-150EA_ES. 10. Click Edit > Edit Device to edit the device. A Device Information window will be opened. Click the Select button and select the package type 1156-ball fpBGA. Click OK. 11. Click the Device Access Options drop-down menu control and select the SPI Flash Background Programming. A SPI Serial Flash Device window will open. 12. Push the Select button and select the Vendor as STMicro, the device as SPI-M25P64 and the package 16lead SOIC as shown in Figure 15. Push the OK button. Figure 15. SPI Flash Device Selection 13. Click the data file Browse button and select the path to the LatticeECP3 “.BIT” bitstream file. Push the Load From File button and then click OK to complete the SPI Flash device selection as shown in Figure 16. Again click OK to exit the Device Information menu. The bitstream is now set up for downloading into the SPI Flash as shown in Figure 17. 35 LatticeECP3 I/O Protocol Board – Revision C User’s Guide Figure 16. SPI Flash Device Setup Complete Figure 17. Bitstream Ready to Download into SPI Flash 14. Click Project > Download or the green Go button to download the bitstream into the SPI Flash device (U12), the bitstream download progress indictor will pop up as shown in Figure 18. When using the built-in USB down36 LatticeECP3 I/O Protocol Board – Revision C User’s Guide load cable, it will take a little under three minutes to erase, program and verify the bitstream loaded properly into the SPI Flash for a PC with USB 2.0 ports. You should see the D1 LED blinking as the bitstream loads in, and then off as ispVM verifies the bitstream. After the SPI Flash contents have been verified, the ispVM status window will report “Operation Successful” as shown in Figure 19. Figure 18. Bitstream Download Progress Indicator Figure 19. SPI Flash Download Operation Successful 15. Push the PROGRAMN button SW1 to load the design. The design will load into the LatticeECP3 (U7) from the external SPI Flash (U12) in 12 seconds, and the “DONE” LED (D5) will light up. LatticeECP3 SRAM Configuration Using a Lattice ispDOWNLOAD Cable at J10 The LatticeECP3 SRAM can be configured easily using the ispVM System software to download a bitstream via an ispDOWNLOAD cable connected to the ‘Local JTAG’ header J10. The LatticeECP3 device is SRAM-based, so it must remain powered on to retain its configuration when programming the SRAM. 37 LatticeECP3 I/O Protocol Board – Revision C User’s Guide 1. Attach a ground connection from test equipment chassis ground to the GND side of terminal block TB1. 2. Connect a Lattice USB download cable to the PC’s USB port (or a Lattice parallel download cable to the PC’s parallel printer port) and attach the 8-pin side of the cable to J10 pin 1 to pin 8 on the board (the leftmost eight pins of J10). The signals requiring connection at the ‘Local JTAG’ connector J10 are: Pin Signal Name Comment 1 VCC Leftmost pin 2 TDO 3 TDI 4 No connect 5 No connect 6 TMS 7 GND 8 TCK 3. Check that the jumpers are installed as shown in Figure 7. 4. Check that all levers of S1 and S4 are in the up position. 5. Connect the 12V wall power adaptor cable to J56. Check to see that the wall power adapter is plugged in to a 120 VAC source and the “12VIN GOOD” LED is lit. The vertical column of 10 LEDs to the left of the ispPACPOWR1220AT8 device should also be lit. LEDs near the ispPAC-POWR1220AT8 device that are on indicate that those power supplies are within the proper voltage range. If any of them are off, those supplies are either off, or outside the normal operation range. 6. Start the ispVM System software and push the SCAN button. You should see the LFE3-150E_ES device listed in the configuration setup window. If the LatticeECP3 device does not show up in ispVM, check that you have the proper cable type selected in ispVM menu Options > Cable and I/O Port Setup and select the Cable Type as Lattice (PC parallel port), USB or USB2 depending on the type of ispDOWNLOAD cable you are connecting to J10. 7. In the ispVM configuration setup window, left-click on the LFE3-150E_ES device to select it, with LFE3150EA_ES as the device to be used. 8. Click Edit > Edit Device to edit the device. A Device Information window will be opened. Click the Select button and select the package type 1156-ball fpBGA, then click OK. 9. Check that the Device Access Options drop-down menu control selects the JTAG 1532 Mode. Check that the Operation drop-down menu selects Fast Program. 10. Click the data file Browse button and select the path to the LatticeECP3 “.BIT” bitstream file then click OK. 11. Click Project >Download or the green Go button to download the bitstream into the LatticeECP3 device (U7). It will take about three minutes to download the bitstream for a PC parallel port download cable connection. You should see the D1 LED blinking as the bitstream loads. When the LatticeECP3 has loaded correctly, the ispVM status window will report “Operation Successful”. LatticeECP3 SRAM Configuration Using SPI Flash and a Lattice ispDOWNLOAD Cable at J10 The LatticeECP3 SRAM can be configured easily using the ispVM System software to download a bitstream to the on-board SPI Flash via an ispDOWNLOAD cable connected to the ‘Local JTAG’ header J10. The LatticeECP3 device is SRAM-based, so it must remain powered on to retain its configuration when programming the SRAM. The on-board SPI Flash retains its programmed bitstreams when power is off, and can quickly load programmed bitstreams into the LatticeECP3 device when power is applied. 38 LatticeECP3 I/O Protocol Board – Revision C User’s Guide 1. Attach a ground connection from test equipment chassis ground to the GND side of terminal block TB1. 2. Connect a Lattice USB download cable to the PC's USB port (or a Lattice parallel download cable to the PC's parallel printer port) and attach the 8-pin side of the cable to J10 pin 1 to pin 8 on the board (the leftmost eight pins of J10). The signals requiring connection at the ‘Local JTAG’ connector J10 are: Pin Signal Name Comment 1 VCC Leftmost pin 2 TDO 3 TDI 4 No connect 5 No connect 6 TMS 7 GND 8 TCK 3. Check that the jumpers are installed as shown in Figure 7. 4. Check that all levers of S1 and S4 are in the up position and all levers of SW5 are in the down position. 5. Connect the 12V wall power adaptor cable to J56. Check to see that the wall power adapter is plugged in to a 120 VAC source and the “12VIN GOOD” LED is lit. The vertical column of 10 LEDs to the left of the ispPACPOWR1220AT8 device should also be lit. LEDs near the ispPAC-POWR1220AT8 device that are on indicate that those power supplies are within the proper voltage range. If any of them are off, those supplies are either off, or outside the normal operation range. 6. Start the ispVM System software and push the Scan button. You should see the LFE3-150E_ES device listed in the configuration setup window. If the LatticeECP3 device does not show up in ispVM, check that you have the proper cable type selected in the ispVM menu Options > Cable and I/O Port Setup and select the Cable Type as Lattice (PC parallel port), USB or USB2 depending on the type of ispDOWNLOAD cable you are connecting to J10. 7. In the ispVM configuration setup window, left-click on the LFE3-150E_ES device to select it, with LFE3150EA_ES as the end device to be used. 8. Click Edit > Edit Device to edit the device. A Device Information window will be opened. Click the Select button and select the package type 1156-ball fpBGA then click OK. 9. Click the Device Access Options drop-down menu control and select SPI Flash Background Programming. A SPI Serial Flash Device window will open. 10. Push the Select button and select the Vendor as STMicro, the device as SPI-M25P64 and package 16-lead SOIC. Push the OK button. 11. Click the data file Browse button and select the path to the LatticeECP3 “.BIT” bitstream file. Push the Load From File button and then click OK. Again click OK to exit the Device Information menu. 12. Click Project > Download or the green Go button to download the bitstream into the SPI Flash device (U12). When using a parallel port download cable, it will take a little over three minutes to load the bitstream into the SPI Flash, then the same time again to verify it loaded properly. You will see the D1 LED blinking as the bitstream loads. This LED will be off as ispVM verifies the bitstream. After the SPI Flash contents have been verified, the ispVM status window will report “Operation Successful”. 13. Push the PROGRAMN button SW1 to load the design. The design will load into the LatticeECP3 (U7) from the external SPI Flash (U12) in 12 seconds, and the “DONE” LED (D5) will light. 39 LatticeECP3 I/O Protocol Board – Revision C User’s Guide ispPAC Configuration Using a Lattice ispDOWNLOAD Cable at J10 The ispPAC-POWR1220AT8 device has been programmed with a factory default bitstream at the board manufacturer. The factory design sets up the ispPAC-POWR1220AT8 to enable, trim and monitor the power supply regulator voltages to ensure that the supplies are within specification for proper operation of the LatticeECP3 and other devices on the board. The ispPAC-POWR1220AT8 can be re-configured easily using the ispVM System software to download a bitstream via an ispDOWNLOAD cable connected to the ‘Local JTAG’ header J10. The ispPAC-POWR1220AT8 device is non-volatile and once programmed it will retain new programming after powering down and will reconfigure with any new downloaded bitstream on power-up. If after modifying the ispPAC-POWR1220AT8 configuration, you would like to return the ispPAC-POWR1220AT8 device to the original factory default programming, a simple LatticeECP3 reference design is available for the board on the Lattice web site that includes the factory default design and bitstream for the ispPAC-POWR1220AT8 device. 1. Attach a ground connection from test equipment chassis ground to the GND side of terminal block TB1. 2. Connect a Lattice USB download cable to the PC’s USB port (or a Lattice parallel download cable to the PC’s parallel printer port) and attach the 8-pin side of the cable to J10 pin 1 to pin 8 on the board (the leftmost eight pins of J10). The signals requiring connection at the ‘Local JTAG’ connector J10 are: Pin Signal Name Comment 1 VCC Leftmost pin 2 TDO 3 TDI 4 No connect 5 No connect 6 TMS 7 GND 8 TCK 3. Check that the jumpers are installed as shown in Figure 7. 4. Remove the jumper on J60 and add it to J59. Also, move the jumper on J9 from shorting pin 3 to pin 5, so it now shorts pin 1 to pin 3 (move the jumper on J9 over to the leftmost, lowest pins). Install a jumper on J49. 5. Check that all levers of S1 are in the up position. 6. Connect the 12V wall power adaptor cable to J56. Check to see that the wall power adapter is plugged in to a 120 VAC source and the “12VIN GOOD” LED is lit. The vertical column of 10 LEDs to the left of the ispPACPOWR1220AT8 device should be lit. LEDs near the ispPAC-POWR1220AT8 device that are on indicate that those power supplies are within the proper voltage range. If any of them are off, those supplies are either off, or outside the normal operation range. 7. Start the ispVM System software and push the Scan button. The ispPAC-POWR1220AT8 device should now be listed in the configuration setup window. If this device does not show up in ispVM, check that you have the proper cable type selected in the ispVM menu Options > Cable and I/O Port Setup and select the Cable Type as Lattice (PC parallel port), USB or USB2 dependent on the type of ispDOWNLOAD cable you are connecting to J10. 8. In the ispVM configuration setup window, right-click on the ispPAC-POWR1220AT8 device and select Edit Device. A Device Information window will be opened. 9. Click the data file Browse button and select the path to the ispPAC-POWR1220AT8 “.JED” configuration file, then click OK. 40 LatticeECP3 I/O Protocol Board – Revision C User’s Guide 10. Click Project > Download or the green Go button to download the bitstream into the ispPAC-POWR1220AT8 device (U17). 11. Verify that the ispVM log window reports a successful download of the “.JED” file into the ispPACPOWR1220AT8 device. MachXO Configuration Using a Lattice ispDOWNLOAD Cable at J4 The MachXO device has been programmed with a factory default bitstream at the board manufacturer. The factory default bitstream sets up the MachXO to implement a built in USB download feature for the board at J2 using a standard USB cable. If the factory default bitstream is not loaded into the MachXO device, the built in USB download at J2 will not function. The MachXO can be re-configured easily using the ispVM System software to download a bitstream via an ispDOWNLOAD cable connected to the ‘XO JTAG’ header J4. The Lattice MachXO device is non-volatile and once programmed it will retain new programming after powering down and will reconfigure with a new downloaded bitstream on power-up. If after modifying the MachXO configuration, you would like to return the MachXO device to the original factory default programming, a simple LatticeECP3 reference design is available for the board on the Lattice web site that includes the factory default bitstream for the MachXO. 1. Attach a ground connection from test equipment chassis ground to the GND side of terminal block TB1. 2. Connect a Lattice USB download cable to the PC’s USB port (or a Lattice parallel download cable to the PC’s parallel printer port) and attach the 8-pin side of the cable to J4 pin 1 to pin 8 on the board. The signals requiring connection at the ‘XO JTAG’ connector J4 are: Pin Signal Name Comment 1 VCC Leftmost pin 2 TDO 3 TDI 4 No connect 5 No connect 6 TMS 7 GND 8 TCK 3. Check that the jumpers are installed as shown in Figure 7. 4. Check that all levers of S1 in the up position. 5. Connect the 12V wall power adaptor cable to J56. Check to see that the wall power adapter is plugged in to a 120 VAC source and the “12VIN GOOD” LED is lit. The vertical column of 10 LEDs to the left of the ispPACPOWR1220AT8 device should also be lit. LEDs near the ispPAC-POWR1220AT8 device that are on indicate that those power supplies are within the proper voltage range. If any of them are off, those supplies are either off, or outside the normal operation range. 6. Start the ispVM System software and push the Scan button. The LCMX02280C device should now be listed in the configuration setup window. If the MachXO device does not show up, check that you have the proper cable type selected in the ispVM menu Options > Cable and I/O Port Setup and select the Cable Type as Lattice (PC parallel port), USB or USB2 dependent on the type of ispDOWNLOAD cable you are connecting to J4. 7. In the ispVM configuration setup window, right-click on the LCMX02280C device and select Edit Device. A Device Information window will be opened. 8. Click the Select button and select the package type 256 ball ftBGA, then click OK. 41 LatticeECP3 I/O Protocol Board – Revision C User’s Guide 9. Check that Operation shows Flash Erase, Program, Verify is selected. 10. Check that Device Access Options shows Flash Programming Mode is selected. 11. Click data file Browse button and select the path to the MachXO “.JED” configuration file then click OK. 12. Click Project > Download or the green Go button to download the bitstream into the MachXO device (U5). 13. Verify that the ispVM log window reports a successful download of the “.JED” file into the LCMXO2280C device. Ordering Information Description Ordering Part Number LatticeECP3 I/O Protocol Board LFE3-150EA-IO-EVN LatticeECP3 I/O Protocol - ADC-DAC Interface Card LFE3-ADC-DAC-EVN China RoHS Environment-Friendly Use Period (EFUP) Technical Support Assistance Hotline: 1-800-LATTICE (North America) +1-503-268-8001 (Outside North America) e-mail: techsupport@latticesemi.com Internet: www.latticesemi.com Revision History Date Version Change Summary November 2009 01.0 Initial release. April 2010 01.1 Updated DDR3 text section. June 2010 01.2 Added sysIO Bank Voltages table. June 2010 01.3 Updated schematic. March 2012 01.4 Updated document with new corporate logo. Appendix A – Updated Programming schematic. Corrected U7 pin D33 symbol text. © 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 42 43 A B C D 4 5 (Sheet 14) (Sheet 8) Clock (Sheet 7) PCSB SMA Test Points, PCSB CLK, Ethernet CLK DDR3 Memory Dual 64 Bit DIMM A 1 4 3 SerDes (Sheet 7, 15) Bank3 (Sheet 9) 1000Base-T PHY/RJ45 3 (Sheet 12) Quad Quad Quad Quad C D B A (Sheet 13) Bank6 Bank2 (Sheet 12) Bank7 (Sheet 5) (Sheet 13) Lattice ECP3-150 1156 ball (Sheet 16) (Sheet 15) Bank8 Bank1 (top view) (Sheet 16, 17) Logic Analyzer Probe, LCD Connector, High Speed Test Points, High Current IO, Aux IO, USB2.0 to RS232 Bank0 (Sheet 15) 7 Segment, DIP Switch, LEDs ECP3 IO Protocol Evaluation Board Block Diagram 5 Date: Size C Title Friday, March 25, 2011 1 Sheet 1 of 18 ECP3 IO Protocol Eval Board Schematic Project Block Diagram C Rev Lattice Semiconductor Corporation 5555 N.E. Moore Court Hillsboro, Oregon. 97124 (Sheet 2, 11) (Sheet 3) (Sheet 10) MACHXO (Sheet 6) Built In USB 2.0 Download Voltage Regulators 2 1 Rev C, 1156 ball, -150EA Power Manager (Sheet 12) SPI4.2, LVDS Access, Test Points (Sheet 5) Programming 2 A B C D LatticeECP3 I/O Protocol Board – Revision C User’s Guide Appendix A. Schematic Figure 20. Block Diagram A B C ILIM IN CNTL GND OUT SENSE EN SC1592 TAB U22 1 2 3 4 5 6 7 PTH12060W R269 10K-0603SMT 5 R266 12_0V R240 2K-0603SMT R304 270R-0603SMT R268 909R-0603SMT GND 2 3_3V_TRIM [3] [3] 3_3V_FET + R246 100R-0603SMT 3_3V_FET C239 10UF-16V-TANTBSMT R2270R-0603SMT F1228CT-ND [3] 2_5V_TRIM C272 C249 + 2.5V 499R-0603SMT R267 0.80v 3_3VIN C36 + 2_5V S1 S2 S3 G Q25 DNI-0603SMT F6 F1228CT-ND 5A Fast-Blo SMT Socketed Fuse 4 D4 D3 D2 D1 8 7 6 5 F1251CT-ND 2 1 NTMS4503 SO8 DI C237 1 2 3 4 J49 HEADER 2 HD2x1 DI +12VDC 1 F2 5A Fast-Blo SMT Socketed Fuse 3_3VIN 1_00K-0603SMT R288 Terminal Block/ED1202DS TB1 2 Set PAC device to +0.6v offset for +/- 5% trim range about the nominal regulator output voltage 5_23K-0603SMT 1_07K-0603SMT 2_5V 2_5V_TRIM_R R86 100R-0805SMT GND 0.415v 5 6 3_3V_TRIM SENSE VOUT R239 Set PAC device to +0.8v offset for +/- 5% trim range about the nominal regulator output voltage [3] 2_5V_EN 8 GND 3.3v is always on, leave pin 3 open 1 VIN INHIBIT# 3 2 ADJUST 4 U14 3.3V GND 7 3_3V_TRIM_R 12_0V 3_3VIN 10 MUP 8 TRACK 9 MDWN D31 SCHOTTKY Vishay V12P10-E3/87A 2_5V_TRIM D 10UF-16V-TANTBSMT +10.8v to +13.2v 100NF-0603SMT + 12_0V R265 10K-0603SMT R262 3 R302 270R-0603SMT R264 2_0K-0603SMT [3] 1_5V_TRIM C271 C247 1_21K-0603SMT R263 + 1.5V 0.80v 3_3VIN VCC_CORE_EN [3] D30 LED-SMT1206_GREEN GND VIN 1.2V Core C34 + 1_5V VOUT SENSE F5 F1228CT-ND 5A Fast-Blo SMT Socketed Fuse R234 12_1K0603SMT 4_53K-0603SMT TP4 1 1 TP7 TP6 1 TP22 1 R291 1_00K-0603SMT TestPoint TestPoint TestPoint TestPoint TestPoint TestPoint VCC_CORE 330UF-FKSMT C212 + 2 ILIM IN CNTL GND OUT SENSE EN 1 2 3 4 5 6 7 12_0V R258 R301 270R-0603SMT R260 1_07K-0603SMT 499R-0603SMT 1_2V R84 100R-0805SMT GND Set PAC device to +0.8v offset for +/- 5% trim range about the nominal regulator output voltage R261 10K-0603SMT SC1592 TAB [3] 1_2V_EN 8 U20 Set PAC device to +0.6v offset for +11, -22% trim range about the nominal regulator output voltage VCC_TRIM [3] + 1_2V_TRIM_R VCC_CORE_MON [3] R290 1_00K-0603SMT F1228CT-ND 5A Fast-Blo SMT Socketed Fuse R176 F3 1 1 TP8 1 TP36 1 TP1 1 TP10 1 TP3 TP9 1 TP33 1 TP16 GND Pads Distributed around the board TestPoint TestPoint TestPoint TestPoint TestPoint TestPoint 0R-0603SMT C215 VCC_TRIM 5 6 D32 SCHOTTKY Vishay V12P10-E3/87A R228 PTH12060L 0.483v VCC_CORE_EN 1 2 U15 12_0V 12VIN GOOD R287 2_2K-1206SMT 12_0V G 1_07K-0603SMT 1_5V 1_5V_TRIM_R R85 100R-0805SMT GND 100UF-FKSMT C250 Set PAC device to +0.8v offset for +/- 5% trim range about the nominal regulator output voltage 1 2 3 4 5 6 7 330UF-FKSMT C213 + 3_3V ILIM IN CNTL GND OUT SENSE EN SC1592 TAB U21 + [3] 1_5V_EN 8 C214 R289 1_00K-0603SMT 3_3V_MON [3] + 470UF-FKSMT C37 D29 SCHOTTKY Vishay V12P10-E3/87A 10UF-16V-TANTBSMT POWER INPUT 330UF-FKSMT 3_3V_GATE F7 5A Fast-Blo SMT Socketed Fuse 3_3VIN 12_0VIN 1_5V_TRIM MUP 1 10UF-16V-TANTBSMT 10 INHIBIT# 3 8 TRACK J56 100NF-0603SMT VCC_TRIM_R GND 9 MDWN ADJUST 4 Male Power Jack 2.1mm 22HP037-2.1mm 3 330UF-FKSMT 10UF-16V-TANTBSMT Voltage Regulators 3_3VIN 7 2 Date: Size C Title 1 5016 1 C270 1 LP5 1 1 5016 C35 + 1_2V 1 5016 LP2 1 Voltage Regulators F4 F1228CT-ND 5A Fast-Blo SMT Socketed Fuse VCC_CORE 3_3V 2_5V Monday, August 17, 2009 1 Sheet 2 of 18 ECP3 IO Protocol Eval Board Schematic Project 1 5016 LP1 1 C Rev Lattice Semiconductor Corporation 5555 N.E. Moore Court Hillsboro, Oregon. 97124 C248 + 1.2V 1 LP6 1_2V 1_5V 1_0K-0603SMT R259 0.80v 3_3VIN 5016 LP3 1 1 5016 LP4 1 [3] 1_2V_TRIM 1_2V_TRIM 3 10UF-16V-TANTBSMT 4 100NF-0603SMT 44 330UF-FKSMT 5 A B C D LatticeECP3 I/O Protocol Board – Revision C User’s Guide Figure 21. Voltage Regulators A B C R73 1K-0603SMT C234 R74 3_01K-0603SMT 12_0V R76 1K-0603SMT C244 R75 3_01K-0603SMT 12_0VIN 1 2 3 ON R254 0R-0603SMT R250 6 5 4 R226 10K-0402SMT 0402 DI PAC_IN4 PAC_IN5 PAC_IN6 5 5 8 7 6 TP48 1_2V C218 C230 C223 3_3VIN D33 BAV74 52 51 47 46 50 48 54 53 56 55 58 57 62 61 64 63 66 65 68 67 70 69 72 71 R224 10K-0402SMT 0402 DI 1_5V 2_5V DDR3_VDD 0R-0603SMT R292 R293 3_3V C221 C217 VMON1+ VMON1GS VMON2+ VMON2GS VMON3+ VMON3GS VMON4+ VMON4GS VMON5+ VMON5GS VMON6+ VMON6GS VMON7+ VMON7GS VMON8+ VMON8GS VMON9+ VMON9GS VMON10+ VMON10GS VMON11+ VMON11GS 3_3VIN 3_3VIN 4 R235 10K-0402SMT [5,6] INITN [5,6] [5,6,14] DONE GSRN VMON12+ VMON12GS 100NF-0603SMT C241 C232 3_3VIN VCCIO_1 5_0V R72 10K-0402SMT 0402 DI 0R-0603SMT TP47 DDR3_VTT 3_3V_MON + VCC WP SCL SDA 24AA1025-ISM U19 GND A2 DDR3_VREF [2] VCC_CORE_MON [2] 3_3VIN D28 BAV74 SW DIP-3 CTS 194-3MST S1 0R-0603SMT 3_3VIN 4 3 A1 A0 EEPROM address = 0xA0 3_3V 2 22UF-16V-TANTBSMT 100NF-0603SMT 100NF-0603SMT 1 1UF-16V-0805SMT D 10NF-0603SMT 100NF-0603SMT U17 POWR1220AT8-1TN0I TQFP100 DI Lattice ispPAC PLDCLK TRIM8 TRIM7 TRIM6 TRIM5 TRIM4 TRIM3 TRIM2 TRIM1 HVOUT4 HVOUT3 HVOUT2 HVOUT1 OUT20 OUT19 OUT18 OUT17 OUT16 OUT15 OUT14 OUT13 OUT12 OUT11 OUT10 OUT9 OUT8 OUT7 OUT6 SMBA/OUT5 95 73 74 75 79 80 82 83 84 40 42 85 86 25 24 23 21 20 19 18 17 16 15 14 12 11 10 9 8 TCK_BUF TDISEL TDO_PAC TDO_ECP3 TDI_BUF Q23 [11] [2] TP23 ispPAC (5A fused) 3 DDR3_VDD_TRIM [11] 2_5V_TRIM [2] 1_5V_TRIM [2] 1_2V_TRIM [2] 3_3V_TRIM [2] VCC_TRIM [2] TP35 TP29 5_0V_FET 3_3V_FET TP34 TP30 12V INPUT R238 10K-0402SMT 0402 DI PLDCLK TRIM8 TRIM7 TRIM6 TRIM5 TRIM4 TRIM3 TRIM2 TRIM1 5_0V_FET 3_3V_FET PWR_GOOD_1_2V PWR_GOOD_VCC PWR_GOOD_3_3V PWR_GOOD_2_5V PWR_GOOD_1_5V PWR_GOOD_DDR3_VDD PWR_GOOD_DDR3_VTT PWR_GOOD_DDR3_VREF PWR_GOOD_5_0V PWR_GOOD_VCCIO_1 TP24 2N2222/SOT23 1 3_3VIN 1 2 1 TMS_BUF POL POL POL 1 D26 LED-SMT1206_GREEN Q19 2N2222/SOT23 1_2V_EN [2] D18 LED-SMT1206_GREEN PWR_GOOD_VCCIO_1 VCCIO_1 D19 LED-SMT1206_GREEN PWR_GOOD_5_0V 5.0V D20 LED-SMT1206_GREEN PWR_GOOD_DDR3_VREF DDR3_VREF D21 LED-SMT1206_GREEN PWR_GOOD_DDR3_VTT DDR3_VTT D22 LED-SMT1206_GREEN PWR_GOOD_DDR3_VDD DDR3_VDD D23 LED-SMT1206_GREEN PWR_GOOD_1_5V 1.5V D24 PWR_GOOD_2_5VLED-SMT1206_GREEN 2.5V 3.3V D25 LED-SMT1206_GREEN PWR_GOOD_3_3V PWR_GOOD_VCC VCC_CORE R213 10K-0402SMT [2] 1_2V MOSFET LDO LDO LDO (5A fused) Date: Size C Title (5A fused) 3_3V, +3.3V, 17A, 0.005 ohm 2 10K-0402SMT 10K-0402SMT Power Manager PWR_GOOD_VCCIO_1 PWR_GOOD_5_0V PWR_GOOD_DDR3_VREF PWR_GOOD_DDR3_VTT PWR_GOOD_DDR3_VDD PWR_GOOD_1_5V PWR_GOOD_2_5V PWR_GOOD_3_3V Friday, June 11, 2010 1 Sheet 3 of 18 ECP3 IO Protocol Eval Board Schematic Project PWR_GOOD_1_2V PWR_GOOD_VCC C Rev Lattice Semiconductor Corporation 5555 N.E. Moore Court Hillsboro, Oregon. 97124 10K-0402SMT 330R-0402SMT R215 R214 R203 330R-0402SMT 10K-0402SMT 330R-0402SMT R204 R216 R205 10K-0402SMT 330R-0402SMT R218 R217 R206 330R-0402SMT 10K-0402SMT R207 R219 330R-0402SMT 10K-0402SMT R208 330R-0402SMT 10K-0402SMT R220 R221 R209 330R-0402SMT 10K-0402SMT R210 R222 10K-0402SMT 330R-0402SMT R223 R211 330R-0402SMT 3_3VIN R212 ETH_1_2V, +1.2V, 1.5A 2_5V, +2.5V, 3A LDO 1_2V, +1.2V, 3A 1_5V, +1.5V, 3A (5A fused) (5A fused) (5A fused) VCC Core, +1.2v , 10A 1 POWER GOOD LEDS D27 LED-SMT1206_GREEN PWR_GOOD_1_2V 5_0V, +5.0V, 100ma Q20 2N2222/SOT23 3_3VIN VCC_CORE_EN 2 DDR3_VDD, +1.5V, 10A (10A fused) DDR3_VTT, +0.75V, +/- 3A DDR3_VREF, +0.75V, +/- 10mA MOSFET 1 R225 10K-0402SMT 3 3.3VIN, +2.5V, 10A Q21 2N2222/SOT23 3_3VIN DDR3_REG_EN Q22 2N2222/SOT23 [11] TMS_BUF [5] 1_5V_EN [2] J59 HEADER 2 Enable PAC in JTAG LDO R236 10K-0402SMT 3_3VIN 1 R245 10K-0402SMT 3_3VIN 10K-0402SMT R294 3 2_5V_EN [2] TCK_BUF [5] TDISEL [5] TDO_PAC [5] TDO_ECP3 [5] TDI_BUF [5] R252 10K-0402SMT 3_3VIN POL regulators powered from 12V are switchers 4 I2C_SCL [14] I2C_SDA [14] I2C Interface ispPAC address is programmable through JTAG TP25 Power Supply Block Diagram TP28 R242 10K-0402SMT 3_3VIN TP26 3 EEPROM 100NF-0603SMT VCCPROG 39 PAC_RESETn GNDD GNDD GNDD GNDD GNDD GNDD 3 22 36 43 88 98 3 5 10NF-0603SMT TP32 TP31 5 97 1 2 4 6 7 VCCINP IN1 IN2 IN3 IN4 IN5 IN6 PAC_MCLK 89 90 VPS0 VPS1 VCCD VCCD VCCD 93 92 SDA SCL 91 RESETb VPS0 VPS1 96 MCLK 13 38 94 VCCJ TDO TDI ATDI TMS TCK TDISEL 33 34 31 30 28 37 32 VCCA 60 G GNDA GNDA G 45 87 45 G 2 G 2 G 3 G 2 G 2 G 3 G 2 G Power Manager A B C D LatticeECP3 I/O Protocol Board – Revision C User’s Guide Figure 22. Power Manager A B C T13 W 13 T22 W 22 AA12 AA23 AC14 AC15 AC20 AC21 M14 M15 M20 M21 P12 P23 R12 R23 Y12 Y23 AC13 AC17 AC18 AC22 AD13 AD16 AD17 AD18 AD19 AD22 AE12 AE13 AE16 AE19 AE22 AE23 5 Pinout for ECP3 device density is shown on symbol as: -95/-150 ECP3-150EA-7FN1156C VCCPLL_L/VCCPLL_L VCCPLL_L/VCCPLL_L VCCPLL_R/VCCPLL_R VCCPLL_R/VCCPLL_R VCCAUX/VCCAUX VCCAUX/VCCAUX VCCAUX/VCCAUX VCCAUX/VCCAUX VCCAUX/VCCAUX VCCAUX/VCCAUX VCCAUX/VCCAUX VCCAUX/VCCAUX VCCAUX/VCCAUX VCCAUX/VCCAUX VCCAUX/VCCAUX VCCAUX/VCCAUX VCCAUX/VCCAUX VCCAUX/VCCAUX VCCAUX/VCCAUX VCCAUX/VCCAUX VCCA/VCCA VCCA/VCCA VCCA/VCCA VCCA/VCCA VCCA/VCCA VCCA/VCCA VCCA/VCCA VCCA/VCCA VCCA/VCCA VCCA/VCCA VCCA/VCCA VCCA/VCCA VCCA/VCCA VCCA/VCCA VCCA/VCCA VCCA/VCCA VCC/VCC VCC/VCC VCC/VCC VCC/VCC VCC/VCC VCC/VCC VCC/VCC VCC/VCC VCC/VCC VCC/VCC VCC/VCC VCC/VCC VCC/VCC VCC/VCC VCC/VCC VCC/VCC VCC/VCC VCC/VCC VCC/VCC VCC/VCC VCC/VCC VCC/VCC VCC/VCC VCC/VCC VCC/VCC VCC/VCC VCC/VCC VCC/VCC VCC/VCC VCC/VCC VCC/VCC VCC/VCC VCCPLL 3_3V VCCA VCC_CORE PP6 C8 VCCPLL 4 C28 C194 + FB5 C208 BLM41PG600SN1 3 PP7 1_5V C178 C267 C268 C33 C211 C159 C135 C101 C85 C90 PP9 C143 C200 3_3V C24 + C204 FB11 BLM41PG600SN1 1_2V C12 C22 C155 C94 C125 PP5 3_3V + C9 C171 C166 C145 C112 VCCA C105 C144 C11 C139 C10 C130 C133 C123 C128 C140 C115 C152 C107 C158 C95 3 C154 C14 C106 C157 VCC_CORE 1 1 VCC_CORE 1NF-0603SMT AA13 AA22 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 P13 P22 R13 R22 U13 U22 V13 V22 Y13 Y22 22UF-16V-TANTBSMT 10NF-0603SMT U7K 1UF-16V-0805SMT 100NF-0603SMT D 4 1UF-16V-0805SMT 1_2V 1_5V 1_2V 1_5V 1_2V 1_5V 1_2V 1_5V 2 2 + C173 + C185 + C138 BLM41PG600SN1 FB1 Date: Size B Title C4 C19 C15 C17 1UF-16V-0805SMT PCSA_VCCIB C150 PCSB_VCCIB C126 C137 Friday, June 11, 2010 1 Sheet 4 of 18 C Rev Lattice Semiconductor Corporation 5555 N.E. Moore Court Hillsboro, Oregon. 97124 PCSB_VCCOB C127 C121 C6 C124 PCSA_VCCOB C153 C172 C146 C160 C182 1 ECP3 IO Protocol Eval Board Schematic Project Core Power + C75 FB6 BLM41PG600SN1(NOB) BLM41PG600SN1 FB2 FB7 BLM41PG600SN1(NOB) BLM41PG600SN1 FB4 FB9 BLM41PG600SN1(NOB) BLM41PG600SN1 FB3 FB8 BLM41PG600SN1(NOB) 22UF-16V-TANTBSMT 2 Core Power 100NF-0603SMT 10NF-0603SMT 100NF-0603SMT 22UF-16V-TANTBSMT 2 100NF-0603SMT 10NF-0603SMT 10NF-0603SMT 100NF-0603SMT 10NF-0603SMT 100NF-0603SMT 100NF-0603SMT 10NF-0603SMT 100NF-0603SMT 10NF-0603SMT 100NF-0603SMT 10NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 10NF-0603SMT 100NF-0603SMT 22UF-16V-TANTBSMT 10NF-0603SMT 10NF-0603SMT 100NF-0603SMT 1UF-16V-0805SMT 10NF-0603SMT 100NF-0603SMT 10NF-0603SMT 100NF-0603SMT 10NF-0603SMT 100NF-0603SMT 1 2 100NF-0603SMT 10NF-0603SMT 10NF-0603SMT 1 2 100NF-0603SMT 100NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 22UF-16V-TANTBSMT 22UF-16V-TANTBSMT 22UF-16V-TANTBSMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 1UF-16V-0805SMT 1UF-16V-0805SMT 1UF-16V-0805SMT 1NF-0603SMT 1NF-0603SMT 1NF-0603SMT 46 1NF-0603SMT 5 A B C D LatticeECP3 I/O Protocol Board – Revision C User’s Guide Figure 23. Core Power A B C INITN 3_3V R141 10K-0603SMT C209 1 SW7 SW2 SW1 PROGRAMN GSRN 6 3 2Y 1Y 5 3 1 2 5 4 3 1 OUT2 OUT1 OUT2 OUT1 MAX6817 IN2 IN1 U23 MAX6817 IN2 IN1 SN74LVC125A/SO14 2A 2OE_N 1A 1OE_N 1 3_3V U11A SW PUSHBUTTON-SPST PROGRAMN SW PUSHBUTTON-SPST GSRN Pushbuttons SW PUSHBUTTON-SPST PB2 SW PUSHBUTTON-SPST SW6 U12 HOLD# CK VCC D DU1 DU8 DU2 DU7 DU3 DU6 DU4 DU5 S# VSS Q W# 4 6 4 6 M25P64-FLASH U24 1 2 3 4 5 6 7 8 D4 LED-SMT1206_RED 680R-0603SMT R121 16 15 14 13 12 11 10 9 11 8 PB2 PB1 4Y 3Y FPGA_MCLK FPGA_SISPI 3_3V CONFIG Status LEDs D3 LED-SMT1206_RED 680R-0603SMT R115 SPI FLASH 3_3V FPGA_CSSPI0N_DI SPI0_Q FLASH_DIS DONE DONE indicator will light when configuration is successfully completed PB1 R128 LED-SMT1206_GREEN C210 Q4 2N2222/SOT23 D5 220R-0603SMT G D 100NF-0603SMT 3 10NF-0603SMT LED-SMT1206_RED R191 10K-0603SMT 2 R110 D2 680R-0603SMT R R197 10K-0603SMT Y GSRN 3_3V 3_3V 12 13 9 10 SN74LVC125A/SO14 4A 4OE_N 3A 3OE_N U11B PB2 [12] PB1 [12] [3]TMS_BUF J60 HEADER 2 TMS_BUF [3]TCK_BUF [3] DONE [3] INITN 4 U7G ECP3-150EA-7FN1156C R188 10K-0603SMT R175 10K-0603SMT CFG0 CFG1 1(OFF) X X 1(OFF) 0(ON) 0(ON) CFG0 1(OFF) 0(ON) 1(OFF) 1(OFF) 0(ON) 0(ON) CFG1 SW5 6 5 4 XOBank2_16 XOBank2_23 XOBank01_1 XOBank2_22 XOBank2_24 XOBank2_25 XOBank3_8 XOBank3_9 XOBank3_10 XOBank3_11 XOBank3_12 XOBank3_13 SW DIP-3 CTS 194-3MST 1 2 3 ON LOCAL_TDI LOCAL_TMS LOCAL_TCK LOCAL_TDO DONE PROGRAMN XOBank1_24 XOBank1_23 XOBank1_18 XOBank1_17 XOBank1_22 XOBank1_1 CFG2 FPGA_SISPI FPGA_WRITEN FPGA_CCLK CFG0 CFG1 CFG2 GPIO_0 GPIO_1 GPIO_2 GPIO_3 GPIO_4 GPIO_5 R173 10K-0603SMT N25 P25 E31 E32 G34 H33 G33 G32 H34 J34 F32 F33 D33 D34 G30 F31 E34 F34 A32 A33 D30 D29 B32 C32 D31 C31 XOBank0_[0..23] XOBank1_[0..27] XOBank01_[0..1] XOBank2_[0..25] XOBank3_[0..27] XOBank4_[0..27] XOBank5_[0..19] XOBank45_[0..1] XOBank6_[0..27] XOBank7_[0..25] XOJTAG[0..3] XOBank3_14 XOBank3_15 XOBank3_16 XOBank3_17 XOBank3_18 XOBank3_19 XOBank3_20 XOBank3_21 XOBank3_0 XOBank3_1 XOBank2_14 XOBank2_15 XOBank0_[0..23] XOBank1_[0..27] XOBank01_[0..1] XOBank2_[0..25] XOBank3_[0..27] XOBank4_[0..27] XOBank5_[0..19] XOBank45_[0..1] XOBank6_[0..27] XOBank7_[0..25] XOJTAG[0..3] Pinout for ECP3 device density is shown on symbol as: -95/-150 1(OFF) X FPGA_CS1N R135 10K-0603SMT ispJTAG Slave Parallel Slave Serial SPIm SPI Flash Configuration Mode CONFIG CFG Switches 0(ON) CFG2 3_3V FPGA_D0 FPGA_D1 FPGA_D2 FPGA_D3 FPGA_D4 FPGA_D5 FPGA_D6 FPGA_D7 FPGA_CSN FPGA_CS1N FPGA_CSSPI1N_DOUT FPGA_CSSPI0N_DI 1 2 3 HEADER 3 J30 3_3V CFG0/CFG0 PR10A/PR10A/WRITEN CFG1/CFG1 PR10B/PR10B/D0/SPIFASTN PR11A/PR11A/D1 CFG2/CFG2 PROGRAMN/PROGRAMN PR11B/PR11B/D2 PR13A/PR13A/D3/SI DONE/DONE PR13B/PR13B/D4/SO INITN/INITN CCLK/CCLK PR14A/PR14A/D5 PR14B/PR14B/D6/SPID1 PR16A/PR16A/D7/SPID0 PR16B/PR16B/BUSY/SISPI/AVDN PR5A/PR5A PR5B/PR5B/DI/CSSPI0N/CEN PR7A/PR7A/CS1N/HOLDN/CONT2N/RDY PR7B/PR7B/CSN/SN/CONT1N/OEN PR8A/PR8A/DOUT/CSON/CSSPI1N PR8B/PR8B/MCLK PT140A/PT176A/XD8 PT140B/PT176B/XD9 PT142A/PT178A/XD10 PT142B/PT178B/XD11 BANK 8 PT143A/PT179A/XD12 PT143B/PT179B/XD13 PT145A/PT181A/XD14 VCCJ/VCCJ PT145B/PT181B/XD15 TCK/TCK TDI/TDI TDO/TDO VCCIO8/VCCIO8 VCCIO8/VCCIO8 TMS/TMS MACHXO K10 D1 E1 C1 D2 B33 F30 D32 B34 G31 C33 C34 [6] USB Download [10] 10K-0402SMT R295 3_3VIN TCK_BUF TDI_BUF TDO_ECP3 3_3V CFG0 CFG1 CFG2 PROGRAMN DONE INITN FPGA_CCLK R244 R120 [3]TDO_ECP3 R142 Enable ECP3 in JTAG 10K-0603SMT R109 3_3V 10K-0603SMT 3_3V R196 10K-0603SMT 10K-0603SMT INITN indicator will light if an error occurs during configuration programming 4_7K-0603SMT 4_7K-0603SMT C32 C26 100NF-0603SMT 100NF-0603SMT 5 VCC 5 VCC R270 R89 Y PROGRAMN R71 OPEN-0603SMT R70 OPEN-0603SMT R55 OPEN-0603SMT R44 OPEN-0603SMT R194 10K-0603SMT 10K-0603SMT 2 1 1 2 3 3 3_3V FPGA_WRITEN FPGA_D0 FPGA_D1 FPGA_D2 FPGA_D3 FPGA_D4 FPGA_D5 FPGA_D6 FPGA_D7 FPGA_SISPI GSRN FPGA_CSSPI0N_DI FPGA_CS1N FPGA_CSN FPGA_CSSPI1N_DOUT FPGA_MCLK GPIO_0 GPIO_1 GPIO_2 GPIO_3 GPIO_4 GPIO_5 I2C_SDA I2C_SCL HEADER 3 J29 1 2 HEADER 2 J17 LOCAL_TRSTN 4 6 OUT Y2 OUT Y1 [3,6] TCK_BUF [3,6] TMS_BUF GND_POWER TCK_BUF TMS_BUF 4 6 GND OUT Y2 OUT Y1 NC7WZ16-MACO6A/Fairchild TinyLogic R95 330R-0603SMT D1 LED-SMT1206_GREEN This LED indicates activity on TDI. TDI_BUF 3_3V 3_3V U4 IN A2 IN A1 U6 IN A2 IN A1 3 2 3 1 Buffer R94 HEADER 17X2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 TDI TDO 2 4 6 HEADER 3X2 PROGRAMN J9 1 3 5 3_3V LOCAL_TMS LOCAL_TCK DONE INITN LOCAL_TDO LOCAL_TDI PROGRAMN INITN 4.7K 4.7K 4.7K 1.0K 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 TDO_MB TDI_MB PROGRAMN_MB TRSTN_MB TP11 TMS_BUF TCK_BUF DONE INIT_MB 1 FPGA_WRITEN CFG0 CFG1 CFG2 FPGA_D6 3_3V INITN PROGRAMN Date: Size C Title LOCAL_TRSTN J24 HEADER 2 DI HD2X1 VCC INITN GND DONE TCK TMS NC ispEN_N TDI TDO 7 1 JTAG, PAC + ECP3 JTAG, ECP3 Only board, TDO_MB board, TDI_MB = ECP3 board, TDI_MB = PAC VCC INITN GND DONE TCK TMS NC ispEN_N TDI TDO 7 1 3_3V Friday, June 11, 2010 1 Sheet 5 of 18 C Rev Lattice Semiconductor Corporation 5555 N.E. Moore Court Hillsboro, Oregon. 97124 TMS GND TCK DONE INITn +3.3V TDO TDI PROGRAMn HEADER 10 2 3 4 5 6 8 9 10 J10 INITn Chain Open: INITn Local Shunt: Local & Offboard HEADER 10 2 3 4 5 6 8 9 10 J11 INITn_MB TMS GND TCK DONE NC TDO_MB TDI_MB PROGRAMn_MB Local Local Multi Multi Multi Multi-board JTAG (J11) ECP3 IO Protocol Eval Board Schematic Project TDO_MB TDI_MB TDO Chaining (J9) TDO_ECP3 TDO_PAC Programming TP12 J18 HEADER 2 DI HD2X1 EXBV8V472JV PROGRAMn Chain Open: PGM Local Shunt: Local & Offboard TDO_ECP3 TDO_PAC TDO PAC TDI ATDI TDISEL TDI_BUF TDO_ECP3 JTAG Daisy Chain Block Diagram ECP3 J5 sysCONFIG Connector FPGA_CCLK FPGA_SISPI FPGA_CSSPI0N_DI FPGA_CSSPI1N_DOUT DONE FPGA_D7 FPGA_D6 FPGA_D5 FPGA_D4 FPGA_D3 FPGA_D2 FPGA_D1 FPGA_D0 FPGA_CSN FPGA_CS1N 3_3V TDO Chaining (J9) 1-3: Local JTAG, PAC + ECP3 3-5: Local JTAG, ECP3 Only 1-2, 3-4: Multi Board JTAG, PAC + ECP3 3-4, 5-6: Multi Board JTAG, ECP3 only TDI_BUF TMS_BUF TCK_BUF SPIFASTN R117 10K-0603SMT SPI0_Q 4_7K-0603SMT [3] TDO_PAC LOCAL_TDO LOCAL_TDI LOCAL_TMS 1 1 2 HEADER 2 J25 LOCAL_TCK Built in USB Download (ispVM at J2) NC7WZ16-MACO6A/Fairchild TinyLogic JTAG R99 4.7K TDISEL [3,13] [3,13] PAC selects short : ATDI open : TDI TDISEL [3] TDI_BUF [3] 3_3V I2C_SDA I2C_SCL R140 10K-0603SMT R144 10K-0603SMT GSRN [3,5,6] FPGA_CSN R122 10K-0603SMT 2 C84 100NF-0603SMT 3 R 5 VCC GND 1 2 4 C119 Multi-board JTAG header 3_3V 100R-0603SMT 100NF-0603SMT 4_7K-0603SMT R257 GND RN21D GND 2 GND 2 R186 100R-0603SMT 4_7K-0603SMT R93 7 RN21B C74 Programming R187 14 VCC RN21C 2 5 VCC GND 2 4 LOCAL_TCK 5 1 RN21A 8 TDO_PAC 2 7 LOCAL_TDI 3 LOCAL_TMS 6 47 1 2 INITN C71 DONE Local JTAG header (ispVM) GSRN 100NF-0603SMT PROGRAMN Local JTAG (ispVM at J10) 100NF-0603SMT 5 A B C D LatticeECP3 I/O Protocol Board – Revision C User’s Guide Figure 24. Programming A B C D R98 300K DI SM/R_0603 USB_RESETn C76 1uF DI SM/C_0603 3_3V USB 2.0 Download J2 DI 5 1 2 VCC OUT 4 3 1 2 3 4 5 6 2 1 3 4 USB_RESETn SW3 PUSHBUTTON DI SMT_SW C253 10NF-0603SMT TP55 USBUSB+ USB_CONN_B TH_TYPE_B 24MHz DI OSC_SMT EN GND Y1 CLK_EN 0.1uF 3_3V SM/C_0402 R92 4.7K DI SM/R_0402 C68 DI USB 2.0 Download USB Reset GND TP TP2 USB26 USB25 USB24 4 L2 Ferrite_bead DI BD0603 AVCC GND_POWER C69 0.1uF DI SM/C_0402 GND C72 0.1uF DI SM/C_0402 C3 C73 0.1uF DI SM/C_0402 3 MACHXO USB0 USB1 USB2 USB3 USB4 USB5 USB6 USB7 USB8 USB9 USB10 USB11 USB12 USB13 USB14 USB15 USB16 USB17 3 [9] Programming [10] PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PD0 PD1 100NF-0603SMT 22UF-16V-TANTBSMT USB7 47 USB6 46 USB5 45 USB4 44 USB3 43 USB2 42 USB1 41 USB0 40 USB23 3 USB22 2 USB21 1 USB20 56 USB19 55 USB18 54 USB17 53 USB16 52 USB15 32 USB14 31 USB13 30 USB12 29 USB11 28 USB10 27 USB9 26 USB8 25 + C70 CY7C68013A DI SSOP56 PA7/FLAGD/SLCS# PA6/PKTEND PA5/FIFOADR1 IFCLK/T0OUT PA4/FIFOADR0 CLKOUT/T1OUT PA3/W U2 XTALOUT PA2/SLOE PA1/INT1# XTALIN PA0/INT0# DPLUS PD7/FD15 DMINUS PD6/FD14 PD5/FD13 W AKEUP PD4/FD12 RESET# PD3/FD11 RESERVED PD2/FD10 PD1/FD9 PD0/FD8 SCL SDA PB7/FD7 PB6/FD6 RDY0/SLRD PB5/FD5 RDY1/SLW R PB4/FD4 PB3/FD3 CTL2/FLAGC PB2/FD2 CTL1/FLAGB PB1/FD1 CTL0/FLAGA PB0/FD0 3_3V 38 37 36 8 9 22 23 USB28 USB27 USB30 USB29 15 16 USB+ USB- 51 49 21 11 12 24MHz USB32 USB31 20 5 USB34 USB33 U3 3_3V 4 6 18 24 34 39 50 10 14 VCC VCC VCC VCC VCC VCC AVCC AVCC GND GND GND GND GND GND AGND AGND 48 4 7 19 33 35 48 13 17 5 XOBank0_[0..23] XOBank1_[0..27] XOBank01_[0..1] XOBank2_[0..25] XOBank3_[0..27] XOBank4_[0..27] XOBank5_[0..19] XOBank45_[0..1] XOBank6_[0..27] XOBank7_[0..25] XOJTAG[0..3] XOBank7_13 XOBank7_12 XOBank7_11 XOBank7_10 XOBank7_7 XOBank7_6 XOBank7_5 XOBank7_4 XOBank6_17 XOBank6_16 XOBank6_19 XOBank6_18 XOBank6_23 XOBank6_22 XOBank6_27 XOBank6_26 XOBank7_25 XOBank7_24 2 XOBank7_21 XOBank7_20 XOBank7_17 XOBank7_16 XOBank6_0 XOBank7_14 XOBank6_15 XOBank6_14 XOBank6_13 XOBank6_11 XOBank6_7 XOBank6_9 XOBank6_8 XOBank7_15 XOBank6_12 XOBank6_5 XOBank6_24 XOBank4_5 XOBank0_[0..23] XOBank1_[0..27] XOBank01_[0..1] XOBank2_[0..25] XOBank3_[0..27] XOBank4_[0..27] XOBank5_[0..19] XOBank45_[0..1] XOBank6_[0..27] XOBank7_[0..25] XOJTAG[0..3] USB18 USB19 USB20 USB21 USB22 USB23 USB24 USB25 USB26 USB27 USB28 USB29 USB30 USB31 USB32 USB33 USB34 2 PD2 PD3 PD4 PD5 PD6 PD7 CTL0 CTL1 CTL2 RDY1 RDY0 SDA SCL RESETn WAKEUP CLKO IFCLK Date: Size B Title 1 2 3 PU0 TCK_XO XO TSALL 1-2: XO I/O Hi-Z 2-3: XO I/O active Monday, August 17, 2009 1 Sheet 6 of 18 C Rev Lattice Semiconductor Corporation 5555 N.E. Moore Court Hillsboro, Oregon. 97124 ECP3 IO Protocol Eval Board Schematic Project XOBank6_10 R106 4.7K SM/R_0402 DI TMS_XO XOJTAG3 TDO_XO TDI_XO XOJTAG2 XOJTAG1 XOJTAG0 Jumper 1-2 : Local JTAG uses parallel port cable Jumper 2-3 : Local JTAG uses USB port cable HEADER_3 HD3x1 DI J20 3_3V 3_3V USB 2.0 Download DI JBLOCK JB1 J4 CON8 HD8x1 DI 1 2 3 4 5 6 7 8 XO JTAG header 1 A B C D LatticeECP3 I/O Protocol Board – Revision C User’s Guide Figure 25. USB 2.0 Download A B C AL17 AK17 AL16 AK16 AL15 AK15 AL14 AK14 AP17 AN17 AP16 AN16 AP15 AN15 AP14 AN14 AH15 AH16 AF17 AF16 AF15 AF14 AG17 AG16 AG15 AG14 5 PCSB_VCCOB PCSB_VCCIB PCSB_HDINP0 PCSB_HDINN0 PCSB_HDINP1 PCSB_HDINN1 PCSB_HDINP2 PCSB_HDINN2 PCSB_HDINP3 PCSB_HDINN3 PCSB_HDOUTP0 PCSB_HDOUTN0 PCSB_HDOUTP1 PCSB_HDOUTN1 PCSB_HDOUTP2 PCSB_HDOUTN2 PCSB_HDOUTP3 PCSB_HDOUTN3 PCSB_REFCLKP PCSB_REFCLKN PCSA_VCCOB PCSA_VCCIB CLK_125M_P CLK_125M_N ETH_SIN_P ETH_SIN_N R108 SMA 1 J8 SMA + 2 3 4 5 2 3 4 5 J26 J21 SMA 4 HI = INT LO = EXT 2 3 4 5 PCSB_HDINN2 2 1 NC DIS# R31 3_3V Q Q_N PCSB_OSC_P PCSB_OSC_N 4 5 R28 PCSB_CLK_SEL + R112 NOTE: PLACE TERMINATIONS CLOSE TO U8 C179 U8A 3 + MUX 2 3 4 5 R174 Ethernet REF CLK disable J40 + Q0 Q0_N PCSB_RCQN PCSB_RCQP 3_3V R119 1_0K-0603SMT R118 R25 49_9R-0603SMT R125 324R-0603SMT 18 19 2 3 4 5 2 3 4 5 SMA 1 J38 SMA 1 J37 2 1 NC DIS# R123 Q Q_N Date: Size B Title 4 R67 49_9R-0603SMT 5 24_9R-0603SMT R66 R192 49_9R-0603SMT Friday, June 11, 2010 1 Sheet 7 of 18 ECP3 IO Protocol Eval Board Schematic Project PCSB_HDOUTN3 R68 24_9R-0603SMT CLK_125M_P CLK_125M_N R69 49_9R-0603SMT NOTE: PLACE TERMINATIONS CLOSE TO Y4 SMA 1 PCSB_HDOUTN1 C Rev Lattice Semiconductor Corporation 5555 N.E. Moore Court Hillsboro, Oregon. 97124 R190 49_9R-0603SMT SERDES 0.75v p-p diff unterminated 24_9R-0603SMT R26 2 SMA 2 3 4 5 J52 1 PCSB_HDOUTP3 1 J51 SMA 2 3 4 5 J44 PCSB_HDOUTP1 1 SMA 1 J43 Y4 CW-P423-125.00MHZ R27 49_9R-0603SMT R24 24_9R-0603SMT PCSB_REFCLKP PCSB_REFCLKN Place termination resistors next to U8 HEADER 2 1 2 2 3 4 5 PCSB_HDOUTN2 125 MHZ 2 3 4 5 PCSB_HDOUTN0 ETHERNET CLK R56 1_0K-0603SMT PCSB_HDOUTP2 1_6R-0603SMT 3_3V SMA 1 2 PCSB_HDOUTP0 Max toggle rate is 1GHz through MC100LVEL56 3_3V MC100LVEL56 COM_SEL SEL0 VBB0 D0B_N D0B D0A_N D0A All high speed signals use 50 ohm traces PCSB CLK MUX R116 348R-0603SMT HI = A in LO = B in 16 17 3 5 EXT_PCSB_CLK_RN 2 1 C151 PCSB_HDINN3 R18 130R-0603SMT SMA 1 82R-0603SMT 82R-0603SMT 4 n.c. 2 3 4 5 R113 3_3V EXT_PCSB_CLK_RP NOTE: PLACE TERMINATIONS CLOSE TO U8 3_3V R19 130R-0603SMT SMA 1 PCSB_HDINP3 1 J34 J35 2 3 4 5 SMA PCSB_HDINN1 SMA 1 J27 J28 2 3 4 5 J23 PCSB_HDINP1 PCSB SMA TEST POINTS SMA 1 J22 Y2 CW-P423-156.25MHZ R129 R124 { LVCMOS25 } [12] PCSB_CLK_SEL 100NF-0603SMT C148 1EXT_PCSB_CLK_N SMA 100NF-0603SMT C132 1EXT_PCSB_CLK_P EXT PCSB CLK R107 130R-0603SMT 2 3 4 5 PCSB_HDINN0 156.25 MHZ SMA 1 J14 SMA 1 INT PCSB CLK R15 1_0K-0603SMT 2 3 4 5 PCSB_HDINP2 1_6R-0603SMT 3_3V 2 3 4 5 PCSB_CLK_SEL ETH_SIN_P [9] ETH_SIN_N [9] ETH_SOUT_P [9] ETH_SOUT_N [9] 100NF-0603SMT ETH_SOUT_P ETH_SOUT_N Pinout for ECP3 device density is shown on symbol as: -95/-150 LFE3-150EA-7FN1156C SERDES Quads A & B PCSB_HDINP0/PCSB_HDINP0 PCSB_HDINN0/PCSB_HDINN0 PCSB_HDINP1/PCSB_HDINP1 PCSB_HDINN1/PCSB_HDINN1 PCSB_HDINP2/PCSB_HDINP2 PCSB_HDINN2/PCSB_HDINN2 PCSB_HDINP3/PCSB_HDINP3 PCSB_HDINN3/PCSB_HDINN3 PCSB_HDOUTP0/PCSB_HDOUTP0 PCSB_HDOUTN0/PCSB_HDOUTN0 PCSB_HDOUTP1/PCSB_HDOUTP1 PCSB_HDOUTN1/PCSB_HDOUTN1 PCSB_HDOUTP2/PCSB_HDOUTP2 PCSB_HDOUTN2/PCSB_HDOUTN2 PCSB_HDOUTP3/PCSB_HDOUTP3 PCSB_HDOUTN3/PCSB_HDOUTN3 PCSB_REFCLKP/PCSB_REFCLKP PCSB_REFCLKN/PCSB_REFCLKN PCSB_VCCIB0/PCSB_VCCIB0 PCSB_VCCIB1/PCSB_VCCIB1 PCSB_VCCIB2/PCSB_VCCIB2 PCSB_VCCIB3/PCSB_VCCIB3 PCSB_VCCOB0/PCSB_VCCOB0 PCSB_VCCOB1/PCSB_VCCOB1 PCSB_VCCOB2/PCSB_VCCOB2 PCSB_VCCOB3/PCSB_VCCOB3 AL21 AK21 AL20 AK20 AL19 AK19 AL18 AK18 AP21 AN21 AP20 AN20 AP19 AN19 AP18 AN18 AH19 AH20 AF21 AF20 AF19 AF18 AG21 AG20 AG19 AG18 10UF-16V-TANTBSMT U7H PCSA_HDINP0/PCSA_HDINP0 PCSA_HDINN0/PCSA_HDINN0 PCSA_HDINP1/PCSA_HDINP1 PCSA_HDINN1/PCSA_HDINN1 PCSA_HDINP2/PCSA_HDINP2 PCSA_HDINN2/PCSA_HDINN2 PCSA_HDINP3/PCSA_HDINP3 PCSA_HDINN3/PCSA_HDINN3 PCSA_HDOUTP0/PCSA_HDOUTP0 PCSA_HDOUTN0/PCSA_HDOUTN0 PCSA_HDOUTP1/PCSA_HDOUTP1 PCSA_HDOUTN1/PCSA_HDOUTN1 PCSA_HDOUTP2/PCSA_HDOUTP2 PCSA_HDOUTN2/PCSA_HDOUTN2 PCSA_HDOUTP3/PCSA_HDOUTP3 PCSA_HDOUTN3/PCSA_HDOUTN3 PCSA_REFCLKP/PCSA_REFCLKP PCSA_REFCLKN/PCSA_REFCLKN PCSA_VCCIB0/PCSA_VCCIB0 PCSA_VCCIB1/PCSA_VCCIB1 PCSA_VCCIB2/PCSA_VCCIB2 PCSA_VCCIB3/PCSA_VCCIB3 PCSA_VCCOB0/PCSA_VCCOB0 PCSA_VCCOB1/PCSA_VCCOB1 PCSA_VCCOB2/PCSA_VCCOB2 PCSA_VCCOB3/PCSA_VCCOB3 2 3 4 5 C13 100NF-0603SMT C131 D C147 PCSB_HDINP0 82R-0603SMT 130R-0603SMT 1 3 2 3 4 5 6 VCC GND 82R-0603SMT 130R-0603SMT C206 J13 10NF-0603SMT 100NF-0603SMT J7 C164 100NF-0603SMT 10UF-16V-TANTBSMT SERDES 10NF-0603SMT 20 C207 3 49_9R-0603SMT 100NF-0603SMT 4 49_9R-0603SMT 49 VCC C27 6 VCC GND 3 5 A B C D LatticeECP3 I/O Protocol Board – Revision C User’s Guide Figure 26. SERDES A B C 5 EXT CLK 2 3 4 5 2 3 4 5 J36 J33 SMA 1 SMA 1 1_6R-0603SMT C21 100NF-0603SMT C187 C199 C202 100NF-0603SMT EXT_CLK_N 100NF-0603SMT C205 4 HI = INT LO = EXT NC DIS# Q_N Q R145 R34 3_3V R33 CLK_SEL 3_3V 9 10 EXT_CLK_R_P EXT_CLK_R_N 3_3V MUX MC100LVEL56 SEL1 VBB1 D1B_N D1B D1A_N D1A U8B + Q1 Q1_N CLK_RN 12 3_3V 3 All high speed signals use 50 ohm traces 1_0K-0603SMT R143 R101 R100 51_1R-0603SMT CLK_RP 13 R137 3_3V R11 130R-0603SMT Max toggle rate is 1 GHz through MC100LVEL56 CLK MUX HI = A in LO = B in 15 8 6 7 CLK_100M_P + C174 3_3V 82R-0603SMT R147 NOTE: PLACE TERMINATIONS CLOSE TO U8 DEVICE. R36 130R-0603SMT C16 CLK_100M_N R146 82R-0603SMT 348R-0603SMT R130 R138 3_3V 5 4 Y3 R35 CW-P423-100.00MHZ 130R-0603SMT INT CLK 2 1 100 MHZ { LVCMOS25 } [12] CLK_SEL NOTE: PLACE TERMINATIONS CLOSE TO U8 DEVICE. 130R-0603SMT 100NF-0603SMT EXT_CLK_P CLK_SEL + R163 10UF-16V-TANTBSMT 6 VCC R45 1_0K-0603SMT C181 GND 82R-0603SMT 130R-0603SMT 100NF-0603SMT 3 82R-0603SMT 130R-0603SMT 10NF-0603SMT R156 10NF-0603SMT 14 VCC 3_3V VEE 11 3 324R-0603SMT 4 30_9R-0603SMT 50 R105 DDR3_CLK_P DDR3_CLK_N 2 CLK_P [12] Date: Size B Title Monday, August 17, 2009 1 Sheet 8 of 18 C Rev Lattice Semiconductor Corporation 5555 N.E. Moore Court Hillsboro, Oregon. 97124 1 ECP3 IO Protocol Eval Board Schematic Project Clock Set reciever to LVDS unterminated 1.5v p-p diff LVPECL Set reciever to SSTL15D unterminated CLK_N [12] DDR3_CLK_P [13] DDR3_CLK_N [13] CLK_N CLK_P HI = 0.893v LO = 0.608v R134 33 R102 51_1R-0603SMT R139 33 Place 33 ohm resistors at CLK inputs and other 6 resistors at DDR3_CLK inputs R13 130R-0603SMT 2 30_9R-0603SMT D Clock 5 A B C D LatticeECP3 I/O Protocol Board – Revision C User’s Guide Figure 27. Clock A B GND 5 8 GND EN IN U13 LT1963-ADJ DI SO-8 2_5V GND C225 0_1uF CC0402 DI GND R78 4_7K CR0603 DI ADJ OUT R79 4_7K CR0603 DI 2 1 GND 5 + R82 4_7K CR0603 DI R83 4_7K CR0603 DI ETH_CFG0 ETH_CFG1 ETH_CFG2 ETH_CFG3 ETH_CFG4 ETH_CFG5 ETH_CFG6 ETH_CFG0 ETH_CFG1 ETH_CFG2 ETH_CFG3 ETH_CFG4 ETH_CFG5 ETH_CFG6 ETH_LED_10 ETH_LED_100 ETH_LED_1000 ETH_LED_DUPLEX ETH_LED_RX ETH_LED_TX C228 C243 C222 ETH_1_2V GND GND C236 0_1uF CC0402 DI AVDD GND TP5 GND 4 GND TP39 C242 0_22uF + C224 CC0603 DI GND R230 4_7K CR0402 DI ETH_COMA DI CR0402 ETH_CLK25_PRIMARY C219 GND R256 22 OSC bypass C238 0_1uF CC0402 DI CLK25 R81 4_7K CR0603 DI C216 GND C233 0_1uF CC0402 DI 4 3 3_3V R80 4_7K CR0603 DI C231 0_01uF CC0402 DI VCC OUT 25MHz DI OSC_SMT EN GND Y5 2_5V VDDO bypass 1 2 R255DNI 4_7KCR0603 C227 0_01uF CC0402 DI 2_5V DVDD bypass C246 0_1uF CC0402 DI GND 3_3V R77 4_7K CR0603 DI 47UF-10V-TANTBSMT C TP46 TP45 TP44 TP43 TP42 2_5V GND TP41 1UF-16V-0805SMT TP40 2_5V 100NF-0603SMT 2_5V TP76 ETH_LED_RX D (000) TP70 (001) TP69 (010) TP71 (011) TP72 (100) TP73 (101) TP74 (110) TP75 (111) 1000Base-T PHY/RJ45 ETH_LED_1000 10NF-0603SMT GND GND GND GND 3 6 7 ETH_LED_10 100NF-0603SMT GTX_CLK COMA XTAL1 XTAL2 125CLK CRS COL CONFIG0 CONFIG1 CONFIG2 CONFIG3 CONFIG4 CONFIG5 CONFIG6 SEL_FREQ RX_DV RX_ER RX_CLK RXD0 RXD1 RXD2 RXD3 RXD4 RXD5 RXD6 RXD7 TX_EN TX_ER TX_CLK TXD0 TXD1 TXD2 TXD3 TXD4 TXD5 TXD6 TXD7 2_5V 3 AVDD R237 49_9 CR0402 DI GND R241 49_9 CR0402 DI GND MD1_BIAS C226 0_01uF CC0402 DI 3 R243 49_9 CR0402 DI ETH_MD1_P ETH_MD1_N ETH_MD0_P GND ETH_RSET_N M2 L7 K8 L8 L9 M9 R248 49_9 CR0402 DI GND DI CR0402 R253 49_9 CR0402 DI ETH_MD3_N ETH_MD3_P TP37 TP38 2 J53 R200 220 R201 220 R198 220 ETH_LED_DUPLEX ETH_LED_1000 ETH_LED_100 R202 220 RJ45 DI RJ45_PTH ETH_LED_10 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PHY_MDIO PHY_MDC PHY_RESET_N PHY_INT_N D13 DI YELLOW_LEDCR0603 DI CR0603 ETH_LED_DUPLEX_PU D15 DI GREEN_LED CR0603 DI CR0603 ETH_LED_1000_PU D16 DI DI AMBER_LED CR0603 CR0603 ETH_LED_100_PU D17 DI ORANGE_LEDCR0603 DI CR0603 ETH_LED_10_PU [12] PHY_MDIO PHY_MDC PHY_RESET_N PHY_INT_N 1 Date: Size B Title 1000Base-T PHY/RJ45 Tuesday, September 08, 2009 1 Sheet 9 of 18 ECP3 IO Protocol Eval Board Schematic Project 2_5V C Rev Lattice Semiconductor Corporation 5555 N.E. Moore Court Hillsboro, Oregon. 97124 Place 49 ohm termination resistors as close as possible to G-PHY. The associated 0.01uF capacitor should be placed close to the 49 ohm resistors. ETH_SOUT_P [9] ETH_SOUT_N [9] GND 2_5V ETH_LED_RX ETH_LED_RX_PU ETH_LED_TX ETH_LED_TX_PU ETH_MD3_P ETH_MD3_N ETH_MD0_N ETH_MD0_P AVDD ETH_MD2_N ETH_MD2_P ETH_MD1_P ETH_MD1_N R249 220 DI CR0402 DI CR0402 2 ETH_SIN_P [9] ETH_SIN_N [9] R232 4_99K R231 1_5K R229 220 DI CR0402 625 MHz MD3_BIAS C240 0_01uF CC0402 DI R251 49_9 CR0402 DI HSDAC_TP HSDAC_n_TP ETH_SOUT_P ETH_SOUT_N A7 A8 M5 M6 ETH_SCLK ETH_SCLK_n A5 A6 ETH_SIN_P ETH_SIN_N PHY_RESET_N PHY_INT_N K3 L1 A3 A4 PHY_MDIO PHY_MDC M1 L3 ETH_MD2_N MD2_BIAS C235 0_01uF CC0402 DI R247 49_9 CR0402 DI ETH_MD3_P ETH_MD3_N N8 N9 ETH_LED_1000 ETH_LED_100 ETH_LED_10 ETH_LED_DUPLEX ETH_LED_RX ETH_LED_TX ETH_MD2_P ETH_MD2_N A9 B8 C8 E8 C9 D9 ETH_MD1_P ETH_MD1_N N6 N7 ETH_MD0_P ETH_MD0_N 2_5V N3 N4 ETH_MD2_P TDI TDO TMS TCK TRST HSDAC HSDAC S_OUT S_OUT S_CLK S_CLK S_IN S_IN RSET RESET INT MDIO MDC LINK1000 LINK100 LINK10 DUPLEX RX_LED TX_LED MDIO_3 MDIO_3 MDIO_2 MDIO_2 MDIO_1 MDIO_1 N1 N2 Ferrite_bead BD0603 MDIO_0 MDIO_0 L3 DI All high speed signals use 50 ohm traces ETH_MD0_N MD0_BIAS C220 0_01uF CC0402 DI R233 49_9 CR0402 DI 88e1111 117TFBGA DI L4 H9 J9 K2 B5 B6 D8 E9 F8 G7 F9 G9 G8 H8 B1 D2 C1 B2 D3 C3 B3 C4 A1 A2 C5 E1 F2 D1 F1 G2 G3 H2 H1 H3 J1 J2 E2 U18 ETH_1_2V C6 C7 D7 E3 E7 F3 J3 J7 DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD B9 F7 J8 VDDOH VDDOH VDDOH B4 C2 K1 VDDO VDDO VDDO K9 L2 VDDOX VDDOX B7 M3 M4 M7 M8 N5 AVDD AVDD AVDD AVDD AVDD AVDD GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VSSC 4 22UF-16V-TANTBSMT 51 D4 D5 D6 E4 E5 E6 F4 F5 F6 G4 G5 G6 H4 H5 H6 J4 J5 J6 K4 K5 K6 L5 L6 H7 5 A B C D LatticeECP3 I/O Protocol Board – Revision C User’s Guide Figure 28. 1000Base-T PHY/RJ45 52 A B C D GND 3_3V 5 GND_POWER C104 0.1uF DI SM/C_0402 F7 F8 A8 T9 G6 H6 J6 K6 L7 L8 L9 L10 J11 K11 G11 H11 F9 F10 C118 0.1uF DI SM/C_0402 3_3V [5] Programming [6] USB Download MACHXO C91 0.1uF DI SM/C_0402 VCCAUX_0 VCCAUX_1 VCCIO7_0 VCCIO7_1 VCCIO6_0 VCCIO6_1 VCCIO5_0 VCCIO5_1 VCCIO4_0 VCCIO4_1 VCCIO3_0 VCCIO3_1 VCCIO2_0 VCCIO2_1 VCCIO1_0 VCCIO1_1 C99 0.1uF DI SM/C_0402 XO_640 common VCCIO VCCJ on VCCIO5 XO_640 common VCCIO XO_640 common VCCIO XO_640 common VCCIO C102 0.01uF DI SM/C_0402 VCC_3 VCC_2 VCC_1 VCC_0 GND_0 GND_1 GND_2 GND_3 GND_4 GND_5 GND_6 GND_7 GND_8 GND_9 GND_10 GND_11 GND_12 GND_13 GND_14 GND_15 GND_16 GND_17 XOBank0_[0..23] XOBank1_[0..27] XOBank01_[0..1] XOBank2_[0..25] XOBank3_[0..27] XOBank4_[0..27] XOBank5_[0..19] XOBank45_[0..1] XOBank6_[0..27] XOBank7_[0..25] XOJTAG[0..3] LCMXO2280C-4FTN256C FTBGA256 VCCIO0_0 VCCIO0_1 U5E DI XOBank0_[0..23] XOBank1_[0..27] XOBank01_[0..1] XOBank2_[0..25] XOBank3_[0..27] XOBank4_[0..27] XOBank5_[0..19] XOBank45_[0..1] XOBank6_[0..27] XOBank7_[0..25] XOJTAG[0..3] 3_3V 4 C97 0.01uF DI SM/C_0402 K7 G7 K10 G10 A16 T16 F11 H10 J10 G9 H9 J9 K9 G8 H8 J8 K8 H7 J7 L6 A1 T1 4 C89 0.01uF DI SM/C_0402 D6 D5 XOBank0_8 XOBank0_9 P5 P6 T5 T4 R6 T6 T8 T7 M7 M8 R7 R8 XOBank5_8 XOBank5_9 XOBank5_10 XOBank5_11 XOBank5_12 XOBank5_13 XOBank5_14 XOBank5_15 XOBank5_16 XOBank5_17 XOBank5_18 XOBank5_19 C98 0.01uF DI SM/C_0402 U5A DI C117 0.001uF DI SM/C_0402 XOBank45_0 XOBank45_1 I/Os in Bank 5 for XO1200 Pin name sequence PB(640,1200,2280) TDI TDO TMS TCK PB4E/PB6C/PB8C PB4F/PB6D/PB8D NC/PB6A/PB7C NC/PB6B/PB7D PB4C/PB5C/PB6A PB4D/PB5D/PB6B PB4A/PB5A/PB5A PB4B/PB5B/PB5B PB3C/PB4C/PB4C PB3D/PB4D/PB4D PB3A/PB4A/PB4A PB3B/PB4B/PB4B PB2C/PB3C/PB3C PB2D/PB3D/PB3D PB2A/PB3A/PB3A PB2B/PB3B/PB3B NC/PB2C/PB2C NC/PB2D/PB2D PT9A/PT7A/PT9C PT9B/PT7B/PT9D VCCIO1 PT7E/PT9E/PT14A PT7F/PT9F/PT14B PT8A/PT9C/PT13C PT8B/PT9D/PT13D PT7A/PT9A/PT12C PT7B/PT9B/PT12D PT7C/PT8E/PT12A PT7D/PT8F/PT12B PT5C/PT8C/PT11A PT5D/PT8D/PT11B PT8C/PT8A/PT10E PT8D/PT8B/PT10F PT6C/PT7E/PT10C PT6D/PT7F/PT10D 3 C122 0.001uF DI SM/C_0402 I/Os in Bank 4 for XO2280 NC/PB11C/PB16C NC/PB11D/PB16D SLEEPN PB9F/PB10F/PB15D NC/PB11A/PB16A NC/PB11B/PB16B PB9C/PB10C/PB15A PB9D/PB10D/PB15B PB9A/PB10A/PB14C PB9B/PB10B/PB14D PB8C/PB9E/PB14A PB8D/PB9F/PB14B PB8A/PB9C/PB13C PB8B/PB9D/PB13D PB7E/PB9A/PB13A PB7F/PB9B/PB13B NC/PB8E/PB12C NC/PB8F/PB12D PB7C/PB8C/PB12A PB7D/PB8D/PB12B PB6C/PB8A/PB11C PB6D/PB8B/PB11D PB6A/PB7E/PB10A PB6B/PB7F/PB10B/CLK3 PB7A/PB7C/PB10C PB7B/PB7D/PB10D PB5A/PB7A/PB10E PB5B/PB7B/PB10F/CLK2 VCCIO4 I/Os in Bank 1 for XO2280 NC/PT11C/PT16C NC/PT11D/PT16D NC/PT11A/PT16A NC/PT11B/PT16B PT9E/PT10E/PT15C PT9F/PT10F/PT15D NC/PT10C/PT15A NC/PT10D/PT15B PT9C/PT10A/PT14C PT9D/PT10B/PT14D LCMXO2280C-4FTN256C FTBGA256 NC/PB2A/PB2A NC/PB2B/PB2B VCCIO5 U5C DI XOBank01_0 XOBank01_1 I/Os in Bank 0 for XO1200 Pin name sequence PT(640,1200,2280) PT4E/PT6C/PT8C PT4F/PT6D/PT8D PT4C/PT6A/PT7C PT4D/PT6B/PT7D PT4A/PT5E/PT7A PT4B/PT5F/PT7B PT3C/PT5C/PT6A PT3D/PT5D/PT6B PT3E/PT5A/PT6C PT3F/PT5B/PT6D NC/PT4C/PT6E NC/PT4D/PT6F PT3A/PT3E/PT5C PT3B/PT3F/PT5D PT2C/PT3C/PT5A PT2D/PT3D/PT5B PT2E/PT4A/PT4A PT2F/PT4B/PT4B NC/PT2C/PT3C NC/PT2D/PT3D PT2A/PT3A/PT3A PT2B/PT3B/PT3B NC/PT2A/PT2C NC/PT2B/PT2D 3 PT6A/PT7C/PT10A PT6B/PT7D/PT10B/CLK1 LCMXO2280C-4FTN256C FTBGA256 VCCIO0 C114 0.001uF DI SM/C_0402 N7 M6 P4 R3 R4 R5 XOBank5_6 XOBank5_7 XOJTAG0 XOJTAG1 XOJTAG2 XOJTAG3 T2 T3 XOBank5_4 XOBank5_5 B8 C8 XOBank0_22 XOBank0_23 N5 N6 A6 A7 XOBank0_20 XOBank0_21 XOBank5_2 XOBank5_3 B6 B7 XOBank0_18 XOBank0_19 P2 P3 C6 C7 XOBank0_16 XOBank0_17 XOBank5_0 XOBank5_1 A5 A4 XOBank0_14 XOBank0_15 E7 E6 C4 C5 XOBank0_6 XOBank0_7 XOBank0_12 XOBank0_13 D3 D4 XOBank0_4 XOBank0_5 B4 B5 A2 A3 XOBank0_2 XOBank0_3 XOBank0_10 XOBank0_11 B2 B3 XOBank0_0 XOBank0_1 PT5A/PT6E/PT9A PT5B/PT6F/PT9B/CLK0 D8 D7 PB5C/PB6E/PB9A PB5D/PB6F/PB9B P7 P8 5 XOBank7_12 XOBank7_13 XOBank7_14 XOBank7_15 XOBank7_16 XOBank7_17 XOBank7_18 XOBank7_19 XOBank7_20 XOBank7_21 XOBank7_22 XOBank7_23 XOBank7_24 XOBank7_25 XOBank4_12 XOBank4_13 XOBank4_14 XOBank4_15 XOBank4_16 XOBank4_17 XOBank4_18 XOBank4_19 XOBank4_20 XOBank4_21 XOBank4_22 XOBank4_23 XOBank4_24 XOBank4_25 R11 R12 P11 P12 T13 T12 R13 R14 T14 T15 R15 R16 P13 P14 XOBank4_26 XOBank4_27 XOBank7_10 XOBank7_11 XOBank4_10 XOBank4_11 N10 N11 P15 P16 XOBank7_8 XOBank7_9 XOBank4_8 XOBank4_9 G1 H1 H4 H5 G3 H3 G4 G5 E1 F1 F2 G2 D2 D1 B1 C1 C3 C2 F5 F6 T10 T11 E4 E5 E3 E2 XOBank1_26 XOBank1_27 A15 B15 G15 H15 XOBank7_6 XOBank7_7 XOBank2_24 XOBank2_25 XOBank1_24 XOBank1_25 B14 C14 G14 H14 XOBank4_6 XOBank4_7 XOBank2_22 XOBank2_23 XOBank1_22 XOBank1_23 B13 C13 H12 H13 R9 R10 XOBank2_20 XOBank2_21 XOBank1_20 XOBank1_21 E10 E11 G12 G13 F3 F4 XOBank2_18 XOBank2_19 XOBank1_18 XOBank1_19 D11 D12 F16 G16 XOBank7_4 XOBank7_5 XOBank2_16 XOBank2_17 XOBank1_16 XOBank1_17 A13 A14 E15 F15 XOBank4_4 XOBank4_5 XOBank2_14 XOBank2_15 XOBank1_14 XOBank1_15 C11 C12 D16 E16 M10 M9 XOBank2_12 XOBank2_13 XOBank1_12 XOBank1_13 B11 B12 C15 D15 XOBank7_2 XOBank7_3 XOBank2_10 XOBank2_11 XOBank1_10 XOBank1_11 A11 A12 B16 C16 XOBank4_2 XOBank4_3 XOBank2_8 XOBank2_9 XOBank1_8 XOBank1_9 B9 B10 E14 F14 P9 P10 XOBank2_6 XOBank2_7 XOBank1_6 XOBank1_7 D9 D10 F13 F12 XOBank7_0 XOBank7_1 XOBank2_4 XOBank2_5 XOBank1_4 XOBank1_5 C9 C10 E13 E12 XOBank4_0 XOBank4_1 XOBank2_2 XOBank2_3 XOBank1_2 XOBank1_3 A10 A9 D14 D13 N8 N9 XOBank2_0 XOBank2_1 XOBank1_0 XOBank1_1 E8 E9 PR8A/PR10C/PR13C PR8B/PR10D/PR13D PR10C/PR12C/PR15C PR10D/PR12D/PR15D PR9C/PR12A/PR15A/LV_T PR9D/PR12B/PR15B/LV_C PR9A/PR11C/PR14C PR9B/PR11D/PR14D PR8C/PR11A/PR14A/LV_T PR8D/PR11B/PR14B/LV_C PL7C/PL9C/PL11C PL7D/PL9D/PL11D PL6A/PL9A/PL11A/LV_T PL6B/PL9B/PL11B/LV_C VCCIO6 NC/PR16A/PR20A NC/PR16B/PR20B NC/PR15A/PR18A/LV_T NC/PR15B/PR18B/LV_C NC/PR14C/PR17C NC/PR14D/PR17D PR11C/PR14A/PR17A/LV_T PR11D/PR14B/PR17B/LV_C PR11A/PR13C/PR16C PR11B/PR13D/PR16D PL11A/PL13C/PL16C PL11B/PL13D/PL16D PL8A/PL13A/PL16A/LV_T PL8B/PL13B/PL16B/LV_C PL9C/PL12C/PL15C PL9D/PL12D/PL15D PL10A/PL12A/PL15A/LV_T PL10B/PL12B/PL15B/LV_C TSALL/PL8C/PL11C/PL14C PL8D/PL11D/PL14D PL10C/PL14C/PL17C PL10D/PL14D/PL17D 2 Pin name sequence PL(640,1200,2280) PL11C/PL16A/PL19A PL11D/PL16B/PL19B PL5C/PL8C/PL10C NC/PL15A/PL18A/LV_T/PLL0_T_IN PL5D/PL8D/PL10DNC/PL15B/PL18B/LV_C/PLL0_C_IN NC/PL8A/PL9A/LV_T NC/PL8B/PL9B/LV_C PL4C/PL7C/PL8C NC/PL14A/PL17A/LV_T/PLL0_T_FB PL4D/PL7D/PL8D NC/PL14B/PL17B/LV_C/PLL0_C_FB NC/PL7A/PL8A/LV_T NC/PL7B/PL8B/LV_C PL4A/PL6C/PL7C PL4B/PL6D/PL7D PL9A/PL10C/PL12C PL9B/PL10D/PL12D PL7A/PL11A/PL13A/LV_T PL7B/PL11B/PL13B/LV_C PL5A/PL6A/PL7A/LV_T PL5B/PL6B/PL7B/GSR/LV_C PL3C/PL5C/PL6C PL3D/PL5D/PL6D PL2A/PL5A/PL5A/LV_T PL2B/PL5B/PL5B/LV_C NC/PL4C/PL4C NC/PL4D/PL4D PL2C/PL4A/PL4A/LV_T PL2D/PL4B/PL4B/LV_C PL3A/PL3C/PL3C/PLL1T_IN PL6C/PL10A/PL12A/LV_T PL3B/PL3D/PL3D/PLL1C_INPL6D/PL10B/PL12B/LV_C NC/PL3A/PL3A/LV_T NC/PL3B/PL3B/LV_C NC/PR9C/PR11C NC/PR9D/PR11D PR7C/PR10A/PR13A/LV_T PR7D/PR10B/PR13B/LV_C LCMXO2280C-4FTN256C FTBGA256 VCCIO7 VCCIO3 PR10A/PR13A/PR16A/LV_T PR10B/PR13B/PR16B/LV_C NC/PL2A/PL2A/PLL1T_FB NC/PL2B/PL2B/PLL1C_FB U5B DI Pin name sequence PR(640,1200,2280) PR6A/PR8C/PR10C PR6B/PR8D/PR10D PR5C/PR8A/PR10A/LV_T PR5D/PR8B/PR10B/LV_C PR6C/PR7C/PR9C PR6D/PR7D/PR9D PR4C/PR7A/PR9A/LV_T PR4D/PR7B/PR9B/LV_C PR5A/PR6C/PR7C PR5B/PR6D/PR7D PR4A/PR6A/PR7A/LV_T PR4B/PR6B/PR7B/LV_C PR3A/PR5C/PR6C PR3B/PR5D/PR6D PR2C/PR5A/PR6A/LV_T PR2D/PR5B/PR6B/LV_C PR2A/PR4C/PR5C PR2B/PR4D/PR5D PR3C/PR4A/PR5A/LV_T PR3D/PR4B/PR5B/LV_C NC/PR3C/PR4C NC/PR3D/PR4D NC/PR3A/PR4A/LV_T NC/PR3B/PR4B/LV_C NC/PR2A/PR3A/LV_T NC/PR2B/PR3B/LV_C PR7A/PR9A/PR11A/LV_T PR7B/PR9B/PR11B/LV_C LCMXO2280C-4FTN256C FTBGA256 VCCIO2 U5D DI 2 N4 N3 M5 M4 L5 L4 K5 K4 R1 R2 J4 J5 M2 N2 L3 M3 N1 P1 L1 M1 K2 L2 J1 K1 J3 K3 H2 J2 L11 M11 N13 N12 M12 M13 N15 N14 L12 L13 L14 M14 M16 N16 L15 M15 K16 L16 J13 K13 J14 K14 J15 K15 J12 K12 H16 J16 Date: Size C Title XOBank6_26 XOBank6_27 XOBank6_24 XOBank6_25 XOBank6_22 XOBank6_23 XOBank6_20 XOBank6_21 XOBank6_18 XOBank6_19 XOBank6_16 XOBank6_17 XOBank6_14 XOBank6_15 XOBank6_12 XOBank6_13 XOBank6_10 XOBank6_11 XOBank6_8 XOBank6_9 XOBank6_6 XOBank6_7 XOBank6_4 XOBank6_5 XOBank6_2 XOBank6_3 XOBank6_0 XOBank6_1 XOBank3_26 XOBank3_27 XOBank3_24 XOBank3_25 XOBank3_22 XOBank3_23 XOBank3_20 XOBank3_21 XOBank3_18 XOBank3_19 XOBank3_16 XOBank3_17 XOBank3_14 XOBank3_15 XOBank3_12 XOBank3_13 XOBank3_10 XOBank3_11 XOBank3_8 XOBank3_9 XOBank3_6 XOBank3_7 XOBank3_4 XOBank3_5 XOBank3_2 XOBank3_3 XOBank3_0 XOBank3_1 Friday, June 11, 2010 1 Sheet 10 of 18 ECP3 IO Protocol Eval Board Schematic Project MACHXO C Rev Lattice Semiconductor Corporation 5555 N.E. Moore Court Hillsboro, Oregon. 97124 1 A B C D LatticeECP3 I/O Protocol Board – Revision C User’s Guide Figure 29. MachXO A B C SP10 SP5 [13] [13] C42 0805 C41 SP2 SP12 SP9 5 SP6 SP1 SP7 SP11 C96 C108 C109 SP3 PP2 C129 SP8 SP4 C116 2 F1 1 4 5_0V 0.76v C63 C62 C61 DDR3_REG_EN 20 19 18 17 16 15 14 13 12 11 C50 C51 C54 C58 CS_1.5 PGOOD DDR3_VDD DDR3_VDD 5_0V 4 4 SOURCE 4 3 2 1 C57 C66 C60 C55 3 C49 DIMM 2 C64 C48 C59 5_0V 10uF Ceramic X5R 0805 C262 2 2 ECP3_REF [13] [2] 2 3 6 7 8 OUT 1 C88 C87 C111 Date: Size B Title C5 C83 C79 C81 C113 C78 C100 Thursday, August 20, 2009 1 Sheet 11 of 18 ECP3 IO Protocol Eval Board Schematic C Rev Lattice Semiconductor Corporation 5555 N.E. Moore Court Hillsboro, Oregon. 97124 J19 HEADER 2 DIMM2_REF [13] C103 C77 C7 499R-0603SMT DDR3_VREF R14 DDR3 Voltage Regulator Project 0603 C43 +5.0V 5_0V 4.7uF Ceramic X5R 8 7 6 5 1K_ADJ/SMT3MM R12 R103 1_21K-0603SMT DDR3_VDD C86 C142 D4 D3 D2 D1 1 NTMS4503 SO8 Q26 DI S1 S2 S3 G DNI-0603SMT C263 1 2 3 4 J61 HEADER 2 HD2x1 DI DIMM1_REF [13] C120 C93 C80 J15 HEADER 2 499R-0603SMT DDR3_VREF R9 1K_ADJ/SMT3MM R7 R96 1_21K-0603SMT DDR3_VDD BANK 7 DDR3_VDD BANK 6 DDR3_VDD BANK 0 DDR3_VDD 5_0V_GATE 100R-0603SMT R303 C256 5_0V_FET 78L05/SO COM COM COM COM IN U2 [3] 5_0V_FET 12_0V J16 HEADER 2 499R-0603SMT DDR3_VREF R97 1K_ADJ/SMT3MM R8 R10 1_21K-0603SMT DDR3_VDD C38 150uF Panasonic SP-CAP EEF-HE0J151R 1 2 SizeD C44 150uF Panasonic SP-CAP EEF-HE0J151R 1 2 SizeD 5_0V Q1 IRF7832 SO-8 N-Channel MOSFET PP4 DIMM 1 100K 10K R4 5.1K L1 N-Channel MOSFET C46 PWR_1.5V 1 2 1.0uH Vishay IHLP-5050FD-ER-1R0-M-01 3 2 1 Q24 IRF7821 SO-8 10uF Ceramic X5R 0805 DRAIN 8 7 6 5 SOURCE R3 R2 GATE_1.5L LL_1.5 GATE_1.5H 3 DRAIN 8 7 6 5 C47 Each DIMM VTT connection can require +/-600 mA DIMM 2 DIMM 1 C67 100NF-0603SMT C275 VBST DRVH LL DRVL PGND CS V5IN PGOOD S5 S3 0402 0.1uF [3] TPS51116PWP VLDOIN VTT VTTGND VTTSNS GND MODE VTTREF COMP VDDQSSNS VDDQSET R1 100K-0603SMT 1 2 3 4 5 6 7 8 9 10 U1 VBST C45 10A FUSE Littelfuse 154010 383milX198mil R305 270R-0603SMT R88 75K R87 75K DDR3_VDD_TRIM [3] PP3 10uF Ceramic X5R 0805 C39 DDR3_VTT C110 ECP3 PP1 10uF Ceramic X5R 0.033uF Ceramic 0402 C40 0.1uF 0402 DDR3_VREF C53 220uF SizeD DDR3_VTT C52 220uF SizeD DDR3_VDD [13] Set PAC device to +0.8v offset for +/- 5% trim range about the nominal regulator output voltage +/-10mA +0.75v +/-3A +0.75v 10A 1 D 1 1 1 2 1 2 1 2 1 2 1 2 1 1 1NF-0402SMT 1 10NF-0603SMT +1.5v 100NF-0603SMT 1 2 5 100NF-0603SMT 100NF-0603SMT 1NF-0402SMT 1NF-0402SMT 1NF-0402SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 1NF-0402SMT 1NF-0402SMT 1NF-0402SMT 2 1 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 2 1NF-0402SMT 1 1 10NF-0603SMT 10NF-0603SMT 100NF-0603SMT 100NF-0603SMT 10NF-0603SMT 10NF-0603SMT 100NF-0603SMT 100NF-0603SMT 10NF-0603SMT 1 1 10NF-0603SMT 10NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 1 1 10NF-0603SMT 10NF-0603SMT 2 1 1 100NF-0603SMT 100NF-0603SMT ECP3_REF 2 1 53 DIMM1_REF 2 1 DIMM2_REF 2 1 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT DDR3 Voltage Regulator A B C D LatticeECP3 I/O Protocol Board – Revision C User’s Guide Figure 30. DDR3 Voltage Regulator A B C GND_H1 GND_H2 GND_H3 GND_H4 GND_H5 GND_H6 GND_H7 GND_H8 GND_H9 GND_H10 GND_F1 GND_F2 GND_F3 GND_F4 GND_F5 GND_F6 GND_F7 GND_F8 GND_F9 GND_F10 GND_D1 GND_D2 GND_D3 GND_D4 GND_D5 GND_D6 GND_D7 GND_D8 GND_D9 GND_D10 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 SPI4_TDAT_N4 SPI4_TDCLK_N SPI4_TDAT_N9 SPI4_TDAT_N10 SPI4_TDAT_N12 SPI4_RSCLK_NC1 SPI4_RDAT_N10 SPI4_RDAT_N6 SPI4_RDAT_N7 SPI4_RDAT_N2 SPI4_TDAT_P0 SPI4_TDAT_P2 SPI4_TDAT_P7 SPI4_TDAT_P14 SPI4_TDAT_P13 SPI4_RCTL_P SPI4_RDAT_P11 SPI4_RDAT_P14 SPI4_RSTAT1 SPI4_RDAT_P1 SPI4_TDAT_N0 SPI4_TDAT_N2 SPI4_TDAT_N7 SPI4_TDAT_N14 SPI4_TDAT_N13 SPI4_RCTL_N SPI4_RDAT_N11 SPI4_RDAT_N14 SPI4_RSTAT0 SPI4_RDAT_N1 SPI4_TDAT_P3 SPI4_TDAT_P5 SPI4_TDAT_P6 SPI4_TDAT_P8 SPI4_TCTL_P SPI4_RDAT_P13 SPI4_RDAT_P12 SPI4_RDAT_P4 SPI4_RDAT_P9 SPI4_RDAT_P3 SPI4_TDAT_N3 SPI4_TDAT_N5 SPI4_TDAT_N6 SPI4_TDAT_N8 SPI4_TCTL_N SPI4_RDAT_N13 SPI4_RDAT_N12 SPI4_RDAT_N4 SPI4_RDAT_N9 SPI4_RDAT_N3 SPI4_TSTAT1 SPI4_TDAT_P1 SPI4_TSCLK SPI4_TDAT_P11 SPI4_TDAT_P15 SPI4_RDAT_P15 SPI4_RDAT_P8 SPI4_RDCLK_P SPI4_RDAT_P0 SPI4_RDAT_P5 SPI4_TSTAT0 SPI4_TDAT_N1 SPI4_TSCLK_NC2 SPI4_TDAT_N11 SPI4_TDAT_N15 SPI4_RDAT_N15 SPI4_RDAT_N8 SPI4_RDCLK_N SPI4_RDAT_N0 SPI4_RDAT_N5 RDAT_N4 RDCLK_N RDAT_N9 RDAT_N10 RDAT_N12 NC1 TDAT_N10 TDAT_N6 TDAT_N7 TDAT_N2 RDAT_P0 RDAT_P2 RDAT_P7 RDAT_P14 RDAT_P13 TCTL_P TDAT_P11 TDAT_P14 TSTAT1 TDAT_P1 RDAT_N0 RDAT_N2 RDAT_N7 RDAT_N14 RDAT_N13 TCTL_N TDAT_N11 TDAT_N14 TSTAT0 TDAT_N1 RDAT_P3 RDAT_P5 RDAT_P6 RDAT_P8 RCTL_P TDAT_P13 TDAT_P12 TDAT_P4 TDAT_P9 TDAT_P3 RDAT_N3 RDAT_N5 RDAT_N6 RDAT_N8 RCTL_N TDAT_N13 TDAT_N12 TDAT_N4 TDAT_N9 TDAT_N3 RSTAT1 RDAT_P1 RSCLK RDAT_P11 RDAT_P15 TDAT_P15 TDAT_P8 TDCLK_P TDAT_P0 TDAT_P5 RSTAT0 RDAT_N1 NC2 RDAT_N11 RDAT_N15 TDAT_N15 TDAT_N8 TDCLK_N TDAT_N0 TDAT_N5 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 ECP3 Symbol Pins: * True LVDS Output ^ DQS Density shown as -95/-150 5 J58 (HMZD) (Receptacle version is TYCO HMZD 6-469001-1) TYCO HMZD 6-469048-1 Header HG1 HG2 HG3 HG4 HG5 HG6 HG7 HG8 HG9 HG10 FG1 FG2 FG3 FG4 FG5 FG6 FG7 FG8 FG9 FG10 DG1 DG2 DG3 DG4 DG5 DG6 DG7 DG8 DG9 DG10 GND_B1 GND_B2 GND_B3 GND_B4 GND_B5 GND_B6 GND_B7 GND_B8 GND_B9 GND_B10 C165 C176 C188 ECP3-150EA-7FN1156C BANK 3 C201 4 C189 2_5V AB23 AB24 V23 V24 W25 W24 C198 VCCIO3/VCCIO3 VCCIO3/VCCIO3 VCCIO3/VCCIO3 VCCIO3/VCCIO3 VTT3/VTT3 VTT3/VTT3 2_5V SPI4_VTT TEST2 TEST3 TEST4 TEST5 TEST12 TEST13 PHY_MDIO PCSB_CLK_SEL PHY_MDC PHY_RESET_N CLK_SEL TEST14 PHY_INT_N SPI4_TCTL_P SPI4_TCTL_N SPI4_TDAT_P14 SPI4_TDAT_N14 SPI4_TDAT_P15 SPI4_TDAT_N15 SPI4_TDAT_P13 SPI4_TDAT_N13 SPI4_TDAT_P11 SPI4_TDAT_N11 SPI4_TDAT_P12 SPI4_TDAT_N12 SPI4_VTT SPI4_TDAT_P10 SPI4_TDAT_N10 PB1 PB2 SPI4_VTT SPI4_TDAT_P8 SPI4_TDAT_N8 SPI4_TDAT_P9 SPI4_TDAT_N9 SPI4_VTT SPI4_TDCLK_P SPI4_TDCLK_N SPI4_VTT SPI4_TDAT_P5 SPI4_TDAT_N5 TP132 TP131 SPI4_TDAT_P6 SPI4_TDAT_N6 SPI4_TDAT_P7 SPI4_TDAT_N7 SPI4_TDAT_P3 SPI4_TDAT_N3 SPI4_TDAT_P4 SPI4_TDAT_N4 SPI4_TDAT_P2 SPI4_TDAT_N2 CLK_FBP CLK_FBN CLK_P CLK_N SPI4_TDAT_P0 SPI4_TDAT_N0 SPI4_TDAT_P1 SPI4_TDAT_N1 R320 R319 R324 R323 R322 R321 R328 R327 R329 R330 SPI4_RDAT_P15 SPI4_RDAT_N15 SPI4_RCTL_P SPI4_RCTL_N TP53 TP118 TP49 TP50 TP51 TP52 TP119 TP120 TP124 TP123 R325 33R-0603SMT 2 3 4 5 33R-0603SMT 33R-0603SMT 33R-0603SMT 33R-0603SMT 33R-0603SMT 33R-0603SMT 33R-0603SMT 33R-0603SMT 33R-0603SMT 33R-0603SMT SMA J68 1 Y32 CLK_P CLK_N CLK_FBN CLK_FBP 3 2 3 4 5 2 3 4 5 C167 CLK_P [8] CLK_N [8] SMA 1 SMA J42 1 J50 BANK 2 C190 2_5V VDDQ LP2996-SO8 5 2_5V VTT 8 3 2_5V C23 C203 C177 VREF VSENSE SD U10 C197 R161 2 4_7K-0603SMT 4 2_5V CLK Feed Back C161 VCCIO2/VCCIO2 VCCIO2/VCCIO2 VCCIO2/VCCIO2 VCCIO2/VCCIO2 VTT2/VTT2 VTT2/VTT2 NC/PR17A NC/PR17B NC/PR19A* NC/PR19B* NC/PR20A* NC/PR20B* NC/PR22A^ NC/PR22B NC/PR23A NC/PR23B NC/PR25A* NC/PR25B* NC/PR26A NC/PR26B NC/PR28A* NC/PR28B* NC/PR29A* NC/PR29B* NC/PR32A NC/PR32B NC/PR34A* NC/PR34B* PR17A/PR35A PR17B/PR35B PR19A*/PR37A* PR19B*/PR37B* PR20A/PR38A* PR20B/PR38B* PR22A^/PR40A^ PR22B/PR40B PR23A/PR41A PR23B/PR41B PR25A*/PR43A* PR25B*/PR43B* PR25E_A/PR43E_A/RUM2_GPLLT_FB_A PR25E_B/PR43E_B/RUM2_GPLLT_FB_B PR25E_C/PR43E_C/RUM2_GPLLT_IN_A PR25E_D/PR43E_D/RUM2_GPLLT_IN_B PR26A/PR44A PR26B/PR44B PR28A*/PR46A* PR28B*/PR46B* PR29A/PR47A* PR29B/PR47B* PR31A^/PR49A^ PR31B/PR49B PR32A/PR50A PR32B/PR50B PR34A*/PR52A*/VREF1_2 PR34B*/PR52B*/VREF2_2 PR35A/PR53A PR35B/PR53B PR37A*/PR55A*/RUM0_GDLLT_IN_A PR37B*/PR55B*/RUM0_GDLLT_IN_B PR38A/PR56A*/RUM0_GDLLT_FB_A PR38B/PR56B*/RUM0_GDLLT_FB_B PR40A^/PR58A^ PR40B/PR58B PR41A/PR59A PR41B/PR59B PR43A*/PR61A*/PCLKT2_0 PR43B*/PR61B*/PCLKC2_0 PR43E_A/PR61E_A/RUM0_GPLLT_FB_A PR43E_B/PR61E_B/RUM0_GPLLT_FB_B PR43E_C/PR61E_C/RUM0_GPLLT_IN_A PR43E_D/PR61E_D/RUM0_GPLLT_IN_B ECP3-150EA-7FN1156C U7C All 33 ohm resistors on this page are near the ECP3 All high speed signals use 50 ohm traces 2_5V 2_5V PHY_INT_N [9] 2_5V PHY_MDIO[9] PCSB_CLK_SEL[7] PHY_MDC [9] PHY_RESET_N [9] CLK_SEL [8] 2_5V 2_5V PB1 [5] PB2 [5] 2_5V 2_5V 2_5V 2_5V 2_5V 2_5V 2_5V 1NF-0402SMT SPI4_RDAT_P12 SPI4_RDAT_N12 SPI4_RDAT_P13 SPI4_RDAT_N13 SPI4_RDAT_P14 SPI4_RDAT_N14 1NF-0402SMT out | in 10NF-0603SMT BG1 BG2 BG3 BG4 BG5 BG6 BG7 BG8 BG9 BG10 SPI4_TDAT_P4 SPI4_TDCLK_P SPI4_TDAT_P9 SPI4_TDAT_P10 SPI4_TDAT_P12 SPI4_RSCLK SPI4_RDAT_P10 SPI4_RDAT_P6 SPI4_RDAT_P7 SPI4_RDAT_P2 RDAT_P4 RDCLK_P RDAT_P9 RDAT_P10 RDAT_P12 TSCLK TDAT_P10 TDAT_P6 TDAT_P7 TDAT_P2 V31 V30 U28 V28 W34 W33 V27 V26 W32 W31 V29 W28 W30 W29 W27 W26 Y34 Y33 Y30 AA29 Y32 Y31 Y26 Y25 AA34 AA33 Y28 Y27 AB34 AB33 AA25 AA26 AA31 AA30 AB30 AC30 AC34 AC33 AA28 AA27 AB32 AB31 AD31 AD30 AE34 AE33 AB26 AB25 AF34 AG34 AD33 AD34 AC32 AC31 AB28 AB29 AE32 AE31 AC28 AB27 AE30 AE29 AC25 AC26 AF32 AF31 AD26 AD25 AM34 AM33 AJ34 AK34 AN34 AN33 AH33 AJ33 AP33 AP32 AL34 AL33 AL32 AK32 AJ31 AK31 AN32 AM32 AL30 AM30 AP31 AN31 AP29 AP30 AL31 AM31 AM29 AN29 AP28 AN28 AP27 AN27 AM27 AL27 AH26 AG26 AM28 AL28 AK27 AJ27 AK28 AJ28 AH27 AH28 AL29 AK29 AF26 AE26 10NF-0603SMT A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 1NF-0402SMT 100NF-0603SMT A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 10NF-0603SMT + C29 C25 2 + PP8 SPI4_VTT 2_5V SPI4_VTT SPI4_VTT 2 HEADER 3 2_5V 2_5V 2_5V 2_5V 2_5V J31 + C183 C20 C168 SPI4_VTT C163 C191 C192 C193 SPI4_RDAT_P5 SPI4_RDAT_N5 SPI4_RDAT_P6 SPI4_RDAT_N6 SPI4_RDAT_P7 SPI4_RDAT_N7 TEST6 TEST7 SPI4_RDAT_P8 SPI4_RDAT_N8 SPI4_RDAT_P9 SPI4_RDAT_N9 SPI4_RDAT_P10 SPI4_RDAT_N10 SPI4_RDCLK_P SPI4_RDCLK_N TEST8 TEST9 TEST10 TEST11 SPI4_RDAT_P11 SPI4_RDAT_N11 SPI4_TSCLK SPI4_TSCLK_NC2 SPI4_TSTAT0 SPI4_TSTAT1 SPI4_VTT SPI4_RSCLK SPI4_RSCLK_NC1 SPI4_RSTAT0 SPI4_RSTAT1 SPI4_RDAT_P0 SPI4_RDAT_N0 SPI4_RDAT_P1 SPI4_RDAT_N1 SPI4_RDAT_P2 SPI4_RDAT_N2 TEST0 TEST1 SPI4_RDAT_P3 SPI4_RDAT_N3 SPI4_RDAT_P4 SPI4_RDAT_N4 LVDS_EM_P2 LVDS_EM_N2 LVDS_EM_P3 LVDS_EM_N3 LVDS_EM_P0 LVDS_EM_N0 LVDS_EM_P1 LVDS_EM_N1 out | in 2_5V N23 N24 U23 U24 T24 T25 K34 K33 L26 M25 L32 L31 M26 M27 L34 L33 K29 K30 M31 M30 L28 M28 M34 M33 K31 K32 M29 L30 N30 N29 N26 P26 N32 N31 N27 N28 N34 N33 P28 P27 P32 P31 P30 R29 P34 P33 R28 R27 R31 R30 R26 R25 R34 R33 T29 T28 T32 T31 T26 T27 T34 T33 T30 U30 U32 U31 U26 U27 U34 U33 V34 V33 1 2 J58 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT D 10NF-0603SMT PR44A/PR62A PR44B/PR62B PR46A*/PR64A*/PCLKT3_0 PR46B*/PR64B*/PCLKC3_0 PR47A/PR65A* PR47B/PR65B* PR49A^/PR67A^ PR49B/PR67B PR50A/PR68A PR50B/PR68B PR52A*/PR70A*/VREF1_3 PR52B*/PR70B*/VREF2_3 PR53A/PR71A PR53B/PR71B PR55A*/PR73A* PR55B*/PR73B* PR56A/PR74A* PR56B/PR74B* PR58A^/PR76A^ PR58B/PR76B PR59A/PR77A PR59B/PR77B PR61A*/PR79A* PR61B*/PR79B* PR61E_A/PR79E_A/RLM1_GPLLT_FB_A PR61E_B/PR79E_B/RLM1_GPLLT_FB_B PR61E_C/PR79E_C/RLM1_GPLLT_IN_A PR61E_D/PR79E_D/RLM1_GPLLT_IN_B PR62A/PR80A PR62B/PR80B PR64A*/PR82A* PR64B*/PR82B* PR65A/PR83A* PR65B/PR83B* PR67A^/PR85A^ PR67B/PR85B PR68A/PR86A PR68B/PR86B PR70A*/PR88A* PR70B*/PR88B* NC/PR89A NC/PR89B NC/PR91A* NC/PR91B* NC/PR92A* NC/PR92B* NC/PR94A^ NC/PR94B NC/PR95A NC/PR95B NC/PR97A* NC/PR97B* PR70E_A/PR97E_A/RLM3_GPLLT_FB_A PR70E_B/PR97E_B/RLM3_GPLLT_FB_B PR70E_C/PR97E_C/RLM3_GPLLT_IN_A PR70E_D/PR97E_D/RLM3_GPLLT_IN_B PR71A/PR98A PR71B/PR98B NC/PR100A* NC/PR100B* PR74A/PR101A* PR74B/PR101B* NC/PR103A^ NC/PR103B PR77A/PR104A PR77B/PR104B NC/PR106A* NC/PR106B* PR79E_A/PR106E_A/RLM4_GPLLT_FB_A PR79E_B/PR106E_B/RLM4_GPLLT_FB_B PR79E_C/PR106E_C/RLM4_GPLLT_IN_A PR79E_D/PR106E_D/RLM4_GPLLT_IN_B PR80A/PR107A PR80B/PR107B PR82A*/PR109A* PR82B*/PR109B* PR83A/PR110A* PR83B/PR110B* PR85A^/PR112A^ PR85B/PR112B PR86A/PR113A PR86B/PR113B PR88A*/PR115A* PR88B*/PR115B* PR89A/PR116A PR89B/PR116B PR91A*/PR118A* PR91B*/PR118B* PR92A/PR119A* PR92B/PR119B* PR94A^/PR121A^ PR94B/PR121B PR95A/PR122A PR95B/PR122B PR97A*/PR124A* PR97B*/PR124B* PB131A/PB167A PB131B/PB167B PB133A/PB169A PB133B/PB169B PB134A/PB170A PB134B/PB170B PB136A/PB172A PB136B/PB172B PB137A/PB173A PB137B/PB173B PB139A/PB175A PB139B/PB175B PB140A/PB176A PB140B/PB176B PB142A/PB178A PB142B/PB178B PB143A/PB179A PB143B/PB179B PB145A/PB181A PB145B/PB181B 100NF-0603SMT U7D 47UF-10V-TANTBSMT SPI4.2 1NF-0402SMT 6 7 AVIN PVIN GND 1 3 100UF-FKSMT 1NF-0603SMT 10UF-16V-TANTBSMT 4 1 2 3 C196 C186 C195 10NF-0603SMT 100NF-0603SMT 1NF-0603SMT 1UF-16V-0805SMT 100NF-0603SMT 1UF-16V-0805SMT 54 10NF-0603SMT 100NF-0603SMT 5 150R-0603SMT R41 R46 140R-0603SMT R40 150R-0603SMT 150R-0603SMT R309 R65 140R-0603SMT R308 150R-0603SMT 150R-0603SMT R335 R333 140R-0603SMT R334 150R-0603SMT 150R-0603SMT R332 R326 140R-0603SMT R331 150R-0603SMT 301 261 210 178 150 124 118 121 127 133 140 150 Date: Size C Title TEST0 TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 TEST8 TEST9 TEST10 TEST11 TEST12 TEST13 TEST14 SPI4_VTT 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 100NF-0603SMT C251 2_5V Friday, June 11, 2010 1 Sheet 12 of 18 C Rev Lattice Semiconductor Corporation 5555 N.E. Moore Court Hillsboro, Oregon. 97124 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 N(K30) P(K29) N(L33) P(L34) N(L31) P(L32) N(M25) P(L26) ECP3 IO Protocol Eval Board Schematic Project 2_5V 33R-0603SMT SPI4.2 R158 R39 R310 R311 R312 R313 R159 R42 R314 R315 R43 R160 R316 R317 R318 2 3 4 5 2 3 4 5 2 3 4 5 2 3 4 5 2 3 4 5 2 3 4 5 2 3 4 5 2 3 4 5 J55 HEADER 17X2 Term R Diff mv is the value measured DC across 100 ohm end term Series R 191 217 266 310 357 417 Emulated LVDS Values: Diff mv SMA J48 LVDS_N3 1 SMA J47 LVDS_P3 1 SMA J67 LVDS_N2 1 SMA J66 LVDS_P2 1 SMA J70 LVDS_N1 1 SMA J69 LVDS_P1 1 SMA J72 LVDS_N0 1 SMA J71 LVDS_P0 1 Place resistors near ECP3 LVDS_EM_N3 LVDS_EM_P3 LVDS_EM_N2 LVDS_EM_P2 LVDS_EM_N1 LVDS_EM_P1 LVDS_EM_N0 LVDS_EM_P0 1 A B C D LatticeECP3 I/O Protocol Board – Revision C User’s Guide Figure 31. SPI4.2 A L13 L17 M13 M17 DDR3_VDD ECP3 Symbol Pins: * True LVDS Output ^ DQS Density shown as -95/-150 5 C264 C266 C269 C273 DDR3_VTT C274 DDR3 clock, address and control signals ECP3-150EA-7FN1156C BANK 0 VCCIO0/VCCIO0 VCCIO0/VCCIO0 VCCIO0/VCCIO0 VCCIO0/VCCIO0 1NF-0402SMT LED[0..7] C265 1 2 3 4 1 2 3 4 1 2 3 4 33 DDR3_VDD TP67 TP68 DDR3_VDD DDR3_VDD DDR3_VDD DDR3_VDD DDR3_VDD DDR3_VDD DDR3_VDD DDR3_VDD TP66 8 7 6 5 8 7 6 5 8 7 6 5 R307 33R-0603SMT 1 J63 RN62 741X083 RN59 741X083 TP18 TP20 TP27 TP56 TP57 TP58 TP59 TP60 TP61 TP62 TP63 TP65 2 3 4 5 C8 [15] SMA SWITCH[0..7] [15] [15] SEVEN_SEG[0..7] TP64 DDR3_VDD 1NF-0402SMT B DDR3_A14 DDR3_A15 DDR3_A10 DDR3_A11 DDR3_A12 DDR3_A13 DDR3_A6 DDR3_A7 DDR3_A8 DDR3_A9 DDR3_A0 DDR3_A1 DDR3_A2 DDR3_A3 DDR3_A4 DDR3_A5 DDR3_BA2 DDR3_1_ODT0 DDR3_1_ODT1 DDR3_2_ODT1 DDR3_2_ODT0 DDR3_1_CKE0 DDR3_1_CKE1 DDR3_2_CKE0 DDR3_2_CKE1 DDR3_BA1 DDR3_BA0 DDR3_2_S1N DDR3_2_S0N DDR3_1_S0N DDR3_1_S1N DDR3_RESETN DDR3_CASN DDR3_RASN DDR3_WEN LED0 LED1 LED2 LED3 LED4 LED5 LED6 LED7 SEVEN_SEG0 SEVEN_SEG1 SEVEN_SEG2 SEVEN_SEG3 SEVEN_SEG4 SEVEN_SEG5 SEVEN_SEG6 SEVEN_SEG7 SWITCH0 SWITCH1 SWITCH2 SWITCH3 SWITCH4 SWITCH5 SWITCH6 SWITCH7 10NF-0603SMT C C3 C4 D3 C2 B1 B2 E4 D4 B3 A2 D5 C6 B4 A3 D6 C5 A4 A5 B7 A7 B6 A6 A8 A9 B8 C8 K11 J11 D9 C9 H11 H12 A10 B10 J12 K12 C11 D11 G11 G12 A11 B11 K13 J13 E11 F12 F10 E10 A12 B12 J14 H13 D12 E12 K14 K15 E13 F13 G13 H14 A13 B13 D10 C10 C13 D13 J15 H15 C14 D14 A14 B14 G16 G17 D15 E15 J16 H16 A15 B15 E17 F18 C16 D16 K16 L16 A16 B16 G18 F19 C17 D17 J17 H17 10NF-0603SMT 100NF-0603SMT D PT2A/PT2A PT2B/PT2B PT4A/PT4A/VREF1_0 PT4B/PT4B/VREF2_0 PT5A/PT5A PT5B/PT5B PT7A^/PT7A^ PT7B/PT7B PT8A/PT8A PT8B/PT8B PT10A/PT10A PT10B/PT10B PT11A/PT11A PT11B/PT11B PT13A/PT13A PT13B/PT13B PT14A/PT14A PT14B/PT14B PT16A^/PT16A^ PT16B/PT16B PT17A/PT17A PT17B/PT17B PT19A/PT19A PT19B/PT19B NC/PT20A NC/PT20B NC/PT22A NC/PT22B NC/PT26A NC/PT26B NC/PT28A NC/PT28B PT20A/PT38A PT20B/PT38B PT22A/PT40A PT22B/PT40B PT23A/PT41A PT23B/PT41B PT25A^/PT43A^ PT25B/PT43B PT26A/PT44A PT26B/PT44B PT28A/PT46A PT28B/PT46B PT29A/PT47A PT29B/PT47B PT31A/PT49A PT31B/PT49B PT32A/PT50A PT32B/PT50B PT34A^/PT52A^ PT34B/PT52B PT35A/PT53A PT35B/PT53B PT37A/PT55A PT37B/PT55B PT38A/PT56A PT38B/PT56B PT40A/PT58A PT40B/PT58B PT41A/PT59A PT41B/PT59B PT43A^/PT61A^ PT43B/PT61B PT44A/PT62A PT44B/PT62B PT46A/PT64A PT46B/PT64B PT50A/PT68A PT50B/PT68B PT56A/PT74A PT56B/PT74B PT58A/PT76A PT58B/PT76B PT59A/PT77A PT59B/PT77B PT61A^/PT79A^ PT61B/PT79B PT62A/PT80A PT62B/PT80B PT64A/PT82A PT64B/PT82B PT65A/PT83A PT65B/PT83B PT67A/PT85A PT67B/PT85B PT68A/PT86A PT68B/PT86B PT70A^/PT88A^ PT70B/PT88B PT71A/PT89A PT71B/PT89B PT73A/PT91A/PCLKT0_0 PT73B/PT91B/PCLKC0_0 U7A 100NF-0603SMT ECP3-150EA-7FN1156C BANK 6 VCCIO6/VCCIO6 VCCIO6/VCCIO6 VCCIO6/VCCIO6 VCCIO6/VCCIO6 VTT6/VTT6 VTT6/VTT6 PB2A/PB2A PB2B/PB2B PB4A/PB4A PB4B/PB4B PB5A/PB5A PB5B/PB5B PB7A/PB7A PB7B/PB7B PB8A/PB8A PB8B/PB8B PB10A/PB10A PB10B/PB10B PB11A/PB11A PB11B/PB11B PB13A/PB13A PB13B/PB13B PB14A/PB14A PB14B/PB14B PB16A/PB16A PB16B/PB16B PL44A/PL62A PL44B/PL62B PL46A*/PL64A*/PCLKT6_0 PL46B*/PL64B*/PCLKC6_0 PL47A/PL65A* PL47B/PL65B* PL49A^/PL67A^ PL49B/PL67B PL50A/PL68A PL50B/PL68B PL52A*/PL70A*/VREF1_6 PL52B*/PL70B*/VREF2_6 PL53A/PL71A PL53B/PL71B PL55A*/PL73A* PL55B*/PL73B* PL56A/PL74A* PL56B/PL74B* PL58A^/PL76A^ PL58B/PL76B PL59A/PL77A PL59B/PL77B PL61A*/PL79A* PL61B*/PL79B* PL61E_A/PL79E_A/LLM1_GPLLT_FB_A PL61E_B/PL79E_B/LLM1_GPLLT_FB_B PL61E_C/PL79E_C/LLM1_GPLLT_IN_A PL61E_D/PL79E_D/LLM1_GPLLT_IN_B PL62A/PL80A PL62B/PL80B PL64A*/PL82A* PL64B*/PL82B* PL65A/PL83A* PL65B/PL83B* PL67A^/PL85A^ PL67B/PL85B PL68A/PL86A PL68B/PL86B PL70A*/PL88A* PL70B*/PL88B* NC/PL89A NC/PL89B NC/PL91A* NC/PL91B* NC/PL92A* NC/PL92B* NC/PL94A^ NC/PL94B NC/PL95A NC/PL95B NC/PL97A* NC/PL97B* PL70E_A/PL97E_A/LLM3_GPLLT_FB_A PL70E_B/PL97E_B/LLM3_GPLLT_FB_B PL70E_C/PL97E_C/LLM3_GPLLT_IN_A PL70E_D/PL97E_D/LLM3_GPLLT_IN_B PL71A/PL98A PL71B/PL98B NC/PL100A* NC/PL100B* PL74A/PL101A* PL74B/PL101B* NC/PL103A^ NC/PL103B PL77A/PL104A PL77B/PL104B NC/PL106A* NC/PL106B* PL79E_A/PL106E_A/LLM4_GPLLT_FB_A PL79E_B/PL106E_B/LLM4_GPLLT_FB_B PL79E_C/PL106E_C/LLM4_GPLLT_IN_A PL79E_D/PL106E_D/LLM4_GPLLT_IN_B PL80A/PL107A PL80B/PL107B PL82A*/PL109A* PL82B*/PL109B* PL83A/PL110A* PL83B/PL110B* PL85A^/PL112A^ PL85B/PL112B PL86A/PL113A PL86B/PL113B PL88A*/PL115A* PL88B*/PL115B* PL89A/PL116A PL89B/PL116B PL91A*/PL118A* PL91B*/PL118B* PL92A/PL119A* PL92B/PL119B* PL94A^/PL121A^ PL94B/PL121B PL95A/PL122A PL95B/PL122B PL97A*/PL124A* PL97B*/PL124B* V11 V12 AB11 AB12 W10 W11 AH7 AJ7 AE9 AD10 AK6 AL6 AF9 AG9 AK7 AL7 AK8 AL8 AM7 AM8 AH9 AJ8 AN7 AP7 AN8 AP8 U2 U1 V9 V8 V2 V1 V5 W5 V4 V3 V7 W7 W2 W1 W8 W9 W4 W3 W6 Y6 Y2 Y1 Y8 AA8 Y5 Y4 Y9 Y10 AA2 AA1 Y7 AA7 AA4 AA3 AA10 AB9 AB2 AB1 AA5 AB5 AB4 AB3 AB7 AB6 AC2 AC1 AD5 AE5 AC5 AC4 AA9 AB8 AD2 AD1 AC6 AC7 AD4 AD3 AB10 AC10 AE2 AE1 AJ1 AK1 AE4 AE3 AC9 AC8 AM1 AM2 AL1 AL2 AN1 AN2 AD9 AD8 AP2 AP3 AJ2 AJ3 AL3 AK3 AJ4 AK4 AN3 AM3 AJ5 AJ6 AL5 AM5 AM6 AN6 AL4 AM4 AP5 AP6 4 DDR3 lower DQ, DQS, and DM signals RN58 U7E 4 DDR3_VDD DDR3_VTT DDR3_DQ0 DDR3_DQ1 DDR3_DQ2 DDR3_DQ3 DDR3_DQ4 DDR3_DQ5 DDR3_DQS0_P DDR3_DQS0_N DDR3_DQ6 DDR3_DQ7 DDR3_DM0 DDR3_DQ8 DDR3_DQ9 DDR3_DQ10 DDR3_DQ11 DDR3_DQ12 DDR3_DQ13 DDR3_DQS1_P DDR3_DQS1_N DDR3_DQ14 DDR3_DQ15 DDR3_DM1 DDR3_VTT DDR3_VTT DDR3_VTT TP94 TP95 TP96 TP97 TP98 TP99 TP100 TP101 TP102 TP103 TP104 TP105 TP106 TP107 DDR3_VTT DDR3_DQ16 DDR3_DQ17 DDR3_DQ18 DDR3_DQ19 DDR3_DQ20 DDR3_DQ21 DDR3_DQS2_P DDR3_DQS2_N DDR3_DQ22 DDR3_DQ23 DDR3_DM2 DDR3_VTT DDR3_DQ24 DDR3_DQ25 DDR3_DQ26 DDR3_DQ27 DDR3_DQ28 DDR3_DQ29 DDR3_DQS3_P DDR3_DQS3_N DDR3_DQ30 DDR3_DQ31 DDR3_DM3 DDR3_2_CK1P DDR3_2_CK1N ECP3_VREF DDR3_1_CK0P DDR3_1_CK0N DDR3_1_CK1P DDR3_1_CK1N DDR3_2_CK0P DDR3_2_CK0N DDR3_VDD DDR3_VDD DDR3_VDD DDR3_VDD DDR3_VDD DDR3_VDD DDR3_VDD SMA R342 33R-0603SMT J64 DDR3_VDD 1 RN60 741X083 8 7 6 5 RN61 DDR3_VDD 33 741X083 1 8 2 7 3 6 4 5 DDR3_VDD 33 1 2 3 4 DDR3_VDD 2 3 4 5 V5 TP88 TP89 TP90 TP91 TP84 TP85 TP86 TP87 BANK 7 N11 N12 U11 U12 T10 T11 G4 G5 K9 K8 H5 H4 F2 F1 F3 E3 G2 G1 G3 H3 H1 J1 J3 H2 K4 K3 K7 J6 K2 K1 L10 L9 L2 L1 M8 L7 L5 L4 K6 K5 M4 M3 N9 M9 M2 M1 M7 L6 N4 N3 M5 N5 N2 N1 M10 N10 P5 P4 N8 P8 P2 P1 N7 N6 R7 R5 P9 P10 R2 R1 P7 P6 R4 R3 R9 R10 T6 T5 R8 T7 T4 T3 T9 T8 T2 T1 U9 U8 U5 U4 U6 U7 [11] 3 ECP3_REF R104 C82 C92 Place VREF resistor and capacitors near ECP3 DDR3_VDD DDR3_VDD DDR3_VTT DDR3_CLK_FBP DDR3_CLK_FBN DDR3_CLK_P DDR3_CLK_N DDR3_DQ40 DDR3_DQ41 DDR3_DQ42 DDR3_DQ43 DDR3_DQ44 DDR3_DQ45 DDR3_DQS5_P DDR3_DQS5_N DDR3_DQ46 DDR3_DQ47 ECP3_VREF DDR3_DM5 DDR3_DQ32 DDR3_DQ33 DDR3_DQ34 DDR3_DQ35 DDR3_DQ36 DDR3_DQ37 DDR3_DQS4_P DDR3_DQS4_N DDR3_DQ38 DDR3_DQ39 DDR3_DM4 DDR3_VTT DDR3_DQ48 DDR3_DQ49 DDR3_DQ50 DDR3_DQ51 DDR3_DQ52 DDR3_DQS6_P DDR3_DQS6_N DDR3_DQ53 DDR3_DQ54 DDR3_DQ55 DDR3_DM6 DDR3_VTT DDR3_VTT DDR3_DQ56 DDR3_DQ57 DDR3_DQ58 DDR3_DQ59 DDR3_DQ60 DDR3_DQ61 DDR3_DQS7_P DDR3_DQS7_N DDR3_DQ62 DDR3_DQ63 DDR3_DM7 ECP3_VREF DDR3 upper DQ, DQS, and DM signals ECP3-150EA-7FN1156C VCCIO7/VCCIO7 VCCIO7/VCCIO7 VCCIO7/VCCIO7 VCCIO7/VCCIO7 VTT7/VTT7 VTT7/VTT7 PL2A/PL2A PL2B/PL2B PL4A*/NC PL4B*/NC PL5A/PL5A PL5B/PL5B PL8A/PL8A PL8B/PL8B PL10A*/PL10A* PL10B*/PL10B* PL11A/PL11A* PL11B/PL11B* PL13A^/PL13A^ PL13B/PL13B PL14A/PL14A PL14B/PL14B PL16A*/PL16A* PL16B*/PL16B* NC/PL17A NC/PL17B NC/PL19A* NC/PL19B* NC/PL20A* NC/PL20B* NC/PL22A^ NC/PL22B NC/PL23A NC/PL23B NC/PL25A* NC/PL25B* NC/PL26A NC/PL26B NC/PL28A* NC/PL28B* NC/PL29A* NC/PL29B* NC/PL31A^ NC/PL31B NC/PL32A NC/PL32B NC/PL34A* NC/PL34B* PL17A/PL35A PL17B/PL35B PL19A*/PL37A* PL19B*/PL37B* PL20A/PL38A* PL20B/PL38B* PL22A^/PL40A^ PL22B/PL40B PL23A/PL41A PL23B/PL41B PL25A*/PL43A* PL25B*/PL43B* PL25E_A/PL43E_A/LUM2_GPLLT_FB_A PL25E_B/PL43E_B/LUM2_GPLLT_FB_B PL25E_C/PL43E_C/LUM2_GPLLT_IN_A PL25E_D/PL43E_D/LUM2_GPLLT_IN_B PL26A/PL44A PL26B/PL44B PL28A*/PL46A* PL28B*/PL46B* PL29A/PL47A* PL29B/PL47B* PL31A^/PL49A^ PL31B/PL49B PL32A/PL50A PL32B/PL50B PL34A*/PL52A*/VREF1_7 PL34B*/PL52B*/VREF2_7 PL35A/PL53A PL35B/PL53B PL37A*/PL55A*/LUM0_GDLLT_IN_A PL37B*/PL55B*/LUM0_GDLLT_IN_B PL38A/PL56A*/LUM0_GDLLT_FB_A PL38B/PL56B*/LUM0_GDLLT_FB_B PL40A^/PL58A^ PL40B/PL58B PL41A/PL59A PL41B/PL59B PL43A*/PL61A*/PCLKT7_0 PL43B*/PL61B*/PCLKC7_0 PL43E_A/PL61E_A/LUM0_GPLLT_FB_A PL43E_B/PL61E_B/LUM0_GPLLT_FB_B PL43E_C/PL61E_C/LUM0_GPLLT_IN_A PL43E_D/PL61E_D/LUM0_GPLLT_IN_B U7F Place all 33 ohm resistors near ECP3 3 100R-0603SMT 5 100NF-0603SMT 55 100NF-0603SMT DDR3 Controller J6 DDR3 CLK Feed Back DDR3_CLK_P [8] DDR3_CLK_N [8] 2 3 4 5 2 3 4 5 2 3 4 5 K4 2 All memory controller buses, clocks, and control traces are 50 ohm transmission lines DDR3_CLK_P DDR3_CLK_N SMA DDR3_CLK_FBN 1 SMA J12 DDR3_CLK_FBP 1 DDR3_VDD DDR3_VDD DDR3_VDD DDR3_VDD DDR3_VDD DDR3_VDD 1 SMA R341 33R-0603SMT J65 DDR3_VDD 2 [14] MEM[0..132] MEM100 MEM101 MEM102 MEM103 MEM104 MEM105 MEM106 MEM107 DDR3_A13 DDR3_A10 DDR3_A11 DDR3_A12 DDR3_A9 DDR3_1_CK0P DDR3_1_CK0N DDR3_A14 Date: Size C Title MEM72 MEM73 MEM74 MEM75 DDR3_DQS6_P DDR3_DQS6_N DDR3_DQ54 DDR3_DQ55 MEM84 MEM85 MEM86 MEM87 MEM68 MEM69 MEM70 MEM71 DDR3_DQ50 DDR3_DQ51 DDR3_DQ52 DDR3_DQ53 DDR3_DQS7_N DDR3_DQ62 DDR3_DQ63 DDR3_DM7 MEM64 MEM65 MEM66 MEM67 DDR3_DQ47 DDR3_DM5 DDR3_DQ48 DDR3_DQ49 MEM80 MEM81 MEM82 MEM83 MEM60 MEM61 MEM62 MEM63 DDR3_DQS5_P DDR3_DQS5_N DDR3_DQ45 DDR3_DQ46 DDR3_DQ59 DDR3_DQ60 DDR3_DQ61 DDR3_DQS7_P MEM56 MEM57 MEM58 MEM59 DDR3_DQ41 DDR3_DQ42 DDR3_DQ43 DDR3_DQ44 MEM76 MEM77 MEM78 MEM79 MEM52 MEM53 MEM54 MEM55 DDR3_DQ38 DDR3_DM4 DDR3_DQ39 DDR3_DQ40 DDR3_DM6 DDR3_DQ56 DDR3_DQ57 DDR3_DQ58 MEM48 MEM49 MEM50 MEM51 MEM44 MEM45 MEM46 MEM47 MEM40 MEM41 MEM42 MEM43 MEM36 MEM37 MEM38 MEM39 MEM32 MEM33 MEM34 MEM35 MEM28 MEM29 MEM30 MEM31 MEM24 MEM25 MEM26 MEM27 MEM20 MEM21 MEM22 MEM23 MEM16 MEM17 MEM18 MEM19 DDR3_DQ36 DDR3_DQ37 DDR3_DQS4_P DDR3_DQS4_N DDR3_DQ32 DDR3_DQ33 DDR3_DQ34 DDR3_DQ35 DDR3_DQS3_N DDR3_DQ30 DDR3_DQ31 DDR3_DM3 DDR3_DQ27 DDR3_DQ28 DDR3_DQ29 DDR3_DQS3_P DDR3_DM2 DDR3_DQ24 DDR3_DQ25 DDR3_DQ26 DDR3_DQS2_P DDR3_DQS2_N DDR3_DQ22 DDR3_DQ23 DDR3_DQ18 DDR3_DQ19 DDR3_DQ20 DDR3_DQ21 DDR3_DQ15 DDR3_DM1 DDR3_DQ16 DDR3_DQ17 DDR3_DQ13 DDR3_DQS1_P DDR3_DQS1_N DDR3_DQ14 MEM12 MEM13 MEM14 MEM15 MEM8 MEM9 MEM10 MEM11 DDR3_DQ6 DDR3_DQ7 DDR3_DQ8 DDR3_DM0 DDR3_DQ9 DDR3_DQ10 DDR3_DQ11 DDR3_DQ12 MEM4 MEM5 MEM6 MEM7 MEM0 MEM1 MEM2 MEM3 DDR3_DQ4 DDR3_DQ5 DDR3_DQS0_P DDR3_DQS0_N DDR3_DQ0 DDR3_DQ1 DDR3_DQ2 DDR3_DQ3 Friday, June 11, 2010 1 Sheet 13 of 18 ECP3 IO Protocol Eval Board Schematic Project 1 C Rev Lattice Semiconductor Corporation 5555 N.E. Moore Court Hillsboro, Oregon. 97124 DDR3 Controller MEM[0..132] MEM127 MEM128 MEM129 MEM130 DDR3_2_CK1P DDR3_2_CK1N DDR3_2_S0N DDR3_2_S1N MEM120 MEM121 MEM122 MEM123 MEM124 MEM125 MEM126 DDR3_1_S1N DDR3_2_CKE1 DDR3_2_CKE0 DDR3_2_CK0P DDR3_2_CK0N DDR3_2_ODT0 DDR3_2_ODT1 MEM116 MEM117 MEM118 MEM119 MEM112 MEM113 MEM114 MEM115 DDR3_WEN DDR3_1_CK1P DDR3_1_CK1N DDR3_1_S0N DDR3_1_ODT0 DDR3_1_ODT1 DDR3_BA0 DDR3_CASN MEM108 MEM109 MEM110 MEM111 MEM96 MEM97 MEM98 MEM99 DDR3_A5 DDR3_A6 DDR3_A7 DDR3_A8 DDR3_A4 DDR3_RASN DDR3_BA1 DDR3_BA2 MEM92 MEM93 MEM94 MEM95 MEM88 MEM89 MEM90 MEM91 DDR3_A1 DDR3_A2 DDR3_A3 DDR3_A15 DDR3_1_CKE1 DDR3_1_CKE0 DDR3_RESETN DDR3_A0 DQ groups must use VREF1 A B C D LatticeECP3 I/O Protocol Board – Revision C User’s Guide Figure 32. DDR3 Controller A B C [11] DIMM2_REF [11] DIMM1_REF DDR3_2_CK1P DDR3_2_CK1N DDR3_2_S0N DDR3_2_S1N DDR3_2_CK0P DDR3_2_CK0N DDR3_2_ODT0 DDR3_2_ODT1 DDR3_1_S1N DDR3_2_CKE1 DDR3_2_CKE0 DDR3_WEN DDR3_1_CK1P DDR3_1_CK1N DDR3_1_S0N DDR3_1_ODT0 DDR3_1_ODT1 DDR3_BA0 DDR3_CASN DDR3_A4 DDR3_RASN DDR3_BA1 DDR3_BA2 DDR3_A9 DDR3_1_CK0P DDR3_1_CK0N DDR3_A14 DDR3_A13 DDR3_A10 DDR3_A11 DDR3_A12 DDR3_A5 DDR3_A6 DDR3_A7 DDR3_A8 DDR3_A1 DDR3_A2 DDR3_A3 DDR3_A15 137R-0603SMT 137R-0603SMT 137R-0603SMT 137R-0603SMT 137R-0603SMT R340 R339 R337 R338 R336 R6 R5 C2 C1 C65 C56 DIMM1_VREF All 15 and 100 ohm resistors on this page are placed near the ECP3 741X083 DIMM1_CKE1 8 DIMM1_CKE0 7 DIMM_RESETN 6 DIMM_A0 5 741X083 DIMM_A1 8 DIMM_A2 7 DIMM_A3 6 DIMM_A15 5 741X083 DIMM_A5 8 DIMM_A6 7 DIMM_A7 6 DIMM_A8 5 741X083 DIMM_A13 8 DIMM_A10 7 DIMM_A11 6 DIMM_A12 5 741X083 DIMM_A9 8 DIMM1_CK0P 7 DIMM1_CK0N 6 DIMM_A14 5 741X083 DIMM_A4 8 DIMM_RASN 7 DIMM_BA1 6 DIMM_BA2 5 741X083 DIMM1_ODT0 8 DIMM1_ODT1 7 DIMM_BA0 6 DIMM_CASN 5 741X083 DIMM_WEN 8 DIMM1_CK1P 7 DIMM1_CK1N 6 DIMM1_S0N 5 741X083 DIMM1_S1N 8 DIMM2_CKE1 7 DIMM2_CKE0 6 5 741X083 DIMM2_CK0P 8 DIMM2_CK0N 7 DIMM2_ODT0 6 DIMM2_ODT1 5 741X083 DIMM2_CK1P 8 DIMM2_CK1N 7 DIMM2_S0N 6 DIMM2_S1N 5 DIMM2_VREF 5 Place VREF resistors and capacitors near DIMMs 15 15 15 15 15 15 15 15 15 15 15 100R-0603SMT 100R-0603SMT RN7 1 2 3 4 RN3 1 2 3 4 RN2 1 2 3 4 RN30 1 2 3 4 RN32 1 2 3 4 RN31 1 2 3 4 RN1 1 2 3 4 RN33 1 2 3 4 RN4 1 2 3 4 RN15 1 2 3 4 RN6 1 2 3 4 [3,5] 15 RN17 1 2 3 4 RN11 1 2 3 4 I2C_SDA I2C_SCL I2C_SDA I2C_SCL DDR3_VTT DDR3_VTT DDR3_VTT DDR3_VTT DDR3_VTT DDR3_VTT DDR3_VTT DDR3_VTT DDR3_VTT DDR3_VTT DDR3_VTT DDR3_VTT DDR3_VTT DDR3_VTT DDR3_VTT DDR3_VTT DDR3_VTT DDR3_VTT DDR3_VTT DDR3_VTT 4 3_3V 3_3V DDR3_VTT DDR3_VDD 2_2K-0603SMT R91 2_2K-0603SMT R90 741X083 DIMM_DM0 8 DIMM_DM1 7 DIMM_DM2 6 DIMM_DM3 5 15 741X083 DIMM_DM4 8 DIMM_DM5 7 DIMM_DM6 6 DIMM_DM7 5 100 741X083 8 7 6 5 100 741X083 8 7 6 5 100 741X083 8 7 6 5 100 741X083 8 7 6 5 100 741X083 8 7 6 5 100 741X083 8 7 6 5 100 741X083 8 7 6 5 100 741X083 8 7 6 5 100 741X083 8 7 6 5 100 741X083 8 7 6 5 100 741X083 8 7 6 5 100 741X083 8 7 6 5 100 741X083 8 7 6 5 100 741X083 8 7 6 5 100 741X083 8 7 6 5 100 741X083 8 7 6 5 100 741X083 8 7 6 5 100 741X083 8 7 6 5 100 741X083 8 7 6 5 100 741X083 8 7 6 5 RN49 1 2 3 4 RN20 1 2 3 4 RN48 1 2 3 4 RN19 1 2 3 4 RN18 1 2 3 4 RN46 1 2 3 4 RN47 1 2 3 4 RN16 1 2 3 4 RN44 1 2 3 4 RN45 1 2 3 4 RN41 1 2 3 4 RN42 1 2 3 4 RN13 1 2 3 4 RN40 1 2 3 4 RN12 1 2 3 4 RN38 1 2 3 4 RN39 1 2 3 4 RN10 1 2 3 4 RN9 1 2 3 4 RN37 1 2 3 4 4 DQ, DQS, and DM signals are common between modules DDR3_DM4 DDR3_DM5 DDR3_DM6 DDR3_DM7 DDR3_DM0 DDR3_DM1 DDR3_DM2 DDR3_DM3 DDR3_DQS7_N DDR3_DQ62 DDR3_DQ63 DDR3_DQ49 DDR3_DQ59 DDR3_DQ60 DDR3_DQ61 DDR3_DQS7_P DDR3_DQ48 DDR3_DQ56 DDR3_DQ57 DDR3_DQ58 DDR3_DQS6_P DDR3_DQS6_N DDR3_DQ54 DDR3_DQ55 DDR3_DQ50 DDR3_DQ51 DDR3_DQ52 DDR3_DQ53 DDR3_DQS5_P DDR3_DQS5_N DDR3_DQ45 DDR3_DQ46 DDR3_DQ41 DDR3_DQ42 DDR3_DQ43 DDR3_DQ44 DDR3_DQ38 DDR3_DQ47 DDR3_DQ39 DDR3_DQ40 DDR3_DQ36 DDR3_DQ37 DDR3_DQS4_P DDR3_DQS4_N DDR3_DQ32 DDR3_DQ33 DDR3_DQ34 DDR3_DQ35 DDR3_DQS3_N DDR3_DQ30 DDR3_DQ31 DDR3_DQ17 DDR3_DQ27 DDR3_DQ28 DDR3_DQ29 DDR3_DQS3_P DDR3_DQ16 DDR3_DQ24 DDR3_DQ25 DDR3_DQ26 DDR3_DQS2_P DDR3_DQS2_N DDR3_DQ22 DDR3_DQ23 DDR3_DQ18 DDR3_DQ19 DDR3_DQ20 DDR3_DQ21 DDR3_DQ13 DDR3_DQS1_P DDR3_DQS1_N DDR3_DQ14 DDR3_DQ9 DDR3_DQ10 DDR3_DQ11 DDR3_DQ12 DDR3_DQ6 DDR3_DQ7 DDR3_DQ8 DDR3_DQ15 DDR3_DQ4 DDR3_DQ5 DDR3_DQS0_P DDR3_DQS0_N DDR3_DQ0 DDR3_DQ1 DDR3_DQ2 DDR3_DQ3 I2C Interface Place 137 ohm pulldowns furthest from the ECP3, near the DIMM1 pins 100NF-0603SMT DDR3_1_CKE1 DDR3_1_CKE0 DDR3_RESETN DDR3_A0 100NF-0603SMT 100NF-0603SMT 56 100NF-0603SMT D DDR3 DIMMs 5 DIMM_2_SA1 DDR3_VTT DIMM_1_SA0 I2C_SCL DDR3_DQ58 DDR3_DQ59 DDR3_DQS7_N DDR3_DQS7_P DDR3_DQ56 DDR3_DQ57 DDR3_DQ50 DDR3_DQ51 DDR3_DQS6_N DDR3_DQS6_P DDR3_DQ48 DDR3_DQ49 DDR3_DQ42 DDR3_DQ43 DDR3_DQS5_N DDR3_DQS5_P DDR3_DQ40 DDR3_DQ41 DDR3_DQ34 DDR3_DQ35 DDR3_DQS4_N DDR3_DQS4_P DDR3_DQ32 DDR3_DQ33 n.c. DIMM1_S1N DIMM1_ODT1 DIMM_WEN DIMM_CASN DIMM_A10 DIMM_BA0 n.c. DIMM1_VREF DIMM1_CK1P DIMM1_CK1N DIMM_A2 DIMM_A5 DIMM_A4 DIMM_A11 DIMM_A7 n.c. DIMM_BA2 DDR3_VTT DIMM1_CKE0 DDR3_VTT n.c. n.c. n.c. n.c. n.c. n.c. DDR3_DQ26 DDR3_DQ27 DDR3_DQS3_N DDR3_DQS3_P DDR3_DQ24 DDR3_DQ25 DDR3_DQ18 DDR3_DQ19 DDR3_DQS2_N DDR3_DQS2_P DDR3_DQ16 DDR3_DQ17 DDR3_DQ10 DDR3_DQ11 DDR3_DQS1_N DDR3_DQS1_P DDR3_DQ8 DDR3_DQ9 DDR3_DQ2 DDR3_DQ3 DDR3_DQS0_N DDR3_DQS0_P DDR3_DQ0 DDR3_DQ1 DIMM1_VREF DDR3_VDD VTT CKE1 CKE0 VDD VDD A15 BA2 A14 ERR_OUT# VDD VDD A12 A11 A9 A7 VDD VDD A8 A5 A6 A4 VDD VDD A3 A1 A2 VDD VDD CK1 VDD CK1# CK0 VDD CK0# VDD VDD VREF_CA EVENT# PAR_IN A0 VDD VDD A10 BA1 BA0 VDD VDD RAS# WE# S0# CAS# VDD VDD ODT0 S1# A13 ODT1 VDD VDD nc nc VSS VSS DQ36 DQ32 DQ37 VSS DQ33 VSS DM4 DQS4# nu DQS4 VSS VSS DQ38 DQ34 DQ39 DQ35 VSS VSS DQ44 DQ40 DQ45 VSS DQ41 VSS DM5 DQS5# nu VSS DQS5 VSS DQ46 DQ42 DQ47 VSS DQ43 VSS DQ52 DQ48 DQ53 DQ49 VSS VSS DM6 DQS6# nu DQS6 VSS VSS DQ54 DQ50 DQ55 DQ51 VSS VSS DQ60 DQ56 DQ61 DQ57 VSS VSS DM7 DQS7# nu DQS7 VSS VSS DQ62 DQ58 DQ63 DQ59 VSS VSS VDDSPD SA0 SA1 SCL SDA VSS SA2 VTT VTT 3 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 3 DIMM #1 is set for EEPROM address 1 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 1.5V DDR3 240-pin DIMM J1B VREF_DQ VSS VSS DQ4 DQ0 DQ5 DQ1 VSS VSS DM0 DQS0# nu DQS0 VSS VSS DQ6 DQ2 DQ7 DQ3 VSS VSS DQ12 DQ8 DQ13 DQ9 VSS VSS DM1 DQS1# nu DQS1 VSS DQ14 VSS DQ10 DQ15 DQ11 VSS VSS DQ20 DQ16 DQ21 DQ17 VSS VSS DM2 DQS2# nu DQS2 VSS DQ22 VSS DQ18 DQ23 DQ19 VSS VSS DQ28 DQ24 DQ29 DQ25 VSS VSS DM3 DQS3# nu DQS3 VSS VSS DQ30 DQ26 DQ31 DQ27 VSS CB4 VSS CB5 CB0 CB1 VSS VSS DM8 DQS8# nu DQS8 VSS CB6 VSS CB7 CB2 CB3 VSS VSS nc VTT RESET# 1.5V DDR3 240-pin DIMM 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 J1A DDR3_VTT I2C_SDA 3_3V DDR3_DQ62 DDR3_DQ63 n.c. DIMM_DM7 DDR3_DQ60 DDR3_DQ61 DDR3_DQ54 DDR3_DQ55 n.c. DIMM_DM6 DDR3_DQ52 DDR3_DQ53 DDR3_DQ46 DDR3_DQ47 n.c. DIMM_DM5 DDR3_DQ44 DDR3_DQ45 DDR3_DQ38 DDR3_DQ39 n.c. DIMM_DM4 DDR3_DQ36 DDR3_DQ37 n.c. DIMM1_ODT0 DIMM_A13 DIMM_RASN DIMM1_S0N DIMM_BA1 DIMM_A0 n.c. DIMM1_CK0P DIMM1_CK0N DIMM_A3 DIMM_A1 DIMM_A8 DIMM_A6 DIMM_A12 DIMM_A9 DIMM_A15 DIMM_A14 DIMM1_CKE1 DIMM_RESETN n.c. n.c. n.c. n.c. n.c. n.c. n.c. DDR3_DQ30 DDR3_DQ31 n.c. DIMM_DM3 DDR3_DQ28 DDR3_DQ29 DDR3_DQ22 DDR3_DQ23 n.c. DIMM_DM2 DDR3_DQ20 DDR3_DQ21 DDR3_DQ14 DDR3_DQ15 n.c. DIMM_DM1 DDR3_DQ12 DDR3_DQ13 DDR3_DQ6 DDR3_DQ7 n.c. DIMM_DM0 DDR3_DQ4 DDR3_DQ5 DDR3_VTT I2C_SCL DDR3_DQ58 DDR3_DQ59 DDR3_DQS7_N DDR3_DQS7_P DDR3_DQ56 DDR3_DQ57 DDR3_DQ50 DDR3_DQ51 DDR3_DQS6_N DDR3_DQS6_P DDR3_DQ48 DDR3_DQ49 DDR3_DQ42 DDR3_DQ43 DDR3_DQS5_N DDR3_DQS5_P DDR3_DQ40 DDR3_DQ41 DDR3_DQ34 DDR3_DQ35 DDR3_DQS4_N DDR3_DQS4_P DDR3_DQ32 DDR3_DQ33 n.c. DIMM2_S1N DIMM2_ODT1 DIMM_WEN DIMM_CASN DIMM_A10 DIMM_BA0 n.c. DIMM2_VREF DIMM2_CK1P DIMM2_CK1N DIMM_A2 DIMM_A5 DIMM_A4 DIMM_A11 DIMM_A7 n.c. DIMM_BA2 DDR3_VTT DIMM2_CKE0 DDR3_VTT n.c. n.c. n.c. n.c. n.c. n.c. DDR3_DQ26 DDR3_DQ27 DDR3_DQS3_N DDR3_DQS3_P DDR3_DQ24 DDR3_DQ25 DDR3_DQ18 DDR3_DQ19 DDR3_DQS2_N DDR3_DQS2_P DDR3_DQ16 DDR3_DQ17 DDR3_DQ10 DDR3_DQ11 DDR3_DQS1_N DDR3_DQS1_P DDR3_DQ8 DDR3_DQ9 DDR3_DQ2 DDR3_DQ3 DDR3_DQS0_N DDR3_DQS0_P DDR3_DQ0 DDR3_DQ1 DIMM2_VREF DDR3_VDD 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 VTT CKE1 VDD CKE0 VDD A15 BA2 A14 ERR_OUT# VDD VDD A12 A11 A9 A7 VDD VDD A8 A5 A6 VDD A4 A3 VDD A1 A2 VDD VDD CK1 VDD CK1# CK0 VDD CK0# VDD VDD VREF_CA EVENT# PAR_IN A0 VDD VDD A10 BA1 BA0 VDD VDD RAS# WE# S0# CAS# VDD VDD ODT0 S1# A13 ODT1 VDD nc VDD nc VSS VSS DQ36 DQ32 DQ37 DQ33 VSS VSS DM4 nu DQS4# DQS4 VSS VSS DQ38 DQ39 DQ34 DQ35 VSS VSS DQ44 DQ40 DQ45 VSS DQ41 DM5 VSS DQS5# nu VSS DQS5 VSS DQ46 DQ47 DQ42 DQ43 VSS VSS DQ52 DQ48 DQ53 DQ49 VSS VSS DM6 nu DQS6# DQS6 VSS DQ54 VSS DQ55 DQ50 VSS DQ51 VSS DQ60 DQ56 DQ61 DQ57 VSS VSS DM7 DQS7# nu DQS7 VSS VSS DQ62 DQ58 DQ63 DQ59 VSS VSS VDDSPD SA0 SA1 SCL SDA SA2 VSS VTT VTT 2 2 DIMM #2 is set for EEPROM address 2 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 1.5V DDR3 240-pin DIMM J3B VSS VREF_DQ VSS DQ4 DQ5 DQ0 VSS DQ1 DM0 VSS nu DQS0# VSS DQS0 DQ6 VSS DQ7 DQ2 VSS DQ3 VSS DQ12 DQ8 DQ13 VSS DQ9 DM1 VSS nu DQS1# VSS DQS1 VSS DQ14 DQ10 DQ15 VSS DQ11 VSS DQ20 DQ21 DQ16 VSS DQ17 DM2 VSS DQS2# nu DQS2 VSS VSS DQ22 DQ23 DQ18 VSS DQ19 VSS DQ28 DQ24 DQ29 VSS DQ25 VSS DM3 DQS3# nu DQS3 VSS VSS DQ30 DQ26 DQ31 DQ27 VSS VSS CB4 CB0 CB5 CB1 VSS DM8 VSS DQS8# nu DQS8 VSS VSS CB6 CB7 CB2 CB3 VSS VSS nc VTT RESET# 1.5V DDR3 240-pin DIMM 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 J3A DDR3_VTT DIMM_2_SA1 I2C_SDA 3_3V DDR3_DQ62 DDR3_DQ63 n.c. DIMM_DM7 DDR3_DQ60 DDR3_DQ61 DDR3_DQ54 DDR3_DQ55 n.c. DIMM_DM6 DDR3_DQ52 DDR3_DQ53 DDR3_DQ46 DDR3_DQ47 n.c. DIMM_DM5 DDR3_DQ44 DDR3_DQ45 DDR3_DQ38 DDR3_DQ39 n.c. DIMM_DM4 DDR3_DQ36 DDR3_DQ37 n.c. DIMM2_ODT0 DIMM_A13 DIMM_RASN DIMM2_S0N DIMM_BA1 DIMM_A0 n.c. DIMM2_CK0P DIMM2_CK0N DIMM_A3 DIMM_A1 DIMM_A8 DIMM_A6 DIMM_A12 DIMM_A9 DIMM_A15 DIMM_A14 DIMM2_CKE1 DIMM_RESETN n.c. n.c. n.c. n.c. n.c. n.c. n.c. DDR3_DQ30 DDR3_DQ31 n.c. DIMM_DM3 DDR3_DQ28 DDR3_DQ29 DDR3_DQ22 DDR3_DQ23 n.c. DIMM_DM2 DDR3_DQ20 DDR3_DQ21 DDR3_DQ14 DDR3_DQ15 n.c. DIMM_DM1 DDR3_DQ12 DDR3_DQ13 DDR3_DQ6 DDR3_DQ7 n.c. DIMM_DM0 DDR3_DQ4 DDR3_DQ5 [13] MEM[0..132] MEM127 MEM128 MEM129 MEM130 Date: Size C Title MEM84 MEM85 MEM86 MEM87 MEM80 MEM81 MEM82 MEM83 MEM76 MEM77 MEM78 MEM79 MEM72 MEM73 MEM74 MEM75 MEM68 MEM69 MEM70 MEM71 MEM64 MEM65 MEM66 MEM67 MEM60 MEM61 MEM62 MEM63 MEM56 MEM57 MEM58 MEM59 MEM52 MEM53 MEM54 MEM55 Friday, June 11, 2010 1 Sheet 14 of 18 ECP3 IO Protocol Eval Board Schematic Project DDR3_DQS7_N DDR3_DQ62 DDR3_DQ63 DDR3_DM7 DDR3_DQ59 DDR3_DQ60 DDR3_DQ61 DDR3_DQS7_P DDR3_DM6 DDR3_DQ56 DDR3_DQ57 DDR3_DQ58 DDR3_DQS6_P DDR3_DQS6_N DDR3_DQ54 DDR3_DQ55 DDR3_DQ50 DDR3_DQ51 DDR3_DQ52 DDR3_DQ53 DDR3_DQ47 DDR3_DM5 DDR3_DQ48 DDR3_DQ49 DDR3_DQS5_P DDR3_DQS5_N DDR3_DQ45 DDR3_DQ46 DDR3_DQ41 DDR3_DQ42 DDR3_DQ43 DDR3_DQ44 DDR3_DQ38 DDR3_DM4 DDR3_DQ39 DDR3_DQ40 MEM48 MEM49 MEM50 MEM51 MEM44 MEM45 MEM46 MEM47 DDR3_DQ32 DDR3_DQ33 DDR3_DQ34 DDR3_DQ35 DDR3_DQ36 DDR3_DQ37 DDR3_DQS4_P DDR3_DQS4_N MEM40 MEM41 MEM42 MEM43 MEM36 MEM37 MEM38 MEM39 MEM32 MEM33 MEM34 MEM35 MEM28 MEM29 MEM30 MEM31 MEM24 MEM25 MEM26 MEM27 MEM20 MEM21 MEM22 MEM23 MEM16 MEM17 MEM18 MEM19 MEM12 MEM13 MEM14 MEM15 MEM8 MEM9 MEM10 MEM11 MEM4 MEM5 MEM6 MEM7 MEM0 MEM1 MEM2 MEM3 DDR3_DQS3_N DDR3_DQ30 DDR3_DQ31 DDR3_DM3 DDR3_DQ27 DDR3_DQ28 DDR3_DQ29 DDR3_DQS3_P DDR3_DM2 DDR3_DQ24 DDR3_DQ25 DDR3_DQ26 DDR3_DQS2_P DDR3_DQS2_N DDR3_DQ22 DDR3_DQ23 DDR3_DQ18 DDR3_DQ19 DDR3_DQ20 DDR3_DQ21 DDR3_DQ15 DDR3_DM1 DDR3_DQ16 DDR3_DQ17 DDR3_DQ13 DDR3_DQS1_P DDR3_DQS1_N DDR3_DQ14 DDR3_DQ9 DDR3_DQ10 DDR3_DQ11 DDR3_DQ12 DDR3_DQ6 DDR3_DQ7 DDR3_DQ8 DDR3_DM0 DDR3_DQ4 DDR3_DQ5 DDR3_DQS0_P DDR3_DQS0_N DDR3_DQ0 DDR3_DQ1 DDR3_DQ2 DDR3_DQ3 C Rev Lattice Semiconductor Corporation 5555 N.E. Moore Court Hillsboro, Oregon. 97124 DDR3 Memory MEM[0..132] MEM123 MEM124 MEM125 MEM126 DDR3_2_CK1P DDR3_2_CK1N DDR3_2_S0N DDR3_2_S1N MEM120 MEM121 MEM122 MEM116 MEM117 MEM118 MEM119 MEM112 MEM113 MEM114 MEM115 DDR3_2_CK0P DDR3_2_CK0N DDR3_2_ODT0 DDR3_2_ODT1 DDR3_1_S1N DDR3_2_CKE1 DDR3_2_CKE0 DDR3_WEN DDR3_1_CK1P DDR3_1_CK1N DDR3_1_S0N DDR3_1_ODT0 DDR3_1_ODT1 DDR3_BA0 DDR3_CASN MEM108 MEM109 MEM110 MEM111 MEM104 MEM105 MEM106 MEM107 DDR3_A9 DDR3_1_CK0P DDR3_1_CK0N DDR3_A14 DDR3_A4 DDR3_RASN DDR3_BA1 DDR3_BA2 MEM100 MEM101 MEM102 MEM103 MEM96 MEM97 MEM98 MEM99 MEM92 MEM93 MEM94 MEM95 MEM88 MEM89 MEM90 MEM91 DDR3_A13 DDR3_A10 DDR3_A11 DDR3_A12 DDR3_A5 DDR3_A6 DDR3_A7 DDR3_A8 DDR3_A1 DDR3_A2 DDR3_A3 DDR3_A15 DDR3_1_CKE1 DDR3_1_CKE0 DDR3_RESETN DDR3_A0 1 A B C D LatticeECP3 I/O Protocol Board – Revision C User’s Guide Figure 33. DDR Memory A B C [13] LED[0..7] LED[0..7] LEDs 2N2222/SOT23 Q6 2N2222/SOT23 R155 270R-0402SMT LED0_E 1 LED-SMT1206_BLUE D6 LED0_C 12_0V U7J ECP3-95E-7FN1156ES LED0 Q2 R126 162R-0402SMT SEG0_E SEVEN_SEG0 1 SEG0 SEVEN_SEG[0..7] R 3 2 3 2 [13] SEVEN_SEG[0..7] 7 Segment Display U9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SEG1 SEG4 SEG3 SEG7 SEG2 SEG6 SEG0 SEG5 LED1 Q7 2N2222/SOT23 Q14 2N2222/SOT23 R177 270R-0402SMT LED1_E 1 LED-SMT1206_GREEN D9 LED1_C 12_0V R150 162R-0402SMT SEG1_E SEVEN_SEG1 1 SEG1 Seven Segment Display NAR141B 738 mil x 412 mil cathode A cathode F annode1 NC1 NC2 NC3 cathode E cathode D cathode DP cathode C cathode G NC4 cathode B annode2 Y 3 2 3 2 D SEG2 LED2 Q10 2N2222/SOT23 Q15 2N2222/SOT23 R189 270R-0402SMT LED2_E 1 LED-SMT1206_YELLOW D10 LED2_C 12_0V R153 162R-0402SMT SEG2_E SEVEN_SEG2 1 12_0V G 3 2 3 2 LED3 Q5 2N2222/SOT23 (C6) Q17 2N2222/SOT23 R195 270R-0402SMT LED3_E 1 LED3_C LED-SMT1206_RED D12 12_0V B(Pin 13) SEG4 LED4 Q3 2N2222/SOT23 Q18 2N2222/SOT23 R199 270R-0402SMT LED4_E 1 LED4_C LED-SMT1206_BLUE D14 12_0V R133 162R-0402SMT SEG4_E SEG5 LED5 Q8 2N2222/SOT23 Q16 2N2222/SOT23 R193 270R-0402SMT LED5_E 1 LED-SMT1206_GREEN D11 LED5_C 12_0V R151 162R-0402SMT SEG5_E SEVEN_SEG5 1 DP(Pin 9) (C5) (D5) (A2) SEVEN_SEG4 1 D(Pin 8) (D6) G(Pin 11) (B3) A(Pin 1) R148 162R-0402SMT SEG3_E SEVEN_SEG3 1 SEG3 (B4) (A3) F(Pin 2) E(Pin 7) LEDs and DIP Switch B 3 2 3 2 3 2 C(Pin 10) B 3 2 3 G 3 2 3 2 4 SEG6 LED6 Q9 2N2222/SOT23 Q13 2N2222/SOT23 R164 270R-0402SMT LED6_E 1 LED-SMT1206_YELLOW D8 LED6_C 12_0V R152 162R-0402SMT SEG6_E SEVEN_SEG6 1 Y 3 GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND 5 4 3 XRES/XRES NC/NC NC/NC SEG7 2 W23 AP4 AN4 Q12 2N2222/SOT23 R162 270R-0402SMT LED7_E 1 LED-SMT1206_RED D7 LED7_C 12_0V R149 10K-0603SMT LED7 Q11 2N2222/SOT23 R154 162R-0402SMT SEG7_E SEVEN_SEG7 1 2 3 2 3 2 3 2 Y3 Y29 Y24 Y21 Y20 Y19 Y18 Y17 Y16 Y15 Y14 Y11 W21 W20 W19 W18 W17 W16 W15 W14 W12 V6 V32 V25 V21 V20 V19 V18 V17 V16 V15 V14 V10 U3 U29 U25 U21 U20 U19 U18 U17 U16 U15 U14 U10 T23 T21 T20 T19 T18 T17 T16 T15 T14 T12 R6 R32 R24 R21 R20 R19 R18 R17 R16 R15 R14 R11 P3 P29 P24 P21 P20 P19 P18 P17 P16 P15 P14 P11 M6 M32 M24 M23 M19 M16 M12 M11 L3 L29 L24 L23 L21 L20 L15 L14 L12 L11 K18 K17 J5 J33 J30 J2 H8 H27 F23 F20 F17 F14 F11 E9 E5 E33 E30 E26 E2 C24 C21 C18 C15 GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND GND/GND A1 A34 AA11 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA24 AA32 AA6 AC11 AC12 AC16 AC19 AC23 AC24 AC29 AC3 AD11 AD12 AD14 AD15 AD20 AD21 AD23 AD24 AD32 AD6 AE10 AE11 AE17 AE18 AE24 AE25 AF10 AF2 AF25 AF30 AF33 AF5 AG10 AG25 AG27 AG8 AH10 AH11 AH14 AH17 AH18 AH21 AH24 AH25 AJ10 AJ11 AJ12 AJ13 AJ14 AJ15 AJ16 AJ17 AJ18 AJ19 AJ20 AJ21 AJ22 AJ23 AJ24 AJ25 AJ26 AJ9 AK2 AK26 AK30 AK33 AK5 AK9 AL26 AL9 AM10 AM11 AM12 AM13 AM14 AM15 AM16 AM17 AM18 AM19 AM20 AM21 AM22 AM23 AM24 AM25 AM26 AM9 AN26 AN30 AN5 AN9 AP1 AP26 AP34 AP9 B26 B30 B5 B9 C12 R 57 2 5 Date: Size C Title 5 4_7K 12 RN50E EXB2HV472JV 6 4_7K 11 RN50F EXB2HV472JV 7 4_7K 10 RN50G EXB2HV472JV 8 4_7K 9 RN50H EXB2HV472JV SWITCH2 SWITCH1 SWITCH0 Monday, June 14, 2010 1 Sheet 15 of 18 ECP3 IO Protocol Eval Board Schematic Project C Rev Lattice Semiconductor Corporation 5555 N.E. Moore Court Hillsboro, Oregon. 97124 SWITCH7 SWITCH6 SWITCH5 SWITCH4 SWITCH3 SWITCH2 SWITCH1 SWITCH0 4 4_7K 13 RN50D EXB2HV472JV 3 4_7K 14 RN50C EXB2HV472JV SWITCH5 SWITCH3 2 4_7K 15 RN50B EXB2HV472JV SWITCH4 1 4_7K 16 RN50A EXB2HV472JV SWITCH7 SWITCH6 SW DIP-8/SM SW4 AL13 AK13 AL12 AK12 AL11 AK11 AL10 AK10 AP13 AN13 AP12 AN12 AP11 AN11 AP10 AN10 AH12 AH13 AE15 AF13 AF12 AF11 AE14 AG13 AG12 AG11 AL25 AK25 AL24 AK24 AL23 AK23 AL22 AK22 AN24 AP25 AN25 AP24 AP23 AN23 AP22 AN22 AH22 AH23 AF24 AF23 AF22 AE20 AG24 AG23 AG22 AE21 DDR3_VDD DIP SWITCH Pinout for ECP3 device density is shown on symbol as: -95/-150 ECP3-150EA-7FN1156C SERDES Quads C & D NC/PCSD_HDINP0 NC/PCSD_HDINN0 NC/PCSD_HDINP1 NC/PCSD_HDINN1 NC/PCSD_HDINP2 NC/PCSD_HDINN2 NC/PCSD_HDINP3 NC/PCSD_HDINN3 NC/PCSD_HDOUTP0 NC/PCSD_HDOUTN0 NC/PCSD_HDOUTP1 NC/PCSD_HDOUTN1 NC/PCSD_HDOUTP2 NC/PCSD_HDOUTN2 NC/PCSD_HDOUTP3 NC/PCSD_HDOUTN3 NC/PCSD_REFCLKP NC/PCSD_REFCLKN NC/PCSD_VCCIB0 NC/PCSD_VCCIB1 NC/PCSD_VCCIB2 NC/PCSD_VCCIB3 NC/PCSD_VCCOB0 NC/PCSD_VCCOB1 NC/PCSD_VCCOB2 NC/PCSD_VCCOB3 PCSC_HDINP0/PCSC_HDINP0 PCSC_HDINN0/PCSC_HDINN0 PCSC_HDINP1/PCSC_HDINP1 PCSC_HDINN1/PCSC_HDINN1 PCSC_HDINP2/PCSC_HDINP2 PCSC_HDINN2/PCSC_HDINN2 PCSC_HDINP3/PCSC_HDINP3 PCSC_HDINN3/PCSC_HDINN3 PCSC_HDOUTN1/PCSC_HDOUTN1 PCSC_HDOUTP0/PCSC_HDOUTP0 PCSC_HDOUTN0/PCSC_HDOUTN0 PCSC_HDOUTP1/PCSC_HDOUTP1 PCSC_HDOUTP2/PCSC_HDOUTP2 PCSC_HDOUTN2/PCSC_HDOUTN2 PCSC_HDOUTP3/PCSC_HDOUTP3 PCSC_HDOUTN3/PCSC_HDOUTN3 PCSC_REFCLKP/PCSC_REFCLKP PCSC_REFCLKN/PCSC_REFCLKN PCSC_VCCIB0/PCSC_VCCIB0 PCSC_VCCIB1/PCSC_VCCIB1 PCSC_VCCIB2/PCSC_VCCIB2 PCSC_VCCIB3/PCSC_VCCIB3 PCSC_VCCOB0/PCSC_VCCOB0 PCSC_VCCOB1/PCSC_VCCOB1 PCSC_VCCOB2/PCSC_VCCOB2 PCSC_VCCOB3/PCSC_VCCOB3 LEDs & DIP Switch [13] SWITCH[0..7] 1 U7I A B C D LatticeECP3 I/O Protocol Board – Revision C User’s Guide Figure 34. LEDs and DIP Switch A B C VCCIO1/VCCIO1 VCCIO1/VCCIO1 VCCIO1/VCCIO1 VCCIO1/VCCIO1 ECP3-150EA-7FN1156C BANK 1 5 U7B VCCIO_1 M22 M18 L22 L18 LA5 LA6 LA7 LA8 LA9 LA10 LA11 LA12 LA13 LA14 LA15 LA16 LA17 LA18 LA19 LA20 LA21 LA22 LA23 LA24 RN54 741X083 33 RN24 741X083 33 RN27 741X083 33 RN53 741X083 33 LA1 8 LA2 7 LA3 6 LA4 5 RN23 741X083 33 LA1 LA3 LA5 LA7 LA9 LA11 LA13 LA15 LA17 LA19 LA21 LA23 LA25 LA27 LA29 LA31 LA33 R16 DNI-0603SMT R22 DNI-0603SMT VCCIO_1 C149 0.1uF VCCIO_1 RN52 741X083 33 PCLKT PCLKC 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 SCL 5V GND SDA CLK1 CLK 7 8 10 9 12 11 14 13 15 16 17 18 20 19 22 21 24 23 25 26 27 28 30 29 32 31 33 34 36 35 37 38 LA1 R111 DNI-0603SMT R114 DNI-0603SMT 0 R20 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 LA2 LA4 LA6 LA8 LA10 LA12 LA14 LA16 LA18 LA20 LA22 LA24 LA26 LA28 LA30 LA32 LA34 VCCIO_1 HC1 HC2 HC3 1 J46 SMA 2 3 4 5 ECP3 Symbol Pins: * True LVDS Output ^ DQS Density shown as -95/-150 HC_SMA High Current IO 37_4R-0603SMT R37 R38 R157 LOGIC ANALYZER PROBE 100NF-0603SMT 4 1NF-0402SMT 3_3V 2_5V 1NF-0402SMT 1_0K-0603SMT BANK 1 1_5V J41 1_2V 10NF-0603SMT SMA J39 1 DNL R64 DNL R185 VCCIO_1 IDC0 IDC1 IDC2 IDC3 IDC4 IDC5 IDC6 IDC7 IDC8 IDC9 IDC10 IDC11 IDC12 IDC13 IDC14 IDC15 2 3 4 5 DNL R63 Contrast Adjustment 2 VR2 10K Copal ST32ETB103 R136 10K N (E20) 2 DNL R61 DNL DNL R49 DNL DNL R47 DNL R167 R165 DNL R60 DNL DNL R58 DNL DNL R51 DNL R181 R179 R169 DNL R52 DNL DNL R53 DNL R170 R171 RX - series resistors near IDC connector remain 0 ohm. Resistors tied to VCCIO_1 and GND should be 240 ohms each. 2 TX - install 70 ohm series resistors near the IDC connector. Do not install resistors tied to VCCIO_1 or GND. 3 LCD0 LCD1 LCD2 LCD3 LCD4 LCD_R/W LCD_DB0 LCD_DB2 LCD_DB4 LCD_DB6 Backlight Adjustment VR1 10K Copal ST32ETB103 ANODE 2 DNL R54 DNL Date: Size B Title DNL R57 DNL DNL R48 NC2 VDD RS E DB1 DB3 DB5 DB7 CATHODE 2 4 6 8 10 12 14 16 18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCCIO_1 ECP3_H23 ECP3_D24 ECP3_E24 ECP3_K23 ECP3_K24 ECP3_A25 ECP3_B25 ECP3_C28 ECP3_D28 ECP3_C25 ECP3_D25 ECP3_G26 ECP3_G25 ECP3_B28 ECP3_A28 ECP3_A26 J57 HEADER 17X2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 Monday, June 14, 2010 1 Sheet 16 of 18 C Rev Lattice Semiconductor Corporation 5555 N.E. Moore Court Hillsboro, Oregon. 97124 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 100NF-0603SMT C252 VCCIO_1 LCD5 LCD6 LCD7 LCD8 LCD9 LCD10 C136 0.1uF Place these resistors near the IDC connector R271 R272 R273 R274 R275 R276 R277 R278 R279 R280 R281 R282 R283 R284 R285 R286 VCCIO_1 C180 LCD_RS LCD_E LCD_DB1 LCD_DB3 LCD_DB5 LCD_DB7 All high speed signals use 50 ohm traces DNL R50 DNL R166 R168 DNL NC1 VSS VO R/W DB0 DB2 DB4 DB6 ANODE LCD Connector 1 3 5 7 9 11 13 15 17 J32 HDR 9x2 ECP3 IO Protocol Eval Board Schematic Project 1 Prototype & Test Prototype & Test DNL R59 DNL R172 R178 R180 Place these resistors near the FPGA DNL R62 DNL 2 3 4 5 ECP3 High Speed Test Points C134 0.1uF VCCIO_1 R184 R183 R182 DNL [11] SMA J45 1 + C184 10uF, Tant 0805 5_0V P (E19) VCCIO_1 1 LA2 3 LA4 5 LA6 7 LA8 9 LA10 11 LA12 13 LA14 15 LA16 17 LA18 19 LA20 21 LA22 23 LA24 25 LA26 27 LA28 29 LA30 31 LA32 33 LA34 35 PLACE CLOSE TO LA CONNECTOR 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 J54 HEADER 18X2 3 For high speed signals over ribbon cable: 1_0K-0603SMT SMA_E19 SMA_E20 LA1 LA3 LA5 LA7 LA9 LA11 LA13 LA15 LA17 LA19 LA21 LA23 LA25 LA27 LA29 LA31 LA33 DNL Place resistors near ECP3 R21 R17 [16] SLEEP# RS232_[0..10] TXDEN# RS232_[0..10] PWREN# 2_767004 RI# DSR# LA25 RN25 8 LA26 741X083 7 LA27 33 6 LA28 5 LA29 RN26 8 LA30 741X083 7 LA31 33 6 LA32 Place resistors 5 LA33 RN55 8 near ECP3 TP19 VCCIO_1 TP21 VCCIO_1 LA34 741X083 7 LCD0 33 6 LCD1 5 LCD2 RN22 8 R30 R32 R131 LCD3 741X083 R127 7 100R-0603SMT 100R-0603SMT LCD4 33 6 LCD5 5 LCD6 RN51 VREF2 VREF1 8 LCD7 741X083 7 LCD8 33 C18 R132 C169 R29 6 LCD9 5 LCD10 R23 33 IDC0 RN57 1 8 IDC1 741X083 2 7 IDC2 33 1_0K-0603SMT 1_0K-0603SMT 3 6 IDC3 4 5 IDC4 RN56 1 8 VCCIO_1 IDC5 741X083 2 7 C156 IDC6 33 C141 C162 C170 C175 C245 3 6 IDC7 4 5 IDC8 RN29 1 8 IDC9 741X083 2 7 IDC10 33 3 6 IDC11 4 5 IDC12 RN28 1 8 IDC13 741X083 7 2 IDC14 33 3 6 IDC15 4 5 RS232_6 DCD# VCCIO_1 HEADER 3X2 RS232_7 CTS# VCCIO_1 RS232_8 RS232_9 RS232_10 RS232_4 RS232_5 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 TXD DTR# RTS# RXD VCCIO_1 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 RS232_0 RS232_1 RS232_2 RS232_3 VREF1 VREF2 PCLKT PCLKC 4 10NF-0603SMT 3 1 1 3 5 A17 B17 E19 E20 A18 B18 J18 H18 D18 E18 G19 H19 A19 B19 K20 L19 C19 D19 J19 K19 A20 B20 G20 G21 C20 D20 F21 F22 A21 B21 F16 E16 C26 D26 B27 C27 D27 E27 D21 E21 H20 J20 A22 B22 J22 J23 C22 D22 J21 H22 A23 B23 E22 E23 C23 D23 K22 K21 A24 B24 G23 H23 D24 E24 K23 K24 A25 B25 C28 D28 C25 D25 G26 G25 B28 A28 A26 A27 A29 A30 H26 H25 A31 B31 C29 C30 GND GND GND GND GND 39 40 41 42 43 2 4 6 100NF-0603SMT 100NF-0603SMT 58 1 3 5 100NF-0603SMT 100NF-0603SMT D PT74A/PT92A PT74B/PT92B PT76A/PT94A/PCLKT1_0 PT76B/PT94B/PCLKC1_0 PT77A/PT95A PT77B/PT95B PT79A^/PT97A^ PT79B/PT97B PT80A/PT98A PT80B/PT98B PT82A/PT100A PT82B/PT100B PT83A/PT101A PT83B/PT101B PT85A/PT103A PT85B/PT103B PT86A/PT104A PT86B/PT104B PT88A^/PT106A^ PT88B/PT106B PT89A/PT107A PT89B/PT107B PT91A/PT109A PT91B/PT109B PT95A/PT113A PT95B/PT113B PT97A^/PT115A^ PT97B/PT115B PT98A/PT116A PT98B/PT116B NC/PT118A NC/PT118B NC/PT157A NC/PT157B NC/PT158A NC/PT158B NC/PT161A NC/PT161B PT101A/PT119A PT101B/PT119B PT103A/PT121A PT103B/PT121B PT104A/PT122A PT104B/PT122B PT106A^/PT124A^ PT106B/PT124B PT107A/PT125A PT107B/PT125B PT109A/PT127A PT109B/PT127B PT110A/PT128A PT110B/PT128B PT112A/PT130A PT112B/PT130B PT113A/PT131A PT113B/PT131B PT115A^/PT133A^ PT115B/PT133B PT116A/PT134A PT116B/PT134B PT118A/PT136A PT118B/PT136B PT119A/PT137A PT119B/PT137B PT121A/PT139A PT121B/PT139B PT122A/PT140A PT122B/PT140B PT124A^/PT142A^ PT124B/PT142B PT125A/PT143A PT125B/PT143B PT127A/PT145A PT127B/PT145B PT128A/PT164A PT128B/PT164B PT130A/PT166A PT130B/PT166B PT131A/PT167A PT131B/PT167B PT133A^/PT169A^ PT133B/PT169B PT134A/PT170A PT134B/PT170B PT136A/PT172A/VREF1_1 PT136B/PT172B/VREF2_1 A B C D LatticeECP3 I/O Protocol Board – Revision C User’s Guide Figure 35. Prototype & Test 59 A B C D 5 USB 2.0 to RS232 5 USB 2.0 to RS232 USB_CONN_B TH_TYPE_B ECP3 -150 density only DTR# RTS# RS232_1 RS232_2 RI# RS232_4 CTS# RS232_7 1 4 1 2 3 4 5 6 C255 0.01uF TP54 J62 DI GND DNI FB10 C259 1 FT232R GPIO3 GPIO2 SLEEP# CTS# DCD# DSR# VCC3I GND RI# RXD VCCIO RTS# DTR# TXD U16 28 R300 1.0KR VCC3O GND 5_0V GND CBUS1 CBUS0 GND C261 47pF** 15 16 17 18 19 20 21 22 23 24 25 26 27 3 3 GND R299 10.0KR R298 4.7KR GND C229 0.1uF GND Valid VCCIO1 settings are 2_5V or 3_3V to permit RS232 operation Draws 15ma typical from 5.0v Using the internal oscillator, the VCC pin must be > 4.0v GND 5_0V USBDP USBDM VCC3O GND RESET# VCC5I GND GPIO0 GPIO1 AVCC AGND TEST OSCI OSCO [14] C260 47pF** 2 RS232_[0..10] 10nF ** GND GND 14 GND 13 RS232_9 TXDEN# 12 11 10 9 8 7 6 5 4 3 2 RS232_10 PWREN# SLEEP# DCD# RS232_6 RS232_8 DSR# RS232_5 GND RXD RS232_3 VCCIO_1 TXD RS232_0 RS232_[0..10] 4 TX GND GND 5_0V C254 0.1uF C257 0.1uF GND VCCIO_1 5_0V RX D35 GREEN_LED CR0603 DI R297 470R C258 4.7uF D34 SCHOTTKY V12P10-E3/87A Vishay VCCIO_1 D36 GREEN_LED CR0603 DI R296 470R 3_3V 2 2 Date: Size B Title Friday, March 25, 2011 1 Sheet 17 of 18 ECP3 IO Protocol Eval Board Schematic Project USB 2.0 to RS232 C Rev Lattice Semiconductor Corporation 5555 N.E. Moore Court Hillsboro, Oregon. 97124 1 A B C D LatticeECP3 I/O Protocol Board – Revision C User’s Guide Figure 36. USB 2.0 to RS232 2 Title Lattice Semiconductor Corporation 5555 N.E. Moore Court Hillsboro, Oregon. 97124 1 60 Date: Monday, August 17, 2009 1 Sheet 18 of 18 ECP3 IO Protocol Eval Board Schematic Project Mechanical Drawing C Rev A A Size C B B C 3 2 C 4 3 D 5 4 D Mechanical Drawing 5 LatticeECP3 I/O Protocol Board – Revision C User’s Guide Figure 37. Mechanical Drawing