LFE3-MEZZ-EVN

 HDMI Mezzanine Card – Revision B User’s Guide September 2012 Revision: EB55_01.1  HDMI Mezzanine Card – Revision B User’s Guide Introduction LatticeECP3 Video Protocol Board includes a daughter card connection to support applications that can be implemented using SERDES. This daughter card connection includes three connectors for the signals of a whole SERDES quad, the control/status signals and the power/ground pins. The HDMI Mezzanine Card is a LatticeECP3 Video Protocol Board daughter card designed for demonstrating the Lattice HDMI/DVI solution using LatticeECP3 SERDES. The scope of this user’s guide covers only revision B of the HDMI Mezzanine Card. Please refer to EB52, LatticeECP3 Video Protocol Board Revision C User’s Guide for more information about the LatticeECP3 device connection to the daughter card. As shown in Figure 1, this card uses Single-Link 19-pin HDMI Type-A connectors. If using passive HDMI-to-DVI cables, this card can also be used to support DVI video. Figure 1. HDMI Mezzanine Card Features • Supports two different HDMI/DVI input paths, with or without the cable equalizer • Supports HDMI/DVI output with TMDS level shifter • TOSLINK fiber optic receiving module for S/PDIF audio input • Headers for HPD, CEC controls and the EDID signals • ESD protection devices for both HDMI/DVI inputs and HDMI/DVI outputs Functional Description There are four transmit channels and four receive channels in each of the LatticeECP3 SERDES quads. For implementing a Single Link HDMI or DVI interface, which includes three data channels and one clock channel, all four transmit channels and three receive channels are used. The clock channel on the receive side is connected to the dedicated SERDES differential reference clock pins. Since the common mode voltage of the HDMI/DVI TMDS sig- 2 HDMI Mezzanine Card – Revision B User’s Guide nals is different from the SERDES CML signals, and the TMDS coding scheme maintains the DC balance of the signal, the AC coupling capacitors are used to block the DC component of the driving signal. Figure 2 shows the functional block diagram of the HDMI Mezzanine Card. For validation purposes, this card is designed to include two HDMI/DVI input ports. One of these input paths has a TMDS cable equalizer and the other does not. The signals of both paths will go into the 2-to-1 TMDS MUX, then the AC coupling capacitors to the SERDES input pins. Depending on which pins a shunt is installed on a 3-pin header, one of the two inputs will be selected and the signals will be fed to the SERDES. For meeting the HDMI/DVI’s strict electrical compliance test specification, a TMDS level shifter is added to the output path. This level shifter can be removed if the design does not have this requirement. The ESD protector is added on both the input and output HDMI/DVI ports. Other than the HDMI/DVI, an S/PDIF input interface is also included for bringing in a digital audio stream through the TOSLINK connector. Figure 2. Functional Block Diagram Clock 2 TMDS 2:1 Switch (PI3HDMI1210-A) 4 Gbps 2 Clock 2 Data Pairs 6 Clock 2 AC Coupling ESD Protector Input 1 Data Pairs 6 Data Pairs Clock 2 ESD Protector TMDS Clock TMDS Level Shifter (STHDLS101T) 3.4 Gbps 6 ESD Protector Input 2 6 TMDS Equalizer (STDVE001) 3.4 Gbps Output AC Coupling Data Pairs Regular 100-mil Connector 10 Gbps Mezzanine Connector 6 Data Pairs 6 Clock 2 S/PDIF TORX147 Figure 3 shows the HDMI Mezzanine Card installed on the LatticeECP3 Video Protocol Board. The two cables are the HDMI cables connecting to J1 (HDMI/DVI input) and J3 (HDMI/DVI output) of the daughter card. A 12 mm tall standoff is recommended for securing the HDMI Mezzanine Card on the LatticeECP3 Video Protocol Board through screws. 3 HDMI Mezzanine Card – Revision B User’s Guide Figure 3. HDMI Mezzanine Card Installed on the LatticeECP3 Video Protocol Board Header Settings This section describes the header settings on the HDMI Mezzanine Card. However, since the card uses SERDES quad C when plugging into the LatticeECP3 Video Protocol Board, the VCCOB and the VCCIB of SERDES quad C need to be powered properly. Please make sure shuts are installed on J18 and J22 of the LatticeECP3 Video Protocol Board. As mentioned previously, the selection of the two HDMI/DVI inputs is done by a 3-pin header. Table 1 shows the locations of where the shunt should be installed. Table 1. MUX Selection Control HDMI/DVI Input Shunt Installation on H13 Mode MUX Select J1 Equalized HDMI/DVI Input High Pin 1/Pin 2 J2 Non-Equalized HDMI/DVI Input Low Pin 2/Pin 3 Other than the TMDS clock and data pairs, the HDMI/DVI interface includes CEC, HPD and the DDC clock and data signals. By installing shuts on different locations of the 12 headers, these signals can be selected to be bypassed from the HDMI/DVI input to the HDMI/DVI output, or they can be selected to be connected to the LatticeECP3 FPGA on the LatticeECP3 Video Protocol Board. Figure 4 shows the locations of these 12 headers on the HDMI Mezzanine Card and the signals these headers control. The 12 headers are divided into four groups as shown in Figure 4. Each group includes three headers for controlling one of the four signals. The black square is used to indicate pin 1 of each header. 4 HDMI Mezzanine Card – Revision B User’s Guide Figure 4. Headers for CEC, HDP, S Settings, LatticeECP3 Video Protocol Board J3 (HDMI Out) J3 (HDMI Out) H12, H11, H10, H9 are associated with HDMI Out H12, H11, H10, H9 J2 (HDMI Input 2) J2 (HDMI Input 2) H8, H7, H6, H5 are associated with HDMI Input 2 H6, H5 H8, H7 J1 (HDMI Input 1) J1 (HDMI Input 1) TOSLINK (S/PDIF) TOSLINK (S/PDIF) H4, H3, H2, H1 are associated with HDMI Input 1 H4, H3, H2, H1 H10, H6, H2 are for SDA control J3 (HDMI Out) H9, H5, H1 are for SCL control J3 (HDMI Out) J2 (HDMI Input 2) J2 (HDMI Input 2) J1 (HDMI Input 1) J1 (HDMI Input 1) TOSLINK (S/PDIF) TOSLINK (S/PDIF) H12, H8, H4 are for CEC control H11, H7, H3 are for HPD control Figure 5 is a conceptual connection of the header connections. This applies to all four signals. An example of the connection is shown in Figure 6. In this example, the shunts are installed on pin1/pin 2 of H9 ~ H12 and pin2/pin3 of H1 ~ H4. This will bypass the four signals between J1 and J3. 5 HDMI Mezzanine Card – Revision B User’s Guide Figure 5. Conceptual Connection for Headers H1 to H12 H12, H11, H10, H9 J3 (HDMI Out) LatticeECP3 FPGA H8, H7, H6, H5 J2 (HDMI Input 2) TMDS Equalizer H4, H3, H2, H1 J1 (HDMI Input 1) Figure 6. Example for Bypassing CEC, HPD, SDA, SCL Between J1 and J3 H12, H11, H10, H9 J3 (HDMI Out) LatticeECP3 FPGA H8, H7, H6, H5 J2 (HDMI Input 2) TMDS Equalizer H4, H3, H2, H1 J1 (HDMI Input 1) Technical Support Assistance Hotline: 1-800-LATTICE (North America) +1-503-268-8001 (Outside North America) e-mail: techsupport@latticesemi.com Internet: www.latticesemi.com Revision History Date Version Change Summary September 2010 01.0 Initial release. September 2012 01.1 Added Appendix B. Hardware Variants. Updated document with new corporate logo. © 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 6 HDMI Mezzanine Card – Revision B User’s Guide Appendix A. Schematic 7 8 HDMI Equalizer TMDS Switch HDMI Output Port 7 8 9 3 2 Internal Version 0.02 1 Tel: 91-44-2253 7900 Fax: 91-44-2252 3514 www.gdatech.com C D Date: B Size Title Tuesday, March 02, 2010 Document Number 1 Sheet GDA09CB004B COVER PAGE GDA Technologies Ltd, L & T Infotech Park, Mount Poonamallee Road, Manapakkam, Ch 89 1 of 11 Rev B A Board Accessories I2C, HPD, CEC Selection 6 B To B Connectors and Audio Input HDMI Input Ports 5 11 Power Scheme 4 10 Block Diagram 3 Description Cover Page Revision History 1 2 Page HDMI MEZZANINE CARD - LATTICE SEMICONDUCTOR CORPORATION 2 A 4 3 COVER PAGE B 5 4 B C D 5 HDMI Mezzanine Card – Revision B User’s Guide Figure 7. Cover Page 9 A B C D 5 5 B A 4 Revision 4 15-Jun-2009 17-Jun-2009 24-Jun-2009 0.10 0.11 0.12 3 11-Jun-2009 0.09 2 'GDA confidential' is removed from all pages as per customer feedback 2-Mar-2010 0.02 Date: B Size Title 1 1 Sheet GDA09CB004B 2 of 11 Rev B Tel: 91-44-2253 7900 Fax: 91-44-2252 3514 www.gdatech.com REVISION HISTORY Tuesday, March 02, 2010 Document Number GDA Technologies Ltd, L & T Infotech Park, Mount Poonamallee Road, Manapakkam, Ch 89 Internal Version 0.02 Clock cleaner is removed and eight 50ohms pullup resistors are added for the HDMI output port as per customer requirement 11-Feb-2010 0.01 Customer Feedbacks implemented on decoupling caps for U3, U8 Customer Feedbacks implemented Customer Feedbacks implemented Version change after customer modification of schematics for HDMI Equivalizer Customer Feedbacks implemented Customer Feedbacks implemented Pin mapping table modified. Pullups added for output signals from ECP3 board. SPDIF data assigned to MZ_CTRL13 Pin Mapping table added for Mezzanine and control signal connectors 09-Jun-2009 03-Jun-2009 0.06 10-Jun-2009 02-Jun-2009 0.05 Single Ended signals swapping done at control signal connector for layout feasibility HDMI signals swapping done for layout feasibility 0.08 29-May-2009 0.04 2 Jumper options for DDC, HPD and CEC lines modified Initial release Description 0.07 27-May-2009 20-May-2009 0.03 18-May-2009 0.02 Release Date 0.01 Verison 3 REVISION HISTORY A B C D HDMI Mezzanine Card – Revision B User’s Guide Figure 8. Revision History 3 Internal Version 0.02 1 Tel: 91-44-2253 7900 Fax: 91-44-2252 3514 www.gdatech.com 10 4 3 Date: B Size Title Tuesday, March 02, 2010 Document Number 1 Sheet GDA09CB004B BLOCK DIAGRAM 3 of 11 Rev B A A GDA Technologies Ltd, L & T Infotech Park, Mount Poonamallee Road, Manapakkam, Ch 89 B B 5 C 2 2 C BLOCK DIAGRAM D 4 D 5 HDMI Mezzanine Card – Revision B User’s Guide Figure 9. Block Diagram Internal Version 0.02 1 Tel: 91-44-2253 7900 Fax: 91-44-2252 3514 www.gdatech.com 11 4 3 Date: B Size Title Tuesday, March 02, 2010 Document Number 1 Sheet GDA09CB004B POWER SCHEME 4 of 11 Rev B A A GDA Technologies Ltd, L & T Infotech Park, Mount Poonamallee Road, Manapakkam, Ch 89 B B 5 C 2 2 C POWER SCHEME 3 D 4 D 5 HDMI Mezzanine Card – Revision B User’s Guide Figure 10. Power Scheme A B C D DDC/CEC GROUND +5V POWER HOT PLUG DETECT 18 19 NC 14 17 CEC 13 SDA TMDS CLOCK- 12 16 TMDS CLOCK SHIELD SCL TMDS CLOCK+ 11 15 TMDS DATA0- 10 TMDS DATA1- 6 9 TMDS DATA1 SHIELD 5 TMDS DATA0 SHIELD TMDS DATA1+ 4 8 TMDS DATA2- 3 TMDS DATA0+ TMDS DATA2 SHIELD 7 TMDS DATA2+ 2 NAME 1 5 PIN NO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 500254_1927 20 21 22 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 J1SDA J1SCL J2SDA J2SCL D1 B340LA-13-F 51E SCL_HDMI1 51E SDA_HDMI1 51E SCL_HDMI2 51E SDA_HDMI2 HPD_HDMI2 R69 R70 HDMI2_CLKCEC_HDMI2 HDMI2_DATA0HDMI2_CLK+ HDMI2_DATA1HDMI2_DATA0+ HDMI2_DATA2HDMI2_DATA1+ HDMI2_DATA2+ D2 B340LA-13-F HPD_HDMI1 R67 R68 HDMI1_CLKCEC_HDMI1 HDMI1_DATA0HDMI1_CLK+ HDMI1_DATA1HDMI1_DATA0+ HDMI1_DATA2HDMI1_DATA1+ HDMI1_DATA2+ VDD_5V0_HDMI2 1 3 4 3 26 25 24 C28 0.1uF 10V 29 28 27 HDMI2_DATA0+ C2 0.1uF 10V CEC_HDMI2 SCL_HDMI2 SDA_HDMI2 HPD_HDMI2 HDMI2_CLK- HDMI2_CLK+ HDMI2_DATA0- HDMI2_DATA1- 23 22 21 20 26 25 24 32 31 30 HDMI2_DATA1+ HDMI2_DATA2- 35 34 33 38 37 36 HDMI2_DATA2+ C1 0.1uF 10V CEC_HDMI1 SCL_HDMI1 SDA_HDMI1 HPD_HDMI1 HDMI1_CLK- HDMI2_ESDBYPASS 29 28 27 HDMI1_CLK+ HDMI1_DATA0- 23 22 21 20 32 31 30 HDMI1_DATA0+ HDMI1_DATA1- HDMI1_DATA2HDMI1_DATA1+ 38 37 36 35 34 33 C27 0.1uF 10V HDMI1_ESDBYPASS HDMI1_DATA2+ HDMI INPUT PORTS Note ---------The 5V Supply of the HDMI Input connectors are not used in the Mezz card since there is no EDID EEPROM available in the card 20 21 22 23 J2 HDMI Input -2 1 500254_1927 20 21 22 23 TP2 Test_Pad 20 21 22 23 J1 HDMI Input -1 1 2 27K CEC1_PULL 1 R1 2 CEC2_PULL 1 27K R5 TP1 Test_Pad 2K R2 2K R6 VDD_5V0_HDMI1 2K R3 2K 4 1K R4 1K R7 12 R8 5 2 CM2021 CE_REMOTE_OUT DDC_CLK_OUT DDC_DAT_OUT HOTPLUG_DET_OUT TMDS_CK2+ TMDS_GND5 TMDS_CK2- TMDS_D0+_2 TMDS_GND6 TMDS_D0-_2 TMDS_D1+_2 TMDS_GND7 TMDS_D1-_2 TMDS_D2+_2 TMDS_GND8 TMDS_D2-_2 NC ESD_BYP GND2 U2 CM2021 CE_REMOTE_OUT DDC_CLK_OUT DDC_DAT_OUT HOTPLUG_DET_OUT TMDS_CK2+ TMDS_GND5 TMDS_CK2- TMDS_D0+_2 TMDS_GND6 TMDS_D0-_2 TMDS_D1+_2 TMDS_GND7 TMDS_D1-_2 TMDS_D2+_2 TMDS_GND8 TMDS_D2-_2 NC ESD_BYP GND2 U1 2 1 2 3 16 17 18 19 13 14 15 10 11 12 7 8 9 4 5 6 1 2 3 VDD_5V0 16 17 18 19 13 14 15 10 11 12 7 8 9 4 5 6 VDD_3V3 VDD_3V3 Date: B Size Title CEC_HDMI_IN2 SCL_HDMI_IN2 SDA_HDMI_IN2 HPD_HDMI_IN2 HDMI2_CLK- HDMI2_CLK+ HDMI2_DATA0- HDMI2_DATA0+ HDMI2_DATA1- HDMI2_DATA1+ HDMI2_DATA2- HDMI2_DATA2+ CEC_HDMI_IN1 SCL_HDMI_IN1 SDA_HDMI_IN1 HPD_HDMI_IN1 HDMI1_CLK- HDMI1_CLK+ HDMI1_DATA0- HDMI1_DATA0+ HDMI1_DATA1- HDMI1_DATA1+ HDMI1_DATA2- HDMI1_DATA2+ Tuesday, March 02, 2010 Document Number HDMI INPUT PORTS 1 Sheet GDA09CB004B [7] [6] [6] [6] [6] [8] [8] [8] [8] [8] [8] [6] [6] [6] [6] [7] [8] [8] [7] [7] 5 of 11 Rev B Tel: 91-44-2253 7900 Fax: 91-44-2252 3514 www.gdatech.com CEC_HDMI_IN2 SCL_HDMI_IN2 SDA_HDMI_IN2 HPD_HDMI_IN2 HDMI2_CLK- HDMI2_CLK+ HDMI2_DATA0- HDMI2_DATA0+ HDMI2_DATA1- HDMI2_DATA1+ HDMI2_DATA2- [7] [7] [7] [7] HDMI2_DATA2+ CEC_HDMI_IN1 SCL_HDMI_IN1 SDA_HDMI_IN1 HPD_HDMI_IN1 HDMI1_CLK- HDMI1_CLK+ HDMI1_DATA0- HDMI1_DATA0+ HDMI1_DATA1- HDMI1_DATA1+ HDMI1_DATA2- HDMI1_DATA2+ GDA Technologies Ltd, L & T Infotech Park, Mount Poonamallee Road, Manapakkam, Ch 89 Internal Version 0.02 CE_REMOTE_IN DDC_CLK_IN DDC_DAT_IN HOTPLUG_DET_IN TMDS_CK1+ TMDS_GND4 TMDS_CK1- TMDS_D0+_1 TMDS_GND3 TMDS_D0-_1 TMDS_D1+_1 TMDS_GND2 TMDS_D1-_1 TMDS_D2+_1 TMDS_GND1 TMDS_D2-_1 5V_SUPPLY LV_SUPPLY GND1 CE_REMOTE_IN DDC_CLK_IN DDC_DAT_IN HOTPLUG_DET_IN TMDS_CK1+ TMDS_GND4 TMDS_CK1- TMDS_D0+_1 TMDS_GND3 TMDS_D0-_1 TMDS_D1+_1 TMDS_GND2 TMDS_D1-_1 TMDS_D2+_1 TMDS_GND1 TMDS_D2-_1 5V_SUPPLY LV_SUPPLY GND1 VDD_5V0 1 A B C D HDMI Mezzanine Card – Revision B User’s Guide Figure 11. HDMI Input Ports 13 5 HPD_HDMI_IN1 4 3 2 1 H3 3 2 1 1x3 H7 3 2 1 SDA_HDMI_IN1 SDA_HDMI_IN2 SDA_HDMI1_EQ_EXT SDA_HDMIOUT_LEVSHIFT SDA_HDMIOUT_CM2020INT JMP_SDA 3 3 2 1 3 2 1 3 2 1 H2 3 2 1 1x3 H6 3 2 1 1x3 H10 3 2 1 SCL_HDMI_IN1 SCL_HDMI_IN2 SCL_HDMI1_EQ_EXT SCL_HDMIOUT_LEVSHIFT SCL_HDMIOUT_CM2020INT JMP_SCL 2 3 2 1 3 2 1 3 2 1 H1 3 2 1 1x3 H5 3 2 1 1x3 H9 3 2 1 1x3 Internal Version 0.02 CEC_HDMIOUT_CM2020INT CEC_HDMIOUT_MEZZCONN HPD_HDMIOUT_CM2020INT HPD_HDMIOUT_LEVSHIFT SDA_HDMIOUT_CM2020INT SDA_HDMIOUT_LEVSHIFT SCL_HDMIOUT_CM2020INT SCL_HDMIOUT_LEVSHIFT CEC_HDMI1_EQ_EXT CEC_HDMI_IN1 CEC_HDMI_IN2 HPD_HDMI1_EQ_EXT HPD_HDMI_IN1 HPD_HDMI_IN2 SDA_HDMI1_EQ_EXT SDA_HDMI_IN1 SDA_HDMI_IN2 SCL_HDMI1_EQ_EXT SCL_HDMI_IN1 SCL_HDMI_IN2 Tel: 91-44-2253 7900 Fax: 91-44-2252 3514 www.gdatech.com [10] [11] [10] [10] [10] [10] CEC_HDMIOUT_CM2020INT CEC_HDMIOUT_MEZZCONN HPD_HDMIOUT_CM2020INT HPD_HDMIOUT_LEVSHIFT [10] [10] [7] SDA_HDMIOUT_CM2020INT SDA_HDMIOUT_LEVSHIFT SCL_HDMIOUT_CM2020INT SCL_HDMIOUT_LEVSHIFT [7] [7] [7] CEC_HDMI1_EQ_EXT CEC_HDMI_IN1 [5] CEC_HDMI_IN2 [5] HPD_HDMI1_EQ_EXT HPD_HDMI_IN1 [5] HPD_HDMI_IN2 [5] SDA_HDMI1_EQ_EXT SDA_HDMI_IN1 [5] SDA_HDMI_IN2 [5] SCL_HDMI1_EQ_EXT SCL_HDMI_IN1 [5] SCL_HDMI_IN2 [5] 1 C D Date: B Size Title Tuesday, March 02, 2010 Document Number 1 Sheet GDA09CB004B 6 of I2C, HPD, CEC SELECTION GDA Technologies Ltd, L & T Infotech Park, Mount Poonamallee Road, Manapakkam, Ch 89 11 Rev B A H4 3 2 1 1x3 H8 3 2 1 1x3 3 2 1 HPD_HDMI_IN2 HPD_HDMI1_EQ_EXT 3 2 1 1x3 3 2 1 H11 HPD_HDMIOUT_LEVSHIFT HPD_HDMIOUT_CM2020INT JMP_HPD H12 3 2 1 1x3 2 A 3 2 1 3 2 1 3 2 1 1x3 HPD, CEC, I2C SELECTION 3 B CEC_HDMI_IN1 CEC_HDMI_IN2 CEC_HDMI1_EQ_EXT CEC_HDMIOUT_MEZZCONN CEC_HDMIOUT_CM2020INT JMP_CEC 1x3 4 B C D 5 HDMI Mezzanine Card – Revision B User’s Guide Figure 12. I2C, HPD, CEC Selection 14 A B C [11] [11] HDMI_EQ_BOOST1 HDMI_EQ_BOOST2 OE#_HDMI_EQUALIZER CEC_HDMI1_EQ_EXT HPD_HDMI1_EQ_EXT DDC_EN_EQUALIZER DDC_EN_EQUALIZER CD60 0.01uF 0.01uF 0.01uF 0.01uF CD62 4 0.01uF CD63 CEC_HDMI1_EQ_EXT CD59 PRE_EQUALIZER SDA_HDMI1_EQ_EXT OE#_HDMI_EQUALIZER SCL_HDMI1_EQ_INT SDA_HDMI1_EQ_INT SCL_HDMI1_EQ_EXT HPD_HDMI1_EQ_INT CD61 HDMI1_DATA2+ HDMI1_DATA2- [5] [5] HPD_HDMI1_EQ_EXT VDD_3V3 VDD_3V3 HDMI1_DATA1+ HDMI1_DATA1- [5] [5] CEC_HDMI1_EQ_INT 5 VDD_3V3 [11] [6] [6] [11] HDMI1_DATA0+ HDMI1_DATA0- [5] [5] SCL_HDMI1_EQ_EXT SDA_HDMI1_EQ_EXT HDMI1_CLK+ HDMI1_CLK- [5] [5] 4 HDMI_EQ_BOOST2 HDMI_EQ_BOOST1 47K R65 47K R64 47K R13 47K R12 47K R11 47K R10 47K R63 47K R66 4.7K R62 4.7K R15 4.7K R14 [6] [6] 4.7K nm R56 D 4.7K nm R57 0.01uF CD64 0.01uF CD65 0.01uF CD66 VDD_3V3 STDVE001A CD3 0.1uF 10V CD4 1000pF 50V 3 De-Caps for HDMI Equalizer CD2 1000pF 50V VDD_3V3 EQ_BOOST1 EQ_BOOST2 OE# CEC_IO HPD_EXT DDC_EN SCL_EXT SDA_EXT IN_D4+ IN_D4- IN_D3+ IN_D3- IN_D2+ IN_D2- IN_D1+ IN_D1- U3 CD1 0.1uF 10V 34 35 HDMI_EQ_BOOST1 HDMI_EQ_BOOST2 CEC_HDMI1_EQ_EXT 25 7 3 HPD_HDMI1_EQ_EXT OE#_HDMI_EQUALIZER 32 48 47 HDMI1_DATA2+ HDMI1_DATA2- DDC_EN_EQUALIZER 45 44 HDMI1_DATA1+ HDMI1_DATA1- 9 8 42 41 HDMI1_DATA0+ HDMI1_DATA0- SCL_HDMI1_EQ_EXT SDA_HDMI1_EQ_EXT 39 38 HDMI1_CLK+ HDMI1_CLK- 3 B3 CD5 0.1uF 10V CEC_HDMI1_EQ_INT 6 CD6 1000pF 50V 3000mA CD7 0.1uF 10V 2 B1 AGND CD9 0.1uF 10V HPD_HDMI1_EQ_INT 30 4 CD8 1000pF 50V SCL_HDMI1_EQ_INT SDA_HDMI1_EQ_INT 28 29 AGND HDMI_EQ_DATA2+ HDMI_EQ_DATA2- 13 14 R9 4.70K 1% HDMI_EQ_DATA1+ HDMI_EQ_DATA1- 16 17 REXT_EQ HDMI_EQ_DATA0+ HDMI_EQ_DATA0- 19 20 10 HDMI_EQ_CLK+ HDMI_EQ_CLK- 2 22 23 STDVE001A REXT PRE CEC_IO_INT HPD_INT SCL_INT SDA_INT OUT_D4+ OUT_D4- OUT_D3+ OUT_D3- OUT_D2+ OUT_D2- OUT_D1+ OUT_D1- HDMI EQUALIZER 11 VDD_EXT 26 VDD_INT 2 15 21 33 40 46 VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 1 5 12 18 24 27 31 36 37 43 E_PAD 49 5 CD10 1000pF 50V 3000mA PRE_EQUALIZER [11] CD12 1000pF 50V Date: B Size Title CD13 0.1uF 10V CD14 1000pF 50V Tuesday, March 02, 2010 Document Number 1 Sheet GDA09CB004B CD16 1000pF 50V 7 of 11 Rev B Tel: 91-44-2253 7900 Fax: 91-44-2252 3514 www.gdatech.com CD15 0.1uF 10V HDMI EQUALIZER GDA Technologies Ltd, L & T Infotech Park, Mount Poonamallee Road, Manapakkam, Ch 89 Internal Version 0.02 [11] [11] CD11 0.1uF 10V CEC_HDMI1_EQ_INT HPD_HDMI1_EQ_INT [11] [11] [8] [8] [8] [8] [8] [8] [8] [8] SCL_HDMI1_EQ_INT SDA_HDMI1_EQ_INT HDMI_EQ_DATA2+ HDMI_EQ_DATA2- HDMI_EQ_DATA1+ HDMI_EQ_DATA1- HDMI_EQ_DATA0+ HDMI_EQ_DATA0- HDMI_EQ_CLK+ HDMI_EQ_CLK- 1 A B C D HDMI Mezzanine Card – Revision B User’s Guide Figure 13. HDMI Equalizer 15 A B C D HDMI_EQ_DATA2+ HDMI_EQ_DATA2HDMI_EQ_DATA1+ HDMI_EQ_DATA1- [7] [7] [7] [7] 5 ----> TMDS Switch Output 4 Equalized HDMI Channel Un Equalized HDMI Channel ----> TMDS Switch Output 44 43 42 41 39 38 37 36 35 34 33 32 HDMI2_DATA0+ HDMI2_DATA0HDMI2_CLK+ HDMI2_CLK- HDMI_EQ_DATA2+ HDMI_EQ_DATA2HDMI_EQ_DATA1+ HDMI_EQ_DATA1HDMI_EQ_DATA0+ HDMI_EQ_DATA0HDMI_EQ_CLK+ HDMI_EQ_CLK- 4.7K TMDS_SW_0B2 4.7K TMDS_SW_1B2 4.7K TMDS_SW_EN# 4.7K TMDS_SW_IN R19 R21 R22 R23 23 21 28 26 29 27 CD18 1000pF 50V CD27 0.1uF 10V CD28 1000pF 50V VDD_5V0 CD17 0.1uF 10V VDD_3V3 VDD_3V3 VDD_5V0 PI3HDMI1210-A HDMI SWITCH D0+ D0- CD20 1000pF 50V 3 CD21 0.1uF 10V CD22 1000pF 50V 3 4 2 16 24 18 20 11 12 9 10 5 6 CD23 0.1uF 10V DATA0+ DATA0- DATA1+ DATA1- DATA2+ DATA2- 0.1uF 0.1uF C15 C14 TMDS_SW_CP1 TMDS_SW_CP2 TMDS_SW_CP3 CD24 1000pF 50V C10 0.1uF 10V 0.1uF 0.1uF C7 C8 CD25 0.1uF 10V CD26 1000pF 50V 2 HDMIIN_CLEANED_CLK+ HDMIIN_CLEANED_CLK- HDMIIN_DATA0+ HDMIIN_DATA0- HDMIIN_DATA1+ HDMIIN_DATA1- HDMIIN_DATA2+ HDMIIN_DATA2- C11 0.1uF 10V 4.7K 4.7K 0.1uF 0.1uF 0.1uF 0.1uF C5 C6 C3 C4 TMDS_SW_A0 R18 TMDS_SW_A1 R20 C9 0.1uF 10V 2 [11] [11] [11] [11] [11] [11] [11] [11] Date: B Size HDMIIN_CLK- R79 Tuesday, March 02, 2010 Document Number 1 Sheet GDA09CB004B TMDS SWITCH GDA Technologies Ltd, L & T Infotech Park, Mount Poonamallee Road, Manapakkam, Ch 89 Internal Version 0.02 Title R77 R78 R76 HDMIIN_CLK+ DATA0+ R75 R74 R73 R72 DATA0- DATA1- DATA1+ DATA2- DATA2+ 1 51 51 51 51 51 51 51 51 VDD_3V3 8 of 11 Rev B Tel: 91-44-2253 7900 Fax: 91-44-2252 3514 www.gdatech.com NOTE: Place resistors closer to AC coupling caps HDMIIN_CLEANED_CLK+ HDMIIN_CLEANED_CLK- HDMIIN_DATA0+ HDMIIN_DATA0- HDMIIN_DATA1+ HDMIIN_DATA1- HDMIIN_DATA2+ HDMIIN_DATA2- NOTE: Place capacitors nearer to J4 as close as possible HDMIIN_CLK+ HDMIIN_CLK- PI3HDMI1210-A CP1 CP2 CP3 A0 A1 CLK+ CLK- D2+ D2- D1+ D1- De-Caps for TMDS Switch EN# IN 0B2 1B2 0B1 1B1 SEL CLK+B CLK-B D2+B D2-B D1+B D1-B D0+B D0-B 3 TMDS SWITCH CLK+A CLK-A D2+A D2-A D1+A D1-A D0+A D0-A U4 CD19 0.1uF 10V Note --------Side Band Channel Disabled 4.7K TMDS_SW_0B1 4.7K TMDS_SW_1B1 8 46 45 HDMI2_DATA1+ HDMI2_DATA1- TMDSSWITCH_CHAN_SEL 48 47 HDMI2_DATA2+ HDMI2_DATA2- R16 R17 HDMI_EQ_CLK+ HDMI_EQ_CLK- VDD_3V3 [7] [7] HDMI_EQ_DATA0+ HDMI_EQ_DATA0- HDMI2_CLK+ HDMI2_CLK- [5] [5] [7] [7] HDMI2_DATA0+ HDMI2_DATA0- [5] [5] SEL Pin = High HDMI Input Channel Select 1 2 3 VDD_3V3 HDMI2_DATA1+ HDMI2_DATA1- [5] [5] SEL Pin = Low 1x3 1 2 3 H13 HDMI2_DATA2+ HDMI2_DATA2- [5] [5] 4 22 VDD5V 1 7 14 31 40 VDD3V3_1 VDD3V3_2 VDD3V3_3 VDD3V3_4 VDD3V3_5 GND1 GND2 GND3 GND4 GND5 GND6 13 15 17 19 25 30 5 A B C D HDMI Mezzanine Card – Revision B User’s Guide Figure 14. TMDS Switch A B C CD42 0.1uF 10V VDD_3V3 CD51 0.1uF 10V VDD_3V3 HDMIOUT_DATA2+ HDMIOUT_DATA2- [11] [11] CD43 1000pF 50V CD52 1000pF 50V [11] [11] [11] HDMIOUT_DATA1+ HDMIOUT_DATA1- VDD_3V3 8 SDA_HDMIOUT_MEZZCONN CD45 1000pF 50V 5 STHDLS101T VDD_3V3 B4 TMDSOUT_DATA2+ TMDSOUT_DATA2- HPD_HDMIOUT_LEVSHIFT SCL_HDMIOUT_LEVSHIFT SDA_HDMIOUT_LEVSHIFT REXT_HDMI_LEVSHIFT 13 14 30 28 29 6 3000mA VDD_3V3 TMDSOUT_DATA1+ TMDSOUT_DATA1- 16 17 STHDLS101T REXT SDA_SINK SCL_SINK HPD_SINK OUT_D4+ OUT_D4- OUT_D3+ OUT_D3- TMDSOUT_DATA0+ TMDSOUT_DATA0- 19 20 CD55 0.1uF 10V CD56 1000pF 50V CD46 0.1uF 10V CD47 1000pF 50V CD48 0.1uF 10V CD49 1000pF 50V CD58 1000pF 50V 4 HPD_HDMIOUT_CM2020INT HPD_HDMIOUT_MEZZCONN CD57 0.1uF 10V SDA_HDMIOUT_CM2020INT SCL_HDMIOUT_MEZZCONN CD68 0.01uF CD67 0.01uF 0.01uF CD69 0.01uF CD70 CEC_HDMIOUT_CM2020INT SCL_HDMIOUT_CM2020INT SDA_HDMIOUT_CM2020INT HPD_HDMIOUT_CM2020INT HPD_HDMIOUT_LEVSHIFT SCL_HDMIOUT_LEVSHIFT SDA_HDMIOUT_LEVSHIFT [6] [6] [6] 0.01uF CD71 0.01uF CD72 0.01uF CD73 CEC_HDMIOUT_CM2020INT SCL_HDMIOUT_CM2020INT SDA_HDMIOUT_CM2020INT HPD_HDMIOUT_CM2020INT HPD_HDMIOUT_LEVSHIFT SCL_HDMIOUT_LEVSHIFT SDA_HDMIOUT_LEVSHIFT CEC_HDMIOUT_CM2020INT SCL_HDMIOUT_CM2020INT OE#_HDMI_LEV_SHIFT De-Caps for HDMI Level Shifter CD44 0.1uF 10V DDC_EN SDA_SOURCE SCL_SOURCE HPD_SOURCE OE# IN_D4+ IN_D4- IN_D3+ IN_D3- OUT_D2+ OUT_D2- OUT_D1+ OUT_D1- SDA_HDMIOUT_MEZZCONN De-Caps for HDMI Level Shifter CD54 1000pF 50V IN_D1+ IN_D1IN_D2+ IN_D2- HDMIOUT_DDC_EN 32 9 SCL_HDMIOUT_MEZZCONN HDMIOUT_DDC_EN 7 HPD_HDMIOUT_MEZZCONN OE#_HDMI_LEV_SHIFT 25 ST_HDMIOUT_DATA2+ 48 ST_HDMIOUT_DATA2- 47 ST_HDMIOUT_DATA1+ 45 ST_HDMIOUT_DATA1- 44 De-Caps for HDMI Level Shifter HDMIOUT_DDC_EN CD53 0.1uF 10V [11] SDA_HDMIOUT_MEZZCONN SCL_HDMIOUT_MEZZCONN HPD_HDMIOUT_MEZZCONN OE#_HDMI_LEV_SHIFT 3.3uF 3.3uF C23 C24 HDMIOUT_DATA2+ HDMIOUT_DATA2- [11] 3.3uF 3.3uF C21 C22 HDMIOUT_DATA1+ HDMIOUT_DATA1- ST_HDMIOUT_DATA0+ 42 ST_HDMIOUT_DATA0- 41 4.7K R49 [11] [11] 3.3uF 3.3uF C19 C20 HDMIOUT_DATA0+ HDMIOUT_DATA0- 4.7K R50 HDMIOUT_DATA0+ HDMIOUT_DATA0- TMDSOUT_DATACLK+ TMDSOUT_DATACLK- 22 23 3 [6] [6] [6] [6] R71 nm 4.7K ANALOG2 R42 4.7K 10 4.7K R51 HDMIOUT_CLK+ HDMIOUT_CLK- 39 38 ANALOG2 4.7K R60 [11] [11] ST_HDMIOUT_CLK+ ST_HDMIOUT_CLK- FUNCTION1 FUNCTION2 FUNCTION3 FUNCTION4 4.7K R61 [11] [11] 3.3uF 3.3uF C16 C17 HDMIOUT_CLK+ HDMIOUT_CLK- 3 4 34 35 U8 2 11 15 21 26 33 40 46 VCC3V3_1 VCC3V3_2 VCC3V3_3 VCC3V3_4 VCC3V3_5 VCC3V3_6 VCC3V3_7 VCC3V3_8 GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 1 5 12 18 24 27 31 36 37 43 47K R48 D 47K R46 VDD_3V3 47K R45 EPAD 49 47K R47 3 0.01uF CD74 nm TMDS CLOCK SHIELD TMDS CLOCKCEC 12 13 SCL SDA DDC/CEC GROUND +5V POWER HOT PLUG DETECT 15 16 17 18 19 NC TMDS CLOCK+ 11 14 TMDS DATA0- TMDS DATA0 SHIELD 10 TMDS DATA0+ 8 9 TMDS DATA17 TMDS DATA1 SHIELD 5 6 TMDS DATA2TMDS DATA1+ 4 TMDS DATA2 SHIELD TMDS DATA2+ NAME 2 TMDS_CK2+ TMDS_GND5 TMDS_CK2- TMDS_D0+_2 TMDS_GND6 TMDS_D0-_2 TMDS_D1+_2 TMDS_GND7 TMDS_D1-_2 TMDS_D2+_2 TMDS_GND8 TMDS_D2-_2 5V_OUT ESD_BYP GND2 TMDSOUT_DATACLKCEC_OUT Date: B Size Title C26 0.1uF CEC_OUT SCL_OUT SDA_OUT HPD_OUT J3 20 21 22 23 500254_1927 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Tuesday, March 02, 2010 Document Number 1 Sheet GDA09CB004B HDMI OUTPUT PORT 9 of 11 Rev B Tel: 91-44-2253 7900 Fax: 91-44-2252 3514 www.gdatech.com R43 15K TMDSOUT_DATACLK- HDMI Output 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 0.1uF 0.1uF TMDSOUT_DATACLK+ TMDSOUT_DATA0- TMDSOUT_DATA0+ TMDSOUT_DATA1- TMDSOUT_DATA1+ TMDSOUT_DATA2- TMDSOUT_DATA2+ C18 C25 GDA Technologies Ltd, L & T Infotech Park, Mount Poonamallee Road, Manapakkam, Ch 89 Internal Version 0.02 HPD_OUT 1 CM2020_ESDBP VDD_5V0_HDMIOUT TMDSOUT_DATA0TMDSOUT_DATACLK+ TMDSOUT_DATA1TMDSOUT_DATA0+ TMDSOUT_DATA2TMDSOUT_DATA1+ TMDSOUT_DATA2+ 23 22 21 20 26 25 24 29 28 27 32 31 30 35 34 33 38 37 36 VDD_5V0_HDMIOUT CM2020 CE_REMOTE_OUT DDC_CLK_OUT DDC_DAT_OUT HOTPLUG_DET_OUT SCL_OUT SDA_OUT CE_REMOTE_IN DDC_CLK_IN DDC_DAT_IN HOTPLUG_DET_IN TMDS_CK1+ TMDS_GND4 TMDS_CK1- TMDS_D0+_1 TMDS_GND3 TMDS_D0-_1 TMDS_D1+_1 TMDS_GND2 TMDS_D1-_1 TMDS_D2+_1 TMDS_GND1 TMDS_D2-_1 5V_SUPPLY LV_SUPPLY GND1 U7 VDD_5V0_HDMIOUT CEC_HDMIOUT_CM2020INT SCL_HDMIOUT_CM2020INT SDA_HDMIOUT_CM2020INT HPD_HDMIOUT_CM2020INT TMDSOUT_DATACLK- 16 17 18 19 13 14 15 TMDSOUT_DATACLK+ TMDSOUT_DATA0- 10 11 12 7 8 9 4 5 6 1 2 3 TMDSOUT_DATA0+ TMDSOUT_DATA1- TMDSOUT_DATA1+ TMDSOUT_DATA2- 3 2 1 PIN NO R44 4.70K 1% R58 4.70K 1% VDD_3V3 VDD_5V0 TMDSOUT_DATA2+ VDD_3V3 2 4.7K R52 HDMI OUTPUT PORT 27K 4 4.7K R53 16 R54 5 A B C D HDMI Mezzanine Card – Revision B User’s Guide Figure 15. HDMI Output Port A B C D [10] [7] 5 HPD_HDMIOUT_MEZZCONN HPD_HDMI1_EQ_INT [8] HDMIIN_DATA0+ [8] HDMIIN_DATA0[8] HDMIIN_DATA1+ [8] HDMIIN_DATA1[8] HDMIIN_DATA2+ [8] HDMIIN_DATA2[9] HDMIIN_CLEANED_CLK+ [9] HDMIIN_CLEANED_CLK- [10] SDA_HDMIOUT_MEZZCONN [10] HDMIOUT_DDC_EN [7] OE#_HDMI_EQUALIZER [7] SDA_HDMI1_EQ_INT [7] HDMI_EQ_BOOST1 1 3 5 7 9 11 13 15 17 19 H16 2 4 6 8 10 12 14 16 18 20 2x10 2 4 6 8 10 12 14 16 18 20 S/PDIF_DATA 1 2 3 4 5 6 7 8 9 10 11 12 J4 13 14 15 16 17 18 19 20 21 22 23 24 0750030005 13 14 15 16 17 18 19 20 21 22 23 24 Mezzanine Card Connector 1 2 3 4 5 6 7 8 9 10 11 12 Control Signal Connector 1 3 5 7 9 11 13 15 17 19 25 26 27 25 26 27 [10] [10] [10] [10] 4 CEC_HDMI1_EQ_INT [7] CEC_HDMIOUT_MEZZCONN HDMIOUT_DATA0+ HDMIOUT_DATA0HDMIOUT_DATA1+ [10] HDMIOUT_DATA1[10] HDMIOUT_DATA2+ HDMIOUT_DATA2HDMIOUT_CLK+ [10] HDMIOUT_CLK[10] SCL_HDMIOUT_MEZZCONN [10] OE#_HDMI_LEV_SHIFT [10] PRE_EQUALIZER [7] SCL_HDMI1_EQ_INT [7] HDMI_EQ_BOOST2 [7] DDC_EN_EQUALIZER [7] [6] 3 3 B TO B CONNECTORS AND AUDIO IN 2 2 L1 H14 1x1 VDD_3V3 NC1 NC2 M1 1 Ground Post 1 3 5 7 9 2 4 6 8 10 2x5 2 4 6 8 10 + - CB7 47uF 20V Date: B Size Title + - VDD_3V3 S/PDIF_DATA 1 Sheet GDA09CB004B 10 of 11 Rev B Tel: 91-44-2253 7900 Fax: 91-44-2252 3514 www.gdatech.com 0E B TO B CONNECTORS AND AUDIO IN Tuesday, March 02, 2010 Document Number GDA Technologies Ltd, L & T Infotech Park, Mount Poonamallee Road, Manapakkam, Ch 89 Internal Version 0.02 Power Connector 1 3 5 7 9 H17 CB6 47uF 20V VDD_5V0 1 ST_S/PDIF_DATA R55 TORX147PL(F,T) OUT CD50 0.1uF 10V S/P DIF CONNECTOR 4 5 47uH VDD_3V3_TOSLINK 3 VCC GND 2 4.7K R59 4 1 17 1 5 A B C D HDMI Mezzanine Card – Revision B User’s Guide Figure 16. B to B Connectors and Audio In Z5 40mil Pad Z1 165 mil Pad Size Z7 100mil Drill Size Z8 100mil Drill Size Mounting Hole 3 2 Internal Version 0.02 Tel: 91-44-2253 7900 Fax: 91-44-2252 3514 www.gdatech.com C D Date: B Size Title Tuesday, March 02, 2010 Document Number 1 Sheet GDA09CB004B 11 BOARD ACCESSORIES GDA Technologies Ltd, L & T Infotech Park, Mount Poonamallee Road, Manapakkam, Ch 89 of 11 Rev B A Tooling Holes 1 A 4 Fiducials Z6 40mil Pad 2 B 5 Z4 40mil Pad 3 BOARD ACCESSORIES B C 1 1 1 1 1 1 1 1 1 1 Z3 40mil Pad 4 1 1 1 18 1 D 5 HDMI Mezzanine Card – Revision B User’s Guide Figure 17. Board Accessories HDMI Mezzanine Card – Revision B User’s Guide Appendix B. Hardware Variants Early versions of the HDMI Mezzanine Card Revision B were produced with U3 (STMicroelectronics STDVE001A Adaptive single 3.4 Gbps TMDS/HDMI signal equalizer) populated. On the current version of the HDMI Mezzanine Card Revision B, U3 is not populated. To receive HDMI/DVI input when U3 is unpopulated: • Connect the HDMI/DVI source using J2. • Install a shunt between pin 2 and pin 3 of header H13 to route J2 HDMI/DVI signals to the FPGA via the Mezzanine connector. On the current version of the board, the following additional changes were made: • To support the Extended Display Identification Data (EDID) via the I2C interface of the FPGA, two modification wires are installed in the following locations on the new HDMI Mezzanine Card Revision B: – R15 (pad nearest U3) to R12 (pad nearest U3) – R14 (pad nearest U3) to R11 (pad nearest U3) These wires bridge the I2C bus around vacant U3. • The resistors R2, R3, R6 and R7 are not populated (to reduce I2C bus pull-up strength). • The resistors R71 and R58 are not populated (to correct a pull-down contention). 19