LFE5U-25F-8BG256C

ECP5 and ECP5-5G Family Data Sheet FPGA-DS-02012-2.2 October 2020 ECP5 and ECP5-5G Family Data Sheet Disclaimers Lattice makes no warranty, representation, or guarantee regarding the accuracy of information contained in this document or the suitability of its products for any particular purpose. All information herein is provided AS IS and with all faults, and all risk associated with such information is entirely with Buyer. Buyer shall not rely on any data and performance specifications or parameters provided herein. Products sold by Lattice have been subject to limited testing and it is the Buyer's responsibility to independently determine the suitability of any products and to test and verify the same. No Lattice products should be used in conjunction with mission- or safety-critical or any other application in which the failure of Lattice’s product could create a situation where personal injury, death, severe property or environmental damage may occur. The information provided in this document is proprietary to Lattice Semiconductor, and Lattice reserves the right to make any changes to the information in this document or to any products at any time without notice. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 2 FPGA-DS-02012-2.2 ECP5 and ECP5-5G Family Data Sheet Contents Acronyms in This Document ................................................................................................................................................. 9 1. General Description .................................................................................................................................................... 10 1.1. Features ............................................................................................................................................................ 10 2. Architecture ................................................................................................................................................................ 12 2.1. Overview ........................................................................................................................................................... 12 2.2. PFU Blocks ......................................................................................................................................................... 13 2.2.1. Slice ............................................................................................................................................................... 14 2.2.2. Modes of Operation...................................................................................................................................... 17 2.3. Routing .............................................................................................................................................................. 18 2.4. Clocking Structure ............................................................................................................................................. 18 2.4.1. sysCLOCK PLL ................................................................................................................................................ 18 2.5. Clock Distribution Network ............................................................................................................................... 20 2.5.1. Primary Clocks .............................................................................................................................................. 20 2.5.2. Edge Clock ..................................................................................................................................................... 21 2.6. Clock Dividers .................................................................................................................................................... 22 2.7. DDRDLL .............................................................................................................................................................. 23 2.8. sysMEM Memory .............................................................................................................................................. 24 2.8.1. sysMEM Memory Block ................................................................................................................................ 24 2.8.2. Bus Size Matching ......................................................................................................................................... 25 2.8.3. RAM Initialization and ROM Operation ........................................................................................................ 25 2.8.4. Memory Cascading ....................................................................................................................................... 25 2.8.5. Single, Dual and Pseudo-Dual Port Modes ................................................................................................... 25 2.8.6. Memory Core Reset ...................................................................................................................................... 26 2.9. sysDSP™ Slice .................................................................................................................................................... 26 2.9.1. sysDSP Slice Approach Compared to General DSP ....................................................................................... 26 2.9.2. sysDSP Slice Architecture Features ............................................................................................................... 27 2.10. Programmable I/O Cells .................................................................................................................................... 31 2.11. PIO ..................................................................................................................................................................... 33 2.11.1. Input Register Block ...................................................................................................................................... 33 2.11.2. Output Register Block ................................................................................................................................... 34 2.12. Tristate Register Block....................................................................................................................................... 35 2.13. DDR Memory Support ....................................................................................................................................... 36 2.13.1. DQS Grouping for DDR Memory ................................................................................................................... 36 2.13.2. DLL Calibrated DQS Delay and Control Block (DQSBUF) ............................................................................... 37 2.14. sysI/O Buffer...................................................................................................................................................... 39 2.14.1. sysI/O Buffer Banks ....................................................................................................................................... 39 2.14.2. Typical sysI/O I/O Behavior during Power-up ............................................................................................... 40 2.14.3. Supported sysI/O Standards ......................................................................................................................... 40 2.14.4. On-Chip Programmable Termination............................................................................................................ 41 2.14.5. Hot Socketing ................................................................................................................................................ 42 2.15. SERDES and Physical Coding Sublayer ............................................................................................................... 42 2.15.1. SERDES Block ................................................................................................................................................ 44 2.15.2. PCS ................................................................................................................................................................ 44 2.15.3. SERDES Client Interface Bus .......................................................................................................................... 45 2.16. Flexible Dual SERDES Architecture .................................................................................................................... 45 2.17. IEEE 1149.1-Compliant Boundary Scan Testability............................................................................................ 45 2.18. Device Configuration ......................................................................................................................................... 46 2.18.1. Enhanced Configuration Options .................................................................................................................. 46 2.18.2. Single Event Upset (SEU) Support ................................................................................................................. 46 2.18.3. On-Chip Oscillator ......................................................................................................................................... 47 2.19. Density Shifting ................................................................................................................................................. 47 3. DC and Switching Characteristics ............................................................................................................................... 48 © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02012-2.2 3 ECP5 and ECP5-5G Family Data Sheet 3.1. Absolute Maximum Ratings ..............................................................................................................................48 3.2. Recommended Operating Conditions ...............................................................................................................48 3.3. Power Supply Ramp Rates.................................................................................................................................49 3.4. Power-On-Reset Voltage Levels ........................................................................................................................49 3.5. Power up Sequence ...........................................................................................................................................49 3.6. Hot Socketing Specifications .............................................................................................................................49 3.7. Hot Socketing Requirements .............................................................................................................................50 3.8. ESD Performance...............................................................................................................................................50 3.9. DC Electrical Characteristics ..............................................................................................................................50 3.10. Supply Current (Static) ......................................................................................................................................51 3.11. SERDES Power Supply Requirements1, 2, 3 ..........................................................................................................52 3.12. sysI/O Recommended Operating Conditions ....................................................................................................54 3.13. sysI/O Single-Ended DC Electrical Characteristics .............................................................................................55 3.14. sysI/O Differential Electrical Characteristics .....................................................................................................56 3.14.1. LVDS ..............................................................................................................................................................56 3.14.2. SSTLD.............................................................................................................................................................56 3.14.3. LVCMOS33D ..................................................................................................................................................56 3.14.4. LVDS25E ........................................................................................................................................................57 3.14.5. BLVDS25 ........................................................................................................................................................58 3.14.6. LVPECL33.......................................................................................................................................................59 3.14.7. MLVDS25 .......................................................................................................................................................60 3.14.8. SLVS ...............................................................................................................................................................61 3.15. Typical Building Block Function Performance ...................................................................................................62 3.16. Derating Timing Tables ......................................................................................................................................63 3.17. Maximum I/O Buffer Speed ..............................................................................................................................64 3.18. External Switching Characteristics ....................................................................................................................65 3.19. sysCLOCK PLL Timing .........................................................................................................................................72 3.20. SERDES High-Speed Data Transmitter ...............................................................................................................73 3.21. SERDES/PCS Block Latency ................................................................................................................................74 3.22. SERDES High-Speed Data Receiver ....................................................................................................................75 3.23. Input Data Jitter Tolerance ................................................................................................................................75 3.24. SERDES External Reference Clock......................................................................................................................76 3.25. PCI Express Electrical and Timing Characteristics..............................................................................................77 3.25.1. PCIe (2.5 Gb/s) AC and DC Characteristics ....................................................................................................77 3.25.2. PCIe (5 Gb/s) – Preliminary AC and DC Characteristics .................................................................................78 3.26. CPRI LV2 E.48 Electrical and Timing Characteristics – Preliminary....................................................................80 3.27. XAUI/CPRI LV E.30 Electrical and Timing Characteristics ..................................................................................81 3.27.1. AC and DC Characteristics .............................................................................................................................81 3.28. CPRI LV E.24/SGMII (2.5 Gbps) Electrical and Timing Characteristics ...............................................................81 3.28.1. AC and DC Characteristics .............................................................................................................................81 3.29. Gigabit Ethernet/SGMII (1.25 Gbps)/CPRI LV E.12 Electrical and Timing Characteristics .................................82 3.29.1. AC and DC Characteristics .............................................................................................................................82 3.30. SMPTE SD/HD-SDI/3G-SDI (Serial Digital Interface) Electrical and Timing Characteristics ...............................83 3.30.1. AC and DC Characteristics .............................................................................................................................83 3.31. sysCONFIG Port Timing Specifications...............................................................................................................84 3.32. JTAG Port Timing Specifications ........................................................................................................................89 3.33. Switching Test Conditions .................................................................................................................................90 4. Pinout Information .....................................................................................................................................................92 4.1. Signal Descriptions ............................................................................................................................................92 4.2. PICs and DDR Data (DQ) Pins Associated with the DDR Strobe (DQS) Pin ........................................................95 4.3. Pin Information Summary .................................................................................................................................95 4.3.1. LFE5UM/LFE5UM5G .....................................................................................................................................95 4.3.2. LFE5U ............................................................................................................................................................97 5. Ordering Information..................................................................................................................................................99 © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 4 FPGA-DS-02012-2.2 ECP5 and ECP5-5G Family Data Sheet 5.1. ECP5/ECP5-5G Part Number Description .......................................................................................................... 99 5.2. Ordering Part Numbers ................................................................................................................................... 100 5.2.1. Commercial ................................................................................................................................................. 100 5.2.2. Industrial ..................................................................................................................................................... 102 Supplemental Information ............................................................................................................................................... 105 For Further Information................................................................................................................................................ 105 Revision History ................................................................................................................................................................ 106 © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02012-2.2 5 ECP5 and ECP5-5G Family Data Sheet Figures Figure 2.1. Simplified Block Diagram, LFE5UM/LFE5UM5G-85 Device (Top Level) ............................................................13 Figure 2.2. PFU Diagram .....................................................................................................................................................14 Figure 2.3. Slice Diagram ....................................................................................................................................................15 Figure 2.4. Connectivity Supporting LUT5, LUT6, LUT7, and LUT8 .....................................................................................16 Figure 2.5. General Purpose PLL Diagram...........................................................................................................................19 Figure 2.6. LFE5UM/LFE5UM5G-85 Clocking ......................................................................................................................20 Figure 2.7. DCS Waveforms ................................................................................................................................................21 Figure 2.8. Edge Clock Sources per Bank ............................................................................................................................22 Figure 2.9. ECP5/ECP5-5G Clock Divider Sources ...............................................................................................................22 Figure 2.10. DDRDLL Functional Diagram ...........................................................................................................................23 Figure 2.11. ECP5/ECP5-5G DLL Top Level View (For LFE-45 and LFE-85) ..........................................................................24 Figure 2.12. Memory Core Reset ........................................................................................................................................26 Figure 2.13. Comparison of General DSP and ECP5/ECP5-5G Approaches ........................................................................27 Figure 2.14. Simplified sysDSP Slice Block Diagram ............................................................................................................29 Figure 2.15. Detailed sysDSP Slice Diagram ........................................................................................................................30 Figure 2.16. Group of Four Programmable I/O Cells on Left/Right Sides ...........................................................................32 Figure 2.17. Input Register Block for PIO on Top Side of the Device ..................................................................................33 Figure 2.18. Input Register Block for PIO on Left and Right Side of the Device ..................................................................33 Figure 2.19. Output Register Block on Top Side .................................................................................................................34 Figure 2.20. Output Register Block on Left and Right Sides ...............................................................................................35 Figure 2.21. Tristate Register Block on Top Side.................................................................................................................35 Figure 2.22. Tristate Register Block on Left and Right Sides ...............................................................................................36 Figure 2.23. DQS Grouping on the Left and Right Edges ....................................................................................................37 Figure 2.24. DQS Control and Delay Block (DQSBUF) .........................................................................................................38 Figure 2.25. ECP5/ECP5-5G Device Family Banks ...............................................................................................................39 Figure 2.26. On-Chip Termination ......................................................................................................................................41 Figure 2.27. SERDES/PCS Duals (LFE5UM/LFE5UM5G-85) .................................................................................................43 Figure 2.28. Simplified Channel Block Diagram for SERDES/PCS Block ..............................................................................44 Figure 3.1. LVDS25E Output Termination Example ............................................................................................................57 Figure 3.2. BLVDS25 Multi-point Output Example..............................................................................................................58 Figure 3.3. Differential LVPECL33 .......................................................................................................................................59 Figure 3.4. MLVDS25 (Multipoint Low Voltage Differential Signaling) ...............................................................................60 Figure 3.5. SLVS Interface ...................................................................................................................................................61 Figure 3.6. Receiver RX.CLK.Centered Waveforms .............................................................................................................69 Figure 3.7. Receiver RX.CLK.Aligned and DDR Memory Input Waveforms .........................................................................69 Figure 3.8. Transmit TX.CLK.Centered and DDR Memory Output Waveforms ...................................................................69 Figure 3.9. Transmit TX.CLK.Aligned Waveforms................................................................................................................70 Figure 3.10. DDRX71 Video Timing Waveforms..................................................................................................................70 Figure 3.11. Receiver DDRX71_RX Waveforms ...................................................................................................................71 Figure 3.12. Transmitter DDRX71_TX Waveforms ..............................................................................................................71 Figure 3.13. Transmitter and Receiver Latency Block Diagram ..........................................................................................74 Figure 3.14. SERDES External Reference Clock Waveforms ................................................................................................76 Figure 3.15. sysCONFIG Parallel Port Read Cycle ................................................................................................................85 Figure 3.16. sysCONFIG Parallel Port Write Cycle ...............................................................................................................86 Figure 3.17. sysCONFIG Slave Serial Port Timing ................................................................................................................86 Figure 3.18. Power-On-Reset (POR) Timing ........................................................................................................................87 Figure 3.19. sysCONFIG Port Timing ...................................................................................................................................87 Figure 3.20. Configuration from PROGRAMN Timing .........................................................................................................88 Figure 3.21. Wake-Up Timing .............................................................................................................................................88 Figure 3.22. Master SPI Configuration Waveforms ............................................................................................................89 Figure 3.23. JTAG Port Timing Waveforms .........................................................................................................................90 Figure 3.24. Output Test Load, LVTTL and LVCMOS Standards ..........................................................................................90 © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 6 FPGA-DS-02012-2.2 ECP5 and ECP5-5G Family Data Sheet Tables Table 1.1. ECP5 and ECP5-5G Family Selection Guide ........................................................................................................ 11 Table 2.1. Resources and Modes Available per Slice .......................................................................................................... 14 Table 2.2. Slice Signal Descriptions ..................................................................................................................................... 16 Table 2.3. Number of Slices Required to Implement Distributed RAM .............................................................................. 17 Table 2.4. PLL Blocks Signal Descriptions............................................................................................................................ 19 Table 2.5. DDRDLL Ports List ............................................................................................................................................... 23 Table 2.6. sysMEM Block Configurations ............................................................................................................................ 25 Table 2.7. Maximum Number of Elements in a Slice .......................................................................................................... 31 Table 2.8. Input Block Port Description .............................................................................................................................. 34 Table 2.9. Output Block Port Description ........................................................................................................................... 35 Table 2.10. Tristate Block Port Description ........................................................................................................................ 36 Table 2.11. DQSBUF Port List Description .......................................................................................................................... 38 Table 2.12. On-Chip Termination Options for Input Modes ............................................................................................... 41 Table 2.13. LFE5UM/LFE5UM5G SERDES Standard Support .............................................................................................. 43 Table 2.14. Available SERDES Duals per LFE5UM/LFE5UM5G Devices............................................................................... 44 Table 2.15. LFE5UM/LFE5UM5G Mixed Protocol Support ................................................................................................. 45 Table 2.16. Selectable Master Clock (MCLK) Frequencies during Configuration (Nominal) ............................................... 47 Table 3.1. Absolute Maximum Ratings ............................................................................................................................... 48 Table 3.2. Recommended Operating Conditions ................................................................................................................ 48 Table 3.3. Power Supply Ramp Rates ................................................................................................................................. 49 Table 3.4. Power-On-Reset Voltage Levels ......................................................................................................................... 49 Table 3.5. Hot Socketing Specifications .............................................................................................................................. 49 Table 3.6. Hot Socketing Requirements ............................................................................................................................. 50 Table 3.7. DC Electrical Characteristics ............................................................................................................................... 50 Table 3.8. ECP5/ECP5-5G Supply Current (Static)............................................................................................................... 51 Table 3.9. ECP5UM ............................................................................................................................................................. 52 Table 3.10. ECP5-5G ........................................................................................................................................................... 53 Table 3.11. sysI/O Recommended Operating Conditions ................................................................................................... 54 Table 3.12. Single-Ended DC Characteristics ...................................................................................................................... 55 Table 3.13. LVDS ................................................................................................................................................................. 56 Table 3.14. LVDS25E DC Conditions.................................................................................................................................... 57 Table 3.15. BLVDS25 DC Conditions ................................................................................................................................... 58 Table 3.16. LVPECL33 DC Conditions .................................................................................................................................. 59 Table 3.17. MLVDS25 DC Conditions .................................................................................................................................. 60 Table 3.18. Input to SLVS .................................................................................................................................................... 61 Table 3.19. Pin-to-Pin Performance.................................................................................................................................... 62 Table 3.20. Register-to-Register Performance ................................................................................................................... 63 Table 3.21. ECP5/ECP5-5G Maximum I/O Buffer Speed ..................................................................................................... 64 Table 3.22. ECP5/ECP5-5G External Switching Characteristics ........................................................................................... 65 Table 3.23. sysCLOCK PLL Timing ........................................................................................................................................ 72 Table 3.24. Serial Output Timing and Levels ...................................................................................................................... 73 Table 3.25. Channel Output Jitter....................................................................................................................................... 73 Table 3.26. SERDES/PCS Latency Breakdown ..................................................................................................................... 74 Table 3.27. Serial Input Data Specifications ....................................................................................................................... 75 Table 3.28. Receiver Total Jitter Tolerance Specification ................................................................................................... 75 Table 3.29. External Reference Clock Specification (refclkp/refclkn) ................................................................................. 76 Table 3.30. PCIe (2.5 Gb/s) ................................................................................................................................................. 77 Table 3.31. PCIe (5 Gb/s) .................................................................................................................................................... 78 Table 3.32. CPRI LV2 E.48 Electrical and Timing Characteristics ........................................................................................ 80 Table 3.33. Transmit ........................................................................................................................................................... 81 Table 3.34. Receive and Jitter Tolerance ............................................................................................................................ 81 Table 3.35. Transmit ........................................................................................................................................................... 81 © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02012-2.2 7 ECP5 and ECP5-5G Family Data Sheet Table 3.36. Receive and Jitter Tolerance ............................................................................................................................82 Table 3.37. Transmit ...........................................................................................................................................................82 Table 3.38. Receive and Jitter Tolerance ............................................................................................................................82 Table 3.39. Transmit ...........................................................................................................................................................83 Table 3.40. Receive .............................................................................................................................................................83 Table 3.41. Reference Clock ...............................................................................................................................................83 Table 3.42. ECP5/ECP5-5G sysCONFIG Port Timing Specifications .....................................................................................84 Table 3.43. JTAG Port Timing Specifications .......................................................................................................................89 Table 3.44. Test Fixture Required Components, Non-Terminated Interfaces ....................................................................91 © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 8 FPGA-DS-02012-2.2 ECP5 and ECP5-5G Family Data Sheet Acronyms in This Document A list of acronyms used in this document. Acronym Definition ALU BGA CDR CRC DCC DCS DDR DLL DSP EBR ECLK FFT FIFO FIR LVCMOS LVDS LVPECL LVTTL LUT MLVDS PCI Arithmetic Logic Unit Ball Grid Array Clock and Data Recovery Cycle Redundancy Code Dynamic Clock Control Dynamic Clock Select Double Data Rate Delay-Locked Loops Digital Signal Processing Embedded Block RAM Edge Clock Fast Fourier Transforms First In First Out Finite Impulse Response Low-Voltage Complementary Metal Oxide Semiconductor Low-Voltage Differential Signaling Low Voltage Positive Emitter Coupled Logic Low Voltage Transistor-Transistor Logic Look Up Table Multipoint Low-Voltage Differential Signaling Peripheral Component Interconnect PCS PCLK PDPR PFU PIC PLL POR SCI SERDES Physical Coding Sublayer Primary Clock Pseudo Dual Port RAM Programmable Functional Unit Programmable I/O Cells Phase-Locked Loops Power On Reset SERDES Client Interface Serializer/Deserializer SEU SLVS SPI SPR SRAM TAP TDM Single Event Upset Scalable Low-Voltage Signaling Serial Peripheral Interface Single Port RAM Static Random-Access Memory Test Access Port Time Division Multiplexing © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02012-2.2 9 ECP5 and ECP5-5G Family Data Sheet 1. General Description The ECP5™/ECP5-5G™ family of FPGA devices is optimized to deliver high performance features such as an enhanced DSP architecture, high speed SERDES (Serializer/Deserializer), and high speed source synchronous interfaces, in an economical FPGA fabric. This combination is achieved through advances in device architecture and the use of 40 nm technology making the devices suitable for high-volume, highspeed, and low-cost applications. The ECP5/ECP5-5G device family covers look-up-table (LUT) capacity to 84K logic elements and supports up to 365 user I/O. The ECP5/ECP5-5G device family also offers up to 156 18 x 18 multipliers and a wide range of parallel I/O standards. The ECP5/ECP5-5G FPGA fabric is optimized high performance with low power and low cost in mind. The ECP5/ ECP5-5G devices utilize reconfigurable SRAM logic technology and provide popular building blocks such as LUT-based logic, distributed and embedded memory, Phase-Locked Loops (PLLs), Delay-Locked Loops (DLLs), pre-engineered source synchronous I/O support, enhanced sysDSP slices and advanced configuration support, including encryption and dual-boot capabilities. The Lattice Diamond™ design software allows large complex designs to be efficiently implemented using the ECP5/ECP5-5G FPGA family. Synthesis library support for ECP5/ECP5-5G devices is available for popular logic synthesis tools. The Diamond tools use the synthesis tool output along with the constraints from its floor planning tools to place and route the design in the ECP5/ECP5-5G device. The tools extract the timing from the routing and back-annotate it into the design for timing verification. Lattice provides many pre-engineered IP (Intellectual Property) modules for the ECP5/ECP5-5G family. By using these configurable soft core IPs as standardized blocks, designers are free to concentrate on the unique aspects of their design, increasing their productivity. 1.1.   The pre-engineered source synchronous logic implemented in the ECP5/ECP5-5G device family supports a broad range of interface standards including DDR2/3, LPDDR2/3, XGMII, and 7:1 LVDS. The ECP5/ECP5-5G device family also features high speed SERDES with dedicated Physical Coding Sublayer (PCS) functions. High jitter tolerance and low transmit jitter allow the SERDES plus PCS blocks to be configured to support an array of popular data protocols including PCI Express, Ethernet (XAUI, GbE, and SGMII) and CPRI. Transmit De-emphasis with pre- and post-cursors, and Receive Equalization settings make the SERDES suitable for transmission and reception over various forms of media.  The ECP5/ECP5-5G devices also provide flexible, reliable and secure configuration options, such as dual-boot capability, bit-stream encryption, and TransFR field upgrade features. ECP5-5G family devices have made some enhancement in the SERDES compared to ECP5UM devices. These enhancements increase the performance of the SERDES to up to 5 Gb/s data rate. The ECP5-5G family devices are pin-to-pin compatible with the ECP5UM devices. These allows a migration path for you to port designs from ECP5UM to ECP5-5G devices to get higher performance.  Features Higher Logic Density for Increased System Integration  12K to 84K LUTs  197 to 365 user programmable I/O Embedded SERDES  270 Mb/s, up to 3.2 Gb/s, SERDES interface (ECP5)  270 Mb/s, up to 5.0 Gb/s, SERDES interface (ECP5-5G)  Supports eDP in RDR (1.62 Gb/s) and HDR  (2.7 Gb/s)  Up to four channels per device: PCI Express, Ethernet (1GbE, SGMII, XAUI), and CPRI sysDSP™  Fully cascadable slice architecture  12 to 160 slices for high performance multiply and accumulate  Powerful 54-bit ALU operations  Time Division Multiplexing MAC Sharing  Rounding and truncation  Each slice supports  Half 36 x 36, two 18 x 18 or four 9 x 9 multipliers  Advanced 18 x 36 MAC and 18 x 18 Multiply-Multiply-Accumulate (MMAC) operations Flexible Memory Resources  Up to 3.744 Mb sysMEM™ Embedded Block  RAM (EBR)  194K to 669K bits distributed RAM © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 10 FPGA-DS-02012-2.2 ECP5 and ECP5-5G Family Data Sheet    sysCLOCK Analog PLLs and DLLs  Four DLLs and four PLLs in LFE5-45 and LFE5-85; two DLLs and two PLLs in LFE5-25 and LFE5-12 Pre-Engineered Source Synchronous I/O  DDR registers in I/O cells  Dedicated read/write levelling functionality  Dedicated gearing logic  Source synchronous standards support  ADC/DAC, 7:1 LVDS, XGMII  High Speed ADC/DAC devices  Dedicated DDR2/DDR3 and LPDDR2/LPDDR3 memory support with DQS logic, up to 800 Mb/s data-rate Programmable sysI/O™ Buffer Supports Wide Range of Interfaces  On-chip termination  LVTTL and LVCMOS 33/25/18/15/12  SSTL 18/15 I, II  HSUL12  LVDS, Bus-LVDS, LVPECL, RSDS, MLVDS  subLVDS and SLVS, SoftIP MIPI D-PHY receiver/transmitter interfaces    Flexible Device Configuration  Shared bank for configuration I/O  SPI boot flash interface  Dual-boot images supported  Slave SPI  TransFR™ I/O for simple field updates Single Event Upset (SEU) Mitigation Support  Soft Error Detect – Embedded hard macro  Soft Error Correction – Without stopping user operation  Soft Error Injection – Emulate SEU event to debug system error handling System Level Support  IEEE 1149.1 and IEEE 1532 compliant  Reveal Logic Analyzer  On-chip oscillator for initialization and general use  V core power supply for ECP5, 1.2 V core power supply for ECP5UM5G Table 1.1. ECP5 and ECP5-5G Family Selection Guide LFE5UM-25 LFE5UM5G-25 LUTs (K) 24 sysMEM Blocks (18 Kb) 56 Embedded Memory (Kb) 1,008 Distributed RAM Bits (Kb) 194 18 X 18 Multipliers 28 SERDES (Dual/Channels) 1/2 PLLs/DLLs 2/2 Packages (SERDES Channels/I/O Count) 144 TQFP — (10 x 10 mm, 0.5 mm) 256 caBGA — (14 x 14 mm, 0.8 mm) 285 csfBGA 2/118 (10 x 10 mm, 0.5 mm) 381 caBGA 2/197 (17 x 17 mm, 0.8 mm) 554 caBGA — (23 x 23 mm, 0.8 mm) 756 caBGA — (27 x 27 mm, 0.8 mm) Device LFE5UM-45 LFE5UM5G-45 44 108 1944 351 72 2/4 4/4 LFE5UM-85 LFE5UM5G-85 84 208 3744 669 156 2/4 4/4 LFE5U12 12 32 576 97 28 0 2/2 LFE5U25 24 56 1,008 194 28 0 2/2 LFE5U45 44 108 1944 351 72 0 4/4 LFE5U85 84 208 3744 669 156 0 4/4 — — 0/96 0/96 0/96 — — — 0/197 0/197 0/197 — 2/118 2/118 0/118 0/118 0/118 0/118 4/203 4/205 0/197 0/197 0/203 0/205 4/245 4/259 — — 0/245 0/259 — 4/365 — — — 0/365 © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02012-2.2 11 ECP5 and ECP5-5G Family Data Sheet 2. Architecture 2.1. Overview Each ECP5/ECP5-5G device contains an array of logic blocks surrounded by Programmable I/O Cells (PIC). Interspersed between the rows of logic blocks are rows of sysMEM™ Embedded Block RAM (EBR) and rows of sysDSP™ Digital Signal Processing slices, as shown in Figure 2.1. The LFE5-85 devices have three rows of DSP slices, the LFE5-45 devices have two rows, and both LFE5-25 and LFE5-12 devices have one. In addition, the LFE5UM/LFE5UM5G devices contain SERDES Duals on the bottom of the device. The Programmable Functional Unit (PFU) contains the building blocks for logic, arithmetic, RAM, and ROM functions. The PFU block is optimized for flexibility, allowing complex designs to be implemented quickly and efficiently. Logic Blocks are arranged in a two-dimensional array. The ECP5/ECP5-5G devices contain one or more rows of sysMEM EBR blocks. sysMEM EBRs are large, dedicated 18 Kb fast memory blocks. Each sysMEM block can be configured in a variety of depths and widths as RAM or ROM. In addition, ECP5/ECP5-5G devices contain up to three rows of DSP slices. Each DSP slice has multipliers and adder/accumulators, which are the building blocks for complex signal processing capabilities. The ECP5 devices feature up to four embedded 3.2 Gb/s SERDES channels, and the ECP5-5G devices feature up to four embedded 5 Gb/s SERDES channels. Each SERDES channel contains independent 8b/10b encoding / decoding, polarity adjust and elastic buffer logic. Each group of two SERDES channels, along with its Physical Coding Sublayer (PCS) block, creates a dual DCU (Dual Channel Unit). The functionality of the SERDES/PCS duals can be controlled by SRAM cell settings during device configuration or by registers that are addressable during device operation. The registers in every dual can be programmed via the SERDES Client Interface (SCI). These DCUs (up to two) are located at the bottom of the devices. Each PIC block encompasses two PIOs (PIO pairs) with their respective sysI/O buffers. The sysI/O buffers of the ECP5/ECP5-5G devices are arranged in seven banks (eight banks for LFE5-85 devices in caBGA756 and caBGA554 packages), allowing the implementation of a wide variety of I/O standards. One of these banks (Bank 8) is shared with the programming interfaces. Half of the PIO pairs on the left and right edges of the device can be configured as LVDS transmit pairs, and all pairs on left and right can be configured as LVDS receive pairs. The PIC logic in the left and right banks also includes pre-engineered support to aid in the implementation of high speed source synchronous standards such as XGMII, 7:1 LVDS, along with memory interfaces including DDR3 and LPDDR3. The ECP5/ECP5-5G registers in PFU and sysI/O can be configured to be SET or RESET. After power up and the device is configured, it enters into user mode with these registers SET/RESET according to the configuration setting, allowing the device entering to a known state for predictable system function. Other blocks provided include PLLs, DLLs and configuration functions. The ECP5/ECP5-5G architecture provides up to four Delay-Locked Loops (DLLs) and up to four Phase-Locked Loops (PLLs). The PLL and DLL blocks are located at the corners of each device. The configuration block that supports features such as configuration bit-stream decryption, transparent updates and dual-boot support is located at the bottom of each device, to the left of the SERDES blocks. Every device in the ECP5/ECP5-5G family supports a sysCONFIG™ ports located in that same corner, powered by VCCIO8, allowing for serial or parallel device configuration. In addition, every device in the family has a JTAG port. This family also provides an on-chip oscillator and soft error detect capability. The ECP5 devices use 1.1 V and ECP5UM5G devices use 1.2 V as their core voltage. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 12 FPGA-DS-02012-2.2 ECP5 and ECP5-5G Family Data Sheet Figure 2.1. Simplified Block Diagram, LFE5UM/LFE5UM5G-85 Device (Top Level) 2.2. PFU Blocks The core of the ECP5/ECP5-5G device consists of PFU blocks. Each PFU block consists of four interconnected slices numbered 0-3, as shown in Figure 2.2. Each slice contains two LUTs. All the interconnections to and from PFU blocks are from routing. There are 50 inputs and 23 outputs associated with each PFU block. The PFU block can be used in Distributed RAM or ROM function, or used to perform Logic, Arithmetic, or ROM functions. Table 2.1 shows the functions each slice can perform in either mode. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02012-2.2 13 ECP5 and ECP5-5G Family Data Sheet Figure 2.2. PFU Diagram 2.2.1. Slice Each slice contains two LUT4s feeding two registers. In Distributed SRAM mode, Slice 0 through Slice 2 are configured as distributed memory, and Slice 3 is used as Logic or ROM. Table 2.1 shows the capability of the slices along with the operation modes they enable. In addition, each PFU contains logic that allows the LUTs to be combined to perform functions such as LUT5, LUT6, LUT7 and LUT8. There is control logic to perform set/reset functions (programmable as synchronous/ asynchronous), clock select, chip-select and wider RAM/ROM functions. Table 2.1. Resources and Modes Available per Slice Slice Slice 0 Slice 1 Slice 2 Slice 3 PFU (Used in Distributed SRAM) Resources Modes 2 LUT4s and 2 Registers RAM 2 LUT4s and 2 Registers RAM 2 LUT4s and 2 Registers RAM 2 LUT4s and 2 Registers Logic, Ripple, ROM PFU (Not used as Distributed SRAM) Resources Modes 2 LUT4s and 2 Registers Logic, Ripple, ROM 2 LUT4s and 2 Registers Logic, Ripple, ROM 2 LUT4s and 2 Registers Logic, Ripple, ROM 2 LUT4s and 2 Registers Logic, Ripple, ROM Figure 2.3 shows an overview of the internal logic of the slice. The registers in the slice can be configured for positive/negative and edge triggered or level sensitive clocks. Each slice has 14 input signals, 13 signals from routing and one from the carry-chain (from the adjacent slice or PFU). There are five outputs, four to routing and one to carry-chain (to the adjacent PFU). There are two inter slice/ PFU output signals that are used to support wider LUT functions, such as LUT6, LUT7, and LUT8. Table 2.2 and Figure 2.3 list the signals associated with all the slices. Figure 2.4 shows the connectivity of the inter-slice/PFU signals that support LUT5, LUT6, LUT7, and LUT8. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 14 FPGA-DS-02012-2.2 ECP5 and ECP5-5G Family Data Sheet FCO FXA FXB M1 M0 A1 B1 C1 D1 LUT4 & CARRY* F1 F1 FF Q1 A0 B0 C0 D0 LUT4 & CARRY* F0 F0 FF Q0 CE CLK LSR FCI From Different Slice/PFU Notes: For Slices 0 and 1, memory control signals are generated from Slice 2 as follows: WCK is CLK WRE is from LSR DI[3:2] for Slice 1 and DI[1:0] for Slice 0 data from Slice 2 WAD [A:D] is a 4-bit address from slice 2 LUT input Figure 2.3. Slice Diagram © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02012-2.2 15 ECP5 and ECP5-5G Family Data Sheet Q1 F0 LUT5 Q0 F1 LUT6 Q1 LUT5 F0 Q0 Q1 F0 LUT5 Q0 A1 B1 C1 D1 A0 B0 C0 D0 FXB FXA A1 B1 C1 D1 A0 B0 C0 D0 FXB FXA LUT7 F1 Q1 LUT5 F0 Q0 F1 LUT6 Q1 LUT5 F0 Q0 A1 B1 C1 D1 A0 B0 C0 D0 FXB FXA A1 B1 C1 D1 A0 B0 C0 D0 FXB FXA 3 SLICE F0 LUT5 Q0 LUT7 Output From Previous PFU F1 LUT6 2 A1 B1 C1 D1 A0 B0 C0 D0 FXB FXA Q1 Q1 SLICE 3 SLICE 2 LUT6 LUT8 F0 LUT5 Q0 F1 LUT7 1 LUT7 1 F1 F1 F1 Q1 SLICE Q0 A1 B1 C1 D1 A0 B0 C0 D0 FXB FXA A1 B1 C1 D1 A0 B0 C0 D0 FXB FXA F0 LUT5 Q0 F1 LUT6 0 F0 LUT5 F0 LUT5 Q0 SLICE SLICE Q1 Q1 1 LUT6 2 F1 F1 SLICE Q0 PFU Col(n+1) LUT8 0 3 SLICE F0 LUT5 A1 B1 C1 D1 A0 B0 C0 D0 FXB FXA SLICE A1 B1 C1 D1 A0 B0 C0 D0 FXB FXA Q1 SLICE A1 B1 C1 D1 A0 B0 C0 D0 FXB FXA F1 LUT8 0 A1 B1 C1 D1 A0 B0 C0 D0 FXB FXA PFU Col(n) SLICE LUT7 Output To Next PFU A1 B1 C1 D1 A0 B0 C0 D0 FXB FXA Q1 SLICE PFU Col(n-1) LUT5 F0 Q0 Figure 2.4. Connectivity Supporting LUT5, LUT6, LUT7, and LUT8 Table 2.2. Slice Signal Descriptions Function Type Signal Names Description Input Data signal A0, B0, C0, D0 Inputs to LUT4 Input Data signal A1, B1, C1, D1 Inputs to LUT4 Input Multi-purpose M0 Multipurpose Input Input Multi-purpose M1 Multipurpose Input Input Control signal CE Clock Enable Input Control signal LSR Local Set/Reset Input Control signal CLK System Clock Input Inter-PFU signal FCI Fast Carry-in1 Input Inter-slice signal FXA Intermediate signal to generate LUT6, LUT7 and LUT82 Input Inter-slice signal FXB Intermediate signal to generate LUT6, LUT7 and LUT82 Output Data signals F0, F1 LUT4 output register bypass signals Output Data signals Q0, Q1 Register outputs Output Inter-PFU signal FCO Fast carry chain output1 Notes: 1. See Figure 2.3 for connection details. 2. Requires two adjacent PFUs. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 16 FPGA-DS-02012-2.2 ECP5 and ECP5-5G Family Data Sheet 2.2.2. Modes of Operation Slices 0-2 have up to four potential modes of operation: Logic, Ripple, RAM, and ROM. Slice 3 is not needed for RAM mode, it can be used in Logic, Ripple, or ROM modes. 2.2.2.1. Logic Mode In this mode, the LUTs in each slice are configured as 4-input combinatorial lookup tables. A LUT4 can have 16 possible input combinations. Any four input logic functions can be generated by programming this lookup table. Since there are two LUT4s per slice, a LUT5 can be constructed within one slice. Larger look-up tables such as LUT6, LUT7, and LUT8 can be constructed by concatenating other slices. Note that LUT8 requires more than four slices. 2.2.2.2. Ripple Mode Ripple mode supports the efficient implementation of small arithmetic functions. In ripple mode, the following functions can be implemented by each slice:  Addition 2-bit  Subtraction 2-bit  Add/Subtract 2-bit using dynamic control  Up counter 2-bit  Down counter 2-bit  Up/Down counter with asynchronous clear  Up/Down counter with preload (sync)  Ripple mode multiplier building block  Multiplier support  Comparator functions of A and B inputs  A greater-than-or-equal-to B  A not-equal-to B  A less-than-or-equal-to B Ripple Mode includes an optional configuration that performs arithmetic using fast carry chain methods. In this configuration (also referred to as CCU2 mode) two additional signals, Carry Generate and Carry Propagate, are generated on a per slice basis to allow fast arithmetic functions to be constructed by concatenating Slices. 2.2.2.3. RAM Mode In this mode, a 16 x 4-bit distributed single port RAM (SPR) can be constructed in one PFU using each LUT block in Slice 0 and Slice 1 as a 16 x 2-bit memory in each slice. Slice 2 is used to provide memory address and control signals. A 16 x 2-bit pseudo dual port RAM (PDPR) memory is created in one PFU by using one Slice as the read-write port and the other companion slice as the read-only port. The slice with the read-write port updates the SRAM data contents in both slices at the same write cycle. ECP5/ECP5-5G devices support distributed memory initialization. The Lattice design tools support the creation of a variety of different size memories. Where appropriate, the software constructs these using distributed memory primitives that represent the capabilities of the PFU. Table 2.3 lists the number of slices required to implement different distributed RAM primitives. For more information about using RAM in ECP5/ECP5-5G devices, refer to ECP5 and ECP5-5G Memory Usage Guide (FPGA-TN-02204). Table 2.3. Number of Slices Required to Implement Distributed RAM RAM Number of Slices SPR 16 X 4 3 PDPR 16 X 4 6 Note: SPR = Single Port RAM, PDPR = Pseudo Dual Port RAM © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02012-2.2 17 ECP5 and ECP5-5G Family Data Sheet 2.2.2.4. ROM Mode ROM mode uses the LUT logic; hence, Slices 0 through 3 can be used in ROM mode. Preloading is accomplished through the programming interface during PFU configuration. For more information, refer to ECP5 and ECP5-5G Memory Usage Guide (FPGA-TN-02204). 2.3. Routing There are many resources provided in the ECP5/ECP5-5G devices to route signals individually or as busses with related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) segments. The ECP5/ECP5-5G family has an enhanced routing architecture that produces a compact design. The Diamond design software tool suites take the output of the synthesis tool and places and routes the design. 2.4. Clocking Structure ECP5/ECP5-5G clocking structure consists of clock synthesis blocks (sysCLOCK PLL); balanced clock tree networks (PCLK and ECLK trees); and efficient clock logic modules (CLOCK DIVIDER and Dynamic Clock Select (DCS), Dynamic Clock Control (DCC) and DLL). All of these functions are described below. 2.4.1. sysCLOCK PLL The sysCLOCK PLLs provide the ability to synthesize clock frequencies. The devices in the ECP5/ECP5-5G family support two to four full-featured General Purpose PLLs. The sysCLOCK PLLs provide the ability to synthesize clock frequencies. The architecture of the PLL is shown in Figure 2.5. A description of the PLL functionality follows. CLKI is the reference frequency input to the PLL and its source can come from two different external CLK inputs or from internal routing. A non-glitchless 2-to-1 input multiplexor is provided to dynamically select between two different external reference clock sources. The CLKI input feeds into the input Clock Divider block. CLKFB is the feedback signal to the PLL which can come from internal feedback path, routing or an external I/O pin. The feedback divider is used to multiply the reference frequency and thus synthesize a higher frequency clock output. The PLL has four clock outputs CLKOP, CLKOS, CLKOS2 and CLKOS3. Each output has its own output divider, thus allowing the PLL to generate different frequencies for each output. The output dividers can have a value from 1 to 128. The CLKOP, CLKOS, CLKOS2, and CLKOS3 outputs can all be used to drive the primary clock network. Only CLKOP and CLKOS outputs can go to the edge clock network. The setup and hold times of the device can be improved by programming a phase shift into the CLKOS, CLKOS2, and CLKOS3 output clocks which advances or delays the output clock with reference to the CLKOP output clock. This phase shift can be either programmed during configuration or can be adjusted dynamically using the PHASESEL, PHASEDIR, PHASESTEP, and PHASELOADREG ports. The LOCK signal is asserted when the PLL determines it has achieved lock and de-asserted if a loss of lock is detected. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 18 FPGA-DS-02012-2.2 ECP5 and ECP5-5G Family Data Sheet PHASESEL[1:0] PHASEDIR PHASESTEP PHASELOADREG PLLREFCS Dynamic Phase Adjust SEL CLKOP Divider (1-128 ) CLKOP CLKOS Divider (1-128 ) CLKOS VCO CLKOS2 Divider (1-128 ) CLKOS2 VCO CLKOS3 Divider (1-128 ) CLKOS3 VCO Refclk CLK0 PLLCSOUT CLKI CLKI2 CLK1 Refclk Divider M CLKI Phase Detector, VCO, and Loop Filter FBKSEL CLKFB Feedback Clock Divider VCO Internal Feedback CLKOP, CLKOS, CLKOS2, CLKOS3 ENCLKOP ENCLKOS ENCLKOS2 ENCLKOS3 RST STDBY Lock Detect LOCK Figure 2.5. General Purpose PLL Diagram Table 2.4 provides a description of the signals in the PLL blocks. Table 2.4. PLL Blocks Signal Descriptions Signal Type Description CLKI Input Clock Input to PLL from external pin or routing CLKI2 Input Mixed clock input to PLL SEL Input Input Clock select, selecting from CLKI and CLKI2 inputs CLKFB Input PLL Feedback Clock PHASESEL[1:0] Input Select which output to be adjusted on Phase by PHASEDIR, PHASESTEP, PHASELODREG PHASEDIR Input Dynamic Phase adjustment direction. PHASESTEP Input Dynamic Phase adjustment step. PHASELOADREG Input Load dynamic phase adjustment values into PLL. CLKOP Output Primary PLL output clock (with phase shift adjustment) CLKOS Output Secondary PLL output clock (with phase shift adjust) CLKOS2 Output Secondary PLL output clock2 (with phase shift adjust) CLKOS3 Output Secondary PLL output clock3 (with phase shift adjust) LOCK Output PLL LOCK to CLKI, Asynchronous signal. Active high indicates PLL lock STDBY Input Standby signal to power down the PLL RST Input Resets the PLL ENCLKOP Input Enable PLL output CLKOP ENCLKOS Input Enable PLL output CLKOS ENCLKOS2 Input Enable PLL output CLKOS2 ENCLKOS3 Input Enable PLL output CLKOS3 For more details on the PLL, you can refer to the ECP5 and ECP5-5G sysClock PLL/DLL Design and Usage Guide (FPGATN-02200). © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02012-2.2 19 ECP5 and ECP5-5G Family Data Sheet 2.5. Clock Distribution Network There are two main clock distribution networks for any member of the ECP5/ECP5-5G product family, namely Primary Clock (PCLK) and Edge Clock (ECLK). These clock networks have the clock sources come from many different sources, such as Clock Pins, PLL outputs, DLLDEL outputs, Clock divider outputs, SERDES/PCS clocks and some on chip generated clock signal. There are clock dividers (CLKDIV) blocks to provide the slower clock from these clock sources. ECP5/ECP5-5G also supports glitchless dynamic enable function (DCC) for the PCLK Clock to save dynamic power. There are also some logics to allow dynamic glitchless selection between two clocks for the PCLK network (DCS). Overview of Clocking Network is shown in Figure 2.6 for LFE5UM/LFE5UM5G-85 device. PIO PLL 12 DCC Bank 7 Edge Clocks PLL Quadrant TL Primary Clocks 12 Primary Sources 16 PIO PIO DLL 14 DCC 14 Primary Sources Fabric Entry Fabric Entry 16 16 Primary Sources Quadrant BL 14 Primary Clocks PCSCLKDIV PCSCLKDIV SERDES DCU0 CLK DIV CLK DIV PLL Mid MUX Bank 8 Mid MUX Quadrant BR 16 DCC PLL DLL 14 DCC Edge Clocks Bank 6 16 14 Primary Sources Center MUX Bank 3 Primary Clocks 16 PIO PIO 14 Fabric Entry Quadrant TR PIO Mid MUX Fabric Entry Primary Clocks PIO PIO Bank 1 PIO Edge Clocks PIO Bank 2 CLK DIV PIO Mid MUX Edge Clocks CLK DIV PIO Bank 0 DLL SERDES DCU1 Bank 4 DLL Figure 2.6. LFE5UM/LFE5UM5G-85 Clocking 2.5.1. Primary Clocks The ECP5/ECP5-5G device family provides low-skew, high fan-out clock distribution to all synchronous elements in the FPGA fabric through the Primary Clock Network. The primary clock network is divided into four clocking quadrants: Top Left (TL), Bottom Left (BL), Top Right (TR), and Bottom Right (BR). Each of these quadrants has 16 clocks that can be distributed to the fabric in the quadrant. The Lattice Diamond software can automatically route each clock to one of the four quadrants up to a maximum of 16 clocks per quadrant. You can change how the clocks are routed by specifying a preference in the Lattice Diamond software to locate the clock to specific. The ECP5/ECP5-5G device provides you with a maximum of 64 unique clock input sources that can be routed to the primary Clock network. Primary clock sources are:  Clock input pins  PLL outputs  CLKDIV outputs  Internal FPGA fabric entries (with minimum general routing)  SERDES/PCS/PCSDIV clocks  OSC clock These sources are routed to one of four clock switches called a Mid Mux. The outputs of the Mid MUX are routed to the center of the FPGA where another clock switch, called the Center MUX, is used to route the primary clock sources to primary clock distribution to the ECP5/ECP5-5G fabric. These routing muxes are shown in Figure 2.6. Since there is a maximum of 60 unique clock input sources to the clocking quadrants, there are potentially 64 unique clock domains that can be used in the ECP5/ECP5-5G Device. For more information about the primary clock tree and connections, refer to ECP5 and ECP5-5G sysClock PLL/DLL Design and Usage Guide (FPGA-TN-02200). © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 20 FPGA-DS-02012-2.2 ECP5 and ECP5-5G Family Data Sheet 2.5.1.1. Dynamic Clock Control The Dynamic Clock Control (DCC), Quadrant Clock enable/disable feature allows internal logic control of the quadrant primary clock network. When a clock network is disabled, the clock signal is static and not toggle. All the logic fed by that clock does not toggle, reducing the overall power consumption of the device. The disable function does not create glitch and increase the clock latency to the primary clock network. This DCC controls the clock sources from the Primary CLOCK MIDMUX before they are fed to the Primary Center MUXs that drive the quadrant clock network. For more information about the DCC, refer to ECP5 and ECP5-5G sysClock PLL/DLL Design and Usage Guide (FPGA-TN-02200). 2.5.1.2. Dynamic Clock Select The Dynamic Clock Select (DCS) is a smart multiplexer function available in the primary clock routing. It switches between two independent input clock sources. Depending on the operation modes, it switches between two (2) independent input clock sources either with or without any glitches. This is achieved regardless of when the select signal is toggled. Both input clocks must be running to achieve functioning glitch-less DCS output clock, but it is not required running clocks when used as non-glitch-less normal clock multiplexer. There are two DCS blocks per device that are fed to all quadrants. The inputs to the DCS block come from all the output of MIDMUXs and Clock from CIB located at the center of the PLC array core. The output of the DCS is connected to one of the inputs of Primary Clock Center MUX. Figure 2.7 shows the timing waveforms of the default DCS operating mode. The DCS block can be programmed to other modes. For more information about the DCS, refer to ECP5 and ECP5-5G sysClock PLL/DLL Design and Usage Guide (FPGA-TN-02200). CLK0 CLK1 SEL CLKO Figure 2.7. DCS Waveforms 2.5.2. Edge Clock ECP5/ECP5-5G devices have a number of high-speed edge clocks that are intended for use with the PIOs in the implementation of high-speed interfaces. There are two ECLK networks per bank I/O on the Left and Right sides of the devices. Each Edge Clock can be sourced from the following:  Dedicated Clock input pins (PCLK)  DLLDEL output (Clock delayed by 90o)  PLL outputs (CLKOP and CLKOS)  ECLKBRIDGE  Internal Nodes © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02012-2.2 21 ECP5 and ECP5-5G Family Data Sheet Top Left / Right PCLK Pin From ECLK of other bank on same side Top Left / Right DLLDEL Output Top Right / Left PLL CLKOP From ECLKBRIDGE Top Right / Left PLL CLKOS ECLK Tree ECLKSYNC Bottom Right / Left PLL CLKOP Bottom Right / Left PLL CLKOS Bottom Left / Right PCLK Pin To ECLK of other bank on same side Bottom Left / Right DLLDEL Output To ECLKBRIDGE to go to other side From Routing Figure 2.8. Edge Clock Sources per Bank The edge clocks have low injection delay and low skew. They are used for DDR Memory or Generic DDR interfaces. For detailed information on Edge Clock connections, refer to ECP5 and ECP5-5G sysClock PLL/DLL Design and Usage Guide (FPGA-TN-02200). 2.6. Clock Dividers ECP5/ECP5-5G devices have two clock dividers, one on the left side and one on the right side of the device. These are intended to generate a slower-speed system clock from a high-speed edge clock. The block operates in a ÷2, ÷3.5 mode and maintains a known phase relationship between the divided down clock and the high-speed clock based on the release of its reset signal. The clock dividers can be fed from selected PLL outputs, external primary clock pins multiplexed with the DDRDEL Slave Delay or from routing. The clock divider outputs serve as primary clock sources and feed into the clock distribution network. The Reset (RST) control signal resets input and asynchronously forces all outputs to low. The SLIP signal slips the outputs one cycle relative to the input clock. For further information on clock dividers, refer to ECP5 and ECP5-5G sysClock PLL/DLL Design and Usage Guide (FPGA-TN-02200). Figure 2.9 shows the clock divider connections. Primary Clock Pin OR DLLDEL output clock PLL clock output (CLKOP/CLKOS) Primary Clock Tree OR Routing CLKDIV (/2 or /3.5) To Primary Clock Tree OR Routing RST SLIP Figure 2.9. ECP5/ECP5-5G Clock Divider Sources © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 22 FPGA-DS-02012-2.2 ECP5 and ECP5-5G Family Data Sheet 2.7. DDRDLL Every DDRDLL (master DLL block) can generate phase shift code representing the amount of delay in a delay block that corresponding to 90° phase of the reference clock input. The reference clock can be either from PLL, or input pin. This code is used in the DQSBUF block that controls a set of DQS pin groups to interface with DDR memory (slave DLL). There are two DDRDLLs that supply two sets of codes (for two different reference clock frequencies) to each side of the I/O (at each of the corners). The DQSBUF uses this code to controls the DQS input of the DDR memory to 90° shift to clock DQs at the center of the data eye for DDR memory interface. The code is also sent to another slave DLL, DLLDEL, that takes a clock input and generates a 90° shift clock output to drive the clocking structure. This is useful to interface edge-aligned Generic DDR, where 90° clocking needs to be created. Figure 2.10 shows DDRDLL functional diagram. DDRDLL CLK DDRDEL RST LOCK UDDCNTLN DCNTL[7:0] FREEZE Figure 2.10. DDRDLL Functional Diagram Table 2.5. DDRDLL Ports List Port Name Type Description CLK RST Input Input Reference clock input to the DDRDLL. Should run at the same frequency as the clock to the delay code. Reset Input to the DDRDLL. UDDCNTLN Input FREEZE Input DDRDEL Output Update Control to update the delay code. The code is the DCNTL[7:0] outputs. These outputs are updated when the UDDCNTLN signal is LOW. FREEZE goes high and, without a glitch, turns off the DLL internal clock and the ring oscillator output clock. When FREEZE goes low, it turns them back on. The delay codes from the DDRDLL to be used in DQSBUF or DLLDEL. LOCK Output Lock output to indicate the DDRDLL has valid delay output. DCNTL [7:0] Output The delay codes from the DDRDLL available for the user IP. There are four identical DDRDLLs, one in each of the four corners in LFE5-85 and LFE5-45 devices, and two DDRDLLs in both LFE5-25 and LFE5-12 devices in the upper two corners. Each DDRDLL can generate delay code based on the reference frequency. The slave DLL (DQSBUF and DLLDEL) use the code to delay the signal, to create the phase shifted signal used for either DDR memory, to create 90° shift clock. Figure 2.11 shows the DDRDLL and the slave DLLs on the top level view. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02012-2.2 23 ECP5 and ECP5-5G Family Data Sheet LFE5 Device Config I/O Figure 2.11. ECP5/ECP5-5G DLL Top Level View (For LFE-45 and LFE-85) 2.8. sysMEM Memory ECP5/ECP5-5G devices contain a number of sysMEM Embedded Block RAM (EBR). The EBR consists of an 18 Kb RAM with memory core, dedicated input registers and output registers with separate clock and clock enable. Each EBR includes functionality to support true dual-port, pseudo dual-port, single-port RAM, ROM and FIFO buffers (via external PFUs). 2.8.1. sysMEM Memory Block The sysMEM block can implement single port, dual port or pseudo dual port memories. Each block can be used in a variety of depths and widths as listed in Table 2.6. FIFOs can be implemented in sysMEM EBR blocks by implementing support logic with PFUs. The EBR block facilitates parity checking by supporting an optional parity bit for each data byte. EBR blocks provide byte-enable support for configurations with 18-bit and 36-bit data widths. For more information, refer to ECP5 and ECP5-5G Memory Usage Guide (FPGA-TN-02204). © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 24 FPGA-DS-02012-2.2 ECP5 and ECP5-5G Family Data Sheet Table 2.6. sysMEM Block Configurations Memory Mode Configurations 16,384 x 1 8,192 x 2 Single Port 4,096 x 4 2,048 x 9 1,024 x 18 512 x 36 16,384 x 1 8,192 x 2 True Dual Port 4,096 x 4 2,048 x 9 1,024 x 18 16,384 x 1 8,192 x 2 Pseudo Dual Port 4,096 x 4 2,048 x 9 1,024 x 18 512 x 36 2.8.2. Bus Size Matching All of the multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB word 0 to MSB word 0, LSB word 1 to MSB word 1, and so on. Although the word size and number of words for each port varies, this mapping scheme applies to each port. 2.8.3. RAM Initialization and ROM Operation If desired, the contents of the RAM can be pre-loaded during device configuration. By preloading the RAM block during the chip configuration cycle and disabling the write controls, the sysMEM block can also be utilized as a ROM. 2.8.4. Memory Cascading Larger and deeper blocks of RAM can be created using EBR sysMEM Blocks. Typically, the Lattice design tools cascade memory transparently, based on specific design inputs. 2.8.5. Single, Dual and Pseudo-Dual Port Modes In all the sysMEM RAM modes the input data and address for the ports are registered at the input of the memory array. The output data of the memory is optionally registered at the output. EBR memory supports the following forms of write behavior for single port or dual port operation:  Normal – Data on the output appears only during a read cycle. During a write cycle, the data (at the current address) does not appear on the output. This mode is supported for all data widths.  Write Through – A copy of the input data appears at the output of the same port during a write cycle. This mode is supported for all data widths.  Read-Before-Write – When new data is written, the old content of the address appears at the output. This mode is supported for x9, x18, and x36 data widths. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02012-2.2 25 ECP5 and ECP5-5G Family Data Sheet 2.8.6. Memory Core Reset The memory array in the EBR utilizes latches at the A and B output ports. These latches can be reset asynchronously or synchronously. RSTA and RSTB are local signals, which reset the output latches associated with Port A and Port B, respectively. The Global Reset (GSRN) signal can reset both ports. The output data latches and associated resets for both ports are as shown in Figure 2.12. Memory Core D SET Q Port A[17:0] LCLR Output Data Latches D SET Q Port B[17:0] LCLR RSTA RSTB GSRN Programmable Disable Figure 2.12. Memory Core Reset For further information on the sysMEM EBR block, see the list of technical documentation in Supplemental Information section. 2.9. sysDSP™ Slice The ECP5/ECP5-5G family provides an enhanced sysDSP architecture, making it ideally suited for low-cost, high-performance Digital Signal Processing (DSP) applications. Typical functions used in these applications are Finite Impulse Response (FIR) filters, Fast Fourier Transforms (FFT) functions, Correlators, Reed-Solomon/Turbo/Convolution encoders and decoders. These complex signal processing functions use similar building blocks such as multiply-adders and multiply-accumulators. 2.9.1. sysDSP Slice Approach Compared to General DSP Conventional general-purpose DSP chips typically contain one to four (Multiply and Accumulate) MAC units with fixed data-width multipliers; this leads to limited parallelism and limited throughput. Their throughput is increased by higher clock speeds. In the ECP5/ECP5-5G device family, there are many DSP slices that can be used to support different data widths. This allows designers to use highly parallel implementations of DSP functions. Designers can optimize DSP performance vs. area by choosing appropriate levels of parallelism. Figure 2.13 compares the fully serial implementation to the mixed parallel and serial implementation. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 26 FPGA-DS-02012-2.2 ECP5 and ECP5-5G Family Data Sheet Operand A Operand A Operand B Operand A Single Multiplier Operand A Operand B Operand B Operand B x M loops x Multiplier 0 x x Multiplier 1 m/k loops Multiplier k Accumulator Function Implemented in General Purpose DSP (k adds) + m/k accumulate Output Function Implemented in ECP5/ECP5-5G Figure 2.13. Comparison of General DSP and ECP5/ECP5-5G Approaches 2.9.2. sysDSP Slice Architecture Features The ECP5/ECP5-5G sysDSP Slice has been significantly enhanced to provide functions needed for advanced processing applications. These enhancements provide improved flexibility and resource utilization. The ECP5/ECP5-5G sysDSP Slice supports many functions that include the following:  Symmetry support. The primary target application is wireless. 1D Symmetry is useful for many applications that use FIR filters when their coefficients have symmetry or asymmetry characteristics. The main motivation for using 1D symmetry is cost/size optimization. The expected size reduction is up to 2x.  Odd mode – Filter with Odd number of taps  Even mode – Filter with Even number of taps  Two dimensional (2D) symmetry mode – supports 2D filters for mainly video applications  Dual-multiplier architecture. Lower accumulator overhead to half and the latency to half compared to single multiplier architecture  Fully cascadable DSP across slices. Support for symmetric, asymmetric and non-symmetric filters.  Multiply (one 18 x 36, two 18 x 18 or four 9 x 9 Multiplies per Slice)  Multiply (36 x 36 by cascading across two sysDSP slices)  Multiply Accumulate (supports one 18 x 36 multiplier result accumulation or two 18 x 18 multiplier result accumulation)  Two Multiplies feeding one Accumulate per cycle for increased processing with lower latency (two 18 x 18 Multiplies feed into an accumulator that can accumulate up to 52 bits)  Pipeline registers  1D Symmetry support. The coefficients of FIR filters have symmetry or negative symmetry characteristics.  Odd mode – Filter with Odd number of taps  Even mode – Filter with Even number of taps © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02012-2.2 27 ECP5 and ECP5-5G Family Data Sheet       2D Symmetry support. The coefficients of 2D FIR filters have symmetry or negative symmetry characteristics.  3*3 and 3*5 – Internal DSP Slice support  5*5 and larger size 2D blocks – Semi internal DSP Slice support Flexible saturation and rounding options to satisfy a diverse set of applications situations Flexible cascading across DSP slices  Minimizes fabric use for common DSP and ALU functions  Enables implementation of FIR Filter or similar structures using dedicated sysDSP slice resources only  Provides matching pipeline registers  Can be configured to continue cascading from one row of sysDSP slices to another for longer cascade chains Flexible and Powerful Arithmetic Logic Unit (ALU) Supports:  Dynamically selectable ALU OPCODE  Ternary arithmetic (addition/subtraction of three inputs)  Bit-wise two-input logic operations (AND, OR, NAND, NOR, XOR and XNOR)  Eight flexible and programmable ALU flags that can be used for multiple pattern detection scenarios, such as, overflow, underflow and convergent rounding.  Flexible cascading across slices to get larger functions RTL Synthesis friendly synchronous reset on all registers, while still supporting asynchronous reset for legacy users Dynamic MUX selection to allow Time Division Multiplexing (TDM) of resources for applications that require processor-like flexibility that enables different functions for each clock cycle For most cases, as shown in Figure 2.14, the ECP5/ECP5-5G sysDSP slice is backwards-compatible with the LatticeECP2™ and LatticeECP3™ sysDSP block, such that, legacy applications can be targeted to the ECP5/ ECP5-5G sysDSP slice. Figure 2.14 shows the diagram of sysDSP, and Figure 2.15 shows the detailed diagram. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 28 FPGA-DS-02012-2.2 ECP5 and ECP5-5G Family Data Sheet ALU24 ALU24 ALU24 PR0 (36) PR1 (36) PR2 (36) PR3 (36) 9x9 9x9 Mult18-1 9x9 Mult18-2 9x9 9x9 One of these Mult18-0 9x9 Mult18-1 36x36 (Mult36) In Reg B 1 9+/-9 9+/-9 9+/-9 In Reg A 1 In Reg B 0 In Reg B 1 9+/-9 18+/-18 MUA1[17:0] MUB0[17:0] MUA0[17:0] C0[53:0] 18+/-18 9+/-9 In Reg A 0 9+/-9 9+/-9 18+/-18 Casc A1 9+/-9 18+/-18 MUB3[17:0] In Reg B 0 Casc A0 MUA3[17:0] In Reg A 1 MUA2[17:0] 18 In Reg A 0 SIGNEDA[3:0] SIGNEDB[3:0] SOURCEA[3:0] SOURCEB[3:0] GSR MUB2[17:0] 18 Flags[7:0] 18 18 SROA[17:0] SROB[17:0] One of these 9x9 COUT[53:0] (hardwired cascade to right DSP) To DSP Block on Right and to CIB Outputs C0[53:0] 9x9 One of these OutB3 (18) OutA3 (18) MUP3[17:0] MUP2[35:18] OutB2 (18) OutA2 (18) MUP2[17:0] MUP1[35:18] OutB1 (18) OutA1 (18) Accumulator/ALU (54) ALU24 MUB1[17:0] SRIA[17:0] SRIB[17:0] Hardwired from DSP Block on Left OutB0 (18) Accumulator/ALU (54) CLK[3:0] CE[3:0] RST[3:0] DYNOP0[10:0], DYNOP1[10:0] MUP1[17:0] MUP0[35:18] MUP0[17:0] OutA0 (18) CIN[53:0] (hardwired cascade from left DSP) MUP3[35:18] SLICE 1 SLICE 0 Figure 2.14. Simplified sysDSP Slice Block Diagram © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02012-2.2 29 ECP5 and ECP5-5G Family Data Sheet MUIA0 MUIB0 INT_A OPCODE_PA MUIA1 MUIB1 INT_B IR INT_B SRIBK_PA IR IR IR IR +/= DYNOP OPA1 SROA SRIA IR IR IR IR SRIB IR MULTA SROB MULTB IR IR PR PR PR B ALU A ALU 0 0 AMUX Shift 18L BMUX R= A ± B ± C R = Logic (B, C) CMUX C_ALU CIN DSP PreAdder Logic +/- OPA0 C INT_A COUT ALU == OR OR FR OR DSP Core Logic MUOP0 R FLAGS MUOP1 DSP SLICE Figure 2.15. Detailed sysDSP Slice Diagram © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 30 FPGA-DS-02012-2.2 ECP5 and ECP5-5G Family Data Sheet In Figure 2.15, note that A_ALU, B_ALU, and C_ALU are internal signals generated by combining bits from AA, AB, BA BB and C inputs. For further information, refer to ECP5 and ECP5-5G sysDSP Usage Guide (FPGA-TN-02205). The ECP5/ECP5-5G sysDSP block supports the following basic elements.  MULT (Multiply)  MAC (Multiply, Accumulate)  MULTADDSUB (Multiply, Addition/Subtraction)  MULTADDSUBSUM (Multiply, Addition/Subtraction, Summation) Table 2.7 shows the capabilities of each of the ECP5/ECP5-5G slices versus the above functions. Table 2.7. Maximum Number of Elements in a Slice Width of Multiply x9 x18 x36 MULT 4 2 1/2 MAC 1 1 — MULTADDSUB 2 1 — MULTADDSUBSUM * * — *Note: Two slices are required for two m9x9addsubsum, and two slices are required for one m18x18addsubsum. Some options are available in the four elements. The input register in all the elements can be directly loaded or can be loaded as a shift register from previous operand registers. By selecting dynamic operation, the following operations are possible:  In the Add/Sub option the Accumulator can be switched between addition and subtraction on every cycle.  The loading of operands can switch between parallel and serial operations. For further information, refer to ECP5 and ECP5-5G sysDSP Usage Guide (FPGA-TN-02205). 2.10. Programmable I/O Cells The programmable logic associated with an I/O is called a PIO. The individual PIO are connected to their respective sysI/O buffers and pads. On the ECP5/ECP5-5G devices, the Programmable I/O cells (PIC) are assembled into groups of four PIO cells called a Programmable I/O Cell or PIC. The PICs are placed on all four sides of the device. On all the ECP5/ECP5-5G devices, two adjacent PIOs can be combined to provide a complementary output driver pair. All PIO pairs can implement differential receivers. Half of the PIO pairs on the left and right edges of these devices can be configured as true LVDS transmit pairs. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02012-2.2 31 ECP5 and ECP5-5G Family Data Sheet 1 PIC PIO A Input Register Block Output and Tristate Register Block Pin A PIO B Input Register Block Input Gearbox Core Logic / Routing Output Gearbox Output and Tristate Register Block Pin B PIO C Input Register Block Output and Tristate Register Block Pin C PIO D Input Register Block Output and Tristate Register Block Pin D Figure 2.16. Group of Four Programmable I/O Cells on Left/Right Sides © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 32 FPGA-DS-02012-2.2 ECP5 and ECP5-5G Family Data Sheet 2.11. PIO The PIO contains three blocks: an input register block, output register block, and tristate register block. These blocks contain registers for operating in a variety of modes along with the necessary clock and selection logic. 2.11.1. Input Register Block The input register blocks for the PIOs on all edges contain delay elements and registers that can be used to condition high-speed interface signals before they are passed to the device core. In addition, the input register blocks for the PIOs on the left and right edges include built-in FIFO logic to interface to DDR and LPDDR memory. The Input register block on the right and left sides includes gearing logic and registers to implement IDDRX1 and IDDRX2 functions. With two PICs sharing the DDR register path, it can also implement IDDRX71 function used for 7:1 LVDS interfaces. It uses three sets of registers to shift, update, and transfer to implement gearing and the clock domain transfer. The first stage registers samples the high-speed input data by the high-speed edge clock on its rising and falling edges. The second stage registers perform data alignment based on the control signals. The third stage pipeline registers pass the data to the device core synchronized to the low-speed system clock. The top side of the device supports IDDRX1 gearing function. For more information on gearing function, refer to ECP5 and ECP5-5G High-Speed I/O Interface (FPGA-TN-02035). Figure 2.17 shows the input register block for the PIOs on the top edge. INCK INFF Programmable Delay Cell D Q INFF IDDRX1 SCLK RST Q[1:0] Figure 2.17. Input Register Block for PIO on Top Side of the Device Figure 2.18 shows the input register block for the PIOs located on the left and right edges. INCK INFF Programmable Delay Cell D INFF Q FIFO Delayed DQS ECLK SCLK RST ALIGNWD ECLK Generic IDDRX1 IDDRX2 IDDRX71* Q[1:0]/ Q[3:0]/ Q[6:0]* Memory IDDRX2 *For 7:1 LVDS interface only. It is required to use PIO pair pins (PIOA/B or PIOC/D). Figure 2.18. Input Register Block for PIO on Left and Right Side of the Device © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02012-2.2 33 ECP5 and ECP5-5G Family Data Sheet 2.11.1.1. Input FIFO The ECP5/ECP5-5G PIO has dedicated input FIFO per single-ended pin for input data register for DDR Memory interfaces. The FIFO resides before the gearing logic. It transfers data from DQS domain to continuous ECLK domain. On the Write side of the FIFO, it is clocked by DQS clock which is the delayed version of the DQS Strobe signal from DDR memory. On the Read side of FIFO, it is clocked by ECLK. ECLK may be any high speed clock with identical frequency as DQS (the frequency of the memory chip). Each DQS group has one FIFO control block. It distributes FIFO read/write pointer to every PIC in same DQS group. DQS Grouping and DQS Control Block is described in DDR Memory Support section. Table 2.8. Input Block Port Description Name Type Description D Input High Speed Data Input Q[1:0]/Q[3:0]/Q[6:0] Output Low Speed Data to the device core RST Input Reset to the Output Block SCLK Input Slow Speed System Clock ECLK Input High Speed Edge Clock DQS Input Clock from DQS control Block used to clock DDR memory data ALIGNWD Input Data Alignment signal from device core. 2.11.2. Output Register Block The output register block registers signal from the core of the device before they are passed to the sysI/O buffers. ECP5/ECP5-5G output data path has output programmable flip flops and output gearing logic. On the left and right sides, the output register block can support 1x, 2x, and 7:1 gearing enabling high speed DDR interfaces and DDR memory interfaces. On the top side, the banks support 1x gearing. ECP5/ECP5-5G output data path diagram is shown in Figure 2.19. The programmable delay cells are also available in the output data path. For detailed description of the output register block modes and usage, refer to ECP5 and ECP5-5G High-Speed I/O Interface (FPGA-TN-02035). Programmable Delay Cell D OUTFF RST SCLK D[1:0] Q Generic ODDRX1 Figure 2.19. Output Register Block on Top Side © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 34 FPGA-DS-02012-2.2 ECP5 and ECP5-5G Family Data Sheet Programmable Delay Cell D OUTFF RST SCLK Q Generic ODDRX1/ ODDRX2/ ODDR71* ECLK DQSW DQSW270 Memory ODDRX2 OSHX2 D[1:0]/ D[3:0]/ D[6:0]* *For 7:1 LVDS interface only. It is required to use PIO pair pins PIOA/B. Figure 2.20. Output Register Block on Left and Right Sides Table 2.9. Output Block Port Description Name Type Description Q Output High Speed Data Output D Input Data from core to output SDR register D[1:0]/D[3:0]/ D[6:0] Input Low Speed Data from device core to output DDR register RST Input Reset to the Output Block SCLK Input Slow Speed System Clock ECLK Input High Speed Edge Clock DQSW Input Clock from DQS control Block used to generate DDR memory DQS output DQSW270 Input Clock from DQS control Block used to generate DDR memory DQ output 2.12. Tristate Register Block The tristate register block registers tristate control signals from the core of the device before they are passed to the sysI/O buffers. The block contains a register for SDR operation. In SDR, TD input feeds one of the flip-flops that then feeds the output. In DDR, operation used mainly for DDR memory interface can be implemented on the left and right sides of the device. Here two inputs feed the tristate registers clocked by both ECLK and SCLK. Figure 2.21 and Figure 2.22 show the Tristate Register Block functions on the device. For detailed description of the tristate register block modes and usage, refer to ECP5 and ECP5-5G High-Speed I/O Interface (FPGA-TN-02035). TQ TD RST SCLK TSFF Figure 2.21. Tristate Register Block on Top Side © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02012-2.2 35 ECP5 and ECP5-5G Family Data Sheet TQ TD TSFF RST SCLK ECLK THSX2 DQSW DQSW270 T[1:0] Figure 2.22. Tristate Register Block on Left and Right Sides Table 2.10. Tristate Block Port Description Name Type Description TD Input Tristate Input to Tristate SDR Register RST Input Reset to the Tristate Block TD[1:0] Input Tristate input to TSHX2 function SCLK Input Slow Speed System Clock ECLK Input High Speed Edge Clock DQSW Input Clock from DQS control Block used to generate DDR memory DQS output DQSW270 Input Clock from DQS control Block used to generate DDR memory DQ output TQ Output Output of the Tristate block 2.13. DDR Memory Support 2.13.1. DQS Grouping for DDR Memory Certain PICs have additional circuitry to allow the implementation of high-speed source synchronous and DDR2, DDR3, LPDDR2 or LPDDR3 memory interfaces. The support varies by the edge of the device as detailed below. The left and right sides of the PIC have fully functional elements supporting DDR2, DDR3, LPDDR2, or LPDDR3 memory interfaces. Every 16 PIOs on the left and right sides are grouped into one DQS group, as shown in Figure 2.23. Within each DQS group, there are two pre-placed pins for DQS and DQS# signals. The rest of the pins in the DQS group can be used as DQ signals and DM signal. The number of pins in each DQS group bonded out is package dependent. DQS groups with less than 11 pins bonded out can only be used for LPDDR2/3 Command/ Address busses. In DQS groups with more than 11 pins bonded out, up to two pre-defined pins are assigned to be used as virtual VCCIO, by driving these pins to HIGH, with the user connecting these pins to VCCIO power supply. These connections create soft connections to VCCIO thru these output pins, and make better connections on VCCIO to help to reduce SSO noise. For details, refer to ECP5 and ECP5-5G High-Speed I/O Interface (FPGA-TN-02035). © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 36 FPGA-DS-02012-2.2 ECP5 and ECP5-5G Family Data Sheet DQS PIO A sysI/O Buffer Pad A (T) PIO B sysI/O Buffer Pad B (C) PIO C sysI/O Buffer Pad C PIO D sysI/O Buffer Pad D PIO A sysI/O Buffer Pad A (T) PIO B sysI/O Buffer Pad B (C) PIO C sysI/O Buffer Pad C PIO D sysI/O Buffer Pad D DQSBUF Delay PIO A sysI/O Buffer Pad A (T) PIO B sysI/O Buffer Pad B (C) PIO C sysI/O Buffer Pad C PIO D sysI/O Buffer Pad D PIO A sysI/O Buffer Pad A (T) PIO B sysI/O Buffer Pad B (C) PIO C sysI/O Buffer Pad C PIO D sysI/O Buffer Pad D Figure 2.23. DQS Grouping on the Left and Right Edges 2.13.2. DLL Calibrated DQS Delay and Control Block (DQSBUF) To support DDR memory interfaces (DDR2/3, LPDDR2/3), the DQS strobe signal from the memory must be used to capture the data (DQ) in the PIC registers during memory reads. This signal is output from the DDR memory device aligned to data transitions and must be time shifted before it can be used to capture data in the PIC. This time shifted is achieved by using DQSDEL programmable delay line in the DQS Delay Block (DQS read circuit). The DQSDEL is implemented as a slave delay line and works in conjunction with a master DDRDLL. This block also includes slave delay line to generate delayed clocks used in the write side to generate DQ and DQS with correct phases within one DQS group. There is a third delay line inside this block used to provide write leveling feature for DDR write if needed. Each of the read and write side delays can be dynamically shifted using margin control signals that can be controlled by the core logic. FIFO Control Block shown in Figure 2.24 generates the Read and Write Pointers for the FIFO block inside the Input Register Block. These pointers are generated to control the DQS to ECLK domain crossing using the FIFO module. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02012-2.2 37 ECP5 and ECP5-5G Family Data Sheet Preamble/Postamble Management & Burst Detect DQS READ[1:0] BURSTDET DATAVALID READCLKSEL[1:0] FIFO Control & Datavalid Generation ECLK SCLK RDPNTR[2:0] WRPNTR[2:0] DQSDEL (90 Deg. Delay Code from DDRDLL) Read Side Slave Delay with Dynamic Margin Control RDLOADN, RDMOVE, RDDIRECTION (Read Side Dynamic Margin Control) DQSR90 (Read Side) DQSW (Write Side) WRLOADN, WRMOVE, WRDIRECTION (Write Side Dynamic Margin Control) Write Side Slave Delay with Dynamic Margin Control DQSW270 (Write Side) RDCFLAG WRCFLAG PAUSE DYNDELAY[7:0] (Write Leveling delay) Write Leveling Figure 2.24. DQS Control and Delay Block (DQSBUF) Table 2.11. DQSBUF Port List Description Name Type Description DQS Input DDR memory DQS strobe READ[1:0] Input Read Input from DDR Controller READCLKSEL[1:0] Input Read pulse selection SCLK Input Slow System Clock ECLK Input High Speed Edge Clock (same frequency as DDR memory) DQSDEL Input 90° Delay Code from DDRDLL RDLOADN, RDMOVE, RDDIRECTION Input Dynamic Margin Control ports for Read delay WRLOADN, WRMOVE, WRDIRECTION Input Dynamic Margin Control ports for Write delay PAUSE Input DYNDELAY[7:0] Input Used by DDR Controller to Pause write side signals during DDRDLL Code update or Write Leveling Dynamic Write Leveling Delay Control DQSR90 Output 90° delay DQS used for Read DQSW270 Output 90° delay clock used for DQ Write DQSW Output Clock used for DQS Write RDPNTR[2:0] Output Read Pointer for IFIFO module WRPNTR[2:0] Output Write Pointer for IFIFO module DATAVALID Output Signal indicating start of valid data BURSTDET Output Burst Detect indicator RDFLAG Output Read Dynamic Margin Control output to indicate max value WRFLAG Output Write Dynamic Margin Control output to indicate max value © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 38 FPGA-DS-02012-2.2 ECP5 and ECP5-5G Family Data Sheet 2.14. sysI/O Buffer Each I/O is associated with a flexible buffer referred to as a sysI/O buffer. These buffers are arranged around the periphery of the device in groups referred to as banks. The sysI/O buffers allow you to implement the wide variety of standards that are found in today’s systems including LVDS, HSUL, BLVDS, SSTL Class I and II, LVCMOS, LVTTL, LVPECL, and MIPI. 2.14.1. sysI/O Buffer Banks ECP5/ECP5-5G devices have seven sysI/O buffer banks, two banks per side at Top, Left and Right, plus one at the bottom left side. The bottom left side bank (Bank 8) is a shared I/O bank. The I/O in that bank contains both dedicated and shared I/O for sysConfig function. When a shared pin is not used for configuration, it is available as a user I/O. For LFE5-85 devices, there is an additional I/O bank (Bank 4) that is not available in other device in the family. In ECP5/ECP5-5G devices, the Left and Right sides are tailored to support high performance interfaces, such as DDR2, DDR3, LPDDR2, LPDDR3 and other high speed source synchronous standards. The banks on the Left and Right sides of the devices feature LVDS input and output buffers, data-width gearing, and DQSBUF block to support DDR2/3 and LPDDR2/3 interfaces. The I/O on the top and bottom banks do not have LVDS input and output buffer, and gearing logic, but can use LVCMOS to emulate most of differential output signaling. Each sysI/O bank has its own I/O supply voltage (VCCIO). In addition, the banks on the Left and Right sides of the device, have voltage reference input (shared I/O pin), VREF1 per bank, which allow it to be completely independent of each other. The VREF voltage is used to set the threshold for the referenced input buffers, such as SSTL. Figure 2.25 shows the seven banks and their associated supplies. In ECP5/ECP5-5G devices, single-ended output buffers and ratioed input buffers (LVTTL and LVCMOS) are powered using VCCIO. LVTTL, LVCMOS33, LVCMOS25, and LVCMOS12 can also be set as fixed threshold inputs independent of VCCIO. TOP VREF1(1)V VCCIO1 GND VREF1(0)V VCCIO0 GND Bank 0 Bank 1 VREF1(7) GND Bank 7 Bank 2 V CCIO7 V REF1(2) GND RIGHT LEFT V CCIO2 V REF1(6) GND Bank 6 Bank 3 V CCIO6 GND V CCIO3 V REF1(3) Bank 8 CONFIG BANK Bank 4* SERDES GND V CCIO4 GND V CCIO8 BOTTOM *Note: Only 85K device has this bank. Figure 2.25. ECP5/ECP5-5G Device Family Banks © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02012-2.2 39 ECP5 and ECP5-5G Family Data Sheet ECP5/ECP5-5G devices contain two types of sysI/O buffer pairs:  Top (Bank 0 and Bank 1) and Bottom (Bank 8 and Bank 4) sysI/O Buffer Pairs (Single-Ended Only) The sysI/O buffers in the Banks at top and bottom of the device consist of ratioed single-ended output drivers and single-ended input buffers. The I/O in these banks are not usually used as a pair, except when used as emulated differential output pair. They are used as individual I/O and be configured as different I/O modes, as long as they are compatible with the VCCIO voltage in the bank. When used as emulated differential outputs, the pair can be used together. The top and bottom side I/O also support hot socketing. They support I/O standards from 3.3 V to 1.2 V. They are ideal for general purpose I/O, or as ADDR/CMD bus for DDR2/DDR3 applications, or for used as emulated differential signaling. Bank 4 I/O only exists in the LFE5-85 device. Bank 8 is a bottom bank that shares with sysConfig I/O. During configuration, these I/O are used for programming the device. Once the configuration is completed, these I/O can be released and you can use these I/O for functional signals in his design.  The top and bottom side pads can be identified by the Lattice Diamond tool. Left and Right (Bank 2, Bank 3, Bank 6, and Bank 7) sysI/O Buffer Pairs (50% Differential and 100% Single-Ended Outputs) The sysI/O buffer pairs in the left and right banks of the device consist of two single-ended output drivers, two single-ended input buffers (both ratioed and referenced) and half of the sysI/O buffer pairs (PIOA/B pairs) also has a high-speed differential output driver. One of the referenced input buffers can also be configured as a differential input. In these banks the two pads in the pair are described as true and comp, where the true pad is associated with the positive side of the differential I/O, and the comp (complementary) pad is associated with the negative side of the differential I/O. In addition, programmable on-chip input termination (parallel or differential, static or dynamic) is supported on these sides, which is required for DDR3 interface. However, there is no support for hot-socketing for the I/O pins located on the left and right side of the device as the PCI clamp is always enabled on these pins. LVDS differential output drivers are available on 50% of the buffer pairs on the left and right banks. 2.14.2. Typical sysI/O I/O Behavior during Power-up The internal Power-On-Reset (POR) signal is deactivated when VCC, VCCIO8 and VCCAUX have reached satisfactory levels. After the POR signal is deactivated, the FPGA core logic becomes active. It is your responsibility to ensure that all other VCCIO banks are active with valid input logic levels to properly control the output logic states of all the I/O banks that are critical to the application. For more information about controlling the output logic state with valid input logic levels during power-up in ECP5/ECP5-5G devices, see the list of technical documentation in Supplemental Information section. The VCC and VCCAUX supply the power to the FPGA core fabric, whereas the VCCIO supplies power to the I/O buffers. In order to simplify system design while providing consistent and predictable I/O behavior, it is recommended that the I/O buffers be powered-up prior to the FPGA core fabric. VCCIO supplies should be powered-up before or together with the VCC and VCCAUX supplies. 2.14.3. Supported sysI/O Standards The ECP5/ECP5-5G sysI/O buffer supports both single-ended and differential standards. Single-ended standards can be further subdivided into LVCMOS, LVTTL and other standards. The buffers support the LVTTL, LVCMOS 1.2 V, 1.5 V, 1.8V, 2.5 V and 3.3 V standards. In the LVCMOS and LVTTL modes, the buffer has individual configuration options for drive strength, slew rates, bus maintenance (weak pull-up or weak pull-down) and open drain. Other single-ended standards supported include SSTL and HSUL. Differential standards supported include LVDS, differential SSTL and differential HSUL. For further information on utilizing the sysI/O buffer to support a variety of standards, refer to ECP5 and ECP55G sysI/O Usage Guide (FPGA-TN-02032). © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 40 FPGA-DS-02012-2.2 ECP5 and ECP5-5G Family Data Sheet 2.14.4. On-Chip Programmable Termination The ECP5/ECP5-5G devices support a variety of programmable on-chip terminations options, including:  Dynamically switchable Single-Ended Termination with programmable resistor values of 50 Ω, 75 Ω, or 150 Ω.  Common mode termination of 100 Ω for differential inputs. Zo = 50 V CCIO Zo = 50 Ω, 75 Ω, or 150 Ω to V CCIO /2 TERM control Zo Zo 2Zo Zo + - VREF OFF-chip + - Zo OFF-chip ON-chip Parallel Single-Ended Input ON-chip Differential Input Figure 2.26. On-Chip Termination See Table 2.12 for termination options for input modes. Table 2.12. On-Chip Termination Options for Input Modes IO_TYPE Terminate to VCCIO/2* Differential Termination Resistor* LVDS25 — 100 BLVDS25 — 100 MLVDS — 100 LVPECL33 — 100 subLVDS — 100 SLVS — 100 HSUL12 HSUL12D SSTL135_I / II SSTL135D_I / II SSTL15_I / II SSTL15D_I / II SSTL18_I / II SSTL18D_I / II 50, 75, 150 — — 100 50, 75, 150 — — 100 50, 75, 150 — — 100 50, 75, 150 — — 100 *Notes:   TERMINATE to VCCIO/2 (Single-Ended) and DIFFRENTIAL TERMINATION RESISTOR when turned on can only have one setting per bank. Only left and right banks have this feature. Use of TERMINATE to VCCIO/2 and DIFFRENTIAL TERMINATION RESISTOR are mutually exclusive in an I/O bank. On-chip termination tolerance ±20%. Refer to ECP5 and ECP5-5G sysI/O Usage Guide (FPGA-TN-02032) for on-chip termination usage and value ranges. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02012-2.2 41 ECP5 and ECP5-5G Family Data Sheet 2.14.5. Hot Socketing ECP5/ECP5-5G devices have been carefully designed to ensure predictable behavior during power-up and power-down. During power-up and power-down sequences, the I/O remain in tristate until the power supply voltage is high enough to ensure reliable operation. In addition, leakage into I/O pins is controlled within specified limits. See the Hot Socketing Specifications section. 2.15. SERDES and Physical Coding Sublayer LFE5UM/LFE5UM5G devices feature up to four channels of embedded SERDES/PCS arranged in dual-channel blocks at the bottom of the devices. Each channel supports up to 3.2 Gb/s (ECP5), or up to 5 Gb/s (ECP5-5G) data rate. Figure 2.27 shows the position of the dual blocks for the LFE5-85. Table 2.13 shows the location of available SERDES Duals for all devices. The LFE5UM/LFE5UM5G SERDES/PCS supports a range of popular serial protocols, including:  PCI Express Gen1 and Gen2 (2.5 Gb/s) on ECP5UM; Gen 1, Gen2 (2.5 Gb/s and 5 Gb/s) on ECP5-5G  Ethernet (XAUI, GbE – 1000 Base CS/SX/LX and SGMII)  SMPTE SDI (3G-SDI, HD-SDI, SD-SDI)  CPRI (E.6.LV: 614.4 Mb/s, E.12.LV: 1228.8 Mb/s, E.24.LV: 2457.6 Mb/s, E.30.LV: 3072 Mb/s), also E.48.LV2:4915 Mb/s in ECP5-5G  JESD204A/B – ADC and DAC converter interface: 312.5 Mb/s to 3.125 Gb/s (ECP5) / 5 Gb/s (ECP5-5G) Each dual contains two dedicated SERDES for high speed, full duplex serial data transfer. Each dual also has a PCS block that interfaces to the SERDES channels and contains protocol specific digital logic to support the standards listed above. The PCS block also contains interface logic to the FPGA fabric. All PCS logic for dedicated protocol support can also be bypassed to allow raw 8-bit or 10-bit interfaces to the FPGA fabric. Even though the SERDES/PCS blocks are arranged in duals, multiple baud rates can be supported within a dual with the use of dedicated, per channel /1, /2 and /11 rate dividers. Additionally, two duals can be arranged together to form x4 channel link. ECP5UM devices and ECP5-5G devices are pin-to-pin compatible. But, the ECP5UM devices require 1.1 V on VCCA, VCCHRX and VCCHTX supplies. ECP5-5G devices require 1.2 V on these supplies. When designing either family device with migration in mind, these supplies need to be connected such that it is possible to adjust the voltage level on these supplies. When a SERDES Dual in a 2-Dual device is not used, the power VCCA power supply for that Dual should be connected. It is advised to connect the VCCA of unused channel to VCC core power supply if you do not use the Dual at all, or it should be connected to a different regulated supply, if that Dual may be used in the future. For an unused channel in a Dual, it is advised to connect the VCCHTX to VCCA, and you can leave VCCHRX unconnected. For information on how to use the SERDES/PCS blocks to support specific protocols, as well on how to combine multiple protocols and baud rates within a device, refer to ECP5 and ECP5-5G SERDES/PCS Usage Guide ( FPGA-TN02206). © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 42 FPGA-DS-02012-2.2 ECP5 and ECP5-5G Family Data Sheet sysI/O Bank 1 sysI/O Bank 6 sysI/O Bank 3 sysI/O Bank 7 sysI/O Bank 2 sysI/O Bank 0 CH0 CH1 CH0 sysI/O Bank 8 CH1 SERDES/ PCS Dual 1 SERDES/ PCS Dual 0 sysI/O Bank 4 Figure 2.27. SERDES/PCS Duals (LFE5UM/LFE5UM5G-85) Table 2.13. LFE5UM/LFE5UM5G SERDES Standard Support Standard Data Rate (Mb/s) Number of General/Link Width Encoding Style PCI Express 1.1 and 2.0 2.02 2500 5000 2 1250 1250 2500 3125 614.4 1228.8 2457.6 3072.0 4915.2 2 270 1483.5 1485 x1, x2, x4 x1, x2 x1 x1 x1 x4 x1, x2, x4 8b10b 8b10b 8b10b 8b10b 8b10b 8b10b 8b10b x1 8b10b x1 NRZI/Scrambled x1 NRZI/Scrambled x1 NRZI/Scrambled Gigabit Ethernet SGMII XAUI CPRI-1 CPRI-2 CPRI-3 CPRI-4 CPRI-5 SD-SDI (259M, 344M) 1 HD-SDI (292M) 3G-SDI (424M) 2967 2970 5000 3125 — — JESD204A/B x1 8b/10b Notes: 1. For SD-SDI rate, the SERDES is bypassed and SERDES input signals are directly connected to the FPGA routing. 2. For ECP5-5G family devices only. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02012-2.2 43 ECP5 and ECP5-5G Family Data Sheet Table 2.14. Available SERDES Duals per LFE5UM/LFE5UM5G Devices Package LFE5UM/LFE5UM5G-25 LFE5UM/LFE5UM5G-45 LFE5UM/LFE5UM5G-85 285 csfBGA 1 1 1 381 caBGA 1 2 2 554 caBGA — 2 2 756 caBGA — — 2 2.15.1. SERDES Block A SERDES receiver channel may receive the serial differential data stream, equalize the signal, perform Clock and Data Recovery (CDR) and de-serialize the data stream before passing the 8- or 10-bit data to the PCS logic. The SERDES transmitter channel may receive the parallel 8- or 10-bit data, serialize the data and transmit the serial bit stream through the differential drivers. Figure 2.28 shows a single-channel SERDES/PCS block. Each SERDES channel provides a recovered clock and a SERDES transmit clock to the PCS block and to the FPGA core logic. Each transmit channel, receiver channel, and SERDES PLL shares the same power supply (VCCA). The output and input buffers of each channel have their own independent power supplies (VCCHTX and VCCHRX). SERDES PCS FPGA Core Recovered Clock* RX_REFCLK HDINP Recovered Clock Equalizer HDINN Clock/Data Recovery Receiver TX REFCLK Deserializer 1:8/1:10 Polarity Adjust Bypass CTC FIFO Word Alignment 8b/10b Decoder Downsample FIFO Bypass Bypass Receive Clock TX PLL (Per Dual) SERDES Tx Clock De-emphasis Tx Driver HDOUTP Serializer 8:1/10:1 HDOUTN Receive Data Polarity Adjust 8b/10b Encoder Upsample FIFO Transmit Data Bypass Transmit Clock Bypass * 1/8 or 1/10 line rate Figure 2.28. Simplified Channel Block Diagram for SERDES/PCS Block 2.15.2. PCS As shown in Figure 2.28, the PCS receives the parallel digital data from the deserializer and selects the polarity, performs word alignment, decodes (8b/10b), provides Clock Tolerance Compensation and transfers the clock domain from the recovered clock to the FPGA clock via the Down Sample FIFO. For the transmit channel, the PCS block receives the parallel data from the FPGA core, encodes it with 8b/10b, selects the polarity and passes the 8/10-bit data to the transmit SERDES channel. The PCS also provides bypass modes that allow a direct 8-bit or 10-bit interface from the SERDES to the FPGA logic. The PCS interface to the FPGA can also be programmed to run at 1/2 speed for a 16-bit or 20-bit interface to the FPGA logic. Some of the enhancements in LFE5UM/LFE5UM5G SERDES/PCS include:  Higher clock/channel granularity: Dual channel architecture provides more clock resource per channel.  Enhanced Tx de-emphasis: Programmable pre- and post-cursors improves Tx output signaling  Bit-slip function in PCS: Improves logic needed to perform Word Alignment function Refer to ECP5 and ECP5-5G SERDES/PCS Usage Guide (FPGA-TN-02206) for more information. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 44 FPGA-DS-02012-2.2 ECP5 and ECP5-5G Family Data Sheet 2.15.3. SERDES Client Interface Bus The SERDES Client Interface (SCI) is an IP interface that allows you to change the configuration thru this interface. This is useful when you need to fine-tune some settings, such as input and output buffer that need to be optimized based on the channel characteristics. It is a simple register configuration interface that allows SERDES/PCS configuration without power cycling the device. The Diamond design tools support all modes of the PCS. Most modes are dedicated to applications associated with a specific industry standard data protocol. Other more general purpose modes allow you to define their own operation. With these tools, you can define the mode for each dual in a design. Popular standards such as 10 Gb Ethernet, x4 PCI Express and 4x Serial RapidIO can be implemented using IP (available through Lattice), with two duals (Four SERDES channels and PCS) and some additional logic from the core. The LFE5UM/LFE5UM5G devices support a wide range of protocols. Within the same dual, the LFE5UM/ LFE5UM5G devices support mixed protocols with semi-independent clocking as long as the required clock frequencies are integer x1, x2, or x11 multiples of each other. Table 2.15 lists the allowable combination of primary and secondary protocol combinations. 2.16. Flexible Dual SERDES Architecture The LFE5UM/LFE5UM5G SERDES architecture is a dual channel-based architecture. For most SERDES settings and standards, the whole dual (consisting of two SERDES channels) is treated as a unit. This helps in silicon area savings, better utilization, higher granularity on clock/SERDES channel and overall lower cost. However, for some specific standards, the LFE5UM/LFE5UM5G dual-channel architecture provides flexibility; more than one standard can be supported within the same dual. Table 2.15 lists the standards that can be mixed and matched within the same dual. In general, the SERDES standards whose nominal data rates are either the same or a defined subset of each other, can be supported within the same dual. The two Protocol columns of the table define the different combinations of protocols that can be implemented together within a Dual. Table 2.15. LFE5UM/LFE5UM5G Mixed Protocol Support Protocol Protocol PCI Express 1.1 with SGMII PCI Express 1.1 with Gigabit Ethernet CPRI-3 with CPRI-2 and CPRI-1 3G-SDI with HD-SDI and SD-SDI There are some restrictions to be aware of when using spread spectrum clocking. When a dual shares a PCI Express x1 channel with a non-PCI Express channel, ensure that the reference clock for the dual is compatible with all protocols within the dual. For example, a PCI Express spread spectrum reference clock is not compatible with most Gigabit Ethernet applications because of tight CTC ppm requirements. While the LFE5UM/LFE5UM5G architecture allows the mixing of a PCI Express channel and a Gigabit Ethernet, or SGMII channel within the same dual, using a PCI Express spread spectrum clocking as the transmit reference clock causes a violation of the Gigabit Ethernet, and SGMII transmit jitter specifications. For further information on SERDES, refer to ECP5 and ECP5-5G SERDES/PCS Usage Guide (FPGA-TN-02206). 2.17. IEEE 1149.1-Compliant Boundary Scan Testability All ECP5/ECP5-5G devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant Test Access Port (TAP). This allows functional testing of the circuit board on which the device is mounted through a serial scan path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in and loaded directly onto test nodes, or test data to be captured and shifted out for verification. The test access port consists of dedicated I/O: TDI, TDO, TCK, and TMS. The test access port uses VCCIO8 for power supply. For more information, refer to ECP5 and ECP5-5G sysCONFIG Usage Guide (FPGA-TN-02039). © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02012-2.2 45 ECP5 and ECP5-5G Family Data Sheet 2.18. Device Configuration All ECP5/ECP5-5G devices contain two ports that can be used for device configuration. The Test Access Port (TAP), which supports bit-wide configuration, and the sysCONFIG port, support dual-byte, byte and serial configuration. The TAP supports both the IEEE Standard 1149.1 Boundary Scan specification and the IEEE Standard 1532 In-System Configuration specification. There are 11 dedicated pins for TAP and sysConfig supports (TDI, TDO, TCK, TMS, CFG[2:0], PROGRAMN, DONE, INITN, and CCLK). The remaining sysCONFIG pins are used as dual function pins. Refer to ECP5 and ECP5-5G sysCONFIG Usage Guide (FPGA-TN-02039) for more information about using the dual-use pins as general purpose I/O. There are various ways to configure an ECP5/ECP5-5G device:  JTAG  Standard Serial Peripheral Interface (SPI) – Interface to boot PROM Support x1, x2, x4 wide SPI memory interfaces.  System microprocessor to drive a x8 CPU port SPCM mode  System microprocessor to drive a serial slave SPI port (SSPI mode)  Slave Serial model (SCM) On power-up, the FPGA SRAM is ready to be configured using the selected sysCONFIG port. Once a configuration port is selected, it remains active throughout that configuration cycle. The IEEE 1149.1 port can be activated any time after power-up by sending the appropriate command through the TAP port. ECP5/ECP5-5G devices also support the Slave SPI Interface. In this mode, the FPGA behaves like a SPI Flash device (slave mode) with the SPI port of the FPGA to perform read-write operations. 2.18.1. Enhanced Configuration Options ECP5/ECP5-5G devices have enhanced configuration features such as: decryption support, decompression support, TransFR™ I/O and dual-boot and multi-boot image support. 2.18.1.1. TransFR (Transparent Field Reconfiguration) TransFR I/O (TFR) is a unique Lattice technology that allows you to update their logic in the field without interrupting system operation using a single ispVM command. TransFR I/O allows I/O states to be frozen during device configuration. This allows the device to be field updated with a minimum of system disruption and downtime. Refer to Minimizing System Interruption During Configuration Using TransFR Technology (FPGA-TN-02198) for details. 2.18.1.2. Dual-Boot and Multi-Boot Image Support Dual-boot and multi-boot images are supported for applications requiring reliable remote updates of configuration data for the system FPGA. After the system is running with a basic configuration, a new boot image can be downloaded remotely and stored in a separate location in the configuration storage device. Any time after the update the ECP5/ECP5-5G devices can be re-booted from this new configuration file. If there is a problem, such as corrupt data during download or incorrect version number with this new boot image, the ECP5/ECP5-5G device can revert back to the original backup golden configuration and try again. This all can be done without power cycling the system. For more information, refer to ECP5 and ECP5-5G sysCONFIG Usage Guide (FPGA-TN-02039). 2.18.2. Single Event Upset (SEU) Support ECP5/ECP5-5G devices support SEU mitigation with three supporting functions:  SED – Soft Error Detect  SEC – Soft Error Correction  SEI – Soft Error Injection ECP5/ECP5-5G devices have dedicated logic to perform Cycle Redundancy Code (CRC) checks. During configuration, the configuration data bitstream can be checked with the CRC logic block. In addition, the ECP5/ECP5-5G device can also be programmed to utilize a Soft Error Detect (SED) mode that checks for soft errors in configuration SRAM. The SED operation can be run in the background during user mode. If a soft error occurs, during user mode (normal operation) the device can be programmed to generate an error signal. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 46 FPGA-DS-02012-2.2 ECP5 and ECP5-5G Family Data Sheet When an error is detected, and your error handling software determines the error did not create any risk to the system operation, the SEC tool allows the device to be re-configured in the background to correct the affected bit. This operation allows the user functions to continue to operate without stopping the system function. Additional SEI tool is also available in the Diamond Software, by creating a frame of data to be programmed into the device in the background with one bit changed, without stopping the user functions on the device. This emulates an SEU situation, allowing you to test and monitor its error handling software. For further information on SED support, refer to LatticeECP3, ECP5 and ECP5-5G Soft Error Detection (SED)/Correction (SEC) Usage Guide ( FPGA-TN-02207). 2.18.3. On-Chip Oscillator Every ECP5/ECP5-5G device has an internal CMOS oscillator which is used to derive a Master Clock (MCLK) for configuration. The oscillator and the MCLK run continuously and are available to user logic after configuration is completed. The software default value of the MCLK is nominally 2.4 MHz. Table 2.16 lists all the available MCLK frequencies. When a different Master Clock is selected during the design process, the following sequence takes place: 1. Device powers up with a nominal Master Clock frequency of 2.4 MHz. 2. During configuration, you can select a different master clock frequency. 3. The Master Clock frequency changes to the selected frequency once the clock configuration bits are received. 4. If you do not select a master clock frequency, then the configuration bitstream defaults to the MCLK frequency of 2.4 MHz. This internal oscillator is available to you by routing it as an input clock to the clock tree. For further information on the use of this oscillator for configuration or user mode, refer to ECP5 and ECP5-5G sysCONFIG Usage Guide (FPGA-TN02039) and ECP5 and ECP5-5G sysClock PLL/DLL Design and Usage Guide (FPGA-TN-02200). Table 2.16. Selectable Master Clock (MCLK) Frequencies during Configuration (Nominal) MCLK Frequency (MHz) 2.4 4.8 9.7 19.4 38.8 62 2.19. Density Shifting The ECP5/ECP5-5G family is designed to ensure that different density devices in the same family and in the same package have the same pinout. Furthermore, the architecture ensures a high success rate when performing design migration from lower density devices to higher density devices. In many cases, it is also possible to shift a lower utilization design targeted for a high-density device to a lower density device. However, the exact details of the final resource utilization impacts the likelihood of success in each case. An example is that some user I/O may become No Connects in smaller devices in the same package. Refer to the ECP5/ECP5-5G Pin Migration Tables and Diamond software for specific restrictions and limitations. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02012-2.2 47 ECP5 and ECP5-5G Family Data Sheet 3. DC and Switching Characteristics 3.1. Absolute Maximum Ratings Table 3.1. Absolute Maximum Ratings Symbol Parameter Min Max Unit VCC Supply Voltage –0.5 1.32 V VCCA Supply Voltage –0.5 1.32 V VCCAUX, VCCAUXA Supply Voltage –0.5 2.75 V VCCIO Supply Voltage –0.5 3.63 V — Input or I/O Transient Voltage Applied –0.5 3.63 V VCCHRX, VCCHTX SERDES RX/TX Buffer Supply Voltages –0.5 1.32 V — Voltage Applied on SERDES Pins –0.5 1.80 V TA Storage Temperature (Ambient) –65 150 °C TJ Junction Temperature — +125 °C Notes: 1. Stress above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. 2. Compliance with the Lattice Thermal Management document is required. 3. All voltages referenced to GND. 3.2. Recommended Operating Conditions Table 3.2. Recommended Operating Conditions Symbol Parameter Min Max Unit VCC2 Core Supply Voltage 1.045 1.155 V ECP5-5G VCCAUX2, 4 Auxiliary Supply Voltage — 1.14 1.26 V 2.375 2.625 VCCIO2, 3 V I/O Driver Supply Voltage — VREF1 Input Reference Voltage — 1.14 3.465 V 0.5 1.0 V tJCOM Junction Temperature, Commercial Operation — tJIND Junction Temperature, Industrial Operation — 0 85 °C –40 100 SERDES External Power Supply5 °C VCCA SERDES Analog Power Supply ECP5UM 1.045 1.155 V VCCAUXA SERDES Auxiliary Supply Voltage ECP5-5G 1.164 1.236 V — 2.374 2.625 V VCCHRX6 SERDES Input Buffer Power Supply ECP5UM 0.30 1.155 V ECP5-5G 0.30 1.26 V VCCHTX SERDES Output Buffer Power Supply ECP5UM 1.045 1.155 V ECP5-5G 1.14 1.26 V ECP5 Notes: 1. For correct operation, all supplies except VREF must be held in their valid operation range. This is true independent of feature usage. 2. All supplies with same voltage, except SERDES Power Supplies, should be connected together. 3. See recommended voltages by I/O standard in Table 3.4. 4. VCCAUX ramp rate must not exceed 30 mV/µs during power-up when transitioning between 0 V and 3 V. 5. Refer to ECP5 and ECP5-5G SERDES/PCS Usage Guide (FPGA-TN-02206) for information on board considerations for SERDES power supplies. 6. VCCHRX is used for Rx termination. It can be biased to Vcm if external AC coupling is used. This voltage needs to meet all the HDin input voltage level requirements specified in the Rx section of this Data Sheet. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 48 FPGA-DS-02012-2.2 ECP5 and ECP5-5G Family Data Sheet 3.3. Power Supply Ramp Rates Table 3.3. Power Supply Ramp Rates Symbol Parameter Min Typ Max Unit tRAMP Power Supply ramp rates for all supplies 0.01 — 10 V/ms Note: Assumes monotonic ramp rates. 3.4. Power-On-Reset Voltage Levels Table 3.4. Power-On-Reset Voltage Levels Symbol Parameter VPORUP All Devices VPORDN All Devices Min Typ Max Unit Power-On-Reset ramp-up trip point (Monitoring VCC, VCCAUX, and VCCIO8) VCC 0.90 — 1.00 V VCCAUX 2.00 — 2.20 V VCCIO8 0.95 — 1.06 V Power-On-Reset rampdown trip point (Monitoring VCC, and VCCAUX VCC 0.77 — 0.87 V VCCAUX 1.80 — 2.00 V Notes:  These POR trip points are only provided for guidance. Device operation is only characterized for power supply voltages specified under recommended operating conditions.  Only VCCIO8 has a Power-On-Reset ramp up trip point. All other VCCIOs do not have Power-On-Reset ramp up detection.  VCCIO8 does not have a Power-On-Reset ramp down detection. VCCIO8 must remain within the Recommended Operating Conditions to ensure proper operation. 3.5. Power up Sequence Power-On-Reset (POR) puts the ECP5/ECP5-5G device in a reset state. POR is released when VCC, VCCAUX, and VCCIO8 are ramped above the VPORUP voltage, as specified above. VCCIO8 controls the voltage on the configuration I/O pins. If the ECP5/ECP5-5G device is using Master SPI mode to download configuration data from external SPI Flash, it is required to ramp VCCIO8 above VIH of the external SPI Flash, before at least one of the other two supplies (VCC and/or VCCAUX) is ramped to VPORUP voltage level. If the system cannot meet this power up sequence requirement, and requires the VCCIO8 to be ramped last, then the system must keep either PROGRAMN or INITN pin LOW during power up, until VCCIO8 reaches VIH of the external SPI Flash. This ensures the signals driven out on the configuration pins to the external SPI Flash meet the VIH voltage requirement of the SPI Flash. For LFE5UM/LFE5UM5G devices, it is required to power up VCCA, before VCCAUXA is powered up. 3.6. Hot Socketing Specifications Table 3.5. Hot Socketing Specifications Symbol Parameter Condition Min Typ Max Unit IDK_HS Input or I/O Leakage Current for Top and Bottom Banks Only 0 VIN VIH (Max) — — ±1 mA IDK Input or I/O Leakage Current for Left and Right Banks Only 0 VIN < VCCIO — — ±1 mA VCCIO VIN VCCIO + 0.5 V — 18 — mA Notes: 1. VCC, VCCAUX and VCCIO should rise/fall monotonically. 2. IDK is additive to IPU, IPW or IBH. 3. LVCMOS and LVTTL only. 4. Hot socket specification defines when the hot socketed device's junction temperature is at 85 oC or below. When the hot socketed device's junction temperature is above 85 oC, the IDK current can exceed ±1 mA. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02012-2.2 49 ECP5 and ECP5-5G Family Data Sheet 3.7. Hot Socketing Requirements Table 3.6. Hot Socketing Requirements Description Input current per SERDES I/O pin when device is powered down and inputs driven. Input current per HDIN pin when device power supply is off, inputs driven1, 2 Current per HDIN pin when device power ramps up, input driven3 Current per HDOUT pin when device power supply is off, outputs pulled up4 Min Typ Max Unit — — 8 mA — — 15 mA — — 50 mA — — 30 mA Notes: 1. Device is powered down with all supplies grounded, both HDINP and HDINN inputs driven by a CML driver with maximum allowed output VCCHTX, 8b/10b data, no external AC coupling. 2. Each P and N input must have less than the specified maximum input current during hot plug. For a device with 2 DCU, the total input current would be 15 mA * 4 channels * 2 input pins per channel = 120 mA. 3. Device power supplies are ramping up (VCCA and VCCAUX), both HDINP and HDINN inputs are driven by a CML driver with maximum allowed output VCCHTX, 8b/10b data, internal AC coupling. 4. Device is powered down with all supplies grounded. Both HDOUTP and HDOUN outputs are pulled up to VCCHTX by the far end receiver termination of 50 Ω single ended. 3.8. ESD Performance Refer to the ECP5 and ECP5-5G Product Family Qualification Summary for complete qualification data, including ESD performance. 3.9. DC Electrical Characteristics Over Recommended Operating Conditions Table 3.7. DC Electrical Characteristics Symbol Parameter Condition IIL, IIH1, 4 Input or I/O Low Leakage IIH1, 3 Input or I/O High Leakage I/O Active Pull-up Current, sustaining logic HIGH state I/O Active Pull-up Current, pulling down from logic HIGH state I/O Active Pull-down Current, sustaining logic LOW state I/O Active Pull-down Current, pulling up from logic LOW state IPU IPD Min Typ Max Unit 0 VIN VCCIO — VCCIO < VIN VIH(MAX) — — 10 µA — 100 µA 0.7 VCCIO VIN VCCIO –30 — — µA 0 VIN 0.7 VCCIO — — –150 µA 0 VIN  VIL (MAX) 30 — — µA 0 VIN VCCIO — — 150 µA C1 I/O Capacitance2 VCCIO = 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V, VCC = 1.2 V, VIO = 0 to VIH(MAX) — 5 8 pf C2 Dedicated Input Capacitance2 VCCIO = 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V, VCC = 1.2 V, VIO = 0 to VIH(MAX) — 5 7 pf VHYST Hysteresis for Single-Ended Inputs VCCIO = 3.3 V — 300 — mV VCCIO = 2.5 V — 250 — mV Notes: 1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tristated. It is not measured with the output driver active. Bus maintenance circuits are disabled. 2. TA 25 oC, f = 1.0 MHz. 3. Applicable to general purpose I/O in top and bottom banks. 4. When used as VREF, maximum leakage= 25 µA. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 50 FPGA-DS-02012-2.2 ECP5 and ECP5-5G Family Data Sheet 3.10. Supply Current (Static) Over recommended operating conditions. Table 3.8. ECP5/ECP5-5G Supply Current (Static) Symbol Parameter Device Typical Unit 77 mA LFE5UM5G-25F 77 mA LFE5U-45F/LFE5UM-45F 116 mA LFE5UM5G-45F 116 mA LFE5U-85F/LFE5UM-85F 212 mA LFE5UM5G-85F 212 mA LFE5U-12F/LFE5U-25F/LFE5UM-25F/ LFE5UM5G-25F 16 mA LFE5U-45F/LFE5UM-45F/LFE5UM5G-45F 17 mA LFE5U-85F/LFE5UM-85F/LFE5UM5G-85F 26 mA LFE5U-12F/LFE5U-25F/LFE5UM-25F/ LFE5UM5G-25F 0.5 mA LFE5U-45F/LFE5UM-45F/LFE5UM5G-45F 0.5 mA LFE5U-85F/LFE5UM-85F/LFE5UM5G-85F 0.5 mA LFE5UM-25F 11 mA LFE5UM5G-25F 12 mA LFE5UM-45F 9.5 mA LFE5UM5G-45F 11 mA LFE5UM-85F 9.5 mA LFE5UM5G-85F 11 mA LFE5U-12F/LFE5U-25F/LFE5UM-25F ICC Core Power Supply Current ICCAUX ICCIO ICCA Auxiliary Power Supply Current Bank Power Supply Current (Per Bank) SERDES Power Supply Current (Per Dual) Notes:  For further information on supply current, see the list of technical documentation in Supplemental Information section.  Assumes all outputs are tristated, all inputs are configured as LVCMOS and held at the VCCIO or GND.  Frequency 0 Hz.  Pattern represents a test bitstream to consume minimum static power.  TJ = 85 °C, power supplies at nominal voltage.  To determine the ECP5/ECP5-5G peak start-up current, use the Power Calculator tool in the Lattice Diamond Design software. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02012-2.2 51 ECP5 and ECP5-5G Family Data Sheet 3.11. SERDES Power Supply Requirements1, 2, 3 Over recommended operating conditions. Table 3.9. ECP5UM Symbol Description Typ Max Unit Standby (Power Down) ICCA-SB VCCA Power Supply Current (Per Channel) 4 9.5 mA ICCHRX-SB4 VCCHRX, Input Buffer Current (Per Channel) — 0.1 mA ICCHTX-SB VCCHTX, Output Buffer Current (Per Channel) — 0.9 mA Operating (Data Rate = 3.125 Gb/s) ICCA-OP VCCA Power Supply Current (Per Channel) 43 54 mA ICCHRX-OP5 VCCHRX, Input Buffer Current (Per Channel) 0.4 0.5 mA ICCHTX-OP VCCHTX, Output Buffer Current (Per Channel) 10 13 mA VCCA Power Supply Current (Per Channel) 40 50 mA VCCHRX, Input Buffer Current (Per Channel) 0.4 0.5 mA VCCHTX, Output Buffer Current (Per Channel) 10 13 mA VCCA Power Supply Current (Per Channel) 34 43 mA VCCHRX, Input Buffer Current (Per Channel) 0.4 0.5 mA VCCHTX, Output Buffer Current (Per Channel) 10 13 mA VCCA Power Supply Current (Per Channel) 28 38 mA VCCHRX, Input Buffer Current (Per Channel) 0.4 0.5 mA 8 10 mA Operating (Data Rate = 2.5 Gb/s) ICCA-OP ICCHRX-OP 5 ICCHTX-OP Operating (Data Rate = 1.25 Gb/s) ICCA-OP ICCHRX-OP 5 ICCHTX-OP Operating (Data Rate = 270 Mb/s) ICCA-OP ICCHRX-OP ICCHTX-OP 5 VCCHTX, Output Buffer Current (Per Channel) Notes: 1. Rx Equalization enabled, Tx De-emphasis (pre-cursor and post-cursor) disabled 2. Per Channel current is calculated with both channels on in a Dual, and divide current by two. If only one channel is on, current is higher. 3. To calculate with Tx De-emphasis enabled, use the Diamond Power Calculator tool. 4. For ICCHRX-SB, during Standby, input termination on Rx are disabled. 5. For ICCHRX-OP, during operational, the max specified when external AC coupling is used. If externally DC coupled, the power is based on current pulled down by external driver when the input is driven to LOW. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 52 FPGA-DS-02012-2.2 ECP5 and ECP5-5G Family Data Sheet Table 3.10. ECP5-5G Symbol Description Typ Max Unit Standby (Power Down) ICCA-SB VCCA Power Supply Current (Per Channel) 4 9.5 mA ICCHRX-SB4 VCCHRX, Input Buffer Current (Per Channel) — 0.1 mA ICCHTX-SB VCCHTX, Output Buffer Current (Per Channel) — 0.9 mA VCCA Power Supply Current (Per Channel) 58 67 mA VCCHRX, Input Buffer Current (Per Channel) 0.4 0.5 mA VCCHTX, Output Buffer Current (Per Channel) 10 13 mA VCCA Power Supply Current (Per Channel) 48 57 mA VCCHRX, Input Buffer Current (Per Channel) 0.4 0.5 mA VCCHTX, Output Buffer Current (Per Channel) 10 13 mA VCCA Power Supply Current (Per Channel) 44 53 mA VCCHRX, Input Buffer Current (Per Channel) 0.4 0.5 mA VCCHTX, Output Buffer Current (Per Channel) 10 13 mA VCCA Power Supply Current (Per Channel) 36 46 mA VCCHRX, Input Buffer Current (Per Channel) 0.4 0.5 mA VCCHTX, Output Buffer Current (Per Channel) 10 13 mA VCCA Power Supply Current (Per Channel) 30 40 mA VCCHRX, Input Buffer Current (Per Channel) 0.4 0.5 mA 8 10 mA Operating (Data Rate = 5 Gb/s) ICCA-OP ICCHRX-OP 5 ICCHTX-OP Operating (Data Rate = 3.2 Gb/s) ICCA-OP ICCHRX-OP 5 ICCHTX-OP Operating (Data Rate = 2.5 Gb/s) ICCA-OP ICCHRX-OP 5 ICCHTX-OP Operating (Data Rate = 1.25 Gb/s) ICCA-OP ICCHRX-OP 5 ICCHTX-OP Operating (Data Rate = 270 Mb/s) ICCA-OP ICCHRX-OP 5 ICCHTX-OP VCCHTX, Output Buffer Current (Per Channel) Notes: 1. Rx Equalization enabled, Tx De-emphasis (pre-cursor and post-cursor) disabled 2. Per Channel current is calculated with both channels on in a Dual, and divide current by two. If only one channel is on, current is higher. 3. To calculate with Tx De-emphasis enabled, use the Diamond Power Calculator tool. 4. For ICCHRX-SB, during Standby, input termination on Rx are disabled. 5. For ICCHRX-OP, during operational, the max specified when external AC coupling is used. If externally DC coupled, the power is based on current pulled down by external driver when the input is driven to LOW. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02012-2.2 53 ECP5 and ECP5-5G Family Data Sheet 3.12. sysI/O Recommended Operating Conditions Table 3.11. sysI/O Recommended Operating Conditions VCCIO Standard VREF (V) Min Typ Max Min Typ Max LVCMOS331 3.135 3.3 3.465 — — — LVCMOS33D Output 3.135 3.3 3.465 — — — LVCMOS25D Output 2.375 2.5 2.625 — — — LVCMOS251 2.375 2.5 2.625 — — — LVCMOS18 1.71 1.8 1.89 — — — LVCMOS15 1.425 1.5 1.575 — — — LVCMOS121 1.14 1.2 1.26 — — — LVTTL331 3.135 3.3 3.465 — — — SSTL15_I, _II2 1.43 1.5 1.57 0.68 0.75 0.9 SSTL18_I, _II2 1.71 1.8 1.89 0.833 0.9 0.969 SSTL135_I, _II2 1.28 1.35 1.42 0.6 0.675 0.75 HSUL122 1.14 1.2 1.26 0.588 0.6 0.612 MIPI D-PHY LP Input3, 5 1.425 1.5 1.575 — — — LVDS251, 3 2.375 2.5 2.625 — — — — — — — — — subLVS3 (Input only) SLVS3 (Input — — — — — — LVDS25E Output 2.375 2.5 2.625 — — — MLVDS251, 3 2.375 2.5 2.625 — — — MLVDS25E Output 2.375 2.5 2.625 — — — LVPECL331, 3 3.135 3.3 3.465 — — — LVPECL33E Output 3.135 3.3 3.465 — — — BLVDS251, 3 2.375 2.5 2.625 — — — BLVDS25E Output 2.375 2.5 2.625 — — — HSULD12D2, 3 1.14 1.2 1.26 — — — SSTL135D_I, II2, 3 1.28 1.35 1.42 — — — II2, 3 1.43 1.5 1.57 — — — 1.71 1.8 1.89 — — — SSTL15D_I, only) SSTL18D_I1, 2, 3, II1, 2, 3 Notes: 1. For input voltage compatibility, refer to ECP5 and ECP5-5G sysI/O Usage Guide (FPGA-TN-02032). 2. VREF is required when using Differential SSTL and HSUL to interface to DDR/LPDDR memories. 3. These differential inputs use LVDS input comparator, which uses VCCAUX power 4. All differential inputs and LVDS25 output are supported in the Left and Right banks only. Refer to ECP5 and ECP5-5G sysI/O Usage Guide (FPGA-TN-02032) for details. 5. MIPI D-PHY LP input can be implemented by powering VCCIO to 1.5 V, and select MIPI LP primitive to meet MIPI Alliance spec on VIH and VIL. It can also be implemented as LVCMOS12 with VCCIO at 1.2 V, which would meet VIH/VIL spec on LVCMOS12. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 54 FPGA-DS-02012-2.2 ECP5 and ECP5-5G Family Data Sheet 3.13. sysI/O Single-Ended DC Electrical Characteristics Table 3.12. Single-Ended DC Characteristics Input/Output Standard VIL VIH Min (V) Max (V) Min (V) Max (V) VOL Max (V) VOH Min (V) IOL1 (mA) LVCMOS33 –0.3 0.8 2.0 3.465 0.4 VCCIO – 0.4 16, 12, 8, 4 LVCMOS25 –0.3 0.7 1.7 3.465 0.4 VCCIO – 0.4 12, 8, 4 –16, –12, –8, –4 –12, –8, –4 LVCMOS18 –0.3 0.35 VCCIO 0.65 VCCIO 3.465 0.4 VCCIO – 0.4 12, 8, 4 –12, –8, –4 LVCMOS15 –0.3 0.35 VCCIO 0.65 VCCIO 3.465 0.4 VCCIO – 0.4 8, 4 –8, –4 LVCMOS12 –0.3 0.35 VCCIO 0.65 VCCIO 3.465 0.4 VCCIO – 0.4 8, 4 –8, –4 LVTTL33 SSTL18_I (DDR2 Memory) SSTL18_II –0.3 –0.3 –0.3 0.8 VREF – 0.125 VREF – 0.125 VREF – 0.1 IOH1 (mA) 2.0 3.465 0.4 VCCIO – 0.4 16, 12, 8, 4 –16, –12, –8, –4 VREF + 0.125 3.465 0.4 VCCIO – 0.4 6.7 –6.7 VREF + 0.125 3.465 0.28 VCCIO – 0.28 13.4 –13.4 SSTL15 _I VREF + 0.1 VCCIO – 0.31 –0.3 3.465 0.31 7.5 –7.5 (DDR3 Memory) SSTL15_II VREF – 0.1 VREF + 0.1 VCCIO – 0.31 –0.3 3.465 0.31 8.8 –8.8 (DDR3 Memory) SSTL135_I VREF – 0.09 VREF + 0.09 VCCIO – 0.27 –0.3 3.465 0.27 7 –7 (DDR3L Memory) SSTL135_II VREF – 0.09 VREF + 0.09 VCCIO – 0.27 –0.3 3.465 0.27 8 –8 (DDR3L Memory) MIPI D-PHY (LP)3 –0.3 0.55 0.88 3.465 — — — — HSUL12 VREF – 0.1 VREF + 0.1 VCCIO – 0.3 –0.3 3.465 0.3 4 –4 (LPDDR2/3 Memory) Notes: 1. For electromigration, the average DC current drawn by the I/O pads within a bank of I/O shall not exceed 10 mA per I/O (All I/O used in the same VCCIO). 2. Not all I/O types are supported in all banks. Refer to ECP5 and ECP5-5G sysI/O Usage Guide (FPGA-TN-02032) for details. 3. MIPI D-PHY LP input can be implemented by powering VCCIO to 1.5 V, and select MIPI LP primitive to meet MIPI Alliance spec on VIH and VIL. It can also be implemented as LVCMOS12 with VCCIO at 1.2 V, which would meet VIH/VIL spec on LVCMOS12. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02012-2.2 55 ECP5 and ECP5-5G Family Data Sheet 3.14. sysI/O Differential Electrical Characteristics 3.14.1. LVDS Over recommended operating conditions. Table 3.13. LVDS Parameter Description Test Conditions VINP, VINM Input Voltage — Min Typ Max Unit 0 — 2.4 V VCM Input Common Mode Voltage VTHD Differential Input Threshold Half the sum of the two Inputs 0.05 — 2.35 V Difference between the two Inputs ±100 — — mV IIN Input Current Power On or Power Off — VOH Output High Voltage for VOP or VOM RT = 100 Ω — — ±10 µA 1.38 1.60 V VOL Output Low Voltage for VOP or VOM RT = 100 Ω 0.9 V 1.03 — V VOD Output Voltage Differential (VOP - VOM), RT = 100 Ω 250 350 450 mV VOD — — 50 mV VOS Change in VOD Between High and Low Output Voltage Offset 1.125 1.25 1.375 V VOS Change in VOS Between H and L — — 50 mV — 12 mA — (VOP + VOM)/2, RT = 100 Ω — VOD = 0 V Driver outputs shorted to — each other Note: On the left and right sides of the device, this specification is valid only for VCCIO = 2.5 V or 3.3 V. ISAB Output Short Circuit Current 3.14.2. SSTLD All differential SSTL outputs are implemented as a pair of complementary single-ended outputs. All allowable single-ended output classes (class I and class II) are supported in this mode. 3.14.3. LVCMOS33D All I/O banks support emulated differential I/O using the LVCMOS33D I/O type. This option, along with the external resistor network, provides the system designer the flexibility to place differential outputs on an I/O bank with 3.3 V VCCIO. The default drive current for LVCMOS33D output is 12 mA with the option to change the device strength to 4 mA, 8 mA, 12 mA, or 16 mA. Follow the LVCMOS33 specifications for the DC characteristics of the LVCMOS33D. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 56 FPGA-DS-02012-2.2 ECP5 and ECP5-5G Family Data Sheet 3.14.4. LVDS25E The top and bottom sides of ECP5/ECP5-5G devices support LVDS outputs via emulated complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The scheme shown in Figure 3.1 is one possible solution for point-to-point signals. VCCIO = 2.5 V (±5%) RS = 158 (±1%) 8 mA VCCIO = 2.5 V (±5%) RS = 158 (±1%) RS = 140 (±1%) RS = 100 (±1%) 8 mA Transmission line, Zo = 100 ON-chip differential OFF-chip ON-chip OFF-chip Figure 3.1. LVDS25E Output Termination Example Table 3.14. LVDS25E DC Conditions Parameter Description VCCIO Output Driver Supply (±5%) Typical Unit 2.50 V ZOUT RS Driver Impedance 20  Driver Series Resistor (±1%) 158  RP Driver Parallel Resistor (±1%) 140  RT Receiver Termination (±1%) 100 VOH Output High Voltage 1.43  V VOL Output Low Voltage 1.07 V VOD Output Differential Voltage 0.35 V VCM Output Common Mode Voltage 1.25 V ZBACK Back Impedance 100.5 IDC DC Output Current 6.03  mA Note: For input buffer, see Table 3.13. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02012-2.2 57 ECP5 and ECP5-5G Family Data Sheet 3.14.5. BLVDS25 The ECP5/ECP5-5G devices support the BLVDS standard. This standard is emulated using complementary LVCMOS outputs in conjunction with a parallel external resistor across the driver outputs. BLVDS is intended for use when multi-drop and bi-directional multi-point differential signaling is required. The scheme shown in Figure 3.2 is one possible solution for bi-directional multi-point differential signals. Heavily loaded backplane, effective Zo ~ 45 Ω to 90 Ω differential 2.5 V R S = 90 Ω 2.5 V R S = 90 Ω 16 mA 16 mA 45 Ω – 90 Ω R TL 2.5 V R TR 45 Ω – 90 Ω 2.5 V 16 mA 16 mA . R. =.90 Ω R S = 90 Ω S 2.5 V + + – 2.5 V 16 mA 16 mA – R S = 90 Ω R S = 90 Ω 2.5 V + – + R S = 90 Ω R S = 90 Ω 2.5 V 16 mA – 16 mA Figure 3.2. BLVDS25 Multi-point Output Example Over recommended operating conditions. Table 3.15. BLVDS25 DC Conditions Parameter Description VCCIO Output Driver Supply (±5%) ZOUT Typical Unit Zo = 45  2.50 Zo = 90  2.50 Driver Impedance 10.00 10.00  RS Driver Series Resistor (±1%) 90.00 90.00  RTL Driver Parallel Resistor (±1%) 45.00 90.00  RTR Receiver Termination (±1%) 45.00 90.00  VOH Output High Voltage 1.38 1.48 V VOL Output Low Voltage 1.12 1.02 V VOD Output Differential Voltage 0.25 0.46 V VCM Output Common Mode Voltage 1.25 1.25 V IDC DC Output Current 11.24 10.20 mA V Note: For input buffer, see Table 3.13. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 58 FPGA-DS-02012-2.2 ECP5 and ECP5-5G Family Data Sheet 3.14.6. LVPECL33 The ECP5/ECP5-5G devices support the differential LVPECL standard. This standard is emulated using complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The LVPECL input standard is supported by the LVDS differential input buffer. The scheme shown in Figure 3.3 is one possible solution for point-to-point signals. VCCIO = 3.3 V (±5%) RS = 93.1 Ω (±1%) 16 mA VCCIO = 3.3 V (±5%) RP = 196 Ω (±1%) RS = 93.1 Ω (±1%) 16 mA + RT = 100 Ω (±1%) – Transmission line, Zo = 100 Ω differential On-chip Off-chip Off-chip On-chip Figure 3.3. Differential LVPECL33 Over recommended operating conditions. Table 3.16. LVPECL33 DC Conditions Parameter Description VCCIO Output Driver Supply (±5%) ZOUT Driver Impedance RS RP RT VOH Typical Unit 3.30 V 10  Driver Series Resistor (±1%) 93  Driver Parallel Resistor (±1%) 196  Receiver Termination (±1%) 100 Output High Voltage 2.05  V VOL Output Low Voltage 1.25 V VOD Output Differential Voltage 0.80 V VCM Output Common Mode Voltage 1.65 V ZBACK Back Impedance 100.5  IDC DC Output Current 12.11 mA Note: For input buffer, see Table 3.13. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02012-2.2 59 ECP5 and ECP5-5G Family Data Sheet 3.14.7. MLVDS25 The ECP5/ECP5-5G devices support the differential MLVDS standard. This standard is emulated using complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The MLVDS input standard is supported by the LVDS differential input buffer. The scheme shown in Figure 3.4 is one possible solution for MLVDS standard implementation. Resistor values in the figure are industry standard values for 1% resistors. Heavily loaded backplace, effective Zo~50 Ω to 70 Ω differential 2.5 V 2.5 V R S = 35 Ω R S = 35 Ω 16 mA 16 mA OE R TL 50 Ω to 70 Ω ±1% 50 Ω to 70 Ω ±1% OE R TR 2.5 V 2.5 V 16 mA 16 mA OE R S = 35 Ω R S = 35 Ω R S = 35 Ω R S = 35 Ω R S = 35 Ω OE R S = 35 Ω + –- OE 16 mA 2.5 V OE OE 2.5 V – 2.5 V + OE 16 mA + 2.5 V – + – 1 6 mA 16 mA Figure 3.4. MLVDS25 (Multipoint Low Voltage Differential Signaling) Table 3.17. MLVDS25 DC Conditions Parameter Description VCCIO Typical Unit Zo=50  Zo=70  Output Driver Supply (±5%) 2.50 2.50 V ZOUT Driver Impedance 10.00 10.00  RS Driver Series Resistor (±1%) 35.00 35.00  RTL Driver Parallel Resistor (±1%) 50.00 70.00  RTR Receiver Termination (±1%) 50.00 70.00 VOH Output High Voltage 1.52 1.60  V VOL Output Low Voltage 0.98 0.90 V VOD Output Differential Voltage 0.54 0.70 V VCM Output Common Mode Voltage 1.25 1.25 V IDC DC Output Current 21.74 20.00 mA Note: For input buffer, see Table 3.13. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 60 FPGA-DS-02012-2.2 ECP5 and ECP5-5G Family Data Sheet 3.14.8. SLVS Scalable Low-Voltage Signaling (SLVS) is based on a point-to-point signaling method defined in the JEDEC JESD8-13 (SLVS-400) standard. This standard evolved from the traditional LVDS standard and relies on the advantage of its use of smaller voltage swings and a lower common-mode voltage. The 200 mV (400 mV p-p) SLVS swing contributes to a reduction in power. The ECP5/ECP5-5G devices can receive differential input up to 800 Mb/s with its LVDS input buffer. This LVDS input buffer is used to meet the SLVS input standard specified by the JEDEC standard. The SLVS output parameters are compared to ECP5/ECP5-5G LVDS input parameters, as listed in Table 3.18. Table 3.18. Input to SLVS Parameter ECP5/ECP5-5G LVDS Input SLVS Output Unit Vcm (min) 50 150 mV Vcm (max) 2350 250 mV Differential Voltage (min) 100 140 mV Differential Voltage (max) — 270 mV ECP5/ECP5-5G does not support SLVS output. However, SLVS output can be created using ECP5/ECP5-5G LVDS outputs by level shift to meet the low Vcm/Vod levels required by SLVS. Figure 3.5 shows how the LVDS output can be shifted external to meet SLVS levels. 2.5 V Typical R3=15 R1=220 R2=47 LVDS + - SLVDS 100 Ω Diff + Z0=50 – R2=47 R1=220 ECP5/ECP5-5G 2.5 V Typical On Chip R3=15 On Chip SLVDS Peer LVDS + –- Z0=50 + –- Figure 3.5. SLVS Interface © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02012-2.2 61 ECP5 and ECP5-5G Family Data Sheet 3.15. Typical Building Block Function Performance Table 3.19. Pin-to-Pin Performance Function –8 Timing Unit 16-Bit Decoder 5.06 ns 32-Bit Decoder 6.08 ns 64-Bit Decoder 5.06 ns 4:1 Mux 4.45 ns 8:1 Mux 4.63 ns 16:1 Mux 4.81 ns 32:1 Mux 4.85 ns Basic Functions Notes: 1. I/O are configured with LVCMOS25 with VCCIO=2.5, 12 mA drive. 2. These functions were generated using Lattice Diamond design software tool. Exact performance may vary with the device and the design software tool version. The design software tool uses internal parameters that have been characterized but are not tested on every device. 3. Commercial timing numbers are shown. Industrial numbers are typically slower and can be extracted from Lattice Diamond design software tool. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 62 FPGA-DS-02012-2.2 ECP5 and ECP5-5G Family Data Sheet Table 3.20. Register-to-Register Performance Function –8 Timing Unit 16-Bit Decoder 441 MHz 32-Bit Decoder 441 MHz 64-Bit Decoder 332 MHz 4:1 Mux 441 MHz 8:1 Mux 441 MHz 16:1 Mux 441 MHz 32:1 Mux 441 MHz 8-Bit Adder 441 MHz 16-Bit Adder 441 MHz 64-Bit Adder 441 MHz 16-Bit Counter 384 MHz 32-Bit Counter 317 MHz 64-Bit Counter 263 MHz 64-Bit Accumulator 288 MHz 1024x18 True-Dual Port RAM (Write Through or Normal), with EBR Output Registers 272 MHz 1024x18 True-Dual Port RAM (Read-Before-Write), with EBR Output Registers 214 MHz 16 x 2 Pseudo-Dual Port or 16 x 4 Single Port RAM (One PFU) 441 MHz 16 x 4 Pseudo-Dual Port (Two PFUs) 441 MHz 9 x 9 Multiplier (All Registers) 225 MHz 18 x 18 Multiplier (All Registers) 225 MHz 36 x 36 Multiplier (All Registers) 225 MHz 18 x 18 Multiply-Add/Sub (All Registers) 225 MHz 18 x 18 Multiply/Accumulate (Input and Output Registers) 225 MHz Basic Functions Embedded Memory Functions Distributed Memory Functions DSP Functions Notes:  These functions were generated using Lattice Diamond design software tool. Exact performance may vary with the device and the design software tool version. The design software tool uses internal parameters that have been characterized but are not tested on every device.  Commercial timing numbers are shown. Industrial numbers are typically slower and can be extracted from Lattice Diamond design software tool. 3.16. Derating Timing Tables Logic timing provided in the following sections of this data sheet and the Diamond design tools are worst case numbers in the operating range. Actual delays at nominal temperature and voltage for best case process, can be much better than the values given in the tables. The Diamond design tool can provide logic timing numbers at a particular temperature and voltage. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02012-2.2 63 ECP5 and ECP5-5G Family Data Sheet 3.17. Maximum I/O Buffer Speed Over recommended operating conditions. Table 3.21. ECP5/ECP5-5G Maximum I/O Buffer Speed Buffer Description Max Unit LVDS25 LVDS, VCCIO = 2.5 V 400 MHz MLVDS25 MLVDS, Emulated, VCCIO = 2.5 V 400 MHz BLVDS25 BLVDS, Emulated, VCCIO = 2.5 V 400 MHz MIPI D-PHY (HS Mode) MIPI Video 400 MHz SLVS SLVS similar to MIPI 400 MHz Mini LVDS Mini LVDS 400 MHz LVPECL33 LVPECL, Emulated, VCCIO = 3.3 V 400 MHz SSTL18 (all supported classes) SSTL_18 class I, II, VCCIO = 1.8 V 400 MHz SSTL15 (all supported classes) SSTL_15 class I, II, VCCIO = 1.5 V 400 MHz SSTL135 (all supported classes) SSTL_135 class I, II, VCCIO = 1.35 V 400 MHz HSUL12 (all supported classes) HSUL_12 class I, II, VCCIO = 1.2 V 400 MHz LVTTL33 LVTTL, VCCIO = 3.3 V 200 MHz LVCMOS33 LVCMOS, VCCIO = 3.3 V 200 MHz LVCMOS25 LVCMOS, VCCIO = 2.5 V 200 MHz LVCMOS18 LVCMOS, VCCIO = 1.8 V 200 MHz LVCMOS15 LVCMOS 1.5, VCCIO = 1.5 V 200 MHz LVCMOS12 LVCMOS 1.2, VCCIO = 1.2 V 200 MHz LVDS25E LVDS, Emulated, VCCIO = 2.5 V 150 MHz LVDS25 LVDS, VCCIO = 2.5 V 400 MHz MLVDS25 MLVDS, Emulated, VCCIO = 2.5 V 150 MHz BLVDS25 BLVDS, Emulated, VCCIO = 2.5 V 150 MHz LVPECL33 LVPECL, Emulated, VCCIO = 3.3 V 150 MHz SSTL18 (all supported classes) SSTL_18 class I, II, VCCIO = 1.8 V 400 MHz SSTL15 (all supported classes) SSTL_15 class I, II, VCCIO = 1.5 V 400 MHz SSTL135 (all supported classes) SSTL_135 class I, II, VCCIO = 1.35 V 400 MHz HSUL12 (all supported classes) HSUL12 class I, II, VCCIO = 1.2 V 400 MHz LVTTL33 LVTTL, VCCIO = 3.3 V 150 MHz LVCMOS33 (For all drives) LVCMOS, 3.3 V 150 MHz LVCMOS25 (For all drives) LVCMOS, 2.5 V 150 MHz LVCMOS18 (For all drives) LVCMOS, 1.8 V 150 MHz LVCMOS15 (For all drives) LVCMOS, 1.5 V 150 MHz LVCMOS12 (For all drives) LVCMOS, 1.2 V 150 MHz Maximum Input Frequency Maximum Output Frequency Notes:  These maximum speeds are characterized but not tested on every device.  Maximum I/O speed for differential output standards emulated with resistors depends on the layout.  LVCMOS timing is measured with the load specified in Table 3.44.  All speeds are measured at fast slew.  Actual system operation may vary depending on user logic implementation.  Maximum data rate equals 2 times the clock rate when utilizing DDR.  MIPI D-PHY HS mode receiver runs 400 MHz as LVDS25. It may exceed ±0.15 UI setup/hold budget at data rate of ≤1 Gbps MIPI Alliance Specification. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 64 FPGA-DS-02012-2.2 ECP5 and ECP5-5G Family Data Sheet 3.18. External Switching Characteristics Over recommended commercial operating conditions. Table 3.22. ECP5/ECP5-5G External Switching Characteristics Parameter Clocks Primary Clock fMAX_PRI tW_PRI tSKEW_PRI Edge Clock fMAX_EDGE tW_EDGE tSKEW_EDGE Description Device –8 –7 –6 Min Max Min Max Min Max Unit Frequency for Primary Clock Tree Clock Pulse Width for Primary Clock Primary Clock Skew within a Device — — 370 — 303 — 257 MHz — 0.8 — 0.9 — 1.0 — ns — — 420 — 462 — 505 ps Frequency for Edge Clock Tree Clock Pulse Width for Edge Clock Edge Clock Skew within a Bank — — — — 1.175 — 400 — 160 — 1.344 — 350 — 180 — 1.50 — 312 — 200 MHz ns ps 5.4 — 6.1 — 6.8 ns — 0 — 0 — ns — 3 — 3.3 — ns — 1.33 — 1.46 — ns — 0 — 0 — ns 400 — 350 — 312 MHz 3.5 — 3.8 — 4.1 ns — 0.78 — 0.85 — ns — 0.89 — 0.98 — ns — 1.78 — 1.95 — ns Generic SDR Input General I/O Pin Parameters Using Dedicated Primary Clock Input without PLL Clock to Output - PIO Output All tCO — Register Devices Clock to Data Setup - PIO Input All tSU 0 Register Devices Clock to Data Hold - PIO Input All tH 2.7 Register Devices Clock to Data Setup - PIO Input All tSU_DEL 1.2 Register with Data Input Delay Devices Clock to Data Hold - PIO Input All tH_DEL 0 Register with Data Input Delay Devices Clock Frequency of I/O and PFU All fMAX_IO — Register Devices General I/O Pin Parameters Using Dedicated Primary Clock Input with PLL Clock to Output - PIO Output All tCOPLL — Register Devices Clock to Data Setup - PIO Input All tSUPLL 0.7 Register Devices Clock to Data Hold - PIO Input All tHPLL 0.8 Register Devices Clock to Data Setup - PIO Input All tSU_DELPLL 1.6 Register with Data Input Delay Devices © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02012-2.2 65 ECP5 and ECP5-5G Family Data Sheet Table 3.22. ECP5/ECP5-5G External Switching Characteristics Parameter Description tH_DELPLL Clock to Data Hold - PIO Input Register with Data Input Delay Device All Devices –8 –7 –6 Min Max Min Max Min Max 0 — 0 — 0 — Unit ns Generic DDR Input Generic DDRX1 Inputs With Clock and Data Centered at Pin (GDDRX1_RX.SCLK.Centered) Using PCLK Clock Input - Figure 3.6 tSU_GDDRX1_centered tHD_GDDRX1_centered fDATA_GDDRX1_centered fMAX_GDDRX1_centered Data Setup Before CLK Input Data Hold After CLK Input GDDRX1 Data Rate GDDRX1 CLK Frequency (SCLK) All Devices All Devices All Devices All Devices 0.52 0.52 — — — — 500 250 0.52 0.52 — — — — 500 250 0.52 0.52 — — — — 500 250 ns ns Mb/s MHz Generic DDRX1 Inputs With Clock and Data Aligned at Pin (GDDRX1_RX.SCLK.Aligned) Using PCLK Clock Input - Figure 3.7 tSU_GDDRX1_aligned Data Setup from CLK Input All Devices — –0.55 — –0.55 — –0.55 tHD_GDDRX1_aligned Data Hold from CLK Input All Devices 0.55 — 0.55 — 0.55 — fDATA_GDDRX1_aligned fMAX_GDDRX1_aligned GDDRX1 Data Rate GDDRX1 CLK Frequency (SCLK) All Devices All Devices — — 500 250 — — 500 250 — — 500 250 ns + 1/2 UI ns + 1/2 UI Mb/s MHz Generic DDRX2 Inputs With Clock and Data Centered at Pin (GDDRX2_RX.ECLK.Centered) Using PCLK Clock Input, Left and Right sides Only - Figure 3.6 tSU_GDDRX2_centered tHD_GDDRX2_centered fDATA_GDDRX2_centered fMAX_GDDRX2_centered Data Setup before CLK Input Data Hold after CLK Input GDDRX2 Data Rate GDDRX2 CLK Frequency (ECLK) All Devices All Devices All Devices All Devices 0.321 0.321 — — — — 800 400 0.403 0.403 — — — — 700 350 0.471 0.471 — — — — 624 312 ns ns Mb/s MHz Generic DDRX2 Inputs With Clock and Data Aligned at Pin (GDDRX2_RX.ECLK.Aligned) Using PCLK Clock Input, Left and Right sides Only - Figure 3.7 tSU_GDDRX2_aligned Data Setup from CLK Input All Devices — –0.344 — –0.42 — -0.495 tHD_GDDRX2_aligned Data Hold from CLK Input All Devices 0.344 — 0.42 — 0.495 — fDATA_GDDRX2_aligned GDDRX2 Data Rate All Devices — 800 — 700 — 624 ns + 1/2 UI ns + 1/2 UI Mb/s fMAX_GDDRX2_aligned GDDRX2 CLK Frequency All Devices — 400 — 350 — 312 MHz (ECLK) Video DDRX71 Inputs With Clock and Data Aligned at Pin (GDDRX71_RX.ECLK) Using PLL Clock Input, Left and Right sides Only Figure 3.11 tSU_LVDS71_i tHD_LVDS71_i fDATA_LVDS71 fMAX_LVDS71 Data Setup from CLK Input (bit i) Data Hold from CLK Input (bit i) DDR71 Data Rate DDR71 CLK Frequency (ECLK) All Devices — –0.271 — –0.39 — –0.41 All Devices 0.271 — 0.39 — 0.41 — All Devices All Devices — — 756 378 — — 620 310 — — 525 262.5 ns+(1/2+i) * UI ns+(1/2+i) * UI Mb/s MHz © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 66 FPGA-DS-02012-2.2 ECP5 and ECP5-5G Family Data Sheet Table 3.22. ECP5/ECP5-5G External Switching Characteristics Parameter Description Device –8 Min –7 Max Min –6 Max Min Max Unit Generic DDR Output Generic DDRX1 Outputs With Clock and Data Centered at Pin (GDDRX1_TX.SCLK.Centered) Using PCLK Clock Input - Figure 3.6 Data Output Valid before CLK ns + tDVB_GDDRX1_centered All Devices –0.67 — –0.67 — –0.67 — Output 1/2 UI Data Output Valid after CLK ns + tDVA_GDDRX1_centered All Devices –0.67 — –0.67 — –0.67 — Output 1/2 UI fDATA_GDDRX1_centered GDDRX1 Data Rate All Devices — 500 — 500 — 500 Mb/s fMAX_GDDRX1_centered GDDRX1 CLK Frequency (SCLK) All Devices — 250 — 250 — 250 MHz Generic DDRX1 Outputs With Clock and Data Aligned at Pin (GDDRX1_TX.SCLK.Aligned) Using PCLK Clock Input - Figure 3.9 Data Output Invalid before All Devices –0.3 — –0.3 — –0.3 — ns CLK Output Data Output Invalid after CLK tDIA_GDDRX1_aligned All Devices — 0.3 — 0.3 — 0.3 ns Output fDATA_GDDRX1_aligned GDDRX1 Data Rate All Devices — 500 — 500 — 500 Mb/s fMAX_GDDRX1_aligned GDDRX1 CLK Frequency (SCLK) All Devices — 250 — 250 — 250 MHz Generic DDRX2 Outputs With Clock and Data Centered at Pin (GDDRX2_TX.ECLK.Centered) Using PCLK Clock Input, Left and Right sides Only - Figure 3.8 Data Output Valid Before CLK – – ns + tDVB_GDDRX2_centered All Devices — –0.56 — — Output 0.442 0.676 1/2 UI Data Output Valid After CLK ns + tDVA_GDDRX2_centered All Devices — 0.442 — 0.56 — 0.676 Output 1/2 UI fDATA_GDDRX2_centered GDDRX2 Data Rate All Devices — 800 — 700 — 624 Mb/s fMAX_GDDRX2_centered GDDRX2 CLK Frequency (ECLK) All Devices — 400 — 350 — 312 MHz Generic DDRX2 Outputs With Clock and Data Aligned at Pin (GDDRX2_TX.ECLK.Aligned) Using PCLK Clock Input, Left and Right sides Only - Figure 3.9 Data Output Invalid before tDIB_GDDRX2_aligned All Devices –0.16 — –0.18 — –0.2 — ns CLK Output Data Output Invalid after CLK tDIA_GDDRX2_aligned All Devices — 0.16 — 0.18 — 0.2 ns Output fDATA_GDDRX2_aligned GDDRX2 Data Rate All Devices — 800 — 700 — 624 Mb/s fMAX_GDDRX2_aligned GDDRX2 CLK Frequency (ECLK) All Devices — 400 — 350 — 312 MHz Video DDRX71 Outputs With Clock and Data Aligned at Pin (GDDRX71_TX.ECLK) Using PLL Clock Input, Left and Right sides Only - Figure 3.12 Data Output Invalid before ns + tDIB_LVDS71_i All Devices –0.16 — –0.18 — –0.2 — CLK Output (i) * UI Data Output Invalid after CLK ns + tDIA_LVDS71_i All Devices — 0.16 — 0.18 — 0.2 Output (i) * UI fDATA_LVDS71 DDR71 Data Rate All Devices — 756 — 620 — 525 Mb/s fMAX_LVDS71 DDR71 CLK Frequency (ECLK) All Devices — 378 — 310 — 262.5 MHz Memory Interface DDR2/DDR3/DDR3L/LPDDR2/LPDDR3 READ (DQ Input Data are Aligned to DQS) tDVBDQ_DDR2 tDVBDQ_DDR3 Data Output Valid before DQS – – ns + 1/2 All Devices — –0.26 — — tDVBDQ_DDR3L Input 0.317 0.374 UI tDVBDQ_LPDDR2 tDVBDQ_LPDDR3 tDIB_GDDRX1_aligned tDVADQ_DDR2 tDVADQ_DDR3 tDVADQ_DDR3L tDVADQ_LPDDR2 tDVADQ_LPDDR3 Data Output Valid after DQS Input All Devices 0.26 — 0.317 — 0.374 — ns + 1/2 UI © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02012-2.2 67 ECP5 and ECP5-5G Family Data Sheet Table 3.22. ECP5/ECP5-5G External Switching Characteristics Parameter Description fDATA_DDR2 fDATA_DDR3 fDATA_DDR3L fDATA_LPDDR2 fDATA_LPDDR3 DDR Memory Data Rate fMAX_DDR2 fMAX_DDR3 fMAX_DDR3L fMAX_LPDDR2 fMAX_LPDDR3 DDR Memory CLK Frequency (ECLK) Device –8 –7 –6 Unit Min Max Min Max Min Max All Devices — 800 — 700 — 624 Mb/s All Devices — 400 — 350 — 312 MHz –0.25 — -0.25 UI DDR2/DDR3/DDR3L/LPDDR2/LPDDR3 WRITE (DQ Output Data are Centered to DQS) tDQVBS_DDR2 tDQVBS_DDR3 Data Output Valid before tDQVBS_DDR3L All Devices — –0.25 — DQS Output tDQVBS_LPDDR2 tDQVBS_LPDDR3 tDQVAS_DDR2 tDQVAS_DDR3 tDQVAS_DDR3L tDQVAS_LPDDR2 tDQVAS_LPDDR3 Data Output Valid after DQS Output All Devices 0.25 — 0.25 — 0.25 — UI fDATA_DDR2 fDATA_DDR3 fDATA_DDR3L fDATA_LPDDR2 fDATA_LPDDR3 DDR Memory Data Rate All Devices — 800 — 700 — 624 Mb/s fMAX_DDR2 fMAX_DDR3 fMAX_DDR3L fMAX_LPDDR2 fMAX_LPDDR3 DDR Memory CLK Frequency (ECLK) All Devices — 400 — 350 — 312 MHz Notes:  Commercial timing numbers are shown. Industrial numbers are typically slower and can be extracted from the Diamond software.  General I/O timing numbers are based on LVCMOS 2.5, 12 mA, Fast Slew Rate, 0pf load.  Generic DDR timing are numbers based on LVDS I/O.  DDR2 timing numbers are based on SSTL18.  DDR3 timing numbers are based on SSTL15.  LPDDR2 and LPDDR3 timing numbers are based on HSUL12.  Uses LVDS I/O standard for measurements.  Maximum clock frequencies are tested under best case conditions. System performance may vary upon the user environment.  All numbers are generated with the Diamond software. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 68 FPGA-DS-02012-2.2 ECP5 and ECP5-5G Family Data Sheet Rx CLK (in) Rx DATA (in) tSU/tDVBDQ tSU/tDVBDQ tHD/tDVADQ tHD/tDVADQ Figure 3.6. Receiver RX.CLK.Centered Waveforms 1/2 UI Rx CLK (in) or DQS Input 1/2 UI 1 UI Rx DATA (in) or DQ Input tSU tSU tHD tHD Figure 3.7. Receiver RX.CLK.Aligned and DDR Memory Input Waveforms 1/2 UI 1/2 UI 1/2 UI 1/2 UI Tx CLK (out) or DQS Output Tx DATA (out) or DQ Output tDVB/tDQVBS tDVB/tDQVBS tDVA/tDQVA tDVA/tDQVAS Figure 3.8. Transmit TX.CLK.Centered and DDR Memory Output Waveforms © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02012-2.2 69 ECP5 and ECP5-5G Family Data Sheet 1 UI Tx CLK (out) Tx DATA (out) tDIB tDIB tDIA tDIA Figure 3.9. Transmit TX.CLK.Aligned Waveforms Receiver – Shown for one LVDS Channel # of Bits Data In 756 Mb/s Clock In 108 MHz For each Channel: 7-bit Output Words to FPGA Fabric Bit # 10 – 1 11 – 2 12 – 3 13 – 4 14 – 5 15 – 6 16 – 7 0x 0x 0x 0x 0x 0x 0x Bit # 20 – 8 21 – 9 22 – 10 23 – 11 24 – 12 25 – 13 26 – 14 Bit # 30 – 15 31 – 16 32 – 17 33 – 18 34 – 19 35 – 20 36 – 21 Bit # 40 – 22 41 – 23 42 – 24 43 – 25 44 – 26 45 – 27 46 – 28 Transmitter – Shown for one LVDS Channel # of Bits Data Out 756 Mb/s Clock Out 108 MHz For each Channel: 7-bit Output Words to FPGA Fabric Bit # 00 – 1 00 – 2 00 – 3 00 – 4 00 – 5 00 – 6 00 – 7 Bit # 10 – 8 11 – 9 12 – 10 13 – 11 14 – 12 15 – 13 16 – 14 Bit # 20 – 15 21 – 16 22 – 17 23 – 18 24 – 19 25 – 20 26 – 21 Bit # 30 – 22 31 – 23 32 – 24 33 – 25 34 – 26 35 – 27 36 – 28 Figure 3.10. DDRX71 Video Timing Waveforms © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 70 FPGA-DS-02012-2.2 ECP5 and ECP5-5G Family Data Sheet Bit 0 1/2 UI Bit i 1/2 UI Bit 1 1 UI CLK (in) DATA (in) tSU_0 tHD_0 tSU_i tHD_i Figure 3.11. Receiver DDRX71_RX Waveforms Bit 0 Bit i Bit 1 1 UI CLK (out) DATA (out) tDIB_0 tDIA_0 tDIB_i tDIA_i Figure 3.12. Transmitter DDRX71_TX Waveforms © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02012-2.2 71 ECP5 and ECP5-5G Family Data Sheet 3.19. sysCLOCK PLL Timing Over recommended operating conditions. Table 3.23. sysCLOCK PLL Timing Parameter Descriptions Conditions Min Max Units fIN Input Clock Frequency (CLKI, CLKFB) — 8 400 MHz fOUT Output Clock Frequency (CLKOP, CLKOS) — 3.125 400 MHz fVCO PLL VCO Frequency — 400 800 MHz fPFD3 Phase Detector Input Frequency — 10 400 MHz tDT Output Clock Duty Cycle — 45 55 % tPH4 Output Phase Accuracy — –5 5 % fOUT ≥ 100 MHz — 100 ps p-p fOUT < 100 MHz — 0.025 UIPP fOUT ≥ 100 MHz — 200 ps p-p fOUT < 100 MHz — 0.050 UIPP fPFD ≥ 100 MHz — 200 ps p-p fPFD < 100 MHz — 0.011 UIPP — 400 ps p-p AC Characteristics Output Clock Period Jitter tOPJIT1 Output Clock Cycle-to-Cycle Jitter Output Clock Phase Jitter tSPO Static Phase Offset tW Output Clock Pulse Width Divider ratio = integer At 90% or 10% 0.9 — ns tLOCK2 PLL Lock-in Time — — 15 ms tUNLOCK PLL Unlock Time — — 50 ns fPFD ≥ 20 MHz — 1,000 ps p-p tIPJIT Input Clock Period Jitter fPFD < 20 MHz — 0.02 UIPP tHI Input Clock High Time 90% to 90% 0.5 — ns tLO Input Clock Low Time 10% to 10% 0.5 — ns tRST RST/ Pulse Width — 1 — ms tRSTREC RST Recovery Time — 1 — ns tLOAD_REG Min Pulse for CIB_LOAD_REG — 10 — ns tROTATE-SETUP Min time for CIB dynamic phase controls to be stable fore CIB_ROTATE — 5 — ns tROTATE-WD Min pulse width for CIB_ROTATE to maintain 0 or 1 — 4 — VCO cycles Notes: 1. Jitter sample is taken over 10,000 samples for Periodic jitter, and 2,000 samples for Cycle-to-Cycle jitter of the primary PLL output with clean reference clock with no additional I/O toggling. 2. Output clock is valid after tLOCK for PLL reset and dynamic delay adjustment. 3. Period jitter and cycle-to-cycle jitter numbers are guaranteed for fPFD > 10 MHz. For fPFD < 10 MHz, the jitter numbers may not be met in certain conditions. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 72 FPGA-DS-02012-2.2 ECP5 and ECP5-5G Family Data Sheet 3.20. SERDES High-Speed Data Transmitter Table 3.24. Serial Output Timing and Levels Symbol Description Min 1, 2 Typ Max Unit VTX-DIFF-PP Peak-Peak Differential voltage on selected amplitude –25% — 25% mV, p-p VTX-CM-DC Output common mode voltage — VCCHTX / 2 — mV, p-p TTX-R Rise time (20% to 80%) 50 — — ps TTX-F Fall time (80% to 20%) 50 — — ps TTX-CM-AC-P RMS AC peak common-mode output voltage — — 20 mV Single ended output impedance for 50/75 Ω –20% 50/75 20% Ω Single ended output impedance for 6K Ω ZTX_SE –25% 6K 25% Ω RLTX_DIFF Differential return loss (with package included) 3 — — –10 dB RLTX_COM Common mode return loss (with package included) 3 — — –6 dB Notes: 1. Measured with 50 Ω Tx Driver impedance at VCCHTX±5%. 2. Refer to ECP5 and ECP5-5G SERDES/PCS Usage Guide (TN1261) for settings of Tx amplitude. 3. Return los = −10 dB (differential), –6 dB (common mode) for 100 MHz ≤ f 1.5 MHz — — — 0.15 UI 3 ps, RMS Transmit1 UI BWTX-PKG-PLL2 TTX-RJ Tx RMS jitter < 1.5 MHz — — — TRF-MISMATCH Tx rise/fall time mismatch — — — 50 MHz < freq < 1.25 GHz 10 — — dB 8 — — dB 6 — — dB 120 Ω RLTX-DIFF Tx Differential Return Loss, including package and silicon UI RLTX-CM Tx Common Mode Return Loss, including package and silicon 1.25 GHz < freq < 2.5 GHz 50 MHz < freq < 2.5 GHz ZTX-DIFF-DC DC differential Impedance — — — VTX-CM-AC-PP Tx AC peak common mode voltage, peak-peak — — — ITX-SHORT Transmitter short-circuit current — — — 90 mA VTX-DC-CM Transmitter DC common-mode voltage — 0 — 1.2 V VTX-IDLE-DIFF-DC Electrical Idle Output DC voltage — 0 — 5 mV VTX-IDLE-DIFF-AC-p — — — VTX-RCV-DETECT Electrical Idle Differential Output peak voltage Voltage change allowed during Receiver Detect — — — 600 mV TTX-IDLE-MIN Min. time in Electrical Idle — 20 — — ns TTX-IDLE-SET-TO-IDLE — — — 8 ns TTX-IDLE-TO-DIFF-DATA Max. time from EI Order Set to valid Electrical Idle Max. time from Electrical Idle to valid differential output — — — 8 ns LTX-SKEW Lane-to-lane output skew — — — mV, p-p mV ps © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 78 FPGA-DS-02012-2.2 ECP5 and ECP5-5G Family Data Sheet Table 3.31. PCIe (5 Gb/s) Symbol Description Test Conditions Min Typ Max Unit Unit Interval — 199.94 200 200.06 ps — 0.343 — 1.2 V, p-p — — 4.2 ps, RMS — — 88 Receive1, 2 UI VRX-DIFF-PP Differential Rx peak-peak voltage TRX-RJ-RMS Receiver random jitter tolerance (RMS) TRX-DJ Receiver deterministic jitter tolerance 1.5 MHz – 100 MHz Random noise — VRX-CM-AC Common mode noise from Rx — RLRX-DIFF Receiver differential Return Loss, package plus silicon 50 MHz < freq < 1.25 GHz 1.25 GHz < freq < 2.5 GHz RLRX-CM ZRX-DC Receiver common mode Return Loss, package plus silicon Receiver DC single ended impedance ps mV, p-p — — 10 — — dB 8 — — dB — 6 — — dB — 40 — 60 Ω — Ω ZRX-HIGH-IMP-DC Receiver DC single ended impedance when powered down — 200K — VRX-CM-AC-P Rx AC peak common mode voltage — — — VRX-IDLE-DET-DIFF-PP Electrical Idle Detect Threshold — 65 — 3403 mv, pp LRX-SKEW Receiver lane-lane skew — — — 8 ns mV, peak Notes: 1. Values are measured at 5 Gb/s. 2. Measured with external AC-coupling on the receiver. 3. Not in compliance with PCI Express standard. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02012-2.2 79 ECP5 and ECP5-5G Family Data Sheet 3.26. CPRI LV2 E.48 Electrical and Timing Characteristics – Preliminary Table 3.32. CPRI LV2 E.48 Electrical and Timing Characteristics Symbol Description Test Conditions Min Typ Max Unit Unit Interval — 203.43 203.45 203.47 ps Duty Cycle Distortion — — — 0.05 UI JUBHPJ Uncorrelated Bounded High Probability Jitter — — — 0.15 UI JTOTAL Total Jitter — — — 0.3 UI ZRX-DIFF-DC DC differential Impedance — 80 — 120 Ω TSKEW Skew between differential signals — — — 9 ps 100 MHz < freq < 3.6864 GHz — — –8 dB RLTX-DIFF Tx Differential Return Loss (S22), including package and silicon — — –8 + 16.6 *log (freq/3.6864) dB 6 — — dB — — 100 mA — — ps Transmit UI TDCD RLTX-CM Tx Common Mode Return Loss, including package and silicon 3.6864 GHz < freq < 4.9152 GHz 100 MHz < freq < 3.6864 GHz ITX-SHORT Transmitter short-circuit current — TRISE_FALL-DIFF Differential Rise and Fall Time — LTX-SKEW Lane-to-lane output skew — — — Receive UI VRX-DIFF-PP Unit Interval — 203.43 203.45 203.47 ps Differential Rx peak-peak voltage — — — 1.2 V, p-p VRX-EYE_Y1_Y2 Receiver eye opening mask, Y1 and Y2 — 62.5 — 375 mV, diff VRX-EYE_X1 Receiver eye opening mask, X1 — — — 0.3 UI TRX-TJ Receiver total jitter tolerance (not including sinusoidal) — — — 0.6 UI 100 MHz < freq < 3.6864 GHz 3.6864 GHz < freq < 4.9152 GHz — — –8 dB RLRX-DIFF Receiver differential Return Loss, package plus silicon — — –8 + 16.6 *log (freq/3.6864) dB RLRX-CM Receiver common mode Return Loss, package plus silicon — 6 — — dB ZRX-DIFF-DC Receiver DC differential impedance — 80 100 120 Ω ps Note: Data is measured with PRBS7 data pattern, not with PRBS-31 pattern. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 80 FPGA-DS-02012-2.2 ECP5 and ECP5-5G Family Data Sheet 3.27. XAUI/CPRI LV E.30 Electrical and Timing Characteristics 3.27.1. AC and DC Characteristics Over recommended operating conditions. Table 3.33. Transmit Symbol Description Test Conditions Min Typ Max TRF Differential rise/fall time 20% to 80% — 80 — ZTX_DIFF_DC Differential impedance — 80 100 120 JTX_DDJ2, 3 Output data deterministic jitter — — — 0.17 JTX_TJ1, 2, 3 Total output data jitter — — — 0.35 Notes: 1. Total jitter includes both deterministic jitter and random jitter. 2. Jitter values are measured with each CML output AC coupled into a 50 Ω impedance (100 Ω differential impedance). 3. Jitter and skew are specified between differential crossings of the 50% threshold of the reference signal. Unit ps Ω UI UI Over recommended operating conditions. Table 3.34. Receive and Jitter Tolerance Symbol Description RLRX_DIFF Differential return loss RLRX_CM Common mode return loss ZRX_DIFF JRX_DJ1, 2, 3 JRX_RJ1, 2, 3 Differential termination resistance Deterministic jitter tolerance (peak-to-peak) Random jitter tolerance (peak-to-peak) Test Conditions Min Typ Max Unit 10 — — dB 6 — — dB 80 — — 100 — — 120 0.37 0.18 Ω UI UI 0.10 0.65 — UI UI UI From 100 MHz to 3.125 GHz From 100 MHz to 3.125 GHz — — — JRX_SJ1, 2, 3 Sinusoidal jitter tolerance (peak-to-peak) — — — JRX_TJ1, 2, 3 Total jitter tolerance (peak-to-peak) — — — TRX_EYE Receiver eye opening — 0.35 — Notes: 1. Total jitter includes deterministic jitter, random jitter and sinusoidal jitter. 2. Jitter values are measured with each high-speed input AC coupled into a 50 Ω impedance. 3. Jitter and skew are specified between differential crossings of the 50% threshold of the reference signal. 3.28. CPRI LV E.24/SGMII (2.5 Gbps) Electrical and Timing Characteristics 3.28.1. AC and DC Characteristics Table 3.35. Transmit Symbol TRF 1 Description Differential rise/fall time ZTX_DIFF_DC JTX_DDJ 3, 4 JTX_TJ2, 3, 4 Test Conditions Min Typ Max Unit 20% to 80% — 80 — ps Differential impedance — 80 100 120 Ω Output data deterministic jitter — — — 0.17 UI Total output data jitter — — — 0.35 UI Notes: 1. Rise and Fall times measured with board trace, connector and approximately 2.5 pf load. 2. Total jitter includes both deterministic jitter and random jitter. The random jitter is the total jitter minus the actual deterministic jitter. 3. Jitter values are measured with each CML output AC coupled into a 50 Ω impedance (100 Ω differential impedance). 4. Jitter and skew are specified between differential crossings of the 50% threshold of the reference signal. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02012-2.2 81 ECP5 and ECP5-5G Family Data Sheet Table 3.36. Receive and Jitter Tolerance Symbol Description Test Conditions RLRX_DIFF RLRX_CM ZRX_DIFF Differential return loss Common mode return loss Differential termination resistance JRX_DJ2, 3, 4 JRX_RJ 2, 3, 4 JRX_SJ2, 3, 4 JRX_TJ 1, 2, 3, 4 TRX_EYE Min Typ Max Unit From 100 MHz to 2.5 GHz From 100 MHz to 2.5 GHz — 10 6 80 — — 100 — — 120 dB dB Ω Deterministic jitter tolerance (peak-to-peak) — — — 0.37 UI Random jitter tolerance (peak-to-peak) — — — 0.18 UI Sinusoidal jitter tolerance (peak-to-peak) — — — 0.10 UI Total jitter tolerance (peak-to-peak) — — — 0.65 UI Receiver eye opening — 0.35 — — UI Notes: 1. Total jitter includes deterministic jitter, random jitter and sinusoidal jitter. 2. Jitter values are measured with each high-speed input AC coupled into a 50 Ω impedance. 3. Jitter and skew are specified between differential crossings of the 50% threshold of the reference signal. 4. Jitter tolerance, Differential Input Sensitivity and Receiver Eye Opening parameters are characterized when Full Rx Equalization is enabled. 3.29. Gigabit Ethernet/SGMII (1.25 Gbps)/CPRI LV E.12 Electrical and Timing Characteristics 3.29.1. AC and DC Characteristics Table 3.37. Transmit Symbol Description TRF Differential rise/fall time 20% to 80% — ZTX_DIFF_DC Differential impedance — 80 Output data deterministic jitter — — Total output data jitter — — JTX_DDJ 2, 3 JTX_TJ1, 2, 3 Test Conditions Min Typ Max Unit 80 — ps 100 120 Ω — 0.10 UI — 0.24 UI Notes: 1. Total jitter includes both deterministic jitter and random jitter. The random jitter is the total jitter minus the actual deterministic jitter. 2. Jitter values are measured with each CML output AC coupled into a 50 Ω impedance (100 Ω differential impedance). 3. Jitter and skew are specified between differential crossings of the 50% threshold of the reference signal. Table 3.38. Receive and Jitter Tolerance Symbol Description Test Conditions RLRX_DIFF Differential return loss From 100 MHz to 1.25 GHz RLRX_CM Common mode return loss From 100 MHz to 1.25 GHz 6 ZRX_DIFF Differential termination resistance — 80 JRX_DJ 1, 2, 3, 4 Min Typ Max Unit 10 — — dB — — dB 100 120 Ω Deterministic jitter tolerance (peak-to-peak) — — — 0.34 UI JRX_RJ1, 2, 3, 4 Random jitter tolerance (peak-to-peak) — — — 0.26 UI JRX_SJ1, 2, 3, 4 Sinusoidal jitter tolerance (peak-to-peak) — — — 0.11 UI JRX_TJ1, 2, 3, 4 Total jitter tolerance (peak-to-peak) — — — 0.71 UI TRX_EYE Receiver eye opening — 0.29 — — UI Notes: 1. Total jitter includes deterministic jitter, random jitter and sinusoidal jitter. 2. Jitter values are measured with each high-speed input AC coupled into a 50 Ω impedance. 3. Jitter and skew are specified between differential crossings of the 50% threshold of the reference signal. 4. Jitter tolerance, Differential Input Sensitivity and Receiver Eye Opening parameters are characterized when Full Rx Equalization is enabled. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 82 FPGA-DS-02012-2.2 ECP5 and ECP5-5G Family Data Sheet 3.30. SMPTE SD/HD-SDI/3G-SDI (Serial Digital Interface) Electrical and Timing Characteristics 3.30.1. AC and DC Characteristics Table 3.39. Transmit Symbol Description BRSDO Serial data rate TJALIGNMENT2 Serial output jitter, alignment 2 Serial output jitter, alignment Serial output jitter, alignment TJALIGNMENT TJALIGNMENT1, 2 Test Conditions Min Typ Max Unit — 270 — 2975 Mb/s 270 Mb/s6 — — 0.2 UI 1485 Mb/s — — 0.2 UI 2970 Mb/s — — 0.3 UI Mb/s6 TJTIMING Serial output jitter, timing 270 — — 0.2 UI TJTIMING Serial output jitter, timing 1485 Mb/s — — 1 UI TJTIMING Serial output jitter, timing 2970 Mb/s — — 2 UI Notes: 1. Timing jitter is measured in accordance with SMPTE serial data transmission standards. 2. Jitter is defined in accordance with SMPTE RP1 184-1996 as: jitter at an equipment output in the absence of input jitter. 3. All Tx jitter are measured at the output of an industry standard cable driver, with the Lattice SERDES device configured to 50 Ω output impedance connecting to the external cable driver with differential signaling. 4. The cable driver drives: RL=75 Ω, AC-coupled at 270, 1485, or 2970 Mb/s. 5. All LFE5UM/LFE5UM5G devices are compliant with all SMPTE compliance tests, except 3G-SDI Level-A pathological compliance pattern test. 6. 270 Mb/s is supported with Rate Divider only. Table 3.40. Receive Symbol Description BRSDI Serial input data rate Test Conditions Min Typ Max Unit — 270 — 2970 Mb/s Test Conditions Min Typ Max Unit Table 3.41. Reference Clock Symbol Description FVCLK Video output clock frequency — 54 — 148.5 MHz DCV Duty cycle, video clock — 45 50 55 % Note: SD-SDI (270 Mb/s) is supported with Rate Divider only. For Single Rate: Reference Clock = 54 MHz and Rate Divider = /2. For Tri-Rate: Reference Clock = 148.5 MHz and Rate Divider = /11. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02012-2.2 83 ECP5 and ECP5-5G Family Data Sheet 3.31. sysCONFIG Port Timing Specifications Over recommended operating conditions. Table 3.42. ECP5/ECP5-5G sysCONFIG Port Timing Specifications Symbol Parameter Min Max Unit — — 33 ms — — 5 us — — 300 ns –20 20 % 40 60 % POR, Configuration Initialization, and Wakeup tVMC Time from the Application of VCC, VCCAUX or VCCIO8 (whichever is the last) to the rising edge of INITN Time from tICFG to the valid Master CCLK tCZ CCLK from Active to High-Z tICFG Master CCLK fMCLK Frequency tMCLK-DC Duty Cycle All selected frequencies All selected frequencies All Configuration Modes tPRGM PROGRAMN LOW pulse accepted — 110 — ns tPRGMRJ PROGRAMN LOW pulse rejected — — 50 ns tINITL INITN LOW time — — 55 ns tDPPINT PROGRAMN LOW to INITN LOW — — 70 ns tDPPDONE PROGRAMN LOW to DONE LOW — — 80 ns tIODISS PROGRAMN LOW to I/O Disabled — — 150 ns fCCLK CCLK input clock frequency — — 60 MHz tCCLKH CCLK input clock pulsewidth HIGH — 6 — ns tCCLKL CCLK input clock pulsewidth LOW — 6 — ns tSTSU CCLK setup time — 1 — ns tSTH CCLK hold time — 1 — ns tSTCO CCLK falling edge to valid output — — 10 ns tSTOZ CCLK falling edge to valid disable — — 10 ns tSTOV CCLK falling edge to valid enable — — 10 ns tSCS Chip Select HIGH time — 25 — ns tSCSS Chip Select setup time — 3 — ns tSCSH Chip Select hold time — 3 — ns fCCLK Max selected CCLK output frequency — — 62 MHz tCCLKH CCLK output clock pulse width HIGH — 3.5 — ns tCCLKL CCLK output clock pulse width LOW — 3.5 — ns tSTSU CCLK setup time — 5 — ns tSTH CCLK hold time — 1 — ns tCSSPI INITN HIGH to Chip Select LOW — 100 200 ns tCFGX INITN HIGH to first CCLK edge — — 150 ns fCCLK CCLK input clock frequency — — 66 MHz tSSCH CCLK input clock pulse width HIGH — 5 — ns tSSCL CCLK input clock pulse width LOW — 5 — ns tSUSCDI CCLK setup time — 0.5 — ns tHSCDI CCLK hold time — 1.5 — ns Slave SPI Master SPI Slave Serial © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 84 FPGA-DS-02012-2.2 ECP5 and ECP5-5G Family Data Sheet Table 3.42. ECP5/ECP5-5G sysCONFIG Port Timing Specifications Symbol Parameter Min Max Unit Slave Parallel fCCLK CCLK input clock frequency — — 50 MHz tBSCH CCLK input clock pulsewidth HIGH — 6 — ns tBSCL CCLK input clock pulsewidth LOW — 6 — ns tCORD CCLK to DOUT for Read Data — — 12 ns tSUCBDI Data Setup Time to CCLK — 1.5 — ns tHCBDI Data Hold Time to CCLK — 1.5 — ns tSUCS CSN, CSN1 Setup Time to CCLK — 2.5 — ns tHCS CSN, CSN1 Hold Time to CCLK — 1.5 — ns tSUWD WRITEN Setup Time to CCLK — 45 — ns tHCWD WRITEN Hold Time to CCLK — 2 — ns tDCB CCLK to BUSY Delay Time — — 12 ns t BSCYC t BSCL t BSCH CCLK t SUCS t HCS tSUWD t HWD CS1N CSN WRITEN t DCB BUSY tCORD D[0:7] Byte 0 Byte 1 Byte 2 Byte n* *n = last byte of read cycle. Figure 3.15. sysCONFIG Parallel Port Read Cycle © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02012-2.2 85 ECP5 and ECP5-5G Family Data Sheet tBSCYC tBSCL t BSCH CCLK* tSUCS tHCS CS1N CSN tSUWD tHWD WRITEN tDCB BUSY tHCBDI t SUCBDI D[0:7] Byte 0 Byte 1 Byte n Byte 2 *In Master Parallel Mode the FPGA provides CCLK (MCLK). In Slave Parallel Mode the external device provides CCLK. Figure 3.16. sysCONFIG Parallel Port Write Cycle tSSCL tSSCH CCLK (input) tHSCDI tSUSCDI DIN tCODO DOUT Figure 3.17. sysCONFIG Slave Serial Port Timing © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 86 FPGA-DS-02012-2.2 ECP5 and ECP5-5G Family Data Sheet VCC/VCCAUX/ VCCIO8 1 tICFG INITN DONE t VMC CCLK 2 CFG[2:0]3 Valid 1. Time taken from VCC, VCCAUX or VCCIO8, whichever is the last to cross the POR trip point. 2. Device is in a Master Mode (SPI, SPIm). 3. The CFG pins are normally static (hardwired). Figure 3.18. Power-On-Reset (POR) Timing Wake Up Clocks tICFG VCC tSSCH tVMC tSSCL tPRGM tPRGMRJ CCLK PROGRAMN tDPPINIT INITN tHSCDI (tHMCDI ) tSUSCDI (tSUMCDI) DONE tCODO tDPPDONE DI GOE Release DOUT tIOENSS sysI/O tIODISS Figure 3.19. sysCONFIG Port Timing © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02012-2.2 87 ECP5 and ECP5-5G Family Data Sheet t PRGMRJ PROGRAMN INITN t DPPI NIT DONE t DI NITD CCLK CFG[2:0]* Valid t IODISS USER I/O *The CFG pins are normally static (hardwired). Figure 3.20. Configuration from PROGRAMN Timing PROGRAMN INITN DONE Wake-Up tMWC CCLK tIOENSS USER I/O Figure 3.21. Wake-Up Timing © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 88 FPGA-DS-02012-2.2 ECP5 and ECP5-5G Family Data Sheet Capture CR0 Capture CFGx VCC PROGRAMN DONE INITN CSSPIN 0 1 2 3 … 7 8 9 10 … 31 32 33 34 … 127 128 CCLK Opcode SISPI Address Ignore SOSPI Valid Bitstream Figure 3.22. Master SPI Configuration Waveforms 3.32. JTAG Port Timing Specifications Over recommended operating conditions. Table 3.43. JTAG Port Timing Specifications Symbol Parameter Min Max Units fMAX TCK clock frequency — 25 MHz tBTCPH TCK [BSCAN] clock pulse width high 20 — ns tBTCPL TCK [BSCAN] clock pulse width low 20 — ns tBTS TCK [BSCAN] setup time 10 — ns tBTH TCK [BSCAN] hold time 8 — ns tBTRF TCK [BSCAN] rise/fall time 50 — mV/ns tBTCO TAP controller falling edge of clock to valid output — 10 ns tBTCODIS TAP controller falling edge of clock to valid disable — 10 ns tBTCOEN TAP controller falling edge of clock to valid enable — 10 ns tBTCRS BSCAN test capture register setup time 8 — ns tBTCRH BSCAN test capture register hold time 25 — ns tBUTCO BSCAN test update register, falling edge of clock to valid output — 25 ns tBTUODIS BSCAN test update register, falling edge of clock to valid disable — 25 ns tBTUPOEN BSCAN test update register, falling edge of clock to valid enable — 25 ns © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02012-2.2 89 ECP5 and ECP5-5G Family Data Sheet TMS TDI tBTS tBTCPH tBTH tBTCP tBTCPL TCK tBTCO tBTCOEN TDO tBTCODIS V a lid D a ta tBTCRH tBTCRS Data to be Captured from I/O V a lid D a ta Data Captured tBTUPOEN tBUTCO Data to be driven out to I/O V a lid D a ta tBTUODIS V a lid D a ta Figure 3.23. JTAG Port Timing Waveforms 3.33. Switching Test Conditions Figure 3.24 shows the output test load that is used for AC testing. The specific values for resistance, capacitance, voltage, and other test conditions are listed in Table 3.44. VT R1 Test Point DUT R2 CL* *CL Includes Test Fixture and Probe Capacitance Figure 3.24. Output Test Load, LVTTL and LVCMOS Standards © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 90 FPGA-DS-02012-2.2 ECP5 and ECP5-5G Family Data Sheet Table 3.44. Test Fixture Required Components, Non-Terminated Interfaces Test Condition LVTTL and other LVCMOS settings (L ≥ H, H ≥ L) R1  R2  CL 0 pF Timing Ref. VT LVCMOS 3.3 = 1.5 V — LVCMOS 2.5 = VCCIO/2 — LVCMOS 1.8 = VCCIO/2 — LVCMOS 1.5 = VCCIO/2 — LVCMOS 1.2 = VCCIO/2 — 1 MΩ 0 pF VCCIO/2 — 1 MΩ  0 pF VCCIO/2 VCCIO  100 0 pF VOH – 0.10 LVCMOS 2.5 I/O (Z ≥ H)  LVCMOS 2.5 I/O (Z ≥ L) LVCMOS 2.5 I/O (H ≥ Z) LVCMOS 2.5 I/O (L ≥ Z) 100 0 pF VOL + 0.10  Note: Output test conditions for all other interfaces are determined by the respective standards. — VCCIO © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02012-2.2 91 ECP5 and ECP5-5G Family Data Sheet 4. Pinout Information 4.1. Signal Descriptions Signal Name I/O Description General Purpose P[L/R] [Group Number]_[A/B/C/D] I/O P[T/B][Group Number]_[A/B] I/O GSRN I [L/R] indicates the L (Left), or R (Right) edge of the device. [Group Number] indicates the PIO [A/B/C/D] group. [A/B/C/D] indicates the PIO within the PIC to which the pad is connected. Some of these user-programmable pins are shared with special function pins. These pins, when not used as special purpose pins, can be programmed as I/O for user logic. During configuration the user-programmable I/O are tristated with an internal pull-down resistor enabled. If any pin is not used (or not bonded to a package pin), it is tristated and default to have pull-down enabled after configuration. PIO A and B are grouped as a pair, and PIO C and D are group as a pair. Each pair supports true LVDS differential input buffer. Only PIO A and B pair supports true LVDS differential output buffer. Each A/B and C/D pair supports programmable on/off differential input termination of 100 Ω. [T/B] indicates the T (top) or B (bottom) edge of the device. [Group Number] indicates the PIO [A/B] group. [A/B] indicates the PIO within the PIC to which the pad is connected. Some of these user-programmable pins are shared with sysConfig pins. These pins, when not used as configuration pins, can be programmed as I/O for user logic. During configuration, the pins not used in configuration are tristated with an internal pull-down resistor enabled. If any pin is not used (or not bonded to a package pin), it is tristated and default to have pull-down enabled after configuration. PIOs on top and bottom do not support differential input signaling or true LVDS output signaling, but it can support emulated differential output buffer. PIO A/B forms a pair of emulated differential output buffer. Global RESET signal (active low). Any I/O pin can be GSRN. NC — No connect. RESERVED — This pin is reserved and should not be connected to anything on the board. GND — Ground. Dedicated pins. VCC — VCCAUX — VCCIOx — VREF1_x — Power supply pins for core logic. Dedicated pins. VCC = 1.1 V (ECP5), 1.2 V (ECP5UM5G) Auxiliary power supply pin. This dedicated pin powers all the differential and referenced input buffers. VCCAUX = 2.5 V. Dedicated power supply pins for I/O bank x. VCCIO8 is used for configuration and JTAG. Reference supply pins for I/O bank x. Pre-determined shared pin in each bank are assigned as VREF1 input. When not used, they may be used as I/O pins. PLL, DLL and Clock Functions [LOC][_GPLL[T, C]_IN PCLK[T/C][Bank]_[num] I I/O General Purpose PLL (GPLL) input pads: [LOC] = ULC, LLC, URC and LRC, T = true and C = complement. These pins are shared I/O pins. When not configured as GPLL input pads, they can be used as general purpose I/O pins. General Purpose Primary CLK pads: [T/C] = True/Complement, [Bank] = (0, 1, 2, 3, 6 and 7). There are two in each bank ([num] = 0, 1). These are shared I/ O pins. When not configured as PCLK pins, they can be used as general purpose I/O pins. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 92 FPGA-DS-02012-2.2 ECP5 and ECP5-5G Family Data Sheet Signal Name I/O Description PLL, DLL and Clock Functions [L/R]DQS[group_num] I/O [T/R]]DQ[group_num] I/O DQS input/output pads: T (top), R (right), group_ num = ball number associated with DQS[T] pin. DQ input/output pads: T (top), R (right), group_ num = ball number associated with DQS[T] pin. Test and Programming (Dedicated Pins) TMS I TCK I TDI I TDO O Test Mode Select input, used to control the 1149.1 state machine. Pull-up is enabled during configuration. This is a dedicated input pin. Test Clock input pin, used to clock the 1149.1 state machine. No pull-up enabled. This is a dedicated input pin. Test Data in pin. Used to load data into device using 1149.1 state machine. After power-up, this TAP port can be activated for configuration by sending appropriate command. (Note: once a configuration port is selected it is locked. Another configuration port cannot be selected until the power-up sequence). Pull-up is enabled during configuration. This is a dedicated input pin. Output pin. Test Data Out pin used to shift data out of a device using 1149.1. This is a dedicated output pin. Configuration Pads (Used during sysCONFIG) CFG[2:0] INITN PROGRAMN I I/O I DONE I/O CCLK I/O HOLDN/DI/BUSY/CSSPIN/CEN I/O CSN/SN I/O CS1N I WRITEN I DOUT/CSON O D0/MOSI/IO0 I/O Mode pins used to specify configuration mode values latched on rising edge of INITN. During configuration, a pull-up is enabled. These are dedicated pins. Open Drain pin. Indicates the FPGA is ready to be configured. During configuration, a pull-up is enabled. This is a dedicated pin. Initiates configuration sequence when asserted low. This pin always has an active pull-up. This is a dedicated pin. Open Drain pin. Indicates that the configuration sequence is complete, and the startup sequence is in progress. This is a dedicated pin. Input Configuration Clock for configuring an FPGA in Slave SPI, Serial, and CPU modes. Output Configuration Clock for configuring an FPGA in Master configuration modes (Master SPI, Master Serial). This is a dedicated pin. Parallel configuration mode busy indicator. SPI/SPIm mode data output. This is a shared I/O pin. This is a shared I/O pin. When not in configuration, it can be used as general purpose I/O pin. Parallel configuration mode active-low chip select. Slave SPI chip select. This is a shared I/O pin. When not in configuration, it can be used as general purpose I/O pin. Parallel configuration mode active-low chip select. This is a shared I/O pin. When not in configuration, it can be used as general purpose I/O pin. Write enable for parallel configuration modes. This is a shared I/O pin. When not in configuration, it can be used as general purpose I/O pin. Serial data output. Chip select output. SPI/SPIm mode chip select. This is a shared I/O pin. When not in configuration, it can be used as general purpose I/O pin. Parallel configuration I/O. Open drain during configuration. When in SPI modes, it is an output in Master mode, and input in Slave mode. This is a shared I/O pin. When not in configuration, it can be used as general purpose I/O pin. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02012-2.2 93 ECP5 and ECP5-5G Family Data Sheet Signal Name I/O Configuration Pads (Used during sysCONFIG) Description Parallel configuration I/O. Open drain during configuration. When in SPI modes, it is an input in Master mode, and output in Slave mode. This is a shared I/O pin. When not in configuration, it can be used as general purpose I/O pin. Parallel configuration I/O. Open drain during configuration. When in SPI modes, it is an input in Master mode, and output in Slave mode. This is a shared I/O pin. When not in configuration, it can be used as general purpose I/O pin. Parallel configuration I/O. Open drain during configuration. When in SPI modes, it is an input in Master mode, and output in Slave mode. This is a shared I/O pin. When not in configuration, it can be used as general purpose I/O pin. Parallel configuration I/O. Open drain during configuration. This is a shared I/O pin. When not in configuration, it can be used as general purpose I/O pin. D1/MISO/IO1 I/O D2/IO2 I/O D3/IO3 I/O D4/IO4 I/O D5/IO5 I/O Parallel configuration I/O. Open drain during configuration. This is a shared I/O pin. When not in configuration, it can be used as general purpose I/O pin. D6/IO6 I/O Parallel configuration I/O. Open drain during configuration. This is a shared I/O pin. When not in configuration, it can be used as general purpose I/O pin. D7/IO7 I/O Parallel configuration I/O. Open drain during configuration. This is a shared I/O pin. When not in configuration, it can be used as general purpose I/O pin SERDES Function VCCAx — VCCAUXAx — HDRX[P/N]_D[dual_num]CH[chan_num] I HDTX[P/N]_D[dual_num]CH[chan_num] O REFCLK[P/N]_D[dual_num] I VCCHRX_D[dual_num]CH[chan_num] — VCCHTX_D[dual_num]CH[chan_num] — SERDES, transmit, receive, PLL and reference clock buffer power supply for SERDES Dual x. All VCCA supply pins must always be powered to the recommended operating voltage range. If no SERDES channels are used, connect VCCA to VCC. VCCAx = 1.1 V for ECP5, VCCAx = 1.2 V for ECP5-5G. SERDES Aux Power Supply pin for SERDES Dual x. VCCAUXAx = 2.5 V. High-speed SERDES inputs, P = Positive, N = Negative, dual_num = [0, 1], chan_num = [0, 1]. These are dedicated SERDES input pins. High-speed SERDES outputs, P = Positive, N = Negative, dual_num = [0, 1], chan_num = [0, 1]. These are dedicated SERDES output pins. SERDES Reference Clock inputs, P = Positive, N = Negative, dual_num = [0, 1]. These are dedicated SERDES input pins. SERDES High-Speed Inputs Termination Voltage Supplies, dual_num = [0, 1], chan_num = [0, 1]. These pins should be powered to 1.1 V on ECP5, or 1.2 V on ECP5-5G. SERDES High-Speed Outputs Buffer Voltage Supplies, dual_num = [0, 1], chan_num = [0, 1]. These pins should be powered to 1.1 V on ECP5, or 1.2 V on ECP5-5G. Notes:  When placing switching I/O around these critical pins that are designed to supply the device with the proper reference or supply voltage, care must be given.  These pins are dedicated inputs or can be used as general purpose I/O. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 94 FPGA-DS-02012-2.2 ECP5 and ECP5-5G Family Data Sheet 4.2. PICs and DDR Data (DQ) Pins Associated with the DDR Strobe (DQS) Pin PICs Associated with DQS Strobe PIO within PIC DDR Strobe (DQS) and Data (DQ) Pins A DQ B DQ C DQ D DQ A DQ B DQ C DQ For Left and Right Edges of the Device Only P[L/R] [n−6] P[L/R] [n−3] P[L/R] [n] P[L/R] [n+3] D DQ A DQS (P) B DQS (N) C DQ D DQ A DQ B DQ C DQ D DQ Note: n is a row PIC number. 4.3. Pin Information Summary 4.3.1. LFE5UM/LFE5UM5G LFE5UM/ LFE5UM5G-25 Pin Information Summary 285 csfBGA 381 caBGA 285 csfBGA 381 caBGA Bank 0 6 24 6 Bank 1 6 32 6 Bank 2 21 32 Bank 3 28 32 Pin Type General Purpose Inputs/Outputs per Bank LFE5UM/LFE5UM5G-45 LFE5UM/LFE5UM5G-85 285 csfBGA 27 554 caBG A 32 554 caBGA 756 caBGA 6 381 caBG A 27 33 40 32 56 6 33 40 48 21 32 28 33 32 21 34 32 48 48 28 33 48 64 Bank 4 0 0 0 0 0 0 0 14 24 Bank 6 26 32 26 33 48 26 33 48 64 Bank 7 18 32 18 32 32 18 32 32 48 Bank 8 13 13 13 13 13 13 13 13 13 Total Single-Ended User I/O 118 197 118 203 245 118 205 259 365 VCC 13 20 13 20 24 13 20 24 36 VCCAUX (Core) VCCIO 3 4 3 4 9 3 4 9 8 Bank 0 1 2 1 2 3 1 2 3 4 Bank 1 1 2 1 2 3 1 2 3 4 Bank 2 2 3 2 3 4 2 3 4 4 Bank 3 2 3 2 3 3 2 3 3 4 Bank 4 0 0 0 0 0 0 0 2 2 Bank 6 2 3 2 3 4 2 3 4 4 Bank 7 2 3 2 3 3 2 3 3 4 Bank 8 2 2 2 2 2 2 2 2 2 © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02012-2.2 95 ECP5 and ECP5-5G Family Data Sheet LFE5UM/ LFE5UM5G-25 Pin Information Summary LFE5UM/LFE5UM5G-45 285 csfBGA 381 caBGA 285 csfBGA 381 caBGA TAP 4 4 4 Miscellaneous Dedicated Pins 7 7 7 GND 83 59 NC 1 8 Pin Type LFE5UM/LFE5UM5G-85 285 csfBGA 4 554 caBG A 4 554 caBGA 756 caBGA 4 381 caBG A 4 7 7 4 4 7 7 7 7 83 59 1 2 113 83 59 113 166 33 1 0 17 29 Reserved 0 2 0 2 4 0 2 4 4 SERDES 14 28 14 28 28 14 28 28 28 VCCA0 2 2 2 2 6 2 2 6 8 VCCA1 0 2 0 2 6 0 2 6 9 VCCAUXA0 2 2 2 2 2 2 2 2 2 VCCAUXA1 0 2 0 2 2 0 2 2 2 VCCA (SERDES) VCCAUXA (SERDES) GNDA (SERDES) 26 26 26 26 49 26 26 49 60 Total Balls 285 381 285 381 554 285 381 554 756 Bank 0 0 0 0 0 0 0 0 0 0 Bank 1 0 0 0 0 0 0 0 0 0 Bank 2 10/8 16/8 10/8 16/8 16/8 10/8 17/9 16/8 24/12 Bank 3 14/7 16/8 14/7 16/8 24/1 2 0 14/7 16/8 24/12 32/16 0 0 0 0 13/6 16/8 24/12 32/16 High Speed Differential Input / Output Pairs Bank 4 0 0 0 0 Bank 6 13/6 16/8 13/6 16/8 Bank 7 8/6 16/8 8/6 16/8 24/1 2 16/8 8/6 16/8 16/8 24/12 Bank 8 0 0 0 0 0 0 0 0 0 45/27 64/32 45/27 64/32 0 0 0 0 65/3 3 0 80/40 0 80/4 0 0 45/27 Bank 0 0 112/5 6 0 Bank 1 0 0 0 0 0 0 0 0 0 Bank 2 1 2 1 2 2 1 2 2 3 Bank 3 2 2 2 2 3 2 2 3 4 Bank 4 0 0 0 0 0 0 0 0 0 Bank 6 2 2 2 2 3 2 2 3 4 Bank 7 1 2 1 2 2 1 2 2 3 Bank 8 0 0 0 0 0 0 0 0 0 6 8 6 8 10 6 8 10 14 Total High Speed Differential I/O Pairs DQS Groups (> 11 pins in group) Total DQS Groups © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 96 FPGA-DS-02012-2.2 ECP5 and ECP5-5G Family Data Sheet 4.3.2. LFE5U Pin Information Summary LFE5U-12 LFE5U-45 LFE5U-85 144 256 285 381 144 256 285 381 144 256 285 381 554 285 381 554 756 TQFP caBGA csfBGA caBGA TQFP caBGA csfBGA caBGA TQFP caBGA csfBGA caBGA caBGA csfBGA caBGA caBGA caBGA Pin Type General Purpose Inputs/Outputs per Bank LFE5U-25 Bank 0 24 6 24 24 Bank 1 Bank 2 32 6 32 32 21 32 Bank 3 32 28 Bank 4 0 0 Bank 6 32 Bank 7 32 Bank 8 6 24 24 6 27 32 32 6 32 32 21 32 32 32 28 0 0 0 26 32 32 18 32 32 6 27 32 56 32 6 33 32 21 32 40 6 33 40 48 32 21 34 32 48 32 32 28 0 0 0 33 48 28 33 48 64 0 0 0 0 14 24 26 32 32 18 32 32 26 33 48 26 33 48 64 18 32 32 18 32 32 48 13 13 13 13 13 13 13 13 13 13 13 13 13 13 197 118 197 197 118 197 197 118 203 245 118 205 259 365 VCC 6 13 20 6 13 20 6 13 20 24 13 20 24 36 VCCAUX (Core) 2 3 4 2 3 4 2 3 4 9 3 4 9 8 Bank 0 2 1 2 2 1 2 2 1 2 3 1 2 3 4 Bank 1 2 1 2 2 1 2 2 1 2 3 1 2 3 4 Bank 2 2 2 3 2 2 3 2 2 3 4 2 3 4 4 Bank 3 2 2 3 2 2 3 2 2 3 3 2 3 3 4 Bank 4 0 0 0 0 0 0 0 0 0 0 0 0 2 2 Bank 6 2 2 3 2 2 3 2 2 3 4 2 3 4 4 Bank 7 2 2 3 2 2 3 2 2 3 3 2 3 3 4 Bank 8 1 2 2 1 2 2 1 2 2 2 2 2 2 2 TAP 4 4 4 4 4 4 4 4 4 4 4 4 4 4 Miscellaneous Dedicated Pins 7 7 7 7 7 7 7 7 7 7 7 7 7 7 GND 27 123 99 27 123 99 27 123 113 198 123 113 198 267 NC 0 1 26 0 1 26 0 1 2 33 1 0 33 29 Reserved 0 4 6 0 4 6 0 4 10 12 4 10 12 12 256 285 381 256 285 381 256 285 381 554 285 381 554 756 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Total Single-Ended User I/O VCCIO Total Balls Bank 0 Bank 1 High Speed Differential Input /Output Pairs 0 24/1 16/8 10/8 16/8 Bank 3 16/8 14/7 16/8 16/8 14/7 16/8 16/8 14/7 16/8 24/12 14/7 16/8 24/12 32/1 0 0 0 0 0 0 0 0 0 0 10/8 17/9 0 16/8 10/8 16/8 Bank 4 16/8 16/8 16/8 10/8 16/8 0 0 0 0 Bank 6 16/8 13/6 16/8 16/8 13/6 16/8 16/8 13/6 16/8 24/12 13/6 16/8 24/12 32/1 Bank 7 16/8 8/6 16/8 16/8 8/6 16/8 16/8 8/6 16/8 16/8 8/6 16/8 16/8 24/1 Bank 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Total High Speed Differential I/O Pairs DQS Groups (> 11 pins in group) 0 Bank 2 64/32 45/27 64/32 64/32 45/27 64/32 64/32 45/27 64/32 80/40 45/27 65/33 80/40 112/56 Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bank 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bank 2 2 1 2 2 1 2 2 1 2 2 1 2 2 3 Bank 3 2 2 2 2 2 2 2 2 2 3 2 2 3 4 Bank 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bank 6 2 2 2 2 2 2 2 2 2 3 2 2 3 4 Bank 7 2 1 2 2 1 2 2 1 2 2 1 2 2 3 Bank 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02012-2.2 97 ECP5 and ECP5-5G Family Data Sheet Pin Information Summary LFE5U-12 Total DQS Groups 8 6 LFE5U-25 8 8 6 LFE5U-45 8 8 6 LFE5U-85 8 10 6 8 10 14 © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 98 FPGA-DS-02012-2.2 ECP5 and ECP5-5G Family Data Sheet 5. Ordering Information 5.1. ECP5/ECP5-5G Part Number Description LFE5U - XX - X XXXXX X Grade C = Commercial I = Industrial Device Family LFE5U (ECP5 FPGA) Logic Capacity 12F = 12K LUTs 25F = 25K LUTs 45F = 45K LUTs 85F = 85K LUTs Package TN144 = 144-pin TQFP BG256 = 256-ball caBGA MG285 = 285-ball csfBGA BG381 = 381-ball caBGA BG554 = 554-ball caBGA BG756 = 756-ball caBGA Speed 6 = Slowest 7 8 = Fastest LFE5UM - XX - X XXXXX X Device Family LFE5UM (ECP5 FPGA with SERDES) Logic Capacity 25F = 25K LUTs 45F = 45K LUTs 85F = 85K LUTs Speed 6 = Slowest 7 8 = Fastest Grade C = Commercial I = Industrial Package MG285 = 285-ball csfBGA BG381 = 381-ball caBGA BG554 = 554-ball caBGA BG756 = 756-ball caBGA © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02012-2.2 99 ECP5 and ECP5-5G Family Data Sheet LFE5UM5G - XX - X XXXXX X Device Family LFE5UM5G (ECP5-5G FPGA with SERDES) Grade C = Commercial I = Industrial Logic Capacity 25F = 25K LUTs 45F = 45K LUTs 85F = 85K LUTs Package MG285 = 285-ball csfBGA BG381 = 381-ball caBGA BG554 = 554-ball caBGA BG756 = 756-ball caBGA Speed 8 = Fastest 5.2. Ordering Part Numbers 5.2.1. Commercial Part number Grade Package Pins Temp. LUTs (K) SERDES LFE5U-12F-6TN144C –6 Lead free TQFP 144 Commercial 12 No LFE5U-12F-7TN144C –7 Lead free TQFP 144 Commercial 12 No LFE5U-12F-8TN144C –8 Lead free TQFP 144 Commercial 12 No LFE5U-12F-6BG256C –6 Lead free caBGA 256 Commercial 12 No LFE5U-12F-7BG256C –7 Lead free caBGA 256 Commercial 12 No LFE5U-12F-8BG256C –8 Lead free caBGA 256 Commercial 12 No LFE5U-12F-6MG285C –6 Lead free csfBGA 285 Commercial 12 No LFE5U-12F-7MG285C –7 Lead free csfBGA 285 Commercial 12 No LFE5U-12F-8MG285C –8 Lead free csfBGA 285 Commercial 12 No LFE5U-12F-6BG381C –6 Lead free caBGA 381 Commercial 12 No LFE5U-12F-7BG381C –7 Lead free caBGA 381 Commercial 12 No LFE5U-12F-8BG381C –8 Lead free caBGA 381 Commercial 12 No LFE5U-25F-6TN144C –6 Lead free TQFP 144 Commercial 24 No LFE5U-25F-7TN144C –7 Lead free TQFP 144 Commercial 24 No LFE5U-25F-8TN144C –8 Lead free TQFP 144 Commercial 24 No LFE5U-25F-6BG256C –6 Lead free caBGA 256 Commercial 24 No LFE5U-25F-7BG256C –7 Lead free caBGA 256 Commercial 24 No LFE5U-25F-8BG256C –8 Lead free caBGA 256 Commercial 24 No LFE5U-25F-6MG285C –6 Lead free csfBGA 285 Commercial 24 No LFE5U-25F-7MG285C –7 Lead free csfBGA 285 Commercial 24 No LFE5U-25F-8MG285C –8 Lead free csfBGA 285 Commercial 24 No LFE5U-25F-6BG381C –6 Lead free caBGA 381 Commercial 24 No LFE5U-25F-7BG381C –7 Lead free caBGA 381 Commercial 24 No LFE5U-25F-8BG381C –8 Lead free caBGA 381 Commercial 24 No LFE5U-45F-6TN144C –6 Lead free TQFP 144 Commercial 44 No LFE5U-45F-7TN144C –7 Lead free TQFP 144 Commercial 44 No LFE5U-45F-8TN144C –8 Lead free TQFP 144 Commercial 44 No LFE5U-45F-6BG256C –6 Lead free caBGA 256 Commercial 44 No LFE5U-45F-7BG256C –7 Lead free caBGA 256 Commercial 44 No © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 100 FPGA-DS-02012-2.2 ECP5 and ECP5-5G Family Data Sheet Part number Grade Package Pins Temp. LUTs (K) SERDES LFE5U-45F-8BG256C –8 Lead free caBGA 256 Commercial 44 No LFE5U-45F-6MG285C –6 Lead free csfBGA 285 Commercial 44 No LFE5U-45F-7MG285C –7 Lead free csfBGA 285 Commercial 44 No LFE5U-45F-8MG285C –8 Lead free csfBGA 285 Commercial 44 No LFE5U-45F-6BG381C –6 Lead free caBGA 381 Commercial 44 No LFE5U-45F-7BG381C –7 Lead free caBGA 381 Commercial 44 No LFE5U-45F-8BG381C –8 Lead free caBGA 381 Commercial 44 No LFE5U-45F-6BG554C –6 Lead free caBGA 554 Commercial 44 No LFE5U-45F-7BG554C –7 Lead free caBGA 554 Commercial 44 No LFE5U-45F-8BG554C –8 Lead free caBGA 554 Commercial 44 No LFE5U-85F-6MG285C –6 Lead free csfBGA 285 Commercial 84 No LFE5U-85F-7MG285C –7 Lead free csfBGA 285 Commercial 84 No LFE5U-85F-8MG285C –8 Lead free csfBGA 285 Commercial 84 No LFE5U-85F-6BG381C –6 Lead free caBGA 381 Commercial 84 No LFE5U-85F-7BG381C –7 Lead free caBGA 381 Commercial 84 No LFE5U-85F-8BG381C –8 Lead free caBGA 381 Commercial 84 No LFE5U-85F-6BG554C –6 Lead free caBGA 554 Commercial 84 No LFE5U-85F-7BG554C –7 Lead free caBGA 554 Commercial 84 No LFE5U-85F-8BG554C –8 Lead free caBGA 554 Commercial 84 No LFE5U-85F-6BG756C –6 Lead free caBGA 756 Commercial 84 No LFE5U-85F-7BG756C –7 Lead free caBGA 756 Commercial 84 No LFE5U-85F-8BG756C –8 Lead free caBGA 756 Commercial 84 No LFE5UM-25F-6MG285C –6 Lead free csfBGA 285 Commercial 24 Yes LFE5UM-25F-7MG285C –7 Lead free csfBGA 285 Commercial 24 Yes LFE5UM-25F-8MG285C –8 Lead free csfBGA 285 Commercial 24 Yes LFE5UM-25F-6BG381C –6 Lead free caBGA 381 Commercial 24 Yes LFE5UM-25F-7BG381C –7 Lead free caBGA 381 Commercial 24 Yes LFE5UM-25F-8BG381C –8 Lead free caBGA 381 Commercial 24 Yes LFE5UM-45F-6MG285C –6 Lead free csfBGA 285 Commercial 44 Yes LFE5UM-45F-7MG285C –7 Lead free csfBGA 285 Commercial 44 Yes LFE5UM-45F-8MG285C –8 Lead free csfBGA 285 Commercial 44 Yes LFE5UM-45F-6BG381C –6 Lead free caBGA 381 Commercial 44 Yes LFE5UM-45F-7BG381C –7 Lead free caBGA 381 Commercial 44 Yes LFE5UM-45F-8BG381C –8 Lead free caBGA 381 Commercial 44 Yes LFE5UM-45F-6BG554C –6 Lead free caBGA 554 Commercial 44 Yes LFE5UM-45F-7BG554C –7 Lead free caBGA 554 Commercial 44 Yes LFE5UM-45F-8BG554C –8 Lead free caBGA 554 Commercial 44 Yes LFE5UM-85F-6MG285C –6 Lead free csfBGA 285 Commercial 84 Yes LFE5UM-85F-7MG285C –7 Lead free csfBGA 285 Commercial 84 Yes LFE5UM-85F-8MG285C –8 Lead free csfBGA 285 Commercial 84 Yes LFE5UM-85F-6BG381C –6 Lead free caBGA 381 Commercial 84 Yes LFE5UM-85F-7BG381C –7 Lead free caBGA 381 Commercial 84 Yes LFE5UM-85F-8BG381C –8 Lead free caBGA 381 Commercial 84 Yes LFE5UM-85F-6BG554C –6 Lead free caBGA 554 Commercial 84 Yes LFE5UM-85F-7BG554C –7 Lead free caBGA 554 Commercial 84 Yes LFE5UM-85F-8BG554C –8 Lead free caBGA 554 Commercial 84 Yes © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02012-2.2 101 ECP5 and ECP5-5G Family Data Sheet Part number Grade Package Pins Temp. LUTs (K) SERDES LFE5UM-85F-6BG756C –6 Lead free caBGA 756 Commercial 84 Yes LFE5UM-85F-7BG756C –7 Lead free caBGA 756 Commercial 84 Yes LFE5UM-85F-8BG756C –8 Lead free caBGA 756 Commercial 84 Yes LFE5UM5G-25F-8MG285C –8 Lead free csfBGA 285 Commercial 24 Yes LFE5UM5G-25F-8BG381C –8 Lead free caBGA 381 Commercial 24 Yes LFE5UM5G-45F-8MG285C –8 Lead free csfBGA 285 Commercial 44 Yes LFE5UM5G-45F-8BG381C –8 Lead free caBGA 381 Commercial 44 Yes LFE5UM5G-45F-8BG554C –8 Lead free caBGA 554 Commercial 44 Yes LFE5UM5G-85F-8MG285C –8 Lead free csfBGA 285 Commercial 84 Yes LFE5UM5G-85F-8BG381C –8 Lead free caBGA 381 Commercial 84 Yes LFE5UM5G-85F-8BG554C –8 Lead free caBGA 554 Commercial 84 Yes LFE5UM5G-85F-8BG756C –8 Lead free caBGA 756 Commercial 84 Yes Part number Grade Package Pins Temp. LUTs (K) SERDES LFE5U-12F-6TN144I –6 Lead free TQFP 144 Industrial 12 No LFE5U-12F-7TN144I –7 Lead free TQFP 144 Industrial 12 No LFE5U-12F-8TN144I –8 Lead free TQFP 144 Industrial 12 No LFE5U-12F-6BG256I –6 Lead free caBGA 256 Industrial 12 No LFE5U-12F-7BG256I –7 Lead free caBGA 256 Industrial 12 No LFE5U-12F-8BG256I –8 Lead free caBGA 256 Industrial 12 No LFE5U-12F-6MG285I –6 Lead free csfBGA 285 Industrial 12 No LFE5U-12F-7MG285I –7 Lead free csfBGA 285 Industrial 12 No LFE5U-12F-8MG285I –8 Lead free csfBGA 285 Industrial 12 No LFE5U-12F-6BG381I –6 Lead free caBGA 381 Industrial 12 No LFE5U-12F-7BG381I –7 Lead free caBGA 381 Industrial 12 No LFE5U-12F-8BG381I –8 Lead free caBGA 381 Industrial 12 No LFE5U-25F-6TN144I –6 Lead free TQFP 144 Industrial 24 No LFE5U-25F-7TN144I –7 Lead free TQFP 144 Industrial 24 No LFE5U-25F-8TN144I –8 Lead free TQFP 144 Industrial 24 No LFE5U-25F-6BG256I –6 Lead free caBGA 256 Industrial 24 No LFE5U-25F-7BG256I –7 Lead free caBGA 256 Industrial 24 No LFE5U-25F-8BG256I –8 Lead free caBGA 256 Industrial 24 No LFE5U-25F-6MG285I –6 Lead free csfBGA 285 Industrial 24 No LFE5U-25F-7MG285I –7 Lead free csfBGA 285 Industrial 24 No LFE5U-25F-8MG285I –8 Lead free csfBGA 285 Industrial 24 No LFE5U-25F-6BG381I –6 Lead free caBGA 381 Industrial 24 No LFE5U-25F-7BG381I –7 Lead free caBGA 381 Industrial 24 No LFE5U-25F-8BG381I –8 Lead free caBGA 381 Industrial 24 No LFE5U-45F-6TN144I –6 Lead free TQFP 144 Industrial 44 No LFE5U-45F-7TN144I –7 Lead free TQFP 144 Industrial 44 No LFE5U-45F-8TN144I –8 Lead free TQFP 144 Industrial 44 No LFE5U-45F-6BG256I –6 Lead free caBGA 256 Industrial 44 No LFE5U-45F-7BG256I –7 Lead free caBGA 256 Industrial 44 No LFE5U-45F-8BG256I –8 Lead free caBGA 256 Industrial 44 No 5.2.2. Industrial © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 102 FPGA-DS-02012-2.2 ECP5 and ECP5-5G Family Data Sheet Part number Grade Package Pins Temp. LUTs (K) SERDES LFE5U-45F-6MG285I –6 Lead free csfBGA 285 Industrial 44 No LFE5U-45F-7MG285I –7 Lead free csfBGA 285 Industrial 44 No LFE5U-45F-8MG285I –8 Lead free csfBGA 285 Industrial 44 No LFE5U-45F-6BG381I –6 Lead free caBGA 381 Industrial 44 No LFE5U-45F-7BG381I –7 Lead free caBGA 381 Industrial 44 No LFE5U-45F-8BG381I –8 Lead free caBGA 381 Industrial 44 No LFE5U-45F-6BG554I –6 Lead free caBGA 554 Industrial 44 No LFE5U-45F-7BG554I –7 Lead free caBGA 554 Industrial 44 No LFE5U-45F-8BG554I –8 Lead free caBGA 554 Industrial 44 No LFE5U-85F-6MG285I –6 Lead free csfBGA 285 Industrial 84 No LFE5U-85F-7MG285I –7 Lead free csfBGA 285 Industrial 84 No LFE5U-85F-8MG285I –8 Lead free csfBGA 285 Industrial 84 No LFE5U-85F-6BG381I –6 Lead free caBGA 381 Industrial 84 No LFE5U-85F-7BG381I –7 Lead free caBGA 381 Industrial 84 No LFE5U-85F-8BG381I –8 Lead free caBGA 381 Industrial 84 No LFE5U-85F-6BG554I –6 Lead free caBGA 554 Industrial 84 No LFE5U-85F-7BG554I –7 Lead free caBGA 554 Industrial 84 No LFE5U-85F-8BG554I –8 Lead free caBGA 554 Industrial 84 No LFE5U-85F-6BG756I –6 Lead free caBGA 756 Industrial 84 No LFE5U-85F-7BG756I –7 Lead free caBGA 756 Industrial 84 No LFE5U-85F-8BG756I –8 Lead free caBGA 756 Industrial 84 No LFE5UM-25F-6MG285I –6 Lead free csfBGA 285 Industrial 24 Yes LFE5UM-25F-7MG285I –7 Lead free csfBGA 285 Industrial 24 Yes LFE5UM-25F-8MG285I –8 Lead free csfBGA 285 Industrial 24 Yes LFE5UM-25F-6BG381I –6 Lead free caBGA 381 Industrial 24 Yes LFE5UM-25F-7BG381I –7 Lead free caBGA 381 Industrial 24 Yes LFE5UM-25F-8BG381I –8 Lead free caBGA 381 Industrial 24 Yes LFE5UM-45F-6MG285I –6 Lead free csfBGA 285 Industrial 44 Yes LFE5UM-45F-7MG285I –7 Lead free csfBGA 285 Industrial 44 Yes LFE5UM-45F-8MG285I –8 Lead free csfBGA 285 Industrial 44 Yes LFE5UM-45F-6BG381I –6 Lead free caBGA 381 Industrial 44 Yes LFE5UM-45F-7BG381I –7 Lead free caBGA 381 Industrial 44 Yes LFE5UM-45F-8BG381I –8 Lead free caBGA 381 Industrial 44 Yes LFE5UM-45F-6BG554I –6 Lead free caBGA 554 Industrial 44 Yes LFE5UM-45F-7BG554I –7 Lead free caBGA 554 Industrial 44 Yes LFE5UM-45F-8BG554I –8 Lead free caBGA 554 Industrial 44 Yes LFE5UM-85F-6MG285I –6 Lead free csfBGA 285 Industrial 84 Yes LFE5UM-85F-7MG285I –7 Lead free csfBGA 285 Industrial 84 Yes LFE5UM-85F-8MG285I –8 Lead free csfBGA 285 Industrial 84 Yes LFE5UM-85F-6BG381I –6 Lead free caBGA 381 Industrial 84 Yes LFE5UM-85F-7BG381I –7 Lead free caBGA 381 Industrial 84 Yes LFE5UM-85F-8BG381I –8 Lead free caBGA 381 Industrial 84 Yes LFE5UM-85F-6BG554I –6 Lead free caBGA 554 Industrial 84 Yes LFE5UM-85F-7BG554I –7 Lead free caBGA 554 Industrial 84 Yes LFE5UM-85F-8BG554I –8 Lead free caBGA 554 Industrial 84 Yes LFE5UM-85F-6BG756I –6 Lead free caBGA 756 Industrial 84 Yes © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02012-2.2 103 ECP5 and ECP5-5G Family Data Sheet Part number Grade Package Pins Temp. LUTs (K) SERDES LFE5UM-85F-7BG756I –7 Lead free caBGA 756 Industrial 84 Yes LFE5UM-85F-8BG756I –8 Lead free caBGA 756 Industrial 84 Yes LFE5UM5G-25F-8MG285I –8 Lead free csfBGA 285 Industrial 24 Yes LFE5UM5G-25F-8BG381I –8 Lead free caBGA 381 Industrial 24 Yes LFE5UM5G-45F-8MG285I –8 Lead free csfBGA 285 Industrial 44 Yes LFE5UM5G-45F-8BG381I –8 Lead free caBGA 381 Industrial 44 Yes LFE5UM5G-45F-8BG554I –8 Lead free caBGA 554 Industrial 44 Yes LFE5UM5G-85F-8MG285I –8 Lead free csfBGA 285 Industrial 84 Yes LFE5UM5G-85F-8BG381I –8 Lead free caBGA 381 Industrial 84 Yes LFE5UM5G-85F-8BG554I –8 Lead free caBGA 554 Industrial 84 Yes LFE5UM5G-85F-8BG756I –8 Lead free caBGA 756 Industrial 84 Yes © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 104 FPGA-DS-02012-2.2 ECP5 and ECP5-5G Family Data Sheet Supplemental Information For Further Information A variety of technical notes for the ECP5/ECP5-5G family are available.  High-Speed PCB Design Considerations (FPGA-TN-02178)  Transmission of High-Speed Serial Signals Over Common Cable Media (FPGA-TN-02196)  PCB Layout Recommendations for BGA Packages (FPGA-TN-02024)  Minimizing System Interruption During Configuration Using TransFR Technology (FPGA-TN-02198)  Electrical Recommendations for Lattice SERDES (FPGA-TN-02077)  LatticeECP3, ECP5 and ECP5-5G Soft Error Detection (SED)/Correction (SEC) Usage Guide (FPGA-TN-02207)  Using TraceID (FPGA-TN-02084)  Sub-LVDS Signaling Using Lattice Devices (FPGA-TN-02208)  Advanced Security Encryption Key Programming Guide for ECP5, ECP5-5G, LatticeECP3, and LatticeECP2/MS Devices (FPGA-TN-02202)  LatticeECP3, LatticeECP2/M, ECP5 and ECP5-5G Dual Boot and Multiple Boot Feature (FPGA-TN-02203)  ECP5 and ECP5-5G sysCONFIG Usage Guide (FPGA-TN-02039)  ECP5 and ECP5-5G SERDES/PCS Usage Guide (FPGA-TN-02206)  ECP5 and ECP5-5G sysI/O Usage Guide (FPGA-TN-02032)  ECP5 and ECP5-5G sysClock PLL/DLL Design and Usage Guide (FPGA-TN-02200)  ECP5 and ECP5-5G Memory Usage Guide (FPGA-TN-02204)  ECP5 and ECP5-5G High-Speed I/O Interface (FPGA-TN-02035)  Power Consumption and Management for ECP5 and ECP5-5G Devices (FPGA-TN-02210)  ECP5 and ECP5-5G sysDSP Usage Guide (FPGA-TN-02205)  ECP5 and ECP5-5G Hardware Checklist (FPGA-TN-02038)  Solder Reflow Guide for Surface Mount Devices (FPGA-TN-02041)  ECP5 and ECP5-5G PCI Express Soft IP Ease of Use Guidelines (FPGA-TN-02045)  Programming External SPI Flash through JTAG for ECP5/ECP5-5G (FPGA-TN-02050)  Adding Scalable Power and Thermal Management to ECP5 Using L-ASC10 (FPGA-AN-02019)  MIPI D-PHY Bandwidth Matrix and Implementation (FPGA-TN-02090) For further information on interface standards, refer to the following websites:  JEDEC Standards (LVTTL, LVCMOS, SSTL): www.jedec.org  PCI: www.pcisig.com © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02012-2.2 105 ECP5 and ECP5-5G Family Data Sheet Revision History Revision 2.2, October 2020 Section Change Summary Disclaimers Introduction Architecture Added this section. Updated Table 1.1.   Updated Table 2.7. Updated content of SERDES and Physical Coding Sublayer section to add VCC core information. DC and Switching Characteristics     Updated Figure 3.14. Updated Supply Current (Static) to change Standby to Static. Updated note in Table 3.8. Updated Table 3.27 and Table 3.29. Pinout Information    Updated table in Signal Descriptions section to remove GR_PCLK[Bank][num] row. Updated table in LFE5UM/LFE5UM5G to correct the Pin Type VCCAUX to VCCAUXA. Updated table in LFE5U to add column for TQFP 144 package and correct the pin count for caBGA 381 package. Ordering Information   Updated figure in ECP5/ECP5-5G Part Number Description. Updated table in Commercial and Industrial. Revision 2.1, April 2019 Section General Description Architecture Change Summary In the Features section, changed feature to subLVDS and SLVS, SoftIP MIPI D-PHY receiver/transmitter interfaces under Programmable sysI/O™ Buffer Supports Wide Range of Interfaces. Updated the Supported sysI/O Standards section. DC and Switching Characteristics      Updated Table 3.11. sysI/O Recommended Operating Conditions. Added/revised standards and values. Corrected typo from LVCOM to LVCMOS. Updated Table 3.12. Single-Ended DC Characteristics. Corrected typo from LVCOM to LVCMOS. Pinout Information   Updated Configuration Pads (Used during sysCONFIG) in Signal Descriptions table. Removed note 3. Supplemental Information  All Updated document numbers of:  PCB Layout Recommendations for BGA Packages to FPGA-TN-02024  ECP5 and ECP5-5G sysI/O Usage Guide to FPGA-TN-02032  ECP5 and ECP5-5G High-Speed I/O Interface to FPGA-TN-02035  Added MIPI D-PHY Bandwidth Matrix and Implementation Technical Note. Minor editorial changes. Revision 2.0, April 2018 Section Pin Information Summary Change Summary Adjusted tables in the LFE5UM/LFE5UM5G and the LFE5U sections. Supplemental Information Updated document number of ECP5 and ECP5-5G sysCONFIG Usage Guide to FPGA-TN02039. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 106 FPGA-DS-02012-2.2 ECP5 and ECP5-5G Family Data Sheet Revision 1.9, March 2018 Section All Change Summary Updated formatting and page referencing. General Description Updated Table 1.1. ECP5 and ECP5-5G Family Selection Guide. Added caBGA256 package in LFE5U-45. Architecture Added a row for SGMII in Table 2.13. LFE5UM/LFE5UM5G SERDES Standard Support. Updated footnote #1. DC and Switching Characteristics            Updated Table 3.2. Recommended Operating Conditions. Added 2 rows and updated values in Table 3.7. DC Electrical Characteristics. Updated Table 3.8. ECP5/ECP5-5G Supply Current (Standby). Updated Table 3.11. sysI/O Recommended Operating Conditions. Updated Table 3.12. Single-Ended DC Characteristics. Updated Table 3.13. LVDS. Updated Table 3.14. LVDS25E DC Conditions. Updated Table 3.21. ECP5/ECP5-5G Maximum I/O Buffer Speed. Updated Table 3.28. Receiver Total Jitter Tolerance Specification. Updated header name of section 3.28 CPRI LV E.24/SGMII(2.5 Gbps) Electrical and Timing Characteristics. Updated header name of section 3.29 Gigabit Ethernet/SGMII (1.25 Gbps)/CPRI LV E.12 Electrical and Timing Characteristics. Pinout Information Updated table in section 4.3.2 LFE5U. Ordering Information   Supplemental Information Updated For Further Information section. Added table rows in 5.2.1 Commercial. Added table rows in 5.2.2 Industrial. Revision 1.8, November 2017 Section General Description Change Summary Updated Table 1.1. ECP5 and ECP5-5G Family Selection Guide. Added caBGA256 package in LFE5U-12 and LFE5U-25. Revision 1.7, April 2017 Section All General Description Architecture DC and Switching Characteristics Pinout Information Change Summary Changed document number from DS1044 to FPGA-DS-02012. Updated Features section. Changed 1.1 V core power supply to 1.1 V core power supply for ECP5, 1.2 V core power supply for ECP5UM5G. Updated Overview section. Change The ECP5/ECP5-5G devices use 1.1 V as their core voltage to The ECP5 devices use 1.1 V, ECP5UM5G devices use 1.2 V as their core voltage.  Updated Table 3.2. Recommended Operating Conditions.  Added ECP5-5G on VCC to be 1.2V +/- 5%.  Added ECP5-5G on VCCA to be 1.2V +/- 3%.  Updated Table 3.8. ECP5/ECP5-5G Supply Current (Standby).  Changed Core Power Supply Current for ICC on LFE5UM5G devices.  Changed SERDES Power Supply Current (Per Dual) for ICCA on LFE5UM5G devices.  Updated Table 3.20. Register-to-Register Performance.  Remove (DDR/SDR) from DSP Function.  Changed DSP functions to 225 MHz. Update Section 4.1 Signal Description. Revised Vcc Description to Power supply pins for core logic. Dedicated pins. VCC = 1.1 V (ECP5), 1.2 V (ECP5UM5G). © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02012-2.2 107 ECP5 and ECP5-5G Family Data Sheet Revision 1.6, February 2016 Section All General Description Change Summary Changed document status from Preliminary to Final. DC and Switching Characteristics   Pinout Information Ordering Information   Updated Features section. Changed 24K to 84K LUTs to 12K to 84K LUTs. Added LFE5U-12 column to Table 1.1. ECP5 and ECP5-5G Family Selection Guide. Updated Power up Sequence section. Identified typical ICC current for specific devices in Table 3.8. ECP5/ECP5-5G Supply Current (Standby).  Updated values in Table 3.9. ECP5.  Updated values in Table 3.10. ECP5-5G.  Added values to –8 Timing column of Table 3.19. Pin-to-Pin Performance.  Added values to –8 Timing column of Table 3.20. Register-to-Register Performance.  Changed LFE5-45 to All Devices in Table 3.22. ECP5/ECP5-5G External Switching Characteristics.  Added table notes to Table 3.31. PCIe (5 Gb/s).  Added table note to Table 3.32. CPRI LV2 E.48 Electrical and Timing Characteristics.  Added values to Max column of Table 3.39. Transmit. Added LFE5U-12 column to the table in LFE5U section. Updated LFE5U in ECP5/ECP5-5G Part Number Description section: added 12 F = 12K LUTs to Logic Capacity. Added LFE5U-12F information to Ordering Part Numbers section. Revision 1.5, November 2015 Section All Change Summary   Added ECP5-5G device family. Changed document title to ECP5 and ECP5-5G Family Data Sheet. Revision 1.4, November 2015 Section General Description Architecture Change Summary Updated Features section. Added support for eDP in RDR and HDR.   DC and Switching Characteristics Ordering Information Updated Overview section.  Revised Figure 2.1. Simplified Block Diagram, LFE5UM/LFE5UM5G-85 Device (Top Level). Modified Flexible sysI/O description and Note. Updated SERDES and Physical Coding Sublayer section.  Changed E.24.V in CPRI protocol to E.24.LV.  Removed 1.1 V from paragraph on unused Dual.  Updated Hot Socketing Requirements section. Revised VCCHTX in table notes 1 and 3. Indicated VCCHTX in table note 4.  Updated SERDES High-Speed Data Transmitter section. Revised VCCHTX in table note 1. Updated ECP5/ECP5-5G Part Number Description section. Changed LFE5 FPGA under Device Family to ECP5 FPGA. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 108 FPGA-DS-02012-2.2 ECP5 and ECP5-5G Family Data Sheet Revision 1.3, August 2015 Section General Description Architecture Change Summary Updated Features section.  Removed SMPTE3G under Embedded SERDES.  Added Single Event Upset (SEU) Mitigation Support.  Removed SMPTE protocol in fifth paragraph. General update. DC and Switching Characteristics General update. Pinout Information Updated Signal Descriptions section. Revised the descriptions of the following signals:  P[L/R] [Group Number]_[A/B/C/D]  P[T/B][Group Number]_[A/B]  D4/IO4 (Previously named D4/MOSI2/IO4)  D5/IO5 (Previously named D5/MISO/IO5)  VCCHRX_D[dual_num]CH[chan_num]  VCCHTX_D[dual_num]CH[chan_num] Supplemental Information Added TN1184 reference. Revision 1.2, August 2014 Section All General Description Change Summary Changed document status from Advance to Preliminary.    Architecture    DC and Switching Characteristics        Updated Features section.  Deleted Serial Rapid I/O protocol under Embedded SERDES.  Corrected data rate under Pre-Engineered Source Synchronous I/O. Changed DD3. LPDDR3 to DDR2/3, LPDDR2/3. Mentioned transmit de-emphasis pre- and post-cursors. Updated Overview section.  Revised description of PFU blocks.  Specified SRAM cell settings in describing the control of SERDES/PCS duals. Updated SERDES and Physical Coding Sublayer section.  Changed PCI Express 2.0 to PCI Express Gen1 and Gen2.  Deleted Serial RapidIO protocol.  Updated Table 2.13. LFE5UM/LFE5UM5G SERDES Standard Support.  Updated Table 2.15. LFE5UM/LFE5UM5G Mixed Protocol Support. Updated On-Chip Oscillator section.  Deleted 130 MHz ±15% CMOS oscillator.  Updated Table 2.16. Selectable Master Clock (MCLK) Frequencies during Configuration (Nominal) Updated Absolute Maximum Ratings section. Added supply voltages VCCA and VCCAUXA. Updated sysI/O Recommended Operating Conditions section. Revised HSULD12D VCCIO values and removed table note. Updated sysI/O Single-Ended DC Electrical Characteristics section. Revised some values for SSTL15 _I, SSTL15 _II, SSTL135_I, SSTL15_II, and HSUL12. Updated External Switching Characteristics section. Changed parameters to tSKEW_PR VCCA and tSKEW_EDGE and added LFE5-85 as device. Updated ECP5 Family Timing Adders section. Added SSTL135_II buffer type data. Removed LVCMOS33_20mA, LVCMOS25_20mA, LVCMOS25_16mA, LVCMOS25D_16mA, and LVCMOS18_16mA buffer types. Changed buffer type to LVCMOS12_4mA and LVCMOS12_8mA. Updated Maximum I/O Buffer Speed section. Revised Max values. Updated sysCLOCK PLL Timing section. Revised tDT Min and Max values. Revised tOPJIT Max value. Revised number of samples in table note 1. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02012-2.2 109 ECP5 and ECP5-5G Family Data Sheet      Updated SERDES High-Speed Data Transmitter section. Updated Table 3.24. Serial Output Timing and Levels and Table 3.25. Channel Output Jitter. In SERDES High-Speed Data Receiver section, updated Table 3.26. Serial Input Data Specifications, Table 3.28. Receiver Total Jitter Tolerance Specification, and Table 3.29. External Reference Clock Specification (refclkp/refclkn). Modified section heading to XXAUI/CPRI LV E.30 Electrical and Timing Characteristics. Updated Table 3.33 Transmit and Table 3.34. Receive and Jitter Tolerance. Modified section heading to CPRI LV E.24 Electrical and Timing Characteristics. Updated Table 3.35. Transmit and Table 3.36. Receive and Jitter Tolerance. Modified section heading to Gigabit Ethernet/SGMII/CPRI LV E.12 Electrical and Timing Characteristics. Updated Table 3.37. Transmit and Table 3.38. Receive and Jitter Tolerance. Revision 1.1, June 2014 Section Ordering Information Change Summary Updated ECP5/ECP5-5G Part Number Description and Ordering Part Numbers sections. Revision 1.0, March 2014 Section All Change Summary Initial release. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 110 FPGA-DS-02012-2.2 www.latticesemi.com