ECP5 Versa Development Board
Evaluation Board User Guide
FPGA-EB-02021-2.4
November 2021
ECP5 Versa Development Board
Evaluation Board User Guide
Disclaimers
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products for any particular purpose. All information herein is provided AS IS, with all faults and associated risk the responsibility entirely of the Buyer.
Buyer shall not rely on any data and performance specifications or parameters provided herein. Products sold by Lattice have been subject to limited
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products should be used in conjunction with mission- or safety-critical or any other application in which the failure of Lattice’s product could create a
situation where personal injury, death, severe property or environmental damage may occur. The information provided in this document is
proprietary to Lattice Semiconductor, and Lattice reserves the right to make any changes to the information in this document or to any products at
any time without notice.
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All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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Contents
Acronyms in This Document ................................................................................................................................................. 5
1. Introduction .................................................................................................................................................................. 6
2. Features ........................................................................................................................................................................ 7
3. ECP5 Device .................................................................................................................................................................. 7
4. Applying Power to the Board........................................................................................................................................ 8
5. Programming/FPGA Configuration ............................................................................................................................... 9
5.1.
Alternate Programmer Download Interface ....................................................................................................... 9
5.2.
Diamond Programmer Requirements ................................................................................................................. 9
6. Setting the Configuration Mode ................................................................................................................................. 10
6.1.
Board Programming .......................................................................................................................................... 10
6.1.1. Configuration Status Indicators .................................................................................................................... 10
6.2.
PROGRAMN and GSRN ...................................................................................................................................... 10
6.3.
Programming Serial SPI Flash Memory ............................................................................................................. 11
7. On-Board Clock Capabilities ....................................................................................................................................... 13
7.1.
General Purpose Clock Source .......................................................................................................................... 14
7.2.
SERDES .............................................................................................................................................................. 14
8. FPGA Test Pins ............................................................................................................................................................ 15
8.1.
General Purpose DIP Switches .......................................................................................................................... 15
8.2.
General Purpose LEDs ....................................................................................................................................... 16
8.3.
Alpha-numeric LED Display ............................................................................................................................... 16
8.4.
DDR3 Memory Device ....................................................................................................................................... 17
8.5.
Ethernet Interfaces ........................................................................................................................................... 18
9. Ordering Information ................................................................................................................................................. 20
References .......................................................................................................................................................................... 21
Technical Support Assistance .............................................................................................................................................. 22
Appendix A. ECP5 Versa Development Board Schematics ................................................................................................. 23
Appendix B. ECP5 Versa Development Board Bill of Materials .......................................................................................... 33
Appendix C. Demo Board Rev A Information ..................................................................................................................... 41
ECP5 Versa Development Board – Working with Revision A.......................................................................................... 41
Revision History................................................................................................................................................................... 42
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02021-2.4
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ECP5 Versa Development Board
Evaluation Board User Guide
Figures
Figure 1.1. ECP5 Versa Development Board, Top Side .........................................................................................................6
Figure 4.1. Power Distribution Scheme ................................................................................................................................8
Figure 6.1. ECP5 Status LEDs and Push-button Controls ....................................................................................................10
Figure 6.2. Diamond Programmer Main Screen .................................................................................................................11
Figure 6.3. Device Properties Dialog Box ............................................................................................................................12
Figure 7.1. Clock Controller Scheme ...................................................................................................................................13
Figure 7.2. PCI Express PRSNT Control Connection ............................................................................................................14
Figure 8.1. ECP5 Versa Development Board LEDs and Switches ........................................................................................15
Figure 8.2. 14-Segment Display ..........................................................................................................................................16
Figure A.1. Board Block Design ...........................................................................................................................................23
Figure A.2. Voltage Regulators ...........................................................................................................................................24
Figure A.3. Programming ....................................................................................................................................................25
Figure A.4. SERDES ..............................................................................................................................................................26
Figure A.5. 10/100/1000-T PHY #1/RJ45 ............................................................................................................................27
Figure A.6. 10/100/1000-T PHY #2/RJ45 ............................................................................................................................28
Figure A.7. DDR3 Memory ..................................................................................................................................................29
Figure A.8. LEDs and Switches ...........................................................................................................................................30
Figure A.9. Reference Clock Generator ..............................................................................................................................31
Figure A.10. Expansion Connector ......................................................................................................................................32
Figure C.1. CFG[2:0] Setting Resistor Field – Revision A .....................................................................................................41
Tables
Table 4.1. Board Power Supply Fuses ...................................................................................................................................8
Table 5.1. JTAG Connector Pinout (J3) ..................................................................................................................................9
Table 6.1. CFG[2:0] Selection – Rev B .................................................................................................................................10
Table 7.1. PCI Express Channel Interconnections ...............................................................................................................14
Table 7.2. SMA Test Interconnections ................................................................................................................................14
Table 8.1. FPGA Ball to DIP Switch Position ........................................................................................................................15
Table 8.2. LED Definitions ...................................................................................................................................................16
Table 8.3. Alpha-numeric LED Definitions ..........................................................................................................................16
Table 8.4. DDR3 Memory Controller Interconnections ......................................................................................................17
Table 8.5. PHY Status Indicators .........................................................................................................................................18
Table 8.6. FPGA GPIO to RGMII Interfaces .........................................................................................................................18
Table 8.7. Expansion Connections ......................................................................................................................................19
Table 9.1. Ordering Information .........................................................................................................................................20
Table C.1. CFG[2:0] Selection – Revision A .........................................................................................................................41
Table C.2. Pin Assignment Updates — Rev A versus Rev B.................................................................................................41
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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Evaluation Board User Guide
Acronyms in This Document
A list of acronyms used in this document.
Acronym
Definition
DDR
DIP
FPGA
JTAG
LVCMOS
SMA
RGMII
SPI
USB
Double Data Rate
Dual In-line Package
Field-Programmable Gate Array
Joint Test Action Group
Low Voltage Complementary Metal Oxide Semiconductor
Sub-Miniature A
Reduced Gigabit Media-Independent Interface
Serial Peripheral Interface
Universal Serial Bus
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02021-2.4
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ECP5 Versa Development Board
Evaluation Board User Guide
1. Introduction
The ECP5™ Versa Development Board allows designers to investigate and experiment with the features of the ECP5
Field-Programmable Gate Array. The features of the ECP5 Versa Development Board can assist engineers with rapid
prototyping and testing of their specific designs. The ECP5 Versa Development Board is part of the ECP5 Versa
Development Kit. The guide is intended to be referenced in conjunction with demo user guides to demonstrate the
ECP5 FPGA.
SERDES Test
SMA Connectors
Push -but tons
LED
Display
Configuration
Mode
Switches
DDR3
Memory
Expansion Connectors
User
Switches
Stat us LEDs
Dual RJ45
Ethernet Ports
USB Programming
SPI Flash
Configuration
Memory
JTAG
Interface
Dual RJ45
Ethernet
Ports
ECP5 Device
On -Board
Clock
Management
12 V DC
Power Input
PCI Express x1
Figure 1.1. ECP5 Versa Development Board, Top Side
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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Evaluation Board User Guide
2. Features
•
•
•
•
•
•
•
•
•
•
•
Half-length PCI Express form-factor
Allows demonstration of PCI Express x1 interconnection
Electrical testing of one full-duplex SERDES channel through SMA connections
USB-B connection for UART and device programming
Two RJ45 interfaces to 10/100/1000 Ethernet to RGMII
On-board Boot Flash
128 M Serial SPI Flash
DDR3-1866 memory components (64 Mb/x16)*
Expansion mezzanine interconnection for prototyping
14-segment alpha-numeric display
Switches, LEDs and displays for demo purposes
Diamond® programming support
On-board reference clock sources
The contents of this user guide include top-level functional descriptions of the various portions of the evaluation board,
descriptions of the on-board connectors, diodes and switches and a complete set of schematics.
*Note: The ECP5 FPGA supports DDR3 memory at data rates up to 800 Mbps.
Caution: The ECP5 Versa Development Board contains ESD-sensitive components. ESD safe practices should be
followed while handling and using the evaluation board.
3. ECP5 Device
This board features an ECP5 FPGA with a 1.1 V core supply. It can accommodate all pin-compatible ECP5 de-vices in the
381 ball caBGA package. A complete description of this device can be found in FPGA-DS-02012, ECP5 Family Data
Sheet.
Note: The connections referenced in this document refer to the LFE5UM-45F-8BG381C device.
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02021-2.4
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ECP5 Versa Development Board
Evaluation Board User Guide
4. Applying Power to the Board
The ECP5 Versa Development Board is ready to power on. The board can be supplied with power from a PCI Express
host system or standalone with an external wall power module.
The 12 V DC input power source is fused with a surface mounted fuse, as noted in Table 1.
Table 4.1. Board Power Supply Fuses
Fuse Designator
F1
Note: See Figure A.2.
Description
12 V Input Supply Fuse
The board may be plugged into a host PC. Only plug the board into a PCI Express slot when the system is powered off.
Once inserted, the PC can be safely powered on.
Using the evaluation board outside of a PC chassis supply requires the factory-supplied wall supply module. Use of
other supplies is not suggested.
EN
LDO
SERDES VCCA0: 1.1 V, 0.5 A
Status LED: D12
EN
LDO
12 V, 5 A fused
Status LED: D13
SW
SERDES VCCHTX0: 1.1 V, 0.5 A
2.5 V, 1.1 A
Status LED: D31
EN
SW
3.3 V, 1.35 A
Status LED: D9
SW
1.5 V, 1.1 A
Status LED: D11
EN
SW
VCC Core: 1.1 V, 1.35 A
Status LED: D10
Figure 4.1. Power Distribution Scheme
Note: See Figure A.2
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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ECP5 Versa Development Board
Evaluation Board User Guide
5. Programming/FPGA Configuration
The ECP5 Versa Development Board has a built-in download controller for programming the ECP5 FPGA. The built-in
module consists of a USB Type-B connector and a USB UART device. To use the built-in download cable, simply connect
a standard USB cable (a USB-B to USB-A cable is included with the ECP5 Versa Development Kit) from J2 to your PC
(with Diamond programming software installed). The USB hub on the PC will detect the addition of the USB function,
making the built-in cable available for use with the Diamond programming software. The USB cable is connected in
parallel to J3.
5.1. Alternate Programmer Download Interface
J3 is a 10 pin JTAG connector that is provided for use with an external Lattice download cable (available separately). A
USB download cable can be attached to the board using J3 to interface with the FPGA (U1).
Note: Resistors R38, R33, R32 and R36 need to be removed for programming with J3.
The same interface can be used to access the ispClock 5406D clock device (U13) by reconfiguring the jumpers on J50
See Figure A.3. U13 is factory-programmed for use with the reference designs and should only be altered for
customized designs.
Table 5.1. JTAG Connector Pinout (J3)
Pin
1
2
3
4
5
6
7
8
9
10
Function
PWR
TDO
TDI
PROGRAMn
N/C
TMS
GND
TCK
DONE
INITn
Note: See Figure A.3.
5.2. Diamond Programmer Requirements
Note: This board includes the built-in download module and only requires the USB cable included with the board. After
initial board setup, use the following procedure to program the board. Instructions assume that Diamond Programmer
software has been installed on a local PC.
Requirements:
• PC with Diamond Programmer 3.5.1 (or later) programming software, installed with appropriate drivers (USB
driver for USB cable).
Note: An option to install these drivers is included as part of the Diamond Programmer setup.
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02021-2.4
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ECP5 Versa Development Board
Evaluation Board User Guide
6. Setting the Configuration Mode
The ECP5 device on the ECP5 Versa Development Board supports a variety of configuration modes, including 1149.1
JTAG and Master SPI. Refer to ECP5 sysCONFIG Usage Guide (FPGA-TN-02039). On the PCB version Rev B, use the CFG
Setting Dip Switch SW4 described in Table 6.1.
Table 6.1. CFG[2:0] Selection – Rev B
Configuration Mode
1149.1 JTAG only
Slave SPI
Master SPI
SCM (Slave_Serial)
SCM (Slave_Parallel)
CFG[2:0]
000
001
010
101
111
SW4.3
Down
Down
Down
Up
Up
SW4.2
Down
Down
Up
Down
Up
SW4.1
Down
Up
Down
Up
Up
6.1. Board Programming
6.1.1. Configuration Status Indicators
See Figure A.3.
Figure 6.1. ECP5 Status LEDs and Push-button Controls
The LEDs indicate the configuration status of the ECP5 FPGA.
• D17 (red) illuminated indicates that programming was aborted or reinitialized, driving the INITN output low.
• D20 (green) illuminated indicates the successful completion of configuration by releasing the open collector DONE
output pin.
• D19 (red) illuminated indicates that PROGRAMN is low.
• D18 (red) illuminated indicates that GSRN is low.
6.2. PROGRAMN and GSRN
These push-button switches assert/de-assert the logic levels on PROGRAMN (SW2) and GSRN (SW1). De-pressing the
button drives a logic level “0” to the device.
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6.3. Programming Serial SPI Flash Memory
A serial SPI (16-pin TSSOP, 128M) Flash memory device (U52) is on-board for non-volatile configuration memory
storage. A Micron N25Q128A device is populated on-board.
The Serial SPI Flash memory device can be configured easily through the ECP5 JTAG port. This mode enables the FPGA
to be programmed at power-up or assertion of PROGRAMN with a bitstream stored in the memory device.
1.
Connect the ECP5 Versa Development Board.
2.
Scan the board or select the LFE5UM-45F device in the ECP5UM device family.
3.
From the Edit pull down menu select Device Properties. Set the Access mode to SPI Flash Background
Programming and Operation to SPI Flash Erase, Program, Verify.
Figure 6.2. Diamond Programmer Main Screen
4.
Under the SPI Flash Options, select Family to SPI Serial Flash, Vendor to Micron, Device to SPI-N25Q128A,
Package to 16-pin SO16.
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All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02021-2.4
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ECP5 Versa Development Board
Evaluation Board User Guide
Figure 6.3. Device Properties Dialog Box
5.
Click OK in the Device Properties dialog box. You will return to the main configuration screen.
6.
Set J50 jumper to ECP5 programming. See Figure A.3.
7.
Ensure the Configuration Mode is set to Master SPI using DIP Switch SW4. See Table 6.1.
8.
From the main programming window, select Program from the top toolbar. This begins the SPI Serial Flash
programming. Note that the SPI Flash Background Programming operation is only possible when the ECP5 device is
either erased or the active design has the MASTER_SPI_PORT mode enabled. For more details see ECP5 sysCONFIG
Usage Guide (FPGA-TN-02039).
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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ECP5 Versa Development Board
Evaluation Board User Guide
7. On-Board Clock Capabilities
See Figure A.9.
The ECP5 Versa Development Board allows for several clock source options. Some of these options are controlled
through the ispClock5406D programmable clock manager device. The ispClock5406D enables the reference clock from
the PCI Express interface to provide a reference clock to the SERDES. This is true only when the board is in a PCI Express
host socket. When the board is not in a PCI Express host socket, the clock will be sup-plied by a 156.25 MHz clock onboard oscillator. Both clock inputs can be fanned out to the dedicated SERDES reference inputs, FPGA inputs, and to
the expansion connectors. The factory default programming only connects the SERDES reference clock inputs. Factorydefined demonstration designs will control and manage the clock.
PCLKT0
A4
FPGA Clock
PCLKC0
A5
PCIE_PRSNT#
SERDES D0
Reference
Clock
PCI Express
0
156.25 MHz
Onboard
Oscillator
1
REFCLKP_D0
Y11
REFCLKN_D0
Y12
Factory Default
Clock Programming
SERDES D1
Reference
Clock
REFCLKP_D1
Y19
REFCLKN_D1
W20
Expansion Interface
Clock(X3)
Figure 7.1. Clock Controller Scheme
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FPGA-EB-02021-2.4
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ECP5 Versa Development Board
Evaluation Board User Guide
7.1. General Purpose Clock Source
An on-board 100 MHz LVDS oscillator is provided for general purpose use. This clock source is connected to differential
inputs P3 and P4 and must be used as LVDS inputs to the FPGA. This pin pair also provides optimal interface to the
FPGA PLL for customized use.
The PCI Express add-in card specification requires add-in boards to include capabilities to tell the host of its presence.
The ECP5 Versa Development Board allows this optional connection through a board jumper. Using the board with a
PCI Express host requires the setting shown in Figure 7.2.
Figure 7.2. PCI Express PRSNT Control Connection
7.2. SERDES
The ECP5 Dual Channel Unit (DCU) SERDES FPGA is utilized on the board for several purposes. DCU0, Channel 0 is
provisioned to provide a single, full-duplex PCI Express channel. The high-speed signals are connected to the PCI
Express edge connection. DCU0, Channel 1 is connected to the SMA connectors for external electrical demonstrations.
Table 7.1. PCI Express Channel Interconnections
Signal Name
PETp0
PETn0
PERp0
PERn0
SERDES Port
HDRXP0_D0CH0
HDRXN0_D0CH0
HDTXP0_D0CH0
HDTXN0_D0CH0
FPGA Ball Number
Y5
Y6
W4
W5
SERDES Port
HDRXP0_D0CH1
HDRXN0_D0CH1
HDTXP0_D0CH1
HDTXN0_D0CH1
FPGA Ball Number
Y7
Y8
W8
W9
Table 7.2. SMA Test Interconnections
Connector
J5
J6
J7
J8
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FPGA-EB-02021-2.4
ECP5 Versa Development Board
Evaluation Board User Guide
8. FPGA Test Pins
See Figure A.8.
8.1. General Purpose DIP Switches
General purpose FPGA pins are available for user applications. FPGA pins are connected to switch SW3, a SPST slideactuated DIP switch. The switches are connected to logic level 0 when moved to the ON position. Switch position 1 is
indicated with an arrow. Inputs 1-4 are within a 1.5 V bank and inputs 5-8 are within a 2.5 V bank. The user must
program inputs 1-4 to be the LVCMOS15 type and inputs 5-8 to be the LVCMOS25 type in the design. Figure 8.1 shows
the switches. Note the silk marking associated with SW3-7 is incorrect in revision B, SW3-7 is mapped to K19, per Table
8.1.
Figure 8.1. ECP5 Versa Development Board LEDs and Switches
The designated pins are connected according to Table 8.1.
Table 8.1. FPGA Ball to DIP Switch Position
FPGA Ball Number
H2
K3
G3
F2
J18
K18
K19
K20
SW3 DIP Switch Position
1
2
3
4
5
6
7
8
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FPGA-EB-02021-2.4
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ECP5 Versa Development Board
Evaluation Board User Guide
8.2. General Purpose LEDs
See Figure A.8.
The LEDs provided on the ECP5 Versa Development Board are connected to general purpose FPGA I/O. These LEDs
provide status for user designs and must be included in the design. The LEDs illuminate when the FPGA output is driven
LOW. Table 8.2 shows the LED and associated FPGA pins. These pins are within an I/O bank connected to 2.5 V and the
user should program these to be LVCMOS25 type outputs in the design.
Table 8.2. LED Definitions
LED Designator
D25
D24
D22
D21
D26
D27
D28
D29
FPGA Ball Number
E16
D17
D18
E18
F17
F18
E17
F16
LED Color
Yellow
Yellow
Green
Green
Red
Red
Red
Red
8.3. Alpha-numeric LED Display
See Figure A.8.
A 14-segment alpha-numeric display is provided on the board (D23). These LED segments are connected to generalpurpose FPGA I/O. The LEDs must be included in the FPGA design. The LEDs illuminate when the FPGA output is driven
LOW. Table 8.3 shows the LED and associated FPGA pins. These pins are within an I/O bank connected to 2.5 V and the
user should program these to be LVCMOS25 outputs in the design.
Figure 8.2. 14-Segment Display
Table 8.3. Alpha-numeric LED Definitions
Display
A
B
C
D
E
F
G
H
FPGA Ball Number
M20
L18
M19
L16
L17
M18
N16
M17
Display
J
K
L
M
N
P
DP
FPGA Ball Number
N18
P17
N17
P16
R16
R17
U1
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16
FPGA-EB-02021-2.4
ECP5 Versa Development Board
Evaluation Board User Guide
8.4. DDR3 Memory Device
See Figure A.7.
• The ECP5 Versa Development Board is equipped with an SDRAM memory device (1.5 V, 64 Mb/x16, 96-ball FBGA,
933 MHz, DDR3-1866) such as the Micron MT41K64M16TW-107:J device.
• The DDR3 memory includes a 16-bit wide memory controller interface.
• The board includes termination of data, address and command signals. It includes all power and external
components needed to demonstrate the memory controller of the ECP5 device.
• A 100 MHz on-board clock oscillator is available to provide a DDR3 reference clock.
Table 8.4. DDR3 Memory Controller Interconnections
DDR3 Signal
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
FPGA Ball Number
L5
F1
K4
G1
L4
H1
G2
J3
D1
C1
E2
C2
F3
A2
DDR3 Signal
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
K_0
FPGA Ball Number
P2
C4
E5
F5
B3
F4
B5
E4
C5
E3
D5
B4
C3
M4
DQ14
DQ15
DQS0
DQS0#
DQS1
DQS1#
CE0
RAS#
CLKP
CLKN
RST#
E1
B1
K2
J1
H4
G5
N2
P1
P3
P4
N4
K_0#
CAS#
BA0
BA1
BA2
ODT
CS0#
WE#
VREF
DM0
DM1
N5
L1
P5
N3
M3
L2
K1
M1
K5
J4
H5
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02021-2.4
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ECP5 Versa Development Board
Evaluation Board User Guide
8.5. Ethernet Interfaces
See Figure A.5 and Figure A.6.
Two Marvell 88E1512 Gigabit Ethernet transceiver devices (U14 and U15) are included on the board. These physical
layer devices support 1000BASE-T, 100BASE-TX, and 10BASE-T applications through a standard media interface to a
dual RJ45 connection. The RJ45 connection includes network magnetics providing the proper signal conditioning,
electro-magnetic interference suppression and signal isolation. Each connector includes two LEDs which are controlled
by the 88E1512 devices. Detailed descriptions are available in the Marvell device data sheet.
Table 8.5. PHY Status Indicators
LED
RJ45 (Yellow)
RJ45 (Green/Orange)
Status Description
Data RX/TX
Link State
Each Marvell 88E1512 device communicates through an RGMII interface to the ECP5 device.
Table 8.6. FPGA GPIO to RGMII Interfaces
Signal
CLK125
CLK125Pll
Config
Resetn
TXCLK
TX_D0
TX_D1
TX_D2
Phy1
L19
U16
T17
U17
P19
N19
N20
P18
Phy2
J20
C18
G20
F20
C20
J17
J16
D19
TX_D3
TXCTRL
RXCLK
RX_D0
RX_D1
RX_D2
RX_D3
RXCTRL
MDIO
MDC
P20
R20
L20
T20
U20
T19
R18
U19
U18
T18
D20
E19
J19
G18
G16
H18
H17
F19
H20
G19
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
18
FPGA-EB-02021-2.4
ECP5 Versa Development Board
Evaluation Board User Guide
Table 8.7. Expansion Connections
X3 Expansion Connector
Pin
Signal
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
GND
NC
2V5
IO29
IO30
IO31
IO32
IO33
IO34
IO35
IO36
IO37
IO38
IO39
IO40
IO41
IO42
IO43
IO44
IO45
5VIN
GND
2V5
GND
3V3
GND
3V3
GND
OSC
GND
CLKIN
GND
CLKOUT
GND
3V3
GND
3V3
GND
3V3
GND
X4 Expansion Connector
FPGA Ball
Number
—
—
—
B19
B12
B9
E6
D6
E7
D7
B11
B6
E9
D9
B8
C8
D8
E8
C7
C6
—
—
—
—
—
—
—
—
—
—
A10
—
E11
—
—
—
—
—
—
—
Pin
Signal
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
RESOUT#
GND
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
IO8
IO9
IO10
IO11
IO12
IO13
IO14
IO15
GND
3V3
IO16
GND
IO17
GND
IO18
GND
IO19
IO20
IO21
GND
IO22
IO23
IO24
GND
IO25
IO26
IO27
CARDSEL#
IO28
GND
FPGA Ball
Number
A8
—
A12
A13
B13
C13
D13
E13
A14
C14
D14
E14
D11
C10
A9
B10
D12
E12
—
—
B15
—
C15
—
D15
—
E15
A16
B16
—
C16
D16
B17
—
C17
A17
B18
A7
A18
—
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02021-2.4
19
ECP5 Versa Development Board
Evaluation Board User Guide
9. Ordering Information
Table 9.1. Ordering Information
Description
Ordering Part Number
ECP5 Versa Development Board
LFE5UM-45F-VERSA-EVN
China RoHS Environment-Friendly Use Period (EFUP)
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
20
FPGA-EB-02021-2.4
ECP5 Versa Development Board
Evaluation Board User Guide
References
•
•
•
•
•
ECP5 and ECP5-5G Family Data Sheet (FPGA-DS-02012)
PCI Express Demos for the ECP5 and ECP5-5G Versa Development Board (FPGA-UG-02006)
DDR3 Demo for the ECP5 Versa Development Board (UG97)
SERDES Eye Demo for the ECP5 Versa Development Board (UG93)
SEU (Single Event Upset) Demo for the ECP5 Versa Development Board (UG92)
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02021-2.4
21
ECP5 Versa Development Board
Evaluation Board User Guide
Technical Support Assistance
Submit a technical support case through www.latticesemi.com/techsupport.
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
22
FPGA-EB-02021-2.4
ECP5 Versa Development Board
Evaluation Board User Guide
Appendix A. ECP5 Versa Development Board Schematics
5
4
3
2
Revision History:
Sept 25, 2015
May 30, 2017
1
Rev A Final Design
Rev B PCIe Improvements
SH
RK
Designator U1 is the FPGA DUT.
D
D
Power
Expansion
Port-3.3V
Device
Power
Pins
Bank 2
1.5V
16-Bit
Bank 0
2.5V
RGMII
PHY#1
Bank 1
DDR3
C
USER DIP
SWITCH
Expansion
Port- 3.3V
C
Bank 7
Bank 6
ECP5
FPGA
Bank
2
Bank
3
SERDES
2.5V
RGMII
PHY#2
LED SEGMENT
ARRAY
PCSA
Bank
8
Programming
3.3V SPI
B
USER LEDS
PLL
100.00M
DIFF OSC
Bank 6,7
B
PCIe
CH#0
X1
SMA Test
CH#3
CLK5406
A
RefClk
156.25M OSC
PCSA
RefClk
REFERENCE
CLOCKS
PCIe
General Clk
A
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Expansion Clk
Title
Board Block Diagram
Size
Project
B ECP5 5G VERSA Eval Board RevB
5
4
3
2
Date: Thursday, June 08, 2017
Sheet
1
Schematic Rev B
Board Rev
1
of 10
B
Figure A.1. Board Block Design
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02021-2.4
23
ECP5 Versa Development Board
Evaluation Board User Guide
2
3
4
U53
2_5V
Pad
IN_8 OUT_1
IN_7 OUT_2
IN_6 OUT_3
VCtrl SET
8
7
6
5
C391
1UF-16V-0805SMT
RLP-133
C392
RLP-133
LT3085
R184
121K-0603SMT
3_3V
C24
0.45 v drop at 500 mA
max
22UF-16VTANTBSMT
Pad
IN_8 OUT_1
IN_7 OUT_2
IN_6 OUT_3
VCtrl SET
8
7
6
5
C394
1UF-16V-0805SMT
RLP-133
R140
TP25
100NFX5R-0402SM
T
TP22
VCCA
9
1
2
3
4
C393
RLP-133
LT3085
R185
121K-0603SMT
C248
100NFX5R-0402SMT
TP23
R70
+1.2 v
500 mA
+ C102 C101
1UF-16V-0805SMT
SERDES VCCA0, +1.2 V, 0.5A
10K-0603SMT
C49
22uF,6.3V-0805SMT
22
VC2
PG1
PG2
GND5
RT/SYNC
1
1
C44 1000pF-0402SMT
17
19
20
3_3V Current
TP16
L2
2
TRACK/SS2
VC1
2
18
GND6
GND7
GND8
GND9
23
C39
220NF-0402SMT
16V
11
C48
330pF-0402SMT
FB2
TRACK/SS1
24
12
C47
10pF-0402SMT
10
VIN2
VIN1
SHDN
SW2
FB1
3_3V
D2
1N4448
W
R64
4.7uH-SPD62R-472M
D4
DFLS220L
1%
R13
11_5K-0603SMT
1%
R12
51K-0402SMT
Freq = 1.0 MHz
C
3.3V
+3.3 v
1.35 A
3_3V
C50
C42
RLP-133
22uF,6.3V-0805SMT
RLP-133
TP17
0.1
1%
cr2010_alt1
R8
35_7K-0603SMT
13
14
15
16
RLP-133
SW1
GND1
GND2
GND3
GND4
R9
1%
1.2v/ms
RLP-133
22uF,6.3V-0805SMT
Vout = 0.8*(R8/R13+1) = 3.28 v
22uF,6.3V-0805SMT
Vout = 0.8*(R7/R9+1) = 2.52 v
TP3
TP1
TP4
RLP-133
LFE5UM-45F-BG381
Schematic symbols rev
4.1
2
FB2
TRACK/SS2
VC2
PG2
1
18
C57 1000pF-0402SMT
17
19
20
LED_BLUE_0603
Q1
2N2222/SOT23
1 R27
10K-0603SMT
Q2
2N2222/SOT23
2
D14
SCHOTTKY/VISHAY-V12P10
GND6
GND7
GND8
GND9
13
14
15
16
+1.5v
1.1 A
3_3V
G
LED_GREEN_0603
D11
1_5V
LED_GREEN_0603
D12
VCCA
D31
2.5V
1_5V
C64
R179
220R-0603SMT
C58
RLP-133
RLP-133
22uF,6.3V-0805SMT
Vout = 0.8*(R16/R17+1) = 1.51
v
LED_GREEN_0603
G
G
1.1V
Analog
1.2v/ms
15K-0603SMT
100pF-0402SMT
R17
16_9K-0603SMT
1%
B
1.5V
DDR3
D9
3.3V
A
R26
220R-0603SMT
3
SCHOTTKY/VISHAYV12P10
LED_GREEN_0603
D10
VCC_CORE
2_5V
TP18
0.1
1%
cr2010_alt1
1 R28
10K-0603SMT
Q3
2N2222/SOT23
1 R29
10K-0603SMT
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
2
D13
D8
DFLS220L
R66
C246
1%
LED_GREEN_0603
R24
1_8K-1206SMT
1.5V
G
12VIN GOOD
R23
1_8K-1206SMT
1.2V
VCC_CORE
3
5A Fast-Blo SMT Socketed Fuse
R22
1_8K-1206SMT
4.7uH-SPD62R-472M
R16 1%
R20
20K-0402SMT
Freq = 625 KHz
12_0V
2
R25
1_8K-1206SMT
G
D33
1
12_0V
F1251CT-ND
3
F1
SCHOTTKY/VISHAY-V12P10
G
D32
1_5V Current
TP19
22uF,6.3V-0805SMT
12_0V
12_0V
1
L4
Vout = 0.8*(R15/R21+1) = 1.21 v
12_0V
C53
220NF-0402SMT
16V
11
DNI
GND5
GND1
GND2
GND3
GND4
SW2
D6
1N4448W
12
2
10
VIN2
9
BOOST2
25
C63
RLP-133
100pF-0402SMT
R21
10K-0603SMT
1%
3
4
5
6
C245
C55
1
C56 1000pF-0402SMT FB1
2
TRACK/SS1
24
VC1
23
DNI
PG1
22
RT/SYNC
3_3V
U4
LT3508EUF
SW1
R18
63_4K-0402SMT
R15
5_11K-0603SMT
1%
VCC_CORE
C54
22uF,6.3V-0805SMT
RLP-133
SHDN
1
0.1
4.7uH-SPD62R-472M
1%
cr2010_alt1
D7
DFLS220L
+ 1.2 v
1.35 A
BOOST1
8
C60
10pF-0402SMT
Core Power
VCC_CORE, +1.2 V, 1.35 A
7
L3
VIN1
21
2
1_5V, +1.5 V, 1.1 A
TP21
R67
1.2v/ms
TP2
R14
51K-0402SMT
D5
1N4448W
C52
220NF-0402SMT
16V
1_2V Current
3_3V, +3.3 V, 1.35 A
C59
330pF-0402SMT
SW
C51
10uF,25V-1206SMT
RLP-134
3_3V
EN
SW
12_0V
SERDES VCCHTX0, +1.2 V, 0.5A
2_5V, +2.5V, 1.1 A
C62
330pF-0402SMT
LDO
C61
10pF-0402SMT
EN
EN
Title
+11v to +16v
Voltage Regulators
Size
POWER INPUT
5
SERDES VCCA
1.2V Power
U3
LT3508EU
F
BOOST2
25
1
C41
1
1000pF-0402SMT
2
C43
9
21
R6
51K-0402SMT
1%
C40
22uF,6.3V-0805SMT
RLP-133
EN
SW
2
1UF-16V-0805SMT
BOOST1
8
R7
21_5K-0603SMT
1%
2_5V
Power Supply Block Diagram
7
22uF,6.3V-0805SMT
22uF,6.3V-0805SMT
Right angle
mount, cable
to board edge
C27
VCCA1
D1
1N4448W
L1
0.1
4.7uH-SPD62R-472M
1%
cr2010_alt1
D3
DFLS220L
TP20
J11
D
VCCA0
+ C26
3
4
5
6
TP15
R63
2
C38
16V
220NF-0402SMT
R11
34K-0402SMT
TP5
1.2v/ms
12_0V
Male Power Jack 2.1mm
3
PJ-002A
SERDES VCCHTX
1.2V Power
12_0V
+2.5v
1.1 A
(5A fused)
A
1UF-16V-0805SMT
FB3
C37
10uF,25V-1206SMT
RLP-134
3_3V
LDO
+1.2 v
500 mA
+ C104 C103
22UF-16V-TANTBSMT
2.5V
SW
12_0VI
N
BLM41PG600SN1
BLM41PG600SN1
FB4
BLM41PG600SN
1
2_5V Current
U10
U11
U12
U13
U14
U7
U8
U9
V12
V13
V14
V15
V16
V19
V20
V5
V6
V7
V8
V9
W12
W15
W16
W19
W6
W7
VCCHTX1
1
C36
+
1UF-16V-0805SMT
FB8
FB7
C46
10pF-0402SMT
C35
C45
330pF-0402SMT
C34
C19
22UF-16V-TANTBSMT
VCCA
current
R10
51K-0402SMT
C33
VCCHTX0
+ C18
22UF-16V-TANTBSMT
BLM41PG600SN1
0.1
1%
cr2010_alt1
2_5V
C32
FB2
BLM41PG600SN1
0.01
1%
cr2512_alt1
22UF-16V-TANTBSMT
U54
2_5V
TP24
VCCHTX
current
C247
C25 +
1UF-16V-0805S
MT
C23
100NF-0402S
MT
C22
100NF-0402S
MT
C21
10NF-0402S
MT
C20
10NF-0402S
MT
C31
VCCHTX
9
1
2
3
4
10uF-6.3V-0805S
MT
100NF-0402S
MT
C11
100NF-0402S
MT
100NF-0402S
MT
100NF-0402S
MT
10NF-0402S
MT
100NF-0402S
MT
10NF-0402S
MT
10NF-0402S
MT
10NF-0402S
MT
10NF-0402S
MT
1NF-0402S
MT
10NF-0402S
MT
C9
R19
30_1K-0402SMT
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
C8
2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
C7
1
B
B14
B7
C19
D4
F13
F14
F7
F8
G10
G11
G12
G13
G14
G15
G17
G4
G6
G7
G8
G9
H19
J10
J11
J12
J14
J2
J7
J9
K10
K11
K12
K14
K15
K6
K7
K9
L10
L11
L12
L9
M10
M11
M12
M14
M16
M2
M7
M9
N14
N15
N6
N7
P11
P12
P13
P14
P7
P8
R19
NC
NC
NC
NC
C6
2
C
C29
VCCAU
X
C5
22UF-16VTANTBSMT
V17
V18
C4
VCCA1
V10
V11
W11
RESERVED2 W10
RESERVED1 K16
NC1 K17
NC2
LFE5UM-45FBG381
U1I
Schematic
GND
GNDA
symbols
rev
GND
GNDA
GND
GNDA
4.1
GND
GNDA
C3
1UF-16V-0805S
MT
VCCAUXA
VCCAUXA
1
1
F15
F6
P15
P6
C2
100NF-0402S
MT
VCCAUXA
VCCAUXA
0
0
C94
VCCA1
C28
VCCAU
VCCAU
X
VCCAU
X
VCCAU
X
X
C95
1NF-0402S
MT
T15
U15
C1
VCCA0
VCCA0
C30
10NF-0402S
MT
VCCA1
VCCA1
T6
U6
10NF-0402S
MT
VCCA0
VCCA0
100NF-0402S
MT
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
100NF-0402S
MT
U1J
1NF-0402S
MT
D
H10
H11
H12
H13
H8
H9
J13
J8
K13
K8
L13
L8
M13
M8
N10
N11
N12
N13
N8
N9
1
Voltage Regulators
VCC_COR
E
10uF-6.3V-0805SMT
5
Project
C ECP5 5G VERSA Eval Board RevB
4
3
2
Date: Thursday, June 08, 2017
1
Sheet
Schematic Rev B
Board Rev
2
of 10
B
Figure A.2. Voltage Regulators
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
24
FPGA-EB-02021-2.4
ECP5 Versa Development Board
Evaluation Board User Guide
5
3
4
1
2
3_3V
2
C
3
13
R50
1M-0603SMT
1
2
TEST
3
3
C80
12PF-0603SMT
12MHZ
3
GSRN
4
C114
100NF-0402SMT
TP7
3
TP8
C115
100NF-0402SMT
D20
PROGRAMN
Q4
2N2222/SOT23
PTS645SM43SMTR92 LFS
100NF-0402
SMT
3_3V
DONE indicator will light when
configuration is successfully
completed
R65
1 10K-0603SMTDONE
R68
10K-0402SMT
TP9
INITN
4
A2 B2
GSRN
D19
2
A1 B1
DONE
R57
4_7K-0603SMT
R69
10K-0402SMT
SpiCSSPIN
SpiSI
DQ2
R129
R130
R134
0R-0402SMT
0R-0402SMT
0R-0402SMT
C249
20pF-0603SMT
DNI
A
TP42
TP43
TP44
TP45
7
8
9
10
3
4
5
6
U52
S#
VCC
DQ1
HOLD#/DQ3
W#/VPP/DQ2
C
VSS
DQ0
DNU_3
DNU_14
DNU_4
DNU_13
DNU_5
DNU_12
DNU_6
DNU_11
2
1
16
15
14
13
12
11
R95
RLP-101
3_3V
MT25QL128ABA8ESF-0SIT TR
C243
R131
R133
C244
100NFX5R-0402SMT
0R-0402SMT DQ3
TP46
SpiMCLK TP47
0R-0402SMT SpiSO
TP48
TP38
TP39
TP40
TP41
3_3V
C84
100NF-0603SMT
C286 C287
20pF-0603SMT 20pF-0603SMT
DNI
DNI
C85
10NF-0402SMT
TP49
TP50
TP51
R135
4_7K-0603SMT
RLP-101
4_7K-0603SMT
10NF-0402SMT
R136
4_7K-0603SMT
RLP-101
Local JTAG
header (ispVM)
C78
{10}
{10}
FTDI_TMS
FTDI_TCK
D15
FTDI_TMS
FTDI_TCK
FTDI_TDI
ispCLOCK_TDI
ispCLOCK_TDO
2
4
6
4
C
{9}
{9}
HEADER 3X2
Default Jumper Settings:1&2, 3&4, 5&6
ECP5 +
ispCLOCK
ECP5
only
ispCLOCK
only
R58
R59
4_7K-0603SMT
B
P10
P9
VCCIO8
VCCIO8
CCLK/MCLK/SCK
CFG_0
CFG_1
CFG_2
DONE
INITN
PB11A/D1/MISO/IO1
PB11B/D0/MOSI/IO0
PB13A/SN/CSN/SCAN_SHFT_EN
PB13B/CS1N
PB15A/HOLDN/DI/BUSY/CSSPIN/CEN
PB15B/DOUT/CSON/ATB_FORCE
PB18A/WRITEN/ATB_SENSE
PB4A/D7/IO7
PB4B/D6/IO6
PB6A/D5/MISO2/IO5
PB6B/D4/MOSI2/IO4
PB9A/D3/IO3
PB9B/D2/IO2
PROGRAMN
TCK/TEST_CLK
TDI
TDO
TMS
U3
U4
T4
R4
Y3
V3
V2
W2
T2
U2
R2
R3
T3
R1
T1
U1
V1
W1
Y2
W3
T5
R5
V4
U5
R187
R190
SpiMCLK
50R-0603SMT
DONE
INITN
SpiSI
SpiSO
FPGA_CSN
FPGA_CS1N
SpiCSSPI
SCL
N
FPGA_WRITEN
CLK_RESETn
GSRN
SEG14
SDA
DQ3
DQ2
PROGRAMN
FTDI_TCK
ECP5_TDI
ECP5_TDO
FTDI_TMS
1K-0603SMT
CFG0
CFG1
CFG2
R191
R192
1K-0603SMT
SW4
8
3
6
2
5
1
418311170804
SCL
{9}
CLK_RESETn
{9}
SEG14
SDA
{8}
{9}
A
Bank 8
LFE5UM-45F-BG381
Schematic symbols rev
4.1
4
7
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Remove internal names in symbol?
Title
Programming
Size
Project
C ECP5 5G VERSA Eval Board RevB
5
{9}
{9}
J50
1
3
5
3_3V 1K-0603SMT
3_3V
R96
1K-0603SMT
RLP-101
7
GND
ECP5_TDI
ECP5_TDO
FTDI_TDO
Place R187 near U1
U1G
128Mb SPI Flash
TCK
INITN
3_3V
CONFIG Status LEDs
3_3V
TMS
DONE
+3.3V
TDO
TDI
PROGRAMn
TMS
GND
TCK
DONE
INITn
3_3V
TP14
INITN
DONE
2
PROGRAMN
GSRN
1
LED_RED_0603
D18
SW2
PROGRAMN
680R-0603SMT
R56
LED_RED_0603
PTS645SM43SMTR92 LFS
B
220R-0603SMT
A2 B2
G
A1 B1
3_3V
3
2
Y
1
3_3V
680R-0603SMT
R55
INITN indicator will light
if an error occurs during
configuration programming
R60
D17
680R-0603SMT R
INITN
LED_RED_0603
R61
LED_GREEN_0603
R53
10K-0402SMT
SW1
PROGRAMN Y
FPGA GSRN
C81
R51
10K-0402SMT
D16
NC
3_3V
18pF = 12pF + Ground Plane ( 6pF )
3_3V
100NF-0402
SMT
PROGRAMN
& GSRN
Pushbuttons
TXD_UART
RXD_UART
48
52
53
54
55
57
58
59
3_3V
1
ispEN_N
R75
2_2K-0603SMT-DNI
DNI
R76
0R-0603SMT-DNI 3_3V
DNI
60
PWREN#
SUSPEND# 36
FT2232H
4
G1 G2
BCBUS0
BCBUS1
BCBUS2
BCBUS3
BCBUS4
BCBUS5
BCBUS6
BCBUS7
R71
2_2K-0603SMT-DNI
DNI
TXD_UART
RXD_UART
UART_ACT
38
39
40
41
43
44
45
46
VCC
TDI
100NF-0603SMT
4
VPHY 9
VPLL
OSCO
10 AGND
1
OSCI
FTDI High-Speed USB
Y1
C79
12PF-0603SMT
BDBUS0
BDBUS1
BDBUS2
BDBUS3
BDBUS4
BDBUS5
BDBUS6
BDBUS7
R30
2_2K-0603SMT
EECS
EECLK
EEDATA
220R-0603SMT
R48
REF
TDO
HEADER 10
G
63
62
61
3_3V
4_7K-0603SMT
C77
100NF-0402SMT
USB1_CS
USB1_SK
USB1_D
USB1_Q
1
VCC
CS 2
NU
CLK 3
ORG
DI 4
VSS
DO
93LC56C-I/SN
26
27
28
29
30
32
33
34
FPGA_CSN
USB Download
8
7
6
5
RESET#
DONE
INITn
R49
4_7K-0603SMT
LED_GREEN_0603
R41
R42
R43
10K-0402SMT 10K-0402SMT 10K-0402SMT
U6
ACBUS0
ACBUS1
ACBUS2
ACBUS3
ACBUS4
ACBUS5
ACBUS6
ACBUS7
FTDI_TMS
FTDI_TCK
J3
2
3
4
5
6
8
9
10
FPGA_CS1N
L5
1UH-1206SMT
DM
DP
JTAG_ACT
R40
14
4_7K-0402SMT
R44
6
12K-0603SMT
VREGOUT
16
17
18
19
21
22
23
24
FPGA_WRITEN
3_3V
7
8
R47
R45 R46
4_7K-0603SMT
4_7K-0603SMT
4_7K-0603SMT
FTDI_TDO
FTDI_TDI
PROGRAMn
R36 0R-0603SMT
R32 0R-0603SMT
R33 0R-0603SMT
R38 0R-0603SMT
JTAG_ACT
220R-0603SMT
USB_N_i
USB_P_i
R35 0R-0402SMT
6
6
49
R39 0R-0402SMT
USB_N
USB_P
ADBUS0
ADBUS1
ADBUS2
ADBUS3
ADBUS4
ADBUS5
ADBUS6
ADBUS7
VREGIN
3_3V
GND
GND
GND
GND
GND
GND
GND
GND
1
2
3
4
5
50
3_3V
1
5
11
15
25
35
47
51
9
J2
VCC
DD+
ID
GND
U5
FT2232HL
3_3V
C74
3_3UF-10V-SMT
+
R37
15K-0603SMT-DNI
DNI
9
SKT_MINIUSB_
B_RA
7
8
7
8
FTVCC1_8V
D
FTVCC1_8V
G
C72
100NF-0402SMT
C70
R31
LED_GREEN_0603
C71
4_7UF-10V-SMT
C69
UART_ACT
2
FB6
MPZ1608Y600B +
C68
100NF-0402
SMT
1
C67
100NF-0402
SMT
C66
100NF-0402SMT
100NF-0402
SMT
C65
4_7UF-10V-SMT
20
VCCIO 31
VCCIO 42
VCCIO 56
VCCIO
2
FB5
MPZ1608Y600B +
12
VCORE 37
VCORE 64
VCORE
D
3_3V
1
3
2
Date: Thursday, June 08, 2017
1
Sheet
Schematic Rev B
Board Rev
3
of 10
B
Figure A.3. Programming
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02021-2.4
25
ECP5 Versa Development Board
Evaluation Board User Guide
5
4
U1H
HDTXP0_D0CH0
VCCHTX0
HDTXN0_D0CH0
T7
VCCHTX0_D0CH0
T11
VCCHTX0_D1CH0
HDTXP0_D0CH1
HDTXN0_D0CH1
D
HDRXP0_D0CH0
HDRXN0_D0CH0
VCCHTX1
T10
VCCHTX1_D0CH1
T14
VCCHTX1_D1CH1
HDRXP0_D0CH1
HDRXN0_D0CH1
REFCLKP_D0
REFCLKN_D0
VCCA0
T8
T12
VCCHRX0_D0CH0
HDTXP0_D1CH1
VCCHRX0_D1CH0
HDTXN0_D1CH1
HDTXP0_D1CH0
HDTXN0_D1CH0
HDRXP0_D1CH0
HDRXN0_D1CH0
W4
HDTXP0_D0CH0
W5
HDTXN0_D0CH0
W8
HDTXP0_D0CH1
W9
HDTXN0_D0CH1
Y5
Y6
x1_PETp0
x1_PETn0
Y7
HDRXP0_D0CH1
Y8
HDRXN0_D0CH1
Y11
REFCLKP_D0
Y12
REFCLKN_D0
W17
HDTXP0_D1CH1
W18
HDTXN0_D1CH1
W13
HDTXP0_D1CH0
W14
HDTXN0_D1CH0
Y14
Y15
HDRXP0_D1CH0
HDRXN0_D1CH0
Y16
HDRXP0_D1CH1
Y17
HDRXN0_D1CH1
3
100NFX5R-0402SMT
T9
VCCHRX1_D0CH1
HDRXP0_D1CH1
VCCHRX1_D1CH1
HDRXN0_D1CH1
C87
x1_PERn0
J4
Place caps near FPGA
SMA
PRSNT1#
2
1
PRSNT3#
4
6
3
5
REFCLKP_D0
REFCLKN_D0
HDTXP0_D1CH1
HDTXN0_D1CH1
HDTXP0_D1CH0
HDTXN0_D1CH0
{6}
{5}
HDRXP0_D1CH0
HDRXN0_D1CH0
{5}
HDRXP0_D1CH1
HDRXN0_D1CH1
{6}
{6}
SERDES
12_0VIN
{5}
{6}
PHY 1 & 2
SGMII
ECP5-45
only
3_3V
CN1
PRSNT1#
W20
REFCLKN_D1
REFCLKP_D1
REFCLKN_D1
{9}
{9}
R72
REFCLKN_D1
LFE5UM-45F-BG381 Schematic
symbols rev 4.1
A1
A2
A6
A7
A8
PCIE_3V3
10NF-0402SMT
C113
R178
PCIE_PERSTN
A9
C93
A11
A12
OPEN-0603SMT
{9}
PCIE_CLKP
{9}
PCIE_CLKN
PCIE_CLKP
A13
PCIE_CLKN
A14
A15
x1_PERp0
x1_PERn0
A16
A17
A18
PRSNT1#
+12V
+12V
GND
JTAG2
JTAG3
JTAG4
JTAG5
+3.3V
+3.3V
PERST
# GND
REFCL
K+
REFCL
K-GND
PERp0
PERn0
GND
B1
B2
+12V
+12V
RSVD_B3
GND
B3
B4
B5
SMCLK
C
B6
B7
SMDAT
GND
B8
+3.3V
JTAG1
3.3Vaux
WAKE#
PCIE_3V3
1
TP6
B9
Testpoint
B10
B11
B12
RSVD_B12
B13
GND
PETp0
PETn0
GND
PRSNT3#
B14
x1_PETp0
B15
x1_PETn0
B16
B17
PRSNT3#
B18
GND
PCI Express x1 Edge Finger Conn.
VCCA1
C112
X1 PCIe Board Fingers
1NF-0402SMT
B side = Primary Component Side(TOP)
A side = Secondary Component Side(BOTTOM)
B
All Nets are 85-ohm differential pairs.
The P and N traces shall be
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