LFEC20E-4F484C

LatticeECP/EC Family Data Sheet DS1000 Version 02.7, February 2008 LatticeECP/EC Family Data Sheet Introduction May 2005 Data Sheet Features ■ Extensive Density and Package Options • 1.5K to 32.8K LUT4s • 65 to 496 I/Os • Density migration supported ■ sysDSP™ Block (LatticeECP™ Versions) • High performance multiply and accumulate • 4 to 8 blocks − 4 to 8 36x36 multipliers or – 16 to 32 18x18 multipliers or − 32 to 64 9x9 multipliers ■ Dedicated DDR Memory Support • Implements interface up to DDR400 (200MHz) − − − − − − LVCMOS 3.3/2.5/1.8/1.5/1.2 LVTTL SSTL 3/2 Class I, II, SSTL18 Class I HSTL 18 Class I, II, III, HSTL15 Class I, III PCI LVDS, Bus-LVDS, LVPECL, RSDS ■ sysCLOCK™ PLLs • Up to four analog PLLs per device • Clock multiply, divide and phase shifting ■ Embedded and Distributed Memory • 18 Kbits to 498 Kbits sysMEM™ Embedded Block RAM (EBR) • Up to 131 Kbits distributed RAM • Flexible memory resources: − Distributed and block memory ■ System Level Support • IEEE Standard 1149.1 Boundary Scan, plus ispTRACY™ internal logic analyzer capability • SPI boot flash interface • 1.2V power supply ■ Low Cost FPGA • Features optimized for mainstream applications • Low cost TQFP and PQFP packaging ■ Flexible I/O Buffer • Programmable sysI/O™ buffer supports wide range of interfaces: Table 1-1. LatticeECP/EC Family Selection Guide Device PFU/PFF Rows PFU/PFF Columns PFUs/PFFs LUTs (K) Distributed RAM (Kbits) EBR SRAM (Kbits) EBR SRAM Blocks sysDSP Blocks 1 LFEC1 12 16 192 1.5 6 18 2 — — 1.2 2 67 97 112 LFEC3 16 24 384 3.1 12 55 6 — — 1.2 2 67 97 145 160 LFEC6/ LFECP6 24 32 768 6.1 25 92 10 4 16 1.2 2 LFEC10/ LFECP10 32 40 1280 10.2 41 276 30 5 20 1.2 4 LFEC15/ LFECP15 40 48 1920 15.4 61 350 38 6 24 1.2 4 LFEC20/ LFECP20 44 56 2464 19.7 79 424 46 7 28 1.2 4 LFEC33/ LFECP33 64 64 4096 32.8 131 498 54 8 32 1.2 4 18x18 Multipliers1 VCC Voltage (V) Number of PLLs Packages and I/O Combinations: 100-pin TQFP (14 x 14 mm) 144-pin TQFP (20 x 20 mm) 208-pin PQFP (28 x 28 mm) 256-ball fpBGA (17 x 17 mm) 484-ball fpBGA (23 x 23 mm) 672-ball fpBGA (27 x 27 mm) 1. LatticeECP devices only. 97 147 195 224 147 195 288 195 352 360 400 360 496 © 2005 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1-1 Introduction_01.3 Lattice Semiconductor Introduction LatticeECP/EC Family Data Sheet Introduction The LatticeECP/EC family of FPGA devices is optimized to deliver mainstream FPGA features at low cost. For maximum performance and value, the LatticeECP™ (EConomy Plus) FPGA concept combines an efficient FPGA fabric with high-speed dedicated functions. Lattice’s first family to implement this approach is the LatticeECPDSP™ (EConomy Plus DSP) family, providing dedicated high-performance DSP blocks on-chip. The LatticeEC™ (EConomy) family supports all the general purpose features of LatticeECP devices without dedicated function blocks to achieve lower cost solutions. The LatticeECP/EC FPGA fabric, which was designed from the outset with low cost in mind, contains all the critical FPGA elements: LUT-based logic, distributed and embedded memory, PLLs and support for mainstream I/Os. Dedicated DDR memory interface logic is also included to support this memory that is becoming increasingly prevalent in cost-sensitive applications. The ispLEVER® design tool suite from Lattice allows large complex designs to be efficiently implemented using the LatticeECP/EC FPGA family. Synthesis library support for LatticeECP/EC is available for popular logic synthesis tools. The ispLEVER tool uses the synthesis tool output along with the constraints from its floor planning tools to place and route the design in the LatticeECP/EC device. The ispLEVER tool extracts the timing from the routing and back-annotates it into the design for timing verification. Lattice provides many pre-designed IP (Intellectual Property) ispLeverCORE™ modules for the LatticeECP/EC family. By using these IPs as standardized blocks, designers are free to concentrate on the unique aspects of their design, increasing their productivity. 1-2 LatticeECP/EC Family Data Sheet Architecture May 2007 Data Sheet Architecture Overview The LatticeECP-DSP and LatticeEC architectures contain an array of logic blocks surrounded by Programmable I/ O Cells (PIC). Interspersed between the rows of logic blocks are rows of sysMEM Embedded Block RAM (EBR), as shown in Figures 2-1 and 2-2. In addition, LatticeECP-DSP supports an additional row of DSP blocks, as shown in Figure 2-2. There are two kinds of logic blocks, the Programmable Functional Unit (PFU) and Programmable Functional unit without RAM/ROM (PFF). The PFU contains the building blocks for logic, arithmetic, RAM, ROM and register functions. The PFF block contains building blocks for logic, arithmetic and ROM functions. Both PFU and PFF blocks are optimized for flexibility, allowing complex designs to be implemented quickly and efficiently. Logic Blocks are arranged in a two-dimensional array. Only one type of block is used per row. The PFU blocks are used on the outside rows. The rest of the core consists of rows of PFF blocks interspersed with rows of PFU blocks. For every three rows of PFF blocks there is a row of PFU blocks. Each PIC block encompasses two PIOs (PIO pairs) with their respective sysI/O interfaces. PIO pairs on the left and right edges of the device can be configured as LVDS transmit/receive pairs. sysMEM EBRs are large dedicated fast memory blocks. They can be configured as RAM or ROM. The PFU, PFF, PIC and EBR Blocks are arranged in a two-dimensional grid with rows and columns as shown in Figure 2-1. The blocks are connected with many vertical and horizontal routing channel resources. The place and route software tool automatically allocates these routing resources. At the end of the rows containing the sysMEM Blocks are the sysCLOCK Phase Locked Loop (PLL) Blocks. These PLLs have multiply, divide and phase shifting capability; they are used to manage the phase relationship of the clocks. The LatticeECP/EC architecture provides up to four PLLs per device. Every device in the family has a JTAG Port with internal Logic Analyzer (ispTRACY) capability. The sysCONFIG™ port which allows for serial or parallel device configuration. The LatticeECP/EC devices use 1.2V as their core voltage. © 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 2-1 Architecture_01.9 Lattice Semiconductor Architecture LatticeECP/EC Family Data Sheet Figure 2-1. Simplified Block Diagram, LatticeEC Device (Top Level) Programmable I/O Cell (PIC) includes sysIO Interface sysMEM Embedded Block RAM (EBR) JTAG Port sysCONFIG Programming Port (includes dedicated and dual use pins) PFF (PFU without RAM) sysCLOCK PLL Programmable Functional Unit (PFU) Figure 2-2. Simplified Block Diagram, LatticeECP-DSP Device (Top Level) Programmable I/O Cell (PIC) includes sysIO Interface sysMEM Embedded Block RAM (EBR) JTAG Port sysCONFIG Programming Port (includes dedicated and dual use pins) PFF (Fast PFU without RAM/ROM) sysDSP Block sysCLOCK PLL Programmable Functional Unit (PFU) 2-2 Lattice Semiconductor Architecture LatticeECP/EC Family Data Sheet PFU and PFF Blocks The core of the LatticeECP/EC devices consists of PFU and PFF blocks. The PFUs can be programmed to perform Logic, Arithmetic, Distributed RAM and Distributed ROM functions. PFF blocks can be programmed to perform Logic, Arithmetic and ROM functions. Except where necessary, the remainder of the data sheet will use the term PFU to refer to both PFU and PFF blocks. Each PFU block consists of four interconnected slices, numbered 0-3 as shown in Figure 2-3. All the interconnections to and from PFU blocks are from routing. There are 53 inputs and 25 outputs associated with each PFU block. Figure 2-3. PFU Diagram From Routing LUT4 & CARRY LUT4 & CARRY LUT4 & CARRY LUT4 & CARRY LUT4 & CARRY LUT4 & CARRY LUT4 & CARRY LUT4 & CARRY Slice 0 Slice 1 Slice 2 Slice 3 D FF/ Latch D FF/ Latch D FF/ Latch D FF/ Latch D FF/ Latch D FF/ Latch D FF/ Latch D FF/ Latch To Routing Slice Each slice contains two LUT4 lookup tables feeding two registers (programmed to be in FF or Latch mode), and some associated logic that allows the LUTs to be combined to perform functions such as LUT5, LUT6, LUT7 and LUT8. There is control logic to perform set/reset functions (programmable as synchronous/asynchronous), clock select, chip-select and wider RAM/ROM functions. Figure 2-4 shows an overview of the internal logic of the slice. The registers in the slice can be configured for positive/negative and edge/level clocks. There are 14 input signals: 13 signals from routing and one from the carry-chain (from adjacent slice or PFU). There are 7 outputs: 6 to routing and one to carry-chain (to adjacent PFU). Table 2-1 lists the signals associated with each slice. 2-3 Lattice Semiconductor Figure 2-4. Slice Diagram To / From Different slice / PFU Architecture LatticeECP/EC Family Data Sheet Slice OFX1 A1 B1 C1 D1 CO F1 F SUM D LUT4 & CARRY CI Q1 FF/ Latch To Routing From Routing M1 M0 LUT Expansion Mux OFX0 A0 B0 CO C0 D0 LUT4 & CARRY CI F SUM OFX0 D F0 Q0 FF/ Latch Control Signals CE selected and CLK inverted per LSR slice in routing Interslice signals are not shown To / From Different slice / PFU Table 2-1. Slice Signal Descriptions Function Input Input Input Input Input Input Input Input Output Output Output Output Output Type Data signal Data signal Multi-purpose Multi-purpose Control signal Control signal Control signal Inter-PFU signal Data signals Data signals Data signals Data signals Inter-PFU signal Signal Names A0, B0, C0, D0 Inputs to LUT4 A1, B1, C1, D1 Inputs to LUT4 M0 M1 CE LSR CLK FCIN F0, F1 Q0, Q1 OFX0 OFX1 FCO Multipurpose Input Multipurpose Input Clock Enable Local Set/Reset System Clock Fast Carry In1 LUT4 output register bypass signals Register Outputs Output of a LUT5 MUX Output of a LUT6, LUT7, LUT82 MUX depending on the slice For the right most PFU the fast carry chain output1 Description 1. See Figure 2-3 for connection details. 2. Requires two PFUs. 2-4 Lattice Semiconductor Architecture LatticeECP/EC Family Data Sheet Modes of Operation Each Slice is capable of four modes of operation: Logic, Ripple, RAM and ROM. The Slice in the PFF is capable of all modes except RAM. Table 2-2 lists the modes and the capability of the Slice blocks. Table 2-2. Slice Modes Logic PFU Slice PFF Slice LUT 4x2 or LUT 5x1 LUT 4x2 or LUT 5x1 Ripple 2-bit Arithmetic Unit 2-bit Arithmetic Unit RAM SPR16x2 N/A ROM ROM16x1 x 2 ROM16x1 x 2 Logic Mode: In this mode, the LUTs in each Slice are configured as 4-input combinatorial lookup tables. A LUT4 can have 16 possible input combinations. Any logic function with four inputs can be generated by programming this lookup table. Since there are two LUT4s per Slice, a LUT5 can be constructed within one Slice. Larger lookup tables such as LUT6, LUT7 and LUT8 can be constructed by concatenating other Slices. Ripple Mode: Ripple mode allows the efficient implementation of small arithmetic functions. In ripple mode, the following functions can be implemented by each Slice: • • • • • • • Addition 2-bit Subtraction 2-bit Add/Subtract 2-bit using dynamic control Up counter 2-bit Down counter 2-bit Ripple mode multiplier building block Comparator functions of A and B inputs - A greater-than-or-equal-to B - A not-equal-to B - A less-than-or-equal-to B Ripple Mode includes an optional configuration that performs arithmetic using fast carry chain methods. In this configuration (also referred to as CCU2 mode) two additional signals, Carry Generate and Carry Propagate, are generated on a per slice basis to allow fast arithmetic functions to be constructed by concatenating Slices. RAM Mode: In this mode, distributed RAM can be constructed using each LUT block as a 16x1-bit memory. Through the combination of LUTs and Slices, a variety of different memories can be constructed. The Lattice design tools support the creation of a variety of different size memories. Where appropriate, the software will construct these using distributed memory primitives that represent the capabilities of the PFU. Table 2-3 shows the number of Slices required to implement different distributed RAM primitives. Figure 2-5 shows the distributed memory primitive block diagrams. Dual port memories involve the pairing of two Slices, one Slice functions as the read-write port. The other companion Slice supports the read-only port. For more information about using RAM in LatticeECP/EC devices, please see the list of technical documentation at the end of this data sheet. Table 2-3. Number of Slices Required For Implementing Distributed RAM SPR16x2 Number of slices 1 DPR16x2 2 Note: SPR = Single Port RAM, DPR = Dual Port RAM 2-5 Lattice Semiconductor Figure 2-5. Distributed Memory Primitives SPR16x2 AD0 AD1 AD2 AD3 DI0 DI1 WRE CK Architecture LatticeECP/EC Family Data Sheet DPR16x2 RAD0 RAD1 RAD2 RAD3 DO0 DO1 WAD0 WAD1 WAD2 WAD3 DI0 DI1 WCK WRE RDO0 RDO1 WDO0 WDO1 ROM16x1 AD0 AD1 AD2 AD3 DO0 ROM Mode: The ROM mode uses the same principal as the RAM modes, but without the Write port. Pre-loading is accomplished through the programming interface during configuration. PFU Modes of Operation Slices can be combined within a PFU to form larger functions. Table 2-4 tabulates these modes and documents the functionality possible at the PFU level. Table 2-4. PFU Modes of Operation Logic LUT 4x8 or MUX 2x1 x 8 LUT 5x4 or MUX 4x1 x 4 LUT 6x 2 or MUX 8x1 x 2 LUT 7x1 or MUX 16x1 x 1 Ripple 2-bit Add x 4 2-bit Sub x 4 2-bit Counter x 4 2-bit Comp x 4 RAM1 SPR16x2 x 4 DPR16x2 x 2 SPR16x4 x 2 DPR16x4 x 1 SPR16x8 x 1 ROM ROM16x1 x 8 ROM16x2 x 4 ROM16x4 x 2 ROM16x8 x 1 1. These modes are not available in PFF blocks 2-6 Lattice Semiconductor Architecture LatticeECP/EC Family Data Sheet Routing There are many resources provided in the LatticeECP/EC devices to route signals individually or as busses with related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) segments. The inter-PFU connections are made with x1 (spans two PFU), x2 (spans three PFU) and x6 (spans seven PFU). The x1 and x2 connections provide fast and efficient connections in horizontal and vertical directions. The x2 and x6 resources are buffered, the routing of both short and long connections between PFUs. The ispLEVER design tool suite takes the output of the synthesis tool and places and routes the design. Generally, the place and route tool is completely automatic, although an interactive routing editor is available to optimize the design. Clock Distribution Network The clock inputs are selected from external I/O, the sysCLOCK™ PLLs or routing. These clock inputs are fed through the chip via a clock distribution system. Primary Clock Sources LatticeECP/EC devices derive clocks from three primary sources: PLL outputs, dedicated clock inputs and routing. LatticeECP/EC devices have two to four sysCLOCK PLLs, located on the left and right sides of the device. There are four dedicated clock inputs, one on each side of the device. Figure 2-6 shows the 20 primary clock sources. Figure 2-6. Primary Clock Sources From Routing Clock Input From Routing PLL Input PLL PLL PLL Input Clock Input 20 Primary Clock Sources To Quadrant Clock Selection Clock Input PLL Input PLL PLL PLL Input From Routing Clock Input From Routing Note: Smaller devices have two PLLs. 2-7 Lattice Semiconductor Secondary Clock Sources Architecture LatticeECP/EC Family Data Sheet LatticeECP/EC devices have four secondary clock resources per quadrant. The secondary clock branches are tapped at every PFU. These secondary clock networks can also be used for controls and high fanout data. These secondary clocks are derived from four clock input pads and 16 routing signals as shown in Figure 2-7. Figure 2-7. Secondary Clock Sources From Routing From Routing From Routing From Routing From Routing From Routing From Routing From Routing 20 Secondary Clock Sources To Quadrant Clock Selection From Routing From Routing From Routing From Routing From Routing From Routing From Routing From Routing Clock Routing The clock routing structure in LatticeECP/EC devices consists of four Primary Clock lines and a Secondary Clock network per quadrant. The primary clocks are generated from MUXs located in each quadrant. Figure 2-8 shows this clock routing. The four secondary clocks are generated from MUXs located in each quadrant as shown in Figure 2-9. Each slice derives its clock from the primary clock lines, secondary clock lines and routing as shown in Figure 2-10. 2-8 Lattice Semiconductor Figure 2-8. Per Quadrant Primary Clock Selection Architecture LatticeECP/EC Family Data Sheet 20 Primary Clock Sources: 12 PLLs + 4 PIOs + 4 Routing1 DCS DCS 4 Primary Clocks (CLK0, CLK1, CLK2, CLK3) per Quadrant 1. Smaller devices have fewer PLL related lines. Figure 2-9. Per Quadrant Secondary Clock Selection 20 Secondary Clock Feedlines : 4 Clock Input Pads + 16 Routing Signals 4 Secondary Clocks per Quadrant Figure 2-10. Slice Clock Selection Primary Clock Secondary Clock Routing GND Clock to each slice sysCLOCK Phase Locked Loops (PLLs) The PLL clock input, from pin or routing, feeds into an input clock divider. There are three sources of feedback signal to the feedback divider: from CLKOP (PLL Internal), from clock net (CLKOP) or from a user clock (PIN or logic). There is a PLL_LOCK signal to indicate that VCO has locked on to the input clock signal. Figure 2-11 shows the sysCLOCK PLL diagram. The setup and hold times of the device can be improved by programming a delay in the feedback or input path of the PLL which will advance or delay the output clock with reference to the input clock. This delay can be either pro- 2-9 Lattice Semiconductor Architecture LatticeECP/EC Family Data Sheet grammed during configuration or can be adjusted dynamically. In dynamic mode, the PLL may lose lock after adjustment and not relock until the tLOCK parameter has been satisfied. Additionally, the phase and duty cycle block allows the user to adjust the phase and duty cycle of the CLKOS output. The sysCLOCK PLLs provide the ability to synthesize clock frequencies. Each PLL has four dividers associated with it: input clock divider, feedback divider, post scalar divider and secondary clock divider. The input clock divider is used to divide the input clock signal, while the feedback divider is used to multiply the input clock signal. The post scalar divider allows the VCO to operate at higher frequencies than the clock output, thereby increasing the frequency range. The secondary divider is used to derive lower frequency outputs. Figure 2-11. PLL Diagram Dynamic Delay Adjustment LOCK CLKI (from routing or external pin) Input Clock Divider (CLKI) Delay Adjust Voltage Controlled VCO Oscillator Post Scalar Divider (CLKOP) Phase/Duty Select CLKOS RST Feedback Divider (CLKFB) Secondary Clock Divider (CLKOK) CLKOP CLKFB from CLKOP (PLL internal), from clock net (CLKOP) or from a user clock (PIN or logic) CLKOK Figure 2-12 shows the available macros for the PLL. Table 2-5 provides signal description of the PLL Block. Figure 2-12. PLL Primitive RST CLKI CLKFB CLKOP CLKOS CLKOK EPLLB CLKOP LOCK CLKI CLKFB DDA MODE DDAIZR DDAILAG DDAIDEL[2:0] EHXPLLB LOCK DDAOZR DDAOLAG DDAODEL[2:0] 2-10 Lattice Semiconductor Table 2-5. PLL Signal Descriptions Signal CLKI CLKFB RST CLKOS CLKOP CLKOK LOCK DDAMODE DDAIZR DDAILAG DDAIDEL[2:0] DDAOZR DDAOLAG DDAODEL[2:0] I/O I I I O O O O I I I I O O O Clock input from external pin or routing Architecture LatticeECP/EC Family Data Sheet Description PLL feedback input from CLKOP (PLL internal), from clock net (CLKOP) or from a user clock (PIN or logic) “1” to reset PLL PLL output clock to clock tree (phase shifted/duty cycle changed) PLL output clock to clock tree (No phase shift) PLL output to clock tree through secondary clock divider “1” indicates PLL LOCK to CLKI Dynamic Delay Enable. “1”: Pin control (dynamic), “0”: Fuse Control (static) Dynamic Delay Zero. “1”: delay = 0, “0”: delay = on Dynamic Delay Lag/Lead. “1”: Lead, “0”: Lag Dynamic Delay Input Dynamic Delay Zero Output Dynamic Delay Lag/Lead Output Dynamic Delay Output For more information about the PLL, please see the list of technical documentation at the end of this data sheet. Dynamic Clock Select (DCS) The DCS is a global clock buffer with smart multiplexer functions. It takes two independent input clock sources and outputs a clock signal without any glitches or runt pulses. This is achieved regardless of where the select signal is toggled. There are eight DCS blocks per device, located in pairs at the center of each side. Figure 2-13 illustrates the DCS Block Macro. Figure 2-13. DCS Block Primitive CLK0 CLK1 SEL DCS DCSOUT Figure 2-14 shows timing waveforms of the default DCS operating mode. The DCS block can be programmed to other modes. For more information about the DCS, please see the list of technical documentation at the end of this data sheet. 2-11 Lattice Semiconductor Figure 2-14. DCS Waveforms CLK0 Architecture LatticeECP/EC Family Data Sheet CLK1 SEL DCSOUT sysMEM Memory The LatticeECP/EC devices contain a number of sysMEM Embedded Block RAM (EBR). The EBR consists of a 9Kbit RAM, with dedicated input and output registers. sysMEM Memory Block The sysMEM block can implement single port, dual port or pseudo dual port memories. Each block can be used in a variety of depths and widths as shown in Table 2-6. Table 2-6. sysMEM Block Configurations Memory Mode Configurations 8,192 x 1 4,096 x 2 2,048 x 4 1,024 x 9 512 x 18 256 x 36 8,192 x 1 4,096 x 2 2,048 x 4 1,024 x 9 512 x 18 8,192 x 1 4,096 x 2 2,048 x 4 1,024 x 9 512 x 18 256 x 36 Single Port True Dual Port Pseudo Dual Port Bus Size Matching All of the multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB word 0 to MSB word 0, LSB word 1 to MSB word 1 and so on. Although the word size and number of words for each port varies, this mapping scheme applies to each port. RAM Initialization and ROM Operation If desired, the contents of the RAM can be pre-loaded during device configuration. By preloading the RAM block during the chip configuration cycle and disabling the write controls, the sysMEM block can also be utilized as a ROM. 2-12 Lattice Semiconductor Memory Cascading Architecture LatticeECP/EC Family Data Sheet Larger and deeper blocks of RAM can be created using EBR sysMEM Blocks. Typically, the Lattice design tools cascade memory transparently, based on specific design inputs. Single, Dual and Pseudo-Dual Port Modes Figure 2-15 shows the four basic memory configurations and their input/output names. In all the sysMEM RAM modes the input data and address for the ports are registered at the input of the memory array. The output data of the memory is optionally registered at the output. Figure 2-15. sysMEM EBR Primitives ADA[12:0] DIA[17:0] CLKA CEA DO[35:0] RSTA WEA CSA[2:0] DOA[17:0] ADB[12:0] DIB[17:0] CEB CLKB RSTB WEB CSB[2:0] DOB[17:0] AD[12:0] DI[35:0] CLK CE RST WE CS[2:0] EBR EBR Single Port RAM True Dual Port RAM AD[12:0] CLK CE RST CS[2:0] EBR ADW[12:0] DI[35:0] CLKW CEW DO[35:0] WE RST CS[2:0] ADR[12:0] EBR DO[35:0] CER CLKR ROM Pseudo-Dual Port RAM The EBR memory supports three forms of write behavior for single port or dual port operation: 1. Normal – data on the output appears only during read cycle. During a write cycle, the data (at the current address) does not appear on the output. This mode is supported for all data widths. 2. Write Through – a copy of the input data appears at the output of the same port during a write cycle. This mode is supported for all data widths. 3. Read-Before-Write – when new data is being written, the old content of the address appears at the output. This mode is supported for x9, x18 and x36 data widths. Memory Core Reset The memory array in the EBR utilizes latches at the A and B output ports. These latches can be reset asynchronously or synchronously. RSTA and RSTB are local signals, which reset the output latches associated with Port A and Port B, respectively. The Global Reset (GSRN) signal resets both ports. The output data latches and associated resets for both ports are as shown in Figure 2-16. 2-13 Lattice Semiconductor Figure 2-16. Memory Core Reset Memory Core D SET Architecture LatticeECP/EC Family Data Sheet Q Port A[17:0] LCLR Output Data Latches D SET Q Port B[17:0] LCLR RSTA RSTB GSRN Programmable Disable For further information about sysMEM EBR block, please see the the list of technical documentation at the end of this data sheet. EBR Asynchronous Reset EBR asynchronous reset or GSR (if used) can only be applied if all clock enables are low for a clock cycle before the reset is applied and released a clock cycle after the reset is released, as shown in Figure 2-17. The GSR input to the EBR is always asynchronous. Figure 2-17. EBR Asynchronous Reset (Including GSR) Timing Diagram Reset Clock Clock Enable If all clock enables remain enabled, the EBR asynchronous reset or GSR may only be applied and released after the EBR read and write clock inputs are in a steady state condition for a minimum of 1/fMAX (EBR clock). The reset release must adhere to the EBR synchronous reset setup time before the next active read or write clock edge. If an EBR is pre-loaded during configuration, the GSR input must be disabled or the release of the GSR during device Wake Up must occur before the release of the device I/Os becomes active. These instructions apply to all EBR RAM and ROM implementations. Note that there are no reset restrictions if the EBR synchronous reset is used and the EBR GSR input is disabled. sysDSP Block The LatticeECP-DSP family provides a sysDSP block, making it ideally suited for low cost, high performance Digital Signal Processing (DSP) applications. Typical functions used in these applications are Finite Impulse Response (FIR) filters; Fast Fourier Transforms (FFT) functions, correlators, Reed-Solomon/Turbo/Convolution encoders and 2-14 Lattice Semiconductor Architecture LatticeECP/EC Family Data Sheet decoders. These complex signal processing functions use similar building blocks such as multiply-adders and multiply-accumulators. sysDSP Block Approach Compared to General DSP Conventional general-purpose DSP chips typically contain one to four (Multiply and Accumulate) MAC units with fixed data-width multipliers; this leads to limited parallelism and limited throughput. Their throughput is increased by higher clock speeds. The LatticeECP, on the other hand, has many DSP blocks that support different data-widths. This allows the designer to use highly parallel implementations of DSP functions. The designer can optimize the DSP performance vs. area by choosing an appropriate level of parallelism. Figure 2-18 compares the serial and the parallel implementations. Figure 2-18. Comparison of General DSP and LatticeECP-DSP Approaches Operand A Operand A Operand B Operand A Operand B Operand B Operand A Operand B x Single Multiplier Multiplier 0 Multiplier 1 x x Multiplier (k-1) x Σ M loops m/k loops Accumulator Accumulator Function implemented in General purpose DSP Σ Output Function implemented in LatticeECP sysDSP Block Capabilities The sysDSP block in the LatticeECP-DSP family supports four functional elements in three 9, 18 and 36 data path widths. The user selects a function element for a DSP block and then selects the width and type (signed/unsigned) of its operands. The operands in the LatticeECP-DSP family sysDSP Blocks can be either signed or unsigned but not mixed within a function element. Similarly, the operand widths cannot be mixed within a block. The resources in each sysDSP block can be configured to support the following four elements: • • • • MULT MAC MULTADD MULTADDSUM (Multiply) (Multiply, Accumulate) (Multiply, Addition/Subtraction) (Multiply, Addition/Subtraction, Accumulate) The number of elements available in each block depends on the width selected from the three available options x9, x18, and x36. A number of these elements are concatenated for highly parallel implementations of DSP functions. Table 2-1 shows the capabilities of the block. 2-15 Lattice Semiconductor Table 2-7. Maximum Number of Elements in a Block Width of Multiply MULT MAC MULTADD MULTADDSUM x9 8 2 4 2 x18 4 2 2 1 Architecture LatticeECP/EC Family Data Sheet x36 1 — — — Some options are available in four elements. The input register in all the elements can be directly loaded or can be loaded as shift registers from previous operand registers. In addition by selecting “dynamic operation” in the ‘Signed/Unsigned’ options the operands can be switched between signed and unsigned on every cycle. Similarly by selecting ‘Dynamic operation’ in the ‘Add/Sub’ option the Accumulator can be switched between addition and subtraction on every cycle. MULT sysDSP Element This multiplier element implements a multiply with no addition or accumulator nodes. The two operands, A and B, are multiplied and the result is available at the output. The user can enable the input/output and pipeline registers. Figure 2-19 shows the MULT sysDSP element. Figure 2-19. MULT sysDSP Element Shift Register B In Multiplicand m Shift Register A In m m Multiplier n n n Output Register Input Data Register A m Multiplier Input Data Register B m n n x Pipeline Register m+n (default) m+n Output Signed Input Register To Multiplier CLK (CLK0,CLK1,CLK2,CLK3) CE (CE0,CE1,CE2,CE3) RST(RST0,RST1,RST2,RST3) Shift Register B Out Shift Register A Out MAC sysDSP Element In this case the two operands, A and B, are multiplied and the result is added with the previous accumulated value. This accumulated value is available at the output. The user can enable the input and pipeline registers but the output register is always enabled. The output register is used to store the accumulated value. A registered overflow signal is also available. The overflow conditions are provided later in this document. Figure 2-20 shows the MAC sysDSP element. 2-16 Lattice Semiconductor Figure 2-20. MAC sysDSP Element Shift Register B In Multiplicand m m Input Data Register A m Multiplier Architecture LatticeECP/EC Family Data Sheet Shift Register A In m Accumulator n Input Data Register B n n x Output Register Multiplier n n m+n+16 bits (default) m+n (default) m+n+16 bits (default) Output n SignedAB Addn Accumsload Input Register Input Register Input Register Pipeline Register Pipeline Register Pipeline Register Overflow Register Pipeline Register To Accumulator To Accumulator To Accumulator Overflow signal CLK (CLK0,CLK1,CLK2,CLK3) CE (CE0,CE1,CE2,CE3) RST(RST0,RST1,RST2,RST3) Shift Register B Out Shift Register A Out MULTADD sysDSP Element In this case, the operands A0 and B0 are multiplied and the result is added/subtracted with the result of the multiplier operation of operands A1 and A2. The user can enable the input, output and pipeline registers. Figure 2-21 shows the MULTADD sysDSP element. Figure 2-21. MULTADD Shift Register B In Multiplicand A0 n n Input Data Register B n m m Input Data Register A m Multiplier Shift Register A In m CLK (CLK0,CLK1,CLK2,CLK3) CE (CE0,CE1,CE2,CE3) Multiplier B0 RST(RST0,RST1,RST2,RST3) n n m m m x Pipeline Register m+n (default) Add/Sub Multiplicand A1 Output Register Output m+n+1 (default) Multiplier B1 n n m+n+1 (default) m Multiplier m+n (default) Input Data Register A Input Data Register B n m Pipeline Pipe Register Reg Pipeline Pipe Register Reg x Pipeline Register Signed Addn n Input Register Input Register To Add/Sub To Add/Sub Shift Register B Out Shift Register A Out 2-17 Lattice Semiconductor MULTADDSUM sysDSP Element Architecture LatticeECP/EC Family Data Sheet In this case, the operands A0 and B0 are multiplied and the result is added/subtracted with the result of the multiplier operation of operands A1 and B1. Additionally the operands A2 and B2 are multiplied and the result is added/ subtracted with the result of the multiplier operation of operands A3 and B3. The result of both addition/subtraction are added in a summation block. The user can enable the input, output and pipeline registers. Figure 2-22 shows the MULTADDSUM sysDSP element. Figure 2-22. MULTADDSUM Shift Register B In Multiplicand A0 Multiplier B0 n n Input Data Register B n m m Input Data Register A m Multiplier Shift Register A In m CLK (CLK0,CLK1,CLK2,CLK3) CE (CE0,CE1,CE2,CE3) n m m m Input Data Register A n x Pipeline Register m+n (default) RST(RST0,RST1,RST2,RST3) Add/Sub0 Multiplicand A1 Multiplier B1 n m+n (default) Multiplier n n Input Data Register B n x Pipeline Register m+n+1 SUM Output Register Multiplicand A2 Multiplier B2 n n Input Data Register B m m m m+n+2 Output m+n+2 n Input Data Register A m Multiplier n m m m Input Data Register A m x Pipeline Register m+n (default) m+n+1 Add/Sub1 Multiplicand A3 Multiplier B3 n m+n (default) Multiplier n n Input Data Register B n m Input Register Input Register Input Register Pipeline Register Pipeline Register Pipeline Register x Pipeline Register Signed Addn0 Addn1 n To Add/Sub0, Add/Sub1 To Add/Sub0 To Add/Sub1 Shift Register B Out Shift Register A Out Clock, Clock Enable and Reset Resources Global Clock, Clock Enable and Reset signals from routing are available to every DSP block. Four Clock, Reset and Clock Enable signals are selected for the sysDSP block. From four clock sources (CLK0, CLK1, CLK2, CLK3) one clock is selected for each input register, pipeline register and output register. Similarly Clock enable (CE) and Reset (RST) are selected from their four respective sources (CE0, CE1, CE2, CE3 and RST0, RST1, RST2, RST3) at each input register, pipeline register and output register. 2-18 Lattice Semiconductor Signed and Unsigned with Different Widths Architecture LatticeECP/EC Family Data Sheet The DSP block supports different widths of signed and unsigned multipliers besides x9, x18 and x36 widths. For unsigned operands, unused upper data bits should be filled to create a valid x9, x18 or x36 operand. For signed two’s complement operands, sign extension of the most significant bit should be performed until x9, x18 or x36 width is reached. Table 2-8 provides an example of this. Table 2-8. An Example of Sign Extension Number Unsigned +5 -6 0101 0110 Unsigned 9-bit 000000101 000000110 Unsigned 18-bit 000000000000000101 000000000000000110 Signed 0101 1010 Two’s Complement Signed 9-Bits 000000101 111111010 Two’s Complement Signed 18-bits 000000000000000101 111111111111111010 OVERFLOW Flag from MAC The sysDSP block provides an overflow output to indicate that the accumulator has overflowed. When two unsigned numbers are added and the result is a smaller number then accumulator roll over is said to occur and overflow signal is indicated. When two positive numbers are added with a negative sum and when two negative numbers are added with a positive sum, then the accumulator “roll-over” is said to have occurred and an overflow signal is indicated. Note when overflow occurs the overflow flag is present for only one cycle. By counting these overflow pulses in FPGA logic, larger accumulators can be constructed. The conditions overflow signals for signed and unsigned operands are listed in Figure 2-23. Figure 2-23. Accumulator Overflow/Underflow Conditions 0101111100 0101111101 0101111110 0101111111 1010000000 1010000001 1010000010 252 253 254 255 256 257 258 000000011 000000010 000000001 000000000 111111111 111111110 111111101 3 2 1 0 511 510 509 Carry signal is generated for one cycle when this boundary is crossed Unsigned Operation 0101111100 252 Overflow signal is generated 0101111101 253 0101111110 254 for one cycle when this 0101111111 255 boundary is crossed 1010000000 256 1010000001 255 1010000010 254 000000011 000000010 000000001 000000000 111111111 111111110 111111101 +3 +2 +1 0 -1 -2 -3 Signed Operation 2-19 Lattice Semiconductor IPexpress™ Architecture LatticeECP/EC Family Data Sheet The user can access the sysDSP block via the IPexpress configuration tool, included with the ispLEVER design tool suite. IPexpress has options to configure each DSP module (or group of modules) or through direct HDL instantiation. Additionally Lattice has partnered Mathworks to support instantiation in the Simulink tool, which is a Graphical Simulation Environment. Simulink works with ispLEVER and dramatically shortens the DSP design cycle in Lattice FPGAs. Optimized DSP Functions Lattice provides a library of optimized DSP IP functions. Some of the IPs planned for LatticeECP DSP are: Bit Correlators, Fast Fourier Transform, Finite Impulse Response (FIR) Filter, Reed-Solomon Encoder/ Decoder, Turbo Encoder/Decoders and Convolutional Encoder/Decoder. Please contact Lattice to obtain the latest list of available DSP IPs. Resources Available in the LatticeECP Family Table 2-9 shows the maximum number of multipliers for each member of the LatticeECP family. Table 2-10 shows the maximum available EBR RAM Blocks in each of the LatticeECP family. EBR blocks, together with Distributed RAM can be used to store variables locally for the fast DSP operations. Table 2-9. Number of DSP Blocks in LatticeECP Family Device LFECP6 LFECP10 LFECP15 LFECP20 LFECP33 DSP Block 4 5 6 7 8 9x9 Multiplier 32 40 48 56 64 18x18 Multiplier 16 20 24 28 32 36x36 Multiplier 4 5 6 7 8 Table 2-10. Embedded SRAM in LatticeECP Family Device LFECP6 LFECP10 LFECP15 LFECP20 LFECP33 EBR SRAM Block 10 30 38 46 54 Total EBR SRAM (Kbits) 92 276 350 424 498 DSP Performance of the LatticeECP Family Table 2-11 lists the maximum performance in millions of MAC operations per second (MMAC) for each member of the LatticeECP family. Table 2-11. DSP Block Performance of LatticeECP Family Device LFECP6 LFECP10 LFECP15 LFECP20 LFECP33 DSP Block 4 5 6 7 8 DSP Performance MMAC 3680 4600 5520 6440 7360 2-20 Lattice Semiconductor Architecture LatticeECP/EC Family Data Sheet For further information about the sysDSP block, please see the list of technical information at the end of this data sheet. Programmable I/O Cells (PIC) Each PIC contains two PIOs connected to their respective sysI/O Buffers which are then connected to the PADs as shown in Figure 2-24. The PIO Block supplies the output data (DO) and the Tri-state control signal (TO) to sysI/O buffer, and receives input from the buffer. Figure 2-24. PIC Diagram PIO A TD OPOS1 ONEG1 TD D0 D1 DDRCLK IOLT0 Tristate Register Block (2 Flip Flops) OPOS0 ONEG0 D0 D1 DDRCLK PADA "T" IOLD0 Output Register Block (2 Flip Flops) INCK INDD INFF IPOS0 IPOS1 INCK INDD INFF IPOS0 IPOS1 sysIO Buffer DI Control Muxes CLK CE LSR GSRN DQS DDRCLKPOL CLKO CEO LSR GSR CLKI CEI Input Register Block (5 Flip Flops) PADB "C" PIO B Two adjacent PIOs can be joined to provide a differential I/O pair (labeled as “T” and “C”) as shown in Figure 2-25. The PAD Labels “T” and “C” distinguish the two PIOs. Only the PIO pairs on the left and right edges of the device can be configured as LVDS transmit/receive pairs. One of every 16 PIOs contains a delay element to facilitate the generation of DQS signals. The DQS signal feeds the DQS bus which spans the set of 16 PIOs. Figure 2-25 shows the assignment of DQS pins in each set of 16 PIOs. The exact DQS pins are shown in a dual function in the Logic Signal Connections table at the end of this data sheet. Additional detail is provided in the Signal Descriptions table at the end of this data sheet. The DQS signal from the bus is used to strobe the DDR data from the memory into input register blocks. This interface is designed for memories that support one DQS strobe per eight bits of data. 2-21 Lattice Semiconductor Table 2-12. PIO Signal List Name CE0, CE1 CLK0, CLK1 LSR GSRN INCK DQS INDD INFF IPOS0, IPOS1 ONEG0 OPOS0, OPOS1 ONEG1 TD DDRCLKPOL Type Control from the core Control from the core Control from the core Control from routing Input to the core Input to PIO Input to the core Input to the core Input to the core Control from the core Control from the core Tristate control from the core Tristate control from the core Control from clock polarity bus Architecture LatticeECP/EC Family Data Sheet Description Clock enables for input and output block FFs. System clocks for input and output blocks. Local Set/Reset. Global Set/Reset (active low). Input to Primary Clock Network or PLL reference inputs. DQS signal from logic (routing) to PIO. Unregistered data input to core. Registered input on positive edge of the clock (CLK0). DDRX registered inputs to the core. Output signals from the core for SDR and DDR operation. Output signals from the core for DDR operation Signals to Tristate Register block for DDR operation. Tristate signal from the core used in SDR operation. Controls the polarity of the clock (CLK0) that feed the DDR input block. Figure 2-25. DQS Routing PIO A PIO B PIO A PIO B PIO A PIO B PIO A PIO B PIO A PIO B PIO A PIO B PIO A PIO B PIO A PIO B sysIO Buffer Delay PADA "T" LVDS Pair PADB "C" PADA "T" LVDS Pair PADB "C" PADA "T" LVDS Pair PADB "C" PADA "T" LVDS Pair PADB "C" Assigned DQS Pin DQS PADA "T" LVDS Pair PADB "C" PADA "T" LVDS Pair PADB "C" PADA "T" LVDS Pair PADB "C" PADA "T" LVDS Pair PADB "C" PIO The PIO contains four blocks: an input register block, output register block, tristate register block and a control logic block. These blocks contain registers for both single data rate (SDR) and double data rate (DDR) operation along with the necessary clock and selection logic. Programmable delay lines used to shift incoming clock and data signals are also included in these blocks. 2-22 Lattice Semiconductor Architecture LatticeECP/EC Family Data Sheet Input Register Block The input register block contains delay elements and registers that can be used to condition signals before they are passed to the device core. Figure 2-26 shows the diagram of the input register block. Input signals are fed from the sysI/O buffer to the input register block (as signal DI). If desired the input signal can bypass the register and delay elements and be used directly as a combinatorial signal (INDD), a clock (INCK) and in selected blocks the input to the DQS delay block. If one of the bypass options is not chosen, the signal first passes through an optional delay block. This delay, if selected, reduces input-register hold-time requirement when using a global clock. The input block allows two modes of operation. In the single data rate (SDR) the data is registered, by one of the registers in the single data rate sync register block, with the system clock. In the DDR Mode two registers are used to sample the data on the positive and negative edges of the DQS signal creating two data streams, D0 and D2. These two data streams are synchronized with the system clock before entering the core. Further discussion on this topic is in the DDR Memory section of this data sheet. Figure 2-27 shows the input register waveforms for DDR operation and Figure 2-28 shows the design tool primitives. The SDR/SYNC registers have reset and clock enable available. The signal DDRCLKPOL controls the polarity of the clock used in the synchronization registers. It ensures adequate timing when data is transferred from the DQS to system clock domain. For further discussion on this topic, see the DDR Memory section of this data sheet. Figure 2-26. Input Register Diagram DI (From sysIO Buffer) INCK INDD Delay Block Fixed Delay DDR Registers SDR & Sync Registers D0 D Q D-Type Q D D-Type /LATCH D2 To Routing IPOS0 D Q D1 D Q D Q IPOS1 D-Type DQS Delayed (From DQS Bus) D-Type D-Type /LATCH CLK0 (From Routing) DDRCLKPOL (From DDR Polarity Control Bus) 2-23 Lattice Semiconductor Figure 2-27. Input Register DDR Waveforms DI (In DDR Mode) DQS DQS Delayed A B C Architecture LatticeECP/EC Family Data Sheet D E F D0 B D D2 A C Figure 2-28. INDDRXB Primitive D ECLK LSR SCLK CE DDRCLKPOL IDDRXB QB QA Output Register Block The output register block provides the ability to register signals from the core of the device before they are passed to the sysI/O buffers. The block contains a register for SDR operation that is combined with an additional latch for DDR operation. Figure 2-29 shows the diagram of the Output Register Block. In SDR mode, ONEG0 feeds one of the flip-flops that then feeds the output. The flip-flop can be configured a Dtype or latch. In DDR mode, ONEG0 is fed into one register on the positive edge of the clock and OPOS0 is latched. A multiplexer running off the same clock selects the correct register for feeding to the output (D0). Figure 2-30 shows the design tool DDR primitives. The SDR output register has reset and clock enable available. The additional register for DDR operation does not have reset or clock enable available. 2-24 Lattice Semiconductor Figure 2-29. Output Register Block Architecture LatticeECP/EC Family Data Sheet ONEG0 Q D D-Type /LATCH 0 OUTDDN 0 1 DO From Routing 1 OPOS0 D Latch LE* CLK1 Q To sysIO Buffer Programmed Control *Latch is transparent when input is low. Figure 2-30. ODDRXB Primitive DA DB CLK LSR ODDRXB Q Tristate Register Block The tristate register block provides the ability to register tri-state control signals from the core of the device before they are passed to the sysI/O buffers. The block contains a register for SDR operation and an additional latch for DDR operation. Figure 2-31 shows the diagram of the Tristate Register Block. In SDR mode, ONEG1 feeds one of the flip-flops that then feeds the output. The flip-flop can be configured a Dtype or latch. In DDR mode, ONEG1 is fed into one register on the positive edge of the clock and OPOS1 is latched. A multiplexer running off the same clock selects the correct register for feeding to the output (D0). 2-25 Lattice Semiconductor Figure 2-31. Tristate Register Block Architecture LatticeECP/EC Family Data Sheet TD OUTDDN ONEG1 Q D D-Type /LATCH 0 0 1 1 TO From Routing OPOS1 D Latch LE* CLK1 Q To sysIO Buffer Programmed Control *Latch is transparent when input is low. Control Logic Block The control logic block allows the selection and modification of control signals for use in the PIO block. A clock is selected from one of the clock signals provided from the general purpose routing and a DQS signal provided from the programmable DQS pin. The clock can optionally be inverted. The clock enable and local reset signals are selected from the routing and optionally inverted. The global tristate signal is passed through this block. DDR Memory Support Implementing high performance DDR memory interfaces requires dedicated DDR register structures in the input (for read operations) and in the output (for write operations). As indicated in the PIO Logic section, the LatticeEC devices provide this capability. In addition to these registers, the LatticeEC devices contain two elements to simplify the design of input structures for read operations: the DQS delay block and polarity control logic. DLL Calibrated DQS Delay Block Source Synchronous interfaces generally require the input clock to be adjusted in order to correctly capture data at the input register. For most interfaces a PLL is used for this adjustment. However in DDR memories the clock (referred to as DQS) is not free running so this approach cannot be used. The DQS Delay block provides the required clock alignment for DDR memory interfaces. The DQS signal (selected PIOs only) feeds from the PAD through a DQS delay element to a dedicated DQS routing resource. The DQS signal also feeds polarity control logic, which controls the polarity of the clock to the sync registers in the input register blocks. Figures 2-32 and 2-33 show how the DQS transition signals are routed to the PIOs. The temperature, voltage and process variations of the DQS delay block are compensated by a set of calibration (6-bit bus) signals from two DLLs on opposite sides of the device. Each DLL compensates DQS Delays in its half of the device as shown in Figure 2-33. The DLL loop is compensated for temperature, voltage and process variations by the system clock and feedback loop. 2-26 Lattice Semiconductor Figure 2-32. DQS Local Bus. Architecture LatticeECP/EC Family Data Sheet Delay Control Bus Polarity Control Bus DQS Bus DQS GSR CLKI CEI DQS PIO Input Register Block ( 5 Flip Flops) To Sync. Reg. sysIO Buffer DDR Datain PAD DI To DDR Reg. PIO sysIO Buffer DQS Strobe PAD DI Polarity Control Logic DQS DQSDEL Calibration Bus from DLL Figure 2-33. DLL Calibration Bus and DQS/DQS Transition Distribution Delay Control Bus Polarity Control Bus DQS Bus DLL DLL 2-27 Lattice Semiconductor Polarity Control Logic Architecture LatticeECP/EC Family Data Sheet In a typical DDR Memory interface design, the phase relation between the incoming delayed DQS strobe and the internal system Clock (during the READ cycle) is unknown. The LatticeECP/EC family contains dedicated circuits to transfer data between these domains. To prevent setup and hold violations at the domain transfer between DQS (delayed) and the system Clock a clock polarity selector is used. This changes the edge on which the data is registered in the synchronizing registers in the input register block. This requires evaluation at the start of each READ cycle for the correct clock polarity. Prior to the READ operation in DDR memories DQS is in tristate (pulled by termination). The DDR memory device drives DQS low at the start of the preamble state. A dedicated circuit detects this transition. This signal is used to control the polarity of the clock to the synchronizing registers. sysI/O Buffer Each I/O is associated with a flexible buffer referred to as a sysI/O buffer. These buffers are arranged around the periphery of the device in eight groups referred to as Banks. The sysI/O buffers allow users to implement the wide variety of standards that are found in today’s systems including LVCMOS, SSTL, HSTL, LVDS and LVPECL. sysI/O Buffer Banks LatticeECP/EC devices have eight sysI/O buffer banks; each is capable of supporting multiple I/O standards. Each sysI/O bank has its own I/O supply voltage (VCCIO), and two voltage references VREF1 and VREF2 resources allowing each bank to be completely independent from each other. Figure 2-34 shows the eight banks and their associated supplies. In the LatticeECP/EC devices, single-ended output buffers and ratioed input buffers (LVTTL, LVCMOS, PCI and PCIX) are powered using VCCIO. LVTTL, LVCMOS33, LVCMOS25 and LVCMOS12 can also be set as fixed threshold input independent of VCCIO. In addition to the bank VCCIO supplies, the LatticeECP/EC devices have a VCC core logic power supply, and a VCCAUX supply that power all differential and referenced buffers. Each bank can support up to two separate VREF voltages, VREF1 and VREF2 that set the threshold for the referenced input buffers. In the LatticeECP/EC devices, some dedicated I/O pins in a bank can be configured to be a reference voltage supply pin. Each I/O is individually configurable based on the bank’s supply and reference voltages. 2-28 Lattice Semiconductor Figure 2-34. LatticeECP/EC Banks TOP Architecture LatticeECP/EC Family Data Sheet GND VREF2(0) GND VREF2(1) VCCIO0 VCCIO7 Bank 0 VREF1(0) VREF1(1) VCCIO1 Bank 1 VCCIO2 VREF1(2) VREF2(2) GND VCCIO3 RIGHT Bank 7 VREF1(7) VREF2(7) GND LEFT VCCIO6 V REF2(6) GND Bank 2 Bank 6 V REF1(6) VREF1(3) VREF2(3) GND Bank 3 Bank 5 Bank 4 VREF1(4) VREF2(4) VREF2(5) V REF1(5) VCCIO5 VCCIO4 GND BOTTOM LatticeECP/EC devices contain two types of sysI/O buffer pairs. 1. Top and Bottom sysI/O Buffer Pairs (Single-Ended Outputs Only) The sysI/O buffer pairs in the top and bottom banks of the device consist of two single-ended output drivers and two sets of single-ended input buffers (both ratioed and referenced). The referenced input buffer can also be configured as a differential input. The two pads in the pair are described as “true” and “comp”, where the true pad is associated with the positive side of the differential input buffer and the comp (complementary) pad is associated with the negative side of the differential input buffer. Only the I/Os on the top and bottom banks have programmable PCI clamps. These I/O banks also support hot socketing with IDK less than 1mA. Note that the PCI clamp is enabled after VCC, VCCAUX and VCCIO are at valid operating levels and the device has been configured. 2. Left and Right sysI/O Buffer Pairs (Differential and Single-Ended Outputs) The sysI/O buffer pairs in the left and right banks of the device consist of two single-ended output drivers, two sets of single-ended input buffers (both ratioed and referenced) and one differential output driver. The referenced input buffer can also be configured as a differential input. In these banks the two pads in the pair are described as “true” and “comp”, where the true pad is associated with the positive side of the differential I/O, and the comp (complementary) pad is associated with the negative side of the differential I/O. Only the left and right banks have LVDS differential output drivers. See the IDK specification for I/O leakage current during power-up. 2-29 GND Lattice Semiconductor Typical I/O Behavior During Power-up Architecture LatticeECP/EC Family Data Sheet The internal power-on-reset (POR) signal is deactivated when VCC and VCCAUX have reached satisfactory levels. After the POR signal is deactivated, the FPGA core logic becomes active. It is the user’s responsibility to ensure that all other VCCIO banks are active with valid input logic levels to properly control the output logic states of all the I/O banks that are critical to the application. For more information about controlling the output logic state with valid input logic levels during power-up in LatticeECP/EC devices, see the list of technical documentation at the end of this data sheet. The VCC and VCCAUX supply the power to the FPGA core fabric, whereas the VCCIO supplies power to the I/O buffers. In order to simplify system design while providing consistent and predictable I/O behavior, it is recommended that the I/O buffers be powered-up prior to the FPGA core fabric. VCCIO supplies should be powered-up before or together with the VCC and VCCAUX supplies. Supported Standards The LatticeECP/EC sysI/O buffer supports both single-ended and differential standards. Single-ended standards can be further subdivided into LVCMOS, LVTTL and other standards. The buffers support the LVTTL, LVCMOS 1.2, 1.5, 1.8, 2.5 and 3.3V standards. In the LVCMOS and LVTTL modes, the buffer has individually configurable options for drive strength, bus maintenance (weak pull-up, weak pull-down, or a bus-keeper latch) and open drain. Other single-ended standards supported include SSTL and HSTL. Differential standards supported include LVDS, BLVDS, LVPECL, RSDS, differential SSTL and differential HSTL. Tables 2-13 and 2-14 show the I/O standards (together with their supply and reference voltages) supported by the LatticeECP/EC devices. For further information about utilizing the sysI/O buffer to support a variety of standards please see the the list of technical information at the end of this data sheet. Table 2-13. Supported Input Standards Input Standard Single Ended Interfaces LVTTL LVCMOS332 LVCMOS252 LVCMOS18 LVCMOS15 LVCMOS122 PCI HSTL18 Class I, II HSTL18 Class III HSTL15 Class I HSTL15 Class III SSTL3 Class I, II SSTL2 Class I, II SSTL18 Class I Differential Interfaces Differential SSTL18 Class I Differential SSTL2 Class I, II Differential SSTL3 Class I, II Differential HSTL15 Class I, III Differential HSTL18 Class I, II, III LVDS, LVPECL, BLVDS, RSDS — — — — — — — — — — — — — — — — — — — 0.9 1.08 0.75 0.9 1.5 1.25 0.9 — — — 1.8 1.5 — 3.3 — — — — — — — VREF (Nom.) VCCIO1 (Nom.) 1. When not specified VCCIO can be set anywhere in the valid operating range. 2. JTAG inputs do not have a fixed threshold option and always follow VCCJ. 2-30 Lattice Semiconductor Table 2-14. Supported Output Standards Output Standard Single-ended Interfaces LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 LVCMOS33, Open Drain LVCMOS25, Open Drain LVCMOS18, Open Drain LVCMOS15, Open Drain LVCMOS12, Open Drain PCI33 HSTL18 Class I, II, III HSTL15 Class I, III SSTL3 Class I, II SSTL2 Class I, II SSTL18 Class I Differential Interfaces Differential SSTL3, Class I, II Differential SSTL2, Class I, II Differential SSTL18, Class I Differential HSTL18, Class I, II, III Differential HSTL15, Class I, III LVDS BLVDS1 LVPECL1 RSDS1 1. Emulated with external resistors. Architecture LatticeECP/EC Family Data Sheet Drive 4mA, 8mA, 12mA, 16mA, 20mA 4mA, 8mA, 12mA 16mA, 20mA 4mA, 8mA, 12mA, 16mA, 20mA 4mA, 8mA, 12mA, 16mA 4mA, 8mA 2mA, 6mA 4mA, 8mA, 12mA 16mA, 20mA 4mA, 8mA, 12mA 16mA, 20mA 4mA, 8mA, 12mA 16mA 4mA, 8mA 2mA, 6mA N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A VCCIO (Nom.) 3.3 3.3 2.5 1.8 1.5 1.2 — — — — — 3.3 1.8 1.5 3.3 2.5 1.8 3.3 2.5 1.8 1.8 1.5 2.5 2.5 3.3 2.5 Hot Socketing The LatticeECP/EC devices have been carefully designed to ensure predictable behavior during power-up and power-down. Power supplies can be sequenced in any order. During power up and power-down sequences, the I/Os remain in tristate until the power supply voltage is high enough to ensure reliable operation. In addition, leakage into I/O pins is controlled within specified limits, this allows for easy integration with the rest of the system. These capabilities make the LatticeECP/EC ideal for many multiple power supply and hot-swap applications. Configuration and Testing The following section describes the configuration and testing features of the LatticeECP/EC devices. IEEE 1149.1-Compliant Boundary Scan Testability All LatticeECP/EC devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant test access port (TAP). This allows functional testing of the circuit board, on which the device is mounted, through a serial scan path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to 2-31 Lattice Semiconductor Architecture LatticeECP/EC Family Data Sheet be shifted in and loaded directly onto test nodes, or test data to be captured and shifted out for verification. The test access port consists of dedicated I/Os: TDI, TDO, TCK and TMS. The test access port has its own supply voltage VCCJ and can operate with LVCMOS3.3, 2.5, 1.8, 1.5 and 1.2 standards. For more details on boundary scan test, please see information regarding additional technical documentation at the end of this data sheet. Device Configuration All LatticeECP/EC devices contain two possible ports that can be used for device configuration. The test access port (TAP), which supports bit-wide configuration, and the sysCONFIG port that supports both byte-wide and serial configuration. The TAP supports both the IEEE Std. 1149.1 Boundary Scan specification and the IEEE Std. 1532 In-System Configuration specification. The sysCONFIG port is a 20-pin interface with six of the I/Os used as dedicated pins and the rest being dual-use pins (please refer to TN1053 for more information about using the dual-use pins as general purpose I/O). There are four configuration options for LatticeECP/EC devices: 1. Industry standard SPI memories. 2. Industry standard byte wide flash and ispMACH 4000 for control/addressing. 3. Configuration from system microprocessor via the configuration bus or TAP. 4. Industry standard FPGA board memory. On power-up, the FPGA SRAM is ready to be configured with the sysCONFIG port active. The IEEE 1149.1 serial mode can be activated any time after power-up by sending the appropriate command through the TAP port. Once a configuration port is selected, that port is locked and another configuration port cannot be activated until the next power-up sequence. For more information about device configuration, please see the list of technical documentation at the end of this data sheet. Internal Logic Analyzer Capability (ispTRACY) All LatticeECP/EC devices support an internal logic analyzer diagnostic feature. The diagnostic features provide capabilities similar to an external logic analyzer, such as programmable event and trigger condition and deep trace memory. This feature is enabled by Lattice’s ispTRACY. The ispTRACY utility is added into the user design at compile time. For more information about ispTRACY, please see information regarding additional technical documentation at the end of this data sheet. External Resistor LatticeECP/EC devices require a single external, 10K ohm +/- 1% value between the XRES pin and ground. Device configuration will not be completed if this resistor is missing. There is no boundary scan register on the external resistor pad. 2-32 Lattice Semiconductor Oscillator Architecture LatticeECP/EC Family Data Sheet Every LatticeECP/EC device has an internal CMOS oscillator which is used to derive a master clock for configuration. The oscillator and the master clock run continuously. The default value of the master clock is 2.5MHz. Table 215 lists all the available Master Clock frequencies. When a different Master Clock is selected during the design process, the following sequence takes place: 1. User selects a different Master Clock frequency. 2. During configuration the device starts with the default (2.5MHz) Master Clock frequency. 3. The clock configuration settings are contained in the early configuration bit stream. 4. The Master Clock frequency changes to the selected frequency once the clock configuration bits are received. For further information about the use of this oscillator for configuration, please see the list of technical documentation at the end of this data sheet. Table 2-15. Selectable Master Clock (CCLK) Frequencies During Configuration CCLK (MHz) 2.5* 4.3 5.4 6.9 8.1 9.2 10.0 CCLK (MHz) 13 15 20 26 30 34 41 CCLK (MHz) 45 51 55 60 130 — — Density Shifting The LatticeECP/EC family has been designed to ensure that different density devices in the same package have the same pin-out. Furthermore, the architecture ensures a high success rate when performing design migration from lower density parts to higher density parts. In many cases, it is also possible to shift a lower utilization design targeted for a high-density device to a lower density device. However, the exact details of the final resource utilization will impact the likely success in each case. 2-33 LatticeECP/EC Family Data Sheet DC and Switching Characteristics February 2008 Data Sheet Absolute Maximum Ratings1, 2, 3 Supply Voltage VCC . . . . . . . . . . . . . . . . . . . -0.5 to 1.32V Supply Voltage VCCAUX . . . . . . . . . . . . . . . . -0.5 to 3.75V Supply Voltage VCCJ . . . . . . . . . . . . . . . . . . -0.5 to 3.75V Output Supply Voltage VCCIO . . . . . . . . . . . -0.5 to 3.75V Dedicated Input Voltage Applied4 . . . . . . . . -0.5 to 4.25V I/O Tristate Voltage Applied 4 . . . . . . . . . . . . -0.5 to 3.75V Storage Temperature (Ambient) . . . . . . . . . -65 to 150°C Junction Temp. (Tj). . . . . . . . . . . . . . . . . . . . . . . . +125°C 1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. 2. Compliance with the Lattice Thermal Management document is required. 3. All voltages referenced to GND. 4. Overshoot and undershoot of -2V to (VIHMAX + 2) volts is permitted for a duration of VCCIO Min. — — — Typ. — — 35 Max. +/-1000 +/-1000 — Units µA µA mA Top and Bottom General Purpose sysI/Os (Banks 0, 1, 4 and 5), JTAG and Dedicated sysCONFIG Pins Left and Right General Purpose sysI/Os (Banks 2, 3, 6 and 7) IDK_LR 1. 2. 3. 4. Input or I/O Leakage Current Insensitive to sequence of VCC, VCCAUX and VCCIO. However, assumes monotonic rise/fall rates for VCC, VCCAUX and VCCIO. 0 ≤ VCC ≤ VCC (MAX), 0 ≤ VCCIO ≤ VCCIO (MAX) or 0 ≤ VCCAUX ≤ VCCAUX (MAX). IDK is additive to IPU, IPW or IBH. LVCMOS and LVTTL only. © 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 3-1 DC and Switching_01.9 Lattice Semiconductor DC and Switching Characteristics LatticeECP/EC Family Data Sheet DC Electrical Characteristics Over Recommended Operating Conditions Symbol IIL, IIH IIH1, 3 IPU IPD IBHLS IBHHS IBHLO IBHLH VBHT C1 C2 1 Parameter Input or I/O Leakage Input or I/O High Leakage I/O Active Pull-up Current I/O Active Pull-down Current Bus Hold Low sustaining current Bus Hold Low Overdrive current Bus Hold High Overdrive current Bus Hold trip Points I/O Capacitance 2 Condition 0 ≤ VIN ≤ (VCCIO - 0.2V) (VCCIO - 0.2V) ≤ VIH ≤ 3.6V 0 ≤ VIN ≤ 0.7 VCCIO VIL (MAX) ≤ VIN ≤ VIH (MAX) VIN = VIL (MAX) 0 ≤ VIN ≤ VIH (MAX) 0 ≤ VIN ≤ VIH (MAX) 0 ≤ VIN ≤ VIH (MAX) VCCIO = 3.3V, 2.5V, 1.8V, 1.5V, 1.2V, VCC = 1.2V, VIO = 0 to VIH (MAX) VCCIO = 3.3V, 2.5V, 1.8V, 1.5V, 1.2V, VCC = 1.2V, VIO = 0 to VIH (MAX) Min. — — -30 30 30 -30 — — VIL (MAX) — — Typ. — — — — — — — — — 8 6 Max. 10 40 -150 150 — — 150 -150 VIH (MIN) — — Units µA µA µA µA µA µA µA µA V pf pf Bus Hold High sustaining current VIN = 0.7VCCIO Dedicated Input Capacitance2 1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tri-stated. It is not measured with the output driver active. Bus maintenance circuits are disabled. 2. TA 25oC, f = 1.0MHz 3. For top and bottom general purpose I/O pins, when VIH is higher than VCCIO, a transient current typically of 30ns in duration or less with a peak current of 6mA can occur on the high-to-low transition. For left and right I/O banks, VIH must be less than or equal to VCCIO. 3-2 Lattice Semiconductor DC and Switching Characteristics LatticeECP/EC Family Data Sheet Supply Current (Standby)1, 2, 3, 4 Over Recommended Operating Conditions Symbol Parameter LFEC1 LFEC3 LFECP6/LFEC6 ICC Core Power Supply Current LFECP10/LFEC10 LFECP15/LFEC15 LFECP20/LFEC20 LFECP33/LFEC33 ICCAUX ICCPLL ICCIO ICCJ 1. 2. 3. 4. 5. 6. Device Typ.5 6 10 15 25 35 60 85 15 5 2 5 Units mA mA mA mA mA mA mA mA mA mA mA Auxiliary Power Supply Current PLL Power Supply Current Bank Power Supply Current6 VCCJ Power Supply Current For further information about supply current, please see the list of technical documentation at the end of this data sheet. Assumes all outputs are tristated, all inputs are configured as LVCMOS and held at the VCCIO or GND. Frequency 0MHz. Pattern represents a “blank” configuration data file. TJ=25oC, power supplies at nominal voltage. Per bank. 3-3 Lattice Semiconductor DC and Switching Characteristics LatticeECP/EC Family Data Sheet Initialization Supply Current1, 2, 3, 4, 5, 6 Over Recommended Operating Conditions Symbol Parameter LFEC1 LFEC3 LFECP6/LFEC6 ICC Core Power Supply Current LFECP10/LFEC10 LFECP15/LFEC15 LFECP20/LFEC20 LFECP33/LFEC33 LFEC1 LFEC3 LFECP6/LFEC6 ICCAUX Auxiliary Power Supply Current LFECP10/LFEC10 LFECP15/LFEC15 LFECP20/LFEC20 LFECP33/LFEC33 ICCPLL PLL Power Supply Current LFEC1 LFEC3 LFECP6/LFEC6 ICCIO Bank Power Supply Current 7 Devices Typ.6 25 40 50 60 70 150 220 30 30 30 35 35 40 40 12 4 5 6 6 7 8 8 20 Units mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA LFECP10/LFEC10 LFECP15/LFEC15 LFECP20/LFEC20 LFECP33/LFEC33 ICCJ 1. 2. 3. 4. 5. 6. 7. VCCJ Power Supply Current Until DONE signal is active. For further information about supply current, please see the list of technical documentation at the end of this data sheet. Assumes all outputs are tristated, all inputs are configured as LVCMOS and held at the VCCIO or GND. Frequency 0MHz. Pattern represents typical design with 65% logic, 55% EBR, 10% routing utilization. TJ=25oC, power supplies at nominal voltage. Per bank. 3-4 Lattice Semiconductor DC and Switching Characteristics LatticeECP/EC Family Data Sheet sysI/O Recommended Operating Conditions VCCIO Standard LVCMOS 3.3 LVCMOS 2.5 LVCMOS 1.8 LVCMOS 1.5 LVCMOS 1.2 LVTTL PCI SSTL18 Class I SSTL2 Class I, II SSTL3 Class I, II HSTL15 Class I HSTL15 Class III HSTL 18 Class I, II HSTL 18 Class III LVDS LVPECL1 BLVDS1 RSDS1 Min. 3.135 2.375 1.71 1.425 1.14 3.135 3.135 1.71 2.375 3.135 1.425 1.425 1.71 1.71 2.375 3.135 2.375 2.375 Typ. 3.3 2.5 1.8 1.5 1.2 3.3 3.3 1.8 2.5 3.3 1.5 1.5 1.8 1.8 2.5 3.3 2.5 2.5 Max. 3.465 2.625 1.89 1.575 1.26 3.465 3.465 1.89 2.625 3.465 1.575 1.575 1.89 1.89 2.625 3.465 2.625 2.625 Min. — — — — — — — 0.833 1.15 1.3 0.68 — — — — — — — VREF (V) Typ. — — — — — — — 0.90 1.25 1.5 0.75 0.9 0.9 1.08 — — — — Max. — — — — — — — 0.969 1.35 1.7 0.9 — — — — — — — 1. Outputs are implemented with the addition of external resistors. VCCIO applies to outputs only. 3-5 Lattice Semiconductor DC and Switching Characteristics LatticeECP/EC Family Data Sheet sysI/O Single-Ended DC Electrical Characteristics Input/Output Standard LVCMOS 3.3 VIL Min. (V) -0.3 Max. (V) 0.8 VIH Min. (V) 2.0 VOL Max. (V) Max. (V) 3.6 0.4 0.2 LVTTL -0.3 0.8 2.0 3.6 0.4 0.2 LVCMOS 2.5 -0.3 0.7 1.7 3.6 0.4 0.2 LVCMOS 1.8 LVCMOS 1.5 LVCMOS 1.2 PCI SSTL3 class I SSTL3 class II SSTL2 class I SSTL2 class II SSTL18 class I HSTL15 class I HSTL15 class III HSTL18 class I HSTL18 class II HSTL18 class III -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 0.35VCCIO 0.35VCCIO 0.35VCC 0.3VCCIO VREF - 0.2 VREF - 0.2 VREF - 0.18 VREF - 0.18 VREF - 0.1 VREF - 0.1 VREF - 0.1 VREF - 0.1 VREF - 0.1 0.65VCCIO 0.65VCCIO 0.65VCC 0.5VCCIO VREF + 0.2 VREF + 0.2 VREF + 0.18 VREF + 0.18 VREF + 0.1 VREF + 0.1 VREF + 0.1 VREF + 0.1 VREF + 0.1 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 0.4 0.2 0.4 0.2 0.4 0.2 0.1VCCIO 0.7 0.5 0.54 0.35 0.4 0.4 0.4 0.4 0.4 0.4 VOH Min. (V) VCCIO - 0.4 VCCIO - 0.2 VCCIO - 0.4 VCCIO - 0.2 VCCIO - 0.4 VCCIO - 0.2 VCCIO - 0.4 VCCIO - 0.2 VCCIO - 0.4 VCCIO - 0.2 VCCIO - 0.4 VCCIO - 0.2 0.9VCCIO VCCIO - 1.1 VCCIO - 0.9 VCCIO - 0.62 VCCIO - 0.43 VCCIO - 0.4 VCCIO - 0.4 VCCIO - 0.4 VCCIO - 0.4 VCCIO - 0.4 VCCIO - 0.4 IOL1 (mA) 20, 16, 12, 8, 4 0.1 20, 16, 12, 8, 4 0.1 20, 16, 12, 8, 4 0.1 16, 12, 8, 4 0.1 8, 4 0.1 6, 2 0.1 1.5 8 16 7.6 15.2 6.7 8 24 9.6 16 24 IOH1 (mA) -20, -16, -12, -8, -4 -0.1 -20, -16, -12, -8, -4 -0.1 -20, -16, -12, -8, -4 -0.1 -16, -12, -8, -4 -0.1 -8, -4 -0.1 -6, -2 -0.1 -0.5 -8 -16 -7.6 -15.2 -6.7 -8 -8 -9.6 -16 -8 VREF - 0.125 VREF + 0.125 1. The average DC current drawn by I/Os between GND connections, or between the last GND in an I/O bank and the end of an I/O bank, as shown in the logic signal connections table shall not exceed n * 8mA. Where n is the number of I/Os between bank GND connections or between the last GND in a bank and the end of a bank. 3-6 Lattice Semiconductor DC and Switching Characteristics LatticeECP/EC Family Data Sheet sysI/O Differential Electrical Characteristics LVDS Over Recommended Operating Conditions Parameter Symbol VINP, VINM VTHD VCM IIN VOH VOL VOD ΔVOD VOS ΔVOS IOSD Parameter Description Input voltage Differential input threshold 100mV ≤ VTHD Input common mode voltage Input current Output high voltage for VOP or VOM Output low voltage for VOP or VOM Output voltage differential Change in VOD between high and low Output voltage offset Change in VOS between H and L Output short circuit current VOD = 0V Driver outputs shorted (VOP + VOM)/2, RT = 100 Ohm 200mV ≤ VTHD 350mV ≤ VTHD Power on or power off RT = 100 Ohm RT = 100 Ohm (VOP - VOM), RT = 100 Ohm Test Conditions Min. 0 +/-100 VTHD/2 VTHD/2 VTHD/2 — — 0.9V 250 — 1.125 — — Typ. — — 1.2 1.2 1.2 — 1.38 1.03 350 — 1.25 — — Max. 2.4 — 1.8 1.9 2.0 +/-10 1.60 — 450 50 1.375 50 6 Units V mV V V V µA V V mV mV V mV mA 3-7 Lattice Semiconductor Differential HSTL and SSTL DC and Switching Characteristics LatticeECP/EC Family Data Sheet Differential HSTL and SSTL outputs are implemented as a pair of complementary single-ended outputs. All allowable single-ended output classes (class I and class II) are supported in this mode. LVDS25E The top and bottom side of LatticeECP/EC devices support LVDS outputs via emulated complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The scheme shown in Figure 3-1 is one possible solution for point-to-point signals. Figure 3-1. LVDS25E Output Termination Example Bourns CAT16-LV4F12 VCCIO = 2.5V (±5%) RS=165 ohms (±1%) VCCIO = 2.5V (±5%) RS=165 ohms (±1%) RD = 140 ohms (±1%) RD = 100 ohms (±1%) + - Transmission line, Zo = 100 ohm differential ON-chip OFF-chip OFF-chip ON-chip Table 3-1. LVDS25E DC Conditions Parameter VOH VOL VOD VCM ZBACK Description Output high voltage Output low voltage Output differential voltage Output common mode voltage Back impedance Typical 1.42 1.08 0.35 1.25 100 Units V V V V Ω 3-8 Lattice Semiconductor BLVDS DC and Switching Characteristics LatticeECP/EC Family Data Sheet The LatticeECP/EC devices support BLVDS standard. This standard is emulated using complementary LVCMOS outputs in conjunction with a parallel external resistor across the driver outputs. BLVDS is intended for use when multi-drop and bi-directional multi-point differential signaling is required. The scheme shown in Figure 3-2 is one possible solution for bi-directional multi-point differential signals. Figure 3-2. BLVDS Multi-point Output Example Heavily loaded backplane, effective Zo ~ 45 to 90 ohms differential 2.5V 80 45-90 ohms 45-90 ohms 80 2.5V 80 2.5V 2.5V 80 + - 80 ... + 80 80 + - 2.5V 2.5V 2.5V 2.5V - Table 3-2. BLVDS DC Conditions1 Over Recommended Operating Conditions Typical Parameter ZOUT RTLEFT RTRIGHT VOH VOL VOD VCM IDC Description Output impedance Left end termination Right end termination Output high voltage Output low voltage Output differential voltage Output common mode voltage DC output current Zo = 45 100 45 45 1.375 1.125 0.25 1.25 11.2 Zo = 90 100 90 90 1.48 1.02 0.46 1.25 10.2 Units ohm ohm ohm V V V V mA 1. For input buffer, see LVDS table. 3-9 + Lattice Semiconductor LVPECL DC and Switching Characteristics LatticeECP/EC Family Data Sheet The LatticeECP/EC devices support differential LVPECL standard. This standard is emulated using complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The LVPECL input standard is supported by the LVDS differential input buffer. The scheme shown in Figure 3-3 is one possible solution for point-to-point signals. Figure 3-3. Differential LVPECL 3.3V 100 ohms + 3.3V 100 ohms Transmission line, Zo = 100 ohm differential Off-chip ~150 ohms 100 ohms - Table 3-3. LVPECL DC Conditions1 Over Recommended Operating Conditions Parameter ZOUT RP RT VOH VOL VOD VCM ZBACK IDC Description Output impedance Driver parallel resistor Receiver termination Output high voltage Output low voltage Output differential voltage Output common mode voltage Back impedance DC output current Typical 100 150 100 2.03 1.27 0.76 1.65 85.7 12.7 Units ohm ohm ohm V V V V ohm mA 1. For input buffer, see LVDS table. For further information about LVPECL, BLVDS and other differential interfaces please see the list of technical information at the end of this data sheet. 3-10 Lattice Semiconductor RSDS DC and Switching Characteristics LatticeECP/EC Family Data Sheet The LatticeECP/EC devices support differential RSDS standard. This standard is emulated using complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The RSDS input standard is supported by the LVDS differential input buffer. The scheme shown in Figure 3-4 is one possible solution for RSDS standard implementation. Use LVDS25E mode with suggested resistors for RSDS operation. Resistor values in Figure 3-4 are industry standard values for 1% resistors. Figure 3-4. RSDS (Reduced Swing Differential Standard) VCCIO = 2.5V 294 Zo = 100 VCCIO = 2.5V 294 + 121 100 - On-chip Emulated RSDS Buffer Off-chip Table 3-4. RSDS DC Conditions Parameter ZOUT RS RP RT VOH VOL VOD VCM ZBACK IDC Description Output impedance Driver series resistor Driver parallel resistor Receiver termination Output high voltage Output low voltage Output differential voltage Output common mode voltage Back impedance DC output current Typical 20 294 121 100 1.35 1.15 0.20 1.25 101.5 3.66 Units ohm ohm ohm ohm V V V V ohm mA 3-11 Lattice Semiconductor DC and Switching Characteristics LatticeECP/EC Family Data Sheet Typical Building Block Function Performance Pin-to-Pin Performance (LVCMOS25 12mA Drive) Function Basic Functions 16-bit decoder 32-bit decoder 64-bit decoder 4:1 MUX 8:1 MUX 16:1 MUX 32:1 MUX 5.5 6.9 7.1 4.3 4.7 5.0 5.5 ns ns ns ns ns ns ns -5 Timing Units Register-to-Register Performance1 Function Basic Functions 16 bit decoder 32 bit decoder 64 bit decoder 4:1 MUX 8:1 MUX 16:1 MUX 32:1 MUX 8-bit adder 16-bit adder 64-bit adder 16-bit counter 32-bit counter 64-bit counter 64-bit accumulator Embedded Memory Functions 256x36 Single Port RAM 512x18 True-Dual Port RAM Distributed Memory Functions 16x2 Single Port RAM 64x2 Single Port RAM 128x4 Single Port RAM 32x2 Pseudo-Dual Port RAM 64x4 Pseudo-Dual Port RAM DSP Function2 9x9 Pipelined Multiply/Accumulate 18x18 Pipelined Multiply/Accumulate 36x36 Pipelined Multiply 242 238 235 MHz MHz MHz 460 375 294 392 332 MHz MHz MHz MHz MHz 280 280 MHz MHz 410 283 272 613 565 526 442 363 353 196 414 317 216 178 MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz -5 Timing Units 1. These timing numbers were generated using the ispLEVER design tool. Exact performance may vary with design and tool version. The tool uses internal parameters that have been characterized but are not tested on every device. 2. Applies to LatticeECP devices only. Timing v.G 0.30 3-12 Lattice Semiconductor DC and Switching Characteristics LatticeECP/EC Family Data Sheet Derating Timing Tables Logic Timing provided in the following sections of the data sheet and the ispLEVER design tools are worst-case numbers in the operating range. Actual delays at nominal temperature and voltage for best-case process, can be much better than the values given in the tables. To calculate logic timing numbers at a particular temperature and voltage multiply the noted numbers with the derating factors provided below. The junction temperature for the FPGA depends on the power dissipation by the device, the package thermal characteristics (ΘJA), and the ambient temperature, as calculated with the following equation: TJMAX = TAMAX + (Power * ΘJA) The user must determine this temperature and then use it to determine the derating factor based on the following derating tables: TJ °C. Table 3-5. Delay Derating Table for Internal Blocks TJ °C Commercial — — 0 25 85 TJ °C Industrial -40 -25 20 45 105 Power Supply Voltage 1.14V 0.82 0.82 0.89 0.93 1.00 1.2V 0.77 0.76 0.83 0.87 0.94 1.26V 0.71 0.71 0.78 0.81 0.89 3-13 Lattice Semiconductor DC and Switching Characteristics LatticeECP/EC Family Data Sheet LatticeECP/EC External Switching Characteristics Over Recommended Operating Conditions -5 Parameter Description Device LFEC1 LFEC3 LFEC6 tCO7 Clock to Output - PIO Output Register LFEC10 LFEC15 LFEC20 LFEC33 LFEC1 LFEC3 LFEC6 tSU 7 -4 Max. 5.09 5.71 5.60 5.47 5.67 5.89 6.19 — — — — — — — — — — — — — — — — — — — — — — — — — — — — 420 Min. — — — — — — — -0.10 -0.84 -0.76 -0.52 -0.84 -1.06 -1.34 2.62 3.36 3.23 3.08 3.32 3.58 3.93 4.03 3.29 3.37 3.61 3.29 3.07 2.79 -1.57 -0.83 -0.96 -1.12 -0.88 -0.61 -0.26 — Max. 6.11 6.85 6.72 6.57 6.81 7.07 7.42 — — — — — — — — — — — — — — — — — — — — — — — — — — — — 378 Min. — — — — — — — -0.12 -0.98 -0.89 -0.61 -0.98 -1.24 -1.56 3.06 3.92 3.77 3.59 3.87 4.18 4.59 4.70 3.84 3.93 4.21 3.83 3.58 3.25 -1.83 -0.97 -1.12 -1.30 -1.02 -0.71 -0.30 — -3 Max. 7.13 7.99 7.84 7.66 7.94 8.25 8.66 — — — — — — — — — — — — — — — — — — — — — — — — — — — — 340 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Mhz Min. — — — — — — — -0.08 -0.70 -0.63 -0.43 -0.70 -0.88 -1.12 2.19 2.80 2.69 2.56 2.76 2.99 3.28 3.36 2.74 2.81 3.01 2.74 2.56 2.32 -1.31 -0.70 -0.80 -0.93 -0.73 -0.51 -0.22 — General I/O Pin Parameters (Using Primary Clock without PLL)1 Clock to Data Setup - PIO Input Register LFEC10 LFEC15 LFEC20 LFEC33 LFEC1 LFEC3 LFEC6 tH7 Clock to Data Hold - PIO Input Register LFEC10 LFEC15 LFEC20 LFEC33 LFEC1 LFEC3 LFEC6 tSU_DEL 7 Clock to Data Setup - PIO Input Register with Data Input Delay LFEC10 LFEC15 LFEC20 LFEC33 LFEC1 LFEC3 LFEC6 tH_DEL 7 Clock to Data Hold - PIO Input Register with Input Data Delay LFEC10 LFEC15 LFEC20 LFEC33 fMAX_IO2 Clock Frequency of I/O and PFU Register Data Valid After DQS (DDR Read) Data Hold After DQS (DDR Read) All DDR I/O Pin Parameters3, 4, 5 tDVADQ tDVEDQ All All — 0.67 0.19 — — 0.67 0.19 — — 0.67 0.19 — UI UI 3-14 Lattice Semiconductor DC and Switching Characteristics LatticeECP/EC Family Data Sheet LatticeECP/EC External Switching Characteristics (Continued) Over Recommended Operating Conditions -5 Parameter tDQVBS tDQVAS fMAX_DDR fMAX_PRI2 tW_PRI tSKEW_PRI 1. 2. 3. 4. 5. 6. 7. -4 Max. — — 200 420 — 250 Min. 0.20 0.20 95 — 1.19 — Max. — — 166 378 — 300 Min. 0.20 0.20 95 — 1.19 — -3 Max. — — 133 340 — 350 Units UI UI MHz MHz ns ps Description Data Valid Before DQS Data Valid After DQS DDR Clock Frequency Frequency for Primary Clock Tree Clock Pulse Width for Primary Clock Primary Clock Skew within an I/O Bank Device All All All All All All Min. 0.20 0.20 95 — 1.19 — Primary and Secondary Clock6 General timing numbers based on LVCMOS2.5V, 12 mA. Loading of 0 pF. Using LVDS I/O standard. DDR timing numbers based on SSTL I/O. DDR specifications are characterized but not tested. UI is average bit period. Based on a single primary clock. These timing numbers were generated using ispLEVER design tool. Exact performance may vary with design and tool version. The tool uses internal parameters that have been characterized but are not tested on every device. Timing v.G 0.30 Figure 3-5. DDR Timings DQ and DQS Read Timings DQS DQ tDVADQ tDVEDQ DQ and DQS Write Timings DQS DQ tDQVBS tDQVAS 3-15 Lattice Semiconductor DC and Switching Characteristics LatticeECP/EC Family Data Sheet LatticeECP/EC Internal Switching Characteristics Over Recommended Operating Conditions -5 Parameter PFU/PFF Logic Mode Timing tLUT4_PFU tLUT6_PFU tLSR_PFU tSUM_PFU tHM_PFU tSUD_PFU tHD_PFU tCK2Q_PFU tLE2Q_PFU tLD2Q_PFU tCORAM_PFU tSUDATA_PFU tHDATA_PFU tSUADDR_PFU tHADDR_PFU tSUWREN_PFU tHWREN_PFU PIC Timing PIO Input/Output Buffer Timing tIN_PIO tOUT_PIO tSUI_PIO tHI_PIO tCOO_PIO tSUCE_PIO tHCE_PIO tSULSR_PIO tHLSR_PIO EBR Timing tCO_EBR tCOO_EBR tSUDATA_EBR tHDATA_EBR tSUADDR_EBR tHADDR_EBR tSUWREN_EBR tHWREN_EBR Clock to Output from Address or Data Clock to Output from EBR output Register Setup Data to EBR Memory Hold Data to EBR Memory Setup Address to EBR Memory Hold Address to EBR Memory Setup Write/Read Enable to EBR Memory Hold Write/Read Enable to EBR Memory — — -0.29 0.37 -0.29 0.37 -0.18 0.23 3.64 0.74 — — — — — — — — -0.35 0.44 -0.35 0.45 -0.22 0.28 4.37 0.88 — — — — — — — — -0.41 0.52 -0.41 0.52 -0.26 0.33 5.10 1.03 — — — — — — ns ns ns ns ns ns ns ns Input Buffer Delay Output Buffer Delay Input Register Setup Time (Data Before Clock) Input Register Hold Time (Data after Clock) Output Register Clock to Output Delay Input Register Clock Enable Setup Time Input Register Clock Enable Hold Time Set/Reset Setup Time Set/Reset Hold Time — — 0.90 0.62 — -0.10 0.12 0.18 -0.15 0.56 1.92 — — 0.33 — — — — — — 1.08 0.74 — -0.12 0.14 0.21 -0.18 0.67 2.31 — — 0.40 — — — — — — 1.26 0.87 — -0.14 0.17 0.25 -0.21 0.78 2.69 — — 0.46 — — — — ns ns ns ns ns ns ns ns ns LUT4 Delay (A to D Inputs to F Output) LUT6 Delay (A to D Inputs to OFX Output) Set/Reset to Output of PFU Clock to Mux (M0,M1) Input Setup Time Clock to Mux (M0,M1) Input Hold Time Clock to D Input Setup Time Clock to D Input Hold time Clock to Q Delay, D-type Register Configuration Clock to Q Delay Latch Configuration D to Q Throughput Delay when Latch is Enabled Clock to Output Data Setup Time Data Hold Time Address Setup Time Address Hold Time Write/Read Enable Setup Time Write/Read Enable Hold Time — — — 0.12 -0.05 0.12 -0.03 — — — — -0.20 0.26 -0.51 0.64 -0.24 0.30 0.25 0.40 0.81 — — — — 0.36 0.48 0.50 0.36 — — — — — — — — — 0.14 -0.06 0.14 -0.03 — — — — -0.24 0.31 -0.62 0.77 -0.29 0.36 0.31 0.48 0.98 — — — — 0.44 0.58 0.60 0.44 — — — — — — — — — 0.16 -0.06 0.16 -0.04 — — — — -0.28 0.36 -0.72 0.90 -0.34 0.42 0.36 0.56 1.14 — — — — 0.51 0.68 0.69 0.51 — — — — — — ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. Min. -4 Max. Min. -3 Max. Units PFU Dual Port Memory Mode Timing IOLOGIC Input/Output Timing 3-16 Lattice Semiconductor DC and Switching Characteristics LatticeECP/EC Family Data Sheet LatticeECP/EC Internal Switching Characteristics (Continued) Over Recommended Operating Conditions -5 Parameter tSUCE_EBR tHCE_EBR tRSTO_EBR PLL Parameters tRSTREC tRSTSU tSUI_DSP tHI_DSP tSUP_DSP tHP_DSP tSUO_DSP4 tHO_DSP 4 -4 Max. — — 1.47 Min. 0.21 -0.17 — Max. — — 1.76 Min. 0.25 -0.20 — -3 Max. — — 2.05 Units ns ns ns Description Clock Enable Setup Time to EBR Output Register Clock Enable Hold Time to EBR Output Register Reset To Output Delay Time from EBR Output Register Reset Recovery to Rising Clock Reset Signal Setup Time Input Register Setup Time Input Register Hold Time Pipeline Register Setup Time Pipeline Register Hold Time Output Register Setup Time Output Register Hold Time Input Register Clock to Output Time Pipeline Register Clock to Output Time Output Register Clock to Output Time AdSub Input Register Setup Time AdSub Input Register Hold Time Min. 0.18 -0.14 — 1.00 1.00 -0.38 0.71 3.31 0.71 5.54 0.71 — — — -0.38 0.71 — — — — — — — — 7.50 4.66 1.47 — — 1.00 1.00 -0.30 0.86 3.98 0.86 6.64 0.86 — — — -0.30 0.86 — — — — — — — — 9.00 5.60 1.77 — — 1.00 1.00 -0.23 1.00 4.64 1.00 7.75 1.00 — — — -0.23 1.00 — — — — — — — — 10.50 6.53 2.06 — — ns ns ns ns ns ns ns ns ns ns ns ns ns DSP Block Timing2, 3 tCOI_DSP4 tCOP_DSP 4 tCOO_DSP tSUADSUB tHADSUB 1. Internal parameters are characterized but not tested on every device. 2. These parameters apply to LatticeECP devices only. 3. DSP Block is configured in Multiply Add/Sub 18 x 18 Mode. 4. These parameters include the Adder Subtractor block in the path. Timing v.G 0.30 3-17 Lattice Semiconductor DC and Switching Characteristics LatticeECP/EC Family Data Sheet Timing Diagrams PFU Timing Diagrams Figure 3-6. Slice Single/Dual Port Write Cycle Timing CK WRE AD[3:0] AD DI[1:0] D DO[1:0] Old Data D Figure 3-7. Slice Single /Dual Port Read Cycle Timing WRE AD[3:0] AD DO[1:0] Old Data D 3-18 Lattice Semiconductor EBR Memory Timing Diagrams Figure 3-8. Read/Write Mode (Normal) CLKA DC and Switching Characteristics LatticeECP/EC Family Data Sheet CSA WEA ADA A0 tSU tH A1 A0 A1 A0 DIA D0 D1 tCO_EBR tCO_EBR D0 D1 tCO_EBR D0 DOA Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive edge of the clock. Figure 3-9. Read/Write Mode with Input and Output Registers CLKA CSA WEA ADA A0 A1 A0 A1 A0 tSU tH DIA D0 D1 tCOO_EBR tCOO_EBR DOA (Regs) Mem(n) data from previous read output is only updated during a read cycle D0 D1 3-19 Lattice Semiconductor DC and Switching Characteristics LatticeECP/EC Family Data Sheet Figure 3-10. Read Before Write (SP Read/Write on Port A, Input Registers Only) CLKA CSA WEA ADA tSU A0 tH A1 A0 A1 A0 DIA D0 tACCESS D1 tACCESS D2 tACCESS D3 tACCESS D1 tACCESS DOA old A0 Data old A1 Data D0 D1 D2 Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive edge of the clock. Figure 3-11. Write Through (SP Read/Write On Port A, Input Registers Only) CLKA CSA WEA Three consecutive writes to A0 ADA A0 tSU tH A1 A0 DIA D0 tACCESS D1 tACCESS D2 tACCESS D3 D4 tACCESS DOA Data from Prev Read or Write D0 D1 D2 D3 D4 Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive edge of the clock. 3-20 Lattice Semiconductor DC and Switching Characteristics LatticeECP/EC Family Data Sheet LatticeECP/EC Family Timing Adders1, 2, 3 Over Recommended Operating Conditions Buffer Type Input Adjusters LVDS25 BLVDS25 LVPECL33 HSTL18_I HSTL18_II HSTL18_III HSTL18D_I HSTL18D_II HSTL18D_III HSTL15_I HSTL15_III HSTL15D_I HSTL15D_III SSTL33_I SSTL33_II SSTL33D_I SSTL33D_II SSTL25_I SSTL25_II SSTL25D_I SSTL25D_II SSTL18_I SSTL18D_I LVTTL33 LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 PCI33 Output Adjusters LVDS25E LVDS25 BLVDS25 LVPECL33 HSTL18_I HSTL18_II HSTL18_III HSTL18D_I HSTL18D_II HSTL18D_III HSTL15_I LVDS 2.5 E LVDS 2.5 BLVDS 2.5 LVPECL 3.3 HSTL_18 class I HSTL_18 class II HSTL_18 class III Differential HSTL 18 class I Differential HSTL 18 class II Differential HSTL 18 class III HSTL_15 class I 0.12 -0.44 0.33 0.20 -0.10 0.06 0.15 -0.10 0.06 0.15 0.08 0.14 -0.53 0.40 0.24 -0.12 0.07 0.19 -0.12 0.07 0.19 0.10 0.17 -0.62 0.46 0.28 -0.14 0.08 0.22 -0.14 0.08 0.22 0.11 ns ns ns ns ns ns ns ns ns ns ns LVDS BLVDS LVPECL HSTL_18 class I HSTL_18 class II HSTL_18 class III Differential HSTL 18 class I Differential HSTL 18 class II Differential HSTL 18 class III HSTL_15 class I HSTL_15 class III Differential HSTL 15 class I Differential HSTL 15 class III SSTL_3 class I SSTL_3 class II Differential SSTL_3 class I Differential SSTL_3 class II SSTL_2 class I SSTL_2 class II Differential SSTL_2 class I Differential SSTL_2 class II SSTL_18 class I Differential SSTL_18 class I LVTTL LVCMOS 3.3 LVCMOS 2.5 LVCMOS 1.8 LVCMOS 1.5 LVCMOS 1.2 PCI 0.41 0.41 0.50 0.41 0.41 0.41 0.37 0.37 0.37 0.40 0.40 0.37 0.37 0.46 0.46 0.39 0.39 0.43 0.43 0.38 0.38 0.40 0.37 0.07 0.07 0.00 0.07 0.24 1.27 0.07 0.50 0.50 0.60 0.49 0.49 0.49 0.44 0.44 0.44 0.48 0.48 0.44 0.44 0.55 0.55 0.47 0.47 0.51 0.51 0.45 0.45 0.48 0.44 0.09 0.09 0.00 0.09 0.29 1.52 0.09 0.58 0.58 0.70 0.57 0.57 0.57 0.52 0.52 0.52 0.56 0.56 0.51 0.51 0.64 0.64 0.55 0.55 0.60 0.60 0.53 0.53 0.56 0.51 0.10 0.10 0.00 0.10 0.33 1.77 0.10 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description -5 -4 -3 Units 3-21 Lattice Semiconductor DC and Switching Characteristics LatticeECP/EC Family Data Sheet LatticeECP/EC Family Timing Adders1, 2, 3 (Continued) Over Recommended Operating Conditions Buffer Type HSTL15_II HSTL15_III HSTL15D_I HSTL15D_III SSTL33_I SSTL33_II SSTL33D_I SSTL33D_II SSTL25_I SSTL25_II SSTL25D_I SSTL25D_II SSTL18_I SSTL18D_I LVTTL33_4mA LVTTL33_8mA LVTTL33_12mA LVTTL33_16mA LVTTL33_20mA LVCMOS33_4mA LVCMOS33_8mA LVCMOS33_12mA LVCMOS33_16mA LVCMOS33_20mA LVCMOS25_4mA LVCMOS25_8mA LVCMOS25_12mA LVCMOS25_16mA LVCMOS25_20mA LVCMOS18_4mA LVCMOS18_8mA LVCMOS18_12mA LVCMOS18_16mA LVCMOS15_4mA LVCMOS15_8mA LVCMOS12_2mA LVCMOS12_6mA LVCMOS12_4mA PCI33 Description HSTL_15 class II HSTL_15 class III Differential HSTL 15 class I Differential HSTL 15 class III SSTL_3 class I SSTL_3 class II Differential SSTL_3 class I Differential SSTL_3 class II SSTL_2 class I SSTL_2 class II Differential SSTL_2 class I Differential SSTL_2 class II SSTL_1.8 class I Differential SSTL_1.8 class I LVTTL 4mA drive LVTTL 8mA drive LVTTL 12mA drive LVTTL 16mA drive LVTTL 20mA drive LVCMOS 3.3 4mA drive LVCMOS 3.3 8mA drive LVCMOS 3.3 12mA drive LVCMOS 3.3 16mA drive LVCMOS 3.3 20mA drive LVCMOS 2.5 4mA drive LVCMOS 2.5 8mA drive LVCMOS 2.5 12mA drive LVCMOS 2.5 16mA drive LVCMOS 2.5 20mA drive LVCMOS 1.8 4mA drive LVCMOS 1.8 8mA drive LVCMOS 1.8 12mA drive LVCMOS 1.8 16mA drive LVCMOS 1.5 4mA drive LVCMOS 1.5 8mA drive LVCMOS 1.2 2mA drive LVCMOS 1.2 6mA drive LVCMOS 1.2 4mA drive PCI33 -5 0.10 0.10 0.08 0.10 -0.05 0.40 -0.05 0.40 0.05 0.25 0.05 0.25 0.01 0.01 0.09 0.07 -0.03 0.36 0.28 0.09 0.07 -0.03 0.36 0.28 0.18 0.10 0.00 0.22 0.14 0.15 0.06 0.01 0.16 0.26 0.04 0.36 0.08 0.36 1.05 -4 0.12 0.12 0.10 0.12 -0.06 0.48 -0.06 0.48 0.07 0.30 0.07 0.30 0.01 0.01 0.11 0.08 -0.04 0.43 0.33 0.11 0.08 -0.04 0.43 0.33 0.21 0.12 0.00 0.26 0.16 0.18 0.08 0.01 0.19 0.31 0.04 0.43 0.10 0.43 1.26 -3 0.14 0.14 0.11 0.14 -0.07 0.56 -0.07 0.56 0.08 0.35 0.08 0.35 0.01 0.01 0.13 0.09 -0.05 0.51 0.39 0.13 0.09 -0.05 0.51 0.39 0.25 0.14 0.00 0.31 0.19 0.21 0.09 0.01 0.22 0.36 0.05 0.50 0.11 0.50 1.46 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1. Timing adders are characterized but not tested on every device. 2. LVCMOS timing measured with the load specified in Switching Test Conditions table of this document. 3. All other standards according to the appropriate specification. Timing v.G 0.30 3-22 Lattice Semiconductor DC and Switching Characteristics LatticeECP/EC Family Data Sheet sysCLOCK PLL Timing Over Recommended Operating Conditions Parameter fIN fOUT fOUT2 fVCO fPFD Description Input Clock Frequency (CLKI, CLKFB) Output Clock Frequency (CLKOP, CLKOS) K-Divider Output Frequency (CLKOK) PLL VCO Frequency Phase Detector Input Frequency Default Duty Cycle Elected3 fOUT >= 100MHz fOUT < 100MHz Divider ratio = integer At 90% or 10% 3 Conditions Min. 25 25 0.195 420 25 Typ. — — — — — Max. 420 420 210 840 — Units MHz MHz MHz MHz MHz AC Characteristics tDT tPH4 tOPJIT1 tSK tW tLOCK2 tPA tIPJIT tFBKDLY tHI tLO tRST Output Clock Duty Cycle Output Phase Accuracy Output Clock Period Jitter Input Clock to Output Clock Skew Output Clock Pulse Width PLL Lock-in Time Programmable Delay Unit Input Clock Period Jitter External Feedback Delay Input Clock High Time Input Clock Low Time RST Pulse Width 90% to 90% 10% to 10% 45 — — — — 1 — 100 — — 0.5 0.5 10 50 — — — — — — 250 — — — — — 55 0.05 +/- 125 0.02 +/- 200 — 150 450 +/- 200 10 — — — % UI ps UIPP ps ns µs ps ps ns ns ns ns 1. Jitter sample is taken over 10,000 samples of the primary PLL output with clean reference clock. 2. Output clock is valid after tLOCK for PLL reset and dynamic delay adjustment. 3. Using LVDS output buffers. 4. Relative to CLKOP. Timing v.G 0.30 3-23 Lattice Semiconductor DC and Switching Characteristics LatticeECP/EC Family Data Sheet LatticeECP/EC sysCONFIG Port Timing Specifications Over Recommended Operating Conditions Parameter sysCONFIG Byte Data Flow tSUCBDI tHCBDI tCODO tSUCS tHCS tSUWD tHWD tDCB tCORD tBSCH tBSCL tBSCYC tSUSCDI tHSCDI tCODO tSUMCDI tHMCDI tSSCH tSSCL tICFG tVMC tPRGMRJ tPRGM tDINIT tDPPINIT tDINITD tIODISS tIOENSS tMWC tSUCFG tHCFG tCFGX tCSSPI tCSCCLK tSOCDO Byte D[0:7] Setup Time to CCLK Byte D[0:7] Hold Time to CCLK Clock to Dout in Flowthrough Mode CS[0:1] Setup Time to CCLK CS[0:1] Hold Time to CCLK Write Signal Setup Time to CCLK Write Signal Hold Time to CCLK CCLK to BUSY Delay Time Clock to Out for Read Data Byte Slave Clock Minimum High Pulse Byte Slave Clock Minimum Low Pulse Byte Slave Clock Cycle Time Din Setup time to CCLK Slave Mode Din Hold Time to CCLK Slave Mode Clock to Dout in Flowthrough Mode Din Setup time to CCLK Master Mode Din Hold Time to CCLK Master Mode Serial Slave Clock Minimum High Pulse Serial Slave Clock Minimum Low Pulse Minimum Vcc to INIT High Time from tICFG to Valid Master Clock Program Pin Pulse Rejection PROGRAMN Low Time to Start Configuration INIT Low Time Delay Time from PROGRAMN Low to INIT Low Delay Time from PROGRAMN Low to DONE Low User I/O Disable from PROGRAMN Low User I/O Enabled Time from CCLK Edge During Wake Up Sequence Additional Wake Master Clock Signals after Done Pin High CFG to INITN Setup Time CFG to INITN Hold Time Init High to CCLK Low Init High to CSSPIN Low CCLK Low Before CSSPIN Low CCLK Low to Output Valid 7 1 — 7 1 7 1 — — 6 9 15 7 1 — 7 1 6 6 — — — 25 — — — — — 120 100 100 — — 0 — — — 12 — — — — 12 12 — — — — — 12 — — — — 50 2 8 — 1 37 37 35 25 — — — 80 2 15 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms us ns ns ms ns ns ns ns cycles ns ns ns us ns ns Description Min. Typ. Max. Units sysCONFIG Byte Slave Clocking sysCONFIG Serial (Bit) Data Flow sysCONFIG Serial Slave Clocking sysCONFIG POR, Initialization and Wake Up sysCONFIG SPI Port 3-24 Lattice Semiconductor DC and Switching Characteristics LatticeECP/EC Family Data Sheet LatticeECP/EC sysCONFIG Port Timing Specifications (Continued) Over Recommended Operating Conditions Parameter tSOE tCSPID fMAXSPI tSUSPI tHSPI Timing v.G 0.30 Description CSSPIN Active Setup Time CSSPIN Low to First Clock Edge Setup Time Max Frequency for SPI SOSPI Data Setup Time Before CCLK SOSPI Data Hold Time After CCLK Min. 300 300+3cyc — 7 1 Typ. Max. — 600+6cyc 25 — — Units ns ns MHz ns ns Master Clock Clock Mode 2.5MHz 5 MHz 10 MHz 15 MHz 20 MHz 25 MHz 30 MHz 35 MHz 40 MHz 45 MHz 50 MHz 55 MHz 60 MHz Duty Cycle Timing v.G 0.30 Min. 1.75 3.78 7 10.5 14 18.2 21 23.8 28.7 31.5 35.7 38.5 42 40 Typ. 2.5 5.4 10 15 20 26 30 34 41 45 51 55 60 — Max. 3.25 7.02 13 19.5 26 33.8 39 44.2 53.3 58.5 66.3 71.5 78 60 Units MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz % 3-25 Lattice Semiconductor Figure 3-12. sysCONFIG Parallel Port Read Cycle tBSCL DC and Switching Characteristics LatticeECP/EC Family Data Sheet tBSCYC tBSCH CCLK 1 t SUCS tHCS CS1N CSN tSUWD t HWD WRITEN tDCB BUSY t CORD D[0:7] Byte 0 Byte 1 Byte 2 Byte n 1. In Master Parallel Mode the FPGA provides CCLK. In Slave Parallel Mode the external device provides CCLK. Figure 3-13. sysCONFIG Parallel Port Write Cycle tBSCL tBSCYC tBSCH CCLK 1 t SUCS tHCS CS1N CSN t SUWD t HWD WRITEN tDCB BUSY tSUCBDI t HCBDI Byte 0 Byte 1 Byte 2 Byte n D[0:7] 1. In Master Parallel Mode the FPGA provides CCLK. In Slave Parallel Mode the external device provides CCLK. 3-26 Lattice Semiconductor Figure 3-14. sysCONFIG Master Serial Port Timing CCLK (output) tSUMCDI DC and Switching Characteristics LatticeECP/EC Family Data Sheet t HMCDI DIN t CODO DOUT Figure 3-15. sysCONFIG Slave Serial Port Timing tSSCL tSSCH CCLK (input) t SUSCDI tHSCDI DIN t CODO DOUT Figure 3-16. Power-On-Reset (POR) Timing VCC/VCCAUX 1 tICFG INITN DONE t VMC CCLK 2 t SUCFG tHCFG Valid CFG[2:0] 3 1. Time taken from VCC or VCCAUX, whichever is the last to reach its VMIN. 2. Device is in a Master Mode. 3. The CFG pins are normally static (hard wired). 3-27 Lattice Semiconductor Figure 3-17. Configuration from PROGRAMN Timing t PRGMRJ DC and Switching Characteristics LatticeECP/EC Family Data Sheet PROGRAMN t DPPINIT tDINIT INITN tDINITD DONE CCLK tSUCFG tHCFG Valid CFG[2:0] tIODISS USER I/O 1. The CFG pins are normally static (hard wired) Figure 3-18. Wake-Up Timing PROGRAMN INITN DONE Wake-Up tMWC CCLK tIOENSS USER I/O Figure 3-19. sysCONFIG SPI Port Sequence Capture CFGx tICFG Capture OPCODE Clock 127 Clock 128 VCC PROGRAMN tPRGM tDINITD DONE tDPPINIT tDINIT tCSSPI tCFGX tCSCCLK tSOE 0 1 2 3 4 5 6 7 INITN CSSPIN CCLK SISPI/BUSY D7/SPID0 tCSPID tSOCDO D7 D6 D5 D4 D3 D2 D1 D0 0 XXX Valid Bitstream 3-28 Lattice Semiconductor DC and Switching Characteristics LatticeECP/EC Family Data Sheet JTAG Port Timing Specifications Over Recommended Operating Conditions Symbol fMAX tBTCP tBTCPH tBTCPL tBTS tBTH tBTRF tBTCO tBTCODIS tBTCOEN tBTCRS tBTCRH tBUTCO tBTUODIS tBTUPOEN Timing v.G 0.30 Parameter TCK clock frequency TCK [BSCAN] clock pulse width TCK [BSCAN] clock pulse width high TCK [BSCAN] clock pulse width low TCK [BSCAN] setup time TCK [BSCAN] hold time TCK [BSCAN] rise/fall time TAP controller falling edge of clock to valid output TAP controller falling edge of clock to valid disable TAP controller falling edge of clock to valid enable BSCAN test capture register setup time BSCAN test capture register hold time BSCAN test update register, falling edge of clock to valid output BSCAN test update register, falling edge of clock to valid disable BSCAN test update register, falling edge of clock to valid enable Min — 40 20 20 8 10 50 — — — 8 25 — — — Max 25 — — — — — — 10 10 10 — — 25 25 25 Units MHz ns ns ns ns ns mV/ns ns ns ns ns ns ns ns ns Figure 3-20. JTAG Port Timing Waveforms TMS TDI tBTS tBTCPH TCK tBTCPL tBTH tBTCP tBTCOEN TDO Valid Data tBTCO Valid Data tBTCODIS tBTCRS Data to be captured from I/O tBTUPOEN Data to be driven out to I/O tBTCRH Data Captured tBUTCO Valid Data tBTUODIS Valid Data 3-29 Lattice Semiconductor DC and Switching Characteristics LatticeECP/EC Family Data Sheet Switching Test Conditions Figure 3-21 shows the output test load that is used for AC testing. The specific values for resistance, capacitance, voltage, and other test conditions are shown in Table 3-6. Figure 3-21. Output Test Load, LVTTL and LVCMOS Standards VT R1 DUT CL* Test Point *CL Includes Test Fixture and Probe Capacitance Table 3-6. Test Fixture Required Components, Non-Terminated Interfaces Test Condition R1 CL Timing Ref. LVCMOS 3.3 = 1.5V LVCMOS 2.5 = VCCIO/2 LVTTL and other LVCMOS settings (L -> H, H -> L) VT — — — — — VOL VOH VOL VOH ∞ 0pF LVCMOS 1.8 = VCCIO/2 LVCMOS 1.5 = VCCIO/2 LVCMOS 1.2 = VCCIO/2 LVCMOS 2.5 I/O (Z -> H) LVCMOS 2.5 I/O (Z -> L) LVCMOS 2.5 I/O (H -> Z) LVCMOS 2.5 I/O (L -> Z) 188Ω 0pF VCCIO/2 VCCIO/2 VOH - 0.15 VOL + 0.15 Note: Output test conditions for all other interfaces are determined by the respective standards. 3-30 LatticeECP/EC Family Data Sheet Pinout Information November 2007 Data Sheet Signal Descriptions Signal Name General Purpose [Edge] indicates the edge of the device on which the pad is located. Valid edge designations are L (Left), B (Bottom), R (Right), T (Top). [Row/Column Number] indicates the PFU row or the column of the device on which the PIC exists. When Edge is T (Top) or (Bottom), only need to specify Row Number. When Edge is L (Left) or R (Right), only need to specify Column Number. P[Edge] [Row/Column Number*]_[A/B] I/O [A/B] indicates the PIO within the PIC to which the pad is connected. Some of these user-programmable pins are shared with special function pins. These pin when not used as special purpose pins can be programmed as I/Os for user logic. During configuration the user-programmable I/Os are tri-stated with an internal pull-up resistor enabled. If any pin is not used (or not bonded to a package pin), it is also tri-stated with an internal pull-up resistor enabled after configuration. GSRN NC GND VCC VCCAUX VCCIOx VREF1_x, VREF2_x XRES VCCPLL I — — — — — — — — Global RESET signal (active low). Any I/O pin can be GSRN. No connect. Ground. Dedicated pins. Power supply pins for core logic. Dedicated pins. Auxiliary power supply pin. It powers all the differential and referenced input buffers. Dedicated pins. Power supply pins for I/O bank x. Dedicated pins. Reference supply pins for I/O bank x. Pre-determined pins in each bank are assigned as VREF inputs. When not used, they may be used as I/O pins. 10K ohm +/-1% resistor must be connected between this pad and ground. Power supply pin for PLL. Applicable to ECP/EC33 device. Reference clock (PLL) input pads: ULM, LLM, URM, LRM, num = row from center, T = true and C = complement, index A,B,C...at each side. Optional feedback (PLL) input pads: ULM, LLM, URM, LRM, num = row from center, T = true and C = complement, index A,B,C...at each side. Primary Clock pads, T = true and C = complement, n per side, indexed by bank and 0,1,2,3 within bank. DQS input pads: T (Top), R (Right), B (Bottom), L (Left), DQS, num = ball function number. Any pad can be configured to be output. Test Mode Select input, used to control the 1149.1 state machine. Pull-up is enabled during configuration. Test Clock input pin, used to clock the 1149.1 state machine. No pull-up enabled. I/O Description PLL and Clock Functions (Used as user programmable I/O pins when not in use for PLL or clock pins) [LOC][num]_PLL[T, C]_IN_A [LOC][num]_PLL[T, C]_FB_A PCLK[T, C]_[n:0]_[3:0] [LOC]DQS[num] Test and Programming (Dedicated pins) TMS TCK I I I I I I © 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 4-1 Pinout Information_02.5 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet Signal Descriptions (Cont.) Signal Name I/O Description Test Data in pin. Used to load data into device using 1149.1 state machine. After power-up, this TAP port can be activated for configuration by sending appropriate command. (Note: once a configuration port is selected it is locked. Another configuration port cannot be selected until the power-up sequence). Pull-up is enabled during configuration. Output pin. Test Data out pin used to shift data out of device using 1149.1. VCCJ - The power supply pin for JTAG Test Access Port. Mode pins used to specify configuration modes values latched on rising edge of INITN. During configuration, a pull-up is enabled. These are dedicated pins. Open Drain pin. Indicates the FPGA is ready to be configured. During configuration, a pull-up is enabled. It is a dedicated pin. Initiates configuration sequence when asserted low. This pin always has an active pull-up. This is a dedicated pin. Open Drain pin. Indicates that the configuration sequence is complete, and the startup sequence is in progress. This is a dedicated pin. TDI I TDO VCCJ O — Configuration Pads (used during sysCONFIG) CFG[2:0] INITN PROGRAMN DONE CCLK BUSY/SISPI CSN CS1N WRITEN D[7:0]/SPID[0:7] DOUT/CSON DI/CSSPIN I I/O I I/O I/O Configuration Clock for configuring an FPGA in sysCONFIG mode. I/O Read control command in SPI3 or SPIX mode. I I I sysCONFIG chip select (Active low). During configuration, a pull-up is enabled. sysCONFIG chip select (Active low). During configuration, a pull-up is enabled. Write Data on Parallel port (Active low). Output for serial configuration data (rising edge of CCLK) when using sysCONFIG port. I/O sysCONFIG Port Data I/O. O Input for serial configuration data (clocked with CCLK) when using sysCONI/O FIG port. During configuration, a pull-up is enabled. Output when used in SPI/SPIX modes. 4-2 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet PICs and DDR Data (DQ) Pins Associated with the DDR Strobe (DQS) Pin PICs Associated with DQS Strobe P[Edge] [n-4] P[Edge] [n-3] P[Edge] [n-2] P[Edge] [n-1] P[Edge] [n] P[Edge] [n+1] P[Edge] [n+2] P[Edge] [n+3] PIO Within PIC A B A B A B A B A B A B A B A B DDR Strobe (DQS) and Data (DQ) Pins DQ DQ DQ DQ DQ DQ DQ DQ [Edge]DQSn DQ DQ DQ DQ DQ DQ DQ Notes: 1. “n” is a Row/Column PIC number 2. The DDR interface is designed for memories that support one DQS strobe per eight bits of data. In some packages, all the potential DDR data (DQ) pins may not be available. 3. PIC numbering definitions are provided in the “Signal Names” column of the Signal Descriptions table. 4-3 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet Pin Information Summary LFEC1 Pin Type Single Ended User I/O Differential Pair User I/O Configuration TAP Dedicated (total without supplies) VCC VCCAUX VCCPLL Bank0 Bank1 Bank2 VCCIO Bank3 Bank4 Bank5 Bank6 Bank7 GND, GND0-GND7 NC Bank 0 Bank 1 Single Ended/ Differential I/O Pair per Bank Bank 2 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7 VCCJ Dedicated Muxed LFEC3 LFECP6/EC6 LFECP/EC10 100- 144- 208- 100- 144- 208- 256- 144- 208- 256- 484- 208- 256- 484TQFP TQFP PQFP TQFP TQFP PQFP fpBGA TQFP PQFP fpBGA fpBGA PQFP fpBGA fpBGA 67 29 13 48 5 80 2 2 0 1 1 1 1 1 1 1 1 8 0 11/5 11/5 3/1 8/4 12/4 9/4 5/2 8/4 1 97 46 13 48 5 110 3 2 0 2 2 1 2 2 2 2 1 13 2 14/7 13/6 8/4 13/6 14/6 13/6 14/7 8/4 1 112 56 13 48 5 160 3 2 0 2 2 1 2 2 2 2 1 13 51 16/8 16/8 8/4 16/8 16/8 16/8 16/8 8/4 1 67 29 13 48 5 80 2 4 0 1 1 2 1 1 1 1 2 8 0 11/5 11/5 3/1 8/4 12/4 9/4 5/2 8/4 1 97 46 13 48 5 110 3 4 0 2 2 2 2 2 2 2 2 13 2 14/7 13/6 8/4 13/6 14/6 13/6 14/7 8/4 1 145 72 13 48 5 160 3 4 0 3 2 2 2 2 2 2 2 16 9 16/8 14/7 16/8 16/8 16/8 15/7 1 160 80 13 48 5 208 10 4 0 2 2 2 2 2 2 2 2 20 35 16/8 16/8 16/8 16/8 16/8 16/8 1 97 46 13 48 5 110 4 2 0 2 2 1 2 2 2 2 1 14 0 13/6 8/4 13/6 14/6 14/7 8/4 1 147 72 13 48 5 160 4 4 0 3 2 2 2 2 3 2 2 18 4 17/8 14/7 16/8 17/8 16/8 15/7 1 195 97 13 48 5 208 10 2 0 2 2 2 2 2 2 2 2 20 0 18/9 16/8 17/8 224 112 13 48 5 373 20 12 0 4 4 4 4 4 4 4 4 44 139 32/16 16/8 32/16 147 72 13 56 5 160 6 4 0 3 2 2 2 2 3 2 2 20 0 17/8 14/7 16/8 17/8 16/8 15/7 1 195 97 13 56 5 208 10 2 0 2 2 2 2 2 2 2 2 20 0 18/9 16/8 17/8 288 144 13 56 5 373 20 12 0 4 4 4 4 4 4 4 4 44 75 32/16 32/16 32/16 26/13 32/16 14/7 26/13 32/16 32/16 26/13 32/16 48/24 32/16 32/16 32/16 32/16 26/13 32/16 13/6 26/13 32/16 32/16 26/13 32/16 48/24 32/16 32/16 16/8 1 16/8 1 32/16 32/16 16/8 1 32/16 1 Note: During configuration the user-programmable I/Os are tri-stated with an internal pull-up resistor enabled. If any pin is not used (or not bonded to a package pin), it is also tri-stated with an internal pull-up resistor enabled after configuration. 4-4 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet Pin Information Summary (Cont.) LFECP/EC15 Pin Type Single Ended User I/O Differential Pair User I/O Configuration TAP Dedicated (total without supplies) VCC VCCAUX VCCPLL Bank0 Bank1 Bank2 VCCIO Bank3 Bank4 Bank5 Bank6 Bank7 GND, GND0-GND7 NC Bank0 Bank1 Bank2 Single Ended/ Differential I/O Pair per Bank Bank3 Bank4 Bank5 Bank6 Bank7 VCCJ Dedicated Muxed 256-fpBGA 195 97 13 56 5 208 10 2 0 2 2 2 2 2 2 2 2 20 0 32/16 18/9 16/8 32/16 17/8 32/16 32/16 16/8 1 484-fpBGA 352 176 13 56 5 373 20 12 0 4 4 4 4 4 4 4 4 44 11 48/24 48/24 40/20 40/20 48/24 48/24 40/20 40/20 1 LFECP20/EC20 484-fpBGA 360 180 13 56 5 373 20 12 0 4 4 4 4 4 4 4 4 44 3 48/24 48/24 40/20 44/22 48/24 48/24 44/22 40/20 1 672-fpBGA 400 200 13 56 5 509 32 20 0 6 6 6 6 6 6 6 6 63 96 64/32 48/24 40/20 48/24 48/24 64/32 48/24 40/20 1 LFECP/EC33 484-fpBGA 360 180 13 56 5 373 16 12 4 4 4 4 4 4 4 4 4 44 3 48/24 48/24 40/20 44/22 48/24 48/24 44/22 40/20 1 672-fpBGA 496 248 13 56 5 509 28 20 4 6 6 6 6 6 6 6 6 63 0 64/32 64/32 56/28 64/32 64/32 64/32 64/32 56/28 1 Note: During configuration the user-programmable I/Os are tri-stated with an internal pull-up resistor enabled. If any pin is not used (or not bonded to a package pin), it is also tri-stated with an internal pull-up resistor enabled after configuration. 4-5 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet Power Supply and NC Connections Signals VCC 12, 64 100 TQFP 144 TQFP 208 PQFP 256 fpBGA EC1, EC3: 13, 92, 99 EC1, EC3: 26, 128, 135 E12, E5, E8, M12, M5, ECP/EC6: 11, 13, 92, 99 ECP/EC6: 24, 26, 128, M9, F6, F11, L11, L6 135 ECP/EC10: 5, 24, 26, 128, 135, 152 136, 143 EC1: 187, 208 EC3, ECP/EC6, ECP/ EC10: 187, 197, 208 157, 176 EC1: 155 EC3, ECP/EC6, ECP/ EC10: 145, 155 106, 120 85, 104 EC1: 53, 74 EC2, ECP/EC6, ECP/ EC10: 53, 64, 74 37, 51 EC1: 2 EC3, ECP/EC6, ECP/ EC10: 2, 13 32 EC1: 84, 177 EC3, ECP/EC6, ECP/ EC10: 22, 84, 136, 177 — EC1: 1, 28, 41, 52, 82, 93, 105, 116, 132, 134, 156, 168, 179 EC3: 1, 28, 41, 52, 72, 82, 93, 105, 116, 132, 134, 138, 156, 168, 179, 189 ECP/EC6: 1, 18, 25, 28, 41, 52, 72, 82, 93, 105, 116, 132, 134, 138, 156, 168, 179, 189 ECP/EC10: 1, 6, 18, 25, 28, 41, 52, 72, 82, 93, 105, 116, 132, 134, 138, 151, 156, 168, 179, 189 EC1: 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 18, 22, 24, 25, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 72, 103, 136, 138, 144, 145, 146, 147, 148, 149, 150, 151, 152, 158, 189, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207 EC3: 5, 6, 18, 24, 25, 103, 151, 152, 158 ECP/EC6: 5, 6, 151, 152 ECP/EC10: None F7, F8 VCCIO0 100 VCCIO1 VCCIO2 86 73 110, 125 108 F9, F10 G11, H11 VCCIO3 VCCIO4 VCCIO5 56 38 26 73, 84 55, 71 38, 44 J11, K11 L9, L10 L7, L8 VCCIO6 VCCIO7 24 2 24, 36 1 J6, K6 G6, H6 VCCJ VCCAUX 18 37, 87 19 54, 126 L4 B15, R2 VCCPLL GND, GND0-GND7 — — — A1, A16, G10, G7, G8, G9, H10, H7, H8, H9, J10, J7, J8, J9, K10, K7, K8, K9, T1, T16 1, 14, 25, 35, 51, 68, 74, EC1, EC3: 15, 28, 37, 89 52, 63, 72, 80, 96, 98, 109, 117, 128, 144 ECP/EC6: 12, 15, 28, 37, 52, 63, 72, 80, 96, 98, 109, 117, 128, 144 NC — EC1, EC3: 11, 12 ECP6/EC6: None EC3: G5, H5, F2, F1, H4, H3, G2, G1, J4, J3, J5, K5, H2, H1, J2, J1, R12, H16, H15, G16, G15, K12, J12, J14, J15, F16, F15, J13, H13, H14, G14, E16, E15, B13, C13 ECP/EC10: None ECP/EC15: None 4-6 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet Power Supply and NC Connections (Cont.) Signals VCC 484 fpBGA 672 fpBGA J16, J7, K16, K17, K6, K7, L17, L6, M17, M6, N16, H10, H11, H16, H17, H18, H19, H8, H9, J18, J9, N17, N6, N7, P16, P7, J6, J17, P6, P17 K8, L19, M19, N7, R20, R7, T19, V18, V8, V9, W10, W11, W16, W17, W18, W19, W8, W9, K19, L8, U19, U8 G11, H10, H11, H9 G12, H12, H13, H14 J15, K15, L15, L16 M15, M16, N15, P15 R12, R13, R14, T12 R10, R11, R9, T11 M7, M8, N8, P8 J8, K8, L7, L8 U2 G15, G16, G7, G8, H16, H7, R16, R7, T15, T16, T7, T8 ECP/EC20: None ECP/EC33: J6, J17, P6, P17 A1, A22, AB1, AB22, H15, H8, J10, J11, J12, J13, J14, J9, K10, K11, K12, K13, K14, K9, L10, L11, L12, L13, L14, L9, M10, M11, M12, M13, M14, M9, N10, N11, N12, N13, N14, N9, P10, P11, P12, P13, P14, P9, R15, R8 H12, H13, J10, J11, J12, J13 H14, H15, J14, J15, J16, J17 K17, K18, L18, M18, N18, N19 P18, P19, R18, R19, T18, U18 V14, V15, V16, V17, W14, W15 V10, V11, V12, V13, W12, W13 P8, P9, R8, R9, T9, U9 K9, L9, M8, M9, N8, N9 U6 G13, H20, H7, J19, J8, K7, L20, M20, M7, N20, P20, P7, T20, T7, T8, V19, V7, W20, Y13, Y7 ECP/EC20: None ECP/EC33: K19, L8, U19, U8 K10, K11, K12, K13, K14, K15, K16, L10, L11, L12, L13, L14, L15, L16, L17, M10, M11, M12, M13, M14, M15, M16, M17, N10, N11, N12, N13, N14, N15, N16, N17, P10, P11, P12, P13, P14, P15, P16, P17, R10, R11, R12, R13, R14, R15, R16, R17, T10, T11, T12, T13, T14, T15, T16, T17, U10, U11, U12, U13, U14, U15, U16, U17 ECP/EC20: E5, D5, F4, F5, C3, D3, C2, B2, H6, J7, G5, H5, H3, J3, H2, J2, AA2, AA3, W5, Y5, Y6, W7, AA4, AB3, AC2, AC3, AA5, AB5, AD3, AD2, AE1, AD1, AD19, AD20, AC19, AB19, AD21, AC20, AF25, AE25, AB21, AB20, AE24, AD23, AD22, AC21, AC22, AB22, AD24, AD25, AE26, AD26, Y20, Y19, AA23, AA22, AB23, AB24, Y21, AA21, Y23, Y22, AA24, Y24, J21, J22, J23, H22, G26, F26, E26, E25, F24, F23, E24, D24, E22, F22, E21, D22, G20, F20, D21, C21, C23, C22, B23, C24, D20, E19, B25, B24, B26, A25, C20, C19 ECP/EC33: None VCCIO0 VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCJ VCCAUX VCCPLL GND, GND0-GND7 NC ECP/EC6: C3, B2, E5, F5, D3, C2, F4, G4, E3, D2, B1, C1, F3, E2, G5, H6, G3, H4, J5, H5, F2, F1, E1, D1, R6, P5, P3, P4, R1, R2, R5, R4, T1, T2, R3, T3, V7, T6, V8, U7, W5, U6, AA3, AB3, Y6, V6, AA5, W6, Y5, Y4, AA4, AB4, W16, U15, V16, U16, Y17, V17, AB20, AA19, Y16, W17, AA20, Y19, Y18, W18, T17, U17, T18, R17, R19, R18, U22, T22, R21, R22, P20, N20, P19, P18, E21, D22, G21, G20, J18, H19, J19, H20, H17, H18, D21, C22, G19, G18, F20, F19, E20, D20, C21, C20, F18, E18, B22, B21, G17, F17, D18, C18, C19, B20, D17, C16, B19, A20, E17, C17, F16, E16, F15, D16, A4, B4, C4, C5, D6, B5, E6, C6, A3, B3, F6, D5, F7, E8, G6, E7, A2, AB2, A21 ECP/EC10: G5, H6, G3, H4, J5, H5, F2, F1, R6, P5, P3, P4, R2, R1, R5, R4, T1, T2, R3, T3, W16, U15, V16, U16, Y17, V17, AB20, AA19, Y16, W17, AA20, Y19, Y18, W18, T17, U17, T18, R17, R19, R18, U22, T22, R21, R22, P20, N20, P19, P18, G21, G20, J18, H19, J19, H20, H17, H18, G17, F17, D18, C18, C19, B20, D17, C16, B19, A20, E17, C17, F16, E16, F15, D16, A2, AB2, A21 ECP/EC15: T1, T2, R3, T3, T18, R17, R19, R18, A2, AB2, A21 ECP/EC20: A2, AB2, A21 ECP/EC33: A2, AB2, A21 4-7 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFEC1, LFEC3 Logic Signal Connections: 100 TQFP LFEC1 Pin Number 1* 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25* 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Pin Function GND0 GND7 VCCIO7 PL2A PL2B PL3A PL3B PL4A PL4B PL5A PL5B XRES VCC TCK GND TDI TMS TDO VCCJ PL7A PL7B PL8A PL8B PL14A VCCIO6 GND5 GND6 VCCIO5 PB2A PB2B PB3A PB3B PB6A PB8A PB8B PB9A GND5 PB9B VCCAUX VCCIO4 PB10A PB10B Bank 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 5 4 4 4 T C WRITEN CS1N C PCLKC5_0 T C T T C T C BDQS6 VREF2_5 VREF1_5 PCLKT5_0 T C T C LLM0_PLLT_IN_A LLM0_PLLC_IN_A LLM0_PLLT_FB_A LLM0_PLLC_FB_A VREF1_6 T C T C T C T C PCLKT7_0 PCLKC7_0 VREF2_7 VREF1_7 LVDS Dual Function Pin Function GND0 GND7 VCCIO7 PL2A PL2B PL7A PL7B PL8A PL8B PL9A PL9B XRES VCC TCK GND TDI TMS TDO VCCJ PL11A PL11B PL12A PL12B PL18A VCCIO6 GND5 GND6 VCCIO5 PB10A PB10B PB11A PB11B PB14A PB16A PB16B PB17A GND5 PB17B VCCAUX VCCIO4 PB18A PB18B Bank 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 5 4 4 4 T C WRITEN CS1N C PCLKC5_0 T C T T C T C BDQS14 VREF2_5 VREF1_5 PCLKT5_0 T C T C LUM0_PLLT_IN_A LUM0_PLLC_IN_A LUM0_PLLT_FB_A LUM0_PLLC_FB_A VREF1_6 T C T C T C T C PCLKT7_0 PCLKC7_0 VREF2_7 VREF1_7 LFEC3 LVDS Dual Function 4-8 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFEC1, LFEC3 Logic Signal Connections: 100 TQFP (Cont.) LFEC1 Pin Number 41 42 43 44 45 46 47 48 49 50 51* 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 Pin Function PB11A PB11B PB12B PB13A PB13B PB14A PB14B PB15B PB16B PB17B GND3 GND4 PR10B PR10A PR9B PR9A VCCIO3 PR8B PR8A PR7B PR7A CFG2 CFG1 CFG0 VCC PROGRAMN CCLK INITN GND DONE PR5B PR5A PR2B VCCIO2 GND2 PT17B PT17A PT14B PT14A PT13A PT12B PT12A Bank 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 1 1 1 1 1 1 1 C T C T C T TDQS14 C T PCLKC2_0 PCLKT2_0 VREF1_2 C T C T DI/CSSPIN DOUT/CSON BUSY/SISPI D7/SPID0 C T C T RLM0_PLLC_FB_A RLM0_PLLT_FB_A RLM0_PLLC_IN_A RLM0_PLLT_IN_A T C T C LVDS T C Dual Function VREF1_4 CSN D0/SPID7 D2/SPID5 D1/SPID6 BDQS14 D3/SPID4 D4/SPID3 D5/SPID2 D6/SPID1 Pin Function PB19A PB19B PB20B PB21A PB21B PB22A PB22B PB23B PB24B PB25B GND3 GND4 PR14B PR14A PR13B PR13A VCCIO3 PR12B PR12A PR11B PR11A CFG2 CFG1 CFG0 VCC PROGRAMN CCLK INITN GND DONE PR9B PR9A PR2B VCCIO2 GND2 PT25B PT25A PT22B PT22A PT21A PT20B PT20A Bank 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 1 1 1 1 1 1 1 C T C T C T TDQS22 C T PCLKC2_0 PCLKT2_0 VREF1_2 C T C T DI/CSSPIN DOUT/CSON BUSY/SISPI D7/SPID0 C T C T RLM0_PLLC_FB_A RLM0_PLLT_FB_A RLM0_PLLC_IN_A RLM0_PLLT_IN_A T C T C LFEC3 LVDS T C Dual Function VREF1_4 CSN D0/SPID7 D2/SPID5 D1/SPID6 BDQS22 D3/SPID4 D4/SPID3 D5/SPID2 D6/SPID1 4-9 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFEC1, LFEC3 Logic Signal Connections: 100 TQFP (Cont.) LFEC1 Pin Number 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Pin Function PT11B PT11A PT10B PT10A VCCIO1 VCCAUX PT9B GND0 PT9A PT8B PT8A PT7B PT6B PT6A PT4B PT4A PT2B PT2A VCCIO0 Bank 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 C T C T C T TDQS6 T C T PCLKT0_0 VREF1_0 VREF2_0 C PCLKC0_0 LVDS C T C T Dual Function VREF2_1 VREF1_1 Pin Function PT19B PT19A PT18B PT18A VCCIO1 VCCAUX PT17B GND0 PT17A PT16B PT16A PT15B PT14B PT14A PT12B PT12A PT10B PT10A VCCIO0 Bank 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 C T C T C T TDQS14 T C T PCLKT0_0 VREF1_0 VREF2_0 C PCLKC0_0 LFEC3 LVDS C T C T Dual Function VREF2_1 VREF1_1 *Double bonded to the pin. 4-10 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFEC1, LFEC3, LFECP/EC6 Logic Signal Connections: 144 TQFP LFEC1 Pin Number Pin Function Bank LVDS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37* 38 39 40 41 42 43 44 45 46 47 48 49 VCCIO7 PL2A PL2B PL3A PL3B PL4A PL4B PL5A PL5B XRES NC NC VCC TCK GND TDI TMS TDO VCCJ PL7A PL7B PL8A PL8B VCCIO6 PL9A PL9B PL10A GND6 PL10B PL11A PL11B PL12A PL12B PL14A PL14B VCCIO6 GND5 GND6 VCCIO5 PB2A PB2B PB3A PB3B PB5B VCCIO5 PB6A PB6B PB7A PB7B PB8A 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 5 5 T C T C T VREF2_5 BDQS6 T C T C C T C T C T C VREF1_6 VREF2_6 LDQS11 T C T T C T C LLM0_PLLT_IN_A LLM0_PLLC_IN_A LLM0_PLLT_FB_A LLM0_PLLC_FB_A T C T C T C T C PCLKT7_0 PCLKC7_0 VREF2_7 VREF1_7 LFEC3 Dual Function Pin Function Bank LVDS VCCIO7 PL2A PL2B PL7A PL7B PL8A PL8B PL9A PL9B XRES NC NC VCC TCK GND TDI TMS TDO VCCJ PL11A PL11B PL12A PL12B VCCIO6 PL13A PL13B PL14A GND6 PL14B PL15A PL15B PL16A PL16B PL18A PL18B VCCIO6 GND5 GND6 VCCIO5 PB10A PB10B PB11A PB11B PB13B VCCIO5 PB14A PB14B PB15A PB15B PB16A 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 5 5 T C T C T VREF2_5 BDQS14 T C T C C T C T C T C VREF1_6 VREF2_6 LDQS15 T C T T C T C LLM0_PLLT_IN_A LLM0_PLLC_IN_A LLM0_PLLT_FB_A LLM0_PLLC_FB_A T C T C T C T C PCLKT7_0 PCLKC7_0 VREF2_7 VREF1_7 Dual Function LFECP6/EC6 Pin Function Bank LVDS VCCIO7 PL2A PL2B PL7A PL7B PL8A PL8B PL9A PL9B XRES VCC GND VCC TCK GND TDI TMS TDO VCCJ PL20A PL20B PL21A PL21B VCCIO6 PL22A PL22B PL23A GND6 PL23B PL24A PL24B PL25A PL25B PL27A PL27B VCCIO6 GND5 GND6 VCCIO5 PB10A PB10B PB11A PB11B PB13B VCCIO5 PB14A PB14B PB15A PB15B PB16A 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 5 5 T C T C T VREF2_5 BDQS14 T C T C C T C T C T C VREF1_6 VREF2_6 LDQS24 T C T T C T C LLM0_PLLT_IN_A LLM0_PLLC_IN_A LLM0_PLLT_FB_A LLM0_PLLC_FB_A T C T C T C T C PCLKT7_0 PCLKC7_0 VREF2_7 VREF1_7 Dual Function 4-11 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFEC1, LFEC3, LFECP/EC6 Logic Signal Connections: 144 TQFP (Cont.) LFEC1 Pin Number Pin Function Bank LVDS 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72* 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 PB8B PB9A GND5 PB9B VCCAUX VCCIO4 PB10A PB10B PB11A PB11B PB12A PB12B PB13A GND4 PB13B PB14A PB14B PB15A PB15B PB16B PB17B VCCIO4 GND3 GND4 VCCIO3 PR14A PR12B PR12A PR11B PR11A PR10B GND3 PR10A PR9B PR9A VCCIO3 PR8B PR8A PR7B PR7A CFG2 CFG1 CFG0 VCC PROGRAMN CCLK INITN GND DONE GND 5 5 5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 C T C T DI/CSSPIN DOUT/CSON BUSY/SISPI D7/SPID0 T C T RLM0_PLLT_FB_A RLM0_PLLC_IN_A RLM0_PLLT_IN_A C T C T C RDQS11 RLM0_PLLC_FB_A VREF1_3 C T C T C D4/SPID3 D5/SPID2 D6/SPID1 D1/SPID6 BDQS14 D3/SPID4 T C T C T C T WRITEN CS1N VREF1_4 CSN VREF2_4 D0/SPID7 D2/SPID5 C PCLKC5_0 C T LFEC3 Dual Function VREF1_5 PCLKT5_0 Pin Function Bank LVDS PB16B PB17A GND5 PB17B VCCAUX VCCIO4 PB18A PB18B PB19A PB19B PB20A PB20B PB21A GND4 PB21B PB22A PB22B PB23A PB23B PB24B PB25B VCCIO4 GND3 GND4 VCCIO3 PR18A PR16B PR16A PR15B PR15A PR14B GND3 PR14A PR13B PR13A VCCIO3 PR12B PR12A PR11B PR11A CFG2 CFG1 CFG0 VCC PROGRAMN CCLK INITN GND DONE GND 5 5 5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 C T C T DI/CSSPIN DOUT/CSON BUSY/SISPI D7/SPID0 T C T RLM0_PLLT_FB_A RLM0_PLLC_IN_A RLM0_PLLT_IN_A C T C T C RDQS15 RLM0_PLLC_FB_A VREF1_3 C T C T C D4/SPID3 D5/SPID2 D6/SPID1 D1/SPID6 BDQS22 D3/SPID4 T C T C T C T WRITEN CS1N VREF1_4 CSN VREF2_4 D0/SPID7 D2/SPID5 C PCLKC5_0 C T Dual Function VREF1_5 PCLKT5_0 LFECP6/EC6 Pin Function Bank LVDS PB16B PB17A GND5 PB17B VCCAUX VCCIO4 PB18A PB18B PB19A PB19B PB20A PB20B PB21A GND4 PB21B PB22A PB22B PB23A PB23B PB24B PB25B VCCIO4 GND3 GND4 VCCIO3 PR27A PR25B PR25A PR24B PR24A PR23B GND3 PR23A PR22B PR22A VCCIO3 PR21B PR21A PR20B PR20A CFG2 CFG1 CFG0 VCC PROGRAMN CCLK INITN GND DONE GND 5 5 5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 C T C T DI/CSSPIN DOUT/CSON BUSY/SISPI D7/SPID0 T C T RLM0_PLLT_FB_A RLM0_PLLC_IN_A RLM0_PLLT_IN_A C T C T C RDQS24 RLM0_PLLC_FB_A VREF1_3 C T C T C D4/SPID3 D5/SPID2 D6/SPID1 D1/SPID6 BDQS22 D3/SPID4 T C T C T C T WRITEN CS1N VREF1_4 CSN VREF2_4 D0/SPID7 D2/SPID5 C PCLKC5_0 C T Dual Function VREF1_5 PCLKT5_0 4-12 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFEC1, LFEC3, LFECP/EC6 Logic Signal Connections: 144 TQFP (Cont.) LFEC1 Pin Number Pin Function Bank LVDS 99 100 101 102 103 104 105 106 107 108 109* 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144* VCC PR5B PR5A PR4B PR4A PR3B PR3A PR2B PR2A VCCIO2 GND1 GND2 VCCIO1 PT17B PT17A PT15A PT14B PT14A PT13B GND1 PT13A PT12B PT12A PT11B PT11A PT10B PT10A VCCIO1 VCCAUX PT9B GND0 PT9A PT8B PT8A PT7B PT7A PT6B PT6A VCCIO0 PT5B PT5A PT4B PT4A PT2B PT2A VCCIO0 GND0 GND7 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C T C T C T T C T C T C T TDQS6 PCLKT0_0 VREF1_0 VREF2_0 C PCLKC0_0 T C T C T C T VREF2_1 VREF1_1 C T C TDQS14 C T C T C T C T C T VREF1_2 VREF2_2 PCLKC2_0 PCLKT2_0 LFEC3 Dual Function Pin Function Bank LVDS VCC PR9B PR9A PR8B PR8A PR7B PR7A PR2B PR2A VCCIO2 GND1 GND2 VCCIO1 PT25B PT25A PT23A PT22B PT22A PT21B GND1 PT21A PT20B PT20A PT19B PT19A PT18B PT18A VCCIO1 VCCAUX PT17B GND0 PT17A PT16B PT16A PT15B PT15A PT14B PT14A VCCIO0 PT13B PT13A PT12B PT12A PT10B PT10A VCCIO0 GND0 GND7 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C T C T C T T C T C T C T TDQS14 PCLKT0_0 VREF1_0 VREF2_0 C PCLKC0_0 T C T C T C T VREF2_1 VREF1_1 C T C TDQS22 C T C T C T C T C T VREF1_2 VREF2_2 PCLKC2_0 PCLKT2_0 Dual Function LFECP6/EC6 Pin Function Bank LVDS VCC PR9B PR9A PR8B PR8A PR7B PR7A PR2B PR2A VCCIO2 GND1 GND2 VCCIO1 PT25B PT25A PT23A PT22B PT22A PT21B GND1 PT21A PT20B PT20A PT19B PT19A PT18B PT18A VCCIO1 VCCAUX PT17B GND0 PT17A PT16B PT16A PT15B PT15A PT14B PT14A VCCIO0 PT13B PT13A PT12B PT12A PT10B PT10A VCCIO0 GND0 GND7 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C T C T C T T C T C T C T TDQS14 PCLKT0_0 VREF1_0 VREF2_0 C PCLKC0_0 T C T C T C T VREF2_1 VREF1_1 C T C TDQS22 C T C T C T C T C T VREF1_2 VREF2_2 PCLKC2_0 PCLKT2_0 Dual Function *Double bonded to the pin. 4-13 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFEC1, LFEC3 Logic Signal Connections: 208 PQFP LFEC1 Pin Number 1* 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Pin Function GND0 GND7 VCCIO7 PL2A PL2B NC NC NC NC NC NC NC NC NC NC PL3A PL3B PL4A NC PL4B PL5A PL5B NC XRES NC NC VCC TCK GND TDI TMS TDO VCCJ PL7A PL7B PL8A PL8B VCCIO6 PL9A PL9B PL10A GND6 PL10B Bank 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 C T C T T C T C LLM0_PLLT_IN_A LLM0_PLLC_IN_A LLM0_PLLT_FB_A LLM0_PLLC_FB_A C T C PCLKT7_0 PCLKC7_0 T C T T C VREF2_7 VREF1_7 LVDS Dual Function Pin Function GND0 GND7 VCCIO7 PL2A PL2B NC NC PL3B PL4A PL4B PL5A PL5B PL6A VCCIO7 PL6B PL7A PL7B PL8A NC PL8B PL9A PL9B VCCAUX XRES NC NC VCC TCK GND TDI TMS TDO VCCJ PL11A PL11B PL12A PL12B VCCIO6 PL13A PL13B PL14A GND6 PL14B LFEC3 Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 C T C T T C T C LLM0_PLLT_IN_A LLM0_PLLC_IN_A LLM0_PLLT_FB_A LLM0_PLLC_FB_A C T C PCLKT7_0 PCLKC7_0 C T C T T C T C T LDQS6 T C VREF2_7 VREF1_7 LVDS Dual Function 4-14 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFEC1, LFEC3 Logic Signal Connections: 208 PQFP (Cont.) LFEC1 Pin Number 43 44 45 46 47 48 49 50 51 52* 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Pin Function PL11A PL11B PL12A PL12B PL13A PL13B PL14A PL14B VCCIO6 GND5 GND6 VCCIO5 NC NC NC NC NC NC NC NC NC NC NC PB2A PB2B PB3A PB3B PB4A PB4B PB5A NC PB5B VCCIO5 PB6A PB6B PB7A PB7B PB8A PB8B PB9A GND5 PB9B VCCAUX Bank 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 C PCLKC5_0 T C T C T C T VREF2_5 VREF1_5 PCLKT5_0 BDQS6 C T C T C T C T LVDS T C T C T C T C VREF1_6 VREF2_6 Dual Function LDQS11 Pin Function PL15A PL15B PL16A PL16B PL17A PL17B PL18A PL18B VCCIO6 GND5 GND6 VCCIO5 PB2A PB2B PB3A PB3B PB4A PB4B PB5A PB5B PB6A PB6B VCCIO5 PB10A PB10B PB11A PB11B PB12A PB12B PB13A GND5 PB13B VCCIO5 PB14A PB14B PB15A PB15B PB16A PB16B PB17A GND5 PB17B VCCAUX 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 C PCLKC5_0 T C T C T C T VREF2_5 VREF1_5 PCLKT5_0 BDQS14 C T C T C T C T T C T C T C T C T C BDQS6 LFEC3 Bank LVDS T C T C T C T C VREF1_6 VREF2_6 Dual Function LDQS15 4-15 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFEC1, LFEC3 Logic Signal Connections: 208 PQFP (Cont.) LFEC1 Pin Number 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105* 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 Pin Function VCCIO4 PB10A PB10B PB11A PB11B PB12A PB12B PB13A GND4 PB13B PB14A PB14B PB15A PB15B PB16A PB16B PB17A PB17B NC VCCIO4 GND3 GND4 VCCIO3 PR14B PR14A PR13B PR13A PR12B PR12A PR11B PR11A PR10B GND3 PR10A PR9B PR9A VCCIO3 PR8B PR8A PR7B PR7A CFG2 CFG1 Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 C T C T DI/CSSPIN DOUT/CSON BUSY/SISPI D7/SPID0 T C T RLM0_PLLT_FB_A RLM0_PLLC_IN_A RLM0_PLLT_IN_A C T C T C T C T C RDQS11 RLM0_PLLC_FB_A VREF2_3 VREF1_3 C T C T C T C T C D6/SPID1 D5/SPID2 D4/SPID3 D1/SPID6 BDQS14 D3/SPID4 T C T C T C T WRITEN CS1N VREF1_4 CSN VREF2_4 D0/SPID7 D2/SPID5 LVDS Dual Function Pin Function VCCIO4 PB18A PB18B PB19A PB19B PB20A PB20B PB21A GND4 PB21B PB22A PB22B PB23A PB23B PB24A PB24B PB25A PB25B NC VCCIO4 GND3 GND4 VCCIO3 PR18B PR18A PR17B PR17A PR16B PR16A PR15B PR15A PR14B GND3 PR14A PR13B PR13A VCCIO3 PR12B PR12A PR11B PR11A CFG2 CFG1 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 C T C T DI/CSSPIN DOUT/CSON BUSY/SISPI D7/SPID0 T C T RLM0_PLLT_FB_A RLM0_PLLC_IN_A RLM0_PLLT_IN_A C T C T C T C T C RDQS15 RLM0_PLLC_FB_A VREF2_3 VREF1_3 C T C T C T C T C D6/SPID1 D5/SPID2 D4/SPID3 D1/SPID6 BDQS22 D3/SPID4 T C T C T C T WRITEN CS1N VREF1_4 CSN VREF2_4 D0/SPID7 D2/SPID5 LFEC3 Bank LVDS Dual Function 4-16 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFEC1, LFEC3 Logic Signal Connections: 208 PQFP (Cont.) LFEC1 Pin Number 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156* 157 158 159 160 161 162 163 164 165 166 167 168 Pin Function CFG0 VCC PROGRAMN CCLK INITN GND DONE GND VCC NC PR5B NC PR5A PR4B PR4A PR3B PR3A NC NC NC NC NC NC NC NC NC PR2B PR2A VCCIO2 GND1 GND2 VCCIO1 NC PT17B PT17A PT16B PT16A PT15B PT15A PT14B PT14A PT13B GND1 Bank 3 3 3 3 3 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 C T C T C T C T C TDQS14 C T VREF1_2 VREF2_2 T C T C T PCLKT2_0 C PCLKC2_0 LVDS Dual Function Pin Function CFG0 VCC PROGRAMN CCLK INITN GND DONE GND VCC VCCAUX PR9B GND2 PR9A PR8B PR8A PR7B PR7A PR6B VCCIO2 PR6A PR5B PR5A PR4B PR4A NC NC PR2B PR2A VCCIO2 GND1 GND2 VCCIO1 NC PT25B PT25A PT24B PT24A PT23B PT23A PT22B PT22A PT21B GND1 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 C T C T C T C T C TDQS22 C T VREF1_2 VREF2_2 T C T C T RDQS6 T C T C T C PCLKT2_0 C PCLKC2_0 LFEC3 Bank LVDS Dual Function 4-17 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFEC1, LFEC3 Logic Signal Connections: 208 PQFP (Cont.) LFEC1 Pin Number 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 Pin Function PT13A PT12B PT12A PT11B PT11A PT10B PT10A VCCIO1 VCCAUX PT9B GND0 PT9A PT8B PT8A PT7B PT7A PT6B PT6A VCCIO0 PT5B NC PT5A PT4B PT4A PT3B PT3A PT2B PT2A NC NC NC NC NC NC NC NC NC NC NC VCCIO0 Bank 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T C T C T C T C T C T C T C T TDQS6 PCLKT0_0 VREF1_0 VREF2_0 C PCLKC0_0 LVDS T C T C T C T VREF2_1 VREF1_1 Dual Function Pin Function PT21A PT20B PT20A PT19B PT19A PT18B PT18A VCCIO1 VCCAUX PT17B GND0 PT17A PT16B PT16A PT15B PT15A PT14B PT14A VCCIO0 PT13B GND0 PT13A PT12B PT12A PT11B PT11A PT10B PT10A VCCIO0 PT6B PT6A PT5B PT5A PT4B PT4A PT3B PT3A PT2B PT2A VCCIO0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C T C T C T C T C T TDQS6 T C T C T C T C T C T C T C T TDQS14 PCLKT0_0 VREF1_0 VREF2_0 C PCLKC0_0 LFEC3 Bank LVDS T C T C T C T VREF2_1 VREF1_1 Dual Function * Double bonded to the pin. 4-18 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFECP/EC6, LFECP/EC10 Logic Signal Connections: 208 PQFP LFECP6/LFEC6 Pin Number 1* 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Pin Function GND0 GND7 VCCIO7 PL2A PL2B NC NC PL3B PL4A PL4B PL5A PL5B PL6A VCCIO7 PL6B PL7A PL7B PL8A GND7 PL8B PL9A PL9B VCCAUX XRES VCC GND VCC TCK GND TDI TMS TDO VCCJ PL20A PL20B PL21A PL21B VCCIO6 PL22A PL22B PL23A GND6 PL23B Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 C T C T T C T C LLM0_PLLT_IN_A LLM0_PLLC_IN_A LLM0_PLLT_FB_A LLM0_PLLC_FB_A C T C PCLKT7_0 PCLKC7_0 C T C T T C T C T LDQS6 T C VREF2_7 VREF1_7 LVDS Dual Function Pin Function GND0 GND7 VCCIO7 PL2A PL2B VCC GND PL12B PL13A PL13B PL14A PL14B PL15A VCCIO7 PL15B PL16A PL16B PL17A GND7 PL17B PL18A PL18B VCCAUX XRES VCC GND VCC TCK GND TDI TMS TDO VCCJ PL29A PL29B PL30A PL30B VCCIO6 PL31A PL31B PL32A GND6 PL32B LFECP10/LFEC10 Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 C T C T T C T C LLM0_PLLT_IN_A LLM0_PLLC_IN_A LLM0_PLLT_FB_A LLM0_PLLC_FB_A C T C PCLKT7_0 PCLKC7_0 C T C T T C T C T LDQS15 T C VREF2_7 VREF1_7 LVDS Dual Function 4-19 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFECP/EC6, LFECP/EC10 Logic Signal Connections: 208 PQFP (Cont.) LFECP6/LFEC6 Pin Number 43 44 45 46 47 48 49 50 51 52* 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Pin Function PL24A PL24B PL25A PL25B PL26A PL26B PL27A PL27B VCCIO6 GND5 GND6 VCCIO5 PB2A PB2B PB3A PB3B PB4A PB4B PB5A PB5B PB6A PB6B VCCIO5 PB10A PB10B PB11A PB11B PB12A PB12B PB13A GND5 PB13B VCCIO5 PB14A PB14B PB15A PB15B PB16A PB16B PB17A GND5 PB17B VCCAUX Bank 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 C PCLKC5_0 T C T C T C T VREF2_5 VREF1_5 PCLKT5_0 BDQS14 C T C T C T C T T C T C T C T C T C BDQS6 LVDS T C T C T C T C VREF1_6 VREF2_6 Dual Function LDQS24 Pin Function PL33A PL33B PL34A PL34B PL35A PL35B PL36A PL36B VCCIO6 GND5 GND6 VCCIO5 PB2A PB2B PB3A PB3B PB4A PB4B PB5A PB5B PB6A PB6B VCCIO5 PB18A PB18B PB19A PB19B PB20A PB20B PB21A GND5 PB21B VCCIO5 PB22A PB22B PB23A PB23B PB24A PB24B PB25A GND5 PB25B VCCAUX LFECP10/LFEC10 Bank 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 C PCLKC5_0 T C T C T C T VREF2_5 VREF1_5 PCLKT5_0 BDQS22 C T C T C T C T T C T C T C T C T C BDQS6 LVDS T C T C T C T C VREF1_6 VREF2_6 Dual Function LDQS33 4-20 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFECP/EC6, LFECP/EC10 Logic Signal Connections: 208 PQFP (Cont.) LFECP6/LFEC6 Pin Number 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105* 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 Pin Function VCCIO4 PB18A PB18B PB19A PB19B PB20A PB20B PB21A GND4 PB21B PB22A PB22B PB23A PB23B PB24A PB24B PB25A PB25B PB33A VCCIO4 GND3 GND4 VCCIO3 PR27B PR27A PR26B PR26A PR25B PR25A PR24B PR24A PR23B GND3 PR23A PR22B PR22A VCCIO3 PR21B PR21A PR20B PR20A CFG2 CFG1 Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 C T C T DI/CSSPIN DOUT/CSON BUSY/SISPI D7/SPID0 T C T RLM0_PLLT_FB_A RLM0_PLLC_IN_A RLM0_PLLT_IN_A C T C T C T C T C RDQS24 RLM0_PLLC_FB_A VREF2_3 VREF1_3 C T C T C T C T C D6/SPID1 D5/SPID2 D4/SPID3 D1/SPID6 BDQS22 D3/SPID4 T C T C T C T WRITEN CS1N VREF1_4 CSN VREF2_4 D0/SPID7 D2/SPID5 LVDS Dual Function Pin Function VCCIO4 PB26A PB26B PB27A PB27B PB28A PB28B PB29A GND4 PB29B PB30A PB30B PB31A PB31B PB32A PB32B PB33A PB33B PB41A VCCIO4 GND3 GND4 VCCIO3 PR36B PR36A PR35B PR35A PR34B PR34A PR33B PR33A PR32B GND3 PR32A PR31B PR31A VCCIO3 PR30B PR30A PR29B PR29A CFG2 CFG1 LFECP10/LFEC10 Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 C T C T DI/CSSPIN DOUT/CSON BUSY/SISPI D7/SPID0 T C T RLM0_PLLT_FB_A RLM0_PLLC_IN_A RLM0_PLLT_IN_A C T C T C T C T C RDQS33 RLM0_PLLC_FB_A VREF2_3 VREF1_3 C T C T C T C T C D6/SPID1 D5/SPID2 D4/SPID3 D1/SPID6 BDQS30 D3/SPID4 T C T C T C T WRITEN CS1N VREF1_4 CSN VREF2_4 D0/SPID7 D2/SPID5 LVDS Dual Function 4-21 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFECP/EC6, LFECP/EC10 Logic Signal Connections: 208 PQFP (Cont.) LFECP6/LFEC6 Pin Number 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156* 157 158 159 160 161 162 163 164 165 166 167 168 Pin Function CFG0 VCC PROGRAMN CCLK INITN GND DONE GND VCC VCCAUX PR9B GND2 PR9A PR8B PR8A PR7B PR7A PR6B VCCIO2 PR6A PR5B PR5A PR4B PR4A NC NC PR2B PR2A VCCIO2 GND1 GND2 VCCIO1 PT33A PT25B PT25A PT24B PT24A PT23B PT23A PT22B PT22A PT21B GND1 Bank 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 C T C T C T C T C TDQS22 C T VREF1_2 VREF2_2 T C T C T RDQS6 T C T C T C PCLKT2_0 C PCLKC2_0 LVDS Dual Function Pin Function CFG0 VCC PROGRAMN CCLK INITN GND DONE GND VCC VCCAUX PR18B GND2 PR18A PR17B PR17A PR16B PR16A PR15B VCCIO2 PR15A PR14B PR14A PR13B PR13A GND VCC PR2B PR2A VCCIO2 GND1 GND2 VCCIO1 PT41A PT33B PT33A PT32B PT32A PT31B PT31A PT30B PT30A PT29B GND1 LFECP10/LFEC10 Bank 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 C T C T C T C T C TDQS30 C T VREF1_2 VREF2_2 T C T C T RDQS15 T C T C T C PCLKT2_0 C PCLKC2_0 LVDS Dual Function 4-22 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFECP/EC6, LFECP/EC10 Logic Signal Connections: 208 PQFP (Cont.) LFECP6/LFEC6 Pin Number 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 Pin Function PT21A PT20B PT20A PT19B PT19A PT18B PT18A VCCIO1 VCCAUX PT17B GND0 PT17A PT16B PT16A PT15B PT15A PT14B PT14A VCCIO0 PT13B GND0 PT13A PT12B PT12A PT11B PT11A PT10B PT10A VCCIO0 PT6B PT6A PT5B PT5A PT4B PT4A PT3B PT3A PT2B PT2A VCCIO0 Bank 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C T C T C T C T C T TDQS6 T C T C T C T C T C T C T C T TDQS14 PCLKT0_0 VREF1_0 VREF2_0 C PCLKC0_0 LVDS T C T C T C T VREF2_1 VREF1_1 Dual Function Pin Function PT29A PT28B PT28A PT27B PT27A PT26B PT26A VCCIO1 VCCAUX PT25B GND0 PT25A PT24B PT24A PT23B PT23A PT22B PT22A VCCIO0 PT21B GND0 PT21A PT20B PT20A PT19B PT19A PT18B PT18A VCCIO0 PT6B PT6A PT5B PT5A PT4B PT4A PT3B PT3A PT2B PT2A VCCIO0 LFECP10/LFEC10 Bank 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C T C T C T C T C T TDQS6 T C T C T C T C T C T C T C T TDQS22 PCLKT0_0 VREF1_0 VREF2_0 C PCLKC0_0 LVDS T C T C T C T VREF2_1 VREF1_1 Dual Function *Double bonded to the pin. 4-23 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFEC3 and LFECP/EC6 Logic Signal Connections: 256 fpBGA Ball Number GND D4 D3 C3 C2 B1 C1 E3 E4 F4 F5 G4 G3 D2 D1 E1 GND E2 F3 G5 H5 F2 F1 H4 H3 G2 G1 J4 J3 J5 K5 H2 H1 J2 J1 K4 K3 L3 L5 L4 LFEC3 Ball Function GND7 PL2A PL2B PL3A PL3B PL4A PL4B PL5A PL5B PL6A PL6B PL7A PL7B PL8A PL8B PL9A GND7 PL9B XRES NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC TCK TDI TMS TDO VCCJ Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 C PCLKC7_0 T C T C T C T C T C T C T C T PCLKT7_0 LDQS6 VREF2_7 VREF1_7 LVDS Dual Function Ball Function GND7 PL2A PL2B PL3A PL3B PL4A PL4B PL5A PL5B PL6A PL6B PL7A PL7B PL8A PL8B PL9A GND7 PL9B XRES PL11A PL11B PL12A PL12B PL13A PL13B PL14A GND6 PL14B PL15A PL15B PL16A PL16B PL17A PL17B PL18A GND6 PL18B TCK TDI TMS TDO VCCJ LFECP6/LFEC6 Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 C C T C T C T C T LDQS15 T C T C T C T C PCLKC7_0 T C T C T C T C T C T C T C T PCLKT7_0 LDQS6 VREF2_7 VREF1_7 LVDS Dual Function 4-24 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFEC3 and LFECP/EC6 Logic Signal Connections: 256 fpBGA (Cont.) Ball Number K2 K1 L2 L1 M2 M1 N1 GND N2 M4 M3 P1 R1 P2 P3 N3 N4 GND GND P4 N5 P5 P6 R4 R3 T2 T3 R5 R6 T4 T5 N6 M6 T6 GND T7 P7 N7 R7 R8 M7 M8 T8 LFEC3 Ball Function PL11A PL11B PL12A PL12B PL13A PL13B PL14A GND6 PL14B PL15A PL15B PL16A PL16B PL17A PL17B PL18A PL18B GND6 GND5 PB2A PB2B PB3A PB3B PB4A PB4B PB5A PB5B PB6A PB6B PB7A PB7B PB8A PB8B PB9A GND5 PB9B PB10A PB10B PB11A PB11B PB12A PB12B PB13A Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 C T C T C T C T T C T C T C T C T C T C T C T BDQS6 C T C T C T C T C VREF1_6 VREF2_6 LDQS15 LVDS T C T C T C T Dual Function LLM0_PLLT_IN_A LLM0_PLLC_IN_A LLM0_PLLT_FB_A LLM0_PLLC_FB_A Ball Function PL20A PL20B PL21A PL21B PL22A PL22B PL23A GND6 PL23B PL24A PL24B PL25A PL25B PL26A PL26B PL27A PL27B GND6 GND5 PB2A PB2B PB3A PB3B PB4A PB4B PB5A PB5B PB6A PB6B PB7A PB7B PB8A PB8B PB9A GND5 PB9B PB10A PB10B PB11A PB11B PB12A PB12B PB13A LFECP6/LFEC6 Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 C T C T C T C T T C T C T C T C T C T C T C T BDQS6 C T C T C T C T C VREF1_6 VREF2_6 LDQS24 LVDS T C T C T C T Dual Function LLM0_PLLT_IN_A LLM0_PLLC_IN_A LLM0_PLLT_FB_A LLM0_PLLC_FB_A 4-25 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFEC3 and LFECP/EC6 Logic Signal Connections: 256 fpBGA (Cont.) Ball Number GND T9 P8 N8 R9 R10 P9 N9 T10 GND T11 T12 T13 P10 N10 T14 T15 M10 GND M11 R11 P11 R13 R14 P12 P13 N11 N12 R12 GND GND N13 N14 P14 P15 R15 R16 M13 M14 P16 GND LFEC3 Ball Function GND5 PB13B PB14A PB14B PB15A PB15B PB16A PB16B PB17A GND5 PB17B PB18A PB18B PB19A PB19B PB20A PB20B PB21A GND4 PB21B PB22A PB22B PB23A PB23B PB24A PB24B PB25A PB25B NC GND4 GND3 PR18B PR18A PR17B PR17A PR16B PR16A PR15B PR15A PR14B GND3 Bank 5 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 C T C T C T C T C RDQS15 RLM0_PLLC_FB_A VREF2_3 VREF1_3 C D6/SPID1 C T C T C T C T D5/SPID2 D4/SPID3 D1/SPID6 BDQS22 D3/SPID4 C T C T C T C T PCLKC5_0 WRITEN CS1N VREF1_4 CSN VREF2_4 D0/SPID7 D2/SPID5 C T C T C T C T VREF2_5 VREF1_5 PCLKT5_0 BDQS14 LVDS Dual Function Ball Function GND5 PB13B PB14A PB14B PB15A PB15B PB16A PB16B PB17A GND5 PB17B PB18A PB18B PB19A PB19B PB20A PB20B PB21A GND4 PB21B PB22A PB22B PB23A PB23B PB24A PB24B PB25A GND4 PB25B PB26A GND4 GND4 GND3 PR27B PR27A PR26B PR26A PR25B PR25A PR24B PR24A PR23B GND3 LFECP6/LFEC6 Bank 5 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 C T C T C T C T C RDQS24 RLM0_PLLC_FB_A VREF2_3 VREF1_3 C D6/SPID1 C T C T C T C T D5/SPID2 D4/SPID3 D1/SPID6 BDQS22 D3/SPID4 C T C T C T C T PCLKC5_0 WRITEN CS1N VREF1_4 CSN VREF2_4 D0/SPID7 D2/SPID5 C T C T C T C T VREF2_5 VREF1_5 PCLKT5_0 BDQS14 LVDS Dual Function 4-26 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFEC3 and LFECP/EC6 Logic Signal Connections: 256 fpBGA (Cont.) Ball Number N16 N15 M15 M16 L16 K16 J16 L12 L14 L13 K13 L15 K15 K14 H16 H15 G16 G15 K12 J12 J14 J15 F16 F15 J13 H13 H14 G14 E16 E15 H12 GND G12 G13 F13 F12 E13 D16 D15 F14 E14 LFEC3 Ball Function PR14A PR13B PR13A PR12B PR12A PR11B PR11A CFG2 CFG1 CFG0 PROGRAMN CCLK INITN DONE NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC PR9B GND2 PR9A PR8B PR8A PR7B PR7A PR6B PR6A PR5B PR5A Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 T C T C T C T C T RDQS6 PCLKT2_0 C PCLKC2_0 LVDS T C T C T C T Dual Function RLM0_PLLT_FB_A RLM0_PLLC_IN_A RLM0_PLLT_IN_A DI/CSSPIN DOUT/CSON BUSY/SISPI D7/SPID0 Ball Function PR23A PR22B PR22A PR21B PR21A PR20B PR20A CFG2 CFG1 CFG0 PROGRAMN CCLK INITN DONE GND3 PR18B PR18A PR17B PR17A PR16B PR16A PR15B PR15A PR14B GND3 PR14A PR13B PR13A PR12B PR12A PR11B PR11A PR9B GND2 PR9A PR8B PR8A PR7B PR7A PR6B PR6A PR5B PR5A 2 2 2 2 2 2 2 2 2 T C T C T C T C T RDQS6 PCLKT2_0 LFECP6/LFEC6 Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 T C T C T C T C PCLKC2_0 C T C T C T C T C RDQS15 LVDS T C T C T C T Dual Function RLM0_PLLT_FB_A RLM0_PLLC_IN_A RLM0_PLLT_IN_A DI/CSSPIN DOUT/CSON BUSY/SISPI D7/SPID0 4-27 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFEC3 and LFECP/EC6 Logic Signal Connections: 256 fpBGA (Cont.) Ball Number C16 B16 C15 C14 D14 D13 GND GND B13 C13 C12 D12 A15 B14 D11 C11 E10 E11 A14 GND A13 D10 C10 A12 B12 A11 B11 A10 GND B10 C9 B9 E9 D9 D8 C8 A9 GND A8 B8 B7 LFEC3 Ball Function PR4B PR4A PR3B PR3A PR2B PR2A GND2 GND1 NC NC PT25B PT25A PT24B PT24A PT23B PT23A PT22B PT22A PT21B GND1 PT21A PT20B PT20A PT19B PT19A PT18B PT18A PT17B GND0 PT17A PT16B PT16A PT15B PT15A PT14B PT14A PT13B GND0 PT13A PT12B PT12A Bank 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T C T T C T C T C T C TDQS14 PCLKT0_0 VREF1_0 VREF2_0 T C T C T C T C PCLKC0_0 VREF2_1 VREF1_1 T C T C T C T C TDQS22 C LVDS C T C T C T VREF1_2 VREF2_2 Dual Function Ball Function PR4B PR4A PR3B PR3A PR2B PR2A GND2 GND1 GND1 PT26B PT26A PT25B GND1 PT25A PT24B PT24A PT23B PT23A PT22B PT22A PT21B GND1 PT21A PT20B PT20A PT19B PT19A PT18B PT18A PT17B GND0 PT17A PT16B PT16A PT15B PT15A PT14B PT14A PT13B GND0 PT13A PT12B PT12A LFECP6/LFEC6 Bank 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T C T T C T C T C T C TDQS14 PCLKT0_0 VREF1_0 VREF2_0 T C T C T C T C PCLKC0_0 VREF2_1 VREF1_1 T C T C T C T C TDQS22 C T C LVDS C T C T C T VREF1_2 VREF2_2 Dual Function 4-28 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFEC3 and LFECP/EC6 Logic Signal Connections: 256 fpBGA (Cont.) Ball Number D7 C7 A7 A6 E7 GND E6 D6 C6 B6 B5 A5 A4 A3 A2 B2 B3 D5 C5 C4 B4 GND A1 A16 G10 G7 G8 G9 H10 H7 H8 H9 J10 J7 J8 J9 K10 K7 K8 K9 T1 T16 E12 LFEC3 Ball Function PT11B PT11A PT10B PT10A PT9B GND0 PT9A PT8B PT8A PT7B PT7A PT6B PT6A PT5B PT5A PT4B PT4A PT3B PT3A PT2B PT2A GND0 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T C T C T C T C T C T C T C T TDQS6 LVDS C T C T C Dual Function Ball Function PT11B PT11A PT10B PT10A PT9B GND0 PT9A PT8B PT8A PT7B PT7A PT6B PT6A PT5B PT5A PT4B PT4A PT3B PT3A PT2B PT2A GND0 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC LFECP6/LFEC6 Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T C T C T C T C T C T C T C T TDQS6 LVDS C T C T C Dual Function 4-29 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFEC3 and LFECP/EC6 Logic Signal Connections: 256 fpBGA (Cont.) Ball Number E5 E8 M12 M5 M9 B15 R2 F7 F8 F10 F9 G11 H11 J11 K11 L10 L9 L7 L8 J6 K6 G6 H6 F6 F11 L11 L6 LFEC3 Ball Function VCC VCC VCC VCC VCC VCCAUX VCCAUX VCCIO0 VCCIO0 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO5 VCCIO5 VCCIO6 VCCIO6 VCCIO7 VCCIO7 VCC VCC VCC VCC Bank 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 LVDS Dual Function Ball Function VCC VCC VCC VCC VCC VCCAUX VCCAUX VCCIO0 VCCIO0 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO5 VCCIO5 VCCIO6 VCCIO6 VCCIO7 VCCIO7 VCC VCC VCC VCC LFECP6/LFEC6 Bank 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 LVDS Dual Function 4-30 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFECP/EC10 and LFECP/EC15 Logic Signal Connections: 256 fpBGA Ball Number GND D4 D3 GND C3 C2 B1 C1 E3 GND E4 F4 F5 G4 G3 D2 D1 E1 GND E2 F3 G5 H5 F2 F1 H4 H3 G2 GND G1 J4 J3 J5 K5 H2 H1 J2 GND J1 K4 K3 LFECP10/LFEC10 Ball Function GND7 PL2A PL2B GND7 PL12A PL12B PL13A PL13B PL14A GND7 PL14B PL15A PL15B PL16A PL16B PL17A PL17B PL18A GND7 PL18B XRES PL20A PL20B PL21A PL21B PL22A PL22B PL23A GND6 PL23B PL24A PL24B PL25A PL25B PL26A PL26B PL27A GND6 PL27B TCK TDI Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 C C T C T C T C T LDQS24 T C T C T C T C PCLKC7_0 C T C T C T C T PCLKT7_0 LDQS15 T C T C T T C VREF2_7 VREF1_7 LVDS Dual Function Ball Function GND7 PL2A PL2B GND7 PL16A PL16B PL17A PL17B PL18A GND7 GND7 PL18B PL19A PL19B PL20A PL20B PL21A PL21B PL22A GND7 PL22B XRES PL24A PL24B PL25A PL25B PL26A PL26B PL27A GND6 PL27B PL28A PL28B PL29A PL29B PL30A PL30B PL31A GND6 PL31B TCK TDI LFECP15/LFEC15 Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 C C T C T C T C T LDQS28 T C T C T C T C PCLKC7_0 C T C T C T C T PCLKT7_0 LDQS19 T C T C T T C VREF2_7 VREF1_7 LVDS Dual Function 4-31 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFECP/EC10 and LFECP/EC15 Logic Signal Connections: 256 fpBGA Ball Number L3 L5 L4 K2 K1 L2 L1 M2 M1 N1 GND N2 M4 M3 P1 R1 P2 P3 N3 N4 GND GND GND P4 N5 P5 P6 R4 R3 T2 GND T3 R5 R6 T4 T5 N6 M6 T6 GND T7 P7 LFECP10/LFEC10 Ball Function TMS TDO VCCJ PL29A PL29B PL30A PL30B PL31A PL31B PL32A GND6 PL32B PL33A PL33B PL34A PL34B PL35A PL35B PL36A PL36B GND6 GND5 GND5 PB10A PB10B PB11A PB11B PB12A PB12B PB13A GND5 PB13B PB14A PB14B PB15A PB15B PB16A PB16B PB17A GND5 PB17B PB18A Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 C T C T C T C T C T BDQS14 T C T C T C T C T C T C T C T C VREF1_6 VREF2_6 LDQS33 T C T C T C T LLM0_PLLT_IN_A LLM0_PLLC_IN_A LLM0_PLLT_FB_A LLM0_PLLC_FB_A LVDS Dual Function Ball Function TMS TDO VCCJ PL37A PL37B PL38A PL38B PL39A PL39B PL40A GND6 GND6 PL40B PL41A PL41B PL42A PL42B PL43A PL43B PL44A PL44B GND6 GND5 GND5 PB10A PB10B PB11A PB11B PB12A PB12B PB13A GND5 PB13B PB14A PB14B PB15A PB15B PB16A PB16B PB17A GND5 PB17B PB18A LFECP15/LFEC15 Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 C T C T C T C T C T BDQS14 T C T C T C T C T C T C T C T C VREF1_6 VREF2_6 LDQS41 T C T C T C T LLM0_PLLT_IN_A LLM0_PLLC_IN_A LLM0_PLLT_FB_A LLM0_PLLC_FB_A LVDS Dual Function 4-32 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFECP/EC10 and LFECP/EC15 Logic Signal Connections: 256 fpBGA Ball Number N7 R7 R8 M7 M8 T8 GND T9 P8 N8 R9 R10 P9 N9 T10 GND T11 T12 T13 P10 N10 T14 T15 M10 GND M11 R11 P11 R13 R14 P12 P13 N11 GND N12 R12 GND GND GND N13 N14 LFECP10/LFEC10 Ball Function PB18B PB19A PB19B PB20A PB20B PB21A GND5 PB21B PB22A PB22B PB23A PB23B PB24A PB24B PB25A GND5 PB25B PB26A PB26B PB27A PB27B PB28A PB28B PB29A GND4 PB29B PB30A PB30B PB31A PB31B PB32A PB32B PB33A GND4 PB33B PB34A GND4 GND4 GND3 PR36B PR36A Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 3 3 3 C T VREF2_3 VREF1_3 C D6/SPID1 C T C T C T C T D5/SPID2 D4/SPID3 D1/SPID6 BDQS30 D3/SPID4 C T C T C T C T PCLKC5_0 WRITEN CS1N VREF1_4 CSN VREF2_4 D0/SPID7 D2/SPID5 C T C T C T C T VREF2_5 VREF1_5 PCLKT5_0 BDQS22 LVDS C T C T C T Dual Function Ball Function PB18B PB19A PB19B PB20A PB20B PB21A GND5 PB21B PB22A PB22B PB23A PB23B PB24A PB24B PB25A GND5 PB25B PB26A PB26B PB27A PB27B PB28A PB28B PB29A GND4 PB29B PB30A PB30B PB31A PB31B PB32A PB32B PB33A GND4 PB33B PB34A GND4 GND4 GND4 GND4 GND3 PR44B PR44A LFECP15/LFEC15 Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 3 3 3 C T VREF2_3 VREF1_3 C D6/SPID1 C T C T C T C T D5/SPID2 D4/SPID3 D1/SPID6 BDQS30 D3/SPID4 C T C T C T C T PCLKC5_0 WRITEN CS1N VREF1_4 CSN VREF2_4 D0/SPID7 D2/SPID5 C T C T C T C T VREF2_5 VREF1_5 PCLKT5_0 BDQS22 LVDS C T C T C T Dual Function 4-33 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFECP/EC10 and LFECP/EC15 Logic Signal Connections: 256 fpBGA Ball Number P14 P15 R15 R16 M13 M14 P16 GND N16 N15 M15 M16 L16 K16 J16 L12 L14 L13 K13 L15 K15 K14 GND H16 H15 G16 G15 K12 J12 J14 J15 F16 GND F15 J13 H13 H14 G14 E16 E15 H12 GND LFECP10/LFEC10 Ball Function PR35B PR35A PR34B PR34A PR33B PR33A PR32B GND3 PR32A PR31B PR31A PR30B PR30A PR29B PR29A CFG2 CFG1 CFG0 PROGRAMN CCLK INITN DONE GND3 PR27B PR27A PR26B PR26A PR25B PR25A PR24B PR24A PR23B GND3 PR23A PR22B PR22A PR21B PR21A PR20B PR20A PR18B GND2 Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 T C T C T C T C PCLKC2_0 T C T C T C T C RDQS24 C T C T C T C T RLM0_PLLT_FB_A RLM0_PLLC_IN_A RLM0_PLLT_IN_A DI/CSSPIN DOUT/CSON BUSY/SISPI D7/SPID0 LVDS C T C T C T C RDQS33 RLM0_PLLC_FB_A Dual Function Ball Function PR43B PR43A PR42B PR42A PR41B PR41A PR40B GND3 PR40A PR39B PR39A PR38B PR38A PR37B PR37A CFG2 CFG1 CFG0 PROGRAMN CCLK INITN DONE GND3 PR31B GND3 PR31A PR30B PR30A PR29B PR29A PR28B PR28A PR27B GND3 PR27A PR26B PR26A PR25B PR25A PR24B PR24A PR22B GND2 LFECP15/LFEC15 Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 T C T C T C T C PCLKC2_0 T C T C T C T C RDQS28 C T C T C T C T RLM0_PLLT_FB_A RLM0_PLLC_IN_A RLM0_PLLT_IN_A DI/CSSPIN DOUT/CSON BUSY/SISPI D7/SPID0 LVDS C T C T C T C RDQS41 RLM0_PLLC_FB_A Dual Function 4-34 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFECP/EC10 and LFECP/EC15 Logic Signal Connections: 256 fpBGA Ball Number G12 G13 F13 F12 E13 D16 D15 F14 GND E14 C16 B16 C15 C14 GND D14 D13 GND GND GND B13 C13 C12 GND D12 A15 B14 D11 C11 E10 E11 A14 GND A13 D10 C10 A12 B12 A11 B11 LFECP10/LFEC10 Ball Function PR18A PR17B PR17A PR16B PR16A PR15B PR15A PR14B GND2 PR14A PR13B PR13A PR12B PR12A GND2 PR2B PR2A GND2 GND1 GND1 PT34B PT34A PT33B GND1 PT33A PT32B PT32A PT31B PT31A PT30B PT30A PT29B GND1 PT29A PT28B PT28A PT27B PT27A PT26B PT26A Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 T C T C T C T VREF2_1 VREF1_1 T C T C T C T C TDQS30 C T C C T VREF1_2 VREF2_2 T C T C T LVDS T C T C T C T C Dual Function PCLKT2_0 Ball Function PR22A PR21B PR21A PR20B PR20A PR19B PR19A PR18B GND2 PR18A PR17B PR17A PR16B PR16A GND2 GND2 PR2B PR2A GND2 GND1 GND1 GND1 GND1 PT34B PT34A PT33B GND1 PT33A PT32B PT32A PT31B PT31A PT30B PT30A PT29B GND1 PT29A PT28B PT28A PT27B PT27A PT26B PT26A LFECP15/LFEC15 Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 T C T C T C T VREF2_1 VREF1_1 T C T C T C T C TDQS30 C T C C T VREF1_2 VREF2_2 T C T C T LVDS T C T C T C T C RDQS19 Dual Function PCLKT2_0 4-35 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFECP/EC10 and LFECP/EC15 Logic Signal Connections: 256 fpBGA Ball Number A10 GND B10 C9 B9 E9 D9 D8 C8 A9 GND A8 B8 B7 D7 C7 A7 A6 E7 GND E6 D6 C6 B6 B5 A5 A4 A3 A2 B2 B3 D5 C5 C4 B4 GND GND A1 A16 G10 G7 G8 LFECP10/LFEC10 Ball Function PT25B GND0 PT25A PT24B PT24A PT23B PT23A PT22B PT22A PT21B GND0 PT21A PT20B PT20A PT19B PT19A PT18B PT18A PT17B GND0 PT17A PT16B PT16A PT15B PT15A PT14B PT14A PT13B GND0 PT13A PT12B PT12A PT11B PT11A PT10B PT10A GND0 GND0 GND GND GND GND GND Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T C T C T C T T C T C T C T C TDQS14 T C T C T C T C T C T C T C T C TDQS22 PCLKT0_0 VREF1_0 VREF2_0 LVDS C Dual Function PCLKC0_0 Ball Function PT25B GND0 PT25A PT24B PT24A PT23B PT23A PT22B PT22A PT21B GND0 PT21A PT20B PT20A PT19B PT19A PT18B PT18A PT17B GND0 PT17A PT16B PT16A PT15B PT15A PT14B PT14A PT13B GND0 PT13A PT12B PT12A PT11B PT11A PT10B PT10A GND0 GND0 GND GND GND GND GND LFECP15/LFEC15 Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T C T C T C T T C T C T C T C TDQS14 T C T C T C T C T C T C T C T C TDQS22 PCLKT0_0 VREF1_0 VREF2_0 LVDS C Dual Function PCLKC0_0 4-36 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFECP/EC10 and LFECP/EC15 Logic Signal Connections: 256 fpBGA Ball Number G9 H10 H7 H8 H9 J10 J7 J8 J9 K10 K7 K8 K9 T1 T16 E12 E5 E8 M12 M5 M9 B15 R2 F7 F8 F10 F9 G11 H11 J11 K11 L10 L9 L7 L8 J6 K6 G6 H6 F6 F11 L11 L6 LFECP10/LFEC10 Ball Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC VCC VCC VCC VCC VCC VCCAUX VCCAUX VCCIO0 VCCIO0 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO5 VCCIO5 VCCIO6 VCCIO6 VCCIO7 VCCIO7 VCC VCC VCC VCC Bank 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 LVDS Dual Function Ball Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC VCC VCC VCC VCC VCC VCCAUX VCCAUX VCCIO0 VCCIO0 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO5 VCCIO5 VCCIO6 VCCIO6 VCCIO7 VCCIO7 VCC VCC VCC VCC LFECP15/LFEC15 Bank 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 LVDS Dual Function 4-37 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFECP/EC6, LFECP/EC10, LFECP/EC15 Logic Signal Connections: 484 fpBGA LFECP6/LFEC6 Ball Number GND D4 E4 C3 B2 E5 F5 D3 C2 F4 G4 E3 D2 B1 C1 F3 GND E2 G5 H6 G3 H4 J5 H5 F2 GND F1 E1 D1 H3 G2 H2 G1 J4 GND J3 J2 H1 K4 K5 K3 K2 J1 GND K1 L3 L4 L5 L2 L1 Ball Function GND7 PL2A PL2B NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC PL3A PL3B PL4A PL4B PL5A PL5B PL6A PL6B PL7A PL7B PL8A PL8B PL9A GND7 PL9B XRES PL11A PL11B PL12A PL12B Bank LVDS 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 T C T C C PCLKC7_0 C T C T C T C T PCLKT7_0 LDQS6 T C T C T T C VREF2_7 VREF1_7 Dual Function Ball Number GND D4 E4 C3 B2 E5 F5 D3 C2 F4 G4 E3 D2 B1 C1 F3 GND E2 G5 H6 G3 H4 J5 H5 F2 GND F1 E1 D1 H3 G2 H2 G1 J4 GND J3 J2 H1 K4 K5 K3 K2 J1 GND K1 L3 L4 L5 L2 L1 LFECP10/LFEC10 Ball Function GND7 PL2A PL2B PL3A PL3B PL4A PL4B PL5A PL5B PL6A PL6B PL7A PL7B PL8A PL8B PL9A GND7 PL9B NC NC NC NC NC NC NC NC PL11A PL11B PL12A PL12B PL13A PL13B PL14A GND7 PL14B PL15A PL15B PL16A PL16B PL17A PL17B PL18A GND7 PL18B XRES PL20A PL20B PL21A PL21B Bank LVDS 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 T C T C C PCLKC7_0 C T C T C T C T PCLKT7_0 LDQS15 T C T C T C T C LUM0_PLLC_FB_A T C T C T C T C T C T C T C T LUM0_PLLT_IN_A LUM0_PLLC_IN_A LUM0_PLLT_FB_A LDQS6 VREF2_7 VREF1_7 Dual Function Ball Number GND D4 E4 C3 B2 E5 F5 D3 C2 F4 G4 E3 D2 B1 C1 F3 GND E2 G5 H6 G3 H4 J5 H5 F2 GND F1 E1 D1 H3 G2 H2 G1 J4 GND J3 J2 H1 K4 K5 K3 K2 J1 GND K1 L3 L4 L5 L2 L1 LFECP/LFEC15 Ball Function GND7 PL2A PL2B PL3A PL3B PL4A PL4B PL5A PL5B PL6A PL6B PL7A PL7B PL8A PL8B PL9A GND7 PL9B PL11A PL11B PL12A PL12B PL13A PL13B PL14A GND7 PL14B PL15A PL15B PL16A PL16B PL17A PL17B PL18A GND7 PL18B PL19A PL19B PL20A PL20B PL21A PL21B PL22A GND7 PL22B XRES PL24A PL24B PL25A PL25B Bank LVDS 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 T C T C C PCLKC7_0 C T C T C T C T PCLKT7_0 LDQS19 C T C T C T C T C T C T C T C T LUM0_PLLC_FB_A T C T C T C T C T C T C T C T LUM0_PLLT_IN_A LUM0_PLLC_IN_A LUM0_PLLT_FB_A LDQS6 VREF2_7 VREF1_7 Dual Function 4-38 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFECP/EC6, LFECP/EC10, LFECP/EC15 Logic Signal Connections: 484 fpBGA (Cont.) LFECP6/LFEC6 Ball Number M4 M5 M1 GND M2 N3 M3 N5 N4 N1 N2 P1 GND P2 R6 P5 P3 P4 R1 R2 R5 GND R4 T1 T2 R3 T3 T5 U5 T4 U1 U2 V1 V2 U3 V3 U4 V5 W1 GND W2 Y1 Y2 AA1 AA2 W4 V4 W3 Y3 GND Ball Function PL13A PL13B PL14A GND6 PL14B PL15A PL15B PL16A PL16B PL17A PL17B PL18A GND6 PL18B NC NC NC NC NC NC NC NC NC NC NC NC TCK TDI TMS TDO VCCJ PL20A PL20B PL21A PL21B PL22A PL22B PL23A GND6 PL23B PL24A PL24B PL25A PL25B PL26A PL26B PL27A PL27B GND6 Bank LVDS 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 C T C T C T C T C VREF1_6 VREF2_6 LDQS24 T C T C T C T LLM0_PLLT_IN_A LLM0_PLLC_IN_A LLM0_PLLT_FB_A LLM0_PLLC_FB_A C C T C T C T C T LDQS15 T C T Dual Function Ball Number M4 M5 M1 GND M2 N3 M3 N5 N4 N1 N2 P1 GND P2 R6 P5 P3 P4 R1 R2 R5 R4 T1 T2 R3 T3 T5 U5 T4 U1 U2 V1 V2 U3 V3 U4 V5 W1 GND W2 Y1 Y2 AA1 AA2 W4 V4 W3 Y3 GND LFECP10/LFEC10 Ball Function PL22A PL22B PL23A GND6 PL23B PL24A PL24B PL25A PL25B PL26A PL26B PL27A GND6 PL27B NC NC NC NC NC NC NC NC NC NC NC NC TCK TDI TMS TDO VCCJ PL29A PL29B PL30A PL30B PL31A PL31B PL32A GND6 PL32B PL33A PL33B PL34A PL34B PL35A PL35B PL36A PL36B GND6 Bank LVDS 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 C T C T C T C T C VREF1_6 VREF2_6 LDQS33 T C T C T C T LLM0_PLLT_IN_A LLM0_PLLC_IN_A LLM0_PLLT_FB_A LLM0_PLLC_FB_A C C T C T C T C T LDQS24 T C T Dual Function Ball Number M4 M5 M1 GND M2 N3 M3 N5 N4 N1 N2 P1 GND P2 R6 P5 P3 P4 R1 R2 R5 GND R4 T1 T2 R3 T3 T5 U5 T4 U1 U2 V1 V2 U3 V3 U4 V5 W1 GND W2 Y1 Y2 AA1 AA2 W4 V4 W3 Y3 GND LFECP/LFEC15 Ball Function PL26A PL26B PL27A GND6 PL27B PL28A PL28B PL29A PL29B PL30A PL30B PL31A GND6 PL31B PL32A PL32B PL33A PL33B PL34A PL34B PL35A GND6 PL35B NC NC NC NC TCK TDI TMS TDO VCCJ PL37A PL37B PL38A PL38B PL39A PL39B PL40A GND6 PL40B PL41A PL41B PL42A PL42B PL43A PL43B PL44A PL44B GND6 Bank LVDS 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 C T C T C T C T C VREF1_6 VREF2_6 LDQS41 T C T C T C T LLM0_PLLT_IN_A LLM0_PLLC_IN_A LLM0_PLLT_FB_A LLM0_PLLC_FB_A C C T C T C T C T C T C T C T C T LDQS28 T C T Dual Function 4-39 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFECP/EC6, LFECP/EC10, LFECP/EC15 Logic Signal Connections: 484 fpBGA (Cont.) LFECP6/LFEC6 Ball Number GND V7 T6 V8 U7 W5 U6 AA3 AB3 Y6 V6 AA5 W6 Y5 Y4 AA4 GND AB4 Y7 W8 W7 U8 W9 U9 Y8 GND Y9 V9 T9 W10 U10 V10 T10 AA6 GND AB5 AA8 AA7 AB6 AB7 Y10 W11 AB8 GND AB9 AA10 AA9 Y11 AA11 V11 Ball Function GND5 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC PB2A PB2B PB3A PB3B PB4A PB4B PB5A PB5B PB6A PB6B PB7A PB7B PB8A PB8B PB9A GND5 PB9B PB10A PB10B PB11A PB11B PB12A PB12B PB13A GND5 PB13B PB14A PB14B PB15A PB15B PB16A Bank LVDS 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 C T C T C T VREF2_5 BDQS14 C T C T C T C T C T C T C T C T BDQS6 T C T C T C T Dual Function Ball Number GND V7 T6 V8 U7 W5 U6 AA3 AB3 Y6 V6 AA5 W6 Y5 Y4 AA4 GND AB4 Y7 W8 W7 U8 W9 U9 Y8 GND Y9 V9 T9 W10 U10 V10 T10 AA6 GND AB5 AA8 AA7 AB6 AB7 Y10 W11 AB8 GND AB9 AA10 AA9 Y11 AA11 V11 LFECP10/LFEC10 Ball Function GND5 PB2A PB2B PB3A PB3B PB4A PB4B PB5A PB5B PB6A PB6B PB7A PB7B PB8A PB8B PB9A GND5 PB9B PB10A PB10B PB11A PB11B PB12A PB12B PB13A GND5 PB13B PB14A PB14B PB15A PB15B PB16A PB16B PB17A GND5 PB17B PB18A PB18B PB19A PB19B PB20A PB20B PB21A GND5 PB21B PB22A PB22B PB23A PB23B PB24A Bank LVDS 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 C T C T C T VREF2_5 BDQS22 C T C T C T C T C T C T C T C T BDQS14 C T C T C T C T T C T C T C T C T C T C T C T BDQS6 Dual Function Ball Number GND V7 T6 V8 U7 W5 U6 AA3 AB3 Y6 V6 AA5 W6 Y5 Y4 AA4 GND AB4 Y7 W8 W7 U8 W9 U9 Y8 GND Y9 V9 T9 W10 U10 V10 T10 AA6 GND AB5 AA8 AA7 AB6 AB7 Y10 W11 AB8 GND AB9 AA10 AA9 Y11 AA11 V11 LFECP/LFEC15 Ball Function GND5 PB2A PB2B PB3A PB3B PB4A PB4B PB5A PB5B PB6A PB6B PB7A PB7B PB8A PB8B PB9A GND5 PB9B PB10A PB10B PB11A PB11B PB12A PB12B PB13A GND5 PB13B PB14A PB14B PB15A PB15B PB16A PB16B PB17A GND5 PB17B PB18A PB18B PB19A PB19B PB20A PB20B PB21A GND5 PB21B PB22A PB22B PB23A PB23B PB24A Bank LVDS 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 C T C T C T VREF2_5 BDQS22 C T C T C T C T C T C T C T C T BDQS14 C T C T C T C T T C T C T C T C T C T C T C T BDQS6 Dual Function 4-40 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFECP/EC6, LFECP/EC10, LFECP/EC15 Logic Signal Connections: 484 fpBGA (Cont.) LFECP6/LFEC6 Ball Number V12 AB10 GND AB11 Y12 U11 W12 U12 W13 U13 AA12 GND AB12 T13 V13 W14 U14 Y13 V14 AA13 GND AB13 AA14 Y14 Y15 W15 V15 T14 AB14 GND AB15 AB16 AA15 AB17 AA16 AB18 AA17 AB19 GND AA18 W16 U15 V16 U16 Y17 V17 AB20 GND AA19 Y16 Ball Function PB16B PB17A GND5 PB17B PB18A PB18B PB19A PB19B PB20A PB20B PB21A GND4 PB21B PB22A PB22B PB23A PB23B PB24A PB24B PB25A GND4 PB25B PB26A PB26B PB27A PB27B PB28A PB28B PB29A GND4 PB29B PB30A PB30B PB31A PB31B PB32A PB32B PB33A PB33B NC NC NC NC NC NC NC NC NC Bank LVDS 5 5 5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 C C T C T C T C T BDQS30 C T C T C T C T D6/SPID1 C T C T C T C T D5/SPID2 D4/SPID3 D1/SPID6 BDQS22 D3/SPID4 C T C T C T C T PCLKC5_0 WRITEN CS1N VREF1_4 CSN VREF2_4 D0/SPID7 D2/SPID5 C T Dual Function VREF1_5 PCLKT5_0 Ball Number V12 AB10 GND AB11 Y12 U11 W12 U12 W13 U13 AA12 GND AB12 T13 V13 W14 U14 Y13 V14 AA13 GND AB13 AA14 Y14 Y15 W15 V15 T14 AB14 GND AB15 AB16 AA15 AB17 AA16 AB18 AA17 AB19 GND AA18 W16 U15 V16 U16 Y17 V17 AB20 GND AA19 Y16 LFECP10/LFEC10 Ball Function PB24B PB25A GND5 PB25B PB26A PB26B PB27A PB27B PB28A PB28B PB29A GND4 PB29B PB30A PB30B PB31A PB31B PB32A PB32B PB33A GND4 PB33B PB34A PB34B PB35A PB35B PB36A PB36B PB37A GND4 PB37B PB38A PB38B PB39A PB39B PB40A PB40B PB41A PB41B NC NC NC NC NC NC NC NC NC Bank LVDS 5 5 5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 C C T C T C T C T BDQS38 C T C T C T C T D6/SPID1 C T C T C T C T D5/SPID2 D4/SPID3 D1/SPID6 BDQS30 D3/SPID4 C T C T C T C T PCLKC5_0 WRITEN CS1N VREF1_4 CSN VREF2_4 D0/SPID7 D2/SPID5 C T Dual Function VREF1_5 PCLKT5_0 Ball Number V12 AB10 GND AB11 Y12 U11 W12 U12 W13 U13 AA12 GND AB12 T13 V13 W14 U14 Y13 V14 AA13 GND AB13 AA14 Y14 Y15 W15 V15 T14 AB14 GND AB15 AB16 AA15 AB17 AA16 AB18 AA17 AB19 GND AA18 W16 U15 V16 U16 Y17 V17 AB20 GND AA19 Y16 LFECP/LFEC15 Ball Function PB24B PB25A GND5 PB25B PB26A PB26B PB27A PB27B PB28A PB28B PB29A GND4 PB29B PB30A PB30B PB31A PB31B PB32A PB32B PB33A GND4 PB33B PB34A PB34B PB35A PB35B PB36A PB36B PB37A GND4 PB37B PB38A PB38B PB39A PB39B PB40A PB40B PB41A GND4 PB41B PB42A PB42B PB43A PB43B PB44A PB44B PB45A GND4 PB45B PB46A Bank LVDS 5 5 5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 C T BDQS46 C T C T C T C T C T C T C T C T BDQS38 C T C T C T C T D6/SPID1 C T C T C T C T D5/SPID2 D4/SPID3 D1/SPID6 BDQS30 D3/SPID4 C T C T C T C T PCLKC5_0 WRITEN CS1N VREF1_4 CSN VREF2_4 D0/SPID7 D2/SPID5 C T Dual Function VREF1_5 PCLKT5_0 4-41 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFECP/EC6, LFECP/EC10, LFECP/EC15 Logic Signal Connections: 484 fpBGA (Cont.) LFECP6/LFEC6 Ball Number W17 AA20 Y19 Y18 W18 T17 U17 GND GND W20 Y20 AA21 AB21 W19 V19 Y21 AA22 V20 GND U20 W21 Y22 V21 W22 U21 V22 T19 U19 U18 V18 T20 T21 R20 T18 R17 R19 R18 U22 GND T22 R21 R22 P20 N20 P19 P18 P21 GND P22 N21 Ball Function NC NC NC NC NC NC NC GND4 GND3 PR27B PR27A PR26B PR26A PR25B PR25A PR24B PR24A PR23B GND3 PR23A PR22B PR22A PR21B PR21A PR20B PR20A CFG2 CFG1 CFG0 PROGRAMN CCLK INITN DONE NC NC NC NC NC NC NC NC NC NC NC NC PR18B GND3 PR18A PR17B Bank LVDS 4 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 T C C T C T C T C T RLM0_PLLT_FB_A RLM0_PLLC_IN_A RLM0_PLLT_IN_A DI/CSSPIN DOUT/CSON BUSY/SISPI D7/SPID0 C T C T C T C T C RDQS24 RLM0_PLLC_FB_A VREF2_3 VREF1_3 Dual Function Ball Number W17 AA20 Y19 Y18 W18 T17 U17 GND GND W20 Y20 AA21 AB21 W19 V19 Y21 AA22 V20 GND U20 W21 Y22 V21 W22 U21 V22 T19 U19 U18 V18 T20 T21 R20 T18 R17 R19 R18 U22 GND T22 R21 R22 P20 N20 P19 P18 P21 GND P22 N21 LFECP10/LFEC10 Ball Function NC NC NC NC NC NC NC GND4 GND3 PR36B PR36A PR35B PR35A PR34B PR34A PR33B PR33A PR32B GND3 PR32A PR31B PR31A PR30B PR30A PR29B PR29A CFG2 CFG1 CFG0 PROGRAMN CCLK INITN DONE NC NC NC NC NC NC NC NC NC NC NC NC PR27B GND3 PR27A PR26B Bank LVDS 4 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 T C C T C T C T C T RLM0_PLLT_FB_A RLM0_PLLC_IN_A RLM0_PLLT_IN_A DI/CSSPIN DOUT/CSON BUSY/SISPI D7/SPID0 C T C T C T C T C RDQS33 RLM0_PLLC_FB_A VREF2_3 VREF1_3 Dual Function Ball Number W17 AA20 Y19 Y18 W18 T17 U17 GND GND W20 Y20 AA21 AB21 W19 V19 Y21 AA22 V20 GND U20 W21 Y22 V21 W22 U21 V22 T19 U19 U18 V18 T20 T21 R20 T18 R17 R19 R18 U22 GND T22 R21 R22 P20 N20 P19 P18 P21 GND P22 N21 LFECP/LFEC15 Ball Function PB46B PB47A PB47B PB48A PB48B PB49A PB49B GND4 GND3 PR44B PR44A PR43B PR43A PR42B PR42A PR41B PR41A PR40B GND3 PR40A PR39B PR39A PR38B PR38A PR37B PR37A CFG2 CFG1 CFG0 PROGRAMN CCLK INITN DONE NC NC NC NC PR35B GND3 PR35A PR34B PR34A PR33B PR33A PR32B PR32A PR31B GND3 PR31A PR30B Bank LVDS 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 T C T C T C T C T C C T C T C T C T RLM0_PLLT_FB_A RLM0_PLLC_IN_A RLM0_PLLT_IN_A DI/CSSPIN DOUT/CSON BUSY/SISPI D7/SPID0 C T C T C T C T C RDQS41 RLM0_PLLC_FB_A VREF2_3 VREF1_3 C T C T C T C Dual Function 4-42 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFECP/EC6, LFECP/EC10, LFECP/EC15 Logic Signal Connections: 484 fpBGA (Cont.) LFECP6/LFEC6 Ball Number N22 N19 N18 M21 L20 L21 GND M20 M18 M19 M22 L22 K22 K21 J22 GND J21 H22 H21 L19 L18 K20 J20 K19 GND K18 G22 F22 F21 E22 E21 D22 G21 G20 GND J18 H19 J19 H20 H17 H18 D21 GND C22 G19 G18 F20 F19 E20 D20 Ball Function PR17A PR16B PR16A PR15B PR15A PR14B GND3 PR14A PR13B PR13A PR12B PR12A PR11B PR11A PR9B GND2 PR9A PR8B PR8A PR7B PR7A PR6B PR6A PR5B PR5A PR4B PR4A PR3B PR3A NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Bank LVDS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 T C T C T T C T C T C T C RDQS6 PCLKT2_0 T C T C T C T C PCLKC2_0 T C T C T C RDQS15 Dual Function Ball Number N22 N19 N18 M21 L20 L21 GND M20 M18 M19 M22 L22 K22 K21 J22 GND J21 H22 H21 L19 L18 K20 J20 K19 GND K18 G22 F22 F21 E22 E21 D22 G21 G20 J18 H19 J19 H20 H17 H18 D21 GND C22 G19 G18 F20 F19 E20 D20 LFECP10/LFEC10 Ball Function PR26A PR25B PR25A PR24B PR24A PR23B GND3 PR23A PR22B PR22A PR21B PR21A PR20B PR20A PR18B GND2 PR18A PR17B PR17A PR16B PR16A PR15B PR15A PR14B GND2 PR14A PR13B PR13A PR12B PR12A PR11B PR11A NC NC NC NC NC NC NC NC PR9B GND2 PR9A PR8B PR8A PR7B PR7A PR6B PR6A Bank LVDS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 T C T C T C T RDQS6 RUM0_PLLT_FB_A RUM0_PLLC_IN_A RUM0_PLLT_IN_A C RUM0_PLLC_FB_A T C T C T C T T C T C T C T C RDQS15 PCLKT2_0 T C T C T C T C PCLKC2_0 T C T C T C RDQS24 Dual Function Ball Number N22 N19 N18 M21 L20 L21 GND M20 M18 M19 M22 L22 K22 K21 J22 GND J21 H22 H21 L19 L18 K20 J20 K19 GND K18 G22 F22 F21 E22 E21 D22 G21 GND G20 J18 H19 J19 H20 H17 H18 D21 GND C22 G19 G18 F20 F19 E20 D20 LFECP/LFEC15 Ball Function PR30A PR29B PR29A PR28B PR28A PR27B GND3 PR27A PR26B PR26A PR25B PR25A PR24B PR24A PR22B GND2 PR22A PR21B PR21A PR20B PR20A PR19B PR19A PR18B GND2 PR18A PR17B PR17A PR16B PR16A PR15B PR15A PR14B GND2 PR14A PR13B PR13A PR12B PR12A PR11B PR11A PR9B GND2 PR9A PR8B PR8A PR7B PR7A PR6B PR6A Bank LVDS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 T C T C T C T RDQS6 RUM0_PLLT_FB_A RUM0_PLLC_IN_A RUM0_PLLT_IN_A T C T C T C T C RUM0_PLLC_FB_A T C T C T C T C T C T C T C T C RDQS19 PCLKT2_0 T C T C T C T C PCLKC2_0 T C T C T C RDQS28 Dual Function 4-43 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFECP/EC6, LFECP/EC10, LFECP/EC15 Logic Signal Connections: 484 fpBGA (Cont.) LFECP6/LFEC6 Ball Number C21 C20 F18 E18 B22 B21 E19 D19 GND GND G17 F17 D18 C18 C19 B20 D17 C16 B19 GND A20 E17 C17 F16 E16 F15 D16 B18 GND A19 B17 A18 B16 A17 B15 A16 A15 GND A14 G14 E15 D15 C15 C14 B14 A13 GND B13 E14 C13 Ball Function NC NC NC NC NC NC PR2B PR2A GND2 GND1 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC PT33B PT33A PT32B PT32A PT31B PT31A PT30B PT30A PT29B GND1 PT29A PT28B PT28A PT27B PT27A PT26B PT26A PT25B GND1 PT25A PT24B PT24A Bank LVDS 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 T C T T C T C T C T C T C T C T C T C TDQS30 C C T VREF1_2 VREF2_2 Dual Function Ball Number C21 C20 F18 E18 B22 B21 E19 D19 GND GND G17 F17 D18 C18 C19 B20 D17 C16 B19 GND A20 E17 C17 F16 E16 F15 D16 B18 GND A19 B17 A18 B16 A17 B15 A16 A15 GND A14 G14 E15 D15 C15 C14 B14 A13 GND B13 E14 C13 LFECP10/LFEC10 Ball Function PR5B PR5A PR4B PR4A PR3B PR3A PR2B PR2A GND2 GND1 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC PT41B PT41A PT40B PT40A PT39B PT39A PT38B PT38A PT37B GND1 PT37A PT36B PT36A PT35B PT35A PT34B PT34A PT33B GND1 PT33A PT32B PT32A Bank LVDS 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 T C T T C T C T C T C T C T C T C T C TDQS38 C C T C T C T C T VREF1_2 VREF2_2 Dual Function Ball Number C21 C20 F18 E18 B22 B21 E19 D19 GND GND G17 F17 D18 C18 C19 B20 D17 C16 B19 GND A20 E17 C17 F16 E16 F15 D16 B18 GND A19 B17 A18 B16 A17 B15 A16 A15 GND A14 G14 E15 D15 C15 C14 B14 A13 GND B13 E14 C13 LFECP/LFEC15 Ball Function PR5B PR5A PR4B PR4A PR3B PR3A PR2B PR2A GND2 GND1 PT49B PT49A PT48B PT48A PT47B PT47A PT46B PT46A PT45B GND1 PT45A PT44B PT44A PT43B PT43A PT42B PT42A PT41B GND1 PT41A PT40B PT40A PT39B PT39A PT38B PT38A PT37B GND1 PT37A PT36B PT36A PT35B PT35A PT34B PT34A PT33B GND1 PT33A PT32B PT32A Bank LVDS 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 T C T T C T C T C T C T C T C T C T C TDQS38 T C T C T C T C C T C T C T C T C TDQS46 C T C T C T C T VREF1_2 VREF2_2 Dual Function 4-44 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFECP/EC6, LFECP/EC10, LFECP/EC15 Logic Signal Connections: 484 fpBGA (Cont.) LFECP6/LFEC6 Ball Number F14 D14 E13 G13 A12 GND B12 F13 D13 F12 D12 F11 C12 A11 GND A10 E12 E11 B11 C11 B9 B10 A9 GND A8 D11 C10 A7 A6 B7 B8 A5 GND B6 G10 E10 F10 D10 G9 E9 C9 GND C8 F9 D9 F8 D7 D8 C7 GND Ball Function PT23B PT23A PT22B PT22A PT21B GND1 PT21A PT20B PT20A PT19B PT19A PT18B PT18A PT17B GND0 PT17A PT16B PT16A PT15B PT15A PT14B PT14A PT13B GND0 PT13A PT12B PT12A PT11B PT11A PT10B PT10A PT9B GND0 PT9A PT8B PT8A PT7B PT7A PT6B PT6A PT5B PT5A PT4B PT4A PT3B PT3A PT2B PT2A GND0 Bank LVDS 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T C T C T C T T C T C T C T C TDQS6 T C T C T C T C T C T C T C T C TDQS14 PCLKT0_0 VREF1_0 VREF2_0 T C T C T C T C PCLKC0_0 VREF2_1 VREF1_1 C T C T C TDQS22 Dual Function Ball Number F14 D14 E13 G13 A12 GND B12 F13 D13 F12 D12 F11 C12 A11 GND A10 E12 E11 B11 C11 B9 B10 A9 GND A8 D11 C10 A7 A6 B7 B8 A5 GND B6 G10 E10 F10 D10 G9 E9 C9 GND C8 F9 D9 F8 D7 D8 C7 GND LFECP10/LFEC10 Ball Function PT31B PT31A PT30B PT30A PT29B GND1 PT29A PT28B PT28A PT27B PT27A PT26B PT26A PT25B GND0 PT25A PT24B PT24A PT23B PT23A PT22B PT22A PT21B GND0 PT21A PT20B PT20A PT19B PT19A PT18B PT18A PT17B GND0 PT17A PT16B PT16A PT15B PT15A PT14B PT14A PT13B GND0 PT13A PT12B PT12A PT11B PT11A PT10B PT10A GND0 Bank LVDS 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T C T C T C T T C T C T C T C TDQS14 T C T C T C T C T C T C T C T C TDQS22 PCLKT0_0 VREF1_0 VREF2_0 T C T C T C T C PCLKC0_0 VREF2_1 VREF1_1 C T C T C TDQS30 Dual Function Ball Number F14 D14 E13 G13 A12 GND B12 F13 D13 F12 D12 F11 C12 A11 GND A10 E12 E11 B11 C11 B9 B10 A9 GND A8 D11 C10 A7 A6 B7 B8 A5 GND B6 G10 E10 F10 D10 G9 E9 C9 GND C8 F9 D9 F8 D7 D8 C7 GND LFECP/LFEC15 Ball Function PT31B PT31A PT30B PT30A PT29B GND1 PT29A PT28B PT28A PT27B PT27A PT26B PT26A PT25B GND0 PT25A PT24B PT24A PT23B PT23A PT22B PT22A PT21B GND0 PT21A PT20B PT20A PT19B PT19A PT18B PT18A PT17B GND0 PT17A PT16B PT16A PT15B PT15A PT14B PT14A PT13B GND0 PT13A PT12B PT12A PT11B PT11A PT10B PT10A GND0 Bank LVDS 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T C T C T C T T C T C T C T C TDQS14 T C T C T C T C T C T C T C T C TDQS22 PCLKT0_0 VREF1_0 VREF2_0 T C T C T C T C PCLKC0_0 VREF2_1 VREF1_1 C T C T C TDQS30 Dual Function 4-45 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFECP/EC6, LFECP/EC10, LFECP/EC15 Logic Signal Connections: 484 fpBGA (Cont.) LFECP6/LFEC6 Ball Number A4 B4 C4 C5 D6 B5 E6 C6 A3 B3 F6 D5 F7 E8 G6 E7 GND A1 A22 AB1 AB22 H15 H8 J10 J11 J12 J13 J14 J9 K10 K11 K12 K13 K14 K9 L10 L11 L12 L13 L14 L9 M10 M11 M12 M13 M14 M9 N10 N11 N12 Ball Function NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Bank LVDS Dual Function Ball Number A4 B4 C4 C5 D6 B5 E6 C6 A3 B3 F6 D5 F7 E8 G6 E7 GND A1 A22 AB1 AB22 H15 H8 J10 J11 J12 J13 J14 J9 K10 K11 K12 K13 K14 K9 L10 L11 L12 L13 L14 L9 M10 M11 M12 M13 M14 M9 N10 N11 N12 LFECP10/LFEC10 Ball Function PT9B PT9A PT8B PT8A PT7B PT7A PT6B PT6A PT5B PT5A PT4B PT4A PT3B PT3A PT2B PT2A GND0 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Bank LVDS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C T C T C T C T C T C T C T C T TDQS6 Dual Function Ball Number A4 B4 C4 C5 D6 B5 E6 C6 A3 B3 F6 D5 F7 E8 G6 E7 GND A1 A22 AB1 AB22 H15 H8 J10 J11 J12 J13 J14 J9 K10 K11 K12 K13 K14 K9 L10 L11 L12 L13 L14 L9 M10 M11 M12 M13 M14 M9 N10 N11 N12 LFECP/LFEC15 Ball Function PT9B PT9A PT8B PT8A PT7B PT7A PT6B PT6A PT5B PT5A PT4B PT4A PT3B PT3A PT2B PT2A GND0 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Bank LVDS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C T C T C T C T C T C T C T C T TDQS6 Dual Function 4-46 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFECP/EC6, LFECP/EC10, LFECP/EC15 Logic Signal Connections: 484 fpBGA (Cont.) LFECP6/LFEC6 Ball Number N13 N14 N9 P10 P11 P12 P13 P14 P9 R15 R8 J16 J7 K16 K17 K6 K7 L17 L6 M17 M6 N16 N17 N6 N7 P16 P7 G11 H10 H11 H9 G12 H12 H13 H14 J15 K15 L15 L16 M15 M16 N15 P15 R12 R13 R14 T12 R10 R11 R9 Ball Function GND GND GND GND GND GND GND GND GND GND GND VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO5 VCCIO5 VCCIO5 Bank LVDS 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3 4 4 4 4 5 5 5 Dual Function Ball Number N13 N14 N9 P10 P11 P12 P13 P14 P9 R15 R8 J16 J7 K16 K17 K6 K7 L17 L6 M17 M6 N16 N17 N6 N7 P16 P7 G11 H10 H11 H9 G12 H12 H13 H14 J15 K15 L15 L16 M15 M16 N15 P15 R12 R13 R14 T12 R10 R11 R9 LFECP10/LFEC10 Ball Function GND GND GND GND GND GND GND GND GND GND GND VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO5 VCCIO5 VCCIO5 Bank LVDS 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3 4 4 4 4 5 5 5 Dual Function Ball Number N13 N14 N9 P10 P11 P12 P13 P14 P9 R15 R8 J16 J7 K16 K17 K6 K7 L17 L6 M17 M6 N16 N17 N6 N7 P16 P7 G11 H10 H11 H9 G12 H12 H13 H14 J15 K15 L15 L16 M15 M16 N15 P15 R12 R13 R14 T12 R10 R11 R9 LFECP/LFEC15 Ball Function GND GND GND GND GND GND GND GND GND GND GND VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO5 VCCIO5 VCCIO5 Bank LVDS 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3 4 4 4 4 5 5 5 Dual Function 4-47 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFECP/EC6, LFECP/EC10, LFECP/EC15 Logic Signal Connections: 484 fpBGA (Cont.) LFECP6/LFEC6 Ball Number T11 M7 M8 N8 P8 J8 K8 L7 L8 G15 G16 G7 G8 H16 H7 R16 R7 T15 T16 T7 T8 J6 J17 P6 P17 A2 AB2 A21 Ball Function VCCIO5 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCC VCC VCC VCC NC NC NC Bank LVDS 5 6 6 6 6 7 7 7 7 Dual Function Ball Number T11 M7 M8 N8 P8 J8 K8 L7 L8 G15 G16 G7 G8 H16 H7 R16 R7 T15 T16 T7 T8 J6 J17 P6 P17 A2 AB2 A21 LFECP10/LFEC10 Ball Function VCCIO5 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCC VCC VCC VCC NC NC NC Bank LVDS 5 6 6 6 6 7 7 7 7 Dual Function Ball Number T11 M7 M8 N8 P8 J8 K8 L7 L8 G15 G16 G7 G8 H16 H7 R16 R7 T15 T16 T7 T8 J6 J17 P6 P17 A2 AB2 A21 LFECP/LFEC15 Ball Function VCCIO5 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCC VCC VCC VCC NC NC NC Bank LVDS 5 6 6 6 6 7 7 7 7 Dual Function 4-48 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFECP/EC20 and LFECP/EC33 Logic Signal Connections: 484 fpBGA LFECP20/LFEC20 Ball Number GND D4 E4 GND C3 B2 E5 F5 D3 C2 GND F4 G4 E3 D2 B1 C1 F3 GND E2 GND G5 H6 G3 H4 J5 H5 F2 GND F1 E1 D1 H3 G2 H2 G1 J4 GND J3 J2 H1 K4 K5 K3 Ball Function Bank LVDS GND7 PL2A PL2B PL3A PL3B PL4A PL4B PL5A PL5B PL6A PL6B PL7A PL7B PL8A PL8B PL9A GND7 PL9B PL11A PL11B PL12A PL12B PL13A PL13B PL14A GND7 PL14B PL15A PL15B PL16A PL16B PL17A PL17B PL18A GND7 PL18B PL19A PL19B PL20A PL20B PL21A 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 C T C T C T LDQS19 C T C T C T C T T C T C T C T C LUM0_PLLC_FB_A T C T C T C T LUM0_PLLT_IN_A LUM0_PLLC_IN_A LUM0_PLLT_FB_A LDQS6 T C T C T C T C VREF2_7 VREF1_7 Dual Function GND D4 E4 GND C3 B2 E5 F5 D3 C2 GND F4 G4 E3 D2 B1 C1 F3 GND E2 GND G5 H6 G3 H4 J5 H5 F2 GND F1 E1 D1 H3 G2 H2 G1 J4 GND J3 J2 H1 K4 K5 K3 LFECP/LFEC33 Ball Number Ball Function Bank LVDS GND7 PL2A PL2B GND7 PL10A PL10B PL11A PL11B PL12A PL12B GND7 PL14A PL14B PL15A PL15B PL16A PL16B PL17A GND7 PL17B GND7 PL23A PL23B PL24A PL24B PL25A PL25B PL26A GND7 PL26B PL27A PL27B PL28A PL28B PL29A PL29B PL30A GND7 PL30B PL31A PL31B PL32A PL32B PL33A 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 C T C T C T LDQS31 C T C T C T C T T C T C T C T LDQS23 C LUM0_PLLC_FB_A T C T C T C T LUM0_PLLT_IN_A LUM0_PLLC_IN_A LUM0_PLLT_FB_A LDQS14 T C T C T C T C VREF2_7 VREF1_7 Dual Function 4-49 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFECP/EC20 and LFECP/EC33 Logic Signal Connections: 484 fpBGA LFECP20/LFEC20 Ball Number K2 J1 GND K1 L3 L4 L5 L2 L1 M4 M5 M1 GND M2 N3 M3 N5 N4 N1 N2 P1 GND P2 R6 P5 P3 P4 R1 R2 R5 GND R4 T1 T2 R3 T3 GND T5 U5 T4 U1 U2 V1 V2 Ball Function Bank LVDS PL21B PL22A GND7 PL22B XRES PL24A PL24B PL25A PL25B PL26A PL26B PL27A GND6 PL27B PL28A PL28B PL29A PL29B PL30A PL30B PL31A GND6 PL31B PL32A PL32B PL33A PL33B PL34A PL34B PL35A GND6 PL35B PL36A PL36B PL37A PL37B GND6 TCK TDI TMS TDO VCCJ PL41A PL41B 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 T C LLM0_PLLT_IN_A LLM0_PLLC_IN_A C T C T C LDQS36 C T C T C T C T C T C T C T C T LDQS28 T C T C T C T C PCLKC7_0 C T PCLKT7_0 Dual Function K2 J1 GND K1 L3 L4 L5 L2 L1 M4 M5 M1 GND M2 N3 M3 N5 N4 N1 N2 P1 GND P2 R6 P5 P3 P4 R1 R2 R5 GND R4 T1 T2 R3 T3 GND T5 U5 T4 U1 U2 V1 V2 LFECP/LFEC33 Ball Number Ball Function Bank LVDS PL33B PL34A GND7 PL34B XRES PL36A PL36B PL37A PL37B PL38A PL38B PL39A GND6 PL39B PL40A PL40B PL41A PL41B PL42A PL42B PL43A GND6 PL43B PL44A PL44B PL45A PL45B PL46A PL46B PL47A GND6 PL47B PL48A PL48B PL49A PL49B GND6 TCK TDI TMS TDO VCCJ PL53A PL53B 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 T C LLM0_PLLT_IN_A LLM0_PLLC_IN_A C T C T C LDQS48 C T C T C T C T C T C T C T C T LDQS40 T C T C T C T C PCLKC7_0 C T PCLKT7_0 Dual Function 4-50 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFECP/EC20 and LFECP/EC33 Logic Signal Connections: 484 fpBGA LFECP20/LFEC20 Ball Number U3 V3 U4 V5 W1 GND W2 Y1 Y2 AA1 AA2 W4 V4 W3 Y3 GND GND GND GND GND V7 T6 V8 U7 W5 U6 AA3 GND AB3 Y6 V6 AA5 W6 Y5 Y4 AA4 GND AB4 Y7 W8 W7 U8 W9 U9 Ball Function Bank LVDS PL42A PL42B PL43A PL43B PL44A GND6 PL44B PL45A PL45B PL46A PL46B PL47A PL47B PL48A PL48B GND6 GND5 GND5 PB10A PB10B PB11A PB11B PB12A PB12B PB13A GND5 PB13B PB14A PB14B PB15A PB15B PB16A PB16B PB17A GND5 PB17B PB18A PB18B PB19A PB19B PB20A PB20B 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 C T C T C T C C T C T C T C T BDQS14 T C T C T C T 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 5 C T C T C T C T C VREF1_6 VREF2_6 LDQS45 T C T C T Dual Function LLM0_PLLT_FB_A LLM0_PLLC_FB_A U3 V3 U4 V5 W1 GND W2 Y1 Y2 AA1 AA2 W4 V4 W3 Y3 GND GND GND GND GND V7 T6 V8 U7 W5 U6 AA3 GND AB3 Y6 V6 AA5 W6 Y5 Y4 AA4 GND AB4 Y7 W8 W7 U8 W9 U9 LFECP/LFEC33 Ball Number Ball Function Bank LVDS PL54A PL54B PL55A PL55B PL56A GND6 PL56B PL57A PL57B PL58A PL58B PL59A PL59B PL68A PL68B GND6 GND6 GND6 GND5 GND5 PB10A PB10B PB11A PB11B PB12A PB12B PB13A GND5 PB13B PB14A PB14B PB15A PB15B PB16A PB16B PB17A GND5 PB17B PB18A PB18B PB19A PB19B PB20A PB20B 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 C T C T C T C C T C T C T C T BDQS14 T C T C T C T C T C T C T C T C VREF1_6 VREF2_6 LDQS57 T C T C T Dual Function LLM0_PLLT_FB_A LLM0_PLLC_FB_A 4-51 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFECP/EC20 and LFECP/EC33 Logic Signal Connections: 484 fpBGA LFECP20/LFEC20 Ball Number Y8 GND Y9 V9 T9 W10 U10 V10 T10 AA6 GND AB5 AA8 AA7 AB6 AB7 Y10 W11 AB8 GND AB9 AA10 AA9 Y11 AA11 V11 V12 AB10 GND AB11 Y12 U11 W12 U12 W13 U13 AA12 GND AB12 T13 V13 W14 U14 Y13 Ball Function Bank LVDS PB21A GND5 PB21B PB22A PB22B PB23A PB23B PB24A PB24B PB25A GND5 PB25B PB26A PB26B PB27A PB27B PB28A PB28B PB29A GND5 PB29B PB30A PB30B PB31A PB31B PB32A PB32B PB33A GND5 PB33B PB34A PB34B PB35A PB35B PB36A PB36B PB37A GND4 PB37B PB38A PB38B PB39A PB39B PB40A 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 C T C T C T D4/SPID3 D1/SPID6 BDQS38 D3/SPID4 C T C T C T C T PCLKC5_0 WRITEN CS1N VREF1_4 CSN VREF2_4 D0/SPID7 D2/SPID5 C T C T C T C T VREF2_5 VREF1_5 PCLKT5_0 BDQS30 C T C T C T C T C T C T C T C T BDQS22 T Dual Function Y8 GND Y9 V9 T9 W10 U10 V10 T10 AA6 GND AB5 AA8 AA7 AB6 AB7 Y10 W11 AB8 GND AB9 AA10 AA9 Y11 AA11 V11 V12 AB10 GND AB11 Y12 U11 W12 U12 W13 U13 AA12 GND AB12 T13 V13 W14 U14 Y13 LFECP/LFEC33 Ball Number Ball Function Bank LVDS PB21A GND5 PB21B PB22A PB22B PB23A PB23B PB24A PB24B PB25A GND5 PB25B PB26A PB26B PB27A PB27B PB28A PB28B PB29A GND5 PB29B PB30A PB30B PB31A PB31B PB32A PB32B PB33A GND5 PB33B PB34A PB34B PB35A PB35B PB36A PB36B PB37A GND4 PB37B PB38A PB38B PB39A PB39B PB40A 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 C T C T C T D4/SPID3 D1/SPID6 BDQS38 D3/SPID4 C T C T C T C T PCLKC5_0 WRITEN CS1N VREF1_4 CSN VREF2_4 D0/SPID7 D2/SPID5 C T C T C T C T VREF2_5 VREF1_5 PCLKT5_0 BDQS30 C T C T C T C T C T C T C T C T BDQS22 T Dual Function 4-52 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFECP/EC20 and LFECP/EC33 Logic Signal Connections: 484 fpBGA LFECP20/LFEC20 Ball Number V14 AA13 GND AB13 AA14 Y14 Y15 W15 V15 T14 AB14 GND AB15 AB16 AA15 AB17 AA16 AB18 AA17 AB19 GND AA18 W16 U15 V16 U16 Y17 V17 AB20 GND AA19 Y16 W17 AA20 Y19 Y18 W18 T17 U17 GND GND GND GND W20 Ball Function Bank LVDS PB40B PB41A GND4 PB41B PB42A PB42B PB43A PB43B PB44A PB44B PB45A GND4 PB45B PB46A PB46B PB47A PB47B PB48A PB48B PB49A GND4 PB49B PB50A PB50B PB51A PB51B PB52A PB52B PB53A GND4 PB53B PB54A PB54B PB55A PB55B PB56A PB56B PB57A PB57B GND4 GND3 PR48B 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 3 3 C VREF2_3 C T C T C T C T C BDQS54 C T C T C T C T C T C T C T C T BDQS46 C T C T C T C T D6/SPID1 C T Dual Function D5/SPID2 V14 AA13 GND AB13 AA14 Y14 Y15 W15 V15 T14 AB14 GND AB15 AB16 AA15 AB17 AA16 AB18 AA17 AB19 GND AA18 W16 U15 V16 U16 Y17 V17 AB20 GND AA19 Y16 W17 AA20 Y19 Y18 W18 T17 U17 GND GND GND GND W20 LFECP/LFEC33 Ball Number Ball Function Bank LVDS PB40B PB41A GND4 PB41B PB42A PB42B PB43A PB43B PB44A PB44B PB45A GND4 PB45B PB46A PB46B PB47A PB47B PB48A PB48B PB49A GND4 PB49B PB50A PB50B PB51A PB51B PB52A PB52B PB53A GND4 PB53B PB54A PB54B PB55A PB55B PB56A PB56B PB57A PB57B GND4 GND4 GND4 GND3 PR68B 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 3 3 C VREF2_3 C T C T C T C T C BDQS54 C T C T C T C T C T C T C T C T BDQS46 C T C T C T C T D6/SPID1 C T Dual Function D5/SPID2 4-53 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFECP/EC20 and LFECP/EC33 Logic Signal Connections: 484 fpBGA LFECP20/LFEC20 Ball Number Y20 GND GND AA21 AB21 W19 V19 Y21 AA22 V20 GND U20 W21 Y22 V21 W22 U21 V22 T19 U19 U18 V18 T20 T21 R20 GND T18 R17 R19 R18 U22 GND T22 R21 R22 P20 N20 P19 P18 P21 GND P22 N21 N22 Ball Function Bank LVDS PR48A PR47B PR47A PR46B PR46A PR45B PR45A PR44B GND3 PR44A PR43B PR43A PR42B PR42A PR41B PR41A CFG2 CFG1 CFG0 PROGRAMN CCLK INITN DONE GND3 PR37B PR37A PR36B PR36A PR35B GND3 PR35A PR34B PR34A PR33B PR33A PR32B PR32A PR31B GND3 PR31A PR30B PR30A 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 T C T T C T C T C T C C T C T C RDQS36 T C T C T C T RLM0_PLLT_IN_A RLM0_PLLC_FB_A RLM0_PLLT_FB_A DI/CSSPIN DOUT/CSON BUSY/SISPI D7/SPID0 C T C T C T C RDQS45 RLM0_PLLC_IN_A T Dual Function VREF1_3 Y20 GND GND AA21 AB21 W19 V19 Y21 AA22 V20 GND U20 W21 Y22 V21 W22 U21 V22 T19 U19 U18 V18 T20 T21 R20 GND T18 R17 R19 R18 U22 GND T22 R21 R22 P20 N20 P19 P18 P21 GND P22 N21 N22 LFECP/LFEC33 Ball Number Ball Function Bank LVDS PR68A GND3 GND3 PR59B PR59A PR58B PR58A PR57B PR57A PR56B GND3 PR56A PR55B PR55A PR54B PR54A PR53B PR53A CFG2 CFG1 CFG0 PROGRAMN CCLK INITN DONE GND3 PR49B PR49A PR48B PR48A PR47B GND3 PR47A PR46B PR46A PR45B PR45A PR44B PR44A PR43B GND3 PR43A PR42B PR42A 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 T C T T C T C T C T C C T C T C RDQS48 T C T C T C T RLM0_PLLT_IN_A RLM0_PLLC_FB_A RLM0_PLLT_FB_A DI/CSSPIN DOUT/CSON BUSY/SISPI D7/SPID0 C T C T C T C RDQS57 RLM0_PLLC_IN_A T Dual Function VREF1_3 4-54 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFECP/EC20 and LFECP/EC33 Logic Signal Connections: 484 fpBGA LFECP20/LFEC20 Ball Number N19 N18 M21 L20 L21 GND M20 M18 M19 M22 L22 K22 K21 J22 GND J21 H22 H21 L19 L18 K20 J20 K19 GND K18 G22 F22 F21 E22 E21 D22 G21 G20 GND J18 H19 J19 H20 H17 H18 D21 GND GND C22 Ball Function Bank LVDS PR29B PR29A PR28B PR28A PR27B GND3 PR27A PR26B PR26A PR25B PR25A PR24B PR24A PR22B GND2 PR22A PR21B PR21A PR20B PR20A PR19B PR19A PR18B GND2 PR18A PR17B PR17A PR16B PR16A PR15B PR15A PR14B PR14A GND2 PR13B PR13A PR12B PR12A PR11B PR11A PR9B GND2 PR9A 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 T RUM0_PLLT_FB_A C T C T C T C RUM0_PLLC_FB_A T C T C T C T C T T C T C T C T C RDQS19 PCLKT2_0 T C T C T C T C PCLKC2_0 C T C T C RDQS28 Dual Function N19 N18 M21 L20 L21 GND M20 M18 M19 M22 L22 K22 K21 J22 GND J21 H22 H21 L19 L18 K20 J20 K19 GND K18 G22 F22 F21 E22 E21 D22 G21 G20 GND J18 H19 J19 H20 H17 H18 D21 GND GND C22 LFECP/LFEC33 Ball Number Ball Function Bank LVDS PR41B PR41A PR40B PR40A PR39B GND3 PR39A PR38B PR38A PR37B PR37A PR36B PR36A PR34B GND2 PR34A PR33B PR33A PR32B PR32A PR31B PR31A PR30B GND2 PR30A PR29B PR29A PR28B PR28A PR27B PR27A PR26B PR26A GND2 PR25B PR25A PR24B PR24A PR23B PR23A PR17B GND2 GND2 PR17A 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 T RUM0_PLLT_FB_A C T C T C T C RDQS23 RUM0_PLLC_FB_A T C T C T C T C T T C T C T C T C RDQS31 PCLKT2_0 T C T C T C T C PCLKC2_0 C T C T C RDQS40 Dual Function 4-55 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFECP/EC20 and LFECP/EC33 Logic Signal Connections: 484 fpBGA LFECP20/LFEC20 Ball Number G19 G18 F20 F19 E20 D20 C21 GND C20 F18 E18 B22 B21 GND E19 D19 GND GND GND G17 GND F17 D18 C18 C19 B20 D17 C16 B19 GND A20 E17 C17 F16 E16 F15 D16 B18 GND A19 B17 A18 B16 A17 Ball Function Bank LVDS PR8B PR8A PR7B PR7A PR6B PR6A PR5B PR5A PR4B PR4A PR3B PR3A PR2B PR2A GND2 GND1 PT57B PT57A PT56B PT56A PT55B PT55A PT54B PT54A PT53B GND1 PT53A PT52B PT52A PT51B PT51A PT50B PT50A PT49B GND1 PT49A PT48B PT48A PT47B PT47A 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 T C T C T T C T C T C T C T C T C T C T C TDQS54 C C T VREF1_2 VREF2_2 T C T C T C T C T C T C RDQS6 Dual Function RUM0_PLLC_IN_A RUM0_PLLT_IN_A G19 G18 F20 F19 E20 D20 C21 GND C20 F18 E18 B22 B21 GND E19 D19 GND GND GND G17 GND F17 D18 C18 C19 B20 D17 C16 B19 GND A20 E17 C17 F16 E16 F15 D16 B18 GND A19 B17 A18 B16 A17 LFECP/LFEC33 Ball Number Ball Function Bank LVDS PR16B PR16A PR15B PR15A PR14B PR14A PR13B GND2 PR13A PR12B PR12A PR11B PR11A GND2 PR2B PR2A GND2 GND1 GND1 PT57B GND1 PT57A PT56B PT56A PT55B PT55A PT54B PT54A PT53B GND1 PT53A PT52B PT52A PT51B PT51A PT50B PT50A PT49B GND1 PT49A PT48B PT48A PT47B PT47A 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 T C T C T T C T C T C T C T C T C T C T C TDQS54 C C T VREF1_2 VREF2_2 T C T C T C T C T C T C RDQS14 Dual Function RUM0_PLLC_IN_A RUM0_PLLT_IN_A 4-56 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFECP/EC20 and LFECP/EC33 Logic Signal Connections: 484 fpBGA LFECP20/LFEC20 Ball Number B15 A16 A15 GND A14 G14 E15 D15 C15 C14 B14 A13 GND B13 E14 C13 F14 D14 E13 G13 A12 GND B12 F13 D13 F12 D12 F11 C12 A11 GND A10 E12 E11 B11 C11 B9 B10 A9 GND A8 D11 C10 A7 Ball Function Bank LVDS PT46B PT46A PT45B GND1 PT45A PT44B PT44A PT43B PT43A PT42B PT42A PT41B GND1 PT41A PT40B PT40A PT39B PT39A PT38B PT38A PT37B GND1 PT37A PT36B PT36A PT35B PT35A PT34B PT34A PT33B GND0 PT33A PT32B PT32A PT31B PT31A PT30B PT30A PT29B GND0 PT29A PT28B PT28A PT27B 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T C T C T C T C T C T C TDQS30 PCLKT0_0 VREF1_0 VREF2_0 T C T C T C T C PCLKC0_0 VREF2_1 VREF1_1 T C T C T C T C TDQS38 T C T C T C T C C T C TDQS46 Dual Function B15 A16 A15 GND A14 G14 E15 D15 C15 C14 B14 A13 GND B13 E14 C13 F14 D14 E13 G13 A12 GND B12 F13 D13 F12 D12 F11 C12 A11 GND A10 E12 E11 B11 C11 B9 B10 A9 GND A8 D11 C10 A7 LFECP/LFEC33 Ball Number Ball Function Bank LVDS PT46B PT46A PT45B GND1 PT45A PT44B PT44A PT43B PT43A PT42B PT42A PT41B GND1 PT41A PT40B PT40A PT39B PT39A PT38B PT38A PT37B GND1 PT37A PT36B PT36A PT35B PT35A PT34B PT34A PT33B GND0 PT33A PT32B PT32A PT31B PT31A PT30B PT30A PT29B GND0 PT29A PT28B PT28A PT27B 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T C T C T C T C T C T C TDQS30 PCLKT0_0 VREF1_0 VREF2_0 T C T C T C T C PCLKC0_0 VREF2_1 VREF1_1 T C T C T C T C TDQS38 T C T C T C T C C T C TDQS46 Dual Function 4-57 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFECP/EC20 and LFECP/EC33 Logic Signal Connections: 484 fpBGA LFECP20/LFEC20 Ball Number A6 B7 B8 A5 GND B6 G10 E10 F10 D10 G9 E9 C9 GND C8 F9 D9 F8 D7 D8 C7 GND A4 B4 C4 C5 D6 B5 E6 C6 A3 GND B3 F6 D5 F7 E8 G6 E7 GND GND A1 A22 AB1 Ball Function Bank LVDS PT27A PT26B PT26A PT25B GND0 PT25A PT24B PT24A PT23B PT23A PT22B PT22A PT21B GND0 PT21A PT20B PT20A PT19B PT19A PT18B PT18A GND0 PT17B PT17A PT16B PT16A PT15B PT15A PT14B PT14A PT13B GND0 PT13A PT12B PT12A PT11B PT11A PT10B PT10A GND0 GND0 GND GND GND 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T C T C T C T C T C T C T C T C TDQS14 T C T C T C T T C T C T C T C TDQS22 T C T C Dual Function A6 B7 B8 A5 GND B6 G10 E10 F10 D10 G9 E9 C9 GND C8 F9 D9 F8 D7 D8 C7 GND A4 B4 C4 C5 D6 B5 E6 C6 A3 GND B3 F6 D5 F7 E8 G6 E7 GND GND A1 A22 AB1 LFECP/LFEC33 Ball Number Ball Function Bank LVDS PT27A PT26B PT26A PT25B GND0 PT25A PT24B PT24A PT23B PT23A PT22B PT22A PT21B GND0 PT21A PT20B PT20A PT19B PT19A PT18B PT18A GND0 PT17B PT17A PT16B PT16A PT15B PT15A PT14B PT14A PT13B GND0 PT13A PT12B PT12A PT11B PT11A PT10B PT10A GND0 GND0 GND GND GND 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T C T C T C T C T C T C T C T C TDQS14 T C T C T C T T C T C T C T C TDQS22 T C T C Dual Function 4-58 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFECP/EC20 and LFECP/EC33 Logic Signal Connections: 484 fpBGA LFECP20/LFEC20 Ball Number AB22 H15 H8 J10 J11 J12 J13 J14 J9 K10 K11 K12 K13 K14 K9 L10 L11 L12 L13 L14 L9 M10 M11 M12 M13 M14 M9 N10 N11 N12 N13 N14 N9 P10 P11 P12 P13 P14 P9 R15 R8 J16 J7 K16 Ball Function Bank LVDS GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC VCC VCC Dual Function AB22 H15 H8 J10 J11 J12 J13 J14 J9 K10 K11 K12 K13 K14 K9 L10 L11 L12 L13 L14 L9 M10 M11 M12 M13 M14 M9 N10 N11 N12 N13 N14 N9 P10 P11 P12 P13 P14 P9 R15 R8 J16 J7 K16 LFECP/LFEC33 Ball Number Ball Function Bank LVDS GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC VCC VCC Dual Function 4-59 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFECP/EC20 and LFECP/EC33 Logic Signal Connections: 484 fpBGA LFECP20/LFEC20 Ball Number K17 K6 K7 L17 L6 M17 M6 N16 N17 N6 N7 P16 P7 G11 H10 H11 H9 G12 H12 H13 H14 J15 K15 L15 L16 M15 M16 N15 P15 R12 R13 R14 T12 R10 R11 R9 T11 M7 M8 N8 P8 J8 K8 L7 Ball Function Bank LVDS VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO7 VCCIO7 VCCIO7 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3 4 4 4 4 5 5 5 5 6 6 6 6 7 7 7 Dual Function K17 K6 K7 L17 L6 M17 M6 N16 N17 N6 N7 P16 P7 G11 H10 H11 H9 G12 H12 H13 H14 J15 K15 L15 L16 M15 M16 N15 P15 R12 R13 R14 T12 R10 R11 R9 T11 M7 M8 N8 P8 J8 K8 L7 LFECP/LFEC33 Ball Number Ball Function Bank LVDS VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO7 VCCIO7 VCCIO7 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3 4 4 4 4 5 5 5 5 6 6 6 6 7 7 7 Dual Function 4-60 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFECP/EC20 and LFECP/EC33 Logic Signal Connections: 484 fpBGA LFECP20/LFEC20 Ball Number L8 G15 G16 G7 G8 H16 H7 R16 R7 T15 T16 T7 T8 J6 J17 P6 P17 A2 AB2 A21 1. Tied to VCCPLL. LFECP/LFEC33 Dual Function Ball Number Ball Function Bank LVDS L8 G15 G16 G7 G8 H16 H7 R16 R7 T15 T16 T7 T8 J6 J17 P6 P17 A2 AB2 A21 VCCIO7 VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCPLL VCCPLL VCCPLL VCCPLL NC NC NC 7 Dual Function Ball Function Bank LVDS VCCIO7 VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCC1 VCC1 VCC NC NC NC 1 7 - VCC1 4-61 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA LFEC20/LFECP20 Ball Number GND E3 E4 E5 D5 F4 F5 C3 D3 C2 B2 B1 C1 F3 G3 D2 E2 D1 E1 F2 G2 F6 G6 H4 GND G4 H6 J7 G5 H5 H3 J3 H2 J2 J4 J5 K4 K5 J6 Ball Function GND7 PL2A PL2B NC NC NC NC NC NC NC NC PL3A PL3B PL4A PL4B PL5A PL5B PL6A PL6B PL7A PL7B PL8A PL8B PL9A GND7 PL9B NC NC NC NC NC NC NC NC PL11A PL11B PL12A PL12B PL13A Bank LVDS 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 T C T C T C LUM0_PLLC_FB_A T C T C T C T LUM0_PLLT_IN_A LUM0_PLLC_IN_A LUM0_PLLT_FB_A LDQS6 T C T C T C T C VREF2_7 VREF1_7 Dual Function Ball Number GND E3 E4 E5 D5 F4 F5 C3 D3 C2 GND B2 B1 C1 F3 G3 D2 E2 GND D1 E1 F2 G2 F6 G6 H4 GND G4 H6 J7 G5 H5 H3 J3 H2 GND J2 J4 J5 K4 K5 J6 Ball Function GND7 PL2A PL2B PL6A PL6B PL7A PL7B PL8A PL8B PL9A GND7 PL9B PL10A PL10B PL11A PL11B PL12A PL12B GND7 PL14A PL14B PL15A PL15B PL16A PL16B PL17A GND7 PL17B PL19A PL19B PL20A PL20B PL21A PL21B PL22A GND7 PL22B PL23A PL23B PL24A PL24B PL25A LFECP/EC33 Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 C T C T C T LDQS23 C T C T C T C T LUM0_PLLC_FB_A T C T C T C T LUM0_PLLT_IN_A LUM0_PLLC_IN_A LUM0_PLLT_FB_A LDQS14 C T C T C T C T C T C T C T C T VREF2_7 VREF1_7 LDQS6 LVDS Dual Function 4-62 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.) LFEC20/LFECP20 Ball Number K6 F1 GND G1 H1 J1 K2 K1 K3 L3 L2 GND L1 M3 M4 M1 M2 L4 L5 N2 GND N1 N3 P1 P2 L7 L6 N4 N5 R1 GND R2 P4 P3 M5 M6 T1 T2 R4 GND R3 N6 Ball Function PL13B PL14A GND7 PL14B PL15A PL15B PL16A PL16B PL17A PL17B PL18A GND7 PL18B PL19A PL19B PL20A PL20B PL21A PL21B PL22A GND7 PL22B XRES PL24A PL24B PL25A PL25B PL26A PL26B PL27A GND6 PL27B PL28A PL28B PL29A PL29B PL30A PL30B PL31A GND6 PL31B PL32A Bank LVDS 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 C T C T C T C T C T LDQS28 T C T C T C T C PCLKC7_0 C T C T C T C T PCLKT7_0 LDQS19 C T C T C T C T C T Dual Function Ball Number K6 F1 GND G1 H1 J1 K2 K1 K3 L3 L2 GND L1 M3 M4 M1 M2 L4 L5 N2 GND N1 N3 P1 P2 L7 L6 N4 N5 R1 GND R2 P4 P3 M5 M6 T1 T2 R4 GND R3 N6 Ball Function PL25B PL26A GND7 PL26B PL27A PL27B PL28A PL28B PL29A PL29B PL30A GND7 PL30B PL31A PL31B PL32A PL32B PL33A PL33B PL34A GND7 PL34B XRES PL36A PL36B PL37A PL37B PL38A PL38B PL39A GND6 PL39B PL40A PL40B PL41A PL41B PL42A PL42B PL43A GND6 PL43B PL44A LFECP/EC33 Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 C T C T C T C T C T LDQS40 T C T C T C T C PCLKC7_0 C T C T C T C T PCLKT7_0 LDQS31 C T C T C T C T LVDS C T Dual Function 4-63 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.) LFEC20/LFECP20 Ball Number P5 P6 R5 U1 U2 T3 GND T4 R6 T5 T6 U5 U3 U4 V1 GND V2 U7 V4 V5 V3 U6 W1 W2 V6 W6 Y1 Y2 W3 GND W4 AA1 AB1 Y4 Y3 AC1 AB2 AA2 AA3 W5 Y5 Ball Function PL32B PL33A PL33B PL34A PL34B PL35A GND6 PL35B PL36A PL36B PL37A PL37B PL38A PL38B PL39A GND6 PL39B TCK TDI TMS TDO VCCJ PL41A PL41B PL42A PL42B PL43A PL43B PL44A GND6 PL44B PL45A PL45B PL46A PL46B PL47A PL47B NC NC NC NC Bank LVDS 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 C T C T C T C LDQS45 T C T C T C T LLM0_PLLT_IN_A LLM0_PLLC_IN_A LLM0_PLLT_FB_A LLM0_PLLC_FB_A C C T C T C T C T LDQS36 C T C T C T Dual Function Ball Number P5 P6 R5 U1 U2 T3 GND T4 R6 T5 T6 U5 U3 U4 V1 GND V2 U7 V4 V5 V3 U6 W1 W2 V6 W6 Y1 Y2 W3 GND W4 AA1 AB1 Y4 Y3 AC1 AB2 AA2 GND AA3 W5 Y5 Ball Function PL44B PL45A PL45B PL46A PL46B PL47A GND6 PL47B PL48A PL48B PL49A PL49B PL50A PL50B PL51A GND6 PL51B TCK TDI TMS TDO VCCJ PL53A PL53B PL54A PL54B PL55A PL55B PL56A GND6 PL56B PL57A PL57B PL58A PL58B PL59A PL59B PL60A GND6 PL60B PL61A PL61B LFECP/EC33 Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 C T C C T C T C T C T LDQS57 T C T C T C T LLM0_PLLT_IN_A LLM0_PLLC_IN_A LLM0_PLLT_FB_A LLM0_PLLC_FB_A C C T C T C T C T LDQS48 LVDS C T C T C T Dual Function 4-64 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.) LFEC20/LFECP20 Ball Number Y6 W7 AA4 AB3 AC2 AC3 AA5 AB5 AD3 AD2 AE1 AD1 AB4 AC4 GND GND AB6 AA6 AC7 Y8 AB7 AA7 AC6 AC5 AB8 AC8 AE2 AA8 AF2 Y9 AD5 GND AD4 AD8 AC9 AE3 AB9 AF3 AD9 AE4 GND Ball Function NC NC NC NC NC NC NC NC NC NC NC NC PL48A PL48B GND6 GND5 PB2A PB2B PB3A PB3B PB4A PB4B PB5A PB5B PB6A PB6B PB7A PB7B PB8A PB8B PB9A GND5 PB9B PB10A PB10B PB11A PB11B PB12A PB12B PB13A GND5 Bank LVDS 6 6 6 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 C T C T C T C T T C T C T C T C T C T C T C T BDQS6 T C VREF1_6 VREF2_6 Dual Function Ball Number Y6 W7 AA4 AB3 AC2 GND AC3 AA5 AB5 AD3 AD2 AE1 AD1 AB4 AC4 GND GND AB6 AA6 AC7 Y8 AB7 AA7 AC6 AC5 AB8 AC8 AE2 AA8 AF2 Y9 AD5 GND AD4 AD8 AC9 AE3 AB9 AF3 AD9 AE4 GND Ball Function PL62A PL62B PL63A PL63B PL64A GND6 PL64B PL65A PL65B PL66A PL66B PL67A PL67B PL68A PL68B GND6 GND5 PB2A PB2B PB3A PB3B PB4A PB4B PB5A PB5B PB6A PB6B PB7A PB7B PB8A PB8B PB9A GND5 PB9B PB10A PB10B PB11A PB11B PB12A PB12B PB13A GND5 LFECP/EC33 Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 C T C T C T C T T C T C T C T C T C T C T C T BDQS6 C T C T C T C T C VREF1_6 VREF2_6 LDQS65 LVDS T C T C T Dual Function 4-65 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.) LFEC20/LFECP20 Ball Number AF4 AE5 AA9 AF5 Y10 AD6 AC10 AF6 GND AE6 AF7 AB10 AE7 AD10 AD7 AA10 AF8 GND AF9 AD11 Y11 AE8 AC11 AF10 AB11 AE10 GND AE9 AA11 Y12 AE11 AF11 AF12 AE12 AD12 GND AC12 AA12 AB12 AE13 AF13 AD13 Ball Function PB13B PB14A PB14B PB15A PB15B PB16A PB16B PB17A GND5 PB17B PB18A PB18B PB19A PB19B PB20A PB20B PB21A GND5 PB21B PB22A PB22B PB23A PB23B PB24A PB24B PB25A GND5 PB25B PB26A PB26B PB27A PB27B PB28A PB28B PB29A GND5 PB29B PB30A PB30B PB31A PB31B PB32A Bank LVDS 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 C T C T C T VREF2_5 BDQS30 C T C T C T C T C T C T C T C T BDQS22 C T C T C T C T C T C T C T C T BDQS14 Dual Function Ball Number AF4 AE5 AA9 AF5 Y10 AD6 AC10 AF6 GND AE6 AF7 AB10 AE7 AD10 AD7 AA10 AF8 GND AF9 AD11 Y11 AE8 AC11 AF10 AB11 AE10 GND AE9 AA11 Y12 AE11 AF11 AF12 AE12 AD12 GND AC12 AA12 AB12 AE13 AF13 AD13 Ball Function PB13B PB14A PB14B PB15A PB15B PB16A PB16B PB17A GND5 PB17B PB18A PB18B PB19A PB19B PB20A PB20B PB21A GND5 PB21B PB22A PB22B PB23A PB23B PB24A PB24B PB25A GND5 PB25B PB26A PB26B PB27A PB27B PB28A PB28B PB29A GND5 PB29B PB30A PB30B PB31A PB31B PB32A LFECP/EC33 Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 C T C T C T VREF2_5 BDQS30 C T C T C T C T C T C T C T C T BDQS22 C T C T C T C T LVDS C T C T C T C T BDQS14 Dual Function 4-66 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.) LFEC20/LFECP20 Ball Number AC13 AF14 GND AE14 AA13 AB13 AD14 AA14 AC14 AB14 AF15 GND AE15 AD15 AC15 AF16 Y14 AE16 AB15 AF17 GND AE17 Y15 AA15 AD17 Y16 AD18 AC16 AE18 GND AF18 AD16 AB16 AF19 AA16 AA17 Y17 AF21 GND AF20 AE21 AC17 Ball Function PB32B PB33A GND5 PB33B PB34A PB34B PB35A PB35B PB36A PB36B PB37A GND4 PB37B PB38A PB38B PB39A PB39B PB40A PB40B PB41A GND4 PB41B PB42A PB42B PB43A PB43B PB44A PB44B PB45A GND4 PB45B PB46A PB46B PB47A PB47B PB48A PB48B PB49A GND4 PB49B PB50A PB50B Bank LVDS 5 5 5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 C T C C T C T C T C T BDQS46 C T C T C T C T D6/SPID1 C T C T C T C T D5/SPID2 D4/SPID3 D1/SPID6 BDQS38 D3/SPID4 C T C T C T C T PCLKC5_0 WRITEN CS1N VREF1_4 CSN VREF2_4 D0/SPID7 D2/SPID5 C T Dual Function VREF1_5 PCLKT5_0 Ball Number AC13 AF14 GND AE14 AA13 AB13 AD14 AA14 AC14 AB14 AF15 GND AE15 AD15 AC15 AF16 Y14 AE16 AB15 AF17 GND AE17 Y15 AA15 AD17 Y16 AD18 AC16 AE18 GND AF18 AD16 AB16 AF19 AA16 AA17 Y17 AF21 GND AF20 AE21 AC17 Ball Function PB32B PB33A GND5 PB33B PB34A PB34B PB35A PB35B PB36A PB36B PB37A GND4 PB37B PB38A PB38B PB39A PB39B PB40A PB40B PB41A GND4 PB41B PB42A PB42B PB43A PB43B PB44A PB44B PB45A GND4 PB45B PB46A PB46B PB47A PB47B PB48A PB48B PB49A GND4 PB49B PB50A PB50B LFECP/EC33 Bank 5 5 5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 C T C C T C T C T C T BDQS46 C T C T C T C T D6/SPID1 C T C T C T C T D5/SPID2 D4/SPID3 D1/SPID6 BDQS38 D3/SPID4 C T C T C T C T PCLKC5_0 WRITEN CS1N VREF1_4 CSN VREF2_4 D0/SPID7 D2/SPID5 LVDS C T Dual Function VREF1_5 PCLKT5_0 4-67 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.) LFEC20/LFECP20 Ball Number AF22 AB17 AE22 AA18 AE19 GND AE20 AA19 Y18 AF23 AA20 AC18 AB18 AF24 AE23 AD19 AD20 AC19 AB19 AD21 AC20 AF25 AE25 AB21 AB20 AE24 AD23 AD22 AC21 AC22 AB22 GND GND AC23 AC24 AD24 AD25 AE26 AD26 Y20 Ball Function PB51A PB51B PB52A PB52B PB53A GND4 PB53B PB54A PB54B PB55A PB55B PB56A PB56B PB57A PB57B NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC GND4 GND3 PR48B PR48A NC NC NC NC NC Bank LVDS 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 3 3 3 C T VREF2_3 VREF1_3 C C T C T C T C T BDQS54 T C T C T Dual Function Ball Number AF22 AB17 AE22 AA18 AE19 GND AE20 AA19 Y18 AF23 AA20 AC18 AB18 AF24 GND AE23 AD19 AD20 AC19 AB19 AD21 AC20 AF25 GND AE25 AB21 AB20 AE24 AD23 AD22 AC21 AC22 AB22 GND GND AC23 AC24 AD24 AD25 AE26 AD26 Y20 Ball Function PB51A PB51B PB52A PB52B PB53A GND4 PB53B PB54A PB54B PB55A PB55B PB56A PB56B PB57A GND4 PB57B PB58A PB58B PB59A PB59B PB60A PB60B PB61A GND4 PB61B PB62A PB62B PB63A PB63B PB64A PB64B PB65A PB65B GND4 GND3 PR68B PR68A PR67B PR67A PR66B PR66A PR65B LFECP/EC33 Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 C T C T C T C VREF2_3 VREF1_3 C T C T C T C T C BDQS62 C T C T C T C T C T C T C T C T BDQS54 LVDS T C T C T Dual Function 4-68 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.) LFEC20/LFECP20 Ball Number Y19 AA23 AA22 AB23 AB24 Y21 AA21 Y23 Y22 AA24 Y24 AC25 AC26 AB25 AA25 AB26 AA26 W23 GND W24 W22 W21 Y25 Y26 W25 W26 V24 V21 V23 V22 V20 V25 U20 V26 GND U26 U24 U25 U23 U22 Ball Function NC NC NC NC NC NC NC NC NC NC NC PR47B PR47A PR46B PR46A PR45B PR45A PR44B GND3 PR44A PR43B PR43A PR42B PR42A PR41B PR41A CFG2 CFG1 CFG0 PROGRAMN CCLK INITN DONE PR39B GND3 PR39A PR38B PR38A PR37B PR37A Bank LVDS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 T C T C T C T C T C T C T RLM0_PLLT_IN_A RLM0_PLLC_FB_A RLM0_PLLT_FB_A DI/CSSPIN DOUT/CSON BUSY/SISPI D7/SPID0 C T C T C T C RDQS45 RLM0_PLLC_IN_A Dual Function Ball Number Y19 AA23 GND AA22 AB23 AB24 Y21 AA21 Y23 Y22 AA24 GND Y24 AC25 AC26 AB25 AA25 AB26 AA26 W23 GND W24 W22 W21 Y25 Y26 W25 W26 V24 V21 V23 V22 V20 V25 U20 V26 GND U26 U24 U25 U23 U22 Ball Function PR65A PR64B GND3 PR64A PR63B PR63A PR62B PR62A PR61B PR61A PR60B GND3 PR60A PR59B PR59A PR58B PR58A PR57B PR57A PR56B GND3 PR56A PR55B PR55A PR54B PR54A PR53B PR53A CFG2 CFG1 CFG0 PROGRAMN CCLK INITN DONE PR51B GND3 PR51A PR50B PR50A PR49B PR49A LFECP/EC33 Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 T C T C T C T C T C T C T RLM0_PLLT_IN_A RLM0_PLLC_FB_A RLM0_PLLT_FB_A DI/CSSPIN DOUT/CSON BUSY/SISPI D7/SPID0 T C T C T C T C RDQS57 RLM0_PLLC_IN_A T C T C T C T C LVDS T C Dual Function RDQS65 4-69 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.) LFEC20/LFECP20 Ball Number U21 T21 T25 GND T26 T22 T23 T24 R23 R25 R24 R26 GND P26 R21 R22 P25 P24 P23 P22 N26 GND M26 N21 P21 N23 N22 N25 N24 L26 GND K26 M22 M23 M25 M24 M21 L21 L22 GND L23 L25 Ball Function PR36B PR36A PR35B GND3 PR35A PR34B PR34A PR33B PR33A PR32B PR32A PR31B GND3 PR31A PR30B PR30A PR29B PR29A PR28B PR28A PR27B GND3 PR27A PR26B PR26A PR25B PR25A PR24B PR24A PR22B GND2 PR22A PR21B PR21A PR20B PR20A PR19B PR19A PR18B GND2 PR18A PR17B Bank LVDS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 T C T C T C T C T C RDQS19 PCLKT2_0 T C T C T C T C PCLKC2_0 T C T C T C T C RDQS28 T C T C T C T C C T C RDQS36 Dual Function Ball Number U21 T21 T25 GND T26 T22 T23 T24 R23 R25 R24 R26 GND P26 R21 R22 P25 P24 P23 P22 N26 GND M26 N21 P21 N23 N22 N25 N24 L26 GND K26 M22 M23 M25 M24 M21 L21 L22 GND L23 L25 Ball Function PR48B PR48A PR47B GND3 PR47A PR46B PR46A PR45B PR45A PR44B PR44A PR43B GND3 PR43A PR42B PR42A PR41B PR41A PR40B PR40A PR39B GND3 PR39A PR38B PR38A PR37B PR37A PR36B PR36A PR34B GND2 PR34A PR33B PR33A PR32B PR32A PR31B PR31A PR30B GND2 PR30A PR29B LFECP/EC33 Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 T C T C T C T C T C RDQS31 PCLKT2_0 T C T C T C T C PCLKC2_0 T C T C T C T C RDQS40 T C T C T C T C LVDS C T C RDQS48 Dual Function 4-70 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.) LFEC20/LFECP20 Ball Number L24 K25 J25 J26 H26 H25 GND J24 K21 K22 K20 J20 K23 K24 J21 J22 J23 H22 G26 F26 E26 E25 F25 GND G25 H23 H24 H21 G21 D26 D25 F21 G22 G24 G23 C26 C25 F24 F23 Ball Function PR17A PR16B PR16A PR15B PR15A PR14B GND2 PR14A PR13B PR13A PR12B PR12A PR11B PR11A NC NC NC NC NC NC NC NC PR9B GND2 PR9A PR8B PR8A PR7B PR7A PR6B PR6A PR5B PR5A PR4B PR4A PR3B PR3A NC NC Bank LVDS 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 T C T C T T C T C T C T C RDQS6 RUM0_PLLT_FB_A RUM0_PLLC_IN_A RUM0_PLLT_IN_A C RUM0_PLLC_FB_A T C T C T C T T C T C T C Dual Function Ball Number L24 K25 J25 J26 H26 H25 GND J24 K21 K22 K20 J20 K23 K24 J21 GND J22 J23 H22 G26 F26 E26 E25 F25 GND G25 H23 H24 H21 G21 D26 D25 F21 GND G22 G24 G23 C26 C25 F24 GND F23 Ball Function PR29A PR28B PR28A PR27B PR27A PR26B GND2 PR26A PR25B PR25A PR24B PR24A PR23B PR23A PR22B GND2 PR22A PR21B PR21A PR20B PR20A PR19B PR19A PR17B GND2 PR17A PR16B PR16A PR15B PR15A PR14B PR14A PR13B GND2 PR13A PR12B PR12A PR11B PR11A PR9B GND2 PR9A LFECP/EC33 Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 T T C T C T C T C T C T C T C RDQS14 RUM0_PLLT_FB_A RUM0_PLLC_IN_A RUM0_PLLT_IN_A T C T C T C T C RUM0_PLLC_FB_A T C T C T C T C RDQS23 LVDS T C T C T C Dual Function 4-71 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.) LFEC20/LFECP20 Ball Number E24 D24 E22 F22 E21 D22 E23 D23 GND GND G20 F20 D21 C21 C23 C22 B23 C24 D20 E19 B25 B24 B26 A25 C20 C19 A24 A23 E18 D19 F19 B22 G19 B21 D18 GND C18 F18 A22 G18 Ball Function NC NC NC NC NC NC PR2B PR2A GND2 GND1 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC PT57B PT57A PT56B PT56A PT55B PT55A PT54B PT54A PT53B GND1 PT53A PT52B PT52A PT51B Bank LVDS 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 T C T C T C T C T C T C TDQS54 C C T VREF1_2 VREF2_2 Dual Function Ball Number E24 D24 E22 F22 E21 D22 E23 D23 GND GND G20 F20 D21 C21 C23 C22 B23 C24 D20 GND E19 B25 B24 B26 A25 C20 C19 A24 GND A23 E18 D19 F19 B22 G19 B21 D18 GND C18 F18 A22 G18 Ball Function PR8B PR8A PR7B PR7A PR6B PR6A PR2B PR2A GND2 GND1 PT65B PT65A PT64B PT64A PT63B PT63A PT62B PT62A PT61B GND1 PT61A PT60B PT60A PT59B PT59A PT58B PT58A PT57B GND1 PT57A PT56B PT56A PT55B PT55A PT54B PT54A PT53B GND1 PT53A PT52B PT52A PT51B LFECP/EC33 Bank 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 T C T C T C T C T C T C TDQS54 T C T C T C T C C T C T C T C T C TDQS62 LVDS C T C T C T C T RDQS6 VREF1_2 VREF2_2 Dual Function 4-72 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.) LFEC20/LFECP20 Ball Number A21 E17 B17 C17 GND D17 F17 E20 G17 B20 E16 A20 A19 GND B19 D16 C16 F16 A18 G16 B18 A17 GND A16 D15 B16 E15 C15 F15 G15 B15 GND A15 E14 G14 D14 E13 F14 C14 B14 GND A14 Ball Function PT51A PT50B PT50A PT49B GND1 PT49A PT48B PT48A PT47B PT47A PT46B PT46A PT45B GND1 PT45A PT44B PT44A PT43B PT43A PT42B PT42A PT41B GND1 PT41A PT40B PT40A PT39B PT39A PT38B PT38A PT37B GND1 PT37A PT36B PT36A PT35B PT35A PT34B PT34A PT33B GND0 PT33A Bank LVDS 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 T PCLKT0_0 T C T C T C T C PCLKC0_0 VREF2_1 VREF1_1 T C T C T C T C TDQS38 T C T C T C T C T C T C T C T C TDQS46 T C T C Dual Function Ball Number A21 E17 B17 C17 GND D17 F17 E20 G17 B20 E16 A20 A19 GND B19 D16 C16 F16 A18 G16 B18 A17 GND A16 D15 B16 E15 C15 F15 G15 B15 GND A15 E14 G14 D14 E13 F14 C14 B14 GND A14 Ball Function PT51A PT50B PT50A PT49B GND1 PT49A PT48B PT48A PT47B PT47A PT46B PT46A PT45B GND1 PT45A PT44B PT44A PT43B PT43A PT42B PT42A PT41B GND1 PT41A PT40B PT40A PT39B PT39A PT38B PT38A PT37B GND1 PT37A PT36B PT36A PT35B PT35A PT34B PT34A PT33B GND0 PT33A LFECP/EC33 Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 T PCLKT0_0 T C T C T C T C PCLKC0_0 VREF2_1 VREF1_1 T C T C T C T C TDQS38 T C T C T C T C T C T C T C T C TDQS46 LVDS T C T C Dual Function 4-73 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.) LFEC20/LFECP20 Ball Number D13 C13 A13 B13 F13 F12 A12 GND B12 A11 B11 D12 C12 B10 A10 G12 GND A9 E12 B9 F11 A8 D11 C11 B8 GND B7 E11 A7 G11 C7 G10 C6 C10 GND D10 F10 A6 E10 C9 G9 D9 Ball Function PT32B PT32A PT31B PT31A PT30B PT30A PT29B GND0 PT29A PT28B PT28A PT27B PT27A PT26B PT26A PT25B GND0 PT25A PT24B PT24A PT23B PT23A PT22B PT22A PT21B GND0 PT21A PT20B PT20A PT19B PT19A PT18B PT18A PT17B GND0 PT17A PT16B PT16A PT15B PT15A PT14B PT14A Bank LVDS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T C T C T C T TDQS14 T C T C T C T C T C T C T C T C TDQS22 T C T C T C T C C T C T C T C TDQS30 Dual Function VREF1_0 VREF2_0 Ball Number D13 C13 A13 B13 F13 F12 A12 GND B12 A11 B11 D12 C12 B10 A10 G12 GND A9 E12 B9 F11 A8 D11 C11 B8 GND B7 E11 A7 G11 C7 G10 C6 C10 GND D10 F10 A6 E10 C9 G9 D9 Ball Function PT32B PT32A PT31B PT31A PT30B PT30A PT29B GND0 PT29A PT28B PT28A PT27B PT27A PT26B PT26A PT25B GND0 PT25A PT24B PT24A PT23B PT23A PT22B PT22A PT21B GND0 PT21A PT20B PT20A PT19B PT19A PT18B PT18A PT17B GND0 PT17A PT16B PT16A PT15B PT15A PT14B PT14A LFECP/EC33 Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T C T C T C T TDQS14 T C T C T C T C T C T C T C T C TDQS22 T C T C T C T C LVDS C T C T C T C TDQS30 Dual Function VREF1_0 VREF2_0 4-74 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.) LFEC20/LFECP20 Ball Number A5 GND A4 F9 B6 E9 C8 G8 B5 A3 GND A2 F8 B4 E8 B3 D8 G7 C4 C5 E7 D4 F7 D6 D7 E6 GND K10 K11 K12 K13 K14 K15 K16 L10 L11 L12 L13 L14 L15 L16 L17 Ball Function PT13B GND0 PT13A PT12B PT12A PT11B PT11A PT10B PT10A PT9B GND0 PT9A PT8B PT8A PT7B PT7A PT6B PT6A PT5B PT5A PT4B PT4A PT3B PT3A PT2B PT2A GND0 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Bank LVDS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T C T C T C T C T C T C T C T TDQS6 T C T C T C T C C Dual Function Ball Number A5 GND A4 F9 B6 E9 C8 G8 B5 A3 GND A2 F8 B4 E8 B3 D8 G7 C4 C5 E7 D4 F7 D6 D7 E6 GND K10 K11 K12 K13 K14 K15 K16 L10 L11 L12 L13 L14 L15 L16 L17 Ball Function PT13B GND0 PT13A PT12B PT12A PT11B PT11A PT10B PT10A PT9B GND0 PT9A PT8B PT8A PT7B PT7A PT6B PT6A PT5B PT5A PT4B PT4A PT3B PT3A PT2B PT2A GND0 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND LFECP/EC33 Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T C T C T C T C T C T C T C T TDQS6 T C T C T C T C LVDS C Dual Function 4-75 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.) LFEC20/LFECP20 Ball Number M10 M11 M12 M13 M14 M15 M16 M17 N10 N11 N12 N13 N14 N15 N16 N17 P10 P11 P12 P13 P14 P15 P16 P17 R10 R11 R12 R13 R14 R15 R16 R17 T10 T11 T12 T13 T14 T15 T16 T17 U10 U11 Ball Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Bank LVDS Dual Function Ball Number M10 M11 M12 M13 M14 M15 M16 M17 N10 N11 N12 N13 N14 N15 N16 N17 P10 P11 P12 P13 P14 P15 P16 P17 R10 R11 R12 R13 R14 R15 R16 R17 T10 T11 T12 T13 T14 T15 T16 T17 U10 U11 Ball Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND LFECP/EC33 Bank LVDS Dual Function 4-76 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.) LFEC20/LFECP20 Ball Number U12 U13 U14 U15 U16 U17 H10 H11 H16 H17 H18 H19 H8 H9 J18 J9 K8 L19 M19 N7 R20 R7 T19 V18 V8 V9 W10 W11 W16 W17 W18 W19 W8 W9 H12 H13 J10 J11 J12 J13 H14 H15 Ball Function GND GND GND GND GND GND VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO1 VCCIO1 Bank LVDS 0 0 0 0 0 0 1 1 Dual Function Ball Number U12 U13 U14 U15 U16 U17 H10 H11 H16 H17 H18 H19 H8 H9 J18 J9 K8 L19 M19 N7 R20 R7 T19 V18 V8 V9 W10 W11 W16 W17 W18 W19 W8 W9 H12 H13 J10 J11 J12 J13 H14 H15 Ball Function GND GND GND GND GND GND VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO1 VCCIO1 LFECP/EC33 Bank 0 0 0 0 0 0 1 1 LVDS Dual Function 4-77 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.) LFEC20/LFECP20 Ball Number J14 J15 J16 J17 K17 K18 L18 M18 N18 N19 P18 P19 R18 R19 T18 U18 V14 V15 V16 V17 W14 W15 V10 V11 V12 V13 W12 W13 P8 P9 R8 R9 T9 U9 K9 L9 M8 M9 N8 N9 G13 H20 Ball Function VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCAUX VCCAUX Bank LVDS 1 1 1 1 2 2 2 2 2 2 3 3 3 3 3 3 4 4 4 4 4 4 5 5 5 5 5 5 6 6 6 6 6 6 7 7 7 7 7 7 Dual Function Ball Number J14 J15 J16 J17 K17 K18 L18 M18 N18 N19 P18 P19 R18 R19 T18 U18 V14 V15 V16 V17 W14 W15 V10 V11 V12 V13 W12 W13 P8 P9 R8 R9 T9 U9 K9 L9 M8 M9 N8 N9 G13 H20 Ball Function VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCAUX VCCAUX LFECP/EC33 Bank 1 1 1 1 2 2 2 2 2 2 3 3 3 3 3 3 4 4 4 4 4 4 5 5 5 5 5 5 6 6 6 6 6 6 7 7 7 7 7 7 LVDS Dual Function 4-78 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.) LFEC20/LFECP20 Ball Number H7 J19 J8 K7 L20 M20 M7 N20 P20 P7 T20 T7 T8 V19 V7 W20 Y13 Y7 K19 L8 U19 U8 Ball Function VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCC1 VCC1 VCC1 VCC1 Bank LVDS Dual Function Ball Number H7 J19 J8 K7 L20 M20 M7 N20 P20 P7 T20 T7 T8 V19 V7 W20 Y13 Y7 K19 L8 U19 U8 Ball Function VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCPLL VCCPLL VCCPLL VCCPLL LFECP/EC33 Bank LVDS Dual Function 1. Tied to VCCPLL. 4-79 Lattice Semiconductor Pinout Information LatticeECP/EC Family Data Sheet Thermal Management Thermal management is recommended as part of any sound FPGA design methodology. To assess the thermal characteristics of a system, Lattice specifies a maximum allowable junction temperature in all device data sheets. Designers must complete a thermal analysis of their specific design to ensure that the device and package do not exceed the junction temperature limits. Refer to the Thermal Management document to find the device/package specific thermal values. For Further Information For further information regarding Thermal Management, refer to the following located on the Lattice website at www.latticesemi.com. • Thermal Management document • Technical Note TN1052 - Power Estimation and Management for LatticeECP/EC and LatticeXP Devices • Power Calculator tool included with Lattice’s ispLEVER design tool, or as a standalone download from www.latticesemi.com/software 4-80 LatticeECP/EC Family Data Sheet Ordering Information November 2005 Data Sheet Part Number Description LFXXX XX X – X XXXX X Device Family Lattice EC (FPGA) Lattice ECP (EC FPGA + DSP Blocks) Logic Capacity 1* = 1.5K LUTs 3* = 3K LUTs 6 = 6K LUTs 10 = 10K LUTs 15 = 15K LUTs 20 = 20K LUTs 33 = 33K LUTs Supply Voltage E = 1.2V Grade C = Commercial I = Industrial Package T100 = 100-pin TQFP* T144 = 144-pin TQFP Q208 = 208-pin PQFP F256 = 256-ball fpBGA F484 = 484-ball fpBGA F672 = 672-ball fpBGA TN100 = 100-pin Lead-free TQFP* TN144 = 144-pin Lead-free TQFP QN208 = 208-pin Lead-free PQFP FN256 = 256-ball Lead-free fpBGA FN484 = 484-ball Lead-free fpBGA FN672 = 672-ball Lead-free fpBGA Speed 3 = Slowest 4 5 = Fastest *Not available in the LatticeECP Family. Ordering Information Note: LatticeECP/EC devices are dual marked. For example, the commercial speed grade LFEC20E-4F484C is also marked with industrial grade -3I (LFEC20E-3F484I). The commercial grade is one speed grade faster than the associated dual mark industrial grade. The slowest commercial speed grade does not have industrial markings. The markings appear as follows: EC LFEC20E4F484C-3I Datecode © 2005 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 5-1 Order Info_02.3 Lattice Semiconductor Conventional Packaging LatticeEC Commercial Part Number LFEC1E-3Q208C LFEC1E-4Q208C LFEC1E-5Q208C LFEC1E-3T144C LFEC1E-4T144C LFEC1E-5T144C LFEC1E-3T100C LFEC1E-4T100C LFEC1E-5T100C Part Number LFEC3E-3F256C LFEC3E-4F256C LFEC3E-5F256C LFEC3E-3Q208C LFEC3E-4Q208C LFEC3E-5Q208C LFEC3E-3T144C LFEC3E-4T144C LFEC3E-5T144C LFEC3E-3T100C LFEC3E-4T100C LFEC3E-5T100C Part Number LFEC6E-3F484C LFEC6E-4F484C LFEC6E-5F484C LFEC6E-3F256C LFEC6E-4F256C LFEC6E-5F256C LFEC6E-3Q208C LFEC6E-4Q208C LFEC6E-5Q208C LFEC6E-3T144C LFEC6E-4T144C LFEC6E-5T144C Part Number LFEC10E-3F484C LFEC10E-4F484C LFEC10E-5F484C LFEC10E-3F256C I/Os 112 112 112 97 97 97 67 67 67 I/Os 160 160 160 145 145 145 97 97 97 67 67 67 I/Os 224 224 224 195 195 195 147 147 147 97 97 97 I/Os 288 288 288 195 Grade -3 -4 -5 -3 -4 -5 -3 -4 -5 Grade -3 -4 -5 -3 -4 -5 -3 -4 -5 -3 -4 -5 Grade -3 -4 -5 -3 -4 -5 -3 -4 -5 -3 -4 -5 Grade -3 -4 -5 -3 Package PQFP PQFP PQFP TQFP TQFP TQFP TQFP TQFP TQFP Package fpBGA fpBGA fpBGA PQFP PQFP PQFP TQFP TQFP TQFP TQFP TQFP TQFP Package fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA PQFP PQFP PQFP TQFP TQFP TQFP Package fpBGA fpBGA fpBGA fpBGA Ordering Information LatticeECP/EC Family Data Sheet Pins 208 208 208 144 144 144 100 100 100 Pins 256 256 256 208 208 208 144 144 144 100 100 100 Pins 484 484 484 256 256 256 208 208 208 144 144 144 Pins 484 484 484 256 Temp. COM COM COM COM COM COM COM COM COM Temp. COM COM COM COM COM COM COM COM COM COM COM COM Temp. COM COM COM COM COM COM COM COM COM COM COM COM Temp. COM COM COM COM LUTs 1.5K 1.5K 1.5K 1.5K 1.5K 1.5K 1.5K 1.5K 1.5K LUTs 3.1K 3.1K 3.1K 3.1K 3.1K 3.1K 3.1K 3.1K 3.1K 3.1K 3.1K 3.1K LUTs 6.1K 6.1K 6.1K 6.1K 6.1K 6.1K 6.1K 6.1K 6.1K 6.1K 6.1K 6.1K LUTs 10.2K 10.2K 10.2K 10.2K 5-2 Lattice Semiconductor Ordering Information LatticeECP/EC Family Data Sheet LatticeEC Commercial (Continued) Part Number LFEC10E-4F256C LFEC10E-5F256C LFEC10E-3Q208C LFEC10E-4Q208C LFEC10E-5Q208C Part Number LFEC15E-3F484C LFEC15E-4F484C LFEC15E-5F484C LFEC15E-3F256C LFEC15E-4F256C LFEC15E-5F256C Part Number LFEC20E-3F672C LFEC20E-4F672C LFEC20E-5F672C LFEC20E-3F484C LFEC20E-4F484C LFEC20E-5F484C Part Number LFEC33E-3F672C LFEC33E-4F672C LFEC33E-5F672C LFEC33E-3F484C LFEC33E-4F484C LFEC33E-5F484C I/Os 195 195 147 147 147 I/Os 352 352 352 195 195 195 I/Os 400 400 400 360 360 360 I/Os 496 496 496 360 360 360 Grade -4 -5 -3 -4 -5 Grade -3 -4 -5 -3 -4 -5 Grade -3 -4 -5 -3 -4 -5 Grade -3 -4 -5 -3 -4 -5 Package fpBGA fpBGA PQFP PQFP PQFP Package fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Package fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Package fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Pins 256 256 208 208 208 Pins 484 484 484 256 256 256 Pins 672 672 672 484 484 484 Pins 672 672 672 484 484 484 Temp. COM COM COM COM COM Temp. COM COM COM COM COM COM Temp. COM COM COM COM COM COM Temp. COM COM COM COM COM COM LUTs 10.2K 10.2K 10.2K 10.2K 10.2K LUTs 15.3K 15.3K 15.3K 15.3K 15.3K 15.3K LUTs 19.7K 19.7K 19.7K 19.7K 19.7K 19.7K LUTs 32.8K 32.8K 32.8K 32.8K 32.8K 32.8K 5-3 Lattice Semiconductor LatticeECP Commercial Part Number LFECP6E-3F484C LFECP6E-4F484C LFECP6E-5F484C LFECP6E-3F256C LFECP6E-4F256C LFECP6E-5F256C LFECP6E-3Q208C LFECP6E-4Q208C LFECP6E-5Q208C LFECP6E-3T144C LFECP6E-4T144C LFECP6E-5T144C Part Number LFECP10E-3F484C LFECP10E-4F484C LFECP10E-5F484C LFECP10E-3F256C LFECP10E-4F256C LFECP10E-5F256C LFECP10E-3Q208C LFECP10E-4Q208C LFECP10E-5Q208C Part Number LFECP15E-3F484C LFECP15E-4F484C LFECP15E-5F484C LFECP15E-3F256C LFECP15E-4F256C LFECP15E-5F256C Part Number LFECP20E-3F672C LFECP20E-4F672C LFECP20E-5F672C LFECP20E-3F484C LFECP20E-4F484C LFECP20E-5F484C Part Number LFECP33E-3F672C LFECP33E-4F672C LFECP33E-5F672C I/Os 224 224 224 195 195 195 147 147 147 97 97 97 I/Os 288 288 288 195 195 195 147 147 147 I/Os 352 352 352 195 195 195 I/Os 400 400 400 360 360 360 I/Os 496 496 496 Grade -3 -4 -5 -3 -4 -5 -3 -4 -5 -3 -4 -5 Grade -3 -4 -5 -3 -4 -5 -3 -4 -5 Grade -3 -4 -5 -3 -4 -5 Grade -3 -4 -5 -3 -4 -5 Grade -3 -4 -5 Package fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA PQFP PQFP PQFP TQFP TQFP TQFP Package fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA PQFP PQFP PQFP Package fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Package fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Package fpBGA fpBGA fpBGA Ordering Information LatticeECP/EC Family Data Sheet Pins 484 484 484 256 256 256 208 208 208 144 144 144 Pins 484 484 484 256 256 256 208 208 208 Pins 484 484 484 256 256 256 Pins 672 672 672 484 484 484 Pins 672 672 672 Temp. COM COM COM COM COM COM COM COM COM COM COM COM Temp. COM COM COM COM COM COM COM COM COM Temp. COM COM COM COM COM COM Temp. COM COM COM COM COM COM Temp. COM COM COM LUTs 6.1K 6.1K 6.1K 6.1K 6.1K 6.1K 6.1K 6.1K 6.1K 6.1K 6.1K 6.1K LUTs 10.2K 10.2K 10.2K 10.2K 10.2K 10.2K 10.2K 10.2K 10.2K LUTs 15.3K 15.3K 15.3K 15.3K 15.3K 15.3K LUTs 19.7K 19.7K 19.7K 19.7K 19.7K 19.7K LUTs 32.8K 32.8K 32.8K 5-4 Lattice Semiconductor Ordering Information LatticeECP/EC Family Data Sheet LatticeECP Commercial (Continued) Part Number LFECP33E-3F484C LFECP33E-4F484C LFECP33E-5F484C I/Os 360 360 360 Grade -3 -4 -5 Package fpBGA fpBGA fpBGA Pins 484 484 484 Temp. COM COM COM LUTs 32.8K 32.8K 32.8K LatticeEC Industrial Part Number LFEC1E-3Q208I LFEC1E-4Q208I LFEC1E-3T144I LFEC1E-4T144I LFEC1E-3T100I LFEC1E-4T100I Part Number LFEC3E-3F256I LFEC3E-4F256I LFEC3E-3Q208I LFEC3E-4Q208I LFEC3E-3T144I LFEC3E-4T144I LFEC3E-3T100I LFEC3E-4T100I Part Number LFEC6E-3F484I LFEC6E-4F484I LFEC6E-3F256I LFEC6E-4F256I LFEC6E-3Q208I LFEC6E-4Q208I LFEC6E-3T144I LFEC6E-4T144I Part Number LFEC10E-3F484I LFEC10E-4F484I LFEC10E-3F256I LFEC10E-4F256I LFEC10E-3 P208I LFEC10E-4 P208I I/Os 112 112 97 97 67 67 I/Os 160 160 145 145 97 97 67 67 I/Os 224 224 195 195 147 147 97 97 I/Os 288 288 195 195 147 147 Grade -3 -4 -3 -4 -3 -4 Grade -3 -4 -3 -4 -3 -4 -3 -4 Grade -3 -4 -3 -4 -3 -4 -3 -4 Grade -3 -4 -3 -4 -3 -4 Package PQFP PQFP TQFP TQFP TQFP TQFP Package fpBGA fpBGA PQFP PQFP TQFP TQFP TQFP TQFP Package fpBGA fpBGA fpBGA fpBGA PQFP PQFP TQFP TQFP Package fpBGA fpBGA fpBGA fpBGA PQFP PQFP Pins 208 208 144 144 100 100 Pins 256 256 208 208 144 144 100 100 Pins 484 484 256 256 208 208 144 144 Pins 484 484 256 256 208 208 Temp. IND IND IND IND IND IND Temp. IND IND IND IND IND IND IND IND Temp. IND IND IND IND IND IND IND IND Temp. IND IND IND IND IND IND LUTs 1.5K 1.5K 1.5K 1.5K 1.5K 1.5K LUTs 3.1K 3.1K 3.1K 3.1K 3.1K 3.1K 3.1K 3.1K LUTs 6.1K 6.1K 6.1K 6.1K 6.1K 6.1K 6.1K 6.1K LUTs 10.2K 10.2K 10.2K 10.2K 10.2K 10.2K 5-5 Lattice Semiconductor Ordering Information LatticeECP/EC Family Data Sheet LatticeEC Industrial (Continued) Part Number LFEC15E-3F484I LFEC15E-4F484I LFEC15E-3F256I LFEC15E-4F256I Part Number LFEC20E-3F672I LFEC20E-4F672I LFEC20E-3F484I LFEC20E-4F484I Part Number LFEC33E-3F672I LFEC33E-4F672I LFEC33E-3F484I LFEC33E-4F484I I/Os 352 352 195 195 I/Os 400 400 360 360 I/Os 496 496 360 360 Grade -3 -4 -3 -4 Grade -3 -4 -3 -4 Grade -3 -4 -3 -4 Package fpBGA fpBGA fpBGA fpBGA Package fpBGA fpBGA fpBGA fpBGA Package fpBGA fpBGA fpBGA fpBGA Pins 484 484 256 256 Pins 672 672 484 484 Pins 672 672 484 484 Temp. IND IND IND IND Temp. IND IND IND IND Temp. IND IND IND IND LUTs 15.3K 15.3K 15.3K 15.3K LUTs 19.7K 19.7K 19.7K 19.7K LUTs 32.8 32.8 32.8 32.8 LatticeECP Industrial Part Number LFECP6E-3F484I LFECP6E-4F484I LFECP6E-3F256I LFECP6E-4F256I LFECP6E-3Q208I LFECP6E-4Q208I LFECP6E-3T144I LFECP6E-4T144I Part Number LFECP10E-3F484I LFECP10E-4F484I LFECP10E-3F256I LFECP10E-4F256I LFECP10E-3Q208I LFECP10E-4Q208I Part Number LFECP15E-3F484I LFECP15E-4F484I LFECP15E-3F256I LFECP15E-4F256I I/Os 224 224 195 195 147 147 97 97 I/Os 288 288 195 195 147 147 I/Os 352 352 195 195 Grade -3 -4 -3 -4 -3 -4 -3 -4 Grade -3 -4 -3 -4 -3 -4 Grade -3 -4 -3 -4 Package fpBGA fpBGA fpBGA fpBGA PQFP PQFP TQFP TQFP Package fpBGA fpBGA fpBGA fpBGA PQFP PQFP Package fpBGA fpBGA fpBGA fpBGA Pins 484 484 256 256 208 208 144 144 Pins 484 484 256 256 208 208 Pins 484 484 256 256 Temp. IND IND IND IND IND IND IND IND Temp. IND IND IND IND IND IND Temp. IND IND IND IND LUTs 6.1K 6.1K 6.1K 6.1K 6.1K 6.1K 6.1K 6.1K LUTs 10.2K 10.2K 10.2K 10.2K 10.2K 10.2K LUTs 15.3K 15.3K 15.3K 15.3K 5-6 Lattice Semiconductor Ordering Information LatticeECP/EC Family Data Sheet LatticeECP Industrial (Continued) Part Number LFECP20E-3F672I LFECP20E-4F672I LFECP20E-3F484I LFECP20E-4F484I Part Number LFECP33E-3F672I LFECP33E-4F672I LFECP33E-3F484I LFECP33E-4F484I I/Os 400 400 360 360 I/Os 496 496 360 360 Grade -3 -4 -3 -4 Grade -3 -4 -3 -4 Package fpBGA fpBGA fpBGA fpBGA Package fpBGA fpBGA fpBGA fpBGA Pins 672 672 484 484 Pins 672 672 484 484 Temp. IND IND IND IND Temp. IND IND IND IND LUTs 19.7K 19.7K 19.7K 19.7K LUTs 32.8K 32.8K 32.8K 32.8K 5-7 Lattice Semiconductor Lead-Free Packaging LatticeEC Commercial Part Number LFEC1E-3QN208C LFEC1E-4QN208C LFEC1E-5QN208C LFEC1E-3TN144C LFEC1E-4TN144C LFEC1E-5TN144C LFEC1E-3TN100C LFEC1E-4TN100C LFEC1E-5TN100C Part Number LFEC3E-3FN256C LFEC3E-4FN256C LFEC3E-5FN256C LFEC3E-3QN208C LFEC3E-4QN208C LFEC3E-5QN208C LFEC3E-3TN144C LFEC3E-4TN144C LFEC3E-5TN144C LFEC3E-3TN100C LFEC3E-4TN100C LFEC3E-5TN100C Part Number LFEC6E-3FN484C LFEC6E-4FN484C LFEC6E-5FN484C LFEC6E-3FN256C LFEC6E-4FN256C LFEC6E-5FN256C LFEC6E-3QN208C LFEC6E-4QN208C LFEC6E-5QN208C LFEC6E-3TN144C LFEC6E-4TN144C LFEC6E-5TN144C Part Number LFEC10E-3FN484C LFEC10E-4FN484C LFEC10E-5FN484C LFEC10E-3FN256C I/Os 112 112 112 97 97 97 67 67 67 I/Os 160 160 160 145 145 145 97 97 97 67 67 67 I/Os 224 224 224 195 195 195 147 147 147 97 97 97 I/Os 288 288 288 195 Grade -3 -4 -5 -3 -4 -5 -3 -4 -5 Grade -3 -4 -5 -3 -4 -5 -3 -4 -5 -3 -4 -5 Grade -3 -4 -5 -3 -4 -5 -3 -4 -5 -3 -4 -5 Grade -3 -4 -5 -3 Package Lead-Free PQFP Lead-Free PQFP Lead-Free PQFP Lead-Free TQFP Lead-Free TQFP Lead-Free TQFP Lead-Free TQFP Lead-Free TQFP Lead-Free TQFP Package Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free PQFP Lead-Free PQFP Lead-Free PQFP Lead-Free TQFP Lead-Free TQFP Lead-Free TQFP Lead-Free TQFP Lead-Free TQFP Lead-Free TQFP Package Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free PQFP Lead-Free PQFP Lead-Free PQFP Lead-Free TQFP Lead-Free TQFP Lead-Free TQFP Package Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Ordering Information LatticeECP/EC Family Data Sheet Pins/Balls 208 208 208 144 144 144 100 100 100 Pins/Balls 256 256 256 208 208 208 144 144 144 100 100 100 Pins/Balls 484 484 484 256 256 256 208 208 208 144 144 144 Pins/Balls 484 484 484 256 Temp. COM COM COM COM COM COM COM COM COM Temp. COM COM COM COM COM COM COM COM COM COM COM COM Temp. COM COM COM COM COM COM COM COM COM COM COM COM Temp. COM COM COM COM LUTs 1.5K 1.5K 1.5K 1.5K 1.5K 1.5K 1.5K 1.5K 1.5K LUTs 3.1K 3.1K 3.1K 3.1K 3.1K 3.1K 3.1K 3.1K 3.1K 3.1K 3.1K 3.1K LUTs 6.1K 6.1K 6.1K 6.1K 6.1K 6.1K 6.1K 6.1K 6.1K 6.1K 6.1K 6.1K LUTs 10.2K 10.2K 10.2K 10.2K 5-8 Lattice Semiconductor Ordering Information LatticeECP/EC Family Data Sheet LatticeEC Commercial (Continued) Part Number LFEC10E-4FN256C LFEC10E-5FN256C LFEC10E-3QN208C LFEC10E-4QN208C LFEC10E-5QN208C Part Number LFEC15E-3FN484C LFEC15E-4FN484C LFEC15E-5FN484C LFEC15E-3FN256C LFEC15E-4FN256C LFEC15E-5FN256C Part Number LFEC20E-3FN672C LFEC20E-4FN672C LFEC20E-5FN672C LFEC20E-3FN484C LFEC20E-4FN484C LFEC20E-5FN484C Part Number LFEC33E-3FN672C LFEC33E-4FN672C LFEC33E-5FN672C LFEC33E-3FN484C LFEC33E-4FN484C LFEC33E-5FN484C I/Os 195 195 147 147 147 I/Os 352 352 352 195 195 195 I/Os 400 400 400 400 400 400 I/Os 496 496 496 360 360 360 Grade -4 -5 -3 -4 -5 Grade -3 -4 -5 -3 -4 -5 Grade -3 -4 -5 -3 -4 -5 Grade -3 -4 -5 -3 -4 -5 Package Lead-Free fpBGA Lead-Free fpBGA Lead-Free PQFP Lead-Free PQFP Lead-Free PQFP Package Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Package Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Package Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Pins/Balls 256 256 208 208 208 Pins/Balls 484 484 484 256 256 256 Pins/Balls 672 672 672 484 484 484 Pins/Balls 672 672 672 484 484 484 Temp. COM COM COM COM COM Temp. COM COM COM COM COM COM Temp. COM COM COM COM COM COM Temp. COM COM COM COM COM COM LUTs 10.2K 10.2K 10.2K 10.2K 10.2K LUTs 15.3K 15.3K 15.3K 15.3K 15.3K 15.3K LUTs 19.7K 19.7K 19.7K 19.7K 19.7K 19.7K LUTs 32.8K 32.8K 32.8K 32.8K 32.8K 32.8K 5-9 Lattice Semiconductor LatticeECP Commercial Part Number LFECP6E-3FN484C LFECP6E-4FN484C LFECP6E-5FN484C LFECP6E-3FN256C LFECP6E-4FN256C LFECP6E-5FN256C LFECP6E-3QN208C LFECP6E-4QN208C LFECP6E-5QN208C LFECP6E-3TN144C LFECP6E-4TN144C LFECP6E-5TN144C Part Number LFECP10E-3FN484C LFECP10E-4FN484C LFECP10E-5FN484C LFECP10E-3FN256C LFECP10E-4FN256C LFECP10E-5FN256C LFECP10E-3QN208C LFECP10E-4QN208C LFECP10E-5QN208C Part Number LFECP15E-3FN484C LFECP15E-4FN484C LFECP15E-5FN484C LFECP15E-3FN256C LFECP15E-4FN256C LFECP15E-5FN256C Part Number LFECP20E-3FN672C LFECP20E-4FN672C LFECP20E-5FN672C LFECP20E-3FN484C LFECP20E-4FN484C LFECP20E-5FN484C Part Number LFECP33E-3FN672C LFECP33E-4FN672C LFECP33E-5FN672C I/Os 224 224 224 195 195 195 147 147 147 97 97 97 I/Os 288 288 288 195 195 195 147 147 147 I/Os 352 352 352 195 195 195 I/Os 400 400 400 400 400 400 I/Os 496 496 496 Grade -3 -4 -5 -3 -4 -5 -3 -4 -5 -3 -4 -5 Grade -3 -4 -5 -3 -4 -5 -3 -4 -5 Grade -3 -4 -5 -3 -4 -5 Grade -3 -4 -5 -3 -4 -5 Grade -3 -4 -5 Package Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free PQFP Lead-Free PQFP Lead-Free PQFP Lead-Free TQFP Lead-Free TQFP Lead-Free TQFP Package Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free PQFP Lead-Free PQFP Lead-Free PQFP Package Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Package Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Package Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Ordering Information LatticeECP/EC Family Data Sheet Pins/Balls 484 484 484 256 256 256 208 208 208 144 144 144 Pins/Balls 484 484 484 256 256 256 208 208 208 Pins/Balls 484 484 484 256 256 256 Pins/Balls 672 672 672 484 484 484 Pins/Balls 672 672 672 Temp. COM COM COM COM COM COM COM COM COM COM COM COM Temp. COM COM COM COM COM COM COM COM COM Temp. COM COM COM COM COM COM Temp. COM COM COM COM COM COM Temp. COM COM COM LUTs 6.1K 6.1K 6.1K 6.1K 6.1K 6.1K 6.1K 6.1K 6.1K 6.1K 6.1K 6.1K LUTs 10.2K 10.2K 10.2K 10.2K 10.2K 10.2K 10.2K 10.2K 10.2K LUTs 15.3K 15.3K 15.3K 15.3K 15.3K 15.3K LUTs 19.7K 19.7K 19.7K 19.7K 19.7K 19.7K LUTs 32.8K 32.8K 32.8K 5-10 Lattice Semiconductor Ordering Information LatticeECP/EC Family Data Sheet LatticeECP Commercial (Continued) Part Number LFECP33E-3FN484C LFECP33E-4FN484C LFECP33E-5FN484C I/Os 360 360 360 Grade -3 -4 -5 Package Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Pins/Balls 484 484 484 Temp. COM COM COM LUTs 32.8K 32.8K 32.8K LatticeEC Industrial Part Number LFEC1E-3QN208I LFEC1E-4QN208I LFEC1E-3TN144I LFEC1E-4TN144I LFEC1E-3TN100I LFEC1E-4TN100I Part Number LFEC3E-3FN256I LFEC3E-4FN256I LFEC3E-3QN208I LFEC3E-4QN208I LFEC3E-3TN144I LFEC3E-4TN144I LFEC3E-3TN100I LFEC3E-4TN100I Part Number LFEC6E-3FN484I LFEC6E-4FN484I LFEC6E-3FN256I LFEC6E-4FN256I LFEC6E-3QN208I LFEC6E-4QN208I LFEC6E-3TN144I LFEC6E-4TN144I Part Number LFEC10E-3FN484I LFEC10E-4FN484I LFEC10E-3FN256I LFEC10E-4FN256I LFEC10E-3QN208I LFEC10E-4QN208I I/Os 112 112 97 97 67 67 I/Os 160 160 145 145 97 97 67 67 I/Os 224 224 195 195 147 147 97 97 I/Os 288 288 195 195 147 147 Grade -3 -4 -3 -4 -3 -4 Grade -3 -4 -3 -4 -3 -4 -3 -4 Grade -3 -4 -3 -4 -3 -4 -3 -4 Grade -3 -4 -3 -4 -3 -4 Package Lead-Free PQFP Lead-Free PQFP Lead-Free TQFP Lead-Free TQFP Lead-Free TQFP Lead-Free TQFP Package Lead-Free fpBGA Lead-Free fpBGA Lead-Free PQFP Lead-Free PQFP Lead-Free TQFP Lead-Free TQFP Lead-Free TQFP Lead-Free TQFP Package Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free PQFP Lead-Free PQFP Lead-Free TQFP Lead-Free TQFP Package Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free PQFP Lead-Free PQFP Pins/Balls 208 208 144 144 100 100 Pins/Balls 256 256 208 208 144 144 100 100 Pins/Balls 484 484 256 256 208 208 144 144 Pins/Balls 484 484 256 256 208 208 Temp. IND IND IND IND IND IND Temp. IND IND IND IND IND IND IND IND Temp. IND IND IND IND IND IND IND IND Temp. IND IND IND IND IND IND LUTs 1.5K 1.5K 1.5K 1.5K 1.5K 1.5K LUTs 3.1K 3.1K 3.1K 3.1K 3.1K 3.1K 3.1K 3.1K LUTs 6.1K 6.1K 6.1K 6.1K 6.1K 6.1K 6.1K 6.1K LUTs 10.2K 10.2K 10.2K 10.2K 10.2K 10.2K 5-11 Lattice Semiconductor Ordering Information LatticeECP/EC Family Data Sheet LatticeEC Industrial (Continued) Part Number LFEC15E-3FN484I LFEC15E-4FN484I LFEC15E-3FN256I LFEC15E-4FN256I Part Number LFEC20E-3FN672I LFEC20E-4FN672I LFEC20E-3FN484I LFEC20E-4FN484I Part Number LFEC33E-3FN672I LFEC33E-4FN672I LFEC33E-3FN484I LFEC33E-4FN484I I/Os 352 352 195 195 I/Os 400 400 400 400 I/Os 496 496 360 360 Grade -3 -4 -3 -4 Grade -3 -4 -3 -4 Grade -3 -4 -3 -4 Package Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Package Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Package Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Pins/Balls 484 484 256 256 Pins/Balls 672 672 484 484 Pins/Balls 672 672 484 484 Temp. IND IND IND IND Temp. IND IND IND IND Temp. IND IND IND IND LUTs 15.3K 15.3K 15.3K 15.3K LUTs 19.7K 19.7K 19.7K 19.7K LUTs 32.8K 32.8K 32.8K 32.8K LatticeECP Industrial Part Number LFECP6E-3FN484I LFECP6E-4FN484I LFECP6E-3FN256I LFECP6E-4FN256I LFECP6E-3QN208I LFECP6E-4QN208I LFECP6E-3TN144I LFECP6E-4TN144I Part Number LFECP10E-3FN484I LFECP10E-4FN484I LFECP10E-3FN256I LFECP10E-4FN256I LFECP10E-3QN208I LFECP10E-4QN208I Part Number LFECP15E-3FN484I LFECP15E-4FN484I LFECP15E-3FN256I LFECP15E-4FN256I I/Os 224 224 195 195 147 147 97 97 I/Os 288 288 195 195 147 147 I/Os 352 352 195 195 Grade -3 -4 -3 -4 -3 -4 -3 -4 Grade -3 -4 -3 -4 -3 -4 Grade -3 -4 -3 -4 Package Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free PQFP Lead-Free PQFP Lead-Free TQFP Lead-Free TQFP Package Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free PQFP Lead-Free PQFP Package Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Pins/Balls 484 484 256 256 208 208 144 144 Pins/Balls 484 484 256 256 208 208 Pins/Balls 484 484 256 256 Temp. IND IND IND IND IND IND IND IND Temp. IND IND IND IND IND IND Temp. IND IND IND IND LUTs 6.1K 6.1K 6.1K 6.1K 6.1K 6.1K 6.1K 6.1K LUTs 10.2K 10.2K 10.2K 10.2K 10.2K 10.2K LUTs 15.3K 15.3K 15.3K 15.3K 5-12 Lattice Semiconductor Ordering Information LatticeECP/EC Family Data Sheet LatticeECP Industrial (Continued) Part Number LFECP20E-3FN672I LFECP20E-4FN672I LFECP20E-3FN484I LFECP20E-4FN484I Part Number LFECP33E-3FN672I LFECP33E-4FN672I LFECP33E-3FN484I LFECP33E-4FN484I I/Os 400 400 400 400 I/Os 496 496 360 360 Grade -3 -4 -3 -4 Grade -3 -4 -3 -4 Package Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Package Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Pins/Balls 672 672 484 484 Pins/Balls 672 672 484 484 Temp. IND IND IND IND Temp. IND IND IND IND LUTs 19.7K 19.7K 19.7K 19.7K LUTs 32.8K 32.8K 32.8K 32.8K 5-13 LatticeECP/EC Family Data Sheet Supplemental Information November 2007 Data Sheet For Further Information A variety of technical notes for the LatticeECP/EC family are available on the Lattice web site at www.latticesemi.com. • • • • • • • LatticeECP/EC sysIO Usage Guide (TN1056) LatticeECP/EC sysCLOCK PLL Design and Usage Guide (TN1049) Memory Usage Guide for LatticeECP/EC Devices (TN1051) LatticeECP/EC DDR Usage Guide (TN1050) Power Estimation and Management for LatticeECP/EC and LatticeXP Devices (TN1052) LatticeECP-DSP sysDSP Usage Guide (TN1057) LatticeECP/EC sysCONFIG Usage Guide (TN1053) • IEEE 1149.1 Boundary Scan Testability in Lattice Devices For further information about interface standards refer to the following web sites: • JEDEC Standards (LVTTL, LVCMOS, SSTL, HSTL): www.jedec.org • PCI: ww.pcisig.com © 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 6-1 Further Info_01.3 LatticeECP/EC Family Data Sheet Revision History February 2008 Data Sheet DS1000 Revision History Date June 2004 August 2004 Version 01.0 01.1 Section — Introduction Architecture DC & Switching Characteristics Ordering Information Initial release. Added new device LFECP/LFEC33 in Table 1-1. Added New device LFECP/LFEC33 in Tables 2-9, 2-10 and 2-11. Added New device LFECP/LFEC33 on Supply current (Standby) tables. Added New device LFECP/LFEC33 on Initialization Supply current tables. Added 33K Logic Capacity Device in Part Number Description section. Added EC33, ECP33 device: Industrial and Commercial to Part Number table. Corrected I/O counts in the part number tables for 100/144 TQFP and 208 PQFP packages to match Table 1-1 on page 1. November 2004 01.3 Introduction Architecture Changed DDR333 (166MHz) to DDR400 (200MHz) Added “RSDS” offering to the Features list: Flexible I/O Buffer Added information about Secondary Clock Sources Added information about DCS Added a section on “Recommended Power-up Sequence” Updated Figure 2-24 “DQS Routing” Added DSP Block performance numbers to Table 2-11 Added another row for RSDS in Table 2-13 and Table 2-14 DC & Switching Characteristics Updated new timing numbers Added numbers to derating table Added DC conditions to RSDS table Changed LVDS Max. VCCIO to 2.625 Added a row for RSDS in “Operating Condition” table Updated standby and initialization current table Added figure 3-12: sysConfig SPI port sequence Added DDR Timing Table and DDR Timings Figure 3-6 Pinout Information Added LFECP/EC6 to Pin Information Added LFECP/EC6 to Power Supply and NC Connections Added LFECP/EC6 144 TQFP Logic Signal Connections Added LFECP/EC6 208 PQFP Logic Signal Connections Added LFECP/EC6 256 fpBGA Logic Signal Connections Added LFECP/EC6 484 fpBGA Logic Signal Connections Ordering Information Added 33K Logic Capacity Device in Part Number Description section. Added Part Number table for Commercial EC33. Added Part Number table for Commercial ECP33. Added Part Number table for Industrial EC33. Added Part Number table for Industrial ECP33. Change Summary © 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 7-1 Lattice Semiconductor Date December 2004 Version 01.4 Section Architecture Pinout Information Revision History LatticeECP/EC Family Data Sheet Change Summary Updated Hot Socketing Recommended Power Up Sequence section. Added LFEC1, LFEC3, LFECP/EC10, LFECP/EC15 to Pin Information Added LFEC1, LFEC3, LFECP/EC10, LFECP/EC15 to Power Supply and NC Connections Added LFEC1 and LFEC3 100 TQFP Pinout Added LFEC1 and LFEC3 144 TQFP Pinout Added LFEC1, LFEC3 and LFECP/EC10 208 PQFP Pinout Added LFEC3, LFECP/EC10 and LFECP/EC15 256 fpBGA Pinout Added LFECP/EC10 and LFECP/EC15 484 fpBGA Pinout Ordering Information Supplemental Information April 2005 01.5 Architecture DC & Switching Characteristics Added Lead-Free Package Designators Added Lead-Free Ordering Part Numbers Updated list of technical notes. EBR memory support section has been updated with clarification. Updated sysIO buffer pair section. Hot Socketing Specification has been updated. DC Electrical Characteristics table (IIL, IIH) has been updated. Supply Current (Standby) table has been updated. Initialization Supply Current table has been updated. External Switching Characteristics section has been updated. Removed tRSTW spec. from PLL Parameter table. tRST specifications have been updated. sysCONFIG Port Timing Specifications (tBSCL, tIODISS, tPRGMRJ) have been updated. Pinout Information Added LFECP/EC33 Pinout Information Pin Information Summary table has been updated. Power Supply and NC Connection table has been updated. 484-fpBGA logic connection has been updated (Ball # J6, J17, P6 and P17 for ECP/EC33 are now called VCCPLL). 672-fpBGA logic connection has been updated (Ball # K19, L8, U19, U8 for ECP/EC33 are now called VCCPLL). May 2005 01.6 Introduction Architecture ECP/EC33 EBR SRAM Bits and Blocks have been updated to 498K and 54 respectively. Table 2-10 has been updated (ECP/EC33 EBR SRAM Bits and Blocks have been updated to 498K and 54 respectively.) Recommended Power Up Sequence section has been removed. Supply Current (Standby) table has been updated. Initialization Supply Current table has been updated. Vos test condition has been updated to (VOP+VOM)/2. Register-to-Register performance table has been updated (rev. G 0.27). External switching characteristics have been updated (rev. G 0.27). Internal timing parameters have been updated (rev. G 0.27). Timing adders have been updated (rev. G 0.27). sysCONFIG port timing specifications have been updated. DC & Switching Characteristics Pinout Information Ordering Information Pin Information Summary table has been updated. Power Supply and NC Connection table has been updated. OPN list has been updated. 7-2 Lattice Semiconductor Date September 2005 Version 02.0 Section Architecture DC & Switching Characteristics Revision History LatticeECP/EC Family Data Sheet Change Summary sysIO section has been updated. Recommended Operating Conditions has been updated with VCCPLL. DC Electrical Characteristics table has been updated Removed 5V Tolerant Input Buffer section. Register-to-Register performance table has been updated (rev. G 0.28). LatticeECP/EC External Switching Characteristics table has been updated (rev. G 0.28). LatticeECP/EC Internal Switching Characteristics table has been updated (rev. G 0.28). LatticeECP/EC Family Timing Adders have been updated (rev. G 0.28). sysCLOCK PLL timing table has been updated (rev. G 0.28) LatticeECP/EC sysCONFIG Port Timing specification table has been updated (rev. G 0.28). Master Clock table has been updated (rev. G 0.28). JTAG Port Timing specification table has been updated (rev. G 0.28). Pinout Information Signal Description table has been updated with VCCPLL. Pin-to-Pin Performance table has been updated (G 0.30) - 4:1MUX, 8:1MUX, 16:1MUX, 32:1MUX Register-to-Register Performance (G 0.30) - No timing number changes. External Switching Characteristics (G 0.30) - No timing number changes. Internal Switching Characteristics (G 0.30) -tSUP_DSP, tHP_DSP, tSUO_DSP, tHO_DSP, tCOI_DSP, tCOD_DSP numbers have been updated. Family Timing Adders (G 0.30) - No timing number changes. sysCLOCK PLL Timing (G 0.30) - No timing number changes. sysCONFIG Port Timing Specifications (G 0.30) - No timing number changes. Master Clock (G 0.30) - No timing number changes. JTAG Port Timing Specification (G 0.30) - No timing number changes. November 2005 02.1 DC & Switching Characteristics Ordering Information March 2006 January 2007 February 2007 02.2 02.3 02.4 DC & Switching Characteristics Architecture Architecture Added 208-PQFP lead-free part numbers. Added footnote 3. to VCCAUX in the Recommended Operating Conditions table. EBR Asynchronous Reset section added. Updated EBR Asynchronous Reset section. Updated Maximum Number of Elements in a Block table - MAC value for x9 changed to 2. May 2007 November 2007 02.5 02.6 Architecture DC & Switching Characteristics Pinout Information Supplemental Information Updated text in Ripple Mode section. Added JTAG Port Waveforms diagram. Updated tRST timing information in the sysCLOCK PLL Timing table. Added Thermal Management text section. Updated title list. Read/Write Mode (Normal) and Read/Write Mode with Input and Output Registers waveforms in the EBR Memory Timing Diagrams section have been updated. February 2008 02.7 DC & Switching Characteristics 7-3