LFSC25E-P1-EV

LatticeSC™ PCI Express x1 Evaluation Board User’s Guide November 2008 Revision: EB24_01.4 LatticeSC PCI Express x1 Evaluation Board User’s Guide Lattice Semiconductor Introduction This user’s guide describes the LatticeSC PCI Express x1 Evaluation Board featuring the LatticeSC LFSCM3GA25 device in a 900 fpBGA package. The stand-alone evaluation PCB provides a functional platform for development and rapid prototyping of applications that require high-speed SERDES interfaces to PCI Express protocols. The evaluation board includes provisioning to connect high-speed SERDES channels via SMA connectors to test and measurement equipment. The board is manufactured using standard FR4 dielectric and through-hole vias. The nominal impedance is 50-ohm for single-ended traces and 100-ohm for differential traces. The board has several debugging and analyzing features for complete evaluation of the LatticeSC device. This user’s guide is intended to be referenced in conjunction with evaluation design tutorials to demonstrate the LatticeSC FPGA. Figure 1. LatticeSC PCI Express x1 Evaluation Board Features • Four SERDES high-speed channels interfaced to SMA test points and clock connections SERDES interface to x1 PCI Express edge fingers • RJ-45 interface for Ethernet • QDR2 and RLDRAMII memory devices • SFP Transceiver cage and associated interface • SATA-like connections to SERDES channels • Power connections and power sources • ispVM® programming support • On-board and external reference clock sources – Interchangeable clock oscillators – On-board reference clock management • ORCAstra Demonstration Software interface via standard ispVM JTAG connection 2 LatticeSC PCI Express x1 Evaluation Board User’s Guide Lattice Semiconductor • RS-232 Communications Port • Logic analyzer connection • Liquid Crystal Display interface connection • User-defined input and output points • SMA connectors included for high-speed clock or data interfacing • Performance monitoring via test headers, LEDs and switches The contents of this user’s guide include top-level functional descriptions of the various portions of the evaluation board, descriptions of the on-board connectors, diodes and switches and a complete set of schematics of the board. Figure 2 shows the functional partitioning of the board. Figure 2. LatticeSC PCI Express x1 Evaluation Board Block Diagram Backpanel Slot 12V Edge Fingers RJ-45 Power Regulation tic ne ag m 12V WallWart s Terminal Block National PHY RLDRAM2 10/100/1000 18-bit Backpanel Slot Clock Control SGMII 1Gbe-SFP SATA-Host SATA-Target RIGHT Osc FlxMac QDR2 Flash REFCLK-RIGHT SERDES Loop SC15/SC25 900 fpBGA JTAG Orcastra BOTTOM 18-bit Osc I2C FlxMac Osc LEFT SERDES SMAs X1 PCIe Fingers Config Status & Control Maxim 6692 PTEMP 100MHz PCI Clk REFCLK-LEFT x1 PCI Express Driver Platform Board for LatticSC 900 fpBGA Devices EE PROM PLL *1.25 Testpoints LEDs Switches Differential Trace Loops RS-232 LVDS SMAs 2x5 COM Additional Resources For additional information and resources related to this board, including updated documentation and software demos, please see the Lattice web site at: www.latticesemi.com/boards, and navigate to the appropriate page for this board. Lattice makes its best effort to provide evaluation board designs to help users with evaluation and development. However it remains the user's responsibility to verify proper and reliable operation of Lattice products in their end application by consulting documentation provided by Lattice. Differences in component selection and/or PCB layout in the user's application may significantly affect circuit performance and reliability. 3 LatticeSC PCI Express x1 Evaluation Board User’s Guide Lattice Semiconductor Figure 3. LatticeSC PCI Express x1 Evaluation Board, Top View LatticeSC Device This board features a LatticeSC FPGA with a 1.2V core supply. It can accommodate all pin compatible LatticeSC devices in the 900-ball fpBGA (1mm pitch) package. A complete description of this device can be found in the LatticeSC Family Data Sheet on the Lattice web site at www.latticesemi.com. Note: The connections referenced in this document refer to the LFSCM3GA25EP1-XXF900 device. Available I/Os and associated sysIO™ banks may differ for other densities within this device family. Applying Power to the Board The LatticeSC PCI Express x1 Evaluation Board is ready to power on. The board can be supplied with power from an AC wall-type transformer power supply shipped with the board or it can be supplied from a bench top supply via terminal screw connections. It also has provisions to be supplied from the PCI Express edge fingers from a host board. To supply power from the factory-supplied wall transformer, simply connect the output connection of the power cord to J6 and plug the wall transformer into an AC wall outlet. Power Supplies (see Appendix A, Figure 6) The evaluation board incorporates an alternate scheme to provide power to the board. The board is equipped to accept a main supply via the TB1 connection. This connection is provided to use with a bench top supply adjusted to provide a nominal 12V DC. All input power sources and on-board power supplies are fused with surface mounted fuses and have green LEDs to indicate power GOOD status of the intermediate supplies 4 LatticeSC PCI Express x1 Evaluation Board User’s Guide Lattice Semiconductor Table 1. Board Power Supply Fuses (see Appendix A, Figure 6) F1 1.0V/1.2V Core Fuse F2 1.5V Fuse F3 3.3V Fuse F4 1.2V Fuse F5 2.5V Fuse F6 1.8V Fuse Table 2. Board Power Supply Indicators (see Appendix A, Figure 6) D6 2.5V Source Good Indicator D7 3.3V Source Good Indicator D8 1.0V/1.2V VCC Core Source Good Indicator D9 1.5V Source Good Indicator D10 1.8V Source Good Indicator D11 1.2V Source Good Indicator D12 12V Input Good Indicator Table 3. Board Supply Disconnects (see Appendix A, Figure 7) Screw Terminal for 12V DC TB1 Pin 1 (Square PCB Pad) = 12V DC Pin 2 = Ground PCI Express Power Interface Power can be sourced to the board via the PCB edge-finger (CN1). This interface allows the user to provide power from a PCI Express host board. VCC Core Selection (see Appendix A, Figure 6) The VCC core can be selected on the board to be either 1.0V or 1.2V using J7. A jumper shunt placed between pin 1 and pin 2 will connect 1.0V. A jumper shunt between pin 2 and pin 3 will connect 1.2V. Programming/FPGA Configuration (see Appendix A, Figure 5) A programming header is provided on the evaluation board, providing access to the LatticeSC JTAG port. Important Note: The board must be un-powered when connecting, disconnecting, or reconnecting the ispDOWNLOAD Cable. Always connect the ispDOWNLOAD Cable's GND pin (black wire), before connecting any other JTAG pins. Failure to follow these procedures can in result in damage to the LatticeSC FPGA device and render the board inoperable. An ispDOWNLOAD® Cable is included with this board and also with each ispLEVER® design tool shipment. Cables may also be purchased separately from Lattice. 5 LatticeSC PCI Express x1 Evaluation Board User’s Guide Lattice Semiconductor ispVM Download Interface J3 is an 10-pin JTAG connector used in conjunction with the ispVM USB download cable to program and control the device. Connections to the cable typically consist of Pin[1:2:3:6:7:8]. The other pins are considered optional and are not required to be connected for standard operation. Table 4. ispVM JTAG Connector (see Appendix A, Figure 5) Pin 1 VCC Pin 2 TDO Pin 3 TDI Pin 4 PROGRAMN1 Pin 5 NC Pin 6 TMS Pin 7 GND Pin 8 TCK Pin 9 DONE1 Pin 10 INITN1 1. Optional pins. Download Procedures Requirements • PC with ispVM System v.16.0 (or later) programming management software, installed with appropriate drivers (USB driver for USB Cable, Windows NT/2000/XP parallel port driver for ispDOWNLOAD Cable). The latest ispVM System software can be downloaded from the Lattice web site at www.latticesemi.com/ispvm. Note: An option to install these drivers is included as part of the ispVM System setup. • ispDOWNLOAD Cable JTAG Download The LatticeSC device can be configured easily via its JTAG port. The device is SRAM-based; it must remain powered on to retain its configuration when programmed in this fashion. 1. Connect the ispDOWNLOAD cable to the appropriate header. J3 is used for the 1x10 cable. Connections to J3 use only pins[1-3][6-8]. 2. Connect the LatticeSC PCI Express x1 evaluation board to the appropriate power sources and power up board. 3. Start the ispVM System software. 6 LatticeSC PCI Express x1 Evaluation Board User’s Guide Lattice Semiconductor 4. Press the SCAN button located in the toolbar. The LatticeSC device is automatically detected. 5. Double-click the device to open the device information dialog. In the device information dialog, click the Browse button located under Data File. Locate the desired bitstream file (.bit). Click OK to both dialog boxes. 6. Click the green GO button. This will begin the download process into the device. Upon successful download, the device will be operational. Configuration Status Indicators (see Appendix A, Figure 5) These LEDs indicate the status of configuration to the FPGA. • D2 (RED) illuminated: This indicates that the programming was aborted or reinitialized driving the INITN output low. 7 LatticeSC PCI Express x1 Evaluation Board User’s Guide Lattice Semiconductor • D5 (GREEN) is illuminated: This indicates the successful completion of configuration by releasing the open collector DONE output pin. • D1 (GREEN) will flash indicating TDI activity. • D4 (RED) illuminated: This indicates that PROGRAMN is low. • D3 (RED) illuminated: This indicates that GSRN is low. PROGRAMN and GSRN (see Appendix A, Figure 5) These push-button switches assert/de-assert the logic levels on the PROGRAMN (SW3) and GSRN (SW2). Depressing the button drives a logic level “0” to the device. Bank1 VCCIO (see Appendix A, Figure 6) VCCIO1 can be selected on the board to be either 3.3V or 2.5V using J5. A jumper shunt placed between pin 1 and pin 2 will connect 2.5V. A jumper shunt between pin 2 and pin 3 will connect 3.3V. On-Board Flash Memory (see Appendix A, Figure 5) Two memory devices (U2 and U3) are on-board for non-volatile configuration memory storage. These two devices occupy the same Flash slot on the board. U2 can be populated with an 8M or smaller 8-pin SOIC device. U3 can be used in place of U2 with a 16-pin TSSOP 64M Flash device. This is the factory supplied Flash memory configuration. U4 is always supplied as an 8M Flash device. SW1 is used to control the selection of the Flash memory to be accessed. Refer to Lattice technical note TN1100, SPI Serial Flash Programming Using ispJTAG™ on LatticeSC FPGAs for recommended procedures and software usage. To use both SPI Flash devices to program the LatticeSC device, the user must write to the Flash devices individually. This is accomplished by setting SW1 accordingly. Writing to Flash #1(U2 OR U3), close 3 and 5 switch positions (ON) and open all others. Writing to Flash #2(U4), close 2 and 4 switch positions (ON) and open all others. For reading from the Flash devices individually, use the same switch settings as described for writing. For reading from both Flash devices in cascading format, close switch positions (1, 3, 4, 5, 8). FPGA Clock Management (see Appendix A, Figures 10 and 11) The evaluation board includes various features for generating and managing on-board clocks. The clocks are generated from either input provided from SMAs (see Table 5) or from crystal oscillators (Y1 and Y4). Y1 and Y4 are socketed for interchangeability. Y2 and Y5 are 321.25MHz surface-mounted oscillators. The Y3 oscillator is fanned out around U1 for reference clocks with a fan-out buffer IC. Y1 and Y4 can be a 4-pin DIP type oscillator like Connor-Winfield XO-400 series. Clock oscillators are selected per quad. Y1 and Y2 can source a clock to the Right SERDES Quads. Y4 and Y5 can source a clock to the Left SERDES Quad. The user needs to select the appropriate oscillator by placing jumper shunts on J20 and/or J22 for the Left reference clock source or J25 and/or J28 for the Right reference clock source. The selection of these clock sources is dependent on the selection pins of the clock multiplexers. The mux select pins are driven from the FPGA and will need to be driven according to the needs of the user design. The following table defines the selection of the clock sources. 8 LatticeSC PCI Express x1 Evaluation Board User’s Guide Lattice Semiconductor Table 5. Clock Source Selection (see Appendix A, Figures 5 and 10) BGA-A19 BGA-A20 Right Clock Source Left Clock Source L L SMA SMA H H Oscillator Oscillator Pin is low when open/float. FPGA general purpose I/O must be driven to control the mux selection. When using FPGA control, 3.3V VCCIO must be used in bank 1. Refer to Bank1 VCCIO section of this document. Table 6. Clock Input SMA (see Appendix A, Figure 10) SMA Signal J29 SMA Reference + Input to Left Quad J30 SMA Reference - Input to Left Quad J23 SMA Reference + Input to Right Quad J24 SMA Reference - Input to Right Quad The clocks sources are fanned-out across the board to several destinations. These clocks are all differential and must be used accordingly. These include SERDES reference clocks, PLL, and primary clock inputs. Table 7. Clock Distribution (see Appendix A, Figure 11) Clock Net FPGA_REFCLKP_L BGA P8 Clock Destination PCLKT7_2 FPGA_REFCLKN_L R8 FPGA_REFCLKP_R AD26 FPGA_REFCLKN_R AC25 LRC_PLLB_C B1 SERDES[360] A_REFCLKP_L PCLKC7_2 LRC_PLLB_T A_REFCLKN_L C1 SERDES[360] A_REFCLKP_R B30 SERDES[3e0] A_REFCLKN_R C30 SERDES[3e0] The clocks are also driven to SMA connections for driving off-board. Table 8. Clock Output SMAs (see Appendix A, Figure 11) SMA SMA EXTCLOCK_L J31 J32 EXTCLOCK_R J33 J34 Net Name SERDES Reference Clock The 50-ohm terminated SMA connectors are provided the supply reference clocks directly to the LatticeSC device from the clock management device. This device will drive clocks to both SERDES quads via 100-ohm LVDS signaling. On-board clock oscillators mentioned in the previous sections can be chosen to drive the same SERDES reference clocks. Also the board can be provisioned to source the clock from the PCI Express edge-fingers directly to FPGA input pins. Both of these input clock sources are routed through clock management devices allowing for clock source selection from a SMA input connector. This is accomplished by using the MUX selector driven by the FPGA output. 9 LatticeSC PCI Express x1 Evaluation Board User’s Guide Lattice Semiconductor SERDES Channels SMA Connections (see Appendix A, Figure 5) DC coupled top-mounted SMA connectors connect to the two SERDES TX and RX channels. These pins are directly coupled to the designated SMA connector creating a path for both input and output differential data. Table 9. SERDES Connectors (see Appendix A, Figure 8) SMA Channel Name 900-Ball fpBGA SMA Channel Name 900-Ball fpBGA J13 A_HDINP1_LEFT B6 J10 A_HDOUTP1_LEFT A6 J15 A_HDINN1_LEFT B5 J12 A_HDOUTN1_LEFT A5 J9 A_HDINP2_LEFT B7 J14 A_HDOUTP2_LEFT A7 J11 A_HDINN2_LEFT B8 J16 A_HDOUTN2_LEFT A8 SERDES SFP Transceiver Interface (see Appendix A, Figure 8) A small form-factor pluggable (SFP) transceiver cage is included for evaluation of SFP specific protocols. The PCB includes the appropriate power and high-speed circuitry needed for the SFP standard transceiver. Table 10. SFP Connections to SERDES Pins (see Appendix A, Figure 5) SFP RX Channel Name 900-Ball fpBGA SFP TX Channel Name 900-Ball fpBGA RD+ A_HDINP0_RIGHT B28 TD+ A_HDOUTP0_RIGHT A28 RD- A_HDINN0_RIGHT B27 TD- A_HDOUTN0_RIGHT A27 Table 11. SFP Control and Status Connections to FPGA SFP Pin 900-Ball fpBGA SFP Pin 900-Ball fpBGA TxFault A15 ModeDef0 E15 TxDis C13 ModeDef1 D15 LOS G15 ModeDef3 C14 RateSel F15 SERDES SATA Channels (see Appendix A, Figure 8) AC-coupled connections are included to attach SATA type cables to SERDES channels for board-to-board or loopback purposes. The connectors are configured using the 7-pin SATA specifications. 10 LatticeSC PCI Express x1 Evaluation Board User’s Guide Lattice Semiconductor Table 12. SERDES to SATA Connections CN1 Pin SERDES Pin 900-Ball fpBGA CN2 Pin SERDES Pin 900-Ball fpBGA 1 __ GND 1 __ GND 2 A_HDOUTP1_R A25 2 A_HDINP2_R B24 3 A_HDOUTN1_R A26 3 A_HDINN2_R B23 4 __ GND 4 __ GND 5 A_HDINP1_R B25 5 A_HDOUTP2_R A24 6 A_HDINN1_R B26 6 A_HDOUTN2_R A23 7 __ GND 7 __ GND SERDES PCI Express Channels (see Appendix A, Figure 8) This board is equipped to communicate directly as an add-on card to a PCI Express host. It is designed with edgefingers (CN1) to fit directly into an x1 host receptacle. Power can be supplied directly from the PCI Express host via the edge-finger connections. Table 13. SERDES to PCI Express Connections PCI Express Pin PCI Express Signal SCM Device Pin 900-Ball fpBGA B14 PETp0 A_HDINP0_L B3 B15 PETn0 A_HDINN0_L B4 A16 PERp0 A_HDOUTP0_L A3 A17 PERn0 A_HDOUTN0_L A4 A13 Refclk+ FPGA URC_A PLL Input+ D28 A14 Refclk- FPGA URC_A PLL Input+ E28 FPGA Test Pins (see Appendix A, Figure 15) General purpose FPGA pins are available for user applications. FPGA pins are connected to SW4 DIP switch. This switch is used for static settings to FPGA input pins. The pins must be set to LVCMOS18 buffer types and are externally pulled up when the switch is open and driven low when the switch is set to “ON” or closed. General purpose outputs are connected to LEDs for observing output status of pins. The FPGA output buffers should be LVCMOS18 and will illuminate the LED when driving a “1” and the LED will be off when driving a “0” or when not used. Table 14. FPGA Test Pins (see Appendix A, Figure 15) Switch BGA Netname LED 900-Ball fpBGA NetName LED Color SW4A G28 Switch1 D15 H26 LED1 Red SW4B F28 Switch2 D16 G26 LED2 Yellow SW4C L25 Switch3 D17 D29 LED3 Green SW4D L26 Switch4 D18 D30 LED4 Blue SW4E E29 Switch5 D19 K25 LED5 Red SW4F E30 Switch6 D20 K26 LED6 Yellow SW4G J28 Switch7 D21 H30 LED7 Green SW4H H28 Switch8 D22 K30 LED8 Blue 11 LatticeSC PCI Express x1 Evaluation Board User’s Guide Lattice Semiconductor Test SMA Connections General-purpose FPGA pins are available via SMA test connections. These connections are designed to permit evaluations of several types of FPGA I/O buffers. The use of several termination schemes permits easy interfaces for the type of buffer. Table 15. Test SMA Connections for FPGA Pins (see Appendix A, Figure 16) Name SCM25 Signal J37 LVDS_INP J39 LVDS_INN J38 J40 SMA Designation 900-Ball fpBGA Termination Description Termination Resistor(s) PR52A AB28 None — PR52B AC28 None — LVDS_OUTP0 PR35A M29 100-ohm Differential R275 LVDS_OUTN0 PR35B N30 100-ohm Differential R275 High Speed Test Point DP2 (see Appendix A, Figure 15 and 16) General-purpose FPGA pins are available via a differential test pad. These connections allow a high-impedance probe to measure the performance of a coupled-differential output buffer pair. Table 16. Differential I/O Test Point Probe True Probe Compliment 100-ohm Differential Resistor AF30 AG30 R274 Logic Analysis Connection LA1 (see Appendix A, Figure 15 and 16) Agilent single-ended probes designed for connection to the supplies Tyco/AMP’s 2-767004-2 MICTOR connector can be easily attached for signal bus analysis. Connections to general-purpose I/O pins are provided to the board ready 38-pin MICTOR connector. Table 17. Logic Analyzer Connections MICTOR Pin Signal 900-Ball fpBGA MICTOR Pin Signal 900-Ball fpBGA 5 LA_CLK1 AJ1 6 LA_CLK2 AF4 7 LA_0 AG3 8 LA_16 AH13 9 LA_1 AH2 10 LA_17 AK8 11 LA_2 AD8 12 LA_18 AK9 13 LA_3 AF7 14 LA_19 AH14 15 LA_4 AJ7 16 LA_20 AG14 17 LA_5 AJ8 18 LA_21 AK10 19 LA_6 AH10 20 LA_22 AK11 21 LA_7 AH11 22 LA_23 AH15 23 LA_8 AF13 24 LA_24 AG15 25 LA_9 AE14 26 LA_25 AH12 12 LatticeSC PCI Express x1 Evaluation Board User’s Guide Lattice Semiconductor Table 17. Logic Analyzer Connections (Continued) MICTOR Pin Signal 900-Ball fpBGA MICTOR Pin Signal 900-Ball fpBGA 27 LA_10 AK6 28 LA_26 AJ13 29 LA_11 AK7 30 LA_27 AD15 31 LA_12 AF14 32 LA_28 AE15 33 LA_13 AF15 34 LA_29 AK12 35 LA_14 AJ11 36 LA_30 AK13 37 LA_15 AG13 38 LA_31 AJ14 RS-232 Interface J36 (see Appendix A, Figures 5 and 16) A simple 2x5 Header provides a connection to create a RS-232 serial communications port. The connection includes the proper level shift needed to connect to a serial port of a PC. The RX and TX pins are connected to the FPGA. Table 18. RS-232 TX/RX Signal 900-Ball fpBGA Buffer Type RS232-RXD F13 LVCMOS25 RS232-TXD F12 LVCMOS25 LCD Interface J41 (see Appendix A, Figures 5 and 16) A 2x8 Header provides a connection to 16-character x 2 line LCD modules such as Varitronix VDM16265. A ribbon cable connection will allow attachment to the connector. The board includes two variable resistors for LCD adjustments. VR1 adjusts the backlight and VR2 provides contrast adjustment. A user design must be included in the FPGA to drive this feature. I2C Interface (see Appendix A, Figures 5 and 16) I2C interface is supplied between the FPGA and two ICs. This interface is used to access a Maxim temperature sensing device as well as a EEPROM. The temperature-sensing device is also connected back to the FPGA via the PTEMP pins to monitor device temperature. Table 19. I2C Interface Signal 900-Ball fpBGA Buffer Type SCL B11 LVCMOS25 or LVTTL33 SDA B12 LVCMOS25 or LVTTL33 Ethernet Interface (see Appendix A, Figures 5 and 13) Interconnection to Base 10/100/1000 Ethernet protocols is supported via a RJ-45 connection (J35). This connection is electrically interfaced to the FPGA through a tri-speed PHY device. Use of this interface requires a MAC 13 LatticeSC PCI Express x1 Evaluation Board User’s Guide Lattice Semiconductor design to be included in the FPGA. The board includes two status LEDs to indicate Base 10 or Base 100 link. LED(D13) is a green LED which will light to indicate a Base100 link and LED(D14) indicates an established Base 10 link. LED indicators on the RJ-45 connector will indicate activity and Base 1000 link status. Table 20 defines the pinout between the FPGA and PHY device. Table 20. LatticeSC FPGA to Ethernet PHY Connections Signal 900-Ball fpBGA ETH_TX_D0 D3 ETH_TX_D1 D2 ETH_TX_D2 J6 ETH_TX_D3 J5 ETH_TX_D4 E3 ETH_TX_D5 E2 ETH_TX_D6 K4 ETH_TX_D7 J4 ETH_RX_D0 F3 ETH_RX_D1 G3 ETH_RX_D2 K5 ETH_RX_D3 K6 ETH_RX_D4 F2 ETH_RX_D5 F1 ETH_RX_D6 E1 ETH_RX_D7 D1 ETH_CRS K3 ETH_COL L3 ETH_RX_CLK L6 ETH_RX_DV M6 ETH_TX_EN J1 ETH_TX_CLK K1 ETH_GTX_CLK L1 ETH_CLK_TO_MAC M1 QDR2 Memory Interface (see Appendix A, Figures 12 and 15) Interconnection to a Cypress CY7C1413AV18-2Mx18 QDR2 SRAM memory device is supplied on board. It includes the proper termination and interface requirements needed to operate at speed. Table 21. QDR2 Memory Interface Pinouts NetName FPGA Ball NetName FPGA Ball NetName FPGA Ball A_0 T30 Q_0 AG29 D_0 AK16 A_1 W28 Q_1 AG28 D_1 AK17 A_2 U26 Q_2 AH30 D_2 AJ16 A_3 U28 Q_3 AJ30 D_3 AJ17 A_4 M30 Q_4 AH29 D_4 AE16 A_5 R29 Q_5 AJ29 D_5 AH16 A_6 P29 Q_6 AE25 D_6 AG16 14 LatticeSC PCI Express x1 Evaluation Board User’s Guide Lattice Semiconductor Table 21. QDR2 Memory Interface Pinouts (Continued) NetName FPGA Ball NetName FPGA Ball NetName FPGA Ball A_7 P27 Q_7 AH28 D_7 AK18 A_8 N29 Q_8 AJ28 D_8 AK19 A_9 N28 Q_9 AE22 D_9 AH17 A_10 R25 Q_10 AK29 D_10 AH18 A_11 R28 Q_11 AK28 D_11 AG17 A_12 N27 Q_12 AH21 D_12 AJ18 A_13 L30 Q_13 AH23 D_13 AJ19 A_14 J30 Q_14 AH22 D_14 AK20 A_15 M26 Q_15 AG22 D_15 AK21 A_16 G29 Q_16 AG21 D_16 AF18 A_17 F29 Q_17 AF21 D_17 AG18 R_N AA30 W_N Y30 CQ AK24 K AJ20 K_N AJ21 RLDRAM-II Memory Interface (see Appendix A, Figures 14 and 15) Interconnection to a Micron MT49H16M18CFM-25 SDRAM memory device is supplied on board. It includes the proper termination and interface requirements needed to operate at speed. Table 22. LatticeSC FPGA to On-board SDRAM Connections 900 Ball fpBGA NetName A_0 AH4 A_1 AG5 NetName 900 Ball fpBGA NetName 900 Ball fpBGA NetName D_0 V2 D_1 W2 900 Ball fpBGA Q_0 V1 BA_0 AJ2 Q_1 U5 BA_1 AK2 A_2 AF8 D_2 V5 Q_2 U4 BA_2 AD7 A_3 AG8 D_3 V4 Q_3 T4 CS_N AH1 A_4 AH3 D_4 Y1 Q_4 T5 DM AJ12 A_5 AJ3 D_5 AA1 Q_5 U1 QK AC7 A_6 AF9 D_6 Y2 Q_6 T1 QVLD N3 A_7 AE10 D_7 AA2 Q_7 V3 DK AC4 A_8 AK3 D_8 Y3 Q_8 U3 DK_N AD4 A_9 AJ4 D_9 W3 Q_9 T6 CK AC3 A_10 AE11 D_10 AB1 Q_10 U2 CK_N AD3 A_11 AF10 D_11 AC1 Q_11 T2 A_12 AH7 D_12 W5 Q_12 R4 A_13 AH8 D_13 Y5 Q_13 R1 A_14 AE12 D_14 Y6 Q_14 P1 A_15 AE13 D_15 AD2 Q_15 R2 A_16 AK4 D_16 AE2 Q_16 P4 A_17 AK5 D_17 AB5 Q_17 P3 15 LatticeSC PCI Express x1 Evaluation Board User’s Guide Lattice Semiconductor NetName 900 Ball fpBGA A_18 AJ5 A_19 AJ6 NetName 900 Ball fpBGA NetName 900 Ball fpBGA NetName 900 Ball fpBGA Ordering Information Description Ordering Part Number LatticeSC PCI Express x1 Evaluation Board China RoHS Environment-Friendly Use Period (EFUP) LFSC25E-P1-EV 10 Technical Support Assistance Hotline: 1-800-LATTICE (North America) +1-503-268-8001 (Outside North America) e-mail: techsupport@latticesemi.com Internet: www.latticesemi.com Revision History Date Version October 2006 01.0 Initial release. Change Summary December 2006 01.1 Includes new SERDES schematic in Appendix A. March 2007 01.2 Added Ordering Information section. April 2007 01.3 Added important information for proper connection of ispDOWNLOAD (Programming) Cables. November 2008 01.4 Updated FPGA Clock Management text section. Updated Clock Source Selection table. Updated Clock Input SMA table. Updated 10/100/1000 PHY schematic. © 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 16 17 A B C D 5 LatticeSC-900fpBGA X1 PCI Express Platform Evaluation Board 5 4 4 3 3 2 D a te : S iz e C Title 1 1 S he e t 1 SC-900fpBGA x1 PCI EXPRESS Card P roje c t Cover Page Board will meet PCI Express Electromechanical Specification Rev 1.0 Add-in card form factor for standard height and full length 4.376" Height x 9.5" Length 2 of 14 R ev 1.0 A B C D Lattice Semiconductor LatticeSC PCI Express x1 Evaluation Board User’s Guide Appendix A. Schematic Figure 4. Cover Page A B C 100NF-0603SMT C1 10NF-0603SMT R1 4_7K-0603SMT R2 4_7K-0603SMT SCSN_1 Q_1 WRITE_PROT_N WRITE_PROT_N SCSN_0 Q_0 FLASH_DIS SCSN_0 Q_0 WRITE_PROT_N R3 4_7K-0603SMT 3_3V R11 10K-0603SMT [5] PCIE_PERSTN R19 5 SW2 SW3 1 2 3 4 3 3 GSRN 11 8 4Y 3Y 3_3V 8 7 6 5 16 15 14 13 12 11 10 9 8 7 6 5 3_3V M25P80-FLASH S# VCC Q HOLD# W# CLK GND DI U4 0R-0603SMT R25 PROGRAMN R20 CK D DU8 DU7 DU6 DU5 VSS W# FLASH1 2 4 Momentary Switch B3F-1150 1 PROGRAMN 2_5V HOLD# VCC DU1 DU2 DU3 DU4 S# Q U3 M25P80-FLASH S# VCC Q HOLD# W# CLK GND DI M25P64-FLASH(NOB) 1 2 3 4 5 6 7 8 1 2 3 4 U2 FLASH0 4 2 Momentary Switch B3F-1150 1 FPGA RESETN/GSRN C2 2Y 1Y 3 OUT2 OUT1 U7A 6 5 4 2 1 4 R4 12 13 9 10 SN74LVC125A/SO14 2A 2OE_N 1A 1OE_N SN74LVC125A/SO14 4A 4OE_N 3A Q_1 MAX6817 IN2 IN1 U5 FLASH_DIS 1 3OE_N U7B 6 3 3_3V FLASH_DIS 3_3V TDA10H0SK1 C3 DATA1 4_7K-0603SMT R13 4_7K-0603SMT 3_3V 100NF-0603SMT SCSN Q_0 5 VCC 10K-0603SMT R12 10K-0603SMT R26 3_3V 3_3V 4 R8 4_7K-0603SMT M0 R7 470R-0603SMT M1 R6 4_7K-0603SMT M2 R5 470R-0603SMT M3 2_5V 2_5V 2 SI LED-SMT1206_RED D3 [13] PTEMP G22 H5 F22 M3 SCSN F4 E4 M2 GSRN F6 M1 F26 F5 PROGRAMN G5 M0 G6 F25 INITN DONE 1CCLK 680R-0603SMT R22 PP1 R9 SPI3 MODE SETTING R10 MPIIRQN 4_7K-0603SMT 3_3V R14 4_7K-0603SMT D 4_7K-0603SMT R15 4_7K-0603SMT 2_5V 1 2 3 LED-SMT1206_RED D4 D5 Q1 2N2222/SOT23 J2 HEADER 4 1 1 B17 A18 R30 10K-0603SMT DONE INITN 2_5V DONE indicator will light when configuration is successfully completed 1 LED-SMT1206_RED R D2 INITN indicator will light if an error occurs during configuration programming 2 PP3 2 PP2 SCK TDO F16 TDI TMS J26 TCK G25 G24 RDCFGN H25 MPIIRQN H24 H6 BOURNS-3224W-10K R17 PT42B/DOUT PT43A/QOUT PT38C/RDY TMS TDO TDI TCK RDCFGN MPIIRQN R23 680R-0603SMT 2_5V 2_5V SC-900FPBGA 680R-0603SMT R21 JUMPER1 J1 SC25-900fpBGA PT49D/HDC PT49C/LDCN RESETN PROGRAMN M3 M2 M1 M0 INITN DONE CCLK U1I TEMP 20 19 18 17 16 15 14 13 12 11 [7] OSC_IN_1 SFP_TXDIS SFP_MODDEF2 SFP_MODDEF1 SFP_MODDEF0 SFP_RATESEL SFP_LOS SFP_TXFAULT CS1 CS0N WRN 4 6 OUT Y2 OUT Y1 2 6 4 TMS TCK OUT Y2 OUT Y1 NC7WZ16-MACO6A/Fairchild TinyLogic R18 220R-0603SMT D1 LED-SMT1206_GREEN This LED indicates activity on TDI. TDI 3_3V LCD0 LCD_R/W LCD1 LCD_DB0 LCD2 LCD_DB2 LCD3 LCD_DB4 LCD4 LCD_DB6 LCD5 LCD_RS DATA0 DATA1 LCD6 LCD_E LCD7 LCD_DB1 LCD8 LCD_DB3 LCD_DB5 LCD9 LCD10 LCD_DB7 ETH_MDIO ETH_MDC ETH_TX_ER ETH_MAC_CLK_EN ETH_RESET_N ETH_RX_ER ETH_EGP0 ETH_EGP1 ETH_EGP2 ETH_EGP3 ETH_EGP4 ETH_EGP5 ETH_EGP6 ETH_EGP7 NC7WZ16-MACO6A/Fairchild TinyLogic [7] CLOCK_CTRL_R [7] CLOCK_CTRL_L [13] LCD[0..10] [5] [5] [5] [5] [5] [5] [5] [10] ETH_EGP[0..7] [5] PCIE_SMCLK [5] PCIE_SMDAT [5] PCIE_WAKEN [5] PCIE_PERSTN [13] SCL [13] SDA [13] RS232_RXD [13] RS232_TXD [10] ETH_MDIO [10] ETH_MDC [10] ETH_TX_ER [10] ETH_MAC_CLK_EN [10] ETH_RESET_N [10] ETH_RX_ER R AD5 1 2 3 4 LCD[0..10] 20 19 18 17 16 15 14 13 12 11 GND 7 GND 2 5 10 9 8 7 6 5 4 3 2 1 R24 3_3V IN A2 IN A1 U6 G9 G10 D12 E12 B11 B12 F13 F12 D13 D14 G11 G12 E13 E14 H13 G13 A13 A14 F14 G14 B13 H14 B14 C13 C14 D15 E15 F15 G15 A15 A16 H16 B15 B16 C15 C16 F17 D16 D17 H17 H18 A17 G16 B18 G17 G18 E16 E17 C17 C18 F18 F19 D18 D19 A19 A20 B19 B20 IN A2 IN A1 U8 C6 VCC GND 2 5 SW1 1 3 3 1 U1K SC25-900fpBGA D a te : S iz e C Title LOCAL_TMS LOCAL_TCK DONE INITN TDO LOCAL_TDI PROGRAMN 3_3V J3 4.7K VCC INITN GND DONE TCK TMS NC ispEN_N TDI TDO HEADER 10 2 3 4 5 6 8 9 10 4.7K Configuration/Top Bank 4.7K EXBV8V472JV 1 S he e t 2 SC-900fpBGA X1 PCI EXPRESS Card P roje c t 4.7K 7 1 3_3V SC-900FPBGA Top BANK1 1 FROM ISPVM CABLE PT23A/D15/MPIWRDATA15 PT23B/A21/MPIBURST PT23C/DP1/MPIWRPARITY1 PT23D/D14/MPIWRDATA14 PT24A/MPITEAN/MPITEA PT24B/A18/MPITSIZ0 PT24C/A20/MPIBDIP PT24D/A19/MPITSIZ1 PT25A/A17/MPIADDR31 PT25B/A15/MPIADDR29 PT25C/D13/MPIWRDATA13 PT25D/A16/MPIADDR30 PT27A/A14/MPIADDR28 PT27B/A13/MPIADDR27 PT27C/D12/MPIWRDATA12 PT27D/D11/MPIWRDATA11 PT28A/A12/MPIADDR26 PT28B/A11/MPIADDR25 PT29A/A10/MPIADDR24 PT29B/A9/MPIADDR23 PT31A/A8/MPIADDR22 PT31C/VREF1_1 PT31B/A7/MPIADDR21 PT32A/A6/MPIADDR20 PT32B/A5/MPIADDR19 PT33A/A4/MPIADDR18 PT33B/A3/MPIADDR17 PT33C/A2/MPIADDR16 PT33D/A1/MPIADDR15 PT35A/A0/MPIADDR14 PT35B/MPIRTRYN/MPIRETRY PT35D/DP3/PCLKC1_4/MPIWRPARITY3 PT37A/MPICLK/PCLKT1_0/MPICLK PT37B/PCLKC1_0 PT38A/MPIACKN/MPITA PT38B/DP0/MPIWRPARITY0 PT38D/EXTDONEO PT39A/EXTCLKP2I PT39B/EXTCLKP2O PT41A/EXTCLKP1I PT41B/EXTCLKP1O PT42A/EXTDONEI PT42D/VREF2_1 PT43B/D0/MPIWRDATA0 PT45A/D1/MPIWRDATA1 PT45B/D2/MPIWRDATA2 PT45C/D3/MPIWRDATA3 PT45D/D4/MPIWRDATA4 PT46A/D5/MPIWRDATA5 PT46B/D6/MPIWRDATA6 PT46C/D7/MPIWRDATA7 PT46D/WRN/MPIRWN PT47A/RDN/MPISTRBN PT47B/CS0N/CS0N PT47C/D10/MPIWRDATA10 PT47D/D9/MPIWRDATA9 PT49A/CS1/CS1 PT49B/D8/MPIWRDATA8 C4 100NF-0603SMT 10 9 8 7 6 5 4 3 2 1 LED-SMT1206_GREEN 100NF-0603SMT WRITE_PROT_N FLASH_DIS CS0N CS1 WRN SCSN_0 SCSN_1 DATA0 R28 2 4_7K-0603SMT 3 2 4 RN1B 5 RN1C 2_5V C7 R29 4_7K-0603SMT 4_7K-0603SMT 100NF-0603SMT RN1D RDCFGN 4_7K-0603SMT Y GSRN R16 14 VCC Y PROGRAMN 220R-0603SMT G 3 2 4 5 VCC GND 2 1 RN1A 8 TDO 7 TCK 3 6 TMS of C5 18 TDI 14 R ev 1.0 A B C D Lattice Semiconductor LatticeSC PCI Express x1 Evaluation Board User’s Guide Figure 5. Configuration/Top Bank 100NF-0603SMT R27 100R-0603SMT 100R-0603SMT SI SCK A B C R48 R42 2_5V PP10 C43 VCC_CORE C37 4 C38 C39 VDDQ VREF LP2996-SO8 5 SD U9 C40 VTT VSENSE C32 8 3 + C41 C29 C81 C30 + 1_8V 0R-0603SMT R46 C56 C57 C58 5 4 2 VDDQ VREF SD U10 C59 LP2996-SO8 SC_RLDRAM_VTT 1_8V VREF_REG2 + C60 VTT VSENSE 3 C61 C50 8 + C51 C82 C83 C84 C85 C86 C87 C88 C52 + C89 PP11 SC_RLDRAM_VTT 0.9V VTT PROBE POINT R43 0R-0603SMT C100 C101 C102 C103 C104 C105 C106 C107 C108 5 4 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT C99 PP8 SC_QDR_VTT 0.9V VTT PROBE POINT R32 0R-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT C80 C8 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT C55 0R-0603SMT R45 R44 1K_ADJ/SMT3MM C36 1_8V SC_QDR_VTT 100NF-0603SMT VREF_REG1 2 1UF-16V-0805SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 100NF-0603SMT 10NF-0603SMT 2_5V C42 [12] SC_RLDRAM_VREF R36 0R-0603SMT C35 C31 1 R37 0R-0603SMT R35 1K_ADJ/SMT3MM R34 1K-0603SMT 2 R31 C44 2_5V C18 100NF-0603SMT C45 C46 1K-0603SMT R33 4_7K-0603SMT 47UF-16V_TANTBSMT C25 100NF-0603SMT C9 100NF-0603SMT 1_8V 2_5V C63 C64 L7 P7 AA6 T7 W6 AC15 AD16 AE9 AD24 AE17 AE18 AC24 T25 W25 L24 T23 VCCJ DP1 3 C65 C66 C67 C68 SC-900FPBGA 1 + C19 3_3V C69 C70 PROBE_VCC [4] J25 S C 2 5 -9 0 0 fpB G A SC-900FPBGA VCC1P2 VCC1P2 VCC1P2 VCC1P2 VCC1P2 VCC1P2 VCC1P2 VCC1P2 VCC1P2 VCCL_URC_B VCCL_URC_A VCCL_ULC_B VCCL_ULC_A VCCL_LRC_B VCCL_LRC_A VCCL_LLC_B VCCL_LLC_A SC25-900fpBGA VTT_7 VTT_7 VTT_6 VTT_6 VTT_6 VTT_5 VTT_5 VTT_5 VTT_4 VTT_4 VTT_4 VTT_3 VTT_3 VTT_3 VTT_2 VTT_2 U1H AB9 AC8 H23 H15 AC23 R23 AB22 T8 H8 D27 E26 D4 E5 AF26 AG27 AF5 AG4 U 1D C22 C72 C73 C74 C75 C76 C77 C78 C79 C91 C92 C93 C94 C95 C96 C97 C98 C110 C111 C112 C113 C114 C115 C116 C117 3 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT C109 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT C90 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT C71 C15 C23 VCCIO1 JUMPER1 C16 1 J4 C24 2 2 C17 3_3V 3 3 2_5V PP13 L10 L21 M10 M21 N10 N21 P10 P21 U10 U21 V10 V21 W10 W21 Y10 Y21 K10 K11 K12 K13 K14 K17 K18 K19 K20 AA10 AA11 AA12 AA13 AA14 AA17 AA18 AA19 AA20 AA21 AA22 AA9 AB10 AB21 J10 J21 J22 J9 K22 K9 K21 VCC SC25-900fpBGA VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC U1E VCCAUX PROBE POINT H12 H11 H20 PP9 H19 M23 N24 M24 N23 U23 V23 V24 U24 W24 W23 AC18 AC17 AD17 AD18 AC19 AD19 AC13 AC14 AC12 AD13 AD14 AD12 V7 V8 U7 U8 W8 W7 M7 N8 M8 N7 C34 VCC_CORE + C33 2_5V C27 U1L VCCAUX 2 C28 C12 PP5 1.8V PROBE POINT PP7 SC25-900fpBGA NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11 NC12 NC13 NC14 NC15 NC16 NC17 NC18 NC19 NC20 NC21 NC22 NC23 NC24 U1G + C53 2_5V C54 D a te : S iz e C Title 2.5V PROBE POINT F11 C12 C19 F20 H10 J20 J14 H21 H22 H9 J11 J12 J13 J17 J15 J16 J18 J19 P22 R22 L23 L22 K24 K23 J24 N22 M22 J23 G30 J29 K27 N25 T22 AB24 AA23 AA24 AB23 Y24 W22 U22 V22 Y22 Y23 AA26 AA29 Y28 AC29 AC22 AC21 AB16 AB17 AB18 AB19 AB20 AC20 AD21 AD22 AD20 AG23 AG20 AJ23 AJ26 AH6 AG11 AJ9 AE7 AD10 AC9 AC11 AC10 AB15 AB14 AB13 AB12 AB11 AD9 AD11 Y9 W9 Y8 Y7 T9 AB8 AB7 AA8 AA7 V9 U9 AA4 AD1 AB2 W4 J8 K7 J7 P9 R9 K8 L8 H4 L2 J2 N6 N4 H2 N9 M9 L9 U1C 1 S he e t 3 of VCCIO 14 SC-900FPBGA SC PCI EXPRESS Card P roje c t 1 SC25-900fpBGA VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 Power Supplies PP12 VCCIO1PROBE POINT BANK 7 VCCIO = 2.5V M4 P5 J3 AB3 AH9 AG7 AK27 AJ24 AA28 P24 K28 P23 L28 E19 G21 G20 G19 F9 A11 G7 AC16 AB30 AF12 AG10 SC25-900fpBGA VCCAUX1 VCCAUX1 VCCAUX1 VCCAUX1 VCCAUX2 VCCAUX2 VCCAUX2 VCCAUX2 VCCAUX3 VCCAUX3 VCCAUX3 VCCAUX3 VCCAUX3 VCCAUX3 VCCAUX4 VCCAUX4 VCCAUX4 VCCAUX4 VCCAUX4 VCCAUX4 VCCAUX5 VCCAUX5 VCCAUX5 VCCAUX5 VCCAUX5 VCCAUX5 VCCAUX6 VCCAUX6 VCCAUX6 VCCAUX6 VCCAUX6 VCCAUX6 VCCAUX7 VCCAUX7 VCCAUX7 VCCAUX7 + C21 1_8V + C14 J5 HEADER 3X1 VCCIO1 SELECT 1UF-16V-0805SMT BANK 2, 3, 4, 5, 6 VCCIO = 1.8V 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT C13 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT C62 PP6 R41 0R-0805SMT R39 OPEN-0603SMT R47 OPEN-0603SMT SC_RLDRAM_VTT SC_QDR_VTT VCC12 PROBE POINT 1_2VDDA 3 22UF-16V_TANTBSMT 2_5V 47UF-16V_TANTBSMT C47 1 10NF-0603SMT 6 7 GND 1 100NF-0603SMT 10NF-0603SMT R40 4_7K-0603SMT 2 100UF-FKSMT D 1K-0603SMT 1K-0603SMT 1UF-16V-0805SMT 100NF-0603SMT C11 C49 1UF-16V-0805SMT AVIN PVIN 6 7 1 2 C26 100NF-0603SMT C48 100NF-0603SMT 100UF-FKSMT 22UF-16V_TANTBSMT C10 10NF-0603SMT 1UF-16V-0805SMT PP4 1UF-16V-0805SMT AVIN PVIN GND 1 10UF-16V_TANTBSMT 1 2 4 1 2 XRES AE4 R38 1K-0603SMT PROBE_GND AE28 PROBE_VCC AD27 PROBE_VCC 1 1 2 2 SC-900FPBGA + 10UF-16V_TANTBSMT 2 1UF-16V-0805SMT 1_8V 22UF-16V_TANTBSMT 1 2 22UF-16V_TANTBSMT 22UF-16V_TANTBSMT 1 2 5 SC-900FPBGA 1 2 [12] SC_QDR_VREF 1 1UF-16V-0805SMT C20 1 2 1UF-16V-0805SMT SC-900FPBGA 19 2 R ev 1.0 A B C D Lattice Semiconductor LatticeSC PCI Express x1 Evaluation Board User’s Guide Figure 6. Power Supplies A B C R80 0R-0805SMT C135 10UF-16V_TANTBSMT 3_3VIN 1 1 1 1 1 R62 0R-0805SMT TP11 TP9 TP7 TP6 TP3 1 C122 10UF-16V_TANTBSMT 3_3VIN TESTPOINT TESTPOINT TESTPOINT TESTPOINT TESTPOINT TESTPOINT TP1 5 1 TP12 1 TP10 1 TP8 1 TP5 1 TP4 1 TP2 TESTPOINT TESTPOINT TESTPOINT TESTPOINT TESTPOINT TESTPOINT C136 2 4 5 100NF-0603SMT 1_5V R83 1 3 1.8V 1_8V C128 C138 4 R81 OPEN-0805SMT 1 2 1 2 U13 U14 12_0V 12_0V Q3 2N2222/SOT23 R67 OPEN-0805SMT R58 1 10K-0603SMT GND VIN GND VIN R56 1 10K-0603SMT LED-SMT1206_GREEN D10 1_8V 1. 8V R51 470R-1206SMT 12_0V PTH12060W SENSE PTH12060W BOURNS-3224W-10K R84 R63 0R-0603SMT 5 6 0R-0603SMT R78 R85 68K-0603SMT 3 1.2V R76 100K-0603SMT 1_8K-0603SMT R74 C133 10UF-16V_TANTBSMT SENSE VOUT BOURNS-3224W-10K R70 5 6 R60 100K-0603SMT 1_2V R59 1 10K-0603SMT C123 10UF-16V_TANTBSMT VOUT Q4 2N2222/SOT23 LED-SMT1206_GREEN D11 1.2V R52 470R-1206SMT 12_0V POWER RAIL GOOD INDICATORS LED-SMT1206_GREEN D9 1_5V 1.5V R50 470R-1206SMT F2 F1228CT-ND 5A Fast-Blo SMT Socketed Fuse F6 F1228CT-ND 5A Fast-Blo SMT Socketed Fuse C127 22UF-16V_TANTBSMT 124R-0603SMT C137 22UF-16V_TANTBSMT BOURNS-3224W-5K R89 AMS1503CT OUTPUT VCONTROL SENSE ADJUST_GND R65 1 3 124R-0603SMT BOURNS-3224W-2K R73 AMS1503CT OUTPUT VCONTROL SENSE ADJUST_GND VPOWER U12 VPOWER U16 C126 2 4 5 VCC_CORE R57 Q5 1 10K-0603SMT 2N2222/SOT23 LED-SMT1206_GREEN D8 VCC CORE 1.5V Q2 2N2222/SOT23 470R-1206SMT R49 12_0V 3 + C129 1_2VDDA C125 10UF-16V_TANTBSMT D12 LED-SMT1206_GREEN 12V INPUT GOOD 12_0V R53 470R-1206SMT 2 12_0V 2 1 R82 OPEN-0805SMT C130 1 2 U15 12_0V 2 GND VIN OPEN-0805SMT R68 3_3VIN PTH12060W 1 2 U11 VOUT GND PTH03010W VOUT 5 6 2.5V JUMPER1 J8 0R-0603SMT R79 R77 100K-0603SMT 1 R88 2_2K-0603SMT 4.32K Typical 2 R66 1V HEADER 3x1 ADJ 1.2V J7 3 1 OPEN-0603SMT SET VALUE 1V= 36.5K 1.2V=17.4K 12_0V 1 S he e t R75 15_4K-0603SMT R72 24K-0603SMT PROBE_VCC [3] SC PCI EXPRESS Card P roje c t 1 C121 10UF-16V_TANTBSMT DC/DC Conversion 330UF-FKSMT D a te : S iz e C Title R64 0R-0603SMT J6 4 F1 F1251CT-ND 10A Fast-Blo SMT Socketed Fuse F5 F1228CT-ND 5A Fast-Blo SMT Socketed Fuse 2 C132 + 2_5V 5 6 R61 100K-0603SMT VCC_CORE 100UF-FKSMT + C119 + 470UF-FKSMT 12_0V 12_0V C118 1 Male Power Jack 2.1mm 22HP037-2.1mm PC 3 POWER INPUT SENSE BOURNS-3224W-10K R71 C131 10UF-16V_TANTBSMT SENSE BOURNS-3224W-10K R87 SC VCC_CORE VIN GND +12VDC Terminal Block/ED1202DS TB1 VCC12 power supply must always be higher than VCC Core, or if lower, then well within 150mV of VCC Core R55 150R-0603SMT 3.3V D7 LED-SMT1206_GREEN 3_3V F3 F1228CT-ND 5A Fast-Blo SMT Socketed Fuse BLM41PG600SN1 FB1 3_3V F4 F1228CT-ND 5A Fast-Blo SMT Socketed Fuse 330UF-FKSMT C134 + 1_2V 330UF-FKSMT C124 + 3_3VIN 3.3V R54 100R-0603SMT 2. 5V D6 LED-SMT1206_GREEN 2_5V G 4 G 12_0V G 3 R69 GND Pads Distributed around the board 100NF-0603SMT G 2 27R-0603SMT G 3 2 G 3 2 D R86 INHIBIT# 3 10 MUP INHIBIT# 3 100NF-0603SMT 8 ADJUST 4 3 56R-0603SMT 1UF-16V-0805SMT 2 100NF-0603SMT 10 MUP 9 MDWN ADJUST 4 3_3_TRIM 9 MDWN 8 TRACK 7 INHIBIT# 3 TRACK GND 7 1_2_TRIM 10 MUP INHIBIT# 3 10 MUP 9 MDWN 8 TRACK ADJUST 4 CORE_TRIM GND 7 2 5 22UF-16V_TANTBSMT G 9 MDWN ADJUST 4 2_5_TRIM GND 8 TRACK GND 20 7 C120 + of 14 R ev 1.0 330UF-FKSMT A B C D Lattice Semiconductor LatticeSC PCI Express x1 Evaluation Board User’s Guide Figure 7. DC/DC Conversion A B C OUT_SATA_TGT- OUT_SATA_HOST+ OUT_SATA_HOST- 50 50 50 50 [12] PCIE_CLKP [12] PCIE_CLKN [2] PCIE_PERSTN 50 1 2 3 4 5 6 7 C141 OUT_SATA_HOST- HDOUT PERp0 PERn0 PCIE_CLKP PCIE_CLKN PCIE_3V3 12_0V 5 x1 PRSNT1# +12V +12V GND JTAG2 JTAG3 JTAG4 JTAG5 +3.3V +3.3V PERST# GND REFCLK+ REFCLKGND PERp0 PERn0 GND CN4 +12V +12V RSVD_B3 GND SMCLK SMDAT GND +3.3V JTAG1 3.3Vaux WAKE# RSVD_B12 GND PETp0 PETn0 GND PRSNT3# GND 200K 200K PCI Express x1 Edge Finger Conn. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 x1 1 HDIN PETp0 PETn0 A_HDOUTP0_L A_HDOUTN0_L 50 50 R90 A3 A4 A6 A5 A7 A8 A10 A9 B28 B27 B25 B26 B24 B23 B21 B22 A28 A27 A25 A26 A24 A23 A21 A22 A_HDOUTP0_L A_HDOUTN0_L A_HDOUTP1_L A_HDOUTN1_L A_HDOUTP2_L A_HDOUTN2_L A_HDINP0_R A_HDINN0_R A_HDINP1_R A_HDINN1_R A_HDINP2_R A_HDINN2_R A_HDOUTP0_R A_HDOUTN0_R A_HDOUTP1_R A_HDOUTN1_R A_HDOUTP2_R A_HDOUTN2_R 4 STUFF OPTION A: LEAVE R106, R107 == OPEN 200K-0402SMT PETp0 C159 200K-0402SMT R107 PETn0 100NFX5R-0402SMT 100NFX5R-0402SMT R106 C157 100NFX5R-0402SMT 100NFX5R-0402SMT C160 C158 STUFF OPTION A: REPLACE C157, C158 WITH 0-OHM SHUNTS B3 B4 B6 B5 B7 B8 B10 B9 R91 4_02K-0603SMT A_HDINP0_L A_HDINN0_L A_HDINP1_L A_HDINN1_L A_HDINP2_L A_HDINN2_L RESP_L AC Coupled receiver + 200K Ohm to GND A_HDINP0_L A_HDINN0_L 50 TP13 TESTPOINT 50 PCIE_WAKEN [2] PCIE_3V3 PCIE_SMCLK [2] PCIE_SMDAT [2] B side = Primary Component Side(TOP) A side = Secondary Component Side(BOTTOM) 50 50 A_HDOUTN1_R A_HDOUTP1_R A_HDOUTN2_R A_HDOUTP2_R A_HDINN1_R A_HDINP1_R A_HDINN2_R A_HDINP2_R OUT_SATA_TGT- C146 C144 C142 C140 X1 PCIe Board Fingers 150R-0603SMT R97 150R-0603SMT R95 10NF-0402SMT C145 10NF-0402SMT C143 10NF-0402SMT 150R-0603SMT OUT_SATA_HOST+ R96 C139 OUT_SATA_TGT+ OUT_SATA_TGT- IN_SATA_TGT+ IN_SATA_TGT- 10NF-0402SMT 150R-0603SMT R94 10NF-0402SMT 10NF-0402SMT 10NF-0402SMT 10NF-0402SMT SATA OUT_SATA_TGT+ OUT_SATA_TGT+ 50 50 IN_SATA_HOST+ IN_SATA_HOST- 50 IN_SATA_TGT+ IN_SATA_TGT- 50 50 Target G A+ AG BB+ G CN2 QUAD_LOOP2_P OPEN-0603SMT RESP_L_N QUAD_LOOP1_P D IN_SATA_HOST+ IN_SATA_HOST- QUAD_LOOP1_N SATA QUAD_LOOP2_N OUT_SATA_HOST+ OUT_SATA_HOST- SFP_TXFAULT SFP_TXDIS SFP_MODDEF2 SFP_MODDEF1 SFP_MODDEF0 SFP_RATESEL SFP_LOS 6 5 4 3 2 1 6 5 4 3 2 1 CG1 A_REFCLKP_R A_REFCLKN_R A_REFCLKP_L A_REFCLKN_L A_RXREFCLKP_R A_RXREFCLKN_R A_RXREFCLKP_L A_RXREFCLKN_L 3 RESP_URC SFP_CAGE 3_3V 11 10 9 8 7 B30 C30 RESP_R_N 11 10 9 8 7 A_REFCLKP_R A_REFCLKN_R A_REFCLKP_L A_REFCLKN_L B1 C1 RESP_L_N B29 C29 B2 C2 RESP_L RESP_R A29 R93 4_02K-0603SMT A2 RESP_R RESP_ULC SERDES SC-900FPBGA Place Capacitors and Resistors as Physically close to device pin as possible PERn0 PERp0 PETn0 PETp0 [2] [2] [2] [2] [2] [2] [2] SC25-900fpBGA A_HDOUTP0_R A_HDOUTN0_R A_HDOUTP1_R A_HDOUTN1_R A_HDOUTP2_R A_HDOUTN2_R A_HDOUTP3_R A_HDOUTN3_R A_HDINP0_R A_HDINN0_R A_HDINP1_R A_HDINN1_R A_HDINP2_R A_HDINN2_R A_HDINP3_R A_HDINN3_R A_HDOUTP0_L A_HDOUTN0_L A_HDOUTP1_L A_HDOUTN1_L A_HDOUTP2_L A_HDOUTN2_L A_HDOUTP3_L A_HDOUTN3_L A_HDINP0_L A_HDINN0_L A_HDINP1_L A_HDINN1_L A_HDINP2_L A_HDINN2_L A_HDINP3_L A_HDINN3_L U1A R92 OPEN-0603SMT RESP_R_N R103 1 2 3 4 5 6 7 10K-0603SMT R99 G A+ AG BB+ G R98 1K-0603SMT Host 10K-0603SMT R101 SATA 10K-0603SMT R100 1 2 3 4 5 6 7 8 9 10 VeeT TDTD+ VeeT VccT VccR VeeR RD+ RDVeeR SFP HOST_SFP VeeT TxFault TxDisable Mod_Def_2 Mod_Def_1 Mod_Def_0 RateSel LOS VeeR VeeR CN3 A_REFCLKP_R [8] A_REFCLKN_R [8] 20 19 18 17 16 15 14 13 12 11 2 SMA_901_144_8(NOB) 1 2 J18 3 4 A_REFCLKP_L [8] 5 A_REFCLKN_L [8] RXREFCLKP_L RXREFCLKP_R J15 Rosenberger 32K153-400E3 J13 Rosenberger 32K153-400E3 J11 Rosenberger 32K153-400E3 J9 Rosenberger 32K153-400E3 2 2 2 2 CN1 10K-0603SMT 2 J14 Rosenberger 32K153-400E3 J16 Rosenberger 32K153-400E3 A_HDINP2_L A_HDINN2_L 1 1 50 SFP_RDP R104 D a te : S iz e C Title A_HDOUTN1_L A_HDOUTP2_L A_HDOUTN2_L 1 1 1 50 C154 A_HDOUTP1_L 1 1 1 SC PCI EXPRESS Card P roje c t SERDES SFP_RDN A_HDINN0_R A_HDINP0_R C153 10UF-16V_TANTBSMT 1UH-1206SMT L2 L1 1UH-1206SMT A_HDOUTP0_R A_HDOUTN0_R 150R-0603SMT R105 C147 100NFX5R-0402SMT C148 100NFX5R-0402SMT 150R-0603SMT SFP_RDN SFP_RDP C152 C156 100NFX5R-0402SMT SFP_TDP C149 C155 100NFX5R-0402SMT SFP_TDN SGMII J12 Rosenberger 32K153-400E3 A_HDINN1_L 1 SMA_901_144_8(NOB) 1 2 J17 3 4 5 J10 Rosenberger 32K153-400E3 3G SMAs A_HDINP1_L 1 100NF-0603SMT 21 100NF-0603SMT 2 2 2 2 3 100NF-0603SMT 4 100NF-0603SMT 5 S he e t C150 3_3V 5 of 14 C151 10UF-16V_TANTBSMT R ev 2.0 A B C D Lattice Semiconductor LatticeSC PCI Express x1 Evaluation Board User’s Guide Figure 8. SERDES 10K-0603SMT R102 22 A B C 5 + C164 R110 OPEN-0805SMT 1_2V + C162 R108 OPEN-0805SMT VDDOB VDDIB C165 R111 0R-0805SMT 1_5V C163 R109 0R-0805SMT 1UF-16V-0805SMT 1UF-16V-0805SMT 22UF-16V_TANTBSMT 22UF-16V_TANTBSMT 1_5V 4 VDDIB VDDOB 22UF-16V_TANTBSMT C167 1_2VDDA VDD_SERDES PROBE POINT + C166 2_5V A_VDDIB0_L VDDOB VDDIB C161 100NF-0603SMT PP14 PP15 VDDAX25 PROBE POINT 1 2 1_2V 1UF-16V-0805SMT 4 1 2 D 5 SC25-900fpBGA C168 100NF-0603SMT C174 100NF-0603SMT C169 3 10NF-0603SMT C175 100NF-0603SMT C176 100NF-0603SMT C170 C171 10NF-0603SMT C177 C28 C25 C24 C21 C27 C26 C23 C22 D25 E24 D23 E22 E25 D24 E23 D22 D5 D26 100NF-0603SMT C178 100NF-0603SMT C172 A_VDDIB0_R A_VDDIB1_R A_VDDIB2_R A_VDDIB3_R A_VDDOB0_R A_VDDOB1_R A_VDDOB2_R A_VDDOB3_R A_VDDRX0_R A_VDDRX1_R A_VDDRX2_R A_VDDRX3_R A_VDDTX0_R A_VDDTX1_R A_VDDTX2_R A_VDDTX3_R A_VDDP_L A_VDDP_R 10NF-0603SMT SERDES SUPPLIES SC-900FPBGA 10NF-0603SMT A_VDDIB0_L A_VDDIB1_L A_VDDIB2_L A_VDDIB3_L A_VDDOB0_L A_VDDOB1_L A_VDDOB2_L A_VDDOB3_L A_VDDRX0_L A_VDDRX1_L A_VDDRX2_L A_VDDRX3_L A_VDDTX0_L A_VDDTX1_L A_VDDTX2_L A_VDDTX3_L A_VDDAX25_R A_VDDAX25_L 1_2VDDA C3 C6 C7 C10 C4 C5 C8 C9 D6 E7 D8 E9 E6 D7 E8 D9 F24 F7 U1B 3 10NF-0603SMT C179 10NF-0603SMT C173 VDDOB VDDIB A_VDDIB0_R 2 1_2VDDA C438 100NF-0603SMT 2 D a te : S iz e C Title 1 S he e t 6 SC-900fpBGA X1 PCI EXPRESS Card P roje c t SERDES Power Supplies 1 of 14 R ev 1.0 A B C D Lattice Semiconductor LatticeSC PCI Express x1 Evaluation Board User’s Guide Figure 9. SERDES Power Supplies A B Oscillator Control 3_3V 1 R128 5 1 C193 1_6R-0603SMT J27 HEADER 2X1 1 + 2 2 1 2 NC DIS# 2 JUMPER1 JUMPER1 J22 + JUMPER1 JUMPER1 J28 HEADER 3x1 J26 J25 1 C182 1_6R-0603SMT R112 3 100NF-0603SMT 1 HEADER 3x1 J19 10UF-16V_TANTBSMT 2 C181 J21 HEADER 2X1 2 C192 2 1 2 Q_N 4 5 Y4 Q 5 4 2 3 4 5 2 3 4 5 8 1 2 3 4 5 2 3 4 5 J24 J23 Q Q_N 1 1 J30 J29 1 1 3_3V 3_3V 1 8 4 NOTE: PLACE TERMINATIONS CLOSE TO DEVICE. 3_3V NOTE: PLACE TERMINATIONS CLOSE TO DEVICE. R143 R142 82R-0603SMT 82R-0603SMT 3 MUX Q6 3 2N2222/SOT23 2 10K-0603SMT Q0 Q0_N MC100LVEL56 COM_SEL SEL0 VBB0 D0B_N D0B R126 16 17 U17A D0A_N D0A 3_3V + C180 100NF-0603SMT 3 19 18 SEL1 [2] CLOCK_CTRL_L + + C194 3_3V U17B MUX 10K-0603SMT Q1 Q1_N 3 Q7 2 3 2N2222/SOT23 MC100LVEL56 SEL1 VBB1 D1B_N D1B D1A_N D1A R141 15 8 10 9 7 6 100NF-0603SMT100NF-0603SMT C191 SEL0 SEL1 Q0/Q0# L L B L H B H H A H L A *** Pin is Low when open/float [2] CLOCK_CTRL_R SEL0 R134 82R-0603SMT R133 82R-0603SMT R137 R138 130R-0603SMT 130R-0603SMT 3_3V 3_3V R120 82R-0603SMT 5 4 2 1 + C184 100NF-0603SMT NOTE: PLACE TERMINATIONS CLOSE TO DEVICE. 130R-0603SMT R116 3_3V R129 R130 130R-0603SMT 130R-0603SMT 3_3V R127 82R-0603SMT Oscillator Socket R125 82R-0603SMT NOTE: PLACE TERMINATIONS CLOSE TO DEVICE. R118 82R-0603SMT 130R-0603SMT R114 3_3V R121 R122 130R-0603SMT 130R-0603SMT SMT Oscillator Y5 CW-P423F-312.5MHZ Q_N Q_N Q Oscillator Socket 4 SMT Oscillator Y2 CW-P423F-312.5MHZ Q 100NF-0603SMT Y1 110-93-314-41-001 110-93-314-41-001 NC DIS# 6 VCC GND 1 2 1 2 3 100NF-0603SMT C 1 2 10UF-16V_TANTBSMT C185 EXTERNAL CLK INPUT 14 VDD GND 7 D 1 1 2 C195 100NF-0603SMT C190 10NF-0603SMT J20 C196 3_3V 10NF-0603SMT 5 6 VCC GND 3 7 1 C183 100NF-0603SMT 14 VDD GND C186 20 VCC 14 VCC 3 100NF-0603SMT EXTERNAL CLK INPUT VEE 11 Oscillator Control 1 13 82R-0603SMT 3_3V 3_3V R136 82R-0603SMT 270R-0603SMT R140 107R-0603SMT R139 R135 82R-0603SMT R132 130R-0603SMT Q1/Q1# B A A B 270R-0603SMT R124 107R-0603SMT R123 R131 130R-0603SMT 12 R119 130R-0603SMT 82R-0603SMT R117 3_3V 3_3V R115 3_3V 130R-0603SMT R113 3_3V REFCLKN_L [8] REFCLKP_L [8] [8] [12] OSC_IN_3 [12] OSC_IN_4 REFCLKN_R REFCLKP_R [8] 3_3V OSC_IN_3 OSC_IN_4 R281 OPEN-0603SMT [2] OSC_IN_1 2 R282 OPEN-0603SMT 1_8V 100NF-0603SMT C187 OSC_IN_1 3_3V 2 Y3 OUT Vcc GND N/C PCA9306 VREF_LV SIGA_LV SIGB_LV CY2304-1 REF FBK CLKA1 VDD CLKA2 CLKB2 GND CLKB1 U18 R284 OPEN-0603SMT R283 OPEN-0603SMT 2 3 4 U29 1 2 3 4 3 4 VREF_HV SIGA_HV SIGB_HV 8 7 6 5 7 6 5 2 1 CTS-CB3LV-3C-100.00MHZ 8 EN GND 23 1 100NF-0603SMT C500 3_3V 1 S he e t 7 of 14 R279 OPEN-0603SMT 10NF-0603SMT C189 R278 OPEN-0603SMT 100NF-0603SMT C188 SC PCI EXPRESS Card P roje c t Clocks R280 200K-0603SMT D a te : S iz e C Title 3_3V 3_3V 1 R ev 1.0 A B C D Lattice Semiconductor LatticeSC PCI Express x1 Evaluation Board User’s Guide Figure 10. Clocks A B C 5 [7] REFCLKN_R [7] REFCLKP_R [7] REFCLKN_L [7] REFCLKP_L C197 100NF-0603SMT + 5 4 + 7 6 MC100LVEL13D CLKB_N CLKB U19B MC100LVEL13D CLKA_N CLKA U19A C198 100NF-0603SMT 3_3V 4 3_3V 3 VCC 4 16 VCC 8 VCC VEE 24 11 D 5 + Q2B_N Q2B Q1B_N Q1B Q0B_N Q0B Q2A_N Q2A Q1A_N Q1A Q0A_N Q0A 3_3V 17 18 19 14 15 12 3_3V R169 82R-0603SMT R166 130R-0603SMT 62R-0603SMT R165 9 13 62R-0603SMT R164 10 C199 100NF-0603SMT R155 82R-0603SMT R152 130R-0603SMT 62R-0603SMT R147 1 20 62R-0603SMT R146 2 3_3V 3_3V R171 82R-0603SMT R_EXT_OUT_N R170 130R-0603SMT R_EXT_OUT_P R159 82R-0603SMT L_EXT_OUT_N R156 130R-0603SMT L_EXT_OUT_P 1 1 3 J34 1 J33 J32 1 J31 R149 51R-0603SMT R144 OPEN-0603SMT 3_3V 3 2 3 4 5 2 3 4 5 2 3 4 5 R151 51R-0603SMT R160 82R-0603SMT A_REFCLKP_L [5] 3_3V 3_3V 3_3V 3_3V R167 82R-0603SMT R162 130R-0603SMT R161 82R-0603SMT 3_3V R168 82R-0603SMT 2 FPGA_REFCLKN_R [12] [12] [12] FPGA_REFCLKP_R [5] A_REFCLKP_R [5] FPGA_REFCLKN_L FPGA_REFCLKP_L [12] A_REFCLKN_R NOTE: PLACE TERMINATIONS CLOSE TO U1 DEVICE. R163 130R-0603SMT R154 82R-0603SMT NOTE: PLACE TERMINATIONS CLOSE TO U1 DEVICE. R150 130R-0603SMT 3_3V NOTE: PLACE TERMINATIONS CLOSE TO U1 DEVICE. R158 OPEN-0603SMT R153 82R-0603SMT R148 130R-0603SMT A_REFCLKN_L [5] R157 OPEN-0603SMT NOTE: PLACE TERMINATIONS CLOSE TO U1 DEVICE. R145 OPEN-0603SMT 2 3 4 5 3_3V 2 Title D a te : S iz e C 1 SC PCI EXPRESS Card P roje c t Clocks(Continued) 1 S he e t 8 of 14 R ev 1.0 A B C D Lattice Semiconductor LatticeSC PCI Express x1 Evaluation Board User’s Guide Figure 11. Clocks (Cont.) A B C227 + G8 H9 G4 H4 H3 K4 H8 F4 K8 L8 J8 E4 F8 E8 J4 L4 VDDQ BLM41PG471SN1L FB3 1_8V 1UF-16V-0805SMT C225 C 47UF-16V_TANTBSMT VDDQ C204 QDR_VDD VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ C212 10NF-0603SMT 10NF-0603SMT C236 5 C242 C205 C213 10NF-0603SMT 10NF-0603SMT C207 C215 100NF-0603SMT 100NF-0603SMT C208 C216 10NF-0603SMT CY7C1413AV18-2Mx18 QDR-II SRAM Power/Gnd 10NF-0603SMT C209 U20B C217 100NF-0603SMT 100NF-0603SMT C211 C219 10NF-0603SMT 10NF-0603SMT 100NF-0603SMT 100NF-0603SMT VREF VREF VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD QDR_VREF C224 QDR_VDD H2 H10 G5 H7 K7 F5 F7 K5 J5 J7 G7 H5 QDR_K# QDR_K Place resistors as close to SRAM device as possible QDR_WRITE_N QDR_READ_N 4 + BLM41PG471SN1L FB2 1_8V [12] QDR_CQ QDR_CQ [12] QDR_A[0..17] QDR_Q0 QDR_Q1 QDR_Q2 QDR_Q3 QDR_Q4 QDR_Q5 QDR_Q6 QDR_Q7 QDR_Q8 QDR_Q9 QDR_Q10 QDR_Q11 QDR_Q12 QDR_Q13 QDR_Q14 QDR_Q15 QDR_Q16 QDR_Q17 All Q lines should be equal lengths and length matched with CQ [12] QDR_K_# [12] QDR_K [12] QDR_WRITE_N [12] QDR_READ_N QDR_VTT R176 B1 C1 D1 E1 F1 G1 J1 K1 L1 M1 N1 P1 C2 E2 J2 K2 M2 P2 A11 A1 P11 M10 L11 K11 J10 F11 E11 C10 B11 B2 D3 E3 F2 G3 K3 L2 N3 P3 U20A R179 VDDQ R180 Value should be 5 times the desired output Impedance i.e. 50 ohms = 250 ohms impedance 0 ohms = min. impedance 3 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC CQ CQ# Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15 Q16 Q17 VDDQ CY7C1413AV18-2Mx18 QDRII-SRAM QDR_A0 QDR_A1 QDR_A2 QDR_A3 QDR_A4 QDR_A5 QDR_A6 QDR_A7 QDR_A8 QDR_A9 QDR_A10 QDR_A11 QDR_A12 QDR_A13 QDR_A14 QDR_A15 QDR_A16 QDR_A17 3 A3 B3 C3 D3 E3 F3 G3 H3 J3 B9 C9 D9 E9 F9 G9 J9 K9 L9 M9 N9 P9 B10 D10 F10 G10 L10 N10 P10 N11 M11 K10 J11 G11 E10 D11 C11 B3 C3 D2 F3 G2 J3 L3 M3 N2 QDR_VTT CTS-RT1402B7 A3 B3 C3 D3 E3 F3 G3 H3 J3 RP2 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 R181 1K-0603SMT When Low PLL bypassed C200 10NF-0603SMT C201 100NF-0603SMT R1=50 Ohm C228 R1 R1 A3 B3 C3 D3 E3 F3 G3 H3 J3 R1=50 Ohm R1 A1 B1 C1 D1 E1 F1 G1 H1 J1 C230 2 A1 B1 C1 D1 E1 F1 G1 H1 J1 R1 RP1 CTS-RT1402B7 A1 B1 C1 D1 E1 F1 G1 H1 J1 A1 B1 C1 D1 E1 F1 G1 H1 J1 QDR_D0 QDR_D1 QDR_D2 QDR_D3 QDR_D4 QDR_D5 QDR_D6 QDR_D7 QDR_D8 QDR_D9 QDR_D10 QDR_D11 QDR_D12 QDR_D13 QDR_D14 QDR_D15 QDR_D16 QDR_D17 2_5V 2_5V Place resistor pack as close to SRAM device as possible A3 B3 C3 D3 E3 F3 G3 H3 J3 QDR_VREF VDDQ 2 VDDQ VREF SD U21 LP2996-SO8 VTT VSENSE 8 3 R183 + C234 0R-0603SMT 1 C235 QDR_VTT 1UF-16V-0805SMT 22UF-16V_TANTBSMT QDR_D[0..17] [12] D a te : S iz e C Title 1 SC PCI EXPRESS Card P roje c t QDR2 SRAM S he e t 9 of 14 R ev 1.0 ALL Memory controller buses, clocks, and control traces must be 50 Ohm Transmission lines 5 4 + VDDQ All ADDRESS & DATA lines should be equal lengths and length matched with the K & K# and WRITE# and READ# Place resistor pack as close to SRAM device as possible C229 C231 QDR_VTT C203 100NF-0603SMT C202 10NF-0603SMT 2 J2 J2 QDR_VTT R177 A6 B6 H2 H2 Place resistors as close to SRAM device as possible R173 K# K 51R-0603SMT A8 A4 1K-0603SMT R175 R# W# G2 G2 51R-0603SMT R172 51R-0603SMT VSS/SA19 VSS/SA20 F2 F2 4 47UF-16V_TANTBSMT H1 DLL# 249R-0603SMT P6 R6 C C# R174 1K-0603SMT R178 A7 A3 OPEN-0603SMT NC/SA22 NC/SA21 51R-0603SMT QDR_A[0..17] 1K-0603SMT H11 ZQ A2 A10 100NF-0603SMT 100NF-0603SMT C237 C243 10NF-0603SMT 10NF-0603SMT 100NF-0603SMT B5 C2 C221 B7 A5 B2 B2 100NF-0603SMT NC D2 E2 E2 4_7K-0603SMT [12] QDR_Q[0..17] C232 C222 D 10NF-0603SMT 10NF-0603SMT A2 A2 C2 C220 5 100NF-0603SMT 1UF-16V-0805SMT BW0 BW1 SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 R3 R4 P4 R5 P5 N5 N6 N7 P7 R7 P8 R8 R9 B4 C5 C7 B8 C6 A9 QDR_Q[0..17] 1UF-16V-0805SMT C226 C233 C206 C214 100NF-0603SMT 100NF-0603SMT 10NF-0603SMT J2 J2 100NF-0603SMT C223 D2 R182 R2 R11 R1 R10 C238 C244 H2 H2 6 7 AVIN PVIN TCK TDI TDO TMS 10NF-0603SMT C239 C245 100NF-0603SMT 100NF-0603SMT G2 G2 C210 C218 C240 F2 F2 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS C246 E2 E2 M4 M5 M6 C8 L5 E7 E5 C4 F6 K6 L6 M7 L7 N8 M8 E6 D7 G6 H6 N4 D6 J6 D8 D4 D5 C241 C247 10NF-0603SMT 10NF-0603SMT 100NF-0603SMT 100NF-0603SMT C2 VSENSE_QDR_VTT D2 D2 100NF-0603SMT B2 B2 10NF-0603SMT A2 A2 C2 47UF-16V_TANTBSMT 25 GND QDR_D[0..17] 1 A B C D Lattice Semiconductor LatticeSC PCI Express x1 Evaluation Board User’s Guide Figure 12. QDR2 SRAM A B C260 C261 C263 ETH_GTX_CLK C264 1_8V 2_5V C267 C268 C269 C270 C271 100NF-0402SMT10NF-0402SMT 100NF-0402SMT10NF-0402SMT 100NF-0402SMT10NF-0402SMT 0402 0402 0402 0402 0402 0402 C266 2_5V Bypass for VDD_CORE and VDD pins. Bypass every other VDD pair, alternating 0.1 and 0.01uF caps. 5 Bypass for IO_VDD pins. Bypass every other IO_VDD pair, alternating 0.1 and 0.01uF caps. C272 10NF-0402SMT 0402 4 Bypass for BG_VDD 100NF-0402SMT 0402 2_5V 25MHz/HC49U HC-49/U Y6 D13 R230 324R-0402SMT 0402 Place xtal close to G-PHY C273 C251 10PF-0402SMT 0402 [2] ETH_EGP[0..7] ETH_MDC R214 2K-0402SMT R211 33R-0402SMT R212 33R-0402SMT 62 60 40 39 79 PHY_TX_EN PHY_TX_CLK PHY_CRS PHY_COL PHY_GTX_CLK R227 2K-0402SMT 0402 23 27 28 31 32 24 87 86 C249 22UF-16V_TANTBSMT 2 1 tantb D14 R229 2K-0402SMT 0402 DP83865 TM0 TMS TDO TDI TRST TCK CLOCK_OUT CLOCK_IN MDIO MDC GTX_CLK / RGMII_TXC CRS / RGMII_SEL1 COL TX_CLK / RGMII_SEL0 TX_EN / RGMII_TX_CTL TX_ER TXD0 / RGMII_TXD0 TXD1 / RGMII_TXD1 TXD2 / RGMII_TXD2 TXD3 / RGMII_TXD3 TXD4 TXD5 TXD6 TXD7 RX_CLK RX_DV / RGMII_RXC RX_ER / RGMII_RX_CTL RXD0 / RGMII_RXD0 RXD1 / RGMII_RXD1 RXD2 / RGMII_RXD2 RXD3 / RGMII_RXD3 RXD4 RXD5 RXD6 RXD7 U22 R228 324R-0402SMT 0402 2_5V R221 2K-0402SMT 0402 X1 R216 1M-0402SMT X0 0402 61 PHY_TX_ER 80 81 76 75 72 71 68 67 66 65 57 44 41 56 55 52 51 50 47 46 45 PHY_TX_D0 PHY_TX_D1 PHY_TX_D2 PHY_TX_D3 PHY_TX_D4 PHY_TX_D5 PHY_TX_D6 PHY_TX_D7 C252 10PF-0402SMT 0402 Place R close to CLOCK_IN ETH_MDIO ETH_CRS ETH_COL R209 33R-0402SMT PHY_RX_DV PHY_RX_ER PHY_RX_D0 PHY_RX_D1 PHY_RX_D2 PHY_RX_D3 PHY_RX_D4 PHY_RX_D5 PHY_RX_D6 PHY_RX_D7 PHY_RX_CLK R192 33R-0402SMT R195 33R-0402SMT R196 33R-0402SMT ETH_RX_ER ETH_RX_DV ETH_RX_CLK 33R-0402SMT 33R-0402SMT 33R-0402SMT 33R-0402SMT 33R-0402SMT 33R-0402SMT 33R-0402SMT 33R-0402SMT R193 R194 R186 R187 R188 R189 R190 R191 ETH_RX_D0 ETH_RX_D1 ETH_RX_D2 ETH_RX_D3 ETH_RX_D4 ETH_RX_D5 ETH_RX_D6 ETH_RX_D7 PHY_TX_D[0..7] PHY_TX_ER PHY_TX_EN R213 33R-0402SMT [12] ETH_CRS [12] ETH_COL R207 33R-0402SMT R208 33R-0402SMT [2] ETH_RX_ER [12] ETH_RX_DV [12] ETH_RX_CLK ETH_RX_D[0..7] C265 100NF-0402SMT10NF-0402SMT 100NF-0402SMT10NF-0402SMT 100NF-0402SMT10NF-0402SMT 10UF-Ceramic X5R/0805SMT 0402 0402 0402 0402 0402 0402 0805 C259 Place caps close to GPHY ETH_TX_D6 ETH_TX_D7 C262 [2] ETH_MDIO [2] ETH_MDC [12] ETH_GTX_CLK R202 33R-0402SMT R203 33R-0402SMT R204 33R-0402SMT R206 33R-0402SMT ETH_TX_D4 ETH_TX_D5 ETH_TX_ER ETH_TX_EN ETH_TX_CLK PHY_TX_D4 PHY_TX_D5 R199 33R-0402SMT R200 33R-0402SMT ETH_TX_D2 ETH_TX_D3 1 PHY_TX_D6 PHY_TX_D7 PHY_TX_D2 PHY_TX_D3 R197 33R-0402SMT R198 33R-0402SMT 1 ETH_TX_D0 ETH_TX_D1 PHY_TX_D0 PHY_TX_D1 ETH_RX_D[0..7] 1 2 1 2 [2] ETH_TX_ER [12] ETH_TX_EN [12] ETH_TX_CLK Decoupling Caps 1 2 C250 22UF-16V_TANTBSMT R185 2 1 tantb R184 these close to G-PHY 3 C274 10NF-0402SMT 0402 2_5V MDIA_BUS7 MDIA_BUS6 MDIA_BUS5 MDIA_BUS4 MDIA_BUS3 MDIA_BUS2 MDIA_BUS1 MDIA_BUS0 C254 10NF-0402SMT 2 1 C 1 2 1 2 ETH_EGP6 3 10R-0402SMT 0402 18R-0402SMT 0402 RX_VDD Giga Phyter 10/100/1000 Giga Phyter V 1_8V 2_5V MDID+ MDDCT MDID- MDIC+ MDCCT MDIC- MDIB+ MDBCT MDIB- MDIA+ MDACT MDIA- J35 1 2 LED2+ LED2LED1+ LED1- SHLD1 SHLD2 7 8 4 5 3 6 RJ-45 Belfuse 0826-1A1T-23 8 7 9 3 1 2 4 6 5 11 12 10 2_5V 85 33 13 14 17 18 95 94 89 88 1 2 3 6 7 8 9 10 34 84 16 15 14 13 19 20 ETH_EGP0 ETH_EGP1 ETH_EGP2 ETH_EGP3 ETH_EGP4 ETH_EGP5 ETH_EGP6 ETH_EGP7 R205 2K-0402SMT 0402 2 C256 10NF-0402SMT 0402 C257 10NF-0402SMT 0402 C258 10NF-0402SMT 0402 ETH_MAC_CLK_EN [2] MH1 MHOLE_1 0.100_PTH MH2 MHOLE_1 0.100_PTH R238 2K-0402SMT 0402 R237 324R-0402SMT 0402 ETH_EGP7 MH1 and MH2 are 0.100" diameter plated through holes D a te : S iz e C Title ETH_EGP4 ETH_EGP7 R232 2K-0402SMT 0402 MDI IO traces must be 50 ohm impedence. 1 S he e t 10 SC-900fpBGA x1 PCI EXPRESS Card P roje c t 10/100/1000 PHY R231 324R-0402SMT 0402 2_5V Ethernet RJ45 Connector C255 10NF-0402SMT 0402 Place caps close to RJ45 jack TX1 R222 (Do not 2K-0402SMT populate) 0402 ETH_RESET_N [2] 2K-0402SMT C253 1UF-16V-0805SMT 0805 ETH_MAC_CLK_EN R220 33R-0402SMT 0402 0402 ETH_RESET_N R219 R218 2_5V 8 2K-0402SMT 0402 2K-0402SMT ETH_EGP[0..7] (Do not populate) ETH_EGP0 2_5V R215 470R-0603SMT 1 2 0402 R217 470R-0603SMT 2 1 PULL_UP 0402 ETH_MAC_CLK_EN ETH_RESET_N MD I A _ B U S 6 MD I A _ B U S 7 Place 9.76K resistor as close to G-PHY as possible Giga Phyter address = 01h 102 R201 9_76K-0402SMT 1 2 0402 MD I _ P 4 MD I _ N 4 MD I A _ B U S 4 MD I A _ B U S 5 126 127 MD I A _ B U S 2 MD I A _ B U S 3 MD I _ P 2 MD I _ N 2 MD I _ P 3 MD I _ N 3 MD I A _ B U S 0 MD I A _ B U S 1 120 121 MD I _ P 1 MD I _ N 1 1 114 115 108 109 [12] ETH_CLK_TO_MAC CLK_TO_MAC RESET_N GP0 (PHYAD0 / DUPLEX_LED) GP1 (PHYAD1) GP2 (PHYAD2) GP3 (PHYAD3) GP4 (PHYAD4) GP5 (MULTI_EN) GP6 (MDIX_EN) GP7 (MAC_CLK_EN) EGP0 (NC_MODE) EGP1 EGP2 (Interrupt) EGP3 (TX_TCLK) EGP4 (SPEED0 / ACT_LED) EGP5 (SPEED1 / LINK10) EGP6 (DUPLEX_EN / LINK100) EGP7 (AN_EN / LINK1000) (Hard Reset) MDIA_BUS[0..7] ETH_EGP[0..7] BG_REF MDID_P MDID_N MDIC_P MDIC_N MDIB_P MDIB_N MDIA_P MDIA_N VDD_SEL REF_SEL 2 Place 49 ohm termination resistors as close as possible to G-PHY. The associated 0.01uF capacitor should be placed close to the 49 ohm resistors. R223 49_9R-0402SMT R233 49_9R-0402SMT Place termination [12] resistors TX_D0-7, TX_ER, TX_EN, GTX_CLK as close to FPGA as possible using 50 ohm impedence traces. PULL_DN 101 BG_VDD 98 PGM_VDD0 11 19 25 35 48 63 73 92 CORE_VDD1 CORE_VDD2 CORE_VDD3 CORE_VDD4 CORE_VDD5 CORE_VDD6 CORE_VDD7 CORE_VDD8 R225 49_9R-0402SMT R224 49_9R-0402SMT R234 49_9R-0402SMT [12] ETH_TX_D[0..7] 1 2 1 2 ETH_EGP5 100 103 105 111 117 123 VDD0 RX_DVDD0 VDD1 VDD2 VDD3 VDD4 R235 49_9R-0402SMT D 1 2 1 2 1 2 1 2 2 1 2 1 2 2 1 2 1 2 1 2 1 2 2 1 96 4 15 21 29 37 42 53 58 69 83 77 90 RJ45 Place termination resistors RX_D0-7, RX_ER, RX_DV, RX_CLK, TX_CLK, CRS, COL as close to the G-PHY as possible using 50 ohm impedence traces. LED-SMT1206_GREEN 2 1 1 2 C248 10NF-0402SMT Place 2 1 0402 1 4 LED-SMT1206_GREEN 1 2 VDD25_0 R226 49_9R-0402SMT ETH_CLK_TO_MAC IO_VDD1 IO_VDD2 IO_VDD3 IO_VDD4 IO_VDD5 IO_VDD6 IO_VDD7 IO_VDD8 IO_VDD9 O_VDD0 IO_VDD10 IO_VDD11 R236 49_9R-0402SMT 1 2 5 1 99 97 5 12 20 16 26 22 36 30 38 49 43 54 64 59 74 70 82 78 93 91 104 106 107 110 112 113 116 118 119 122 124 125 128 1 2 1 VSS0 PGM_VSS0 IO_VSS1 CORE_VSS1 CORE_VSS2 IO_VSS2 CORE_VSS3 IO_VSS3 CORE_VSS4 IO_VSS4 IO_VSS5 CORE_VSS5 IO_VSS6 IO_VSS7 CORE_VSS6 IO_VSS8 CORE_VSS7 IO_VSS9 O_VSS0 IO_VSS10 CORE_VSS8 IO_VSS11 RX_DVSS0 VSS1 CD_VSS1 CD_VSS2 VSS2 CD2_VSS1 CD2_VSS2 VSS3 CD3_VSS1 CD3_VSS2 VSS4 CD4_VSS1 CD4_VSS2 2 2 1 2 1 2 26 1 of 14 R ev 1.0 A B C D Lattice Semiconductor LatticeSC PCI Express x1 Evaluation Board User’s Guide Figure 13. 10/100/1000 PHY A 5 R1 100NF-0603SMT + C298 + C312 RLDRAM_VDD C304 C299 C313 RLDRAM_VDDQ C300 RLDRAM_VEXT C305 100NF-0603SMT + C303 J2 J2 R1=50 Ohm G2 H2 1UF-16V-0805SMT CTS-RT1402B7 100NF-0603SMT A3 B3 C3 D3 E3 F3 G3 H3 J3 100NF-0603SMT A3 B3 C3 D3 E3 F3 G3 H3 J3 R1 R1 F2 F2 C306 C283 C293 10NF-0603SMT 100NF-0603SMT C282 RLDRAM_A18 RLDRAM_A19 RLDRAM_A20 RLDRAM_A21 RLDRAM_A22 RLDRAM_BA2 RLDRAM_BA1 RLDRAM_BA0 RLDRAM_REF# E2 E2 100NF-0603SMT B CTS-RT1402B7 R1 RP3 A1 B1 C1 D1 E1 F1 G1 H1 J1 RLDRAM_A9 RLDRAM_A10 RLDRAM_A11 RLDRAM_A12 RLDRAM_A13 RLDRAM_A14 RLDRAM_A15 RLDRAM_A16 RLDRAM_A17 22UF-16V_TANTBSMT RP4 A1 B1 C1 D1 E1 F1 G1 H1 J1 A1 B1 C1 D1 E1 F1 G1 H1 J1 4 RLDRAM_CS# RLDRAM_WE# RLDRAM_DM Place resistors as close to RLDRAM device as possible. 22UF-16V_TANTBSMT D2 D2 C314 22UF-16V_TANTBSMT C2 C2 C301 H2 1UF-16V-0805SMT B2 10NF-0603SMT G2 1UF-16V-0805SMT A2 C315 B2 10NF-0603SMT C280 C290 J2 J2 H2 H2 G2 G2 F2 F2 D2 D2 B2 B2 C2 C2 A2 A2 E2 E2 R1=50 Ohm C302 A2 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT + C275 C276 RLDRAM_VTT R242 0R-0603SMT 10UF-16V_TANTBSMT C281 C291 A1 B1 C1 D1 E1 F1 G1 H1 J1 100NF-0603SMT 100NF-0603SMT C292 A3 B3 C3 D3 E3 F3 G3 H3 J3 C307 10NF-0603SMT A3 B3 C3 D3 E3 F3 G3 H3 J3 C308 RLDRAM_A0 RLDRAM_A1 RLDRAM_A2 RLDRAM_A3 RLDRAM_A4 RLDRAM_A5 RLDRAM_A6 RLDRAM_A7 RLDRAM_A8 22UF-16V_TANTBSMT 100NF-0603SMT C316 C RLDRAM_VTT 100NF-0603SMT + C286 100NF-0603SMT C287 C288 47UF-16V_TANTBSMT C284 100NF-0603SMT VTT VSENSE C310 C296 C294 LP2996-SO8 8 3 + SP1 SP5 SP2 SP6 SP3 SP7 SP4 RLDRAM_VEXT RLDRAM_VDD R244 OPEN-0603SMT VREF_B RLDRAM_VDDQ BLM41PG471SN1L FB6 1_8V + RLDRAM_VEXT RLDRAM_VDD BLM41PG471SN1L FB5 1_8V + 5 4 2 C285 BLM41PG471SN1L FB4 2_5V VDDQ VREF SD U24 100NF-0603SMT SP8 VREF_RLD R245 0R-0603SMT R241 1K_ADJ/SMT3MM VREF_B_W 3 RLDRAM_VEXT RLDRAM_VTT RLDRAM_VDD RLDRAM_VDDQ R240 R239 RLDRAM_VDDQ Place SP Testpoints (.025 square pads) around RLDRAM BGA as close as possible to edge balls. + C289 + 2_5V 10NF-0603SMT RLDRAM_VDDQ 3 C279 D C309 1 1UF-16V-0805SMT C295 4 100NF-0603SMT C277 1UF-16V-0805SMT C297 1UF-16V-0805SMT C311 C278 4_7K-0603SMT R243 1K-0603SMT 1K-0603SMT 5 100NF-0603SMT 7 6 PVIN AVIN GND 47UF-16V_TANTBSMT 47UF-16V_TANTBSMT J2 J1 V12 V11 A11 A12 T12 T1 C12 C1 V10 V3 A10 A3 V1 A1 T9 T4 P9 P4 E9 E4 C9 C4 K10 K9 K4 K3 B1 G4 G9 J3 J4 J9 J10 M9 M4 U1 U12 B12 V9 V4 R1 L10 L9 L4 L3 A2 A4 A9 D12 H3 H4 H9 H10 R12 U9 U4 B4 B9 D4 D9 F4 F9 N4 N9 R4 R9 1_8V 2 R247 220R-0603SMT R246 OPEN-0603SMT RLDRAM_II_CIO_SIO_0 NFU2 NFU1 TDI TDO TMS TCK VTT VTT VTT VTT VEXT VEXT VEXT VEXT VREF VREF VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ U23 2 RLDRAM-II CIO/SIO 144-BALL FBGA ZQ 1UF-16V-0805SMT 47UF-16V_TANTBSMT 1 1 1 1 1 1 1 1 27 V2 D a te : S iz e C Title D11 R2 R3 D10 U3 T3 P3 N3 U10 T10 R10 P10 N10 F3 E3 D3 C3 B3 F10 E10 C10 B10 G12 G11 G10 H12 H11 F1 G2 G3 G1 H2 M12 M11 M10 L12 L11 P1 M2 M3 N1 N12 E12 E1 D1 B11 C11 E11 F11 B2 C2 D2 E2 F2 N11 P11 R11 T11 U11 N2 P2 T2 U2 L1 L2 M1 P12 K12 J12 H1 K11 J11 K1 K2 F12 RLDRAM_Q17 RLDRAM_Q16 RLDRAM_Q15 RLDRAM_Q14 RLDRAM_Q13 RLDRAM_Q12 RLDRAM_Q11 RLDRAM_Q10 RLDRAM_Q9 RLDRAM_Q8 RLDRAM_Q7 RLDRAM_Q6 RLDRAM_Q5 RLDRAM_Q4 RLDRAM_Q3 RLDRAM_Q2 RLDRAM_Q1 RLDRAM_Q0 RLDRAM_A0 RLDRAM_A1 RLDRAM_A2 RLDRAM_A3 RLDRAM_A4 RLDRAM_A5 RLDRAM_A6 RLDRAM_A7 RLDRAM_A8 RLDRAM_A9 RLDRAM_A10 RLDRAM_A11 RLDRAM_A12 RLDRAM_A13 RLDRAM_A14 RLDRAM_A15 RLDRAM_A16 RLDRAM_A17 RLDRAM_A18 RLDRAM_A19 RLDRAM_A20 RLDRAM_A21 RLDRAM_A22 RLDRAM_D0 RLDRAM_D1 RLDRAM_D2 RLDRAM_D3 RLDRAM_D4 RLDRAM_D5 RLDRAM_D6 RLDRAM_D7 RLDRAM_D8 RLDRAM_D9 RLDRAM_D10 RLDRAM_D11 RLDRAM_D12 RLDRAM_D13 RLDRAM_D14 RLDRAM_D15 RLDRAM_D16 RLDRAM_D17 RLDRAM_REF# RLDRAM_CS# RLDRAM_WE# RLDRAM_DM RLDRAM_CK# RLDRAM_CK RLDRAM_BA2 RLDRAM_BA1 RLDRAM_BA0 RLDRAM_DK RLDRAM_DK# RLDRAM_QVLD RLDRAM_QK0 RLDRAM_QK1 1 SC PCI EXPRESS Card P roje c t RLDRAM QK0 QK1 QK1# QK0# Q17 Q16 Q15 Q14 Q13 Q12 Q11 Q10 Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 REF# CS# WE# DM CK# CK B2 B1 B0 DK DK# QVLD 1 S he e t 11 of RLDRAM_REF# [12] RLDRAM_CS# [12] RLDRAM_WE# [12] RLDRAM_DM [12] RLDRAM_CK# [12] RLDRAM_CK [12] RLDRAM_BA2 [12] RLDRAM_BA1 [12] RLDRAM_BA0 [12] RLDRAM_DK [12] RLDRAM_DK# [12] RLDRAM_QVLD [12] 14 [12] [12] [12] RLDRAM_D[0:17] RLDRAM_A[0:19] RLDRAM_Q[0:17] RLDRAM_QK0 [12] RLDRAM_QK1 [12] R ev 1.0 A B C D Lattice Semiconductor LatticeSC PCI Express x1 Evaluation Board User’s Guide Figure 14. RLDRAM 100UF-FKSMT 1UF-16V-0805SMT 1UF-16V-0805SMT 28 A B C D LED8 LED7 LED1 LED2 LED3 LED4 LED5 LED6 [13] LA_CLK1 [13] LA_CLK2 [13] LA_[0..31] LA_CLK1 LA_CLK2 LA_0 LA_1 LA_2 LA_3 LA_4 LA_5 LA_6 LA_7 LA_8 LA_9 LA_10 LA_11 LA_12 LA_13 LA_14 LA_15 LA_16 LA_17 LA_18 LA_19 LA_20 LA_21 LA_22 LA_23 LA_24 LA_25 LA_26 LA_27 LA_28 LA_29 LA_30 LA_31 R285 0R-0603SMT BOURNS-3224W-202E-2K R248 LEDs and Switches Available in SCM15 & SCM25 [3] SC_QDR_VREF [13] SWITCH[1..8] [13] LED[1..8] 5 SGND Bank 2 DIFFR_3 PR29A/PCLKT3_0 PR29B/PCLKC3_0 PR29C/PCLKT3_1 PR29D/PCLKC3_1 PR30A PR30B PR30C/PCLKT3_3 PR31A PR31B PR31C/PCLKT3_2 PR31D/PCLKC3_2 PR34A PR34B PR34C/VREF1_3 PR34D PR35A PR35B PR35C PR36A PR36B PR38A PR38B PR39A PR39B PR40A PR40B PR42A PR42B PR42C PR42D/DIFFR_3 PR43A PR43B PR43C PR43D PR44A PR44B PR47A PR47B PR47C PR47D PR48A PR48C PR48B PR49A PR49B PR51A PR51B PR51D/VREF2_3 PR52A PR52B PR53A PR53B PR55A PR55B PR55C/LRC_DLLT_IN_E/LRC_DLLT_FB_F PR55D/LRC_DLLC_IN_E/LRC_DLLC_FB_F PR56A PR56B PR57A/LRC_DLLT_IN_F/LRC_DLLT_FB_E PR57B/LRC_DLLC_IN_F/LRC_DLLC_FB_E PR57C/LRC_PLLT_IN_B/LRC_PLLT_FB_A PR57D/LRC_PLLC_IN_B/LRC_PLLC_FB_A Off Page Connections QDR_A0 QDR_A1 QDR_A2 QDR_A3 QDR_A4 QDR_A5 QDR_A6 QDR_A7 QDR_A8 QDR_A9 QDR_A10 QDR_A11 QDR_A12 QDR_A13 QDR_A14 QDR_A15 QDR_A16 QDR_A17 [10] ETH_CRS [10] ETH_COL [10] ETH_RX_CLK [10] ETH_RX_DV [10] ETH_TX_EN [10] ETH_TX_CLK [10] ETH_GTX_CLK [10] ETH_CLK_TO_MAC [8] FPGA_REFCLKP_L [8] FPGA_REFCLKN_L [10] ETH_RX_D[0..7] [10] ETH_TX_D[0..7] 4 ETH_RX_D4 ETH_RX_D5 ETH_RX_D6 ETH_RX_D7 ETH_CRS ETH_COL ETH_RX_CLK ETH_RX_DV ETH_TX_EN ETH_TX_CLK ETH_GTX_CLK ETH_CLK_TO_MAC ETH_TX_D0 ETH_TX_D1 ETH_TX_D2 ETH_TX_D3 ETH_TX_D4 ETH_TX_D5 ETH_TX_D6 ETH_TX_D7 ETH_RX_D0 ETH_RX_D1 ETH_RX_D2 ETH_RX_D3 D3 D2 J6 J5 E3 E2 K4 J4 F3 G3 K5 K6 G2 G1 L5 M5 F2 F1 E1 D1 K3 L3 L6 M6 J1 K1 L1 M1 P8 R8 P28 QDR_A11 R28 SGND R26 QDR_A10 R25 QDR_A9 N28 QDR_A8 N29 QDR_A7 P27 QDR_A6 P29 QDR_A5 R29 SGND L29 QDR_A4 M30 T28 QDR_A3 U28 SC_QDR_VREF T26 QDR_A2 U26 LVDS_OUTP M29 LVDS_OUTN N30 T24 T29 U29 LOOP_P0 P30 LOOP_N0 R30 LOOP_P2 U27 LOOP_N2 V27 LOOP_P3 R27 LOOP_N3 T27 V28 QDR_A1 W28 U25 DIFFR_3 V25 QDR_A0 T30 U30 V26 W26 LOOP_P1 V29 LOOP_N1 W29 LOOP_P2 V30 LOOP_N2 W30 LOOP_P3 Y27 LOOP_N3 W27 QDR_WRITE_N Y30 Y25 QDR_READ_N AA30 LOOP_P0 AA25 LOOP_N0 AB25 LOOP_P1 AD30 LOOP_N1 AE30 SC_QDR_VREF AB27 LVDS_INP AB28 LVDS_INN AC28 AD29 AE29 AF30 LVDS_PROBEP AG30 LVDS_PROBEN AB26 AC26 AC27 AD28 AF29 AF28 AD26 AC25 [11] RLDRAM_WE# [11] RLDRAM_CS# SC25-900fpBGA 3 [9] RLDRAM_CS# LA_CLK1 LA_CLK2 RLDRAM_WE# LA_0 LA_1 RLDRAM_REF# RLDRAM_BA0 RLDRAM_BA1 RLDRAM_BA2 LA_2 LA_3 SGND RLDRAM_A0 RLDRAM_A1 RLDRAM_A2 RLDRAM_A3 RLDRAM_A4 RLDRAM_A5 RLDRAM_A6 RLDRAM_A7 RLDRAM_A9 RLDRAM_A8 RLDRAM_A10 RLDRAM_A11 RLDRAM_A12 RLDRAM_A13 RLDRAM_A14 RLDRAM_A15 RLDRAM_A16 RLDRAM_A17 RLDRAM_A18 RLDRAM_A19 LA_4 LA_5 LA_6 LA_7 LA_8 LA_9 LA_10 LA_11 LA_12 LA_13 LA_14 RLDRAM_DM LA_15 LA_16 LA_17 LA_18 LA_19 LA_20 LA_21 LA_22 LA_23 LA_24 LA_25 LA_26 LA_27 LA_28 LA_29 LA_30 LA_31 3 AH1 AJ1 AF4 AE5 AG3 AH2 AD6 AJ2 AK2 AD7 AD8 AF7 AF6 AH4 AG5 AF8 AG8 AH3 AJ3 AF9 AE10 AK3 AJ4 AE11 AF10 AH7 AH8 AE12 AE13 AK4 AK5 AJ5 AJ6 AJ7 AJ8 AH10 AH11 AF13 AE14 AK6 AK7 AF14 AF15 AJ11 AJ12 AG13 AH13 AK8 AK9 AH14 AG14 AK10 AK11 AH15 AG15 AH12 AJ13 AD15 AE15 AK12 AK13 AJ14 AJ15 AK14 AK15 Bank 5 N2 N1 R7 R6 N3 P3 P4 P2 R2 T3 R3 P1 R1 R5 R4 T2 U2 T6 U3 V3 T1 U1 T5 T4 U4 U5 V1 W1 U6 V6 V2 W2 V5 V4 Y1 AA1 Y2 AA2 Y3 W3 AB1 AC1 W5 Y5 Y6 AD2 AE2 AB5 AC3 AD3 AC4 AD4 AF1 AG1 AB6 AC5 AE3 AF3 AF2 AG2 AC6 AC7 SC25-900fpBGA SGND RLDRAM_Q14 RLDRAM_Q13 SC_RLDRAM_VREF RLDRAM_Q12 RLDRAM_Q11 RLDRAM_Q10 RLDRAM_Q9 RLDRAM_Q8 RLDRAM_Q7 RLDRAM_Q6 RLDRAM_Q5 RLDRAM_Q4 RLDRAM_Q3 RLDRAM_Q2 RLDRAM_Q1 RLDRAM_Q0 SGND RLDRAM_QK0 RLDRAM_QK1 SGND SGND SGND RLDRAM_D0 RLDRAM_D1 RLDRAM_D2 RLDRAM_D3 RLDRAM_D4 RLDRAM_D5 RLDRAM_D6 RLDRAM_D7 RLDRAM_D8 RLDRAM_D9 RLDRAM_D10 RLDRAM_D11 RLDRAM_D12 RLDRAM_D13 RLDRAM_D14 RLDRAM_D15 RLDRAM_D16 RLDRAM_D17 RLDRAM_CK RLDRAM_CK# RLDRAM_DK RLDRAM_DK# SC-900FPBGA 2 PB37A PB37B PB38A PB38B PB38C PB39A PB39B PB38D PB41A PB41B PB42A PB42B PB42C PB42D PB43A PB43B PB46A/PCLKT4_2 PB46B/PCLKC4_2 PB47A/PCLKT4_1 PB47B/PCLKC4_1 PB49A/PCLKT4_0 PB49B/PCLKC4_0 PB49C/VREF2_4 PB49D PB51A/PCLKT4_5 PB51B/PCLKC4_5 PB51C/DIFFR_4 PB51D PB52A/PCLKT4_3 PB52B/PCLKC4_3 PB52C/PCLKT4_4 PB52D/PCLKC4_4 PB53A PB53B PB55A PB55B PB56A PB56B PB56C PB57A PB57B PB59A PB59B PB60A PB60B PB60C PB61A PB61B PB63A PB63B PB64A PB64B PB65A PB65B PB67A PB67B PB67C/VREF1_4 PB67D PB68A/LRC_DLLT_IN_C/LRC_DLLT_FB_D PB68B/LRC_DLLC_IN_C/LRC_DLLC_FB_D PB68C PB68D PB69A/LRC_PLLT_IN_A/LRC_PLLT_FB_B PB69B/LRC_PLLC_IN_A/LRC_PLLC_FB_B PB69C/LRC_DLLT_IN_D/LRC_DLLT_FB_C PB69D/LRC_DLLC_IN_D/LRC_DLLC_FB_C 2 Bank 4 QDR_D0 AK16 QDR_D1 AK17 QDR_D2 AJ16 QDR_D3 AJ17 QDR_D4 AE16 QDR_D5 AH16 QDR_D6 AG16 SGND AF16 QDR_D7 AK18 QDR_D8 AK19 QDR_D9 AH17 QDR_D10 AH18 SGND AF17 QDR_D11 AG17 QDR_D12 AJ18 QDR_D13 AJ19 QDR_D14 AK20 QDR_D15 AK21 QDR_D16 AF18 QDR_D17 AG18 QDR_K AJ20 QDR_K# AJ21 AG19 SC_QDR_VREF SGND AF19 AK22 AK23 AH19 AH20 QDR_CQ AK24 AK25 AE19 AE20 SGND AE21 QDR_Q17 AF21 QDR_Q16 AG21 QDR_Q15 AG22 QDR_Q14 AH22 QDR_Q13 AH23 QDR_Q12 AH21 SGND AD23 AE23 SGND AH24 AH25 QDR_Q11 AK28 QDR_Q10 AK29 QDR_Q9 AE22 SGND AH26 AH27 AF24 AG24 AG25 AF25 SGND AG26 AF27 QDR_Q8 AJ28 QDR_Q7 AH28 AE24 SC_QDR_VREF QDR_Q6 AE25 QDR_Q5 AJ29 QDR_Q4 AH29 AE26 SGND AD25 QDR_Q3 AJ30 QDR_Q2 AH30 QDR_Q1 AG28 QDR_Q0 AG29 1 QDR_CQ [9] QDR_K [9] QDR_K_# [9] QDR_Q[0..17] QDR_D[0..17] [9] [9] [11] OSC_IN_4 [7] RLDRAM_QK0 [11] RLDRAM_QK1 [11] RLDRAM_CK [11] RLDRAM_CK# [11] RLDRAM_DK [11] RLDRAM_DK# [11] RLDRAM_D[0:17] [11] SC_RLDRAM_VREF RLDRAM_QVLD [11] RLDRAM_Q[0:17] [3] D a te : S iz e C Title 1 SC PCI EXPRESS Card P roje c t FPGA Banks BANK 7 VCCIO = 2.5V S he e t 12 of BANK 2, 3, 4, 5, 6 VCCIO = 1.8V SC_RLDRAM_VREF 14 R ev 1.0 SCM15 QDR MACO PREFERRED PINS SCM25 RLDRAM MACO PREFERRED PINS Bottom SGND RLDRAM_QVLD RLDRAM_Q17 RLDRAM_Q16 SGND RLDRAM_Q15 SGND PB3A/LLC_PLLT_IN_A/LLC_PLLT_FB_B PB3B/LLC_PLLC_IN_A/LLC_PLLC_FB_B PB3C/LLC_DLLT_IN_C/LLC_DLLT_FB_D PB3D/LLC_DLLC_IN_C/LLC_DLLC_FB_D PB4A/LLC_DLLT_IN_D/LLC_DLLT_FB_C PB4B/LLC_DLLC_IN_D/LLC_DLLC_FB_C PB4C PB5A PB5B PB5C PB5D/VREF1_5 PB7A PB7B PB8A PB8B PB9A PB9B PB11A PB11B PB11C PB11D PB12A PB12B PB13A PB13B PB15A PB15B PB15C PB15D PB16A PB16B PB17A PB17B PB19A PB19B PB20A/PCLKT5_3 PB20B/PCLKC5_3 PB20C/PCLKT5_4 PB20D/PCLKC5_4 PB21A/PCLKT5_5 PB21B/PCLKC5_5 PB21C/DIFFR_5 PB21D PB23A/PCLKT5_0 PB23B/PCLKC5_0 PB23C PB23D/VREF2_5 PB24A/PCLKT5_1 PB24B/PCLKC5_1 PB25A/PCLKT5_2 PB25B/PCLKC5_2 PB28A PB28B PB29A PB29B PB31A PB31B PB31C PB31D PB32A PB32B PB33A PB33B PB35A PB35B U1J PL29A/PCLKT6_0 PL29B/PCLKC6_0 PL29C/PCLKT6_1 PL29D/PCLKC6_1 PL30A PL30B PL30C/PCLKT6_3 PL31A PL31B PL31C/PCLKT6_2 PL31D/PCLKC6_2 PL34A PL34B PL34C/VREF1_6 PL34D PL35A PL35B PL35C PL36A PL36B PL38A PL38B PL39A PL39B PL40A PL40B PL42A PL42B PL42C PL42D/DIFFR_6 PL43A PL43B PL43C PL43D PL44A PL44B PL47A PL47B PL47C PL47D PL48A PL48B PL48C PL49A PL49B PL51A PL51B PL51D/VREF2_6 PL52A PL52B PL53A PL53B PL55A PL55B PL55C/LLC_DLLT_IN_E/LLC_DLLT_FB_F PL55D/LLC_DLLC_IN_E/LLC_DLLC_FB_F PL56A PL56B PL57A/LLC_DLLT_IN_F/LLC_DLLT_FB_E PL57B/LLC_DLLC_IN_F/LLC_DLLC_FB_E PL57C/LLC_PLLT_IN_B/LLC_PLLT_FB_A PL57D/LLC_PLLC_IN_B/LLC_PLLC_FB_A SC-900FPBGA LEFT FPGA_REFCLKP_R [8] FPGA_REFCLKN_R [8] LVDS_PROBEP [13] LVDS_PROBEN [13] LVDS_INP [13] LVDS_INN [13] QDR_READ_N [9] [11] RLDRAM_DM QDR_WRITE_N LVDS_OUTP [13] LVDS_OUTN [13] [11] RLDRAM_A[0:19] [11] RLDRAM_REF# [11] RLDRAM_BA0 [11] RLDRAM_BA1 [11] RLDRAM_BA2 OSC_IN_3 [7] PL16A/ULC_PLLT_IN_A/ULC_PLLT_FB_B/DEBUG_BUS11 PL16B/ULC_PLLC_IN_A/ULC_PLLC_FB_B/DEBUG_BUS10 PL16C/DEBUG_BUS13 PL16D PL17A/ULC_DLLT_IN_C/ULC_DLLT_FB_D/DEBUG_BUS9 PL17B/ULC_DLLC_IN_C/ULC_DLLC_FB_D/DEBUG_BUS8 PL17C/ULC_PLLT_IN_B/ULC_PLLT_FB_A PL17D/ULC_PLLC_IN_B/ULC_PLLC_FB_A PL18A/ULC_DLLT_IN_D/ULC_DLLT_FB_C PL18B/ULC_DLLC_IN_D/ULC_DLLC_FB_C PL18C/DEBUG_BUS12 PL18D/VREF2_7/DEBUG_BUS6 PL20A PL20B PL21A PL21B PL22A PL22B PL22C PL22D PL25A/TESTCFGN PL25B/DEBUG_BUS7 PL25C/VREF1_7/DEBUG_BUS5 PL25D/DIFFR_7/DEBUG_BUS4 PL26A/PCLKT7_1/DEBUG_BUS3 PL26B/PCLKC7_1/DEBUG_BUS2 PL27A/PCLKT7_0/DEBUG_BUS1 PL27B/PCLKC7_0/DEBUG_BUS0 PL27C/PCLKT7_2/DEBUG_BUS14 PL27D/PCLKC7_2/DEBUG_BUS15 U1M PHY to MAC Interface/ Available in SCM15 & SCM25 SC25-900fpBGA 4 BANK 3 LOOP[2:3], Not Available in SCM15 RIGHT SC-900FPBGA PR16A/URC_PLLT_IN_A/URC_PLLT_FB_B PR16B/URC_PLLC_IN_A/URC_PLLC_FB_B PR16C PR16D PR17A/URC_DLLT_IN_C/URC_DLLT_FB_D PR17B/URC_DLLC_IN_C/URC_DLLC_FB_D PR17C/URC_PLLT_IN_B/URC_PLLT_FB_A PR17D/URC_PLLC_IN_B/URC_PLLC_FB_A PR18A/URC_DLLT_IN_D/URC_DLLT_FB_C PR18B/URC_DLLC_IN_D/URC_DLLC_FB_C PR18C PR18D/VREF2_2 PR20A PR20B PR21A PR21B PR22A PR22B PR22C PR22D PR25A PR25B PR25C/VREF1_2 PR25D/DIFFR_2 PR26A/PCLKT2_1 PR26B/PCLKC2_1 PR27A/PCLKT2_0 PR27B/PCLKC2_0 PR27C/PCLKT2_2 PR27D/PCLKC2_2 U1N [9] QDR_A[0..17] R249 0R-0603SMT QDR_A12 QDR_A13 QDR_A14 SWITCH5 SWITCH6 SWITCH7 SWITCH8 QDR_A17 QDR_A16 SC_QDR_VREF QDR_A15 SWITCH1 SWITCH2 SWITCH3 SWITCH4 D28 E28 H26 G26 D29 D30 K25 K26 G28 F28 L25 L26 G27 H27 L27 M27 E29 E30 J28 H28 F29 G29 M25 M26 H30 J30 K30 L30 P26 N27 R250 1_1K-0603SMT [5] PCIE_CLKP [5] PCIE_CLKN MUST USE LVCMOS18 BUFFER TYPES FOR LOGIC ANALYZER QDR_Q[0..17] QDR_A[0..17] 5 Bank 6 QDR_D[0..17] Bank 7 A B C D Lattice Semiconductor LatticeSC PCI Express x1 Evaluation Board User’s Guide Figure 15. FPGA Banks A B 8 7 6 5 4 3 2 1 16 15 14 13 12 11 10 9 SW4 5 16 15 14 13 12 11 10 9 3_3V R273 1 2 3 4 MAX6692 VCC DXP DXN OVERTN U26 1_8V C325 + 12_0V 24AA1025-ISM WP 3 VIN U28 SCL VCC A2 GND A1 SDA 2 LD1085CDT50-DPAK VOUT SWITCH8 SWITCH7 SWITCH6 SWITCH5 SWITCH4 SWITCH3 SWITCH2 SWITCH1 C326 + R264 13 8 16 1 3 4 5 2 6 11 10 SCL SDA [12] I2C GND T1OUT T2OUT R1OUT R2OUT 15 14 7 12 9 VR1 20K POT Murata PV37W101C01 PV37W ANODE 2 Backlight Adjustment SWITCH[1..8] 100NF-0603SMT C324 4 MAX3232 TSSOP16 VCC C1+ C1C2+ C2V+ V- T1IN T2IN R1IN R2IN U25 Address-1001100 2_5V SCL 6 8 7 SDA 8 7 6 5 100NF-0603SMT 5 EEPROM 4 3 2 A0 U27 SWITCHES 2_5V 1 SMCLK SMDAT ALERTN GND RS232_TXD 3_3V 100NF-0603SMT C323 R262 200R-0805SMT C320 100NF-0402SMT 0402 TEMP SENSE R269 100K-0603SMT PTEMP 2200PF-0603SMT C322 16 0R-0603SMT RN3A EXB2HV472JV 4.7K TDA08H0SK1 8 7 6 5 4 3 2 1 R272 PTEMP 0R-0603SMT 15 1 [2] C319 100NF-0402SMT 0402 14 C321 C318 100NF-0402SMT 0402 13 3 C C317 100NF-0402SMT 0402 12 4 RS232_RXD R263 OPEN-0805SMT D 10 7 R265 [2] RS232_TXD GND 1 2 10UF-16V_TANTBSMT 11 6 0R-0805SMT 5 R277 9 10K-0603SMT 10UF-16V_TANTBSMT 8 10K-0603SMT 1 3 [2] RS232_RXD R276 10K-0603SMT 5 4 Contrast Adjustment 1 3 [2] [2] VR2 20K POT Murata PV37W203C01 PV37W 2 LCD0 LCD_R/W LCD1 LCD_DB0 LCD2 LCD_DB2 LCD3 LCD_DB4 LCD4 LCD_DB6 J40 Johnson 142-0711-201 J39 Johnson 142-0711-201 J38 Johnson 142-0711-201 J37 Johnson 142-0711-201 SCL SDA RS232 2 2 2 2 1 1 LED7 LED3 LED5 LED1 CATHODE VDD RS E DB1 DB3 DB5 DB7 2 4 6 8 10 12 14 16 LVDS_OUTN [12] LVDS_OUTP [12] LVDS_INN [12] LVDS_INP [12] LCD_Connector ANODE VSS VO R/W DB0 DB2 DB4 DB6 2 4 6 8 10 3 3 LCD Connector 1 3 5 7 9 11 13 15 J41 LVDS_OUTN R275 100R-0603SMT LVDS_OUTP LVDS_INN 1 LVDS_INP HEADER 5X2 1 1 3 5 7 9 J36 RN2A LCD_RS LCD_E LCD_DB1 LCD_DB3 LCD_DB5 LCD_DB7 1 DP2 3 R270 1 1 LVDS_PROBEP GREEN2 LCD[0..10] [2] LVDS_PROBEN [12] LVDS_PROBEP [12] Q14 2N2222/SOT23 LED-SMT1206_GREEN D21 C327 100NF-0603SMT 0603 LCD[0..10] LVDS_PROBEN LED-SMT1206_RED D19 [12] LED[1..8] Q12 2N2222/SOT23 12_0V 470R-1206SMT RED2 LED-SMT1206_GREEN D17 Q10 2N2222/SOT23 12_0V 470R-1206SMT R267 GREEN1 1 LED-SMT1206_RED D15 Q8 2N2222/SOT23 12_0V 470R-1206SMT R254 RED1 1 R274 100R-0603SMT LCD5 LCD6 LCD7 LCD8 LCD9 LCD10 7 10 EXB2HV103JV 10K RN2G 12 5 EXB2HV103JV 10K RN2E 3 14 EXB2HV103JV 10K RN2C 16 1 EXB2HV103JV 10K 470R-1206SMT R251 12_0V R 3 2 G 3 2 R 3 2 G 3 2 2 RN2B RN2D 15 2 EXB2HV103JV 10K LED7 LED8 D22 LED6 LED5 LED4 LED3 LED2 LED1 R266 680R-0603SMT R261 680R-0603SMT R260 680R-0603SMT BLUE1 1 [12] LA_[0..31] [12] LA_CLK1 8 9 EXB2HV103JV 10K RN2H 11 6 EXB2HV103JV 10K R271 1 BLUE2 1 D a te : S iz e C Title LA_CLK1 LA_0 LA_1 LA_2 LA_3 LA_4 LA_5 LA_6 LA_7 LA_8 LA_9 LA_10 LA_11 LA_12 LA_13 LA_14 LA_15 LA1 2_767004 5V SCL GND SDA CLK1 CLK 8 7 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 LA_CLK2 LA_16 LA_17 LA_18 LA_19 LA_20 LA_21 LA_22 LA_23 LA_24 LA_25 LA_26 LA_27 LA_28 LA_29 LA_30 LA_31 1 S he e t 13 of LA_CLK2 [12] 14 R ev 1.0 LED-SMT1206_BLUE D22 SC-900fpBGA x1 PCI EXPRESS Card P roje c t I2C,RS232,Test 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 LED-SMT1206_YELLOW D20 Q15 2N2222/SOT23 12_0V 470R-1206SMT YELLOW2 LED-SMT1206_BLUE D18 Q13 2N2222/SOT23 12_0V 470R-1206SMT R268 LOGIC ANALYZER PROBE LED8 LED6 RN2F 13 4 EXB2HV103JV 10K LED-SMT1206_YELLOW D16 Q11 2N2222/SOT23 12_0V 470R-1206SMT R255 YELLOW1 1 Q9 2N2222/SOT23 12_0V 470R-1206SMT R252 R258 680R-0603SMT LED4 LED2 1 R259 680R-0603SMT R257 680R-0603SMT R256 680R-0603SMT R253 680R-0603SMT D21 D20 D19 D18 D17 D16 D15 LED8 LED7 LED6 LED5 LED4 LED3 LED2 LED1 STATUS LEDS Layout LEDs along Backpanel PCB edge 2 Y 3 2 B 3 2 Y 3 2 B 3 2 29 2 A B C D Lattice Semiconductor LatticeSC PCI Express x1 Evaluation Board User’s Guide Figure 16. I2C RS232 Test 30 A B C VCCIO7 VCCIO6 VCCIO3 VCCIO2 2_5V VCCIO1 3.3V or 2.5V VDDTX VDDRX VDDP C331 C332 C333 C334 C335 C336 C337 C356 C357 C358 C359 C360 C361 C362 C366 C375 C370 C376 C377 C378 C379 C371 C390 C391 22PF-0402SMT C386 C392 C393 C394 C395 C396 C398 C399 C400 C401 C402 C403 C404 C431 C432 C433 C434 C435 C436 C437 C422 C423 C424 C425 C426 C427 C428 C429 C447 C448 C449 C450 C451 C452 1_8V C453 C454 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT C421 VCCIO1 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT C430 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT C397 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT C389 1000PF-0402SMT C385 C465 C466 C467 C468 C469 C470 C471 C472 C474 C475 C476 C477 C478 C479 C480 C481 C492 C493 C494 C495 C496 C497 C498 C499 5 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT C491 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT C473 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT C464 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT C446 C374 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT C373 VDDOB 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT C355 VDDIB 1_2VDDA VDDOB VDDIB C330 C338 C339 C340 C341 C342 C343 C344 C345 C346 C347 C348 C349 C350 C351 C352 C353 C354 2 4 C365 C367 C368 C369 C381 SC_QDR_VTT C382 C383 C372 C384 C456 VCCIO4 C457 2_5V C458 1000PF-0402SMT C387 C459 C460 22PF-0402SMT C388 C461 C462 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT C380 C463 VCC12 VCCAUX C483 VCCIO5 C484 C485 C486 C487 C488 C489 C490 M HOLE2 MH3 M HOLE2 MH4 M HOLE2 MH5 3 1 C406 C407 C408 VSS SC-900FPBGA C409 C410 C411 2_5V C412 C413 C414 C415 C416 C417 C418 C420 SC25-900fpBGA U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 M19 M20 A1 A30 C419 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 2 D a te : S iz e C Title 1 SC PCI EXPRESS Card P roje c t VSS/Decoupling S he e t 14 of 14 R ev 1.0 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT U1F GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND C405 Y19 Y20 N15 N16 N17 N18 N19 N20 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 TWO HOLES NEEDED FOR FACEPLATE ATTACHMENT PER PCIe Spec 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT C482 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT C455 C364 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT C363 VDDAX25 HSTL VTT SC_RLDRAM_VTT GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND AA15 AA16 AK1 AK30 K15 K16 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 M11 M12 M13 M14 M15 M16 M17 M18 N12 N13 N11 N14 D C329 3 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT C328 VCC_CORE 4 ALL CAPS PLACED UNDER BGA H1 K2 M3 N5 L4 M2 P6 H3 G4 Y4 AE1 AC2 AA3 AB4 AA5 AE8 AE6 AH5 AG9 AF11 AG12 AG6 AJ10 AJ27 AK26 AJ22 AF20 AJ25 AF23 AF22 AE27 AA27 AB29 Y29 Y26 AC30 F27 E27 F30 P25 H29 K29 R24 M28 J27 N26 E20 E21 F21 F23 D21 D20 G23 E18 C20 C11 A12 F8 E11 G8 D11 D10 H7 F10 E10 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC CORE 5 A B C D Lattice Semiconductor LatticeSC PCI Express x1 Evaluation Board User’s Guide Figure 17. VSS Decoupling Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Lattice: LFSC25E-P1-EV