LatticeXP2 Advanced Evaluation Board
User’s Guide
March 2011
Revision: EB30_01.5
LatticeXP2 Advanced
Evaluation Board User’s Guide
Lattice Semiconductor
Introduction
The LatticeXP2™ Advanced Evaluation Board provides a convenient platform to evaluate, test and debug user
designs and IP cores targeted for the LatticeXP2-17 FPGA. The board features of a LatticeXP2-17 FPGA in a 484
fpBGA package. The LatticeXP2 I/Os are connected to a rich variety of both generic and application-specific interfaces described later in this document.
Important: This document (including the schematics in the appendix) describes LatticeXP2 Advanced Evaluation
Boards marked as Rev B. This marking can be seen on the silkscreen of the printed circuit board, under the Lattice
Semiconductor logo.
The LatticeXP2 is a second-generation non-volatile FPGA device. It combines a Look-up Table (LUT) based FPGA
fabric with Flash non-volatile cells in a flexiFLASH™ architecture. The flexiFLASH approach provides benefits such
as instant-on, small footprint, on chip storage with FlashBAK™ embedded block memories and Serial TAG memory
and design security. The LatticeXP2 also support live updates with TransFR™, 128-bit AES encryption and dualboot technologies. The LatticeXP2 devices include LUT-based logic, distributed and embedded memory, Phase
Locked Loops (PLLs), pre-engineered source synchronous I/O and enhanced sysDSP™ blocks.
For a full description of the LatticeXP2 FPGA, see the Lattice website for data sheets, technical notes, technology
summaries and more: www.latticesemi.com.
Some common uses for the LatticeXP2 Advanced Evaluation Board include:
• Video and other DSP processing
• An analog-to-digital, and digital-to-analog mixed signal source/sink
• A single-board computer system
• A platform for evaluating the Input/Output (I/O) characteristics of the FPGA
• A platform for evaluation and development with Lattice IP cores
Features
Key features of the LatticeXP2 Advanced Evaluation Board include:
• SPI Serial Flash device included for low-cost, non-volatile configuration storage
• One 32-bit DDR2 SO-DIMM module connector
• 32-bit PCI connector
• Both a Tri-speed (10/100/1000 Mbit) Ethernet PHY that includes RJ-45, magnetics and spark gap, as well as a
directly wired RJ-45 connector
• RS-232 interface chip and 9-pin D-sub connector
• PS/2 Mouse connector
• USB 1.1 transceiver and USB type-A and type-B connectors
• USB download of LatticeXP2 and power manager bitstreams
• Video TX and RX MDR connectors
• Quad 12-bit ADC and Quad 12-bit DAC
• Two 8-pin DIP switches
• Discrete LEDs and 7-segment LED
• CompactFlash connector for type I and type II CompactFlash cards
• LCD module connector
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• Prototyping areas with access to 14 I/O pins
• Selectable I/O bank voltages
• Four pairs of SMA connectors for high speed differential signals
• Oscillator socket for both half-size and full-size oscillators
• 3.3V, 2.5V, 1.8V, 1.2V and ADJ (adjustable voltage) powers generated from a single 5V to 28V power source
• ispPAC®-POWR1220AT8 Power Manager II device for monitoring the 3.3V, 2.5V, 1.8V, 1.2V, ADJ voltages and
DDR Vref, Vtt voltages
• ispVM® System programming support
General Description
The heart of the board is the LatticeXP2 non-volatile FPGA. The board also provides several different interconnections and support devices that permit it to be used for a variety of purposes. The PCI connector, DDR2 socket, and
Tri-speed Ethernet PHY are useful for applications using Lattice IP cores.
A number of connectors are useful for general purpose of the LatticeXP2 I/O capability. These include the SMA
connectors, RS-232, Video Tx/Rx MDR connectors, and the various generic prototype access points.
The CompactFlash connector is also useful for expansion purposes. It provides the ability to add storage, or communication capabilities to the board.
Other features on the board help in evaluating the capabilities and performance of the LatticeXP2. The A/D, D/A,
and digital potentiometer are helpful for some basic mixed signal applications. The SMA connectors permit the
evaluation of high-speed differential signals, and protocols. The SPI memory showcases the failsafe capabilities of
the LatticeXP2.
The board also acts as a showcase for the ispPAC-POWR1220 power manager. The ispPAC-POWR1220 is a programmable device useful for safely managing the power supply system on the board. While the LatticeXP2 device
has no specific power-sequencing requirements, the ispPAC-POWR1220 device can be used to sequence and
monitor voltages.
Additional Resources
Additional resources for the LatticeXP2 Advanced Evaluation Board, such as updates to this document, sample
programs and links to demos can be found on the Lattice web site. Go to www.latticesemi.com/boards, and navigate to the appropriate page for this board.
Initial Setup and Handling
The following is recommended reading prior to removing the evaluation board from the static shielding bag and
may or may not apply to your particular use of the board.
CAUTION: The devices on the board can be damaged by improper handling.
The devices on the evaluation board contain fairly robust ESD (Electro Static Discharge) protection structures
within them, able to withstand typical static discharges (see the “Human Body Model” specification for an example
of ESD characterization requirements). Even so, the devices are static sensitive to conditions that exceed their
designed in protection. For example: higher static voltages, as well as lower voltages with lower series resistance
or larger capacitance than the respective ESD specifications require can potentially damage or degrade the
devices on the evaluation board.
As such, it is recommended that you wear an approved and functioning grounded wrist strap at all times while handling the evaluation board when it is removed from the static shielding bag. If you will not be using the board for a
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while, it’s best to put it back in the static shielding bag. Please save the static shielding bag and packing box for
future storage of the board when it is not in use.
When reaching for the board, it is recommended that you first touch the outside threaded portion of one of the gold
SMA connectors. This will neutralize any static voltage difference between your body and the board prior to any
contact with signal I/O.
CAUTION: to minimize the possibility of ESD damage, the first and last electrical connection to the board, should
always be from test equipment chassis ground to GND on the board (black banana jack).
Before connecting signals or power to the board, attach a cable from chassis ground on grounded test equipment
to the GND on the board. Connecting the board ground to test equipment chassis ground will decrease the risk of
ESD damage to the I/O on the board as the initial connections to the board are made. Likewise, when unplugging
cables from the evaluation board, the last connection unplugged, should be the chassis GND connection to eval
board GND. If you have signal sources that are floating with respect to chassis GND, attempt to neutralize any
static charge on that signal source prior to attaching it to the evaluation board.
If you are holding or carrying the board while it’s not in a static shielding bag, please keep one finger on the
threaded portion of one of the gold SMA connectors. This will keep the board at the same voltage potential as your
body until you can pick up the static shielding bag and put the board back in it.
Electrical, Mechanical, and Environmental Specifications
The nominal board dimensions are 12 inches by 6 inches. The environmental specifications are as follows:
• Operating temperature: 0°C to 55°C
• Storage temperature: -40°C to 75°C
• Humidity: VCC_3.3V
2-4 -> VCC_2.5V
3-5 -> VCC_1.8V
4-6 -> VCC_ADJ
1
VCC_2.5V
2
VCC_1.8V
3
VCC_1.8V
4
VCC_3.3V
5
VCC_3.3V
7
VCC_3.3V
Depending on the optional devices installed, some sysIO banks may have restrictions. For each of J34 and J37
only select one bank voltage position at that jumper. For example, attaching more than one jumper to J34’s 6
square pins will short supplies.
Table 6. sysIO Bank Considerations
Bank
Setting
0
Selectable. CompactFlash requires 3.3V.
1
Cannot be changed
2
3
4
5
6
Selectable. Video TX/RX requires 2.5V.
7
Cannot be changed
The following tables detail the various I/O standards supported by the LatticeXP2 sysIO structures. More information can be found in technical note TN1136, LatticeXP2 sysIO Usage Guide.
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Table 7. Mixed Voltage I/O Support
Input sysIO Standards
VCCIO
1.2V
1.2V
Yes
1.5V
Yes
1.8V
Yes
2.5V
3.3V
1.5V
1.8V
Output sysIO Standards
2.5V
3.3V
1.2V
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
1.5V
1.8V
2.5V
3.3V
Yes
Yes
Yes
Yes
For example, if VCCIO is 3.3V then signals from devices powered by 1.2V, 2.5V, or 3.3V can be input and the thresholds will be correct, assuming the user has selected the desired input level using ispLEVER® software. Output levels are tied directly to VCCIO.
Table 8. sysIO Standards Supported per Bank
Description
Top Side, Banks 0-1
Right Side, Banks 2-3 Bottom Side, Banks 4-5
Left Side, Banks 6-7
Types of I/O Buffers
Single-ended
Single-ended and
Differential
Single-ended
Single-ended and
Differential
Output standards
supported
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
SSTL18 Class I, II
SSTL25 Class I, II
SSTL33 Class I, II
SSTL18 Class I, II
SSTL25 Class I, II
SSTL33 Class I, II
SSTL18 Class I
SSTL2 Class I, II
SSTL3 Class I, II
SSTL18 Class I
SSTL2 Class I, II
SSTL3 Class I, II
HSTL15 Class I
HSTL18_I, II
HSTL15 Class I
HSTL18 Class I, II
HSTL15 Class I
HSTL18 Class I, II
HSTL15 Class I, III
HSTL18 Class I, II, III
SSTL18D Class I, II
SSTL25D Class I, II
SSTL33D Class I, II
SSTL18D Class I, II
SSTL25D Class I, II
SSTL33D Class I, II
SSTL18D Class I, II
SSTL25D Class I, II,
SSTL33D Class I, II
SSTL18D Class I,
SSTL25D Class I, II,
SSTL33D_I, II
HSTL15D Class I
HSTL18D Class I, II
HSTL15D Class I, II
HSTL18D Class I, II
HSTL15D Class I
HSTL18D Class I, II
HSTL15D Class I
HSTL18D Class I, II
PCI33
LVDS25E1
LVPECL1
BLVDS1
RSDS1
PCI33
LVDS
LVDS25E1
LVPECL1
BLVDS1
RSDS1
PCI33
LVDS25E1
LVPECL1
BLVDS1
RSDS1
PCI33
LVDS
LVDS25E1
LVPECL1
BLVDS1
RSDS1
Inputs
All Single-ended,
Differential
All Single-ended,
Differential
All Single-ended,
Differential
All Single-ended,
Differential
Clock Inputs
All Single-ended,
Differential
All Single-ended,
Differential
All Single-ended,
Differential
All Single-ended,
Differential
PCI Support
PCI33 no clamp
PCI33 no clamp
PCI33 with clamp
PCI33 no clamp
LVDS Output Buffers
LVDS (3.5mA) Buffers2
1. These differential standards are implemented by using complementary LVCMOS drivers and external resistors.
2. Available on 50% of the I/Os in the bank.
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Prototype Areas
For general purpose I/O testing or monitoring, numerous test points are provided for direct access. Some test
points are grouped together and arranged in a grid pattern according to their associated I/O bank and are labeled
with the pin locations on the silkscreen of the board. Other test point I/Os are brought out to IDC connectors J1 and
J10 with both source and end termination resistors available for high speed parallel signal transmission over ribbon
cable.
Differential Signal Connections
There are four pairs of SMA connectors and one RJ-45 connector connected directly to the LatticeXP2 differential
I/O pairs.
The eight SMA connectors are provided for clocks or general purpose, user-definable signals. The center pin is
wired to an I/O pin and the outer case is soldered to ground. Table 9 details to which I/O pin each SMA connector
is wired.
Table 9. SMA Connectors
Location
LatticeXP2 I/O
Polarity
sysIO Bank
Description
J121
A2*
Pair#0 P
0
PT4A/ULC_GPLLT_IN_A
J6
B3
Pair#0 N
0
PT4B/ULC_GPLLC_IN_A
J13
F7
Pair#1 P
0
PT5A/ULC_GPLLT_FB_A
J7
G7
Pair#1 N
0
PT5B/ULC_GPLLC_FB_A
J14
P4
Pair#2 P
6
PL37A
J8
P5
Pair#2 N
6
PL37B
J15
Y1
Pair#3 P
6
PL35A
J9
AA1
Pair#3 N
6
PL35B
1. The SMA connector on J12 is shared with the on-board oscillator. When this SMA connector is used, the jumper on
J17 needs to be removed.
RJ-45 Connectors
There are two RJ-45 connectors, J5 and J43, on the evaluation board. J5 is a simple RJ-45 female connector provided for general-purpose differential interfacing to the LatticeXP2 device, while J43 is a full featured Ethernet PHY
connection with internal magnetics and spark gap. The connections for J5 are listed in Table 10. J43 is described in
more detail in the Ethernet section later in this user guide.
Table 10. J5 RJ-45 Connections
J1 Pin
LatticeXP2 I/O
Polarity
SysIO Bank
Description
1
2
P2
Pair#0 P
6
PL32A
P3
Pair#0 N
6
PL32B
3
T1
Pair#1 P
6
PL30A/LDQS30
6
U1
Pair#1 N
6
PL30B
4
M4
Pair#2 P
6
PL28A
5
M5
Pair#2 N
6
PL28B
7
R5
Pair#3 P
6
PL40A
8
P6
Pair#3 N
6
PL40B
Oscillator
The 3.3V oscillator socket (Y1) accepts both full-size and half-size oscillators and can route to different clock
inputs, depending on its position within the socket (see Figure 2). The board is shipped with an EPSON programmable oscillator programmed to 33.33MHz.
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The 16-pin socket will allow connection to PLL clock pin A2 when the top of the oscillator is aligned to socket pins 1
and 16. Note that the SMA connector J12 is shared with the on-board oscillator. When installing the oscillator to
connect the clock to PLL clock pin A2, the SMA connector J12 cannot be used and the jumper on J17 needs to be
installed.
When the bottom of the oscillator is aligned to socket pins 8 and 9, the clock is provided to primary clock pin L4.
Figure 2. On-board Oscillator
SPI Serial Flash
SPI Serial Flash are available in three package styles. The device used this board is an 8-pin, 16-Mbit, sufficient to
store two bitstreams simultaneously in order to support SPIm mode.
Configuration/Programming Headers
Four programming headers are provided on the evaluation board, providing access to the LatticeXP2, MachXO™,
and ispPAC-POWR1220AT8 and LatticeXP2 SPI Slave JTAG ports. The JTAG connectors J25, J32, J39 and J40
are 1x10 headers. The JTAG ports for the LatticeXP2 and ispPAC-POWR1220AT8 devices can be configured as
loop-through connectors to allow for easy daisy chaining of multiple boards. With proper jumper selection (see the
next section) standard IDC ribbon cable can be used without the need to swap any wires on the cable.
The pinouts for these headers are provided in the following tables.
A USB ispDOWNLOAD® cable is included with each LatticeXP2 Advanced Evaluation Board. When using the 1x8
cable adapter, connect pin 1 of the cable to pin 1 of the 1x10 JTAG header.
Important Note: The board must be un-powered when connecting, disconnecting, or reconnecting the ispDOWNLOAD Cable or USB cable. Always connect an ispDOWNLOAD Cable’s GND pin (black wire), before connecting
any other JTAG pins. Failure to follow these procedures can in result in damage to the LatticeXP2 FPGA and render the board inoperable.
LatticeXP2 Configuration
Two programming headers, J39 and J40, are provided on the evaluation board, providing access to the LatticeXP2
JTAG port and the ispPAC-POWR1220AT8 JTAG port. The pinouts for the headers are provided in Table 11.
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Table 11. JTAG Programming Headers
Separate Programming
Chained Programming
Jumper on J49 (None on J45)
Pin
J39 Function
Jumper on J45 (None on J49)
J40 Function
J39 Function
J40 Function
1
Vcc (3.3V)
Vcc (3.3V)
Vcc (3.3V)
Not used
2
TDO of ispPAC-POWR1220AT8
TDO of LatticeXP2
TDO of ispPAC-POWR1220AT8
Not used
3
TDI of ispPAC-POWR1220AT8
TDI of LatticeXP2
TDI of LatticeXP2
Not used
4
NC
NC
NC
Not used
5
NC
NC
NC
Not used
6
TMS of both chips
TMS of both chips
TMS of both chips
Not used
7
GND
GND
GND
Not used
8
TCK of ispPAC-POWR1220AT8
TCK of LatticeXP2
TCK of both chips
Not used
9
NC
DONE of LatticeXP2
NC
Not used
10
NC
INITN of LatticeXP2
NC
Not used
J49 and J45 control the functions of the two programming headers. When a jumper is installed on J49, the programming header J39 is connected to the JTAG port of ispPAC-POWR1220AT8 and is used for programming the
ispPAC-POWR1220AT8 only; the programming header J40 is connected to the JTAG port of LatticeXP2 and is
used for programming the LatticeXP2 only.
When the jumper is moved from J49 to J45, the JTAG ports of the LatticeXP2 and ispPAC-POWR1220AT8 are
chained together. In this case, the programming header J40 is connected to the JTAG port of the LatticeXP2 first
and then chained with the JTAG port of ispPAC-POWR1220AT8. The programming header J39 should not be used
when the JTAG ports are chained together. During chained programming, the ispPAC-POWR1220AT8 device will
set the HVOUT1 signal (pin 86 of U17) tri-state until programming completes, so the enable for the 3.3V power for
the LatticeXP2 device will be interrupted during programming unless a jumper is installed at J52. After chained programming of the ispPAC-POWR1220AT8, the jumper at J52 can be removed.
Additional instructions and recommendations for programming this board are provided in the Configuring/Programming the Board section of this document.
Switches
There are two 8-position switches and six push-button switches for implementing basic static input functions.
Switches SW3, SW4, SW5, SW6, SW7 and SW10 are momentary switches. The pull-up resistors associated with
these switches are wired to 3.3V. Pushing the switches down produces a low (0), otherwise it produces a high (1).
The signals controlled by SW4, SW5, SW6, SW7 and SW10 are debounced by an MC14490 (U15) before connecting to an LatticeXP2 I/O pin. Table 12 shows the control relationship between the switches, LatticeXP2 and ispPACPOWR1220AT8 I/O pins.
Table 12. Momentary Switches
Switch
Connection
User-Definable
1
Debounced
SW3
Pin 97 of ispPAC-POWR1220AT8*
Yes
No
SW4
J6 of LatticeXP2 (PROGRAMN)
No
Yes
SW5
E12 of LatticeXP2 (GSRN)
Yes
Yes
SW6
W18 of LatticeXP2
Yes
Yes
SW7
W17 of LatticeXP2
Yes
Yes
SW10
U7 of LatticeXP2
Yes
Yes
1. SW3 signal is also connected (wire-AND) to position#1 of SW2. Therefore, when position#1 of SW2 is in the down position,
SW3 signal (POWR1220AT8 pin 97) will be low even when SW3 is not being pushed.
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SW2 and SW8 on the right side and the upper side of the board are 8-pin DIP switches. The pull-up resistors associated with these switches are wired to 3.3V. A switch in the down position produces a low (0), the up position produces a high (1). All signals of SW8 are debounced before connecting to LatticeXP2 I/O pins. Table 13 shows the
SW8 connections to the LatticeXP2 and Table 14 shows the SW2 connections to ispPAC-POWR1220AT8 I/O pins.
Table 13. 8-Position Switch SW8
Switch (Position#)
LatticeXP2 I/O
sysIO Bank
SW8 (position #1)
W15
4
SW8 (position #2)
U16
4
SW8 (position #3)
T16
4
SW8 (position #4)
Y15
4
SW8 (position #5)
Y16
4
SW8 (position #6)
Y18
4
SW8 (position #7)
Y17
4
SW8 (position #8)
W18
4
Switch (Position#)
POWR1220AT8
I/O Pin
Pin Name
SW2 (position #1)
97
IN1
SW2 (position #2)
1
IN2
SW2 (position #3)
2
IN3
SW2 (position #4)
4
IN4
SW2 (position #5)
6
IN5
SW2 (position #6)
7
IN6
SW2 (position #7)
89
VPS0
SW2 (position #8)
90
VPS1
Table 14. 8-Position Switch SW2
LEDs
The eight user-definable LEDs are provided on the lower right side of the board. These LEDs are each wired to a
separate general purpose I/O as defined in the Table 15. The current limiting resistors associated with these LEDs
are wired to 3.3V but it is safe to use any FPGA I/O voltage. The LED will light when its associated I/O pin is driven
low.
Table 15. Connection between LEDs and LatticeXP2
LED
LatticeXP2 I/O
Bank
LED
LatticeXP2 I/O
Bank
D17
AB18
4
D21
Y14
4
D18
AB19
4
D22
AA13
4
D19
V12
4
D24
AB16
4
D20
U12
4
D25
AB17
4
Table 16 describes the three LEDs associated with the dedicated programming pins.
Table 16. Programming LEDs
LED
Pin
Color
Function
D27
PROGRAMN
Yellow
On when signal is low
D29
INIT
Red
On when initializing
D28
DONE
Green
On when config is complete
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Seven Segment Display
The 7-segment LED located near the eight LEDs is controlled by LatticeXP2 Bank 4 I/O pins. The connections of
the segments are shown in Figure 3.
Figure 3. 7-Segment Display
LCD
The LCD module connector (J55) is a 2x9 header. This 18-pin header is compatible with quite a few character LCD
modules. Table 17 shows the pin function of the header and the connections to the bank 0 of the LatticeXP2 FPGA.
Table 17. LCD Header Connection
Pin #
Function
LatticeXP2 I/O
Pin #
Function
LatticeXP2 I/O
1
Anode
—
2
Cathode (GND)
—
3
VSS(GND)
—
4
VDD (5V)
—
5
VO
—
6
RS
U14
7
R/W
AA20
8
E
AA21
9
DB0
AB20
10
DB1
AA22
11
DB2
V14
12
DB3
Y21
13
DB4
W14
14
DB5
Y22
15
DB6
U15
16
DB7
V15
17
Anode
—
18
Cathode (GND)
—
The VR4 potentiometer is used to limit the current that flows through the backlight LED on the LCD module. The
VR5 potentiometer is used to adjust the VO voltage that controls the LCD contrast.
When the following LCD modules are used, connect pin 1 to 16 to the backlight LCD module or connect pin 1 to 14
to the non-backlight LCD module:
Optrex:
• C-51505 Series: 20 characters x 2 lines
When the following LCD modules are used, connect pin 3 to 18 to the backlight LCD module or connect pin 3 to 16
to the non-backlight LCD module.
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Lumex:
• LCM-S01601 Series: 16 characters x 1 line
• LCM-S00802 Series: 8 characters x 2 lines
• LCM-S01602 Series: 16 characters x 2 lines
• LCM-S02002 Series: 20 characters x 2 lines
• LCM-S02402 Series: 24 characters x 2 lines
• LCM-S04002 Series: 40 characters x 2 lines
• LCM-S02004 Series: 20 characters x 4 lines
• LCM-S02404 Series: 24 characters x 4 lines
Varitronix:
• MDLS-20189 Series: 20 characters x 1 line
• MDLS-20265 Series: 20 characters x 2 lines
• MDLS-24265 Series: 24 characters x 2 lines
• MDLS-40266 Series: 40 characters x 2 lines
Video TX and RX MDR Connectors
The video TX (J2) and RX (J3) MDR connectors accept 7:1 LVDS 2.5v differential video signals. The connections
between the connector pins and LatticeXP2 I/O are shown in Tables 18 and 19. All the pins are connected to Bank
6 I/Os. The Bank 6 supply voltage (VCCIO_6) must be set to select 2.5V for proper LVDS 2.5V signal levels.
Table 18. Video TX MDR Connections
Pin #
Function
LatticeXP2 I/O
Pin #
Function
LatticeXP2 I/O
1
—
—
14
TX_OUT0_N
Y4
2
GND
—
15
TX_OUT0_P
AA3
3
—
—
16
—
—
4
TX_OUT1_N
U5
17
GND
—
5
TX_OUT1_P
U4
18
—
—
6
TX_OUT2_N
V3
19
GND
—
7
TX_OUT2_P
U2
20
—
—
8
—
—
21
—
—
9
—
—
22
TX_CLKOUT_N
T2
10
GND
—
23
TX_CLKOUT_P
R2
11
—
—
24
—
—
12
TX_OUT3_N
R4
25
GND
—
13
TX_OUT3_P
R3
26
—
—
13
LatticeXP2 Advanced
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Lattice Semiconductor
Table 19. Video RX MDR Connections
Pin #
Function
LatticeXP2 I/O
Pin #
Function
LatticeXP2 I/O
1
—
—
14
RX_IN3_P
Y3
2
GND
—
15
RX_IN3_N
W3
3
—
—
16
—
—
4
RX_CLKIN_P
P1
17
GND
—
5
RX_CLKIN_N
R1
18
—
—
6
—
—
19
—
—
7
—
—
20
RX_IN2_P
R7
8
GND
—
21
RX_IN2_N
R6
9
—
—
22
RX_IN1_P
T3
10
GND
—
23
RX_IN1_N
U3
11
—
—
24
—
—
12
RX_IN0_P
T6
25
GND
—
13
RX_IN0_N
T7
26
—
—
CompactFlash
The CompactFlash connector (J38) on the board accepts both type-I and type-II CompactFlash cards. The connections between the connector pins and LatticeXP2 balls are shown in Table 20. All the pins are connected to Bank 1
I/Os.
Table 20. CompactFlash Connection
Pin #
Function
LatticeXP2 I/O
Pin #
Function
LatticeXP2 I/O
1
2
GND
—
26
CD1
A8
D3
A14
27
D11
B8
3
D4
B13
28
D12
A7
4
D5
F12
29
D13
F9
5
D6
F11
30
D14
E9
6
D7
C12
31
D15
C8
7
CE1/CS0
E11
32
CE2/CS1
D8
8
A10
A13
33
VS1
B7
9
OE/ATASEL
B12
34
IORD
B6
10
A9
A12
35
IOWR
A6
11
A8
B11
36
WE
A5
12
A7
G9
37
READY/IREQ/INTRQ
J7
13
VCC
—
38
VCC
—
14
A6
G8
39
CSEL
H7
15
A5
C11
40
VS2
C7
16
A4
D11
41
RESET
C6
17
A3
A11
42
WAIT/IORDY
A4
18
A2
A10
43
INPACK/DMARQ
A3
19
A1
B10
44
REG/DMACK
C4
20
A0
B9
45
BVD2/SPKR/DASP
C5
21
D0
E10
46
BVD1/STSCHG/PDIAG
E8
22
D1
F10
47
D8
F8
23
D2
C9
48
D9
D5
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LatticeXP2 Advanced
Evaluation Board User’s Guide
Lattice Semiconductor
Table 20. CompactFlash Connection (Continued)
Pin #
Function
LatticeXP2 I/O
Pin #
Function
LatticeXP2 I/O
24
WP/IOIS16/IOCS16
D9
49
D10
D6
25
CD2
A9
50
GND
—
USB 1.1
For implementing the USB interface, the LatticeXP2 board contains a USB 1.1 transceiver MAX3454EETE (or
NCN2500MNR2 from On Semiconductor), a type-A connector and a type-B USB connector. Note there is a third
USB connector, which is used for the built-in USB download cable, described later in this document.
Table 21. Header Settings for Configuring USB Interface as USB Host
Header/Connector
Jumper Position
Description
J21
Pin 1 and 2
Drive USB transceiver ENUM pin to GND to disconnect the internal 1.5K
resistor between Vtrm and D+ or D-.
J22 (D+)
Pin 1 and 2
Pull D+ signal low through an external 15K resistor.
J23 (D-)
Pin 1 and 2
Pull D- signal low through an external 15K resistor.
J24
Pin 1 and 2
Provide 5V power to the external USB device.
J16 (USB type A)
—
Type A is used while implementing USB host.
J20 (USB type B)
—
This connector is not used in this configuration.
Table 22. Header Settings for Configuring USB Interface as USB Device
Header/Connector
Jumper Position
Description
J21
Pin 2 and 3
Drive USB transceiver ENUM pin to 3.3V to connect the internal 1.5K
resistor between Vtrm and D+ or D-.
J22 (D+)
Pin 2 and 3
Disconnect D+ signal from the external 15K pull-down.
J23 (D-)
Pin 2 and 3
Disconnect D- signal from the external 15K pull-down.
J24
Pin 2 and 3
No 5V power is provided when implementing USB device.
J16 (USB type A)
—
This connector is not used in this configuration.
J20 (USB type B)
—
Type A is used while implementing USB host.
The connections between the USB 1.1 transceiver MAX3454EETE (or NCN2500MNR2 from On Semiconductor)
and the LatticeXP2 FPGA are shown in Table .
Table 23. Connections Between USB 1.1 Transceiver and LatticeXP2
Pin #
MAX3454EETE NCN2500MNR2
1
SPD
DSPD
LatticeXP2 I/O
D4
Description
Connect to LatticeXP2 bank 7 I/O
2
RCV
RCV
E3
Connect to LatticeXP2 bank 7 I/O
3
VP
VP
C1
Connect to LatticeXP2 bank 7 I/O
4
VM
VM
D1
Connect to LatticeXP2 bank 7 I/O
5
NC
EN_Vobus#
—
Connect to 3.3V
6
GND
GND
—
Connect to GND
7
SUS
SPND
E1
Connect to LatticeXP2 bank 7 I/O
8
NC
NC
—
No connect
9
OE#
OE#
D3
Connect to LatticeXP2 bank 7 I/O
10
D-
D-
—
Connect to USB connectors through 33 Ohm resistor
11
D+
D+
—
Connect to USB connectors through 33 Ohm resistor
12
Vtrm
Vreg
—
Connect to GND though a capacitor
15
LatticeXP2 Advanced
Evaluation Board User’s Guide
Lattice Semiconductor
Table 23. Connections Between USB 1.1 Transceiver and LatticeXP2 (Continued)
Pin #
MAX3454EETE NCN2500MNR2
LatticeXP2 I/O
Description
13
ENUM
Vobus
—
Connect to J21 pin 2
14
Vbus
Vusb
—
Connect to USB connectors
15
VL
Vcc
—
Connect to 3.3V
16
NC
EN_RPU
—
Connect to J21 pin 2
PS/2 Mouse
The PS/2 mouse connector (JP1) on this board connects the clock and data through the PCA9306 level translator
to the LatticeXP2. The clock and data are connected as described in Table 24.
Table 24. Connections Between PS/2 Mouse Connector and LatticeXP2
JP1 Pin #
Signal
LatticeXP2 I/O
1
DATA
V5
PS/2 data signal, open drain
Description
5
CLOCK
V4
PS/2 clock signal, open drain
RS-232
The RS-232 interface on this board includes a RS-232 interface chip (MAX3232), a 9-pin D-sub female connector
and four headers. This RS-232 interface can be configured to DCE or DTE by changing the jumper settings of J27,
J28, J29 and J30 headers. These headers are used to connect the MAX3232 to the D-sub connector. Installing
jumpers on Pin 1 and Pin 2 of these headers configures the RS-232 to DCE. Installing jumpers on Pin 2 and Pin 3
of these headers configures the RS-232 to DTE. The connections and functions of the signals between MAX3232
and LatticeXP2 stay the same for DCE and DTE configurations. These are listed in Table 25.
Table 25. Connections Between MAX3232 and LatticeXP2
Signal Name
MAX3232 Pin
LatticeXP2 I/O
LatticeXP2 Bank
LatticeXP2 I/O Type
/CTS
9 (R2OUT)
C3
7
Input
RXD
12 (R1OUT)
B2
7
Input
TXD
11 (T1IN)
B1
7
Output
/RTS
10 (T2IN)
C2
7
Output
DDR2
The 200-pin SODIMM socket provides a built-in 32-bit interface to standard 1.8V DDR2 SDRAM memory modules
(PC2-5300). Lattice recommends the Kingston KVR533D284/512. However, other memories conforming to this
standard will also work. The required VREF and VTT voltages, as well as termination of each signal to VTT are provided. Performance has been verified at above the 533Mbps data rate. Write mode dynamic ODT at the memory
modules is fully supported, while read mode ODT at the controller (FPGA) is approximated with external terminations optimized for best performance. The connections between the connector pins and LatticeXP2 balls are shown
in Table 26.
Table 26. DDR2 Interface to SODIMM Socket
Description
LatticeXP2 I/O
sysIO Bank
J36
DDR2_DQ0
R21
3
5
DDR2_DQ1
R20
3
7
DDR2_DQ2
N17
3
17
DDR2_DQ3
N16
3
19
DDR2_DQ4
P19
3
4
DDR2_DQ5
R19
3
6
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LatticeXP2 Advanced
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Lattice Semiconductor
Table 26. DDR2 Interface to SODIMM Socket (Continued)
Description
LatticeXP2 I/O
sysIO Bank
J36
DDR2_DQ6
T21
3
14
DDR2_DQ7
T20
3
16
DDR2_DM0
P16
3
10
DDR2_DQS0_P
T22
3
13
DDR2_DQS0_N
U22
3
11
DDR2_DQ8
K21
3
23
DDR2_DQ9
L21
3
25
DDR2_DQ10
M19
3
35
DDR2_DQ11
M20
3
37
DDR2_DQ12
M17
3
20
DDR2_DQ13
M16
3
22
DDR2_DQ14
M21
3
36
DDR2_DQ15
N21
3
38
DDR2_DM1
P21
3
26
DDR2_DQS1_P
M22
3
31
DDR2_DQS1_N
N22
3
29
DDR2_DQ16
G21
2
43
DDR2_DQ17
F22
2
45
DDR2_DQ18
J17
2
55
DDR2_DQ19
K17
2
57
DDR2_DQ20
K18
2
44
DDR2_DQ21
L17
2
46
DDR2_DQ22
H22
2
56
DDR2_DQ23
G22
2
58
DDR2_DM2
J16
2
52
DDR2_DQS2_P
H21
2
51
DDR2_DQS2_N
J21
2
49
DDR2_DQ24
H20
2
61
DDR2_DQ25
G20
2
63
DDR2_DQ26
E19
2
73
DDR2_DQ27
F19
2
75
DDR2_DQ28
J20
2
62
DDR2_DQ29
H19
2
64
DDR2_DQ30
C22
2
74
DDR2_DQ31
B22
2
76
DDR2_DM3
H17
2
67
DDR2_DQS3_P
D22
2
70
DDR2_DQS3_N
E22
2
68
DDR2_A0
R18
3
102
DDR2_A1
R17
3
101
DDR2_A2
U21
3
100
DDR2_A3
V22
3
99
DDR2_A4
U20
3
98
DDR2_A5
V20
3
97
17
LatticeXP2 Advanced
Evaluation Board User’s Guide
Lattice Semiconductor
Table 26. DDR2 Interface to SODIMM Socket (Continued)
Description
LatticeXP2 I/O
sysIO Bank
J36
DDR2_A6
R16
3
94
DDR2_A7
T17
3
92
DDR2_A8
Y20
3
93
DDR2_A9
Y19
3
91
DDR2_A10
W22
3
105
DDR2_A11
G15
2
90
DDR2_A12
G16
2
89
DDR2_A13
F17
2
116
DDR_BA0
P20
3
107
DDR_BA1
P22
3
106
DDR_BA2
F18
2
85
DDR2_CK0_P
G17
2
30
DDR2_CK0_N
H18
2
32
DDR2_CK1_P
B21
2
164
DDR2_CK1_N
C21
2
166
DDR2_CKE0
J19
2
79
DDR2_CKE1
C20
2
80
DDR2_S0_N
J18
2
110
DDR2_S1_N
H16
2
115
DDR2_RAS_N
K16
2
108
DDR2_CAS_N
L18
2
113
DDR2_WE_N
L19
2
109
DDR2_ODT0
P18
3
114
DDR2_ODT1
N18
3
119
DDR2_SDA
AA2
0
195
DDR2_SCL
Y2
0
197
Ethernet PHY
In the upper middle portion of the board is U11, a National Semiconductor Gigabit Ethernet PHY (DP83865). The
LatticeXP2 FPGA interacts with the PHY over a Media Independent Interface (MII). The PHY is connected to an
RJ45 connector J43 on the Media Dependent Interface (MDI). The RJ45 connector J43 has built in magnetics and
spark-gap capacitor.
The PHY is available on the board in order to demonstrate the Lattice Ethernet Media Access (MAC) IP core. However, it is also possible to use the PHY to evaluate a custom MAC solution.
Refer to the schematic and the National Semiconductor DP83865 Data Sheet for detailed information about the
operation of the Ethernet PHY interface on this device. Refer to Table 27 for a description of the Ethernet PHY connections.
18
LatticeXP2 Advanced
Evaluation Board User’s Guide
Lattice Semiconductor
Table 27. 10/100/1000 Ethernet PHY Connection Summary
Description
LatticeXP2 I/O
sysIO Bank
ETH_CLK_TO_MAC
G11
1
ETH_COL
A17
1
ETH_CRS
B16
1
ETH_EGP0
(low, install R91 to pull high)
--
ETH_EGP2
G13
1
ETH_EGP4
G14
1
ETH_EGP5
D12
1
ETH_EGP6
B14
1
ETH_EGP7
A15
1
ETH_GTX_CLK
D15
1
ETH_MAC_CLK_EN
G10
1
ETH_MDC
E15
1
ETH_MDIO
E14
1
ETH_RESET_N
A16
1
ETH_RX_CLK
B15
1
ETH_RX_D0
F14
1
ETH_RX_D1
D14
1
ETH_RX_D2
C16
1
ETH_RX_D3
C17
1
ETH_RX_D4
B17
1
ETH_RX_D5
A18
1
ETH_RX_D6
F13
1
ETH_RX_D7
G12
1
ETH_RX_DV
C14
1
ETH_RX_ER
E13
1
ETH_TX_CLK
C15
1
ETH_TX_D0
D17
1
ETH_TX_D1
E18
1
ETH_TX_D2
C18
1
ETH_TX_D3
C19
1
ETH_TX_D4
A20
1
ETH_TX_D5
D19
1
ETH_TX_D6
D17
1
ETH_TX_D7
D18
1
ETH_TX_EN
A19
1
ETH_TX_ER
A21
1
PCI Connection
The 124-pin PCI connector installed at the bottom-left corner of the board is used for 32-bit PCI. With this PCI connector, PCI IP and proper LatticeXP2 FPGA design, the LatticeXP2 Advanced Evaluation board can be used in a
PCI slot on a PC motherboard. There are two sides to the PCI connector, component side (J11) and solder side
(J56). Refer to Tables 28 and 29 for a description of the PCI connections where the I/O direction is referenced to
the LatticeXP2 Advanced Evaluation Board.
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LatticeXP2 Advanced
Evaluation Board User’s Guide
Lattice Semiconductor
Table 28. PCI Connector Component Side
J11 Pin#
Signal
I/O
Description
1
12V
Vcc
12V voltage supply pin
2
TCK
-
PCI JTAG TCK signal
3
GND
Vss
4
TDO
-
JTAG TDO signal
—
5
5V
Vcc
5V voltage supply pin
—
6
5V
Vcc
5V voltage supply pin
—
7
INTB#
O
PCI INTB# signal
—
8
INTD#
O
PCI INTD# signal
—
System ground
LatticeXP2 Connection
—
—
GND
9
PRSNT1#
O
PCI PRSNT1# signal
—
10
Reserved
-
Reserved
—
11
PRSNT2#
O
PCI PRSNT2# signal
—
14
Reserved
-
Reserved
—
15
GND
Vss
16
CLK
I
17
GND
Vss
18
REQ#
O
19
+VIO
20
AD[31]
21
22
System ground
GND
PCI system clock
AB14
System ground
GND
PCI arbitration request signal
W5
Vio
VIO voltage supply pin
—
I/O
PCI address and bit 31
Y5
AD[29]
I/O
PCI address and data bit 29
GND
Vss
System ground
GND
23
AD[27]
I/O
PCI address and data bit 27
AB6
24
AD[25]
I/O
PCI address and data bit 25
25
+3.3V
Vcc
3.3V voltage supply pin
26
C/BE#[3]
I/O
PCI bus command, byte enable, bit 3
27
AD[23]
I/O
PCI address and data bit 23
28
GND
Vss
System ground
29
AD[21]
I/O
PCI address and data bit 21
30
AD[19]
I/O
PCI address and data bit 19
31
+3.3V
Vcc
3.3V voltage supply pin
32
AD[17]
I/O
PCI address and data bit 17
33
C/BE#[2]
I/O
PCI bus command, byte enable, bit 2
34
GND
Vss
System ground
35
IRDY#
I/O
PCI initiator ready signal
T10
36
+3.3V
Vcc
3.3V voltage supply pin
+3.3V
37
DEVSEL#
I/O
PCI device select
38
GND
Vss
System ground
39
LOCK#
I/O
PCI lock signal
40
PERR#
I/O
PCI parity error signal
41
+3.3V
Vcc
3.3V voltage supply pin
+3.3V
42
SERR#
I/O
PCI system error signal
V11
43
+3.3V
Vcc
3.3V voltage supply pin
+3.3V
44
C/BE#[1]
I/O
PCI bus command, byte enable, bit 1
T12
45
AD[14]
I/O
PCI address and data bit 14
T13
46
GND
Vss
System ground
GND
20
Y6
AA7
+3.3V
Y8
W4
GND
W6
U8
+3.3V
W8
V9
GND
T9
GND
V10
LatticeXP2 Advanced
Evaluation Board User’s Guide
Lattice Semiconductor
Table 28. PCI Connector Component Side (Continued)
J11 Pin#
Signal
I/O
Description
LatticeXP2 Connection
47
AD[12]
I/O
PCI address and data bit 12
AA9
48
AD[10]
I/O
PCI address and data bit 10
Y9
49
M66EN
O
PCI 66 MHz enable
—
52
AD[8]
I/O
PCI address and data bit 8
53
AD[7]
I/O
PCI address and data bit 7
AA11
54
+3.3V
Vcc
3.3V voltage supply pin
+3.3V
55
AD[5]
I/O
PCI address and data bit 5
AB12
56
AD[3]
I/O
PCI address and data bit 3
AB13
57
GND
Vss
System ground
GND
58
AD[1]
I/O
PCI address and data bit 1
Y12
59
+VIO
Vio
VIO voltage supply pin
—
60
ACK64#
I/O
PCI 64-bit acknowledge pin
—
61
+5V
Vcc
5V voltage supply pin
—
62
+5V
Vcc
5V voltage supply pin
—
AB11
Table 29. PCI Connector Solder Side
J56 Pin#
Signal
I/O
1
TRST#
I
2
+12V
3
4
Description
LatticeXP2 Connection
PCI JTAG TRST# signal
—
Vcc
12V voltage supply pin
—
TMS
I
PCI JTAG TMS signal
—
TDI
I
JTAG TDI signal
—
5
+5V
Vcc
6
INTA#
O
PCI INTA# signal
AB2
7
INTC#
O
PCI INTC# signal
—
8
+5V
Vcc
5V voltage supply pin
—
9
Reserved
—
Reserved
—
10
VIO
Vio
VIO voltage supply pin
—
Reserved
—
11
Reserved
—
14
+3.3V AUX
Vcca
15
RST#
I
16
VIO
Vio
17
GNT#
I
18
GND
Vss
5V voltage supply pin
3.3V auxiliary voltage supply
PCI system reset
VIO voltage supply pin
—
—
AB3
—
PCI arbitration grant
AB4
System ground
GND
AB5
19
PME#
—
20
AD[30]
I/O
PCI address and data bit 30
—
21
+3.3V
Vcc
3.3V voltage supply
22
AD[28]
I/O
PCI address and data bit 28
23
AD[26]
I/O
PCI address and data bit 26
24
GND
Vss
System ground
GND
25
AD[24]
I/O
PCI address and data bit 24
AB7
26
IDSEL
I
PCI interface control, ID select
AA8
27
+3.3V
Vcc
3.3V voltage supply pin
28
AD[22]
I/O
PCI address and data bit 22
V6
29
AD[20]
I/O
PCI address and data bit 20
U6
21
+3.3V
AA6
Y7
+3.3V
LatticeXP2 Advanced
Evaluation Board User’s Guide
Lattice Semiconductor
Table 29. PCI Connector Solder Side (Continued)
J56 Pin#
Signal
I/O
Description
LatticeXP2 Connection
30
GND
Vss
System ground
31
AD[18]
I/O
PCI address and data bit 18
V8
32
AD[16]
I/O
PCI address and data bit 16
U9
33
+3.3V
Vcc
3.3V voltage supply pin
34
FRAME#
I/O
PCI interface control FRAME# signal
35
GND
Vss
System ground
36
TRDY#
I/O
PCI interface control TRDY# signal
37
GND
Vss
System ground
GND
38
STOP#
I/O
PCI interface control STOP# signal
T11
39
+3.3V
Vcc
3.3V voltage supply pin
40
Reserved
—
Reserved
—
41
Reserved
—
Reserved
—
42
GND
Vss
System ground
GND
43
PAR
I/O
PCI address and data PAR signal
U10
44
AD[15]
I/O
PCI address and data bit 15
U11
45
+3.3V
Vcc
3.3V voltage supply pin
46
AD[13]
I/O
PCI address and data bit 13
AB8
47
AD[11]
I/O
PCI address and data bit 11
AB9
48
GND
Vss
System ground
GND
49
AD[9]
I/O
PCI address and data bit 9
AB10
52
C/BE#[0]
I/O
PCI bus command, byte enable, bit 0
AA10
53
+3.3V
Vcc
3.3V voltage supply pin
+3.3V
54
AD[6]
I/O
PCI address and data bit 6
Y11
55
AD[4]
I/O
PCI address and data bit 4
W11
56
GND
Vss
System ground
GND
57
AD[2]
I/O
PCI address and data bit 2
AB15
58
AD[0]
I/O
PCI address and data bit 0
AA12
59
+VIO
Vio
VIO voltage supply pin
—
60
REQ64#
I/O
PCI 64-bit request transfer pin
—
61
+5V
Vcc
5V voltage supply pin
—
62
+5V
Vcc
5V voltage supply pin
—
GND
+3.3V
W9
GND
T8
+3.3V
+3.3V
4-Input ADC
U3 is the quad ADC (Analog to Digital Converter) ADS7842 IC. The four analog inputs AIN0 to AIN3 are RC filtered
versions of the external analog signals applied at J10. The full scale values for the ADC inputs will match that of the
AREF signal described below. AIN3 is also tied to VR1 to allow user adjustment of a set DC value based on the
AREF signal described below. The connections between the ADC pins and LatticeXP2 balls are shown in Table 30.
22
LatticeXP2 Advanced
Evaluation Board User’s Guide
Lattice Semiconductor
Table 30. ADC Connections
Description
LatticeXP2 I/O
sysIO Bank
D0
H3
7
D1
H4
7
D2
G3
7
D3
G2
7
D4
H1
7
D5
H2
7
D6
G6
7
D7
H6
7
D8
H5
7
D9
J5
7
D10
J1
7
D11
J2
7
A0
F3
7
A1
E5
7
CLK
F2
7
BUSYN
F1
7
WRN
G1
7
CSN
F5
7
RDN
F4
7
4-Output DAC
U5 is the quad DAC (Digital to Analog Converter) DAC7617 IC. The four analog outputs, AOUT0 to AOUT3, are
available at connector J10. The full scale values for the DAC outputs will match that of the AREF signal described
below. The connections between the DAC pins and LatticeXP2 balls are shown in Table 31.
Table 31. DAC Connections
Description
LatticeXP2 I/O
sysIO Bank
RSTN
K1
7
LOADREGN
K2
7
LDACN
J4
7
CSN
M1
7
CLK
M2
7
SDI
L3
7
The AREF signal is used by both the ADC and DAC as the full scale voltage reference. The AREF signal can be
selected from three different sources: a low drift band gap voltage provided at U2, the power supply voltage
VCC_3.3v, or an externally applied voltage at jumper J4 pin 2. J4 allows selection of which voltage will be the
source of the AREF signal as shown in Table 32.
Table 32. DAC and ADC Full Scale Reference Selection (AREF)
J4 Jumper Position
AREF Source
ADC and DAC Usage
1-2
VCC_3.3v
2-3
Band gap reference
Full scale values track 3.3v power
open
J4 pin 2
Full scale values track low drift reference
Full scale values track external voltage
23
LatticeXP2 Advanced
Evaluation Board User’s Guide
Lattice Semiconductor
USB Download
The evaluation board has a USB download cable built in. The built-in cable consists of a USB Type-B connector
(J33), a USB microcontroller, and a MachXO device.
To use the built-in download cable, simply connect a standard USB cable from J33 to your PC (with ispVM System
software installed). The USB hub on the PC will detect the addition of the USB function making the built-in cable
available for use with Lattice’s ispVM System software. J35 must have a jumper shunted from pins 2-3 to enable
the built-in download cable.
The built-in USB cable is connected in parallel to J39 and J40. J39 and J40 are 1x10 100mil headers that are provided for use with an external Lattice download cable. A Lattice parallel port or USB download cable can be
attached to the board using J39 or J40.
Use of the built-in cable must be mutually exclusive to the use of an external download cable. When using an external download cable, the jumper on J35 must be moved to shunt pins 1 and 2. This tri-states the MachXO device,
preventing it from interfering with the external download cable.
Important Note: The board must be un-powered when connecting, disconnecting, or reconnecting the ispDOWNLOAD Cable or USB cable. Always connect an ispDOWNLOAD Cable’s GND pin (black wire), before connecting
any other JTAG pins. Failure to follow these procedures can in result in damage to the LatticeXP2 FPGA and render the board inoperable.
Default Jumper Settings
The evaluation board is shipped with default jumper positions as shown in Figure 4. Some jumper settings are
required for bitstream downloading and display functionality.
Figure 4. Default Jumper Settings
Configuring/Programming the Board
Requirements:
• PC with Lattice’s ispVM System version 17.0 (or later) programming software, installed with appropriate drivers
(USB driver for USB Cable, Windows NT/2000/XP parallel port driver for ispDOWNLOAD Cable). Note: An option
to install these drivers is included as part of the ispVM System setup.
• Standard USB cable, or any ispDOWNLOAD or Lattice USB Cable (pDS4102-DL2x, HW7265-DL3x, HW-USB2x, etc.).
24
LatticeXP2 Advanced
Evaluation Board User’s Guide
Lattice Semiconductor
The following device programming sections provide procedures for programming the on-board SPI Flash using
either a standard USB cable, or an ispDOWNLOAD cable (parallel or USB). If you would like to program the
LatticeXP2 SRAM or Flash directly instead, then the procedures are slightly different in that you will select those
rather than SPI Flash programming at Step 7, Figure 6 in the first procedure below, and much the same for the second configuration procedure.
For a complete discussion of the LatticeXP2’s configuration and programming options, refer to technical note
TN1141, LatticeXP2 sysCONFIG Usage Guide.
LatticeXP2 SRAM Configuration Using SPI Flash and a Standard USB Cable at J33
The LatticeXP2 SRAM can be configured easily via the on-board SPI Flash using the USB Download port at J33
and ispVM. The LatticeXP2 device is SRAM-based, so it must remain powered on to retain its configuration when
programming the SRAM. The on-board SPI Flash retains its programmed bitstreams when power is off, and can
quickly load programmed bitstreams into the LatticeXP2 device when power is applied.
1. Attach a ground connection from the test equipment chassis ground to the black GND terminal J51.
2. Check that the jumpers are installed as shown in Figure 4. Now move the J35 jumper from the left-side two
pins to be on the right-side two pins.
3. Connect the LatticeXP2 Evaluation Board to an external 5V supply.
4. Push the SW1 USB Download reset button located just above the MachXO device (U9). Connect a standard
USB cable from your PC’s USB connector to the USB download connector J33 on the LatticeXP2 Advanced
Evaluation Board.
5. Start the ispVM System software, then select Options > Cable and I/O Port Setup..., then check that the
Cable Type is set to USB.
Note: If you receive a Windows notification about installing a USB driver, then in ispVM System select ISPTOOLS
and INSTALL/UNINSTALL LSC USB/PARALLEL PORT DRIVER..., then select the LSC WINDOWS USB
DRIVER, and push the INSTALL button. Now push the SW1 USB Download reset button located just above the
MachXO device (U9). Windows should recognize the USB cable to the LatticeXP2 Advanced Evaluation Board.
6. Press the SCAN button located in the toolbar. The LatticeXP2 device will be automatically detected. The resulting screen will be similar to Figure 5. If offered multiple LatticeXP2 device types, select the LFXP2-17E.
Figure 5. ispVM System Interface
7. Left-click on the LFXP2-17E device line and if offered other selections, select the LFXP2-17E, and leave that
line selected. Now, in the ispVM main menu select Edit > EDIT_DEVICE and a Device Information window will
25
LatticeXP2 Advanced
Evaluation Board User’s Guide
Lattice Semiconductor
open as shown in Figure 6. Select Device Access Options and SPI Flash Programming as shown in
Figure 7.
Figure 6. Device Information Dialog
Figure 7. SPI Serial Flash Device Dialog
8. Select Browse and point to the location of the bitstream file. Note that if you have a “.JED” file output from ispLEVER, you can convert it to a “.BIT” file using ispVM and selecting the UFW (Universal File Writer) icon with
the input file being the “.JED” file from ispLEVER and the output file being a “.BIT” file.
9. Select Flash Device and in the Select Device window, change the selections as shown in Figure 8. Press OK
to close the Select Device window.
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LatticeXP2 Advanced
Evaluation Board User’s Guide
Lattice Semiconductor
Figure 8. Select Device Dialog
10. Check that the SPI Serial Flash Device window now appears as shown in Figure 9, then press OK to close
the SPI Serial Flash Device window.
Figure 9. SPI Serial Flash Device Dialog
11. Check that the Device Information window appears as shown in Figure 10, then press OK to close the Device
Information window.
27
LatticeXP2 Advanced
Evaluation Board User’s Guide
Lattice Semiconductor
Figure 10. Device Information Dialog
12. Check that the LSC ispVM System window appears as it does in Figure 11.
Figure 11. ispVM System Interface
13. To begin the download of the bitstream into the SPI Flash, press the GO menu button. You will see a small
counter display window start up and then that window will change to a Processing address window. A blue
section of that processing window will start to fill in from the left side until it reaches the right side of the window. When downloading to SPI Flash is complete, ispVM will then begin to verify the downloaded bitstream
loaded into the SPI Flash with another small processing window and blue bar moving across it.
14. Upon successful verification of the downloaded bitstream to SPI Flash, the LatticeXP2 device can then be programmed by powering down the evaluation board and re-applying power.
15. You should now see the LatticeXP2 evaluation board’s LED digit display incrementing from 0 to 9 and a to f, the
digit decimal point should be blinking, and the LEDs to the left of the digit should show the internal counter
state while the digit count is incrementing.
28
LatticeXP2 Advanced
Evaluation Board User’s Guide
Lattice Semiconductor
LatticeXP2 SRAM Configuration Using SPI Flash and a Lattice ispDOWNLOAD Cable at
J40
The LatticeXP2 SRAM can be configured easily via the on board SPI Flash using the JTAG port and ispVM. The
LatticeXP2 device is SRAM-based, so it must remain powered on to retain its configuration when programming the
SRAM. The on-board SPI Flash retains its programmed bitstreams when power is off, and can quickly load programmed bitstreams into the LatticeXP2 device when power is applied.
1. Attach a ground connection from the test equipment chassis ground to the black GND terminal J51.
2. Check that the jumpers are installed as shown in Figure 4.
3. Connect the LatticeXP2 Evaluation Board to an external 5V supply.
4. Connect the Lattice ispDOWNLOAD cable to the header at J40 labeled “XP2”.
Note: When using a 1x8 download cable, connect to the 1x10 header by justifying the alignment to pin 1 (VCC).
The board must be un-powered when connecting, disconnecting, or reconnecting the ispDOWNLOAD Cable or
USB cable. Always connect an ispDOWNLOAD Cable’s GND pin (black wire), before connecting any other
JTAG pins. Failure to follow these procedures can in result in damage to the LatticeXP2 FPGA and render the
board inoperable.
5. Start the ispVM System software, then select Options > Cable and I/O Port Setup... For the Cable Type,
select either Lattice for parallel port or USB for the type of ispDOWNLOAD cable you are using.
6. Press the SCAN button located in the toolbar. The LatticeXP2 device will be automatically detected. The resulting screen will be similar to Figure 5.
Figure 12. ispVM System Interface
7. Left-click on the LFXP2-17E device line and if offered other selections, select the LFXP2-17E and leave that
line selected. Now in the ispVM main menu select Edit > EDIT_DEVICE and a Device Information window will
open as shown in Figure 13. Select Device Access Options and SPI Flash Programming as shown in
Figure 14.
29
LatticeXP2 Advanced
Evaluation Board User’s Guide
Lattice Semiconductor
Figure 13. Device Information Dialog
Figure 14. SPI Serial Flash Device Dialog
8. Select Browse and point to the location of the bitstream file. Note that if you have a “.JED” file output from ispLEVER, you can convert it to a “.BIT” file using ispVM and selecting the UFW (Universal File Writer) icon with
the input file being the “.JED” file from ispLEVER and the output file being a “.BIT” file.
9. Select Flash Device and in the Select Device window, change the selections as shown in Figure 15. Press
OK to close the Select Device window.
30
LatticeXP2 Advanced
Evaluation Board User’s Guide
Lattice Semiconductor
Figure 15. Select Device Dialog
10. Check that the SPI Serial Flash Device window now appears as shown in Figure 16, then press OK to close
the SPI Serial Flash Device window.
Figure 16. SPI Serial Flash Device Dialog
11. Check that the Device Information window appears as shown in Figure 17, then press OK to close the Device
Information window.
31
LatticeXP2 Advanced
Evaluation Board User’s Guide
Lattice Semiconductor
Figure 17. Device Information Dialog
12. Check that the LSC ispVM System window appears as it does in Figure 18.
Figure 18. ispVM System Interface
13. To begin the download of the bitstream into the SPI Flash, press the GO menu button. You will see a small
counter display window start up and then that window will change to a Processing address window. A blue
section of that processing window will start to fill in from the left side until it reaches the right side of the window. When downloading to SPI Flash is complete, ispVM will then begin to verify the downloaded bitstream
loaded into the SPI Flash with another small processing window and blue bar moving across it.
14. Upon successful verification of the downloaded bitstream to SPI Flash, the LatticeXP2 device can then be programmed by powering down the evaluation board and re-applying power.
15. You should now see the LatticeXP2 evaluation board’s LED digit display incrementing from 0 to 9 and a to f, the
digit decimal point should be blinking, and the LEDs to the left of the digit should show the internal counter
state while the digit count is incrementing.
32
LatticeXP2 Advanced
Evaluation Board User’s Guide
Lattice Semiconductor
Ordering Information
Description
Ordering Part Number
LatticeXP2 Advanced Evaluation Board
(RoHS Compliant)
LFXP2-17E-H-EVN
LatticeXP2 Advanced Evaluation Board
(non-RoHS, Obsolete)
LFXP2-17E-H-EV
China RoHS Environment-Friendly
Use Period (EFUP)
10
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
+1-503-268-8001 (Outside North America)
e-mail: techsupport@latticesemi.com
Internet: www.latticesemi.com
Revision History
Date
Version
Change Summary
June 2007
01.0
Initial release.
March 2008
01.1
Updated LatticeXP2 Advanced Evaluation Board User’s Guide photo.
Updated Power Setup text section.
Updated USB Download text section.
May 2008
01.2
Corrected ball assignment for ETH_MDC in 10/100/1000 Ethernet PHY
Connection Summary table.
January 2009
01.3
Updated ordering information.
January 2011
01.4
Updated the DDR2 text section.
March 2011
01.5
Added “LatticeXP2 SRAM Configuration Using a Standard USB Cable
at J33” and “LatticeXP2 SRAM Configuration Using a Lattice ispDOWNLOAD Cable at J40” text sections.
© 2011 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as
listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of
their respective holders. The specifications and information herein are subject to change without notice.
33
34
A
B
C
D
5
(Sheet 6)
ADCs, DACs,
USB, RS-232,
Clock Osc
(Sheets 2, 3)
(Sheet 2)
4
1
(Sheet 5)
3
3
(Sheet 8)
Bank
8
Bank 3
Bank 2
Bank 1
(Sheets 4, 9)
(Sheet 10)
1
Lattice Semiconductor Corporation
Switches, LEDs
LCD Display
Programming, USB DL
DDR2
SDRAM
32 BIT
2
Date:
Size
A
2
Document Number
Sheet
1
1
of
14
Lattice XP2 Advanced Engineering Board 484 fpBGA
Title
(Sheet 7)
22
Ethernet PHY
Bank 4
XP2
FPGA
Bank 5
Bank 6
Bank 7
Bank 0
PCI 32 BIT
AB
A
Compact Flash,
PLL SMA I/O
4
Video I/O,
Signal SMA I/O,
RJ-45 & PS/2
(Sheet 11)
FPGA
Power
Pins
Power
(Sheet 12,13)
5
B
Rev
A
B
C
D
Lattice Semiconductor
LatticeXP2 Advanced
Evaluation Board User’s Guide
Appendix A. Schematic
Figure 19. LatticeXP2 Advanced Evaluation Board
A
B
C
VR1
AIN0
AIN1
AIN2
AIN3
0.1uF
C63
ADJ_REF
IDC12
IDC13
IDC14
IDC15
VCC_3.3V
C7
0.1uF
5
XP2_INITN
XP2_PROGRAMN
XP2_DONE
VCC_3.3V
R132
10K
C60
0.01uF
0402
0.01uF
C8
ADS7842
AIN0
AIN1
AIN2
AIN3
VREF
AGND
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DGND
U3
0.01uF
C10
28
27
26
25
24
23
22
21
20
19
18
17
16
15
L1
BEAD / 0805
VANA
VDIG
A1
A0
CLK
BUSYN
WRN
CSN
RDN
DB0
DB1
DB2
DB3
DB4
0.001uF 0.001uF 0.001uF 0.001uF
C67
C66
C65
C64
1
2
3
4
5
6
7
8
9
10
11
12
13
14
[4]
R128
10K
CFG1
10uF X7R
C5
A_3.3V
F5
F4
H3
H4
A/D_CSn
A/D_RDn
A/D_D0
A/D_D1
H5
J5
J1
J2
K1
K2
A/D_D8
A/D_D9
A/D_D10
A/D_D11
D/A_RSTn
D/A_LOADREGn
0.1uF
C3
VCCIO7
VCCIO7
VCCIO7
VCCIO7
C111
0.01uF
0402
C73
0.001uF
0402
LFXP217-fpBGA484
1
2
C11
10uF Ceramic X5R
0805
VCC_3.3V
E2
G5
J8
K4
PL24A/PCLKT7_0
PL24B/PCLKC7_0
PL23A*/SI
PL23B*/INITN
PL22A/CCLK
PL22B/SO
PL21A*/LDQS21
PL21B*
PL20A/CSSPISN
PL20B/CSSPIN
PL19A*/CFG1
PL19B*
PL18A/PROGRAMN
PL18B/DONE
PL17A*
PL17B*
PL16A
PL16B
PL15A*
PL15B*
PL14A
PL14B
PL13A*/LDQS13
PL13B*
PL12A
PL12B
PL11A*
PL11B*
PL10A
PL10B
PL9A*
PL9B*
PL8A
PL8B
PL7A*
PL7B*
PL6A
PL6B
PL5A*
PL5B*
PL4A
PL4B
C85
0.1uF
0402
BANK 7
TX_OUT1_P
TX_OUT1_N
RX_IN2_P
RX_IN2_N
TX_OUT2_P
TX_OUT2_N
RX_IN3_P
RX_IN3_N
TX_OUT3_P
TX_OUT3_N
U4
U5
R7
R6
U2
V3
Y3
W3
R3
R4
N4
P8
T5
V2
P1
R1
M6
M7
M4
M5
M3
N2
T1
U1
N5
N6
P2
P3
V1
W1
Y1
AA1
N7
P7
P4
P5
AA2
Y2
R2
T2
C81
0.001uF
0402
[11]
VCCIO_6
RX_CLKIN_P
RX_CLKIN_N
XP2_M6
XP2_M7
XP2_M3
XP2_N2
XP2_N5
XP2_N6
XP2_V1
XP2_W1
XP2_N7
XP2_P7
I2C_SDA
I2C_SCL
4
0.01uF
C4
[3]
IDC[16..19]
AOUT1
AOUT0
AOUT3
AOUT2
IDC18
IDC19
IDC16
IDC17
1K
1K
1K
1K
1
2
3
4
JP1
PS2
6
4
2
PCA9306
GND
REF1
SCL1
SDA1
U1
EN
REF2
SCL2
SDA2
DNL
R61
R63
R64
IDC9
IDC10
IDC7
IDC8
IDC5
IDC6
IDC3
IDC4
IDC1
IDC2
IDC[1..10]
DNL
DNL
DNL
DNL
DNL
RJ45_P1
RJ45_P3
RJ45_P6
RJ45_P7
0
AREF
R14
R15
DNL
RJ45_P7
RJ45_P8
PS2_DIN_D
R5
2.7K
VCC_5.0V
RJ45_P2
RJ45_P5
RJ45_P4
RJ45_P8
3
1
2
3
4
5
6
7
8
DAC7617
16
15
14
13
12
11
10
9
D/A_RSTn
D/A_LOADREGn
D/A_LDACn
D/A_CSn
D/A_CLK
D/A_SDI
measurement across CAT-5 cable
(Not an Ethernet Port)
VDD
RESETSEL
VOUTD
RSTn
VOUTC LOADREGn
LDACn
VREFL
VREFH
CSn
VOUTB
CLK
SDI
VOUTA
AGND
GND
U5
RJ45_P5
RJ45_P6
RJ45_P3
RJ45_P4
RJ45_P1
RJ45_P2
Pair#0_N(P3)
Pair#2_P(M4)
Pair#1_N(U1)
Pair#3_N(P6)
DNL
DNL
DNL
DNL
DNL
2
1
1
S
J8
S
J14
GND
GND
GND
GND
GND
GND
GND
GND
2
P(P4)
2
3
4
5
N(P5)
2
3
4
5
TX_OUT3_P
TX_OUT3_N
TX_CLKOUT_P
TX_CLKOUT_N
TX_OUT2_P
TX_OUT2_N
TX_OUT1_P
TX_OUT1_N
TX_OUT0_P
TX_OUT0_N
27
28
1
14
2
15
3
16
4
17
5
18
6
19
7
20
8
21
9
22
10
23
11
24
12
25
13
26
1
1
S
J9
S
J15
GND
GND
GND
GND
GND
GND
GND
GND
26
27
28
26
13
25
12
24
11
23
10
22
9
21
8
20
7
19
6
18
5
17
4
16
3
15
2
14
1
3M_Rx_10226-1210VE
Mounting_R
Mounting_L
DDC_Gnd_26
RxIn0RxIn0Gnd
RxIn0+
Sense
USB/DDC_Gnd
RxIn1RxIn1Gnd
RxIn1+
DDC/SDA
RxIn2RxIn2Gnd
RxIn2+
USB+
USB_Shield
USBDDC/SCL
RxClkInRxClkInGnd
RxClkIn+
USB_+5VDC
DDC_+5VDC
RxIn3RxIn3Gnd
RxIn3+
DDC_Gnd_1
R65
100
0603
R66
100
0603
R67
100
0603
R48
100
0603
RX_CLKIN_N
RX_CLKIN_P
RX_IN3_N
RX_IN3_P
RX_IN2_N
RX_IN2_P
RX_IN1_N
RX_IN1_P
Date:
Size
C
Video I/O
Document Number
1
Sheet
2
of
14
Lattice Semiconductor Corporation
Title
R46
100
0603
RX_IN0_N
RX_IN0_P
LVDS pairs
25
13
24
12
23
22
21
20
19
18
17
16
15
14
N(AA1)
2
3
4
5
11
9
8
7
6
5
4
3
2
1
P(Y1)
2
3
4
5
10
Place resistors next to FPGA
3M_Tx_10226-1210VE
Mounting_R
Mounting_L
DDC_Gnd_1
TxOut0TxOut0Gnd
TxOut0+
Sense
USB/DDC_Gnd
TxOut1TxOut1Gnd
TxOut1+
DDC/SDA
TxOut2TxOut2Gnd
TxOut2+
USB+
USB_Shield
USBDDC/SCL
TxClkOutTxClkOutGnd
TxClkOut+
USB_+5VDC
DDC_+5VDC
TxOut3TxOut3Gnd
TxOut3+
DDC_Gnd_26
J2
Video TX
Video RX
J3
1
SMA Connector AEP 9650-1113-005
High Speed Signal I/O
Diff pair
50 ohm traces
RJ-45
Connector
RJ-45 Connector for signal quality
2
4
6
8
0
IDC[1..10][3]
R49
R37
0
R50
R53
0
R29
R31
R45
R30
R40
0
0
R32
0
0
0
4 Output DAC
RJ-45
1
3
5
7
J5
0
R43
R41
R58
R42
R33
R47
R34
R59
R62
R60
Differential Pair Traces
A_3.3V
R12
R13
0
R44
0
R1
2.7K
PS2_DIN_C
0.1uF
C1
Connector
side view
5
3
1
8
7
6
5
PS/2 Mouse
C62
0.1uF
VCC_5.0V
VCC_3.3V
R2
100K
Place resistors next to FPGA
I2C_SDA [10,12] arrange them to fit on 4 pads
I2C_SCL [10,12]
Category-5 Cable
Pairing Information:
(1,2), (3,6), (4,5), (7,8)
Pair#0_P(P2)
Pair#1_P(T1)
Pair#2_N(M5)
Pair#3_P(R5)
R3
5K
TX_CLKOUT_P
TX_CLKOUT_N
RX_IN1_P
RX_IN1_N
R5
P6
TX_OUT0_P
TX_OUT0_N
AA3
Y4
T3
U3
PS2_CLK
PS2_DATA
RX_IN0_P
RX_IN0_N
V4
V5
3
T6
T7
2
C72
10uF Ceramic X5R
0805
C82
0.01uF
0402
1
VCCIO6
VCCIO6
VCCIO6
VCCIO6
PL26A*/PCLKT6_0
PL26B*/PCLKC6_0
PL27A
PL27B
PL28A*
PL28B*
PL29A
PL29B
PL30A*/LDQS30
PL30B*
PL31A
PL31B
PL32A*
PL32B*
PL33A
PL33B
PL35A*
PL35B*
PL36A
PL36B
PL37A*
PL37B*
PL38A
PL38B
PL39A*/LDQS39
PL39B*
PL40A
PL40B
PL41A*
PL41B*
PL42A
PL42B
PL43A*
PL43B*
PL44A
PL44B
PL45A*
PL45B*
PL46A
PL46B
PL47A*
PL47B*
PL48A
PL48B
PL49A/VREF1_6
PL49B/VREF2_6
R4
5K
Place smaller value caps directly under FPGA
C80
0.1uF
0402
[12]
VCC_3.3V
L3
L4
L5
L6
SI
D/A_SDI
OSC_PCLK
K6
K7
XP2_CCLK
SO
M1
M2
L1
L2
CSSPISN
CSSPIN
D/A_CSn
D/A_CLK
J3
J4
CFG1
D/A_LDACn
J6
K5
H1
H2
G6
H6
A/D_D4
A/D_D5
A/D_D6
A/D_D7
G3
G2
F1
G1
A/D_BUSYn
A/D_WRn
A/D_D2
A/D_D3
F3
F2
XP2_E4 E4
E5
D4
D3
E3
E1
C1
D1
PL3A*
PL3B*
PL2A/VREF1_7
PL2B/VREF2_7
U8A
VCC_3.3V
SMA Connector
SMA Connector
C3
B2
B1
C2
A/D_A0
A/D_CLK
IDC0
A/D_A1
ADC and DAC have an analog
voltage range of 0 to AREF
OSC_PCLK
XP2_SI
A_3.3V
VCC_3.3V
A/D_A1
A/D_A0
A/D_CLK
A/D_BUSYn
A/D_WRn
A/D_CSn
A/D_RDn
A/D_D0
A/D_D1
A/D_D2
A/D_D3
A/D_D4
[3]
[4]
[4] XP2_CCLK
[4] XP2_SO
IDC0
USB_SPD
USB_OE_N
USB4
USB5
[3]
USB_VP
USB_VM
USB_RCV
USB_SUS
USB0
USB1
RS232_TXD
RS232_RTS_N
RS232_2
RS232_3
USB2
USB3
RS232_CTS_N
RS232_RXD
RS232_0
RS232_1
[4] XP2_CSSPISN
[4] XP2_CSSPIN
R129
10K
USB[0..5]
4 Input ADC
0.1uF
A/D_D11
A/D_D10
A/D_D9
A/D_D8
A/D_D7
A/D_D6
A/D_D5
AREF
R7
R8
R9
R10
C9
[3]
100
100
100
100
XP2_INITN
XP2_PROGRAMN
XP2_DONE
[4,7]
[4,7]
[4,7]
C61
0.1uF
0402
AREF
47uF Ceramic X5R
1206
C2
[3]
D1
B320A Diodes Inc.
ADJ_REF range is
1.24v to 3.15v
PV37W
VR2
R6
32.4K 1%
33
SMA_PKG
R146
50K POT Murata PV36Y503C01
2
U2
LM385/SO
R147
10K
IDC[12..15]
2
1
2
3
HEADER 3
50K POT Murata PV36Y503C01
PV37W
AREF
VCC_5.0V
VCC_5.0V
VCC_3.3V
1
2
[13]
3
1
1
2
J4
1
2
RS232_[0..3]
1
2
7
8
9
[3]
1
2
BANK 6
1
2
SMA Connector
SMA Connector
4
1
2
D
3
1
1
2
5
11
12
35
11
12
B
Rev
A
B
C
D
Lattice Semiconductor
LatticeXP2 Advanced
Evaluation Board User’s Guide
Figure 20. Video I/O
36
A
B
C
D
IDC[0..10]
XP2_E4
XP2_N7
XP2_P7
XP2_V1
XP2_W1
XP2_N5
XP2_N6
XP2_M3
XP2_N2
XP2_M6
XP2_M7
XP2_F6
R73
R74
R76
R75
0
0
0
0
IDC0 R174
IDC1 R175
IDC2 R177
IDC3 R179
IDC4 R172
IDC5 R171
IDC6 R170
IDC7 R169
IDC8 R178
IDC9 R168
IDC10 R176
IDC11 R167
VCC_3.3V
5
16
15
14
13
12
11
10
9
VCC_3.3V
DIPSOC-8x2
Y1
DNL
R70
DNL
DNL
DNL
DNL
DNL
R20
DNL
R26
DNL
R28
DNL
R24
1
3
5
7
9
11
13
15
17
19
21
23
IDC24
J10
Place these resistors
near the IDC connector
A_IN0
A_IN1
A_IN2
A_IN3
A_OUT0
A_OUT1
A_OUT2
A_OUT3
TP_XO_K5
0
TP_XO_K4
0
TP_XO_M5
0
TP_XO_M4
0
DNL
R23
DNL
R22
DNL
R21
DNL
R27
DNL
DNL
DNL
DNL
DNL
DNL
DNL
DNL
DNL
R18
DNL
R25
DNL
R17
DNL
OSC_PCLK
OSC1(L4)
OSC_PLLCLK
OSC2(A2)
RS232_RTS_N
RS232_3
OSC_PCLK
[2]
4
RS232_TXD
RS232_2
[6]
RS232_RXD
RS232_1
OSC_PLLCLK
RS232_CTS_N
RS232_0
R79
R78
R80
R72
C100
0.1uF
0402
0
0
0
0
C98
0.1uF
0402
RX - series resistors remain 0 ohm. Resistors tied to
VCC_3.3v and GND should be 240 ohms each.
0
0
0
0
0
0
0
0
0
0
0
0
1
3
5
7
9
11
13
15
17
19
21
23
USB[0..5]
TP_XP2_E4
TP_XP2_N7
TP_XP2_P7
TP_XP2_V1
TP_XP2_W1
TP_XP2_N5
TP_XP2_N6
TP_XP2_M3
TP_XP2_N2
TP_XP2_M6
TP_XP2_M7
TP_XP2_F6
[2]
IDC24
J1
C99
0.1uF
0402
LV_RTS_N
LV_TXD
LV_RXD
LV_CTS_N
C97
0.1uF
0402
Place these resistors
near the IDC connector
R145
R144
R143
R142
R141
R140
R139
R138
R137
R136
R135
R134
TX - install series resistors of 33 ohms near the FPGA and
70 ohms near the IDC connector. Do not install resistors
tied to VCC_3.3v or GND.
DNL
[8]
DNL
For high speed signals over ribbon cable:
Place these resistors near the FPGA
DNL
2
4
6
8
10
12
14
16
18
20
22
24
XP2 Test Points
R154 R155 R161 R163 R159 R158 R157 R156 R162 R153 R160 R152
DNL
R19
[2] RS232_[0..3]
0
0
0
0
0
0
0
0
0
0
0
0
(33.33 MHz OSC Installed)
1
2
3
4
5
6
7
8
DNL
R71
R180 R181 R183 R182
DNL
R69
IDC12
IDC13
IDC14
IDC15
IDC16
IDC17
IDC18
IDC19
R148
R149
R150
R151
Place these resistors near the FPGA
IDC20
IDC21
IDC22
IDC23
DNL
R68
VCC_3.3V
Oscillator Socket
[8] XP2_F6
[2] IDC[0..10]
XO_K5
XO_K4
XO_M5
XO_M4
IDC[12..23]
VCC_3.3V
2
4
6
8
10
12
14
16
18
20
22
24
USB0
USB1
USB2
USB3
USB4
USB5
3
C101
0.1uF
0402
USB_VP
USB_VM
USB_RCV
USB_SUS
USB_SPD
USB_OE_N
16
1
3
4
5
2
6
11
10
13
8
3
4
2
7
1
9
16
13
MAX3232
TSSOP16
VCC
C1+
C1C2+
C2V+
V-
T1IN
T2IN
R1IN
R2IN
U7
GND
T1OUT
T2OUT
R1OUT
R2OUT
MAX3454EETE
VP
VM
RCV
SUS (SPND)
SPD (DSPD)
OE#
QFN16
NC (EN_Vobus#)
NC
VTRM (Vreg)
VCC_3.3V
14
11
10
6
5
8
12
R164
R165
15
14
7
12
9
6
5
4
3
2
1
1
2
3
1
2
3
HV_TXD
HV_CTS_N
1
2
3
1
2
3
HEADER 3
HEADER 3
J24
1
2
3
J23
R36
15K
2
1
VCC_5.0V
J20
D-
VBUS
1
2
3
1
2
3
HV_RXD
HV_RTS_N
RXD Selection
HEADER 3
J27
HEADER 3
J29
3
4
(Female)
RS-232
CONNECTOR DB9 Norcomp 182-009-212-161
11
[13]
1
Sheet
OSC, USB & RS-232
Document Number
3
of
14
B
Rev
Lattice Semiconductor Corporation
Date:
Size
C
Title
1
6
2
7
3
8
4
9
5
J26
Used when the FPGA is
configured as USB device.
10
USB(Type B)
USB Series-B Receptacle Molex 67068-8000
D+
GND
/RTS Selection
C68
4.7uF Ceramic X5R
0603
2
1
Wired as USB Host ->
installed Jumpers on pin 1-2 of all headers
Wired as USB Device ->
installed Jumpers on pin 2-3 of all headers
HEADER 3
J22
R35
15K
Wired as DCE (default) ->
installed Jumpers on pin 1-2 of all headers
Wired as DTE ->
installed Jumpers on pin 2-3 of all headers
TXD Selection
HEADER 3
J28
HEADER 3
J30
/CTS Selection
Used when the FPGA is
configured as USB host.
USB Series-A Receptacle Molex 67643-2910
MH2
MH1
GND
D+
DVBUS
J16
33
33
1
2
3
HEADER 3
J21
C70
1uF Ceramic X5R
0402
C69
1uF Ceramic X5R
0402
USB(Type A)
VBUS (Vusb)
D+
DGND
MAX3454EETE (or NCN2500MNR2)
NC (EN_RPU)
ENUM (VObus)
U4
[12] VCC_3.3V
1
2
ADCs, DACs, XO Test Points
15
VL (Vcc)
IDC[12..23]
1
2
[2]
4
3
2
1
1
2
2
1
2
4
3
3
5 MH1
4
6 MH2
5
A
B
C
D
Lattice Semiconductor
LatticeXP2 Advanced
Evaluation Board User’s Guide
Figure 21. OSC, LSB and RS-232
37
A
B
C
D
4
1
2
3
4
VCC
/HOLD
C
D
5
J40:
JTAG header
for XP2
J39:
JTAG header
for ispPAC
TDI
TCK
TMS
TDO
TDI
TCK
TMS
TDO
J52
TDI
TCK
TDO
TMS
XP2
FPGA
VCC
TDI
J45
ATDI
TCK
ispPAC
HVOUT
TMS
TDO
TDISEL
VCC
4
XP2_CSSPIN
XP2_SO
XP2_SI
R166 4.7K
TP4
TP6
TP3
VCC_3.3V
XP2_CCLK
C71
0.1uF
0402
VCC_3.3V
CON10
CON10
C185
0.1uF
0402 J40
JTAG header
for XP2
3
CON10
J25
[2]
[2]
[2]
[2]
C184
0.1uF
0402 J39
XP2_CSSPIN
XP2_SO
XP2_SI
XP2_CCLK
[12]
JTAG header
for ispPAC
CSSPISN is the slave chip select
For chaining XP2 and
ispPAC together:
(1) Remove the jumper on J49
and install it on J45.
(2) Connect the download
cable to J39.
J49
VCC_3.3V
R173 10K
3
CSSPIN is the master chip select
When TDISEL=0 (J49 short),
ATDI is selected.
When TDISEL=1 (J49 open),
TDI is selected.
CONFIGURATION (2): J49 open, with J45 and J52 short
J39 => for programming both XP2 and ispPAC (JTAG chained together)
J40 => not used
Power Supplies
8
7
6
5
(16Mbit)
SST25VF016B-50-4C-S2AF
/S
Q
/W
VSS
U6
SPI Serial Flash
CONFIGURATION (1): J49 short and J45 open (default setting)
J39 => for ispPAC programming only
J40 => for XP2 programming only
5
1
2
3
[12]
CFG1
R227
10K
CFG1
[2]
1
2
3
2
CFG0
R233
10K
[2,7]
[2,7]
HEADER 3
J44
XP2_DONE
XP2_INITN
XP2_TCK [9]
XP2_TMS
[9]
XP2_TCK
XP2_TMS
[12]
[12]
[12]
XP2_TDO [9]
XP2_TDI [9]
PWR_TDI
PWR_TCK
PWR_TMS
CFG0
R243
10K
TDISEL
[11]
[12]
[12]
[12]
[2]
[2]
PWR_TDO
PWR_ATDI
XP2_DONE
XP2_INITN
XP2_CSSPISN [2]
[2]
XP2_PROGRAMN
XP2_TDO
XP2_TDI
XP2_DONE
XP2_INITN
VCC_3.3V
PWR_TCK
PWR_TMS
PWR_TDO
PWR_ATDI
PWR_3.3V_10A
XP2_CCLK
XP2_DONE
XP2_INITN
VCC_3.3V
XP2_SO
XP2_SI
XP2_CSSPISN
XP2_PROGRAMN
(nc)
HEADER 3
J42
VCC_3.3V
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
9
10
XP2 SPI
Slave header
2
R242
10K
R272
4.7K
1
2
1
2
HEADER 2
J45
HEADER 2
J49
1
Programming
Document Number
Sheet
4
of
14
B
Rev
Lattice Semiconductor Corporation
Date:
Size
C
Title
1
A
B
C
D
Lattice Semiconductor
LatticeXP2 Advanced
Evaluation Board User’s Guide
Figure 22. Programming
A
B
C
PCI_3.3V
PCI_3.3V
R11
0
J18
HEADER 2
PCI_RST_N
J19
HEADER 2
J56
PCI EDGE CONN Solder Side
PCI_AD30
PCI_AD31
PCI_AD29
PCI_REQ_N
PCI_CLK
1
2
PCI_GNT_N
J11
PCI EDGE CONN Component Side
5
Maximum trace length for PCI_CLK signal is 2.5"
Maximum trace length for 32 bit interface signals is 1.5"
[12]
2
1
PCI_IDSEL
TP43
PCI_AD15
PCI_CBE1_N
PCI_SERR_N
PCI_PERR_N
PCI_DEVSEL_N
PCI_IRDY_N
PCI_AD18
PCI_AD16
PCI_AD17
PCI_CBE2_N
PCI_AD22
PCI_AD20
PCI_AD21
PCI_AD19
PCI_AD23
PCI_AD28
PCI_AD26
PCI_AD27
PCI_AD25
PCI_CBE3_N
PCI_INTA_N
PCI_INTC_N
PCI_INTB_N
PCI_INTD_N
PCI_PRSNT1_N
4
J31
CON3
[12]
PCI_VIO
C159
0.01u
R82
5K
PCI_GND
PCI_PAR
PCI_FRAME_N
PCI_STOP_N
PCI_TRDY_N
PCI_AD24
4
J34 should be placed next to C37
[12]
[12]
VCC_3.3V
VCC_3.3V
C37 must be placed within 0.25" of the PCI connector
3
3
C144
0.001uF
0402
VCC_3.3V
C88
0.001uF
0402
VCC_3.3V
PCI_VIO
C118
0.001uF
0402
C117
0.001uF
0402
C75
0.01uF
0402
C94
0.01uF
0402
C95
0.01uF
0402
PCI_CLK
PCI_AD2
PCI_AD1
C84
0.01uF
0402
TP52
PCI_AD3
PCI_AD5
C147
0.1uF
0402
C74
0.1uF
0402
AA5
R9
V7
W10
AB14
AB15
Y12
W12
AB13
AB12
AB11
AB10
AB8
AB9
PCI_AD13
PCI_AD11
PCI_AD8
PCI_AD9
T12
T13
PCI_CBE1_N
PCI_AD14
AA12
Y11
AB6
AB7
PCI_AD0
PCI_AD6
AB4
AB5
PCI_AD27
PCI_AD24
AA11
AA10
PCI_AD7
PCI_CBE0_N
PCI_GNT_N
PCI_AD30
AB2
AB3
PCI_INTA_N
PCI_RST_N
T11
U11
AA8
AA9
PCI_IDSEL
PCI_AD12
PCI_STOP_N
PCI_AD15
V11
W11
PCI_SERR_N
PCI_AD4
PCI_AD10
PCI_CBE3_N
T10
V10
Y9
Y8
PCI_AD29
PCI_AD26
PCI_IRDY_N
PCI_PERR_N
Y6
Y7
PCI_REQ_N
PCI_AD21
AA6
AA7
W5
W6
PCI_TRDY_N
PCI_DEVSEL_N
PCI_AD28
PCI_AD25
T8
T9
PCI_AD18
PCI_AD17
V9
W9
V8
W8
PCI_AD22
PCI_AD20
U9
U10
V6
U6
PCI_AD23
PCI_AD31
PCI_CBE2_N
PCI_FRAME_N
W4
Y5
PCI_AD19
PCI_AD16
PCI_PAR
U7
U8
U8B
C6
10uF Ceramic X5R
0805
VCCIO4
VCCIO4
VCCIO4
VCCIO4
PB29A/PCLKT4_0
PB29B/PCLKC4_0
PB30A
PB30B
PB31A
PB31B
PB32A
PB32B
PB33A/BDQS33
PB33B
PB34A
PB34B
PB35A
PB35B
PB36A
PB36B
PB37A
PB37B
PB38A
PB38B
PB39A
PB39B
PB40A
PB40B
PB41A
PB41B
PB42A/BDQS42
PB42B
PB43A
PB43B
PB44A/LRC_GPLLT_IN_A
PB44B/LRC_GPLLC_IN_A
C146
0.1uF
0402
2
PB46A/VREF1_4
PB46B/VREF2_4
PB45A/LRC_GPLLT_FB_A
PB45B/LRC_GPLLC_FB_A
C77
10uF Ceramic X5R
0805
BANK 5
C76
0.1uF
0402
LFXP217-fpBGA484
VCCIO5
VCCIO5
VCCIO5
VCCIO5
PB28A/PCLKT5_0
PB28B/PCLKC5_0
PB27A
PB27B
PB26A
PB26B
PB25A
PB25B
PB24A/BDQS24
PB24B
PB23A
PB23B
PB22A
PB22B
PB21A
PB21B
PB20A
PB20B
PB19A
PB19B
PB18A
PB18B
PB17A
PB17B
PB16A
PB16B
PB15A/BDQS15
PB15B
PB14A
PB14B
PB13A
PB13B
PB12A
PB12B
PB11A
PB11B
PB10A
PB10B
PB9A
PB9B
PB8A
PB8B
PB7A
PB7B
PB6A/BDQS6
PB6B
PB5A/LLC_GPLLT_FB_A
PB5B/LLC_GPLLC_FB_A
PB4A/LLC_GPLLT_IN_A
PB4B/LLC_GPLLC_IN_A
PB3A/VREF1_5
PB3B/VREF2_5
2
BANK 4
D
5
PCI_AD14
1
2
3
4
5
6
7
8
9
10
11
PCI_PRSNT2_N
PCI_AD13
PCI_AD11
PCI_AD12
PCI_AD10
TRST#
+12V
TMS
TDI
+5V_5
INTA#
INTC#
+5V_8
Reserved_9
+VIO_10
Reserved_11
1
2
3
4
5
6
7
8
9
10
11
-12V
TCK
Ground_3
TDO
+5V_5
+5V_7
INTB#
INTD#
PRSNT1#
Reserved_10
PRSNT2#
PCI_AD9
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
3.3VAUX
RST#
+VIO_16
GNT#
Ground_18
PME#
AD[30]
+3.3V_21
AD[28]
AD[26]
Ground_24
AD[24]
IDSEL
+3.3V_27
AD[22]
AD[20]
Ground_30
AD[18]
AD[16]
+3.3V_33
FRAME#
Ground_35
TRDY#
Ground_37
STOP#
+3.3V_39
Reserved_40
Reserved_41
Ground_42
PAR
AD[15]
+3.3V_45
AD[13]
AD[11]
Ground_48
AD[09]
PCI_CBE0_N
PCI_AD8
PCI_AD7
1
2
3
PCI_REQ64_N
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
PCI_AD1
Reserved_14
Ground_15
CLK
Ground_17
REQ#
+VIO_19
AD[31]
AD[29]
Ground_22
AD[27]
AD[25]
+3.3V_25
C/BE#[3]
AD[23]
Ground_28
AD[21]
AD[19]
+3.3V_31
AD[17]
C/BE#[2]
Ground_34
IRDY#
+3.3V_36
DEVSEL#
Ground_38
LOCK#
PERR#
+3.3V_41
SERR#
+3.3V_43
C/BE#[1]
AD[14]
Ground_46
AD[12]
AD[10]
M66EN
PCI_M66EN
PCI_AD6
PCI_AD4
PCI_AD5
PCI_AD3
1
2
PCI_AD2
PCI_AD0
52
53
54
55
56
57
58
59
60
61
62
C/BE#[0]
+3.3V_53
AD[06]
AD[04]
Ground_56
AD[02]
AD[00]
+VIO_59
REQ64#
+5V_61
+5V_62
PCI_ACK64_N
52
53
54
55
56
57
58
59
60
61
62
AD[08]
AD[07]
+3.3V_54
AD[05]
AD[03]
Ground_57
AD[01]
+VIO_59
ACK64#
+5V_61
+5V_62
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
38
2
AA18
R14
V16
W13
AB16
AB17
Y14
AA13
V12
U12
AB18
AB19
AA14
AA15
T14
T15
V13
U13
LED6
LED7
LED4
LED5
LED2
LED3
LED0
LED1
LCD[0..10]
[7]
LED[0..7] [7]
[7]
SEVEN_SEG[0..7]
LCD[0..10]
SWITCH[0..9] [7]
PCI
Document Number
1
Sheet
5
of
14
B
Rev
Lattice Semiconductor Corporation
Date:
Size
C
Title
SEVEN_SEG6
SEVEN_SEG1
SEVEN_SEG7
SEVEN_SEG2
SEVEN_SEG4
SEVEN_SEG3
SEVEN_SEG0
SEVEN_SEG5
LCD1
LCD0
AA16
AA17
LCD3
LCD2
AB20
AA20
LCD9
LCD8
Y22
Y21
W14
V14
SWITCH0
LCD10
W15
V15
LCD7
LCD6
SWITCH2
SWITCH1
T16
U16
LCD5
LCD4
SWITCH4
SWITCH3
Y16
Y15
AA22
AA21
SWITCH6
SWITCH5
Y17
Y18
U14
U15
PB3
PB2
PB1
SWITCH9
SWITCH8
SWITCH7
W17
W18
1
A
B
C
D
Lattice Semiconductor
LatticeXP2 Advanced
Evaluation Board User’s Guide
Figure 23. PCI
A
B
C
[12]
CF_D03
CF_D04
CF_D05
CF_D06
CF_D07
CF_CE1
CF_A10
CF_OE
CF_A09
CF_A08
CF_A07
CF_A06
CF_A05
CF_A04
CF_A03
CF_A02
CF_A01
CF_A00
CF_D00
CF_D01
CF_D02
CF_WP
CF_CD2
CF0
CF1
CF2
CF3
CF4
CF5
CF6
CF7
CF8
CF9
CF10
CF11
CF12
CF13
CF14
CF15
CF16
CF17
CF18
CF19
CF20
CF21
CF22
CF[0..45]
5
VCC_3.3V
Hirose MI20-50PD-SF
GND
CD1
D03
D11
D04
D12
D05
D13
D06
D14
D07
D15
CE1/CE1/CS0 CE2/CE2/CS1
A10
VS1
OE/OE/ATASEL
IORD
A09
IOWR
A08
WE
A07
READY/IREQ/INTRQ
VCC
VCC
A06
CSEL
A05
VS2
A04
RESET
WAIT/WAIT/IORDY
A03
A02 INPACK/INPACK/DMARQ
A01
REG/REG/DMACK
A00
BVD2/SPKR/DASP
D00
BVD1/STSCHG/PDIAG
D01
D08
D02
D09
WP/IOIS16/IOCS16
D10
CD2
GND
PC Card Memory Mode/
PC Card I/O Mode/
True IDE Mode
CF[0..45]
C183
0.1uF
0402
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Compact Flash Connector
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
J38
C180
0.1uF
0402
CF23
CF24
CF25
CF26
CF27
CF28
CF29
CF30
CF31
CF32
CF33
CF34
R215
100K
R213
47K
R209
47K
R216
47K
R214
47K
CF_CSEL
CF_VS2
CF_RESET
CF_WAIT
CF_INPACK
CF_REG
CF_BVD2
CF_BVD1
CF_D08
CF_D09
CF_D10
CF35
CF36
CF37
CF38
CF39
CF40
CF41
CF42
CF43
CF44
CF45
4
CF_BVD1
CF42
Ultra DMA is not supported
Traces from the ECP2 to
the CF connector must
be less than 6 inches
Compact Flash
Connector
CF_BVD2
CF41
CF_CD1
CF_D11
CF_D12
CF_D13
CF_D14
CF_D15
CF_CE2
CF_VS1
CF_IORD
CF_IOWR
CF_WE
CF_READY
CF_VS1
CF30
R210
100K
CF_VS2
CF36
R218
100K
CF_INPACK
CF39
R217
100K
CF_WP
CF21
R211
100K
CF_READY
CF34
R212
100K
CF_WAIT
CF38
VCC_3.3V
CF_CD1
CF23
D
4
CF_CD2
CF22
5
CF[0..45]
[8]
[3]OSC_PLLCLK
PLL_FB_P
PLL_FB_N
[8]
[8]
DNL
DNL
R39
0
R57
0
R56
R55
0
R52
0
R38
R54
R51
1
2
DNL
DNL
3
2
2
1
1
S
J6
S
J12
GND
GND
GND
GND
GND
GND
GND
GND
2
3
4
5
N(B3)
2
3
4
5
P(A2)
1
1
S
J7
S
J13
SMA Connector
1
GND
GND
GND
GND
GND
GND
GND
GND
P(F7)
2
3
4
5
N(G7)
2
3
4
5
Date:
Size
C
Title
Document Number
1
Sheet
6
of
Compact Flash, PLL SMA I/O
14
Lattice Semiconductor Corporation
SMA Connector AEP 9650-1113-005
The pad of Pin 2 is directly
put on the trace of the differential
pair to minimize the trace stub.
No extra trace stub is created on
the differential pair trace.
Diff pair
50 ohm traces
HEADER 2
J17
Place resistors next to FPGA
arrange them to fit on 4 pads
PLL_IN_P
PLL_IN_N
[8]
[8]
Installing jumper on pin 1 and 2
will connect the on-board
oscillator clock output to the PLL
clock input on the XP2 ball A2.
CF[0..45]
3
SMA Connector
SMA Connector
39
SMA Connector
B
Rev
A
B
C
D
Lattice Semiconductor
LatticeXP2 Advanced
Evaluation Board User’s Guide
Figure 24. CompactFlash, PLL, SMA I/O
A
B
C
D
[12] VCC_3.3V
(V13)
(AA17)
220
220
220
220
220
220
220
5
R285
220
LED(AB17)
R284
LED(AB16)
R283
LED(AA13)
R282
LED(Y14)
R278
LED(U12)
R277
LED(V12)
R276
LED(AB19)
R275
LED(AB18)
(U13)
D(Pin 8)
(AA14)
G(Pin 11)
(AA16)
A(Pin 1)
B(Pin 13)
C(Pin 10)
F(Pin 2)
E(Pin 7)
SSEG_B
R294
LED 0603 Green
D25
LED 0603 Green
D24
LED 0603 Green
D22
LED 0603 Green
D21
LED 0603 Green
D20
LED 0603 Green
ON
VCC_3.3V
PROGRAMN
(E12)
(W18)
PB1
(W17)
PB2
GSRN
4
[5]
(U7)
PB3
0402
0402
0402
0402
0402
0402
0402
0402
D19
LED0
LED1
LED2
LED3
LED4
LED5
LED6
LED7
LED[0..7]
470
470
470
470
470
470
SSEG_E
SSEG_D
SSEG_DP
SSEG_C
SSEG_G
R289
R298
R297
R296
R295
470
470
SSEG_A
R287
SSEG_F
R288
VCC_3.3V
LED 0603 Green
D18
LED 0603 Green
D17
(T14)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Seven Segment Display Fairchild MAN4710A
738milX386mil
cathode A
cathode F
annode1
NC1
NC2
NC3
cathode E
cathode D
cathode DP
cathode C
cathode G
NC4
cathode B
annode2
DP(Pin 9)
(T15)
(AA15)
U20
7 Segment Display
VCC_3.3V
VCC_3.3V
[5]
SW DIP-8 CTS 194-8MST
SW8
VCC_5.0V
R247
10K
R245
10K
C219
0.01uF
0402
C214
0.01uF
0402
VCC_5.0V
7
9
1
14
3
12
5
10
7
9
1
14
3
12
5
10
VDD
GND
Aout
Bout
Cout
Dout
Eout
Fout
MC14490
GND
Aout
Bout
Cout
Dout
Eout
Fout
Debouncer
OSCin
OSCout
Ain
Bin
Cin
Din
Ein
Fin
U18
MC14490
OSCin
OSCout
Ain
Bin
Cin
Din
Ein
Fin
8
15
2
13
4
11
6
16
8
15
2
13
4
11
6
16
VCC_3.3V
VDD
Debouncer
U15
Contrast
Adjustment
VR4
100 POT Murata PV36Y101C01
PV37W
ANODE
2
VCC_3.3V
PB1
GSRN
PB3
PB2
SWITCH0
SWITCH1
SWITCH2
SWITCH3
SWITCH4
SWITCH5
SWITCH6
SWITCH7
SWITCH9
SWITCH8
VR5
20K POT Murata PV36Y203C01
PV37W
2
LCD0
LCD_R/W
LCD1
LCD_DB0
LCD2
LCD_DB2
LCD3
LCD_DB4
LCD4
LCD_DB6
3
2
1
3
5
7
9
11
13
15
17
[8]
Gate
SOT-23
XP2_PROGRAMN
GSRN
VCC_3.3V
Source
Drain
VCC_3.3V
VCC_3.3V
R293
470
470
470
2
4
6
8
10
12
14
16
18
Gate
R292
R286
CATHODE
VDD
RS
E
DB1
DB3
DB5
DB7
CATHODE
LCD_Connector
ANODE
VSS
VO
R/W
DB0
DB2
DB4
DB6
ANODE
J55
SWITCH[0..9] [5]
LUMEX or Equiv. use pins 3-18
OPTREX 51505 or Equiv. use pins 1-16
LCD Connector
2
1
2
3
4
5
6
7
8
(W15) (U16) (T16) (Y15) (Y16) (Y18) (Y17) (W18)
R248
10K
R246
10K
Backlight
Adjustment
[13]
DIP_SWITCH0
DIP_SWITCH1
DIP_SWITCH2
DIP_SWITCH3
DIP_SWITCH4
DIP_SWITCH5
DIP_SWITCH6
DIP_SWITCH7
R299 R300 R301 R302 R303 R304 R305 R306
10K
10K
10K
10K
10K
10K
10K
10K
SW4
SW PUSHBUTTON Panasonic EVQP2H02B
SW5
SW PUSHBUTTON Panasonic EVQP2H02B
SW6
SW PUSHBUTTON Panasonic EVQP2H02B
SW7
SW PUSHBUTTON Panasonic EVQP2H02B
SW10
SW PUSHBUTTON Panasonic EVQP2H02B
SEVEN_SEG1
SEVEN_SEG4
SEVEN_SEG3
SEVEN_SEG7
SEVEN_SEG2
SEVEN_SEG6
SEVEN_SEG0
SEVEN_SEG5
SEVEN_SEG[0..7]
3
1
3
4
1
3
5
16
15
14
13
12
11
10
9
40
1
2
3
4
5
6
7
8
[4]
LCD[0..10]
TP108
XP2_INITN
XP2_INITN
XP2_DONE
[2]
[2]
[2]
XP2_PROGRAMN
LCD[0..10]
[5]
1
Sheet
7
of
14
Switches, LEDs, LCD Display
Document Number
B
Rev
Lattice Semiconductor Corporation
Date:
Size
C
TP109
XP2_DONE
On when INITN low
D29
LED 0603 Red
INIT
Source
Q10
BSS138LT1
SOT-23
Drain
On when DONE high
TP107
XP2_PROGRAMN
D28
LED 0603 Green
DONE
Title
LCD5
LCD6
LCD7
LCD8
LCD9
LCD10
C57
0.1uF
0402
On when PROGRAMN low
D27
LED 0603 Yellow
PROGRAM
LCD_RS
LCD_E
LCD_DB1
LCD_DB3
LCD_DB5
LCD_DB7
1
A
B
C
D
Lattice Semiconductor
LatticeXP2 Advanced
Evaluation Board User’s Guide
Figure 25. Switches, LEDs, LCD Display
A
B
C
D
E14
E15
ETH_MDIO
ETH_MDC
VCC_2.5V
[13]
[7]
GSRN
TP89
VCCIO1
VCCIO1
VCCIO1
VCCIO1
0.01uF
0402
C155
B18
D13
E16
H14
0.001uF
0402
C109
LFXP217-fpBGA484
PT29A/PCLKT1_0
PT29B/PCLKC1_0
PT30A
PT30B
PT31A
PT31B
PT32A
PT32B
PT33A/TDQS33
PT33B
PT34A
PT34B
PT35A
PT35B
PT36A
PT36B
PT37A
PT37B
PT38A
PT38B
PT39A
PT39B
PT40A
PT40B
PT41A
PT41B
PT42A/TDQS42
PT42B
PT43A
PT43B
0.01uF
0402
C189
0.01uF
0402
C194
BANK 1
0.1uF
0402
C193
0.1uF
0402
C201
0.01uF
0402
C191
5
CF35
CF34
CF33
CF32
CF31
CF30
CF29
CF28
H7
J7
A5
A6
B6
B7
D8
C8
CF13
CF12
D11
C11
B11
A12
B5
D10
E7
H9
B13
A14
F11
F12
E11
C12
B12
A13
0.01uF
0402
C204
4
R244
ETH_MDIO
ETH_MDC
VCC_2.5V
ETH_CRS
ETH_COL
PHY_TX_D[0..7]
[13]
C205
10pF
0402
[9]
[9]
[9]
[9]
[9]
ETH_TMS
ETH_TDO
ETH_TDI
ETH_TRST
ETH_TCK
Place xtal
close to
G-PHY
25MHz
HC-49/U
Y3
R220
324
0402
LED 0603 Green
D2
R219
2K
0402
ETH_TMS
ETH_TDO
ETH_TDI
ETH_TRST
ETH_TCK
C206
10pF
0402
R113
1M
0402
23
27
28
31
32
24
87
86
3
R221
324
0402
0.01uF
1 0402
C210 22uF
2
1
SizeB
DP83865
TM0
TMS
TDO
TDI
TRST
TCK
CLOCK_OUT
CLOCK_IN
MDIO
MDC
GTX_CLK / RGMII_TXC
CRS / RGMII_SEL1
COL
TX_CLK / RGMII_SEL0
TX_EN / RGMII_TX_CTL
TX_ER
TXD0 / RGMII_TXD0
TXD1 / RGMII_TXD1
TXD2 / RGMII_TXD2
TXD3 / RGMII_TXD3
TXD4
TXD5
TXD6
TXD7
RX_CLK
RX_DV / RGMII_RXC
RX_ER / RGMII_RX_CTL
RXD0 / RGMII_RXD0
RXD1 / RGMII_RXD1
RXD2 / RGMII_RXD2
RXD3 / RGMII_RXD3
RXD4
RXD5
RXD6
RXD7
U11
D3
LED 0603 Green
R222
2K
0402
VCC_2.5V
ETH_EGP[0..7]
X1
X0
79
PHY_GTX_CLK
80
81
40
39
PHY_CRS
PHY_COL
R97
R95
2K
60
33
33
62
61
PHY_TX_ER
PHY_TX_CLK
76
75
72
71
68
67
66
65
PHY_TX_D0
PHY_TX_D1
PHY_TX_D2
PHY_TX_D3
PHY_TX_D4
PHY_TX_D5
PHY_TX_D6
PHY_TX_D7
PHY_TX_EN
57
PHY_RX_CLK
R109 33
Place termination
resistors TX_D0-7,
TX_ER, TX_EN,
GTX_CLK as close to
FPGA as possible
using 50 ohm
impedence traces.
41
PHY_RX_ER
PHY_RX_DV
R96
33
R99
33
R107 33
ETH_RX_ER
ETH_RX_DV
ETH_RX_CLK
44
56
55
52
51
50
47
46
45
PHY_RX_D0
PHY_RX_D1
PHY_RX_D2
PHY_RX_D3
PHY_RX_D4
PHY_RX_D5
PHY_RX_D6
PHY_RX_D7
33
33
33
33
33
33
33
33
R108
R105
R103
R104
R101
R102
R100
R98
ETH_RX_D0
ETH_RX_D1
ETH_RX_D2
ETH_RX_D3
ETH_RX_D4
ETH_RX_D5
ETH_RX_D6
ETH_RX_D7
Place termination
resistors RX_D0-7,
RX_ER, RX_DV, RX_CLK,
TX_CLK, CRS, COL
as close to the
G-PHY as possible
using 50 ohm impedence
traces.
Place R close to CLOCK_IN
PHY_TX_EN
PHY_TX_D0
PHY_TX_D1
PHY_TX_D2
PHY_TX_D3
PHY_TX_D4
PHY_TX_D5
PHY_TX_D6
PHY_TX_D7
PHY_TX_ER
C156
10uF Ceramic X5R
0805
Bypass for BG_VDD
0.1uF
0402
C138
2
[11]
[6]
10uF Ceramic X5R
0805
C86
VCCIO_0
CF[0..45]
C79
0.01uF
0402
1
[13]
C197
10uF Ceramic X5R
0805
VCC_1.8V
C107
0.001uF
0402
CF1
CF0
CF3
CF2
CF5
CF4
CF7
CF6
CF9
CF8
CF11
CF10
CF15
CF14
A10
A11
G8
G9
CF17
CF16
CF19
CF18
CF21
CF20
CF23
CF22
CF25
CF24
B9
B10
F10
E10
D9
C9
A8
A9
A7
B8
ETH_TX_D0
ETH_TX_D1
ETH_TX_D2
ETH_TX_D3
ETH_TX_D4
ETH_TX_D5
ETH_TX_D6
ETH_TX_D7
ETH_TX_ER
VCC_2.5V
CF37
CF36
C6
C7
CF27
CF26
ETH_TX_CLK
ETH_GTX_CLK R185 33
CF39
CF38
A3
A4
E9
F9
ETH_TX_EN R189 33
CF41
CF40
33
33
33
33
33
33
33
33
33
CF43
CF42
C5
C4
R184
R190
R187
R191
R194
R195
R186
R188
R196
CF45
CF44
F8
E8
[6]
[6]
D6
D5
PLL_FB_P
PLL_FB_N
PLL_FB_P
PLL_FB_N
[6]
[6]
[3]
PLL_IN_P
PLL_IN_N
PLL_IN_P
PLL_IN_N
TP50
XP2_F6
A2
B3
XP2_F6
XP2_E6
F7
G7
F6
E6
C110
0.01uF
0402
VCC_2.5V
0.01uF
0402
C202
C108
0.1uF
0402
VCCIO0
VCCIO0
VCCIO0
VCCIO0
PT28A/PCLKT0_0
PT28B/PCLKC0_0
PT27A
PT27B
PT26A
PT26B
PT25A
PT25B
PT24A/TDQS24
PT24B
PT23A
PT23B
PT22A
PT22B
PT21A
PT21B
PT20A
PT20B
PT19A
PT19B
PT18A
PT18B
PT17A
PT17B
PT16A
PT16B
PT15A/TDQS15
PT15B
PT14A
PT14B
PT13A
PT13B
PT12A
PT12B
PT11A
PT11B
PT10A
PT10B
PT9A
PT9B
PT8A
PT8B
PT7A
PT7B
PT6A/TDQS6
PT6B
PT5A/ULC_GPLLT_FB_A
PT5B/ULC_GPLLC_FB_A
PT4A/ULC_GPLLT_IN_A
PT4B/ULC_GPLLC_IN_A
PT3A/VREF1_0
PT3B/VREF2_0
Bypass for IO_VDD pins. Bypass every other
IO_VDD pair, alternating 0.1 and 0.01uF caps.
0.1uF
0402
C203
0.1uF
0402
C190
Place caps close to GPHY
0.001uF
0402
C140
PT44A/URC_GPLLT_IN_A
PT44B/URC_GPLLC_IN_A
PT45A/URC_GPLLT_FB_A
PT45B/URC_GPLLC_FB_A
Decoupling Caps
0.1uF
0402
C139
GSRN
B14
A15
G10
G11
ETH_MAC_CLK_EN
ETH_CLK_TO_MAC
ETH_EGP6
ETH_EGP7
B15
A16
ETH_RX_CLK
ETH_RESET_N
E12
D12
B16
A17
ETH_CRS
ETH_COL
ETH_EGP5
E13
C14
ETH_RX_ER
ETH_RX_DV
ETH_RX_D6 F13
ETH_RX_D7 G12
ETH_RX_D4 B17
ETH_RX_D5 A18
ETH_RX_D2 C16
ETH_RX_D3 C17
ETH_RX_D0 F14
ETH_RX_D1 D14
ETH_EGP2 G13
ETH_EGP4 G14
C15
D15
ETH_TX_CLK
ETH_GTX_CLK
D17
D18
ETH_TX_D6
ETH_TX_D7
A21
A19
A20
D19
ETH_TX_ER
ETH_TX_EN
C18
C19
ETH_TX_D4
ETH_TX_D5
PT46A/VREF1_1
PT46B/VREF2_1
BANK 0
U8D
PHY_GTX_CLK
ETH_TX_D2
ETH_TX_D3
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
E17
E18
ETH_EGP6
1
2
C28
2
C209 22uF
2
1
SizeB
Place these close to G-PHY
1
R106
R112
Giga Phyter
10/100/1000
Giga Phyter V
RX_VDD
10
0402
18
0402
2
VCC_1.8V
C195
0.01uF
0402
MDIA_BUS7
J43
LED2+
LED2LED1+
LED1-
SHLD1
SHLD2
7
8
4
5
3
6
1
2
19
20
16
15
14
13
RJ-45 Belfuse 0826-1A1T-23
MDID+
MDDCT
MDID-
MDIC+
MDCCT
MDIC-
MDIB+
MDBCT
MDIB-
MDIA+
MDACT
MDIA-
2
85
33
13
14
17
18
95
94
89
88
1
2
3
6
7
8
9
10
ETH_EGP4
ETH_EGP5
ETH_EGP6
ETH_EGP7
ETH_EGP2
ETH_EGP0
R92
2K
0402
R225 470
1
2
0402
R238 470
1
2
0402
ETH_MAC_CLK_EN
C199
0.01uF
0402
0402
R240
2K
0402
C200
0.01uF
0402
2K
C192
1uF Ceramic X5R
0402
ETH_RESET_N
0402
R226
2K
VCC_2.5V
R239
C187
0.01uF
0402
VCC_2.5V
(Do not
populate)
ETH_MAC_CLK_EN
PULL_UP
R91
2K
0402
R94
2K
0402
R93
324
0402
Date:
Size
C
R235
324
0402
ETH_EGP4
ETH_EGP7
R234
2K
0402
VCC_2.5V
MDI IO traces must be 50 ohm impedence.
Ethernet
Document Number
1
Sheet
8
of
14
B
Rev
Lattice Semiconductor Corporation
ETH_EGP7
MH1 and MH2
are 0.100"
diameter plated
through holes
Title
MH1
MH2
MHOLE_1 MHOLE_1
0.100_PTH 0.100_PTH
Ethernet RJ45 Connector
C186
0.01uF
0402
MDIA_BUS6
MDIA_BUS7
MDIA_BUS4
MDIA_BUS5
MDIA_BUS2
MDIA_BUS3
MDIA_BUS0
MDIA_BUS1
ETH_EGP[0..7]
(Do not
populate)
ETH_EGP0
VCC_2.5V
Place caps close to RJ45 jack TX1
R241
33
ETH_RESET_N
1
Place 9.76K resistor as close
to G-PHY as possible
Giga Phyter address = 01h
102
34
84
R237 9.76K 1%
1
2
0402
MDI_P4
MDI_N4
MDI_P3
MDI_N3
120
121
126
127
MDI_P2
MDI_N2
MDI_P1
MDI_N1
114
115
108
109
ETH_CLK_TO_MAC
CLK_TO_MAC
RESET_N
GP0 (PHYAD0 / DUPLEX_LED)
GP1 (PHYAD1)
GP2 (PHYAD2)
GP3 (PHYAD3)
GP4 (PHYAD4)
GP5 (MULTI_EN)
GP6 (MDIX_EN)
GP7 (MAC_CLK_EN)
Place 49 ohm termination resistors as
close as possible to G-PHY.
The associated 0.01uF capacitor should
be placed close to the 49 ohm resistors.
VCC_2.5V
8
7
9
MDIA_BUS6
MDIA_BUS5
MDIA_BUS3
MDIA_BUS1
3
1
2
R224
49_9
0402
R231
49_9
0402
MDIA_BUS4
R223
49_9
0402
R230
49_9
0402
4
6
5
R229
49_9
0402
R232
49_9
0402
MDIA_BUS2
R228
49_9
0402
R236
49_9
0402
11
12
10
C188
0.01uF
0402
MDIA_BUS[0..7]
VDD_SEL
REF_SEL
BG_REF
MDID_P
MDID_N
MDIC_P
MDIC_N
MDIB_P
MDIB_N
MDIA_P
MDIA_N
VCC_2.5V
EGP0 (NC_MODE)
EGP1
EGP2 (Interrupt)
EGP3 (TX_TCLK)
EGP4 (SPEED0 / ACT_LED)
EGP5 (SPEED1 / LINK10)
EGP6 (DUPLEX_EN / LINK100)
EGP7 (AN_EN / LINK1000)
(Hard Reset)
ETH_EGP[0..7]
MDIA_BUS0
2
ETH_TX_D0
ETH_TX_D1
ETH_EGP5
101
BG_VDD
98
PGM_VDD0
11
19
25
35
48
63
73
92
CORE_VDD1
CORE_VDD2
CORE_VDD3
CORE_VDD4
CORE_VDD5
CORE_VDD6
CORE_VDD7
CORE_VDD8
100
103
105
111
117
123
VDD0
RX_DVDD0
VDD1
VDD2
VDD3
VDD4
96
VDD25_0
4
15
21
29
37
42
53
58
69
83
77
90
IO_VDD1
IO_VDD2
IO_VDD3
IO_VDD4
IO_VDD5
IO_VDD6
IO_VDD7
IO_VDD8
IO_VDD9
O_VDD0
IO_VDD10
IO_VDD11
RJ45
3
1
4
1
2
1
2
5
1
2
1
2
1
2
2
1
1
2
1
2
2
1
1
2
1
2
2
1
1
99
97
5
12
20
16
26
22
36
30
38
49
43
54
64
59
74
70
82
78
93
91
104
106
107
110
112
113
116
118
119
122
124
125
128
1
1
2
1
2
1
2
1
2
1
2
2
1
2
1
VSS0
PGM_VSS0
IO_VSS1
CORE_VSS1
CORE_VSS2
IO_VSS2
CORE_VSS3
IO_VSS3
CORE_VSS4
IO_VSS4
IO_VSS5
CORE_VSS5
IO_VSS6
IO_VSS7
CORE_VSS6
IO_VSS8
CORE_VSS7
IO_VSS9
O_VSS0
IO_VSS10
CORE_VSS8
IO_VSS11
RX_DVSS0
VSS1
CD_VSS1
CD_VSS2
VSS2
CD2_VSS1
CD2_VSS2
VSS3
CD3_VSS1
CD3_VSS2
VSS4
CD4_VSS1
CD4_VSS2
2
1
2
2
1
2
1
2
41
1
A
B
C
D
Lattice Semiconductor
LatticeXP2 Advanced
Evaluation Board User’s Guide
Figure 26. Ethernet
A
B
C
D
2
D-
CON10
J32
15
16
C102
C103
0.01uF
0.1uF
0.1uF
C126
C105
1
2
3
4
5
6
7
8
9
10
PWR_3.3V_10A
XO_TDO
XO_TDI
5
R77
4.7K
XO_TCK
XO_TMS
CTL2/FLAGC
CTL1/FLAGB
CTL0/FLAGA
RDY0/SLRD
RDY1/SLWR
SCL
SDA
WAKEUP
RESET#
RESERVED
DPLUS
DMINUS
XTALOUT
XTALIN
USB+
FX2
PA7/FLAGD/SLCS#
PA6/PKTEND
PA5/FIFOADR1
PA4/FIFOADR0
PA3/WU2
PA2/SLOE
PA1/INT1#
PA0/INT0#
PD7/FD15
PD6/FD14
PD5/FD13
PD4/FD12
PD3/FD11
PD2/FD10
PD1/FD9
PD0/FD8
PB7/FD7
PB6/FD6
PB5/FD5
PB4/FD4
PB3/FD3
PB2/FD2
PB1/FD1
PB0/FD0
IFCLK/T0OUT
CLKOUT/T1OUT
R192
10K
TP40
TP32
TP37
TP33
TP38
A6
A7
B8
C8
B6
B7
C6
C7
A5
A4
E7
E6
B4
B5
D6
D5
C4
C5
D3
D4
A2
A3
B2
B3
XO_GPIO10
XO_GPIO11
XO_GPIO12
SW1
USB_PA7
USB_PA6
USB_PA5
USB_PA4
USB_PA3
USB_PA2
USB_PA1
USB_PA0
USB_PD7
USB_PD6
USB_PD5
USB_PD4
USB_PD3
USB_PD2
USB_PD1
USB_PD0
USB_PB7
USB_PB6
USB_PB5
USB_PB4
USB_PB3
USB_PB2
USB_PB1
USB_PB0
TP17
TP18
TP24
TP23
TP15
TP13
TP16
TP14
E3
E2
USB_PA5
USB_PA4
D2
D1
USB_PA1
USB_PA0
G3
H3
USB_PD3
USB_PD2
I/Os in Bank 0
for XO1200
Pin name sequence
PT(640,1200,2280)
PT4E/PT6C/PT8C
PT4F/PT6D/PT8D
PT4C/PT6A/PT7C
PT4D/PT6B/PT7D
PT4A/PT5E/PT7A
PT4B/PT5F/PT7B
PT3C/PT5C/PT6A
PT3D/PT5D/PT6B
PT3E/PT5A/PT6C
PT3F/PT5B/PT6D
NC/PT4C/PT6E
NC/PT4D/PT6F
PT3A/PT3E/PT5C
PT3B/PT3F/PT5D
PT2C/PT3C/PT5A
PT2D/PT3D/PT5B
PT2E/PT4A/PT4A
PT2F/PT4B/PT4B
NC/PT2C/PT3C
NC/PT2D/PT3D
PL11A/PL13C/PL16C
PL11B/PL13D/PL16D
PL8A/PL13A/PL16A/LV_T
PL8B/PL13B/PL16B/LV_C
PL9C/PL12C/PL15C
PL9D/PL12D/PL15D
PL10A/PL12A/PL15A/LV_T
PL10B/PL12B/PL15B/LV_C
TSALL/PL8C/PL11C/PL14C
PL8D/PL11D/PL14D
PL10C/PL14C/PL17C
PL10D/PL14D/PL17D
USB_CLKO
I/Os in Bank 1
for XO2280
NC/PT11C/PT16C
NC/PT11D/PT16D
NC/PT11A/PT16A
NC/PT11B/PT16B
PT9E/PT10E/PT15C
PT9F/PT10F/PT15D
NC/PT10C/PT15A
NC/PT10D/PT15B
PT9C/PT10A/PT14C
PT9D/PT10B/PT14D
PT7E/PT9E/PT14A
PT7F/PT9F/PT14B
PT8A/PT9C/PT13C
PT8B/PT9D/PT13D
PT7A/PT9A/PT12C
PT7B/PT9B/PT12D
PT7C/PT8E/PT12A
PT7D/PT8F/PT12B
PT5C/PT8C/PT11A
PT5D/PT8D/PT11B
PT8C/PT8A/PT10E
PT8D/PT8B/PT10F
PT6C/PT7E/PT10C
PT6D/PT7F/PT10D
PT6A/PT7C/PT10A
PT6B/PT7D/PT10B/CLK1
TP60
TP72
0
0
0
0
ETH_TDO_p R84
ETH_TCK_p R203
ETH_TMS_p R207
ETH_TDI_p R89
A13
A14
D11
D12
0
0
0
0
XP2_TDO_p R86
XP2_TCK_p R87
XP2_TMS_p R85
XP2_TDI_p R204
B14
C14
A15
B15
B13
C13
E10
E11
0
0
TP45
TP47
XO_GPIO19
XO_GPIO20
B11
B12
PWR_ATDI_p R88
ETH_TRST_p R205
TP46
TP53
XO_GPIO17
XO_GPIO18
A11
A12
C11
C12
TP39
TP42
D9
D10
XO_GPIO15
XO_GPIO16
0
0
PWR_TMS_pR202
PWR_TDI_p R81
B9
B10
0
0
XO_GPIO13
XO_GPIO14
PWR_TDO_p R83
PWR_TCK_p R206
TP44
TP41
R208
R90
TP55
TP49
C9
C10
XP2_DONE_p
XP2_INITN_p
TP61
TP2
A10
A9
E8
E9
TP59
TP1
Pin name sequence
PL(640,1200,2280)
0603
0603
0603
0603
0603
0603
0603
0603
0603
0603
0603
0603
0603
0603
0
0
IDC[20..23]
IDC22
IDC23
DNI
DNI
DNI
C165 C17
XP2_TMS
XP2_TDI
XP2_TDO
XP2_TCK
C168
DNI
DNI
C21
ETH_TMS
ETH_TDI
ETH_TDO
ETH_TCK
PWR_ATDI
ETH_TRST
DNI
C154 C163
PWR_TMS
PWR_TDI
DNI
DNI
DNI
3
DNI
C19 C18
DNI
C164 C16
DNI
C167 C15
DNI
DNI
PWR_TDO
PWR_TCK
C169
C22
XP2_DONE
XP2_INITN
IDC[20..23]
USB_PB7
USB_PB6
USB_PB5
USB_PB4
XO_K5
XO_K4
IDC20
IDC21
[12]
DNI
[2]
[2]
ETH_TMS[8]
ETH_TDI [8]
ETH_TDO[8]
ETH_TCK[8]
XP2_TMS [4]
XP2_TDI [4]
PWR_3.3V_10A
PR8A/PR10C/PR13C
PR8B/PR10D/PR13D
TP57
TP62
TP63
TP58
TP56
TP11
TP9
TP5
TP10
TP12
TP7
TP8
C171
0.01uF
0402
XO_TDI
XO_TDO
XO_TMS
XO_TCK
XO_GPIO34
XO_GPIO35
XO_GPIO32
XO_GPIO33
XO_GPIO30
XO_GPIO31
XO_GPIO28
XO_GPIO29
XO_GPIO26
XO_GPIO27
XO_GPIO24
XO_GPIO25
C170
0.01uF
0402
C130
0.001uF
0402
L11
M11
N13
N12
M12
M13
N15
N14
L12
L13
L14
M14
M16
N16
L15
M15
K16
L16
J13
K13
J14
K14
J15
K15
J12
K12
N7
M6
P4
R3
R7
R8
M7
M8
T8
T7
R6
T6
T5
T4
P5
P6
R4
R5
T2
T3
N5
N6
P2
P3
C172
0.01uF
0402
2
H16
J16
C133
0.001uF
0402
NC/PR16A/PR20A
NC/PR16B/PR20B
NC/PR15A/PR18A/LV_T
NC/PR15B/PR18B/LV_C
NC/PR14C/PR17C
NC/PR14D/PR17D
PR11C/PR14A/PR17A/LV_T
PR11D/PR14B/PR17B/LV_C
PR11A/PR13C/PR16C
PR11B/PR13D/PR16D
PR10A/PR13A/PR16A/LV_T
PR10B/PR13B/PR16B/LV_C
PR10C/PR12C/PR15C
PR10D/PR12D/PR15D
PR9C/PR12A/PR15A/LV_T
PR9D/PR12B/PR15B/LV_C
PR9A/PR11C/PR14C
PR9B/PR11D/PR14D
PR8C/PR11A/PR14A/LV_T
PR8D/PR11B/PR14B/LV_C
C134
0.1uF
0402
Pin name sequence
PR(640,1200,2280)
PR6A/PR8C/PR10C
PR6B/PR8D/PR10D
PR5C/PR8A/PR10A/LV_T
PR5D/PR8B/PR10B/LV_C
PR6C/PR7C/PR9C
PR6D/PR7D/PR9D
PR4C/PR7A/PR9A/LV_T
PR4D/PR7B/PR9B/LV_C
PR5A/PR6C/PR7C
PR5B/PR6D/PR7D
PR4A/PR6A/PR7A/LV_T
PR4B/PR6B/PR7B/LV_C
PR3A/PR5C/PR6C
PR3B/PR5D/PR6D
PR2C/PR5A/PR6A/LV_T
PR2D/PR5B/PR6B/LV_C
PR2A/PR4C/PR5C
PR2B/PR4D/PR5D
PR3C/PR4A/PR5A/LV_T
PR3D/PR4B/PR5B/LV_C
PR7C/PR10A/PR13A/LV_T
PR7D/PR10B/PR13B/LV_C
NC/PR9C/PR11C
NC/PR9D/PR11D
NC/PR3A/PR4A/LV_T
NC/PR3B/PR4B/LV_C
NC/PR3C/PR4C
NC/PR3D/PR4D
PR7A/PR9A/PR11A/LV_T
PR7B/PR9B/PR11B/LV_C
VCCIO3
MachXO_2280_fpBGA256
NC/PR2A/PR3A/LV_T
NC/PR2B/PR3B/LV_C
VCCIO2
U10D
PWR_ATDI [12]
ETH_TRST [8]
[12]
[12]
[12]
[12]
XP2_TDO [4]
XP2_TCK [4]
DNI
C166 C20
PWR_TMS
PWR_TDI
PWR_TDO
PWR_TCK
XP2_DONE
XP2_INITN
PWR_3.3V_10A
G15
H15
G14
H14
H12
H13
G12
G13
F16
G16
USB_PB1
USB_PB0
USB_PB3
USB_PB2
E15
F15
D16
E16
C15
D15
USB_CTL1
USB_CTL0
USB_WAKEUP
USB_CTL2
USB_RDY1
B16
C16
F13
F12
USB_SCL
USB_SDA
TP51
XO Tristate
E13
E12
D14
D13
E14
F14
N4
N3
0603
0603
J35
HEADER 3
1
2
3
USB_RDY0
XO_M5
XO_M4
TP48
3
PWR_3.3V_10A
USB_IFCLK
USB_PA7
USB_PA6
M5
M4
L5
L4
K5
K4
R1
R2
J4
J5
M2
N2
L3
M3
N1
P1
L1
M1
K2
L2
J1
K1
J3
K3
H2
J2
TP71
[3]
PL11C/PL16A/PL19A
PL11D/PL16B/PL19B
PL5C/PL8C/PL10C NC/PL15A/PL18A/LV_T/PLL0_T_IN
PL5D/PL8D/PL10DNC/PL15B/PL18B/LV_C/PLL0_C_IN
NC/PL8A/PL9A/LV_T
NC/PL8B/PL9B/LV_C
PL4C/PL7C/PL8C NC/PL14A/PL17A/LV_T/PLL0_T_FB
PL4D/PL7D/PL8D NC/PL14B/PL17B/LV_C/PLL0_C_FB
NC/PL7A/PL8A/LV_T
NC/PL7B/PL8B/LV_C
PL4A/PL6C/PL7C
PL4B/PL6D/PL7D
PL9A/PL10C/PL12C
PL9B/PL10D/PL12D
PL7A/PL11A/PL13A/LV_T
PL7B/PL11B/PL13B/LV_C
PL5A/PL6A/PL7A/LV_T
PL5B/PL6B/PL7B/GSR/LV_C
PL3C/PL5C/PL6C
PL3D/PL5D/PL6D
PL2A/PL5A/PL5A/LV_T
PL2B/PL5B/PL5B/LV_C
NC/PL4C/PL4C
NC/PL4D/PL4D
PL2C/PL4A/PL4A/LV_T
PL2D/PL4B/PL4B/LV_C
PT9A/PT7A/PT9C
PT9B/PT7B/PT9D
4
PL7C/PL9C/PL11C
PL7D/PL9D/PL11D
PL3A/PL3C/PL3C/PLL1T_IN PL6C/PL10A/PL12A/LV_T
PL3B/PL3D/PL3D/PLL1C_INPL6D/PL10B/PL12B/LV_C
NC/PL3A/PL3A/LV_T
NC/PL3B/PL3B/LV_C
PL6A/PL9A/PL11A/LV_T
PL6B/PL9B/PL11B/LV_C
VCCIO6
MachXO_2280_fpBGA256
NC/PL2A/PL2A/PLL1T_FB
NC/PL2B/PL2B/PLL1C_FB
VCCIO7
U10B
VCCIO1
MachXO_2280_fpBGA256
PT2A/PT3A/PT3A
PT2B/PT3B/PT3B
NC/PT2A/PT2C
NC/PT2B/PT2D
VCCIO0
U10A
G1
H1
H4
H5
G4
G5
USB_PD5
USB_PD4
USB_PD1
USB_PD0
E1
F1
USB_PD6
USB_PD7
F2
USB_RESET G2
B1
C1
USB_PA3
USB_PA2
C3
C2
F3
F4
F5
F6
E4
E5
USB_CLKO
SW PUSHBUTTON Panasonic EVQP2H02B
47
46
45
44
43
42
41
40
3
2
1
56
55
54
53
52
32
31
30
29
28
27
26
25
XO_GPIO8
XO_GPIO9
XO_GPIO6
XO_GPIO7
XO_GPIO4
XO_GPIO5
TP28
TP31
TP30
TP27
XO_GPIO2
XO_GPIO3
0.1uF
C151
USB_RESET
TP26
TP25
0.01uF
C125
0.1uF
C150
USB(Type B)
0.1uF
0.1uF
3
4
38
37
36
8
9
22
23
BEAD / 0805
USB Series-B Receptacle Molex 67068-8000
D+
GND
USB_CTL2
USB_CTL1
USB_CTL0
USB_RDY0
USB_RDY1
USB_SCL
USB_SDA
C127
0.1uF
C104
20
5
11
12
USB_WAKEUP 51
USB_RESET
49
21
USB+
USB-
24MHz
USB_IFCLK
USB_CLKO
JTAG header
for MachXO
AVCC_3.3V
J33
4
3
VBUS
PWR_3.3V_10A
USB-
1
VCC
OUT
OSC4/SM
EN
GND
Y2
U9
6
18
24
34
39
50
10
14
VCC
VCC
VCC
VCC
VCC
VCC
AVCC
AVCC
CY7C68013A-56SSOP
GND
GND
GND
GND
GND
GND
AGND
AGND
4
7
19
33
35
48
13
17
4
2
I/Os in Bank 5
for XO1200
Pin name sequence
PB(640,1200,2280)
TDI
TDO
TMS
TCK
PB4E/PB6C/PB8C
PB4F/PB6D/PB8D
NC/PB6A/PB7C
NC/PB6B/PB7D
PB4C/PB5C/PB6A
PB4D/PB5D/PB6B
PB4A/PB5A/PB5A
PB4B/PB5B/PB5B
PB3C/PB4C/PB4C
PB3D/PB4D/PB4D
PB3A/PB4A/PB4A
PB3B/PB4B/PB4B
PB2C/PB3C/PB3C
PB2D/PB3D/PB3D
PB2A/PB3A/PB3A
PB2B/PB3B/PB3B
NC/PB2C/PB2C
NC/PB2D/PB2D
NC/PB11C/PB16C
NC/PB11D/PB16D
SLEEPN
PB9F/PB10F/PB15D
NC/PB11A/PB16A
NC/PB11B/PB16B
PB9C/PB10C/PB15A
PB9D/PB10D/PB15B
PB9A/PB10A/PB14C
PB9B/PB10B/PB14D
PB8C/PB9E/PB14A
PB8D/PB9F/PB14B
PB8A/PB9C/PB13C
PB8B/PB9D/PB13D
PB7E/PB9A/PB13A
PB7F/PB9B/PB13B
NC/PB8E/PB12C
NC/PB8F/PB12D
PB7C/PB8C/PB12A
PB7D/PB8D/PB12B
PB6C/PB8A/PB11C
PB6D/PB8B/PB11D
PB6A/PB7E/PB10A
PB6B/PB7F/PB10B/CLK3
PB7A/PB7C/PB10C
PB7B/PB7D/PB10D
I/Os in Bank 4
for XO2280
VCCJ on VCCIO5
XO_640 common VCCIO
VCCIO6_0
VCCIO6_1
VCCAUX_0
VCCAUX_1
VCCIO7_0
VCCIO7_1
XO_640 common VCCIO
VCCIO5_0
VCCIO5_1
XO_640 common VCCIO
XO_640 common VCCIO
VCCIO4_0
VCCIO4_1
VCCIO3_0
VCCIO3_1
VCCIO2_0
VCCIO2_1
VCCIO1_0
VCCIO1_1
VCCIO0_0
VCCIO0_1
PWR_3.3V_10A
A8
T9
G6
H6
J6
K6
L7
L8
L9
L10
J11
K11
G11
H11
C135
0.01uF
0402
PB5A/PB7A/PB10E
PB5B/PB7B/PB10F/CLK2
VCCIO4
MachXO_2280_fpBGA256
NC/PB2A/PB2A
NC/PB2B/PB2B
VCCIO5
U10C
C131
0.001uF
0402
C132
0.001uF
0402
F7
F8
F9
F10
1
MachXO_2280_fpBGA256
VCC_3
VCC_2
VCC_1
VCC_0
GND_0
GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
GND_9
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
K7
G7
K10
G10
A16
T16
F11
H10
J10
G9
H9
J9
K9
G8
H8
J8
K8
H7
J7
L6
A1
T1
C129
0.01uF
0402
C106
0.01uF
0402
C152
0.01uF
0402
C137
0.1uF
0402
C128
0.1uF
0402
C136
0.1uF
0402
C153
0.1uF
0402
R11
R12
P13
P14
4.7K
PWR_3.3V_10A
Date:
Size
C
Title
1
USB Download
Document Number
Sheet
9
Lattice Semiconductor Corporation
P15
P16
R193
TP76
TP77
XO_GPIO46
XO_GPIO47
T14
T15
TP54
XO_GPIO44
XO_GPIO45
R15
R16
TP74
TP70
TP73
TP75
XO_GPIO42
XO_GPIO43
T13
T12
TP67
TP69
R13
R14
P11
P12
XO_GPIO40
XO_GPIO41
TP66
TP68
XO_GPIO38
XO_GPIO39
T10
T11
N10
N11
TP64
TP65
XO_GPIO36
XO_GPIO37
R9
R10
M10
M9
P9
P10
N8
N9
of
Mach XO needs to be a "D" device
PWR_3.3V_10A
U10E
1
2
AVCC_3.3V
1
2
L7
1
2
1
2
1
2
1
2
4.7K
4
3
1
2
PWR_3.3V_10A
5 MH1
1
2
R201
6 MH2
1
2
PWR_3.3V_10A
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
5
PT5A/PT6E/PT9A
PT5B/PT6F/PT9B/CLK0
D8
D7
PB5C/PB6E/PB9A
PB5D/PB6F/PB9B
42
P7
P8
JB
14
B
Rev
A
B
C
D
Lattice Semiconductor
LatticeXP2 Advanced
Evaluation Board User’s Guide
Figure 27. USB Download
A
B
C
D
VREF
SODIMM_ODT1
SODIMM_CAS_N
SODIMM_S1_N
SODIMM_A10
SODIMM_BA0
SODIMM_WE_N
SODIMM_A5
SODIMM_A3
SODIMM_A1
SODIMM_A12
SODIMM_A9
SODIMM_A8
SODIMM_BA2
SODIMM_CKE0
SODIMM_DQ26
SODIMM_DQ27
SODIMM_DM3
SODIMM_DQ24
SODIMM_DQ25
SODIMM_DQ18
SODIMM_DQ19
SODIMM_DQS2_N
SODIMM_DQS2_P
SODIMM_DQ16
SODIMM_DQ17
???????
SODIMM_DQ10
SODIMM_DQ11
SODIMM_DQS1_N
SODIMM_DQS1_P
SODIMM_DQ8
SODIMM_DQ9
SODIMM_DQ2
SODIMM_DQ3
SODIMM_DQS0_N
SODIMM_DQS0_P
SODIMM_DQ0
SODIMM_DQ1
[13] VTT
[2] I2C_SDA
[2] I2C_SCL
[12] VCC_3.3V
at
modules
[13]
VTT
C179
0.1uF
0402
I2C_SDA
I2C_SCL
VCC_3.3V
SODIMM_DQ58
SODIMM_DQ59
SODIMM_DM7
SODIMM_DQ56
SODIMM_DQ57
SODIMM_DQ50
SODIMM_DQ51
VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
5
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
n.c.
VSS
DQ26
DQ27
VSS
CKE0
VDD
n.c.
NC/BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
S1#
VDD
ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
n.c.
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
VSS
DQ20
DQ21
VSS
n.c.
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
CKE1
VDD
n.c.
n.c.
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
n.c.
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SA0
SA1
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
VCC_1.8V
C158
0.01uF
0402
C175
0.1uF
0402
C161
0.1uF
0402
C174
0.01uF
0402
C162
0.1uF
0402
1.8V DDR2 200-pin SO-DIMM Standard
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
J36B
1.8V DDR2 200-pin SO-DIMM Standard
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
J36A
at modules
VCC_1.8V
C157
0.01uF
0402
SODIMM_DQS6_N
SODIMM_DQS6_P
SODIMM_DQ48
SODIMM_DQ49
SODIMM_DQ42
SODIMM_DQ43
SODIMM_DM5
SODIMM_DQ40
SODIMM_DQ41
SODIMM_DQ34
SODIMM_DQ35
SODIMM_DQ32
SODIMM_DQ33
C25
47uF Ceramic X5R
SODIMM_DQS4_N
1206
SODIMM_DQS4_P
C145
0.1uF
0402
1
2
1
2
1
2
C176
0.01uF
0402
C177
0.1uF
0402
EEPROM SA = 000
SODIMM_DQ62
SODIMM_DQ63
SODIMM_DQS7_N
SODIMM_DQS7_P
SODIMM_DQ60
SODIMM_DQ61
SODIMM_DQ54
SODIMM_DQ55
SODIMM_DM6
SODIMM_CK1_P
SODIMM_CK1_N
SODIMM_DQ52
SODIMM_DQ53
SODIMM_DQ46
SODIMM_DQ47
SODIMM_DQS5_N
SODIMM_DQS5_P
SODIMM_DQ44
SODIMM_DQ45
SODIMM_DQ38
SODIMM_DQ39
SODIMM_DM4
SODIMM_DQ36
SODIMM_DQ37
SODIMM_ODT0
SODIMM_A13
SODIMM_BA1
SODIMM_RAS_N
SODIMM_S0_N
SODIMM_A4
SODIMM_A2
SODIMM_A0
SODIMM_A11
SODIMM_A7
SODIMM_A6
SODIMM_CKE1
SODIMM_DQ30
SODIMM_DQ31
SODIMM_DQS3_N
SODIMM_DQS3_P
SODIMM_DQ28
SODIMM_DQ29
SODIMM_DQ22
SODIMM_DQ23
SODIMM_DM2
SODIMM_DQ20
SODIMM_DQ21
SODIMM_DQ14
SODIMM_DQ15
SODIMM_CK0_P
SODIMM_CK0_N
SODIMM_DM1
SODIMM_DQ12
SODIMM_DQ13
SODIMM_DQ6
SODIMM_DQ7
SODIMM_DM0
SODIMM_DQ4
SODIMM_DQ5
C122
0.1uF
0402
4
P16
P17
DDR2_DM0
C142
0.001uF
0402
K21
L21
DDR2_DQ8
DDR2_DQ9
VCC_1.8V
On die
terms
SODIMM
EEPROM
External
SSTL_18
terms
4
C141
0.001uF
0402
C148
0.01uF
0402
LFXP217-fpBGA484
VCCIO3
VCCIO3
VCCIO3
VCCIO3
TDI
PR26A*/PCLKT3_0
PR26B*/PCLKC3_0
PR27A
PR27B
PR28A*
PR28B*
PR29A
PR29B
PR30A*/RDQS30
PR30B*
PR31A
PR31B
PR32A*
PR32B*
PR33A
PR33B
PR35A*
PR35B*
PR36A
PR36B
PR37A*
PR37B*
PR38A
PR38B
PR39A*/RDQS39
PR39B*
PR40A
PR40B
PR41A*
PR41B*
PR42A
PR42B
PR43A*
PR43B*
PR44A
PR44B
PR45A*
PR45B*
PR46A
PR46B
PR47A*
PR47B*
PR48A/VREF1_3
PR48B/VREF2_3
PR12A
PR12B
PR11A*
PR11B*
PR10A
PR10B
PR9A*
PR9B*
PR8A
PR8B
PR7A*
PR7B*
PR6A
PR6B
PR5A*
PR5B*
PR4A
PR4B
PR3A*
PR3B*
PR2A/VREF1_2
PR2B/VREF2_2
C124
0.1uF
0402
VCCIO2
VCCIO2
VCCIO2
VCCIO2
PR24A/PCLKT2_0
PR24B/PCLKC2_0
PR23A*
PR23B*
PR22A
PR22B
PR21A*/RDQS21
PR21B*
PR20A
PR20B
PR19A*
PR19B*
PR18A
PR18B
PR17A*
PR17B*
PR16A
PR16B
PR15A*
PR15B*
PR14A
PR14B
PR13A*/RDQS13
PR13B*
C96
0.01uF
0402
BANK 2
BANK 3
DDR2_CK1_P
DDR2_CK1_N
DDR2_DQ24
DDR2_DQ25
DDR2_DQ26
DDR2_DQ27
DDR2_DQ28
DDR2_DQ29
DDR2_DQ31
DDR2_DQ30
B21
C21
H20
G20
E19
F19
J20
H19
B22
C22
C149
0.1uF
0402
E21
G18
J15
K19
J22
K22
L19
L18
J16
K16
H21
J21
G22
H22
K18
L17
J17
K17
G21
F22
F20
F21
J19
J18
H16
H17
3
All the 741X083 devices
and discrete resistors on
this page with 33 ohm
value tied to FPGA, should
be placed physically near
the FPGA.
DMx: data mask
DQx: data
DQSx: data strobe diff pair
CKx: clock x diff pair
SCL: clock
SDA: data
SA: address
VDDSPD: power
ODTx: On die termination enable
CAS: Column select
RAS: Row select
WE: Write enable
CKEx: clock enable
Sx: SODIMM select
BAx: bank address
Ax: address
TP87
TP85
TP86
C14
10uF Ceramic X5R
0805
VCC_1.8V
DDR2_WE_N
DDR2_CAS_N
DDR2_DM2
DDR2_RAS_N
DDR2_DQS2_P
DDR2_DQS2_N
DDR2_DQ23
DDR2_DQ22
DDR2_DQ20
DDR2_DQ21
DDR2_DQ18
DDR2_DQ19
DDR2_DQ16
DDR2_DQ17
VCC_1.8V
DDR2_CKE0
DDR2_S0_N
DDR2_S1_N
DDR2_DM3
DDR2_DQS3_P
DDR2_DQS3_N
DDR2_CK0_P
DDR2_CK0_N
D22
E22
DDR2_A11
DDR2_A12
G15
G16
G17
H18
DDR2_CKE1
B20
C20
VCC_1.8V
DDR2_BA2
DDR2_A13
E20
D20
VCC_1.8V
F15
F16
3
F18
F17
Smaller value caps should be placed
directly under the ECP2 device. Larger
value caps can be placed further out.
N19
P15
T18
V21
L20
M19
M20
[9]
XP2_TDI
M17
M16
DDR2_DQ14
DDR2_DQ15
DDR2_DQ12
DDR2_DQ13
M22
N22
M21
N21
DDR2_DQS1_P
DDR2_DQS1_N
DDR2_DQ10
DDR2_DQ11
P18
N18
P22
R22
DDR2_BA1
DDR2_ODT0
DDR2_ODT1
R21
R20
DDR2_DQ0
DDR2_DQ1
P21
P20
N17
N16
DDR2_DQ2
DDR2_DQ3
DDR2_DM1
DDR2_BA0
P19
R19
DDR2_DQ4
DDR2_DQ5
VCC_1.8V
T21
T20
DDR2_DQ6
DDR2_DQ7
T22
U22
R18
R17
DDR2_A0
DDR2_A1
DDR2_DQS0_P
DDR2_DQS0_N
U21
V22
DDR2_A2
DDR2_A3
U20
V20
R16
T17
DDR2_A6
DDR2_A7
DDR2_A4
DDR2_A5
Y20
Y19
W22
W20
W19
V19
V17
V18
VREF
U8C
DDR2_A8
DDR2_A9
VCC_1.8V
VCC_1.8V
C181
0.1uF
0402
1
2
[13]
DDR2_A10
VREF
1
2
TP88
5
1
2
VCC_1.8V
1
2
1
2
SODIMM_DQ12
SODIMM_DQ8
SODIMM_DQ9
SODIMM_DQ10
SODIMM_DQ11
SODIMM_DQ14
SODIMM_DQ15
SODIMM_DQ13
SODIMM_DM1
SODIMM_DQS1_N
SODIMM_DQS1_P
SODIMM_DQ0
SODIMM_DQ1
SODIMM_DQ4
SODIMM_DQ5
SODIMM_DM0
SODIMM_DQS0_N
SODIMM_DQS0_P
SODIMM_DQ6
SODIMM_DQ7
SODIMM_DQ2
SODIMM_DQ3
SODIMM_DQ18
SODIMM_DQ22
SODIMM_DQ23
SODIMM_DQ19
SODIMM_DQ21
SODIMM_DM2
SODIMM_DQS2_N
SODIMM_DQS2_P
SODIMM_DQ20
SODIMM_DQ16
SODIMM_DQ17
33
33
RN14
1
2
3
4
RN17
1
2
3
4
33
RN13
1
2
3
4
SODIMM_CK1_N
SODIMM_CK1_P
SODIMM_CK0_N
SODIMM_CK0_P
TP78
TP83
TP81
R198 0402
33
R197 0402
33
R200 0402
33
R199 0402
DDR2_CK1_N
DDR2_CK1_P
DDR2_CK0_N
DDR2_CK0_P
RN8
1
2
3
4
RN10
1
2
3
4
RN22
RN23
RN21
33
33
33
33
RN12
1
2
3
4
[#]
33
RN15
1
2
3
4
RN27
RN24
RN25
[#]
33
RN16
1
2
3
4
RN28
RN26
RN29
SODIMM_DQ30
SODIMM_DQ31
SODIMM_DQ26
SODIMM_DQ27
33
33
RN20
1
2
3
4
SODIMM_DQ24
SODIMM_DQ28
SODIMM_DQ29
TP82
33
RN18
1
2
3
4
[#]
33
RN19
1
2
3
4
RN31
RN32
RN30
RN11
1
2
3
4
SODIMM_DQS3_N
SODIMM_DQS3_P
SODIMM_DQ25
SODIMM_DM3
100
100
100
VTT
100
100
100
VTT
100
100
100
VTT
100
100
100
VTT
2
TP84
TP80
Date:
Size
C
Title
VTT
22
RN9
1
2
3
4
DDR2_ODT1
DDR2_A13
DDR2_ODT0
741X083
DDR2_WE_N
8
DDR2_RAS_N
7
DDR2_BA0
6
5
RN1
1
2
3
4
22
1
Sheet
10
DDR2 SDRAM SO-DIMM
Document Number
of
14
All the 741X083 devices
on this page with 22 ohm
value tied to FPGA, should
be placed physically near
the FPGA.
741X083 22
8
7
6
5
RN2
1
2
3
4
DDR2_A8
DDR2_A7
DDR2_A9
DDR2_A11
741X083
DDR2_A0
8
DDR2_A2
7
DDR2_A3
6
5
RN7
1
2
3
4
22
33 741X083
RN33
VTT
741X083 22
8
7
6
5
RN4
1
2
3
4
DDR2_S1_N
DDR2_CAS_N
DDR2_S0_N
741X083
DDR2_BA1
8
DDR2_A10
7
DDR2_A1
6
5
741X083
DDR2_A12
8
DDR2_BA2
7
DDR2_CKE1
6
DDR2_CKE0
5
741X083
DDR2_A4
8
DDR2_A5
7
DDR2_A6
6
5
[13]
RN3
1
2
3
4
22
33 741X083
RN39
VTT
741X083 22
8
7
6
5
RN5
1
2
3
4
33 741X083
RN37
VTT
22
RN6
1
2
3
4
33 741X083
RN40
VTT
1
Lattice Semiconductor Corporation
SODIMM_ODT1
SODIMM_A13
SODIMM_ODT0
SODIMM_WE_N
SODIMM_RAS_N
SODIMM_BA0
33 741X083
RN38
SODIMM_A8
SODIMM_A7
SODIMM_A9
SODIMM_A11
SODIMM_A0
SODIMM_A2
SODIMM_A3
33 741X083
RN34
SODIMM_S1_N
SODIMM_CAS_N
SODIMM_S0_N
SODIMM_BA1
SODIMM_A10
SODIMM_A1
33 741X083
RN35
SODIMM_A12
SODIMM_BA2
SODIMM_CKE1
SODIMM_CKE0
SODIMM_A4
SODIMM_A5
SODIMM_A6
33 741X083
RN36
C160
220uF
SizeD
(Left end of VTT island)
All the 741X083 devices
on this page with 33 ohm
value tied to VTT, should
be placed near the DDR2
SODIMM socket.
741X083
DDR2_DQ30
8
DDR2_DQ31
7
DDR2_DQ26
6
DDR2_DQ27
5
741X083
8
DDR2_DQ24
7
DDR2_DQ28
6
DDR2_DQ29
5
741X083
DDR2_DQS3_N
8
DDR2_DQS3_P
7
DDR2_DQ25
6
DDR2_DM3
5
741X083
741X083
741X083
741X083
DDR2_DQ18
8
DDR2_DQ22
7
DDR2_DQ23
6
DDR2_DQ19
5
741X083
DDR2_DQ21
8
DDR2_DM2
7
DDR2_DQS2_N
6
DDR2_DQS2_P
5
741X083
8
DDR2_DQ20
7
DDR2_DQ16
6
DDR2_DQ17
5
741X083
741X083
741X083
741X083
8
DDR2_DQ12
7
DDR2_DQ8
6
DDR2_DQ9
5
741X083
DDR2_DQ10
8
DDR2_DQ11
7
DDR2_DQ14
6
DDR2_DQ15
5
741X083
DDR2_DQ13
8
DDR2_DM1
7
DDR2_DQS1_N
6
DDR2_DQS1_P
5
741X083
741X083
741X083
741X083
DDR2_DQ0
8
DDR2_DQ1
7
DDR2_DQ4
6
DDR2_DQ5
5
741X083
8
DDR2_DM0
7
DDR2_DQS0_N
6
DDR2_DQS0_P
5
TP79
All the 741X083
devices on this
page with 100 ohm
value tied to VTT
should be placed
near the FPGA.
741X083
DDR2_DQ6
8
DDR2_DQ7
7
DDR2_DQ2
6
DDR2_DQ3
5
741X083
741X083
741X083
2
1
2
C182
0.01uF
0402
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
3
4
8
7
6
5
1
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
2
1
2
3
4
8
7
6
5
1
2
3
4
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
1
2
3
4
8
7
6
5
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
43
8
7
6
5
B
Rev
A
B
C
D
Lattice Semiconductor
LatticeXP2 Advanced
Evaluation Board User’s Guide
Figure 28. DDR2 SDRAM SO-DIMM
A
B
C
CFG0
5
VCC_1.2V
[4,9] XP2_TDO
[4,9] XP2_TCK
[4,9] XP2_TMS
TP29
[4]
H15
VCC_3.3V
C89
0.001uF
0402
C87
0.001uF
0402
TP20
TP21
TP34
TP19
TP22
TP35
TP36
VCC_3.3V
or -40 device
or -40 device
or -40 device
or -40 device
or -40 device
C116
0.001uF
0402
C91
0.01uF
0402
C93
0.1uF
0402
LFXP217-fpBGA484
-30
NC
-30
NC
-30
-30
-30
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCJ
TDO
TCK
TMS
TOE
CFG0
U8E
C114
0.001uF
0402
AB21
H8
R15
R8
U19
U17
U18
H11
H12
L15
L8
M15
M8
R11
R12
N9
P10
J10
J11
J12
P11
P12
J13
K14
P13
K9
L14
L9
M14
M9
N14
M18
L16
L22
L7
TOE
XP2_TDO
XP2_TCK
XP2_TMS
N1
CFG0
R16
10K 1%
VCC_3.3V
VCC_1.2V
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
C92
0.01uF
0402
C119
0.1uF
0402
1
2
1
2
C115
0.01uF
0402
C120
0.1uF
0402
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
1
4
C90
0.01uF
0402
C121
0.1uF
0402
A1
A22
AA19
AA4
AB1
AB22
B19
B4
C10
C13
D16
D2
D21
D7
G19
G4
H10
H13
J14
J9
K10
K11
K12
K13
K15
K20
K3
K8
L10
L11
L12
L13
M10
M11
M12
M13
N10
N11
N12
N13
N15
N20
N3
N8
P14
P9
R10
R13
T19
T4
W16
W2
W21
W7
Y10
Y13
C113
0.01uF
0402
C123
0.1uF
0402
C112
0.01uF
0402
C143
0.1uF
0402
[13]
[13]
[13]
[13]
VCC_ADJ
VCC_2.5V
VCC_1.8V
VCC_1.2V
VCC_3.3V
VCC_2.5V
VCC_3.3V
VCC_2.5V
VCC_1.8V
J37
HEADER 3X2
VCC_ADJ
VCC_1.8V
J34
HEADER 3X2
VCC_ADJ
VCC_2.5V
[8]
C198
10uF Ceramic X5R
0805
C83
10uF Ceramic X5R
0805
[2]
GND5 GND3 GND8 GND7 GND1 GND4 GND6 GND2 GND9 GND10
CON1 CON1 CON1 CON1 CON1 CON1 CON1 CON1 CON1 CON1
3
VCC_ADJ
VCC_1.2V
C24
10uF Ceramic X5R
0805
C13
10uF Ceramic X5R
0805
2
Video TX/RX LVDS, High Speed SMA, IDC
VCCIO_6
Compact Flash, PLL SMA I/O
VCCIO_0
C196
10uF Ceramic X5R
0805
C78
10uF Ceramic X5R
0805
2
C23
10uF Ceramic X5R
0805
C12
10uF Ceramic X5R
0805
C173
10uF Ceramic X5R
0805
1
C178
10uF Ceramic X5R
0805
1
Sheet
FPGA Power Pins
Document Number
11
of
14
B
Rev
Lattice Semiconductor Corporation
Date:
Size
C
Title
VCC_1.8V
1
2
VCC_3.3V
GND Pins for Signal Probing
VCC_ADJ
VCC_2.5V
VCC_1.8V
VCC_1.2V
1
D
1
2
1
2
VCC_3.3V
1
VCC_3.3V
1
[12]
1
1
2
Bulk Capacitors
1
1
2
1
2
3
1
4
1
1
2
1
2
2
4
6
1
3
5
2
4
6
1
3
5
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
5
1
44
1
A
B
C
D
Lattice Semiconductor
LatticeXP2 Advanced
Evaluation Board User’s Guide
Figure 29. FPGA Power Pins
A
B
C
D
16
15
14
13
12
11
10
9
1
1
2
3
S
BANANA JACK
J51
2.5mm Pin, (+)
5.5mm Barrel, (-)
1
VCC_IN
Power Input
+5 to +28VDC
J54
PWR JACK
RAPC712
S
BANANA JACK
J53
VCC_IN
5
VTT
VCC_3.3V
VCC_2.5V
VCC_1.8V
VCC_1.2V
D30
1N5820
267-05
[13] VCC_5.0V
[13]
[13]
[13]
[13]
[13]
VREF
VCC_ADJ
SW DIP-8 CTS 194-8MST
SW2
SW3
SW PUSHBUTTON Panasonic EVQP2H02B
ON
R270
4.7K
R269
4.7K
VMON1+
VMON1GS
VMON2+
VMON2GS
VMON3+
VMON3GS
VMON4+
VMON4GS
VMON5+
VMON5GS
VMON6+
VMON6GS
VMON7+
VMON7GS
VMON8+
VMON8GS
VMON9+
VMON9GS
VMON10+
VMON10GS
VMON11+
VMON11GS
TP92
1
2
3
Off
C56
0.001uF
0402
PCI_GND
3.3V On/Off Switch
SW9
EG1257
On
R266
10K
R267
10K
R123
4.7K
POWR1220AT8
Lattice
ispPAC
U17
PLDCLK
TRIM8
TRIM7
TRIM6
TRIM5
TRIM4
TRIM3
TRIM2
TRIM1
HVOUT4
HVOUT3
HVOUT2
HVOUT1
OUT20
OUT19
OUT18
OUT17
OUT16
OUT15
OUT14
OUT13
OUT12
OUT11
OUT10
OUT9
OUT8
OUT7
OUT6
SMBA/OUT5
TDISEL
TP106
TP105
TP104
TP102
TP103
TP95
TP101
TP98
73
74
75
79
80
82
83
84
R268
10K
C59
2200pF
0402
R133
10K
0402
[5]
4
[5]
Vosence
Vprog
Ith
FCB
Run/SS
EXTVcc
10
11
12
14
13
15
C2012X5ROJ475M
BG
INTVcc
Boost
SW
TG
TK
R263
10K
R291
10
0402
3
EN_ADJ
[13]
R290
10K
0402
4
4
[13]
[13]
3 2 1
8 7 6 5
3 2 1
8 7 6 5
Q13
MMBT2222ALT
SOT-23
DIS_1.2V
DIS_2.5V
3
C55
0.47uF Ceramic X5R
R130
0603
10K
0402
10
0402
C221
4.7uF Ceramic X5R
0603
59-10
1N5819
D26
R131
DC-DC converter traces >= 10mil
U21
LTC1775CS
7
8
5
4
3
1
TP97
TP94
TP100
TP99
95
[2]
[2]
ADJ_1.2V
ADJ_1.5V
ADJ_1.8V
ADJ_2.5V
ADJ_3.3V
PWR_GOOD_VTT
PWR_GOOD_VREF
PWR_GOOD_1.2V
PWR_GOOD_1.8V
PWR_GOOD_2.5V
PWR_GOOD_3.3V
DIS_1.2V
DIS_2.5V
I2C_SCL
I2C_SDA
40
42
85
86
25
24
23
21
20
19
18
17
16
15
14
12
11
10
9
8
[4]
[4]
[4]
[4]
[4]
[4]
I2C_SCL
PWR_TDO
PWR_TDI
PWR_ATDI
PWR_TMS
PWR_TCK
TP90
I2C_SDA
VCC_3.3V
TP91
R124
4.7K
HVOUT1 from ispPAC is disabled during programming so
jumper J52 must be added during chained programming
of the XP2 and ispPAC
R250
4.7K
VMON12+
VMON12GS
R264
4.7K
100uF AVX Tantalum TPSE107K020R0150
SizeE
C58
47
46
50
48
52
51
54
53
56
55
58
57
62
61
64
63
66
65
68
67
70
69
72
71
R265
4.7K
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
3
22
36
43
88
98
R271
4.7K
VCCA
60
R273
4.7K
87
45
1
2
3
4
5
6
7
8
4
91
GNDA
GNDA
R274
4.7K
89
90
5
97
1
2
4
6
7
VCCPROG
VCCINP
IN1
IN2
IN3
IN4
IN5
IN6
VCCD
VCCD
VCCD
VPS0
VPS1
39
93
92
SDA
SCL
RESETb
SGND
6
1
2
TP96
96
MCLK
13
38
94
TP93
33
34
31
30
28
37
32
VCCJ
TDO
TDI
ATDI
TMS
TCK
TDISEL
16
Vin
PGND
9
Q12
MMBT2222ALT
SOT-23
EN_5.0V
[13]
R249
10K
1
3.3V
2.5V
1.8V
2
R251
R252
R253
R254
R255
R256
R257
R258
R259
R260
R261
Source
PWR_3.3V_3A
Q7
NTR4501N 20V 3.2A
SOT-23
Drain
PWR_3.3V_10A
Source
2
HEADER 2
F5
J52
2
C220
0.1uF
0402
C50
470uF KEMET T510X477K006AS
SizeD
PWR_3.3V_10A
1
[4,13]
[5]
C215
0.1uF
0402
MOSFET
PWR_3.3V_10A
PCI_3.3V
C218
0.1uF
0402
+3.3V
10A
C217
10uF Ceramic X5R
0805
ADJ, 1.5A
+1.2V, 3A
+1.8V, 10A
+2.5V, 3A
+3.3V, 3A
+5.0V, 1A
Date:
Size
C
Power_1
Document Number
1
Sheet
12
of
14
Lattice Semiconductor Corporation
Title
ispPAC
C52
10uF Ceramic X5R
0805
VCC_3.3V
J50
BANANA JACK
+3.3VDC
VCC_3.3V
[2,3,4,5,6,7,11]
C216
0.1uF
0402
Power
Input
+5~28V
3A FUSE Littelfuse 154003
383milX198mil
1
1
2
330
330
330
330
330
330
330
330
330
330
330
2
C53
470uF KEMET T510X477K006AS
SizeD
L6
10uH Coilcraft DO5010H-103ML
15.24mmX18.54mm
Gate
Gate
Drain
3.3V Power Good
2.5V Power Good
1.8V Power Good
1.2V Power Good
VREF Power Good
SOT-23
S3S5_1.8V
[13]
Q11
MMBT2222ALT
SOT-23
VTT Power Good
D23
Q8
Si4840DY
403-03
SO-8
MBRS340
Q9
Si4840DY
SO-8
R127
100
LED 0603 Green
D5
LED 0603 Green
D6
LED 0603 Green
D7
LED 0603 Green
D8
LED 0603 Green
D9
D10
LED 0603 Green
D11
LED 0603 Green
LED 0603 Green
D12
LED 0603 Green
D13
LED 0603 Green
D14
D15
LED 0603 Green1.5V
1.2V
ADJ Voltage Indicators
R262
10K
1
2
1
2
5
1
2
1
2
S
1
1
45
2
B
Rev
A
B
C
D
Lattice Semiconductor
LatticeXP2 Advanced
Evaluation Board User’s Guide
Figure 30. Power 1
A
B
C
D
[12]
[12]
DIS_1.2V
PWR_3.3V_10A
DIS_2.5V
PWR_3.3V_10A
1
2
F3
1
G
G
U12
TPS64203DVB
/EN
GND
FB
5
C42
10uF Ceramic X5R
0805
R122
10K
1
2
3
TPS64203DVB
/EN
GND
FB
U16
SW
VIN
ISENSE
Q5
Si2323DS Vishay Siliconix SOT23
SOT-23
1
2
3
Another P-Channel MOSFET option
in SOT23 package
DRAIN_1.2
GATE_1.2
PWR_3.3V_10A
R114
10K
SW
VIN
ISENSE
Q1
Si2323DS Vishay Siliconix SOT23
SOT-23
Another P-Channel MOSFET option
in SOT23 package
DRAIN_2.5
GATE_2.5
PWR_3.3V_10A
6
5
4
6
5
4
100
R126
R125 10
100
R110
R116 10
GATE_2.5
VBST
DRVH
LL
DRVL
PGND
CS
V5IN
PGOOD
S5
S3
0402
0.1uF
4
C43
1800p
0402
DRAIN_1.2
P-Channel
MOSFET
GATE_1.2
C29
1800p
0402
DRAIN_2.5
P-Channel
MOSFET
On
On
On
On
On
Off(Hi-Z)
Off(Discharge) Off(Discharge) Off(Discharge)
HI HI
LO HI
LO LO
TPS51116PWP
S0
S3
S4/S5
VTT
U14
VLDOIN
VTT
VTTGND
VTTSNS
GND
MODE
VTTREF
COMP
VDDQSSNS
VDDQSET
VBST
C213
VDDQ
VTTREF
1
2
3
4
5
6
7
8
9
10
PWR_1.8V
S3 S5
C34
0.033uF Ceramic
0402
VREF
C32
10uF Ceramic X5R
0805
VTT
C41
10uF Ceramic X5R
0805
10A FUSE Littelfuse 154010
383milX198mil
STATE
C208
0.1uF
0402
C33
10uF Ceramic X5R
0805
VCC_1.8V
C207
10uF Ceramic X5R
0805
[10]
VREF
[10]
VTT
VCC_1.8V
[8,9,10,11,12]
S
BANANA JACK
1
2
+1.8VDC
1
2
1
2
J47
1
20
19
18
17
16
15
14
13
12
11
4
3
2
1
G
D
D
D
S
D
D
D
S
4
D4
R117
10K
PGOOD
CS_1.8
3 2 1
VCC_2.5V
10uF Ceramic X5R
0805
100K
1
1uF Ceramic X5R
2
0402
C47
10uF Ceramic X5R
0805
C45
0.1uF
0402
C46
1
1uF Ceramic X5R
2
0402
F4
3A FUSE Littelfuse 154003
383milX198mil
+1.2VDC
3
C48
100uF Parasonic SP-CAP EEF-HD0J101R
SizeD
PWR_1.2V
VCC_1.2V
VCC_1.2V
R115 39K 1% YAGEO 0402
J48
BANANA JACK
C30
100uF Parasonic SP-CAP EEF-HD0J101R
SizeD
C27
F1
3A FUSE Littelfuse 154003
383milX198mil
C26
10uF Ceramic X5R
0805
+2.5VDC
J41
BANANA JACK
C35
4.7uF Ceramic X5R
0603
VCC_5.0V
C212
150uF Panasonic SP-CAP EEF-HE0J151R
1
2 SizeD
VCC_2.5V
R111
42.2K 1% YAGEO 0402
C44
0.01uF
0402
3
C211
150uF Panasonic SP-CAP EEF-HE0J151R
2 SizeD
1
5.1K
PWR_2.5V
R119
R118
Q3
IRF7832
SO-8
N-Channel
MOSFET
[2,5,6,9,11,12]
C31
4.7pF
0402
1
2
6.2uH Sumida CDRH6D38-6R2
B320A Diodes Inc.
SMA_PKG
D16
L4
Q6
Si5447DC
1206-8
B320A Diodes Inc.
SMA_PKG
4
SOURCE
N-Channel
MOSFET
PWR_3.3V_10A
Q4
IRF7821
SO-8
C40
L3
1
2
1.0uH Vishay IHLP-5050FD-ER-1R0-M-01
3 2 1
DRAIN 8 7 6 5
SOURCE
4
DRAIN 8 7 6 5
10uF Ceramic X5R
0805
[2,8,10,11,12]
L2
1
2
6.2uH Sumida CDRH6D38-6R2
Q2
Si5447DC
1206-8
GATE_1.8L
LL_1.8
GATE_1.8H
C37
1
2
S
1
2
1
[12]
[12]
EN_ADJ
PWR_3.3V_10A
EN_5.0V
[12]
[12]
S3S5_1.8V
PWR_3.3V_10A
PWR_3.3V_10A
1
2
5
1
2
1
2
1
2
R281
10K
1
2
3
4
5
6
7
8
NC
VOUT
VOUT
VOUT
FB
GND
LBO
EN
TPS61030PWP
SW
SW
PGND
PGND
PGND
VBAT
LBI
SYNC
U19
16
15
14
13
12
11
10
9
VCC_5.0V
VCC_5.0V
+5.0VDC
[7,12]
C39
4.7uF Ceramic X5R
0603
2
R121
10K
1
2
EN
VIN
U13
FB
VOUT
5
4
TPS78601KTT
2
VCC_ADJ
PWR_ADJ
VCC_ADJ
C36
10uF Ceramic X5R
0805
C38
2.2uF Ceramic X5R
0603
F2
1.5A FUSE Littelfuse 15401.5
383milX198mil
Power_2
Document Number
1
Sheet
13
of
14
B
Rev
Lattice Semiconductor Corporation
Date:
Size
C
Title
R120
30.1K 1% YAGEO 0402
J46
BANANA JACK
R280
221K 1% YAGEO 0603
VR3
50K POT Murata PV36Y503C01
PV37W
[11,12]
C54
2.2uF Ceramic X5R
0603
220uF AVX Tantalum TPSD227K010R0150
2 SizeD
1
R279
2.0M 1% YAGEO 0603
C51
1
(Adjustable between 1.2V to +3.3V)
L5
6.8uH Sumida CDRH124-6R8
1
2
VCC_ADJ
C49
10uF Ceramic X5R
0805
2
3
D
S
D
1
2
5
6
7
8
4
3
2
1
G
D
D
D
S
D
D
D
5
6
7
8
2
1
2
1
2
1
2
1
2
1
2
S
1
2
1
GND
3
1
2
S
1
2
1
46
1
A
B
C
D
Lattice Semiconductor
LatticeXP2 Advanced
Evaluation Board User’s Guide
Figure 31. Power 2
47
4
3
2
Lattice Semiconductor Corporation
Date:
Size
C
Document Number
1
Sheet
14
of
14
B
Rev
A
A
Placement & Dimension (6.0"x12.0")
B
B
5
Title
1
C
2
C
3
D
4
D
5
Lattice Semiconductor
LatticeXP2 Advanced
Evaluation Board User’s Guide
Figure 32. Placement and Dimension (6” x 12”)
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