LFXP2-17E-L-EVN

 LatticeXP2 Standard Evaluation Board User’s Guide February 2010 Revision: EB29_01.5  LatticeXP2 Standard Evaluation Board User’s Guide Lattice Semiconductor Introduction The LatticeXP2™ Standard Evaluation Board provides a convenient platform to evaluate, test and debug user designs. The board features a LatticeXP2-17 FPGA in a 484 fpBGA package. The LatticeXP2 I/Os are connected to a rich variety of interfaces described later in this document. This document (including the schematics in the appendix) describes LatticeXP2 Standard Evaluation Boards marked as Rev 000. This marking can be seen on the etching on the back of the printed circuit board, under the Lattice Semiconductor logo. The LatticeXP2 is a third-generation non-volatile FPGA device. It combines a Look-up Table (LUT) based FPGA fabric with Flash Non-volatile cells in a flexiFLASH™ architecture. The flexiFLASH approach provides benefits such as instant-on, small footprint, on chip storage with FlashBAK™ embedded block memories and Serial TAG memory and design security. The LatticeXP2 also supports live updates with TransFR™, 128-bit AES Encryption and Dual-Boot technologies. The LatticeXP2 devices include LUT-based logic, distributed and embedded memory, Phase Locked Loops (PLLs), pre-engineered source synchronous I/O and enhanced sysDSP™ blocks. For a full description of the LatticeXP2 FPGA, see the Lattice website for data sheets, technical notes, technology summaries and more: www.latticesemi.com/products/xp2. Some common uses for the LatticeXP2 Standard Evaluation Board include: • A Single Board Computer system • An analog-to-digital, and digital-to-analog mixed signal source/sink • A platform for evaluating the Input/Output (I/O) characteristics of the FPGA Features Key features of the LatticeXP2 Standard Evaluation Board include: • LatticeXP2 FPGA 484-pin fine pitch Ball Grid Array device (LFXP2-17E-6F484C) • Single printed circuit board solution • Eight LEDs for visual feedback • Seven-segment LED • Eight-position switch input • General purpose push buttons • SRAM memory for microprocessor applications • Compact Flash connector for adding peripherals • RS232 DB9 Female connector • LCD connector with backlight and contrast controls • IEEE 1149.1 JTAG programming/boundary-scan interface • Built-in USB download for use with ispVM® software • Built-in power supply operating from a 5V DC input • Power supply manager for testing supply sequencing • Selectable voltage for bank 6 I/O • Replaceable oscillator for reference clocks • SMA connectors to LatticeXP2 clock input/general purpose I/O pins • 100mil center-center test point grid 2 LatticeXP2 Standard Evaluation Board User’s Guide Lattice Semiconductor Other items included with this board: • USB Cable (for programming) • AC adapter (5V DC output, international AC input) Additional Resources Additional resources for this board can be downloaded from the web at www.latticesemi.com/boards. Navigate to the appropriate evaluation board to find items such as; updated documentation, software, sample designs and demos, and more. We will continue to add resources to this web page. If you wish to be notified when additional resources are available, click the subscribe to page updates icon at the top-right of the screen. General Description The heart of the board is the LatticeXP2 non-volatile FPGA. The board provides several different interconnections and support devices that permit it to be used for a variety of purposes. The SRAM, RS232, and CF connector are useful for microprocessor evaluation functions. The CF connector is also useful for expansion purposes. It provides the ability to add storage, or communication capabilities to the board. Other features on the board are useful for evaluation of the LatticeXP2 FPGA or development of more complex solutions. The A/D, D/A, and digital potentiometer are helpful for mixed signal applications. SMA connections can be used for the evaluation of high-speed differential signals, and protocols. (Note: the SMA connectors are not populated by default, but SMA connector footprints are available). The SPI memory showcases the failsafe capabilities of the LatticeXP2. The board also acts as a showcase for the small, cost effective ispPAC®-POWR607 Power Manager device. The ispPAC-POWR607 is a programmable device useful for safely managing the power supply system on the board. It can be used to sequence and monitor the voltages on the LatticeXP2 Standard Evaluation Board. Functional Description The LatticeXP2 Standard Evaluation Board is comprised of several primary functional blocks as shown in Figure 1. In the descriptions below, locations of components and board features are described relative to a compass symbol placed adjacent to the Lattice Semiconductor Corp. logo. For example, the 8-position DIP switch is on the southwest corner of the board, and the RS232 DB9 connector is on the northeast corner of the board. 3 LatticeXP2 Standard Evaluation Board User’s Guide Lattice Semiconductor Figure 1. LatticeXP2 Standard Evaluation Board RS232 DB9 SMA Connector Footprint Compact Flash RS232 PHY SMA Connector Footprint Oscillator DAC ADC SMA Connector Footprint LatticeXP2 FPGA ispPAC-POWR607 MachXO SRAM DIP Switch USB Programming Connector Power Supply The LatticeXP2 Standard Evaluation Board features a single coaxial input connector to apply power. The coaxial connector is located at the southwest side of the board. A 5V DC source must be applied to power the board. The 5V input voltage is used to power the ispPAC-POWR607 Power Manager device (U1). The input voltage is regulated down with a zener diode and a transistor. The Power Manager uses this supply rail to boot and run a power up sequence. While the LatticeXP2 does not require any specific order for the voltage rails to be applied, the Power Manager can be used to try a wide variety of sequence options. The Power Manager controls the enable inputs of three Bellnix BSV-m DC/DC converters. The Bellnix BSV-m is a point-of-load power supply. Each point-of-load supply is placed physically near the DC load. In this case the DC load of interest is the LatticeXP2 FPGA. There are three Bellnix converters on the LatticeXP2 Standard Evaluation Board. One supplies the LatticeXP2 core voltage, which is 1.2V. Another supplies the VCCAUX, VCCIO1/2/3/4/5/7, and all other 3.3V logic on the board. The third converter is adjustable from 1.1V to 2.5V and can be used to power VCCIO6. The ispPAC-POWR607 is pre-programmed to initialize the power system in a specific order. The order is arbitrary, and is not a power-sequencing guideline for the LatticeXP2. The ispPAC-POWR607 starts by turning on the 1.2V core voltage. It does not turn on any other supply on the board until the 1.2V supply reaches a programmed thresh4 LatticeXP2 Standard Evaluation Board User’s Guide Lattice Semiconductor old. Once the 1.2V supply rail is stable, the Power Manager turns on the 3.3V rail. Once again it waits for the 3.3V supply rail to stabilize before performing any other action. The Power Manager, having detected both the 1.2V and 3.3V supplies as stable, turns on the adjustable supply. Since the adjustable supply is not critical to the operation of the board the Power Manager does not wait for it to stabilize. After the board is fully powered, the ispPAC-POWR607 monitors for power-down requests – pin IN1 for a highgoing transition. When IN1 is pulled above Vth the Power Manager de-asserts the enable pins on all of the DC conversion devices, effectively powering the board down. The Power Manager continues to monitor the IN1 input, and when it is pulled below Vth it restarts the board in the same order as described earlier. U3, U4, and U6, once enabled by the ispPAC-POWR607, supply all power to the board. Adjacent to U3 and U6 are current sense resistors. These are intended to permit the measurement of the current flowing from each of the power supplies. The current sense resistors are 10mOhm in value. Table 1. LatticeXP2 Current Sense Resistors Resistor Voltage Supply R12 Vcore R17 VCCAUX, VCCIO 1/2/3/4/5/7 The LatticeXP2 Standard Evaluation Board also permits the voltage on VCCIO6 to be changed. Using a jumper on J12 controls the voltage applied to VCCIO6. The voltages that can be supplied are shown in Table 2. Table 2. LatticeXP2 IO Voltage Selection Jumper Block J12 VCCIO6 Voltage 1-2 User input from TP14/TP15 3-4 VAdj from U4 (1.1V-2.5V). Use R10 to adjust the output. 5-6 3.3V Programmability There are three programmable devices on the board. Of primary interest for the FPGA user is the LatticeXP2. However, the ispPAC-POWR607 Power Manager, and the MachXO™2280 are also important to the overall operation of the board. USB Download Cable The evaluation board has a download cable built in. The components for the built-in download cable are located in the southeast corner of the board. The built-in cable consists of a USB Type-B connector, a USB microcontroller, and a MachXO device. To use the built-in download cable, simply connect a standard USB cable (included) from J21 to your PC (with ispVM System installed). The USB Hub on the PC will detect the addition of the USB Function making the built-in cable available for use with Lattice’s ispVM System software. The USB cable is connected in parallel to J34. J34 is a 1x10 100mil header that is provided for use with an external Lattice download cable (available separately). A Lattice parallel port or USB download cable can be attached to the board using J34. Use of the built-in cable must be mutually exclusive to use of an external download cable. When using an external download cable the jumper on J28 must be moved to shunt pins 1-2. This tri-states the MachXO device, preventing it from interfering with the external download cable. 5 LatticeXP2 Standard Evaluation Board User’s Guide Lattice Semiconductor Note: The board must be un-powered when connecting, disconnecting, or reconnecting the ispDOWNLOAD® Cable or USB cable. Always connect an ispDOWNLOAD Cable’s GND pin (black wire), before connecting any other JTAG pins. Failure to follow these procedures can in result in damage to the LatticeXP2 FPGA and render the board inoperable. LatticeXP2 JTAG Access The default configuration of the LatticeXP2 Standard Evaluation Board connects the built-in JTAG cable/J34 to only access the LatticeXP2 FPGA. The serial output from the USB cable/J34 is routed directly to the serial input of the LatticeXP2 FPGA. The serial output from the LatticeXP2 is routed to J29. A jumper on J29 directs the serial output of the LatticeXP2 back to the USB cable/J34. This is the factory default configuration and is expected to be the primary JTAG mode for most users. The board can also be configured to access the LatticeXP2 FPGA, and a chained evaluation board. A 1x10 cable (not supplied) can be connected locally to J33 and the opposite end of the cable can be attached to another system that has a JTAG chain. Chaining the LatticeXP2 Standard Evaluation Board with another board is accomplished by changing the routing of the TDI/TDO/TMS/TCK I/Os. Jumpers J29, J30, J31, and J32 determine how the TDI/TDO chain and TMS pins behave. Table 3. LatticeXP2 Single/Multi-Board Configuration Jumper Block LatticeXP2 Board Plus Off-board JTAG Chain LatticeXP2 Board Only J29 1-2 2-3 J30 Open 1-2 J31 1-2 (1K pull-down resistor on TCK) 1-2 (off-board chain does not pull TCK to GND). Open (off-board chain pulls TCK to GND). J32 Open 1-2 J31, when shorted, adds a pull-down resistor to the TCK signal. Only one chained evaluation board should have a pull-down on TCK. Figure 2. Single/Multi-Board Jumpers LatticeXP2 Only LatticeXP2 + Eval J28 J29 Offboard JTAG Chain J33 J30 J31 J32 JTAG J34 6 LatticeXP2 Standard Evaluation Board User’s Guide Lattice Semiconductor The JTAG port is used for programming the LatticeXP2 and can also be used for programming the off-chip SPI PROM. The LatticeXP2 FPGA has several modes it can use to get configuration data. Available sources for configuration data are: • JTAG programming • On-chip Flash PROM (with automatic failsafe) • Off-chip SPI PROM (LatticeXP2 fetches configuration data) • Off-chip SPI interface (LatticeXP2 receives configuration data from a master) The JTAG interface to the LatticeXP2 provides several methods to program the LatticeXP2 and devices attached to the LatticeXP2. JTAG programming can be used to program the LatticeXP2 in SRAM mode (volatile). It can also be used to program the on-chip LatticeXP2 Flash memory (non-volatile). It also provides the ability to program an attached SPI PROM (U5). The SPI PROM is used for storing failsafe configuration data. ispPAC-POWR607 JTAG Access The ispPAC-POWR607 Power Manager comes from the factory with a default power sequence. It may be desired for evaluation purposes to try other power sequences. Connector J5 is the access point for the ispPAC-POWR607 JTAG I/O. See the Power Supplies and Supply Control section below for the details of using the ispPAC-POWR607. SPI Slave Connection The LatticeXP2 has configuration pins that define how the device will find a non-volatile bitstream to configure itself. In most cases the configuration pins will be set to have the LatticeXP2 act as a master device and actively read data from its internal Flash or from the attached SPI PROM. The LatticeXP2 can also be configured to act as a slave device, and accept bitstream data from an external master. The master can be connected to either the JTAG port, or it can be connected to the SPI interface. The LatticeXP2 Standard Evaluation Board provides a 1x10 header, J11, that permits an off-chip SPI master to program the LatticeXP2 FPGA. MachXO JTAG Connection The MachXO’s primary function is to be the USB download cable interface for the LatticeXP2. However, the MachXO is a PLD, and has some connections to the LatticeXP2. It is possible, therefore, to use the LatticeXP2 and the MachXO together. The MachXO can be reprogrammed with custom logic using connector J23. The factory program for the MachXO is available on-line to restore the device if needed. LatticeXP2 and Support Interfaces The LatticeXP2 Standard Evaluation Board provides a variety of support features for evaluating the performance and functionality of the LatticeXP2 FPGA. A FPGA can be used for a large number of different applications. The LatticeXP2 Standard Evaluation Board attempts to balance the ability to test I/O and the ability to use interesting/common logic functions. The evaluation board has features designed to make it easier to locate resources on the board and resources connected to the FPGA. • Devices are numbered in a consistent fashion. Each device starts at reference designator ‘1’ in the northwest corner of the board (i.e. R1, C1, U1, L1...). The component number increases by one in a columnar fashion (i.e. southward). When the south edge of the board is reached, the count resumes slightly east, and at the north side of the board. Thus, the highest numbered components will always be in the southeast corner of the board. This same numbering sequence is applied to the secondary side of the printed-circuit board. • Adjacent to most of the switch inputs, LED outputs, SMA connectors, and test points is the alphanumeric position of the pin on the LatticeXP2 FPGA. For example: next to the SMA connector J1, in the silkscreen, is the designator (P1). Thus LatticeXP2 (U7) pin P1 is connected to the center post of J1. • SMA connectors have an open white rectangle area near them denoting the positive side of a matched pair. The negative side of the matched pair has a solid filled white rectangular area. 7 LatticeXP2 Standard Evaluation Board User’s Guide Lattice Semiconductor Push-Buttons and Status LEDs There are four push-buttons and three LEDs on the south edge of the evaluation board. Switch SW2 and SW3, the westernmost, are routed to generic LatticeXP2 I/Os. One of these buttons typically acts as a reset switch, providing a reset pulse to logic inside the LatticeXP2. SW4, which is near the USB connector, is tied to the LatticeXP2’s PROGRAMn input. Pressing this switch will cause the LatticeXP2 to reprogram itself, as long as CFG0 is set to VIL. SW5 is adjacent to SW4 and is the reset button for the built-in USB download cable. Pressing this button will cause the USB cable to re-enumerate with the USB hub. In the southeast corner of the board are three status LEDs. These indicate the state of the LatticeXP2’s Done, INITn, and PROGRAMn I/O pins. During normal operation the Done and the INITn LEDs will illuminate. Global Output Enable The LatticeXP2 has a global output enable control. The GOE is routed to J15, and the factory default setting on J15 is to enable the LatticeXP2 outputs. The jumper on J15 can be moved from the default setting (open) to disable (tristate) all of the LatticeXP2 I/Os. Table 4. Global Output Enable Jumper Block J15 Output Enable State Shunt Outputs disabled (tri-state) Open* Outputs enabled Prototype Grid The board provides a small 100mil center-center prototype area. The prototype area has a set of plated throughholes in a 5x8 pattern. There are a total of 16 I/O pins connected in the prototype area. The topmost row is a series of eight horizontal plated through-holes connected to the ground plane. South of this row is a row of plated throughholes connected to the LatticeXP2 device. The rows alternate GND/signal/GND/signal/GND from north to south. Some of the plated through-holes are connected to LatticeXP2 Bank 6. It is possible to modify the I/O voltage on Bank 6 using J12. Table 5. Testpoint Connections Bank # LatticeXP2 I/O Bank # LatticeXP2 I/O 6 T3 6 U3 6 U2 6 V3 6 R3 6 R4 6 P4 6 M3 6 N2 6 M4 3 W22 3 W20 3 U20 3 V20 3 U21 3 V22 LED Displays In the northwest corner of the board is a set of eight green 0603 form factor LEDs. These LEDs are connected to IO pins dedicated to driving the LEDs. Table 6 shows the LatticeXP2 I/O pins that control each LED. The LEDs illuminate when the corresponding I/O is driven to VOL. 8 LatticeXP2 Standard Evaluation Board User’s Guide Lattice Semiconductor Table 6. LED Pin Assignments LED LatticeXP2 I/O D2 J2 D3 J1 D4 K2 D5 K1 D6 M2 D7 M1 D8 L4 D9 L3 In addition to the discrete chip LEDs there is a single 7-segment display. Like the discrete LEDs, a VOL level will cause a segment to illuminate. The segment order is defined in the Lumex LDS-A304RI Data Sheet. Table 7. 7-Segment LED Pin Assignments Segment LatticeXP2 I/O A J4 B H4 C F4 D E4 E E3 F H3 G G3 DP F3 Switches The evaluation board provides a set of eight simple toggle switches at the southwest edge of the board. The silkscreen calls out the alphanumeric location of the I/O on the FPGA. The switch, when in the up position, is pulled to VCCIO6 through a 10K resistor. When in the down position, the switch is tied to ground. Table 8. SW1 Switch Pin Assignments Switches LatticeXP2 I/O SW1-0 AA3 SW1-1 AA2 SW1-2 AA1 SW1-3 Y4 SW1-4 Y3 SW1-5 Y2 SW1-6 Y1 SW1-7 W3 Oscillator and Clock Inputs FPGA designs are almost without exception created with logic synchronous to some reference frequency. The LatticeXP2 Standard Evaluation Board provides a built-in oscillator that provides a reference frequency for synchronous FPGA logic. Reference frequencies can be applied to other LatticeXP2 clock inputs as well. The LatticeXP2 board provides a low-voltage (3.3V) DIP oscillator. The oscillator is installed in a 14-pin DIP socket. The socket permits the use of either a half-size or full-size DIP oscillator. 9 LatticeXP2 Standard Evaluation Board User’s Guide Lattice Semiconductor Figure 3. Oscillator Positions Full-Size Placement Half-Size Placement OSC OSC Pin 1 The output from the oscillator is routed to two series resistors. One of the series resistors is connected to a primary clock input pin. The other resistor is connected to a PLL input pin. It is important to mention that DIP socket pin 8 is shorted to pin 11, so it is not possible to input two different clock frequencies from the socket. In order to provide a frequency on the primary clock input that is different from the PLL clock input it is necessary to remove one of the two series termination resistors, and add a temporary modification to inject an electrically isolated clock signal. Differential/50 Ohm Input/Output The LatticeXP2 Standard Evaluation Board provides connections to differential I/O pins. The circuit board traces for these connections are nominally 50-ohm impedance. Some of the differential I/O pins are inputs to primary or PLL clock drivers. If the built-in oscillator in socket XU1 does not provide the right kind of input clock the SMA connectors listed in Table 9 can be used to provide additional reference clock frequencies. Table 9. Differential/50 Ohm Trace Pin Assignments Connector Pair LatticeXP2 I/O Clock Input J1 P1 N J2 R1 N J3 J4 Physical connection T1 Silkscreen text W4 Physical connection U1 Silkscreen text Y5 Y (P) Y (N) J6 P2 N J10 P3 N T2 (3) / R2 (4) N J7 J8 Physical connection Y5 (3) / W4 (4) Silkscreen text U1 (3) / T1 (4) N J24 J22 Y (P) J25 K22 Y (N) J26 K21 Y (P) J27 L21 Y (N) Power Supplies and Supply Control The LatticeXP2 Standard Evaluation Board operates from a 5V DC input voltage. The input voltage is supplied via J9, a coaxial DC input jack. The following components operate using the 5V input: • ispPAC-POWR607 Power Manager • Bellnix DC/DC converters 10 LatticeXP2 Standard Evaluation Board User’s Guide Lattice Semiconductor • LCD Display, contrast and backlight controls ispPAC-POWR607 The ispPAC-POWR607 is a low-cost power management chip that is used on the LatticeXP2 Standard Evaluation Board to turn on the DC/DC converters in a controlled sequence. The LatticeXP2 FPGA does not require voltages to be applied in a predefined sequence. The ispPAC-POWR607 permits testing any startup sequence. The ispPAC-POWR607 operates over a much looser DC input range than most 3.3V logic. It is capable of running from an input supply less than 3.96V and greater than 2.64V. This allows the DC regulation from the 5V input to be performed with loose tolerances and inexpensive components. The evaluation board uses a zener diode and a transistor to regulate the 5V input. The ispPAC-POWR607 is the first device on the board to have a stable supply voltage. Using this stable supply voltage it is able to turn on other supplies in a controlled sequence. The sequence is reprogrammable. Reprogramming is done using Lattice Semiconductor’s PAC Designer® software, available from www.latticesemi.com/pac-designer. The source code for the factory default program is available on the Lattice web site at www.latticesemi.com/boards. Navigate to the appropriate page for this board and choose “Design Files” from the list of available resources. The ispPAC-POWR607 sequence programmed from the factory starts by enabling the 1.2V DC converter. The Power Manager waits for the 1.2V supply rail to reach 95% of its threshold voltage before turning on any other supply. The next voltage supply to be enabled is the 3.3V rail. Once again the Power Manager waits for this rail to reach 95% threshold. When the 3.3V rail reaches threshold, the adjustable voltage rail is enabled, but the Power Manager does not wait for it to reach a specified threshold since this rail is an auxiliary supply rail. The next step is for the Power Manager to monitor the PWDN/IN1 input pin. When this pin goes to VIH the Power Manager disables all of the DC/DC converters. When the IN1 pin returns to VIL the Power Manager starts over as if power had just been applied. Table 10. ispPAC-POWR607 to LatticeXP2 General Purpose Connections ispPAC-POWR607 Pin LatticeXP2 I/O 28 V19 26 P19 23 R19 22 M19 20 M20 Bellnix DC/DC Converters The 5V rail also supplies power to Bellnix DC/DC converters. The Bellnix converters are point of load (POL) DC supplies. The supplies are mounted close to the LatticeXP2 FPGA in order to increase response time during periods of high current demand. U3 is solely dedicated to supplying the LatticeXP2 FPGA’s core voltage. The 1.2V passes through R12, a 10mOhm current sense resistor. The resistor permits voltage drop measurements to be used to determine how much power is being used by the LatticeXP2. U5 is an adjustable supply with a range from 1.1V through 2.5V. The voltage from this supply is only routed to J12. J12 is used to configure the I/O voltage used by Bank 6. U6 is a fixed 3.3V supply. It provides 3.3V to all of the ICs on the board, as well as the LatticeXP2’s VCCAUX and VCCIO banks (except Bank 6). The 3.3V provided to VCCAUX and VCCIO pass through R17, a 10 mOhm current sense resistor. This allows for a voltage drop measurement to be taken indicating the amount of current being drawn by the LatticeXP2. 11 LatticeXP2 Standard Evaluation Board User’s Guide Lattice Semiconductor LCD Connector Connector J13 is a 2x9 100mil center-center header designed to allow the use of LCD displays. The connector provides 5V directly from the DC input (J9). It also has adjustable backlight (R15) and contrast (R16) potentiometer controls. The connector is designed for use with LCD displays such as the Lumex LCM-S02002DSF or LCMS02002DSR. Note: Recent Lumex specifications show a 16-pin interface, which corresponds to pins 2-18 on the J13 LCD Connector. Table 11. LCD Connections LCD Pin # LCD Function LatticeXP2 I/O 6 RS U22 7 RW Physical Connection T21 Silkscreen Text R22 8 E 9 D0 T22 Physical Connection R22 Silkscreen Text R20 10 D1 11 D2 T20 Physical Connection R20 Silkscreen Text P21 12 D3 13 D4 R21 Physical Connection P21 Silkscreen Text N22 14 D5 15 D6 P22 Physical Connection N22 Silkscreen Text 16 — D7 P20 RS232 Interface The evaluation board provides a RS232 connection for interfacing to equipment with RS232 ports. The RS232 connector is a female DB9 connector, and can be found in the northeast corner of the board. Four 1x3 jumpers are provided on the board to permit reconfiguration of the RX/TX/RTS/CTS connections. Table 12. RS232 DB9 Pin Assignments RS232 Signal Connector Pin 1-2 Pin 2-3 RX J18 J16-3 J16-2 TX J17 J16-2 J16-3 CTS J19 J16-7 J16-8 RTS J22 J16-8 J16-7 The LatticeXP2 FPGA is connected to the RS232 DB9 connector using a Max 3232 buffer chip. This buffer permits the LatticeXP2 3.3V I/O pins to be interfaced to the 12V RS232 signaling standard. The LatticeXP2 I/O pins that connect to the RS232 buffer listed in Table 13. Table 13. LatticeXP2 to RS232 Pin Assignments RS232 Signal LatticeXP2 I/O RX C21 TX B22 CTS B21 RTS C22 12 LatticeXP2 Standard Evaluation Board User’s Guide Lattice Semiconductor Compact Flash Connector Connector J14 provides the evaluation board with the ability to interface to 3.3V Type II Compact Flash devices. The FPGA can be programmed to use the various different Compact Flash protocols. Table 14. Compact Flash Pin Assignments Connector Pin LatticeXP2 I/O Connector Pin LatticeXP2 I/O CF0 B12 CF23 D6 CF1 A12 CF24 C6 CF2 A11 CF25 A5 CF3 B11 CF26 C5 CF4 D11 CF27 A4 CF5 C11 CF28 C4 CF6 A10 CF29 A3 CF7 B10 CF30 B3 CF8 E10 CF31 B2 CF9 A9 CF32 B1 CF10 B9 CF33 C3 CF11 D9 CF34 C2 CF12 C9 CF35 C1 CF13 A8 CF36 D4 CF14 B8 CF37 D3 CF15 D8 CF38 D1 CF16 C8 CF39 E1 CF17 A7 CF40 F2 CF18 B7 CF41 F1 CF19 F7 CF42 G2 CF20 C7 CF43 G1 CF21 A6 CF44 H2 CF22 B6 CF45 H1 Mixed Signal Support The LatticeXP2 Standard Evaluation Board also provides access to some mixed signal interface chips. There are four primary components dedicated to performing mixed signal functions on the evaluation board. These components are: • 12-bit Analog to Digital Converter • 12-bit Digital to Analog Converter • 128-position Digital Potentiometer • 25K ohm Discrete Potentiometer The mixed signal devices are all powered from the 3.3V supply. The digital power for these devices comes directly from the 3.3V plane layer. The analog power is supplied via a smaller independent 3.3V plane. The independent plane is supplied from the 3.3V digital plane, but it is filtered with a ferrite bead. Analog to Digital Converter The board includes a Burr Brown ADS7842 4 Channel Parallel Sampling Analog to Digital converter. 13 LatticeXP2 Standard Evaluation Board User’s Guide Lattice Semiconductor The analog inputs of the device are connected to four test points. One of these test points is also connected to a 25K ohm discrete potentiometer. The potentiometer permits the input voltage level to vary between 0V to 3.3V at one of the A/D inputs. The remaining three inputs are not connected to any passive or active components. These test points can be used to inject signals meeting your own test requirements. The digital I/O side of the device connects directly to the LatticeXP2 FPGA. Twelve of the I/O are the data-bus pins, and seven are used to access the internal registers. Table 15. A/D Connections A/D Function LatticeXP2 I/O A/D Function LatticeXP2 I/O AD0 A17 AD10 C19 AD1 B16 AD11 D19 AD2 A16 A0 C20 AD3 B15 A1 A21 AD4 A15 CLK B20 AD5 C16 BUSYn A20 AD6 C17 WRn A19 AD7 D17 CSn A18 AD8 C18 RDn B17 AD9 D18 Digital to Analog Converter The board also includes a Burr Brown DAC7617 12-bit Serial Input Digital to Analog converter. The digital interface of the converter is a six-wire control set. Changes to the analog outputs are performed using serial data. A change to an internal register requires 16 clock cycles. The analog outputs from the D/A are connected directly to individual test points. There is no other logic connected to the analog outputs. The AIN2 input pin controls the range of the analog outputs. AIN2 is connected to a test-point adjacent to the A/D converter described in the section above. AIN2 is also accessible via J20 pin 2. J20 is a 1x2 pin header that allows the output of the digital potentiometer to be connected to the D/A VREFH input. In order for the digital potentiometer to supply the reference voltage to the D/A converter, J20 must have pins 1-2 shunted. Regardless of the VREFH source voltage, the D/A is able to output a voltage between VREFL (GND) and VREFH (AIN2) in a +/- 1/4096th increment. Table 16. D/A Connections Digital to Analog Function LatticeXP2 I/O Serial Data In C12 Clock D12 Chip Select A13 Load All A14 Load Register C14 Reset D14 Digital Potentiometer The evaluation board also provides a 10K ohm digital potentiometer. The potentiometer can be set to one of 128 positions between 0 ohm and 10K ohm. The potentiometer output voltage, which is present on J20 pin 1, can vary from 0V to 3.3V. The potentiometer will be at the midpoint resistance at power up. 14 LatticeXP2 Standard Evaluation Board User’s Guide Lattice Semiconductor Operation of the potentiometer is very simple. Whenever the CS is asserted (VIL) and a clock transition occurs, the output voltage will change up/down by 1/128th. When the UP direction is requested, the output voltage will increase. Table 17. Digital Potentiometer Connections POT Function LatticeXP2 I/O CLK D15 Up/Down_n C15 CS_n B14 SRAM The evaluation board provides a quantity of asynchronous SRAM. The memory is organized as 256Kx32 providing 1Mbyte of storage. Asynchronous SRAMs provide a simple electrical and control interface eliminating the need for more complex memory control systems. Table 18. SRAM Connections SRAM Function LatticeXP2 I/O SRAM Function LatticeXP2 I/O SRAM Function LatticeXP2 I/O A0 W9 BE2 AA17 D14 AB6 A1 AB10 BE3 AB17 D15 AB5 A2 AA10 CE0 AB2 D16 W14 A3 Y11 CE1 Y14 D17 Y15 A4 W11 WE Y12 D18 W15 A5 W12 OE AB12 D19 Y16 A6 AA13 D0 V6 D20 Y17 A7 AA14 D1 W5 D21 W17 A8 AA15 D2 Y6 D22 Y18 A9 AA16 D3 W6 D23 W18 A10 AB16 D4 Y7 D24 Y22 A11 AB15 D5 Y8 D25 AA22 A12 AB14 D6 W8 D26 Y21 A13 AB13 D7 Y9 D27 AA21 A14 AA12 D8 AB9 D28 AA20 A15 AA11 D9 AA8 D29 AB20 A16 AB11 D10 AB8 D30 AB19 D31 AB18 A17 AA9 D11 AA7 BE0 AB4 D12 AB7 BE1 AB3 D13 AA6 Ordering Information Description LatticeXP2 Standard Evaluation Board Ordering Part Number China RoHS Environment-Friendly Use Period (EFUP) LFXP2-17E-L-EV 10 15 LatticeXP2 Standard Evaluation Board User’s Guide Lattice Semiconductor Technical Support Assistance Hotline: 1-800-LATTICE (North America) +1-503-268-8001 (Outside North America) e-mail: techsupport@latticesemi.com Internet: www.latticesemi.com Revision History Date Version May 2007 01.0 Initial release. Change Summary October 2007 01.1 Updated schematic diagrams. Note: The schematic diagrams on previous versions of this document contained erroneous reference designators for the board components. January 2008 01.2 Updated Differential/50 Ohm Trace Pin Assignments table. February 2008 01.3 Updated 7-Segment LED Pin Assignments table. May 2008 01.4 Corrected LatticeXP2 FPGA part number in the Features list. February 2010 01.5 Updated SRAM Connections table. Updated LCD Connections table. © 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 16 17 A B C D 5 D3 D4 D5 D6 D7 CE1N/CE1N/CS0N A10 OEN/OEN/ATA_SELN A9 A8 A7 A6 A5 A4 A3 A2 5 CF0 CF1 CF2 CF3 CF4 CF5 CF6 CF7 CF8 CF9 CF10 CF11 CF12 CF13 CF14 CF15 VADJ +1_2V +3_3V XP2_VCCIO[0..7] XP2Bank5_19 XP2Bank5_45 XP2Bank5_31 XP2Bank5_39 XP2Bank5_25 XP2Bank5_49 XP2Bank4_33 XP2Bank4_26 XP2Bank4_27 XP2Bank4_20 XP2Bank4_34 XP2Bank5_51 XP2Bank5_50 XP2Bank5_46 XP2Bank5_38 XP2Bank5_30 XP2Bank5_44 XP2Bank5_27 XP2Bank5_34 XP2Bank5_29 XP2Bank4_21 XP2Bank4_35 XP2Bank5_28 XP2Bank4_32 XP2Bank5_48 XP2Bank5_47 SRAM_BE0 SRAM_BE1 SRAM_BE2 SRAM_BE3 SRAM_CE0 SRAM_CE1 SRAM_WE SRAM_OE VCCIO6 LED[0..7] PB[0..1] SRAM_OE SRAM_WE SRAM_CE[0..1] SRAM_BE[0..3] SRAM_A[0..17] 4 SRAM SRAM_OE SRAM_WE SRAM_CE[0..1] SRAM_BE[0..3] SRAM_A[0..17] SRAM_D[0..31] CF[0..45] CLK[0..7] RS232_[0..3] LVDS_C[0..3] LVDS_T[0..3] LCD[0..10] AD_A0 AD_A1 AD_CLK AD_BUSYn AD_WRn AD_CSn AD_RDn XP2Bank7_2 POT_CLK XP2Bank7_0 POT_U_Dn XP2Bank7_3 POT_CSn XP2Bank7_4 XP2Bank7_8 S_A XP2Bank7_9 S_F XP2Bank7_5 S_E XP2Bank7_7 XP2Bank7_13 S_D XP2Bank7_14 S_DP XP2Bank7_21 S_C XP2Bank7_15 S_G XP2Bank7_23 S_B XP2Bank7_22 XP2_CFG3 XP2_CFG4 XP2_CFG0 XP2_CFG1 XP2_CFG2 XP2_CFG3 XP2_CFG4 XP2_CFG5 XP2_CFG6 XP2_CFG7 XP2_CFG8 XP2_CFG9 XP2_CFG10 +3_3V SWITCH[0..7] CF32 CF33 CF34 CF35 CF36 CF37 CF38 CF39 CF40 CF41 CF42 CF43 CF44 CF45 CFG0 CFG1 TOE DONE INITN PROGRAMN CCLK CSSPIN SO SI CSSPISN XP2_CFG[0..10] XP2_JTAG[0..3] XP2_VCCIO[0..7] XP2_VCCAUX XP2_VCORE Page 10 CF[0..45] CLK[0..7] RS232_[0..3] LVDS_C[0..3] LVDS_T[0..3] LCD[0..10] SWITCH[0..7] Page 7 H7 AD_CTRL[0..6] DA[0..5] XP2_CFG[0..10] VCC_JTAG XP2_JTAG[0..3] VCCIO[0..7] VCC_AUX VCC_CORE IOWRN WEN READY/IREQN/INTRQ CSELN VS2N RESET/RESET/RESETN WAITN/WAITN/IORDY INPACK/DMARQ REGN/DMACKN BVD2/SPRKRN/DASPN BVD1/STSCHGN/PDIAGN D8 D9 D10 AD_D[0..11] SEG[0..7] POT[0..2] Peripherals H4 Page 2 XP2_VCCIO[0..7] XP2Bank0_23 XP2Bank0_26 XP2Bank0_21 XP2Bank0_4 XP2Bank0_15 XP2Bank0_19 XP2Bank0_20 XP2Bank0_6 XP2Bank0_14 XP2Bank0_18 XP2Bank0_10 XP2Bank0_13 XP2Bank0_11 XP2Bank0_12 XP2Bank0_3 XP2Bank7_1 XP2_VCCIO6 SRAM_A0 SRAM_A1 SRAM_A2 SRAM_A3 SRAM_A4 SRAM_A5 SRAM_A6 SRAM_A7 SRAM_A8 SRAM_A9 SRAM_A10 SRAM_A11 SRAM_A12 SRAM_A13 SRAM_A14 SRAM_A15 SRAM_A16 SRAM_A17 LED[0..7] PB[0..1] DA[0..5] AD_CTRL[0..6] AD_D[0..11] SEG[0..7] POT[0..2] CF16 CF17 CF18 CF19 CF20 CF21 CF22 CF23 CF24 CF25 CF26 CF27 CF28 CF29 CF30 CF31 XP2_VCCAUX XP2_VCORE A1 A0 D0 D1 D2 WP/IOIS16N/IOCS16N CD2N CD1N D11 D12 D13 D14 D15 CE2N/CE2N/CS1N VS1N IORDN Page 6 XP2_VCCAUX XP2_VCORE XP2Bank7_[0..45] XP2Bank6_[0..45] XP2Bank5_[0..52] XP2Bank4_[0..37] XP2Bank3_[0..45] XP2Bank2_[0..45] XP2Bank1_[0..35] XP2Bank0_[0..51] XP2 H2 +3_3V +1_2V VADJ XP2Bank7_[0..45] XP2Bank6_[0..45] XP2Bank5_[0..52] XP2Bank4_[0..37] XP2Bank3_[0..45] XP2Bank2_[0..45] XP2Bank1_[0..35] XP2Bank0_[0..51] XP2_VCCIO[0..7] XP2Bank0_44 XP2Bank0_43 XP2Bank0_37 XP2Bank0_42 XP2Bank0_38 XP2Bank0_39 XP2Bank0_36 XP2Bank0_35 XP2Bank0_33 XP2Bank0_29 XP2Bank0_34 XP2Bank0_30 XP2Bank0_31 XP2Bank0_28 XP2Bank0_27 XP2Bank0_22 BYPASS H8 XP2Bank7_[0..45] XP2Bank6_[0..45] XP2Bank5_[0..52] XP2Bank4_[0..37] XP2Bank3_[0..45] XP2Bank2_[0..45] XP2Bank1_[0..35] XP2Bank0_[0..51] 4 SRAM_D[0..31] LCD0 LCD1 LCD2 LCD3 LCD4 LCD5 LCD6 LCD7 LCD8 LCD9 LCD10 SRAM_D0 SRAM_D1 SRAM_D2 SRAM_D3 SRAM_D4 SRAM_D5 SRAM_D6 SRAM_D7 SRAM_D8 SRAM_D9 SRAM_D10 SRAM_D11 SRAM_D12 SRAM_D13 SRAM_D14 SRAM_D15 SRAM_D16 SRAM_D17 SRAM_D18 SRAM_D19 SRAM_D20 SRAM_D21 SRAM_D22 SRAM_D23 SRAM_D24 SRAM_D25 SRAM_D26 SRAM_D27 SRAM_D28 SRAM_D29 SRAM_D30 SRAM_D31 XP2Bank3_20 XP2Bank3_29 XP2Bank3_27 XP2Bank3_30 XP2Bank3_35 XP2Bank3_19 XP2Bank3_18 XP2Bank3_21 XP2Bank3_26 XP2Bank3_28 XP2Bank3_31 XP2Bank1_27 XP2Bank1_26 XP2Bank1_29 XP2Bank1_28 XP2Bank1_35 XP2Bank1_18 XP2Bank1_19 XP2Bank1_6 XP2Bank1_2 XP2Bank1_7 XP2Bank1_3 XP2Bank1_5 XP2Bank2_5 XP2Bank1_8 XP2Bank2_4 XP2Bank1_4 XP2Bank1_9 XP2Bank1_21 XP2Bank1_20 XP2Bank7_35 XP2Bank7_19 XP2Bank7_17 XP2Bank7_10 XP2Bank7_6 XP2Bank7_18 XP2Bank7_20 XP2Bank7_12 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 AD_D0 AD_D1 AD_D2 AD_D3 AD_D4 AD_D5 AD_D6 AD_D7 AD_D8 AD_D9 AD_D10 AD_D11 AD_CTRL0 AD_CTRL1 AD_CTRL2 AD_CTRL3 AD_CTRL4 AD_CTRL5 AD_CTRL6 XP2Bank1_11 XP2Bank1_10 XP2Bank1_34 XOBank1_[0..28] POT0 POT1 POT2 XOBank1_22 XOBank1_25 XP2Bank7_33 XP2Bank7_43 XP2Bank7_32 XP2Bank7_40 XP2Bank7_37 XP2Bank7_41 XP2Bank7_42 XP2Bank7_36 XP2Bank7_34 XP2_CFG[0..10] XOBank1_[0..28] 3 3 XP2Bank6_37 XP2Bank6_21 XP2Bank6_33 XP2Bank6_45 LVDS_C0 LVDS_C1 LVDS_C2 LVDS_C3 XP2Bank0_2 XP2Bank0_50 XP2Bank3_42 XP2Bank3_43 XP2Bank2_44 XP2Bank2_45 XP2Bank5_2 XP2Bank5_3 XP2Bank7_44 XP2Bank7_45 XP2Bank7_38 XP2Bank7_39 XP2Bank7_30 XP2Bank7_31 XP2Bank7_28 XP2Bank7_29 XP2Bank6_30 XP2Bank6_31 XP2Bank1_17 XP2Bank1_25 XP2Bank0_51 XP2Bank0_45 XP2Bank1_33 XP2Bank0_47 XP2Bank5_4 XP2Bank5_10 XP2Bank5_12 XP2Bank5_11 XP2Bank5_13 XP2Bank5_15 XP2Bank5_7 XP2Bank5_14 XP2Bank5_43 XP2Bank5_26 XP2Bank5_42 XP2Bank5_21 XP2Bank5_37 XP2Bank5_20 XP2Bank5_36 XP2Bank5_35 XP2Bank4_16 XP2Bank4_5 XP2Bank4_8 XP2Bank4_4 XP2Bank4_2 XP2Bank4_0 XP2Bank4_3 XP2Bank4_1 XP2Bank4_10 XP2Bank4_12 XP2Bank4_11 XP2Bank4_13 XP2Bank4_19 XP2Bank4_18 XP2Bank4_29 XP2Bank4_28 CLK0 CLK1 CLK2 CLK3 CLK4 CLK5 CLK6 CLK7 LED0 LED1 LED2 LED3 LED4 LED5 LED6 LED7 PB0 PB1 DA0 DA1 DA2 DA3 DA4 DA5 XP2Bank6_4 XP2Bank6_22 XP2Bank6_29 XP2Bank6_5 XP2Bank6_14 XP2Bank6_23 XP2Bank6_28 XP2Bank6_15 XP2Bank6_36 XP2Bank6_20 XP2Bank6_32 XP2Bank6_44 LVDS_T0 LVDS_T1 LVDS_T2 LVDS_T3 SWITCH0 SWITCH1 SWITCH2 SWITCH3 SWITCH4 SWITCH5 SWITCH6 SWITCH7 XP2Bank2_12 XP2Bank2_13 XP2Bank2_20 XP2Bank2_21 RS232_0 RS232_1 RS232_2 RS232_3 Page 5 XP2_CFG[0..10] XP2_JTAG[0..3] XOBank1_[0..28] CONFIG H9 PLL_IN PCLK_IN PCLK3_T PCLK3_C PCLK2_T PCLK2_C PLL_T PLL_C DA_RSTn DA_LOADREGn DA_LDACn DA_CSn DA_CLK DA_SI CTSn RXD TXD RTSn VCCIO7 XP2_VCCIO7 Placement H10 Page 20 2 XOBank3[0..28] PCLK3_T PCLK3_C XP2Bank5_2 XP2Bank5_3 XP2Bank2_44 XP2Bank2_45 XP2Bank3_42 XP2Bank3_43 XP2Bank2_7 XP2Bank2_22 XP2Bank2_6 XP2Bank2_23 XP2Bank2_28 XP2Bank2_29 XP2Bank2_31 XP2Bank2_15 XP2Bank2_30 XP2Bank2_36 XP2Bank2_14 XP2Bank2_38 XP2Bank2_37 XP2Bank2_18 XP2Bank2_39 Page 16 XOBank3_[0..28] XOBank2_[0..25] XOBank01_[0..1] XOBank1_[0..28] PCLK2_T PCLK2_C PLL_T PLL_C Page 12 XOBank0_[0..23] USB H1 Page 11 VADJ +1_2V XOBank3_0 XOBank2_25 XOBank2_23 XOBank7_[0..25] XOBank6_[0..27] XOBank45_[0..1] XOBank5_[0..19] XOBank4_[0..27] VADJ Date: Size C Title Document Number XP2 Standard Evaluation Board Lattice Semiconductor Corporation 5555 NE Moore Ct Hillsboro, OR 97124 XOBank2[0..25] XP2Bank2[0..45] XOBank7_[0..25] XOBank6_[0..27] XOBank45_[0..1] XOBank5_[0..19] +1_2V XP2Bank6_[0..45] XP2Bank3_[0..45] XOBank4_[0..27] XP2Bank6_[0..45] XP2Bank3_[0..45] XP2Bank3_[0..45] +3_3V POWER H5 Prototype H6 XOBank3_15 XOBank3_20 XOBank3_21 XOBank3_14 XOBank3_13 XOBank3_17 XOBank3_11 XOBank3_12 XOBank3_16 XOBank3_19 XOBank3_10 XOBank3_5 XOBank3_7 XOBank3_9 XOBank3_1 XOBank3_[0..28] XOBank2_[0..25] XOBank01_[0..1] XOBank1_[0..28] XOBank0_[0..23] XP2Bank3_[0..45] +3_3V 2 1 Sheet XP2Bank3_36 XP2Bank3_34 XP2Bank3_37 1 1 of XP2Bank3[0..45] 20 Rev 000 A B C D Lattice Semiconductor LatticeXP2 Standard Evaluation Board User’s Guide Appendix A. Schematics Figure 4. LatticeXP2 Standard Evaluation Board 18 A B C D XP2_JTAG[0..3] 5 XP2_CFG[0..10] VCCIO[0..7] VCC_CORE VCC_JTAG XP2_CFG[0..10] VCCIO[0..7] XP2_JTAG[0..3] 5 B18 D13 E16 H14 E21 G18 J15 K19 N19 P15 T18 V21 AA18 R14 V16 W13 AA5 R9 V7 W10 N4 P8 T5 V2 E2 G5 J8 K4 VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 XP2_CFG0 N1 XP2_CFG2 L7 H9 E7 D10 B5 N9 P10 J10 J11 J12 P11 P12 J13 K14 P13 K9 L14 L9 M14 M9 N14 H15 L20 M18 L16 L22 VCCIO0 XP2_JTAG0 XP2_JTAG1 XP2_JTAG2 XP2_JTAG3 CFG0 TOE VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCJ TDI TDO TCK TMS U7E DI LFXP217 FPBGA484 4 NC1 NC2 4 H8 U19 VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND R12 R11 M8 M15 L8 L15 H12 H11 A1 A22 AA19 AA4 AB1 AB22 B19 B4 C10 C13 D16 D2 D21 D7 G19 G4 H10 H13 J14 J9 K10 K11 K12 K13 K15 K20 K3 K8 L10 L11 L12 L13 M10 M11 M12 M13 N10 N11 N12 N13 N15 N20 N3 N8 P14 P9 R10 R13 T19 T4 W16 W2 W21 W7 Y10 Y13 VCC_AUX 3 XP2Bank7_[0..45] XP2Bank6_[0..45] XP2Bank5_[0..52] XP2Bank4_[0..37] XP2Bank3_[0..45] XP2Bank2_[0..45] XP2Bank1_[0..35] XP2Bank0_[0..51] 3 XP2Bank7_[0..45] XP2Bank6_[0..45] XP2Bank5_[0..52] XP2Bank4_[0..37] XP2Bank3_[0..43] XP2Bank2_[0..45] XP2Bank1_[0..35] XP2Bank0_[0..51] XP2Bank3_[0..45] XP2Bank2_[0..45] XP2Bank1_[0..35] XP2Bank0_[0..51] XP2Bank7_[0..45] XP2Bank6_[0..45] XP2Bank5_[0..52] XP2Bank4_[0..37] XP2_BANK_4_7 H3 XP2_BANK0_3 H1 2 Page 4 Page 3 2 Date: Size B Title Document Number XP2 Power and Configuration 5555 NE Moore Ct Hillsboro, OR 97124 Lattice Semiconductor Corporation Sheet 1 1 2 of 20 Rev 000 A B C D Lattice Semiconductor LatticeXP2 Standard Evaluation Board User’s Guide Figure 5. LatticeXP2 Power and Configuration 19 A B C D 5 E13 C14 B16 A17 B15 A16 G10 G11 E12 D12 B14 A15 XP2Bank1_24 XP2Bank1_25 XP2Bank1_26 XP2Bank1_27 XP2Bank1_28 XP2Bank1_29 XP2Bank1_30 XP2Bank1_31 XP2Bank1_32 XP2Bank1_33 XP2Bank1_34 XP2Bank1_35 C16 C17 XP2Bank1_18 XP2Bank1_19 B17 A18 F14 D14 XP2Bank1_16 XP2Bank1_17 F13 G12 G13 G14 XP2Bank1_14 XP2Bank1_15 XP2Bank1_22 XP2Bank1_23 E14 E15 XP2Bank1_12 XP2Bank1_13 XP2Bank1_20 XP2Bank1_21 A21 A19 XP2Bank1_6 XP2Bank1_7 C15 D15 D17 D18 XP2Bank1_4 XP2Bank1_5 XP2Bank1_10 XP2Bank1_11 A20 D19 XP2Bank1_2 XP2Bank1_3 XP2Bank1_8 XP2Bank1_9 E17 E18 C18 C19 XP2Bank1_0 XP2Bank1_1 5 LFXP217 FPBGA484 PT29A/PT38A/PT38A/PCLKT1_0 PT29B/PT38B/PT38B/PCLKC1_0 PT30A/PT39A/PT39A PT30B/PT39B/PT39B PT31A/PT40A/PT40A PT31B/PT40B/PT40B PT32A/PT41A/PT41A PT32B/PT41B/PT41B PT33A^/PT42A^/PT42A^ PT33B/PT42B/PT42B PT34A/PT43A/PT43A PT34B/PT43B/PT43B PT35A/PT44A/PT44A PT35B/PT44B/PT44B PT36A/PT45A/PT45A PT36B/PT45B/PT45B PT37A/PT46A/PT46A PT37B/PT46B/PT46B PT38A/PT47A/PT47A PT38B/PT47B/PT47B PT39A/PT48A/PT48A PT39B/PT48B/PT48B PT40A/PT49A/PT49A PT40B/PT49B/PT49B PT41A/PT50A/PT50A PT41B/PT50B/PT50B PT42A^/PT51A^/PT51A^ PT42B/PT51B/PT51B PT43A/PT52A/PT52A PT43B/PT52B/PT52B PT44A/PT62A/PT70A/URC_GPLLT_IN_A PT44B/PT62B/PT70B/URC_GPLLC_IN_A PT45A/PT63A/PT71A/URC_GPLLT_FB_A PT45B/PT63B/PT71B/URC_GPLLC_FB_A PT46A/PT64A/PT72A/VREF1_1 PT46B/PT64B/PT72B/VREF2_1 U7D DI PT3A/PT3A/PT3A/VREF1_0 PT3B/PT3B/PT3B/VREF2_0 4 PT28A/PT37A/PT37A/PCLKT0_0 PT28B/PT37B/PT37B/PCLKC0_0 PT27A/PT36A/PT36A PT27B/PT36B/PT36B PT26A/PT35A/PT35A PT26B/PT35B/PT35B PT25A/PT34A/PT34A PT25B/PT34B/PT34B PT24A^/PT33A^/PT33A^ PT24B/PT33B/PT33B PT23A/PT32A/PT32A PT23B/PT32B/PT32B PT22A/PT31A/PT31A PT22B/PT31B/PT31B PT21A/PT30A/PT30A PT21B/PT30B/PT30B PT20A/PT29A/PT29A PT20B/PT29B/PT29B PT19A/PT28A/PT28A PT19B/PT28B/PT28B PT18A/PT27A/PT27A PT18B/PT27B/PT27B PT17A/PT26A/PT26A PT17B/PT26B/PT26B PT16A/PT25A/PT25A PT16B/PT25B/PT25B PT15A^/PT24A^/PT24A^ PT15B/PT24B/PT24B PT14A/PT23A/PT23A PT14B/PT23B/PT23B PT13A/PT22A/PT22A PT13B/PT22B/PT22B PT12A/PT21A/PT21A PT12B/PT21B/PT21B PT11A/PT20A/PT20A PT11B/PT20B/PT20B PT10A/PT19A/PT19A PT10B/PT19B/PT19B PT9A/PT18A/PT18A PT9B/PT18B/PT18B PT8A/PT17A/PT17A PT8B/PT17B/PT17B PT7A/PT16A/PT16A PT7B/PT16B/PT16B PT6A^/PT15A^/PT15A^ PT6B/PT15B/PT15B PT5A/PT5A/PT5A/ULC_GPLLT_FB_A PT5B/PT5B/PT5B/ULC_GPLLC_FB_A PT4A/PT4A/PT4A/ULC_GPLLT_IN_A PT4B/PT4B/PT4B/ULC_GPLLC_IN_A 4 XP2Bank3_8 XP2Bank3_9 XP2Bank3_10 XP2Bank3_11 XP2Bank3_12 XP2Bank3_13 XP2Bank3_14 XP2Bank3_15 XP2Bank3_16 XP2Bank3_17 XP2Bank3_18 XP2Bank3_19 XP2Bank3_20 XP2Bank3_21 XP2Bank0_10 XP2Bank0_11 XP2Bank0_12 XP2Bank0_13 XP2Bank0_14 XP2Bank0_15 XP2Bank0_16 XP2Bank0_17 XP2Bank0_18 XP2Bank0_19 XP2Bank0_20 XP2Bank0_21 XP2Bank0_22 XP2Bank0_23 C5 C4 A3 A4 C6 C7 H7 J7 A5 A6 B6 B7 D8 C8 XP2Bank3_30 XP2Bank3_31 XP2Bank3_32 XP2Bank3_33 XP2Bank3_34 XP2Bank3_35 XP2Bank3_36 XP2Bank3_37 XP2Bank3_38 XP2Bank3_39 XP2Bank3_40 XP2Bank3_41 XP2Bank3_42 XP2Bank3_43 XP2Bank0_32 XP2Bank0_33 XP2Bank0_34 XP2Bank0_35 XP2Bank0_36 XP2Bank0_37 XP2Bank0_38 XP2Bank0_39 XP2Bank0_40 XP2Bank0_41 XP2Bank0_42 XP2Bank0_43 XP2Bank0_44 XP2Bank0_45 XP2Bank0_46 XP2Bank0_47 XP2Bank0_48 XP2Bank0_49 XP2Bank0_50 XP2Bank0_51 B9 B10 A10 A11 D11 C11 G8 G9 B11 A12 B12 A13 E11 C12 F11 F12 B13 A14 F10 E10 V17 V18 K21 L21 M19 M20 M17 M16 M21 N21 M22 N22 P18 N18 P21 P20 P22 R22 R21 R20 N17 N16 P19 R19 T21 T20 T22 U22 P16 P17 R18 R17 U21 V22 U20 V20 R16 T17 Y20 Y19 W22 W20 W19 V19 U17 U18 XP2Bank3_[0..45] XP2Bank2_[0..45] XP2Bank1_[0..35] XP2Bank0_[0..51] XP2Bank3_28 XP2Bank3_29 XP2Bank0_30 XP2Bank0_31 D9 C9 XP2Bank3_26 XP2Bank3_27 XP2Bank0_28 XP2Bank0_29 A8 A9 A7 B8 XP2Bank3_24 XP2Bank3_25 XP2Bank3_6 XP2Bank3_7 XP2Bank0_8 XP2Bank0_9 F8 E8 XP2Bank3_22 XP2Bank3_23 XP2Bank3_4 XP2Bank3_5 XP2Bank0_6 XP2Bank0_7 D6 D5 XP2Bank0_26 XP2Bank0_27 XP2Bank3_2 XP2Bank3_3 XP2Bank0_4 XP2Bank0_5 F7 G7 XP2Bank0_24 XP2Bank0_25 XP2Bank3_44 XP2Bank3_45 XP2Bank0_2 XP2Bank0_3 A2 B3 E9 F9 XP2Bank3_0 XP2Bank3_1 XP2Bank0_0 XP2Bank0_1 F6 E6 3 3 LFXP217 FPBGA484 XP2Bank3_[0..45] XP2Bank2_[0..45] XP2Bank1_[0..35] XP2Bank0_[0..51] PR26A*/PR32A*/PR38A*/PCLKT3_0 PR26B*/PR32B*/PR38B/*PCLKC3_0 PR27A/PR33A/PR39A PR27B/PR33B/PR39B PR28A*/PR34A*/PR40A* PR28B*/PR34B*/PR40B* PR29A/PR35A/PR41A PR29B/PR35B/PR41B PR30A*^/PR36A*^/PR42A*^ PR30B*/PR36B*/PR42B* PR31A/PR37A/PR43A PR31B/PR37B/PR43B PR32A*/PR38A*/PR44A* PR32B*/PR38B*/PR44B* PR33A/PR39A/PR45A PR33B/PR39B/PR45B PR35A*/PR40A*/PR46A* PR35B*/PR40B*/PR46B* PR36A/PR41A/PR47A PR36B/PR41B/PR47B PR37A*/PR42A*/PR48A* PR37B*/PR42B*/PR48B* PR38A/PR43A/PR49A PR38B/PR43B/PR49B PR39A*^/PR44A*^/PR50A*^ PR39B*/PR44B*/PR50B* PR40A/PR45A/PR51A PR40B/PR45B/PR51B PR41A*/PR46A*/PR52A* PR41B*/PR46B*/PR52B* PR42A/PR47A/PR53A PR42B/PR47B/PR53B PR43A*/PR49A*/PR55A* PR43B*/PR49B*/PR55B* PR44A/PR50A/PR56A PR44B/PR50B/PR56B PR45A*/PR51A*/PR57A* PR45B*/PR51B*/PR57B* PR46A/PR52A/PR58A PR46B/PR52B/PR58B PR47A*/PR53A*^/PR59A*^ PR47B*/PR53B*/PR59B* NC/PR54A/PR60A NC/PR54B/PR60B PR48A/PR59B/PR69B/VREF1_3 PR48B/PR60B/PR70B/VREF2_3 U7C DI 2 BANK 3 2 Date: Size B Title Document Number XP2 Banks 0-3 5555 NE Moore Ct Hillsboro, OR 97124 Lattice Semiconductor Corporation PR24A/PR30A/PR36A/PCLKT2_0 PR24B/PR30B/PR36B/PCLKC2_0 PR23A*/PR29A*/PR35A* PR23B*/PR29B*/PR35B* PR22A/PR28A/PR34A PR22B/PR28B/PR34B PR21A*^/PR27A*^/PR33A*^ PR21B*/PR27B*/PR33B* PR20A/PR26A/PR32A PR20B/PR26B/PR32B PR19A*/PR25A*/PR31A* PR19B*/PR25B*/PR31B* PR18A/PR24A/PR30A PR18B/PR24B/PR30B PR17A*/PR23A*/PR29A* PR17B*/PR23B*/PR29B* PR16A/PR22A/PR28A PR16B/PR22B/PR28B PR15A*/PR21A*/PR27*A PR15B*/PR21B*/PR27B* PR14A/PR20A/PR26A PR14B/PR20B/PR26B PR13A*^/PR19A*^/PR25A*^ PR13B*/PR19B*/PR25B* PR12A/PR18A/PR24A PR12B/PR18B/PR24B PR11A*/PR17A*/PR23A* PR11B*/PR17B*/PR23B* PR10A/PR16A/PR22A PR10B/PR16B/PR22B PR9A*/PR15A*/PR21A* PR9B*/PR15B*/PR21B* PR8A/PR14A/PR19A PR8B/PR14B/PR19B PR7A*/PR13A*/PR18A* PR7B*/PR13B*/PR18B* PR6A/PR12A/PR17A PR6B/PR12B/PR17B PR5A*/PR11A*^/PR16A*^ PR5B*/PR11B*/PR16B* PR4A/PR10A/PR15A PR4B/PR10B/PR15B PR3A*/PR9A*/PR14A* PR3B*/PR9B*/PR14B* PR2A/PR4A/PR5A/VREF1_2 PR2B/PR4B/PR5B/VREF2_2 XP2Bank2_4 XP2Bank2_5 XP2Bank2_6 XP2Bank2_7 XP2Bank2_8 XP2Bank2_9 XP2Bank2_10 XP2Bank2_11 XP2Bank2_12 XP2Bank2_13 XP2Bank2_14 XP2Bank2_15 XP2Bank2_16 XP2Bank2_17 XP2Bank2_18 XP2Bank2_19 XP2Bank2_20 XP2Bank2_21 B20 C20 E20 D20 G15 G16 G17 H18 B21 C21 H20 G20 E19 F19 J20 H19 B22 C22 Sheet J22 K22 L19 L18 J16 K16 H21 J21 G22 H22 K18 L17 J17 K17 G21 F22 F20 F21 J19 J18 H16 H17 3 of XP2Bank2_44 XP2Bank2_45 XP2Bank2_42 XP2Bank2_43 XP2Bank2_40 XP2Bank2_41 XP2Bank2_38 XP2Bank2_39 XP2Bank2_36 XP2Bank2_37 XP2Bank2_34 XP2Bank2_35 XP2Bank2_32 XP2Bank2_33 XP2Bank2_30 XP2Bank2_31 XP2Bank2_28 XP2Bank2_29 XP2Bank2_26 XP2Bank2_27 XP2Bank2_24 XP2Bank2_25 XP2Bank2_22 XP2Bank2_23 XP2Bank2_2 XP2Bank2_3 F18 F17 D22 E22 XP2Bank2_0 XP2Bank2_1 F15 F16 1 1 20 Rev 000 A B C D Lattice Semiconductor LatticeXP2 Standard Evaluation Board User’s Guide Figure 6. LatticeXP2 Banks 0 to 3 BANK 2 BANK 0 BANK 1 20 A B C D V6 U6 R8 V8 W8 T8 T9 W5 W6 Y6 Y7 Y9 Y8 U9 U10 V9 W9 AA6 AA7 T10 V10 V11 W11 AA8 AA9 AB2 AB3 AA11 AA10 T11 U11 AB4 AB5 AB6 AB7 AA12 Y11 T12 T13 AB8 AB9 AB11 AB10 AB13 AB12 Y12 W12 AB14 AB15 XP2Bank5_2 XP2Bank5_3 XP2Bank5_4 XP2Bank5_5 XP2Bank5_52 XP2Bank5_6 XP2Bank5_7 XP2Bank5_8 XP2Bank5_9 XP2Bank5_10 XP2Bank5_11 XP2Bank5_12 XP2Bank5_13 XP2Bank5_14 XP2Bank5_15 XP2Bank5_16 XP2Bank5_17 XP2Bank5_18 XP2Bank5_19 XP2Bank5_20 XP2Bank5_21 XP2Bank5_22 XP2Bank5_23 XP2Bank5_24 XP2Bank5_25 XP2Bank5_26 XP2Bank5_27 XP2Bank5_28 XP2Bank5_29 XP2Bank5_30 XP2Bank5_31 XP2Bank5_32 XP2Bank5_33 XP2Bank5_34 XP2Bank5_35 XP2Bank5_36 XP2Bank5_37 XP2Bank5_38 XP2Bank5_39 XP2Bank5_40 XP2Bank5_41 XP2Bank5_42 XP2Bank5_43 XP2Bank5_44 XP2Bank5_45 XP2Bank5_46 XP2Bank5_47 XP2Bank5_48 XP2Bank5_49 XP2Bank5_50 XP2Bank5_51 5 U7 U8 W4 Y5 XP2Bank5_0 XP2Bank5_1 5 LFXP217 FPBGA484 PB28A/PB37A/PB37A/PCLKT5_0 PB28B/PB37B/PB37B/PCLKC5_0 PB27A/PB36A/PB36A PB27B/PB36B/PB36B PB26A/PB35A/PB35A PB26B/PB35B/PB35B PB25A/PB34A/PB34A PB25B/PB34B/PB34B PB24A^/PB33A^/PB33A^ PB24B/PB33B/PB33B PB23A/PB32A/PB32A PB23B/PB32B/PB32B PB22A/PB31A/PB31A PB22B/PB31B/PB31B PB21A/PB30A/PB30A PB21B/PB30B/PB30B PB20A/PB29A/PB29A PB20B/PB29B/PB29B PB19A/PB28A/PB28A PB19B/PB28B/PB28B PB18A/PB27A/PB27A PB18B/PB27B/PB27B PB17A/PB26A/PB26A PB17B/PB26B/PB26B PB16A/PB25A/PB25A PB16B/PB25B/PB25B PB15A^/PB24A^/PB24A^ PB15B/PB24B/PB24B PB14A/PB23A/PB23A PB14B/PB23B/PB23B PB13A/PB22A/PB22A PB13B/PB22B/PB22B PB12A/PB21A/PB21A PB12B/PB21B/PB21B PB11A/PB20A/PB20A PB11B/PB20B/PB20B PB10A/PB19A/PB19A PB10B/PB19B/PB19B PB9A/PB18A/PB18A PB9B/PB18B/PB18B PB8A/PB17A/PB17A PB8B/PB17B/PB17B PB7A/PB16A/PB16A PB7B/PB16B/PB16B PB6A^/PB15A^/PB15A^ PB6B/PB15B/PB15B NC/PB8A/PB8A PB5A/PB5A/PB5A/LLC_PLLT_FB_A PB5B/PB5B/PB5B/LLC_PLLC_FB_A PB4A/PB4A/PB4A/LLC_PLLT_IN_A PB4B/PB4B/LLC_PLLC_IN_A PB3A/PB3A/PB3A/VREF1_5 PB3B/PB3B/PB3B/VREF2_5 U7B DI PB46A/PB64A/PB72A/VREF1_4 PB46B/PB64B/PB72B/VREF2_4 4 IO Order = 17/30/40 * = LVDS I/O ^ = DQS input [ = DQS reach PB29A/PB38A/PB38A/PCLKT4_0 PB29B/PCLKC4_0 PB30A/PB39A/PB39A PB30B/PB39B/PB39B PB31A/PB40A/PB40A PB31B/PB40B/PB40B PB32A/PB41A/PB41A PB32B/PB41B/PB41B PB33A^/PB42A^/PB42A^ PB33B/PB42B/PB42B PB34A/PB43A/PB43A PB34B/PB43B/PB43B PB35A/PB44A/PB44A PB35B/PB44B/PB44B PB36A/PB45A/PB45A PB36B/PB45B/PB45B PB37A/PB46A/PB46A PB37B/PB46B/PB46B PB38A/PB47A/PB47A PB38B/PB47B/PB47B PB39A/PB48A/PB48A PB39B/PB48B/PB48B PB40A/PB49A/PB49A PB40B/PB49B/PB49B PB41A/PB50A/PB50A PB41B/PB50B/PB50B PB42A^/PB51A^/PB51A^ PB42B/PB51B/PB51B PB43A/PB52A/PB52A PB43B/PB52B/PB52B NC/PB59A/PB67A NC/PB59B/PB67B PB44A/PB62A/PB70A/LRC_GPLLT_IN_A PB44B/PB62B/PB70B/LRC_GPLLC_IN_A PB45A/PB63A/PB71A/LRC_GPLLT_FB_A PB45B/PB63B/PB71B/LRC_GPLLC_FB_A 4 F1 G1 G3 G2 H1 H2 XP2Bank7_10 XP2Bank7_11 XP2Bank7_12 XP2Bank7_13 XP2Bank7_14 XP2Bank7_15 XP2Bank7_16 XP2Bank7_17 XP2Bank7_18 XP2Bank7_19 XP2Bank7_20 XP2Bank7_21 XP2Bank7_22 XP2Bank7_23 XP2Bank7_24 XP2Bank7_25 XP2Bank4_8 XP2Bank4_9 XP2Bank4_10 XP2Bank4_11 XP2Bank4_12 XP2Bank4_13 XP2Bank4_14 XP2Bank4_15 XP2Bank4_16 XP2Bank4_17 XP2Bank4_18 XP2Bank4_19 XP2Bank4_20 XP2Bank4_21 XP2Bank4_22 XP2Bank4_23 Y22 Y21 AA22 AA21 U14 U15 W14 V14 AB20 AA20 AA16 AA17 V13 U13 AB16 AB17 Y14 AA13 V12 U12 AB18 AB19 AA14 AA15 XP2Bank4_34 XP2Bank4_35 XP2Bank4_32 XP2Bank4_33 XP2Bank4_30 XP2Bank4_31 XP2Bank4_28 XP2Bank4_29 XP2Bank4_26 XP2Bank4_27 3 XP2Bank7_[0..45] XP2Bank6_[0..45] XP2Bank5_[0..52] XP2Bank4_[0..37] XP2Bank7_44 XP2Bank7_45 XP2Bank7_42 XP2Bank7_43 XP2Bank7_40 XP2Bank7_41 XP2Bank7_38 XP2Bank7_39 XP2Bank7_36 XP2Bank7_37 XP2Bank7_34 XP2Bank7_35 XP2Bank7_32 XP2Bank7_33 XP2Bank7_30 XP2Bank7_31 XP2Bank7_28 XP2Bank7_29 XP2Bank7_26 XP2Bank7_27 F3 F2 XP2Bank7_8 XP2Bank7_9 XP2Bank4_6 XP2Bank4_7 T16 U16 W15 V15 XP2Bank4_24 XP2Bank4_25 D4 D3 XP2Bank7_6 XP2Bank7_7 XP2Bank4_36 XP2Bank4_37 R15 AB21 T14 T15 E3 E1 XP2Bank7_4 XP2Bank7_5 XP2Bank4_4 XP2Bank4_5 Y16 Y15 LFXP217 FPBGA484 PL24A/PL30A/PL36A/PCLKT7_0 PL24B/PL30B/PL36B/PCLKC7_0 PL23A*/PL29A*/PL35A*/SI PL23B*/PL29B*/PL35B*/INITN PL22A/PL28A/PL34A/CCLK PL22B/PL28B/PL34B/SO PL21A*^/PL27A*^/PL33A*^ PL21B*/PL27B*/PL33B* PL20A//PL26A/PL32A/CSSPISN PL20B/PL26B/PL32B/CSSPIN PL19A*/PL25A*/PL31A*/CFG1 PL19B*/PL25B*/PL31B* PL18A/PL24A/PL30A/PROGRAMN PL18B/PL24B/PL30B/DONE PL17A*/PL23A*/PL29A* PL17B*/PL23B*/PL29B* PL16A/PL22A/PL28A PL16B/PL22B/PL28B PL15A*/PL21A*/PL27A* PL15B*/PL21B*/PL27B* PL14A/PL20A/PL26A PL14B/PL20B/PL26B PL13A*^/PL19A*^/PL25A*^ PL13B*/PL19B*/PL25B* PL12A/PL18A/PL24A PL12B/P18B/PL24B PL11A*/PL17A*/PL23A* PL11B*/PL17B*/PL23B* PL10A/PL16A/PL22A PL10B/PL16B/PL22B PL9A*/PL15A*/PL21A* PL9B*/PL15B*/PL21B* PL8A/PL14A/PL19A PL8B/PL14B/PL19B PL7A*/PL13A*/PL18A* PL7B*/PL13B*/PL18B* PL6A/PL12A/PL17A PL6B/PL12B/PL17B PL5A*^/PL11A*^/PL16A*^ PL5B*/PL11B*/PL16B* PL4A/PL10A/PL15A PL4B/PL10B/PL15B PL3A*/PL9A*/PL14A* PL3B*/PL9B*/PL14B* PL2A/PL4A/PL5A/VREF1_7 PL2B/PL4B/PL5B/VREF2_7 U7A DI XP2Bank7_[0..45] XP2Bank6_[0..45] XP2Bank5_[0..52] XP2Bank4_[0..37] L3 L4 L5 L6 K6 K7 M1 M2 L1 L2 J3 J4 J6 K5 K1 K2 J1 J2 H5 J5 G6 H6 H3 H4 F5 F4 E4 E5 C1 D1 B1 C2 XP2Bank7_2 XP2Bank7_3 XP2Bank4_2 XP2Bank4_3 C3 B2 XP2Bank7_0 XP2Bank7_1 XP2Bank4_0 XP2Bank4_1 W17 W18 Y17 Y18 3 2 2 Date: Size B Title Document Number XP2 Banks 4-7 5555 NE Moore Ct Hillsboro, OR 97124 Lattice Semiconductor Corporation PL26A*/P32A*/PL38A*/PCLKT6_0 PL26B*/PL32B*/PL38B*/PCLKC6_0 PL27A/PL33A/PL39A PL27B/PL33B/PL39B PL28A*/PL34A*/PL40A* PL28B*/PL34B*/PL40B* PL29A/PL35A/PL41A PL29B/PL35B/PL41B PL30A*^/PL36A*^/PL42A*^ PL30B*/PL36B*/PL42B* PL31A/PL37A/PL43A PL31B/PL37B/PL43B PL32A*/PL38A*/PL44A* PL32B*/PL38B*/PL44B* PL33A/PL39A/PL45A PL33B/PL39B/PL45B PL35A*/PL40A*/PL46A* PL35B*/PL40B*/PL46B* PL36A/PL41A/PL47A PL36B/PL41B/PL47B PL37A*/PL42A*/PL48A* PL37B*/PL42B*/PL48B* PL38A/PL43A/PL49A PL38B/PL43B/PL49B PL39A*^/PL44A*^/PL50A*^ PL39B*/PL44B*/PL50B* PL40A/PL45A/PL51A PL40B/PL45B/PL51B PL41A*/PL46A*/PL52A* PL41B*/PL46B*/PL52B* PL42A/PL47A/PL53A PL42B/PL47B/PL53B PL43A*/PL49A*/PL55A* PL43B*/PL49B*/PL55B* PL44A/PL50A/PL56A PL44B/PL50B/PL56B PL45A*/PL51A*/PL57A* PL45B*/PL51B*/PL57B* PL46A/PL52A/PL58A PL46B/PL52B/PL58B PL47A*/PL53A*^/PL59A*^ PL47B*/PL53B*/PL59B* PL48A/PL53A/PL60A PL48B/PL53B/PL60B PL49A/PL60A/PL70A/VREF1_6 PL49B/PL60B/PL70B/VREF2_6 XP2Bank6_4 XP2Bank6_5 XP2Bank6_6 XP2Bank6_7 XP2Bank6_8 XP2Bank6_9 XP2Bank6_10 XP2Bank6_11 XP2Bank6_12 XP2Bank6_13 XP2Bank6_14 XP2Bank6_15 XP2Bank6_16 XP2Bank6_17 XP2Bank6_18 XP2Bank6_19 T3 U3 U4 U5 R7 R6 U2 V3 Y3 W3 R3 R4 R5 P6 Sheet P1 R1 M6 M7 M4 M5 M3 N2 T1 U1 N5 N6 P2 P3 V1 W1 Y1 AA1 N7 P7 P4 P5 AA2 Y2 4 of XP2Bank6_44 XP2Bank6_45 XP2Bank6_42 XP2Bank6_43 XP2Bank6_40 XP2Bank6_41 XP2Bank6_38 XP2Bank6_39 XP2Bank6_36 XP2Bank6_37 XP2Bank6_34 XP2Bank6_35 XP2Bank6_32 XP2Bank6_33 XP2Bank6_30 XP2Bank6_31 XP2Bank6_28 XP2Bank6_29 XP2Bank6_26 XP2Bank6_27 XP2Bank6_24 XP2Bank6_25 XP2Bank6_22 XP2Bank6_23 XP2Bank6_20 XP2Bank6_21 XP2Bank6_2 XP2Bank6_3 AA3 Y4 R2 T2 XP2Bank6_0 XP2Bank6_1 V4 V5 T6 T7 1 1 20 Rev 000 A B C D Lattice Semiconductor LatticeXP2 Standard Evaluation Board User’s Guide Figure 7. LatticeXP2 Banks 4 to 7 BANK 6 BANK 7 BANK 4 BANK 5 A B C D GND CSSPIN SO CFG0 CFG1 TOE TP TP8 TP TP11 XP2_CFG7 TP TP5 XP2_CFG8 2 4 6 5 1 2 3 4 U5 16Mbit_SPI DI SOIC-8 /S Q /W VSS PU1 DONE INITN PROGRAMN TOE VCC /HOLD C D GND CCLK DONE INITn XP2_CFG6 XP2_CFG9 4.7K SM/R_0402 4 TP6 TP TP7 TP XP2_CFG[0..10] 2 SW4 3 PUSHBUTTON DI SMT_SW 1 D11 YELLOW_LED DI SM/D_0603 4 HD10x1 CON10 DNI J11 1 2 3 4 5 6 7 8 9 10 +3_3V XP2_CFG6 XP2_CFG3 XP2_CFG4 XP2_CFG8 XP2_CFG9 XP2_CFG10 XP2_CFG5 TP9 TP XOBank1_[0..28] TMS GND TCK DONE INITn +3.3V TDO TDI PROGRAMn PROGRAMn TP27 TP PROGRAMn R98 470 DI SM/R_0402 PROGRAMN CCLK SI CL10 XP2 SPI Slave header R64 DI CCLK SI +3_3V +3.3V SO SI CSSPISN PROGRAMn 8 7 6 5 DI JBLOCK JB4 XP2_CFG[0..10] DI DI XP2_CFG0 XP2_CFG1 XP2_CFG2 XP2_CFG3 XP2_CFG4 XP2_CFG5 JBLOCK JB3 INITn TP76 TP JBLOCK JB2 INITN INITn R99 470 DI SM/R_0402 +3_3V R62 10K_1% DI SM/R_0402 Q3 BSS138LT1 DI SOT-23 D12 RED_LED DI SM/D_0603 10K SM/R_0402 CSSPIN SO R63 DI R56 4.7K DI SM/R_0402 DONE TP75 TP C26 0.1uF DI SM/C_0402 +3_3V 1 3 5 R55 4.7K DI SM/R_0402 DONE DONE J15 HEADER_3X2 DI Header_3x2 VCCIO7 Q2 BSS138LT1 DI SOT-23 D10 GREEN_LED DI SM/D_0603 CL8 DON_0 R97 470 DI SM/R_0402 CL9 DON_1 +3_3V XOBank1_[0..28] 3 1 2 3 4 5 6 7 8 9 10 XP2_JTAG2 XP2_CFG3 XP2_CFG4 XP2_JTAG3 TDO_CABLE XP2_JTAG0 PROGRAMN +3_3V TCK Pulldown Open: TCK float Shunt: TCK pulled low PROGRAMn Chain Open: PGM Local Shunt: Local & Offboard INITn Chain Open: INITn Local Shunt: Local & Offboard HD10x1 CON10 DI J34 C5 DNI C3 DNI R18 DI R20 DI R21 DI R19 DI J32 HEADER_2 DI HDR2X1 DI JBLOCK JB7 J30 HEADER_2 DI HDR2X1 INIT_CHN 0.1uF SM/C_0603 0.1uF SM/C_0603 TDO Chaining 1-2: TDO Local 2-3: Local & Offboard C4 DNI C6 DNI 2 R101 4.7K DI SM/R_0402 TDO_CHAIN XP2_JTAG1 PROGRAMn_CHN 0.1uF SM/C_0603 0.1uF SM/C_0603 0 SM/R_0603 0 SM/R_0603 0 SM/R_0603 0 SM/R_0603 J29 HEADER_3 JBLOCK DI HD3x1 DI JB5 XOBank1_23 XOBank1_24 XOBank1_17 XOBank1_18 XP2 JTAG header 3 1 2 4 1 2 3 1 2 5 TCK_DN 21 2 J31 HEADER_2 DI HDR2X1 1 2 CON10 HD10x1 DI TMS GND TCK DONE INITn_OB NC TDO_OB TDI_OB PROGRAMn_OB Date: Size B Title Document Number XP2 Programming Interfaces 5555 NE Moore Ct Hillsboro, OR 97124 1 Sheet Multi-board JTAG header J33 5 of XP2_JTAG[0..3] FPBGA484_SKT DNI FPBGA484 XU1 XP2_JTAG[0..3] Lattice Semiconductor Corporation 1 2 3 4 5 6 7 8 9 10 XP2_TMS XP2_JTAG3 XP2_TDI XP2_JTAG0 XP2_TDO TDO_CABLE XP2_TCK XP2_JTAG2 1 20 Rev 000 A B C D Lattice Semiconductor LatticeXP2 Standard Evaluation Board User’s Guide Figure 8. LatticeXP2 Programming Interfaces 22 A B C D XP2_VCCAUX XP2_VCORE +1_2V +3_3V VADJ XO_VCCIO[0..7] XP2_VCCIO[0..7] 5 5 +3.3V VADJ VIn XP2_VCCAUX XP2_VCORE +1_2V +3_3V VADJ XO_VCCIO[0..7] EXT EXT XP2_VCCIO[0..7] EXT_IN VADJ +3_3V TP14 TP TP15 TP 2 4 6 +1_2V DI JBLOCK JB1 1 3 5 4 R12 .010 DI 16mm J12 HEADER_3X2 DI Header_3X2 +3_3V R17 .010 DI 16mm 4 C42 0.1uF DI SM/C_0402 C38 0.01uF DI SM/C_0402 C41 0.01uF DI SM/C_0402 C72 0.01uF DI SM/C_0402 C58 0.01uF DI SM/C_0402 C34 0.01uF DI SM/C_0402 C61 0.01uF DI SM/C_0402 C40 0.01uF DI SM/C_0402 C85 0.01uF DI SM/C_0402 C56 0.1uF DI SM/C_0402 C55 0.01uF DI SM/C_0402 C70 0.01uF DI SM/C_0402 C60 0.1uF DI SM/C_0402 C79 0.1uF DI SM/C_0402 C51 0.01uF DI SM/C_0402 C44 0.01uF DI SM/C_0402 XP2 VCCAUX BYPASS C67 0.1uF DI SM/C_0402 XP2_VCORE XP2 VCORE BYPASS C39 0.1uF DI SM/C_0402 XP2_VCCIO6 C75 0.1uF DI SM/C_0402 C66 0.1uF DI SM/C_0402 C33 0.1uF DI SM/C_0402 C77 0.1uF DI SM/C_0402 C76 0.1uF DI SM/C_0402 C74 0.1uF DI SM/C_0402 XP2_BYPASS XP2 BYPASS CAPS 3 3 C65 0.1uF DI SM/C_0402 C62 0.01uF DI SM/C_0402 C32 0.01uF DI SM/C_0402 C59 0.01uF DI SM/C_0402 C43 0.01uF DI SM/C_0402 C52 0.01uF DI SM/C_0402 C53 0.01uF DI SM/C_0402 C31 0.01uF DI SM/C_0402 C64 0.01uF DI SM/C_0402 C73 0.01uF DI SM/C_0402 C68 0.01uF DI SM/C_0402 C35 0.1uF DI SM/C_0402 C78 0.1uF DI SM/C_0402 C63 0.1uF DI SM/C_0402 C69 0.1uF DI SM/C_0402 C54 0.1uF DI SM/C_0402 C36 0.1uF DI SM/C_0402 C71 0.1uF DI SM/C_0402 C57 0.1uF DI SM/C_0402 C37 0.1uF DI SM/C_0402 2 2 XP2_BYPASS XP2_BYPASS XP2_BYPASS XP2_BYPASS XP2_BYPASS XP2_BYPASS XP2_BYPASS XP2_BYPASS Date: Size B Title Document Number XP2 Bypass Capacitors 5555 NE Moore Ct Hillsboro, OR 97124 Lattice Semiconductor Corporation XP2_VCCIO7 XP2_VCCAUX XP2_VCCIO0 XP2_VCCIO1 XP2_VCCIO2 XP2_VCCIO3 XP2_VCCIO4 XP2_VCCIO5 1 Sheet 1 6 of 20 Rev 000 A B C D Lattice Semiconductor LatticeXP2 Standard Evaluation Board User’s Guide Figure 9. LatticeXP2 Bypass Capacitors 23 A B C D POT[0..2] DA[0..5] CLK5 CLK4 CLK3 CLK2 AD_CTRL[0..6] AD_D[0..11] RS232_[0..3] SEG[0..7] POT[0..2] DA[0..5] AD_CTRL[0..6] AD_D[0..11] RS232_[0..3] SEG[0..7] 0 SM/R_0603 5 R89 100 DNI SM/R_0603 R87 0 DNI SM/R_0603 R86 DNI 1 1 0 SM/R_0603 GND GND GND GND 2 3 4 5 S GND GND GND GND 2 3 4 5 J27 SMA_Connector DNI th_sma S GND GND GND GND 2 3 4 5 S GND GND GND GND 2 3 4 5 J25 SMA_Connector DNI th_sma S J24 SMA_Connector DNI th_sma 1 1 Page 8 J26 SMA_Connector DNI th_sma Peripherals1 H1 R90 100 DNI SM/R_0603 R91 0 DNI SM/R_0603 R88 DNI POT[0..2] DA[0..5] AD_CTRL[0..6] AD_D[0..11] RS232_[0..3] SEG[0..7] 5 TP16 TP TP73 TP TP42 TP TP40 TP GND (K22) N GND (J22) P GND (L21) N GND (K21) P 4 SWITCH[0..7] 4 LVDS_C0 LVDS_T0 VCCIO6 R73 DNI 0 SM/R_0603 Peripherals2 VCCIO6 SWITCH[0..7] 1 2 3 4 5 6 7 DIP14 DI DIP14 XU1 R83 OSC_EN DI C50 DI 1 1 GND GND GND GND S 4.7K SM/R_0402 14 13 12 11 10 9 8 2 3 4 5 CLK 2 3 4 5 3 R84 DI R85 DI CLK[0..7] GND GND GND GND 1 2 VCC OUT CLK0 CLK1 33MHz DI OSC_TH EN GND Y1 CLK[0..7] GND (Y5) N GND (W4) P LCD[0..10] LVDS_C[0..3] LVDS_T[0..3] CLK[0..7] CF[0..45] 33 SM/R_0402 PLL_IN PCLK_IN 33 SM/R_0402 TP26 TP TP34 TP LCD[0..10] LVDS_C[0..3] J4 SMA_Connector DNI th_sma S CLK[0..7] CF[0..45] LVDS_T[0..3] J3 SMA_Connector DNI th_sma Page 9 0.1uF +3_3V SM/C_0402 R70 100 DNI SM/R_0603 R79 0 DNI SM/R_0603 SWITCH[0..7] H2 3 4 3 (B13) PCLK (A2) PLL LCD[0..10] LVDS_C[0..3] LVDS_T[0..3] CLK[0..7] CF[0..45] 2 2 VCCIO6 R36 DI R60 DI 1 R61 DI 1 Date: Size B Title Document Number Peripherals and Clock inputs 5555 NE Moore Ct Hillsboro, OR 97124 Lattice Semiconductor Corporation PB[0..1] PB1 1 Sheet (W1) C21 1uF DI SM/C_0603 PB[0..1] 10K SM/R_0402 2 SW3 3 PUSHBUTTON DI SMT_SW 4 VCCIO6 LED7 LED6 LED5 LED4 LED3 LED2 LED1 LED0 (V1) C20 1uF DI SM/C_0603 PB0 GREEN_LED SM/D_0603 GREEN_LED SM/D_0603 GREEN_LED SM/D_0603 GREEN_LED SM/D_0603 GREEN_LED SM/D_0603 GREEN_LED SM/D_0603 GREEN_LED SM/D_0603 GREEN_LED SM/D_0603 10K SM/R_0402 2 SW2 3 PUSHBUTTON DI SMT_SW 4 VCCIO6 D2 DI D3 DI D4 DI D5 DI D6 DI D7 DI D8 DI D9 DI LED[0..7] 470 SM/R_0402 CL7 470 SM/R_0402 CL6 470 SM/R_0402 CL5 R38 DI R37 DI 470 SM/R_0402 CL4 R39 DI 470 SM/R_0402 CL3 470 SM/R_0402 CL2 R41 DI R40 DI 470 SM/R_0402 CL1 470 SM/R_0402 CL0 R46 DI R47 DI LED[0..7] +3_3V 1 7 of (J2) (J1) (K2) (K1) (M2) (M1) (L4) (L3) 20 Rev 000 A B C D Lattice Semiconductor LatticeXP2 Standard Evaluation Board User’s Guide Figure 10. Peripherals and Clock Inputs A B C D +3_3V C98 0.1uF DI SM/C_0402 C1010.1uF DI SM/C_0402 5 DI JB11 DI JB10 DI U12 DI VCC C1+ C1C2+ C2V+ V- T1IN T2IN R1IN R2IN C97 0.1uF DI SM/C_0402 16 13 8 TP MAX3232 TSSOP16 GND T1OUT T2OUT R1OUT R2OUT TP74 15 14 7 12 9 DI L3 DI 4 TP72 J19 DI HEADER_3 HD3x1 TXD Select TXD 1-2: DB9 pin 2 2-3: DB9 pin 3 J17 DI X3 X2 X7 X8 HEADER_3 HD3x1 J22 DI HEADER_3 HD3x1 RTS# 1-2: DB9 pin 8 2-3: DB9 pin 7 GND TP HEADER_3 HD3x1 RXD Select RXD 1-2: DB9 pin 3 2-3: DB9 pin 2 J18 DI POT[0..2] 3 1 2 3 4 1 6 2 7 3 8 4 9 5 L1 DI 3 Ferrite_bead BD0603 J16 DB9-Female DI DB9 U9 8 7 6 5 POT_OUT POT_CSn +3_3V C83 0.1uF SM/C_0402 DI SEG4 SEG5 SEG0 AIN2 DI JBLOCK JB12 AIN2 POT2 J20 HEADER_2 DI HDR2X1 POT_OUT C82 10uF SM/C_0805 DI +3_3A CLK VDD U/Dn CSn B1 A1 GND W1 AD5220 DI SOIC8 RS-232 POT0 POT_CLK POT1 POT_U_Dn C88 0.1uF DI SM/C_0402 POT[0..2] /RTS Select +3_3V CTS# 1-2: DB9 pin 7 2-3: DB9 pin 8 0.1uF SM/C_0402 Ferrite_bead BD0603 /CTS Select C102 DI AD_CTRL1 AD_CTRL0 AD_CTRL2 AD_CTRL3 AD_CTRL4 AD_CTRL5 AD_CTRL6 AD_D0 AD_D1 AD_D2 AD_D3 AD_D4 HV_TXD HV_RTS_N JBLOCK JBLOCK JBLOCK JBLOCK JB9 JB8 AGND +3_3A 4 DCE (default) -> shunt pin 1-2 of all headers DTE ->shunt pin 2-3 of all headers +3_3V RS232_3 C100 0.1uF DI SM/C_0402 0 LV_TXD 11 LV_RTS_N 10 SM/R_0402 C1+ 1 C13 C2+ 4 C25 V+ 2 V6 R96 DI C99 0.1uF DI SM/C_0402 0 SM/R_0402 R94 DI RS232_2 LV_RXD HV_RXD 0 SM/R_0402 28 27 26 25 24 23 22 21 20 19 18 17 16 15 TP TP47 VANA VDIG A1 A0 CLK BUSYN WRN CSN RDN DB0 DB1 DB2 DB3 DB4 HV_CTS_N LV_CTS_N ADS7842 DI SSOP28 AIN0 AIN1 AIN2 AIN3 VREF AGND DB11 DB10 DB9 DB8 DB7 DB6 DB5 DGND U13 R95 DI 1 2 3 4 5 6 7 8 9 10 11 12 13 14 RS232_1 RS232_[0..3] TP TP38 C103 2.2uF DI SM/C_0402 AD_D11 AD_D10 AD_D9 AD_D8 AD_D7 AD_D6 AD_D5 AIN0 AIN1 AIN2 AIN3 0 SM/R_0402 GND TP TP43 TP TP44 TP TP46 R100 DI RS232_[0..3] AIN3 TP45 TP AIN0 AIN1 AIN2 RS232_0 R22 25K DI POT +3_3V 5 3 2 1 AD_D[0..11] AD_CTRL[0..6] 3 2 1 1 2 3 24 1 2 3 1 2 AD_D[0..11] AD_CTRL[0..6] R52 DI R42 DI R48 DI VOUT1 VOUT0 VOUT3 VOUT2 TP22 TP23 TP19 TP21 TP 2 C84 0.1uF SM/C_0402 DI 470 SM/R_0402 470 SM/R_0402 470 SM/R_0402 AGND +3_3A S_E 1 2 3 4 5 6 7 U2 1 2 3 4 5 6 7 8 U10 14 13 12 11 10 9 8 GND Date: Size B Title Document Number D/A, A/D, 7 Segment, RS232 5555 NE Moore Ct Hillsboro, OR 97124 Lattice Semiconductor Corporation S_D S_G S_C S_DP S_B 16 15 14 13 12 11 10 9 TP TP20 RESETSEL RSTn LOADREGn LDACn CSn CLK SDI GND SEG[0..7] DAC7617 DI SOIC16 VDD VOUTD VOUTC VREFL VREFH VOUTB VOUTA AGND Seven_Segment_Display DI DIP14 +3_3V SEG[0..7] AIN2 VOUTB VOUTA VOUTD VOUTC S_A S_F TP24 C89 0.1uF DI SM/C_0402 TP TP TP TP 2 R54 DI R53 DI R51 DI R50 DI R49 DI 1 Sheet 8 470 SM/R_0402 SEG3 470 SM/R_0402 SEG7 470 SM/R_0402 SEG2 470 SM/R_0402 SEG6 of DA[0..5] 470 SM/R_0402 SEG1 DA0 DA1 DA2 DA3 DA4 DA5 1 20 Rev 000 DA[0..5] A B C D Lattice Semiconductor LatticeXP2 Standard Evaluation Board User’s Guide Figure 11. D/A, A/D, 7-Segment and RS232 A B C D CF[0..45] GND TP +3_3V CF35 CF36 CF37 CF38 CF39 CF40 CF41 CF42 CF43 CF44 CF45 CF11 CF12 CF13 CF14 CF15 CF16 CF17 CF18 CF19 CF20 CF21 CF22 CF23 CF24 CF25 CF26 CF27 CF28 CF29 CF30 CF31 CF32 CF33 CF34 CF0 CF1 CF2 CF3 CF4 CF5 CF6 CF7 CF8 CF9 CF10 TP3 5 C30 10uF DI SM/C_0805 CF[0..45] 5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 J14 CF Socket (Normal) DI CF_2X30 VIN 3 R15 100 POT DI (T21) (R22) (R20) (P21) (N22) R16 20K POT DI 2 GND D3 D4 D5 D6 D7 CE1N/CE1N/CS0N A10 OEN/OEN/ATA_SELN A9 A8 A7 VCC A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 WP/IOIS16N/IOCS16N CD2N CD1N D11 D12 D13 D14 D15 CE2N/CE2N/CS1N VS1N IORDN IOWRN WEN READY/IREQN/INTRQ VCC CSELN VS2N RESET/RESET/RESETN WAITN/WAITN/IORDY INPACKN/DMARQ REGN/DMACKN BVD2/SPKRN/DASPN BVD1/STSCHGN/PDIAGN D8 D9 D10 GND 1 25 3 4 LCD0 LCD1 LCD2 LCD3 LCD4 1 100 SM/R_0603 0 SM/R_0603 R65 DNI R67 DNI 1 1 S 2 3 4 5 GND GND GND GND 2 3 4 5 GND GND GND GND 2 3 4 5 S 2 4 6 8 10 12 14 16 18 VIN GND GND GND GND 2 3 4 5 J10 SMA_Connector DNI th_sma S J6 SMA_Connector DNI th_sma LCD_Connector DI HD9x2 1 3 5 7 9 11 13 15 17 J13 GND GND GND GND J2 SMA_Connector DNI th_sma S LVDS_T[0..3] LVDS_C[0..3] 1 1 J1 SMA_Connector DNI th_sma LCD[0..10] 0 SM/R_0603 LCD[0..10] CONTRAST LCD_RW LCD_D0 LCD_D2 LCD_D4 LCD_D6 0 SM/R_0603 R68 DNI BACKLIGHT LVDS_C2 LVDS_T2 R69 DNI R66 100 DNI SM/R_0603 R74 0 DNI SM/R_0603 LVDS_T[0..3] LVDS_C[0..3] LVDS_C3 LVDS_T3 4 LCD_RS LCD_E LCD_D1 LCD_D3 LCD_D5 LCD_D7 3 TP10 TP GND (P3) N TP28 TP GND (P2) P TP32 TP GND (R1) N TP68 TP GND (P1) P 3 LCD5 LCD6 LCD7 LCD8 LCD9 LCD10 (U22) (T22) (T20) (R21) (P22) (P20) CLK[7..0] VCCIO6 (AA3) (AA2) (AA1) (Y4) (Y3) (Y2) (Y1) (W3) 2 3 4 3 4 J7 DNI J8 DNI 10K SM/R_0402 10K SM/R_0402 10K SM/R_0402 10K SM/R_0402 SWITCH0 SWITCH1 SWITCH2 SWITCH3 SWITCH4 SWITCH5 SWITCH6 SWITCH7 SWITCH[0..7] R28 DI R29 DI R30 DI R31 DI 100 SM/R_0603 0 SM/R_0603 0 SM/R_0603 0 SM/R_0603 100 SM/R_0603 R71 DNI VCCIO6 2 0 SM/R_0603 R75 DNI R76 DNI R77 DNI R72 DNI R78 DNI SWITCH[0..7] LVDS_T1 LVDS_C1 CLK6 CLK7 CLK[7..0] R32 DI R33 DI R34 DI R35 DI 10K SM/R_0402 10K SM/R_0402 10K SM/R_0402 10K SM/R_0402 TP54 TP TP64 TP Date: Size B Title Document Number 16 15 14 13 12 11 10 9 DI 861milX425mil SW DIP-8 SW1 1 Sheet Compact Flash, LVDS, Switches, and LCD 5555 NE Moore Ct Hillsboro, OR 97124 1 2 3 4 5 6 7 8 (T2) P GND (R2) P (U1) P GND (T1) P Lattice Semiconductor Corporation 1 2 HEADER_2X2 Header_2X2 1 2 HEADER_2X2 Header_2X2 1 9 of 20 Rev 000 A B C D Lattice Semiconductor LatticeXP2 Standard Evaluation Board User’s Guide Figure 12. Compact Flash, LVDS, Switches and LCD 2 26 A B C D SRAM_D[0..31] 5 SRAM_D[0..31] SRAM_A[0..17] SRAM_BE[0..3] SRAM_CE[0..1] SRAM_WE SRAM_OE GND GND +3_3V TP TP13 TP TP25 4 SRAM_D20 SRAM_D21 SRAM_D22 SRAM_D23 SRAM_WE SRAM_A5 SRAM_A6 SRAM_A7 SRAM_A8 SRAM_A9 SRAM_A0 SRAM_A1 SRAM_A2 SRAM_A3 SRAM_A4 SRAM_CE1 SRAM_D16 SRAM_D17 SRAM_D18 SRAM_D19 SRAM_D4 SRAM_D5 SRAM_D6 SRAM_D7 SRAM_WE SRAM_A5 SRAM_A6 SRAM_A7 SRAM_A8 SRAM_A9 SRAM_A0 SRAM_A1 SRAM_A2 SRAM_A3 SRAM_A4 SRAM_CE0 SRAM_D0 SRAM_D1 SRAM_D2 SRAM_D3 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 C80 0.1uF DI SM/C_0402 +3_3V SRAM TSOPII44 SRAM TSOPII44 C92 0.1uF DI SM/C_0402 C81 0.1uF DI SM/C_0402 A0/A4/A4 A17/A5/A5 A1/A3/A3 A16/A6/A6 A2/A2/A2 A15/A7/A7 A3/A1/A1 OEn A4/A0/A0 BHEn CEn BLEn I/O0 I/O15 I/O1 I/O14 I/O2 I/O13 I/O3 I/O12 VCC VSS VSS VCC I/O4 I/O11 I/O5 I/O10 I/O6 I/O9 I/O7 I/O8 WEn NC A5/A16/A15 A14/A8/A8 A6/A15/A14 A13/A9/A9 A7/A14/A13 A12/A10/A10 A8/A13/A12 A11/A11/A11 A9/A12/NC A10/NC/NC 256K/128K/64Kx16 U11 DI A0/A4/A4 A17/A5/A5 A1/A3/A3 A16/A6/A6 A2/A2/A2 A15/A7/A7 A3/A1/A1 OEn A4/A0/A0 BHEn CEn BLEn I/O0 I/O15 I/O1 I/O14 I/O2 I/O13 I/O3 I/O12 VCC VSS VSS VCC I/O4 I/O11 I/O5 I/O10 I/O6 I/O9 I/O7 I/O8 WEn NC A5/A16/A15 A14/A8/A8 A6/A15/A14 A13/A9/A9 A7/A14/A13 A12/A10/A10 A8/A13/A12 A11/A11/A11 A9/A12/NC A10/NC/NC 256K/128K/64Kx16 U8 DI 256Kx16 - CY7C1041CV33 128Kx16 - CY7C1011CV33 64Kx16 - CY7C1021CV33 256Kx16 - CY7C1041CV33 128Kx16 - CY7C1011CV33 64Kx16 - CY7C1021CV33 SRAM_A[0..17] SRAM_BE[0..3] SRAM_CE[0..1] SRAM_WE SRAM_OE 5 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 +3_3V 3 C93 0.1uF DI SM/C_0402 3 SRAM_A14 SRAM_A13 SRAM_A12 SRAM_A11 SRAM_A10 SRAM_D27 SRAM_D26 SRAM_D25 SRAM_D24 SRAM_A17 SRAM_A16 SRAM_A15 SRAM_OE SRAM_BE3 SRAM_BE2 SRAM_D31 SRAM_D30 SRAM_D29 SRAM_D28 SRAM_A14 SRAM_A13 SRAM_A12 SRAM_A11 SRAM_A10 SRAM_D11 SRAM_D10 SRAM_D9 SRAM_D8 SRAM_A17 SRAM_A16 SRAM_A15 SRAM_OE SRAM_BE1 SRAM_BE0 SRAM_D15 SRAM_D14 SRAM_D13 SRAM_D12 2 2 Date: Size B Title Document Number Asynchronous SRAM 5555 NE Moore Ct Hillsboro, OR 97124 Lattice Semiconductor Corporation 1 Sheet 1 10 of 20 Rev 000 A B C D Lattice Semiconductor LatticeXP2 Standard Evaluation Board User’s Guide Figure 13. Asynchronous SRAM 27 A B C D XP2Bank6_[0..45] XP2Bank3_[0..45] 5 XP2Bank6_[0..45] XP2Bank3_[0..45] 5 XP2Bank6_6 XP2Bank6_7 XP2Bank6_12 XP2Bank6_13 XP2Bank6_16 XP2Bank6_17 XP2Bank6_24 XP2Bank6_38 XP2Bank6_39 XP2Bank6_40 XP2Bank3_4 XP2Bank3_5 XP2Bank3_10 XP2Bank3_11 XP2Bank3_12 XP2Bank3_13 XP2_IO_0 XP2_IO_1 XP2_IO_2 XP2_IO_3 XP2_IO_4 XP2_IO_5 XP2_IO_6 XP2_IO_7 XP2_IO_8 XP2_IO_9 XP2_IO_10 XP2_IO_11 XP2_IO_12 XP2_IO_13 XP2_IO_14 XP2_IO_15 TP41 TP55 TP59 TP63 TP67 TP71 TP31 TP35 TP39 TP53 TP57 TP61 TP65 TP69 TP33 TP37 TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP 4 4 TP29 TP30 TP48 TP49 TP50 TP51 TP52 TP36 TP58 TP62 TP66 TP70 TP56 TP60 (U3) (T3) (U2) (V3) (R3) (R4) (P4) (M3) (N2) (M4) (W22) (W20) (U20) (V20) (U21) (V22) TP TP TP TP TP TP TP TP TP TP TP TP TP TP 3 3 2 2 Date: Size B Title Document Number Prototype Grid 5555 NE Moore Ct Hillsboro, OR 97124 Lattice Semiconductor Corporation 1 Sheet 1 11 of 20 Rev 000 A B C D Lattice Semiconductor LatticeXP2 Standard Evaluation Board User’s Guide Figure 14. Prototype Grid 28 A B C D 5V Input J9 DI M_HOLE1 DI IW_MNT0 M_HOLE1 DI IW_MNT0 5 EN_VADJ EN_3_3V EN_1_2V PWR JACK PWR_JACK VIN 1 1 1 2 3 MH3 MH1 5 VIN VIN Page 15 EN_VADJ VIN VADJ H3 VADJ +3_3V Page 14 EN_3_3V VIN V3_3 H2 +1_2V Page 13 EN_1_2V V1_2 H1 GND M_HOLE1 DI IW_MNT0 TP4 TP 1 M_HOLE1 DI IW_MNT0 1 VIN MH4 MH2 4 4 J5 CON8 HD8x1 DI 1 2 3 4 5 6 7 8 VADJ +3_3V +1_2V R44 4.7K SM/R_0402 DI PAC_TCK PAC_TMS VPAC PAC_TDO PAC_TDI R43 100 SM/R_0603 DNI 3 C15 47pF SM/C_0603 DNI R4 10K SM/R_0402 DI 18 14 19 15 29 28 2 3 5 6 7 10 VMON1 VMON2 VMON3 VMON4 VMON5 VMON6 TDI TDO TMS TCK IN1 IN2 21 4 13 HVOUT1 HVOUT2 VCCJ 12 11 GNDA U1 ispPAC-POWR607 32QFN DI IN/OUT3 IN/OUT4 IN/OUT5 IN/OUT6 IN/OUT7 VCCA GNDD VCCD C2 0.1uF SM/C_0603 DNI Q1 2N2222 SOT23 VPAC DI PAC_PWRDN_n XP2Bank3_3 D1 ZENER_DIODE SOD323 DI R6 470 SM/R_0603 DI BIAS R27 10K SM/R_0402 DI PAC PWDN_n TP TP1 C1 1uF SM/C_0603 DI VIN 3 27 26 23 22 20 30 31 2 EN_VADJ XP2Bank3_22 XP2Bank3_23 XP2Bank3_40 XP2Bank3_41 EN_1_2V EN_3_3V 2 VPAC XP2Bank3_[0..45] Date: Size B Title Document Number Power Manager 5555 NE Moore Ct Hillsboro, OR 97124 Lattice Semiconductor Corporation R5 4.7K SM/R_0402 DI R7 4.7K SM/R_0402 DI R8 4.7K SM/R_0402 DI R9 +3_3V 4.7K SM/R_0402 DI R3 4.7K SM/R_0402 DI R2 4.7K SM/R_0402 DI R1 4.7K SM/R_0402 DI 1 Sheet 12 of XP2Bank3_[0..45] 1 20 Rev 000 A B C D Lattice Semiconductor LatticeXP2 Standard Evaluation Board User’s Guide Figure 15. Power Manager 29 A B C 5 GND VIN EN_1_2V C10 10uF SM/C_1206 DNI TP TP2 4 7 EN_1_2 SS EN IN U15 MP2307 SOIC8N DNI 5 EN_1_2 3 4 VIN BS Vout VAR HS NC 1 7 8 6 2 +1_2V 3 R14 DI R26 4.7K SM/R_0402 DNI 1_2_ADJ1 C7 0.1uF SM/C_0603 DNI C12 10nF SM/C_0603 DNI 3 C8 5.6nF SM/C_0603 DNI RC_1_2 FB_1_2 3 5 BS_1_2 SW_1_2 1 COMP_1_2 FB SW PWR_GOOD Bellnix_BSV_m3 DI SMT_PWR GND RC Vin U3 C9 0.1uF SM/C_0603 DNI SS_1_2 8 2 VIN C11 10uF SM/C_1206 DNI 4 GND 4 COMP 6 D 5 47.5K_1% SM/R_0402 1_2_ADJ2 D13 BarrierDiode SOD123FL DNI R13 1910_1% SM/R_0402 DI R25 10K_1% DNI SM/R_0603 R24 3.01K_1% SM/R_0603 DNI L5 10uH CDRH8D43 DNI 2 C13 22uF SM/C_1210 DNI 2 Date: Size B Title Document Number 1.2V Core Supply 5555 NE Moore Ct Hillsboro, OR 97124 Lattice Semiconductor Corporation C14 22uF SM/C_1210 DNI +1_2V 1 Sheet 1 13 of 20 Rev 000 A B C D Lattice Semiconductor LatticeXP2 Standard Evaluation Board User’s Guide Figure 16. 1.2V Core Supply 30 A B C 5 GND EN_3_3V VIN 4 C29 10uF SM/C_1206 DNI TP TP18 7 EN_3_3 5 EN_3_3 3 4 VIN VAR HS NC PWR_GOOD Vout 1 7 8 6 2 C27 0.1uF SM/C_0603 DNI 3 C48 10nF SM/C_0603 DNI 3 +3_3V R82 4.7K SM/R_0402 DNI C45 5.6nF SM/C_0603 DNI RC_3_3 FB_3_3 SW_3_3 3 5 BS_3_3 1 COMP_3_3 FB SW BS Bellnix_BSV_m6 DI SMT_PWR GND RC Vin U6 SS EN IN U17 MP2307 SOIC8N DNI C46 0.1uF SM/C_0603 DNI SS_3_3 8 2 VIN C28 10uF SM/C_1206 DNI 4 GND 4 COMP 6 D 5 D15 BarrierDiode SOD123FL DNI R80 10K_1% SM/R_0603 DNI R81 26.1K_1% SM/R_0603 DNI L7 10uH CDRH8D43 DNI 2 2 C49 22uF SM/C_1210 DNI Date: Size B Title Document Number 3.3V Power converter 5555 NE Moore Ct Hillsboro, OR 97124 Lattice Semiconductor Corporation C47 22uF SM/C_1210 DNI +3_3V 1 Sheet 1 14 of 20 Rev 000 A B C D Lattice Semiconductor LatticeXP2 Standard Evaluation Board User’s Guide Figure 17. 3.3V Power Converter 31 A B C 5 GND EN_VADJ VIN C18 10uF SM/C_1206 DNI TP TP12 4 5 EN_VADJ 3 4 VIN C22 0.1uF SM/C_0603 DNI 8 7 EN_VADJ SS_ADJ 2 VIN C19 10uF SM/C_1206 DNI 4 VAR HS NC PWR_GOOD Vout 1 7 8 6 2 C16 0.1uF SM/C_0603 DNI C17 5.6nF SM/C_0603 DNI C24 10nF SM/C_0603 DNI 3 3 VADJ_1 VADJ D14 BarrierDiode SOD123FL DNI R45 DI VADJ_2 47.5K_1% SM/R_0402 Adjustable range: 1.1-2.5V R58 4.7K SM/R_0402 DNI RC_ADJ FB_ADJ SW_ADJ 3 5 BS_ADJ 1 COMP_ADJ FB SW BS Bellnix_BSV_m3 DI SMT_PWR GND RC Vin U4 SS EN IN U16 MP2307 SOIC8N DNI GND 4 COMP 6 D 5 R10 250K DI TH_POT R57 10K_1% SM/R_0603 DNI MPS VADJ R11 25K POT DNI Bellnix VADJ ADJ_1_2 R59 2.32K_1% SM/R_0603 DNI L6 10uH CDRH8D43 DNI 2 2 C25 22uF SM/C_1210 DNI C23 22uF SM/C_1210 DNI VADJ Date: Size B Title Document Number Adjustable Power Supply 5555 NE Moore Ct Hillsboro, OR 97124 Lattice Semiconductor Corporation VADJ 1 Sheet 1 15 of 20 Rev 000 A B C D Lattice Semiconductor LatticeXP2 Standard Evaluation Board User’s Guide Figure 18. Adjustable Power Supply 32 A B C D R93 300K DI SM/R_0603 USB_RESETn C106 0.1uF DI SM/C_0402 XO_VCCIO4 C87 1uF DI SM/C_0603 +3_3V 1 2 3 4 5 6 5 L4 DI 4 3 C90 0.1uF DI SM/C_0402 XO_VCCIO5 2 1 Ferrite_bead BD0603 USBUSB+ 3 4 EN VCC GND OUT 24MHz DI OSC_SMT Y2 USB_CONN_B TH_TYPE_B SGND J21 DI 1 2 CLK_EN USB Reset C107 0.1uF DI SM/C_0402 XO_VCCIO6 SW5 PUSHBUTTON DI SMT_SW USB_RESETn 0.1uF +3_3V SM/C_0402 R92 4.7K DI SM/R_0402 C86 DI TP17 C112 0.1uF DI SM/C_0402 L2 Ferrite_bead DI BD0603 CTL2/FLAGC CTL1/FLAGB CTL0/FLAGA RDY0/SLRD RDY1/SLWR SCL SDA WAKEUP RESET# RESERVED DPLUS DMINUS XTALOUT XTALIN IFCLK/T0OUT CLKOUT/T1OUT U18 AVCC C95 0.1uF DI SM/C_0402 4 +3_3V C91 0.1uF DI SM/C_0402 47 46 45 44 43 42 41 40 3 2 1 56 55 54 53 52 32 31 30 29 28 27 26 25 C111 0.1uF DI SM/C_0402 USB7 USB6 USB5 USB4 USB3 USB2 USB1 USB0 USB23 USB22 USB21 USB20 USB19 USB18 USB17 USB16 USB15 USB14 USB13 USB12 USB11 USB10 USB9 USB8 C104 0.1uF DI SM/C_0402 XOJTAG[0..3] 3 C109 0.1uF DI SM/C_0402 H3 MACHXO C105 0.1uF DI SM/C_0402 XO_VCCIO2 2 USB18 USB19 USB20 USB21 USB22 USB23 USB24 USB25 USB26 USB27 USB28 USB29 USB30 USB31 USB32 USB33 USB34 Page 17 2 XOBank7_21 XOBank7_20 XOBank7_17 XOBank7_16 XOBank6_0 XOBank7_14 XOBank6_15 XOBank6_14 XOBank6_13 XOBank6_11 XOBank6_7 XOBank6_9 XOBank6_8 XOBank7_15 XOBank6_12 XOBank6_5 XOBank6_24 XOBank4_5 VCCIO[0..7] VCCAUX VCORE XOBank7_[0..25] XOBank6_[0..27] XOBank45_[0..1] XOBank5_[0..19] XOBank4_[0..27] XO_VCCIO3 C108 0.1uF DI SM/C_0402 XOJTAG[0..3] XOBank3_[0..28] XOBank2_[0..25] XOBank01_[0..1] XOBank1_[0..28] XOBank0_[0..23] XOBank7_13 XOBank7_12 XOBank7_11 XOBank7_10 XOBank7_7 XOBank7_6 XOBank7_5 XOBank7_4 XOBank6_17 XOBank6_16 XOBank6_19 XOBank6_18 XOBank6_23 XOBank6_22 XOBank6_27 XOBank6_26 XOBank7_25 XOBank7_24 XOJTAG[0..3] XOBank3_[0..28] XOBank2_[0..25] XOBank01_[0..1] XOBank1_[0..28] XOBank0_[0..23] USB0 USB1 USB2 USB3 USB4 USB5 USB6 USB7 USB8 USB9 USB10 USB11 USB12 USB13 USB14 USB15 USB16 USB17 C110 0.1uF DI SM/C_0402 XO_VCCIO1 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PD0 PD1 XOBank3_[0..28] XOBank2_[0..25] XOBank01_[0..1] XOBank1_[0..28] XOBank0_[0..23] 3 XO_VCCIO0 XO VCCAUX BYPASS C96 0.1uF DI SM/C_0402 CY7C68013A DI SSOP56 PA7/FLAGD/SLCS# PA6/PKTEND PA5/FIFOADR1 PA4/FIFOADR0 PA3/WU2 PA2/SLOE PA1/INT1# PA0/INT0# PD7/FD15 PD6/FD14 PD5/FD13 PD4/FD12 PD3/FD11 PD2/FD10 PD1/FD9 PD0/FD8 PB7/FD7 PB6/FD6 PB5/FD5 PB4/FD4 PB3/FD3 PB2/FD2 PB1/FD1 PB0/FD0 XO VCORE BYPASS C94 0.1uF DI SM/C_0402 +3_3V 38 37 36 USB26 USB25 USB24 TP 8 9 XO_VCCIO7 GND 22 23 USB28 USB27 51 49 21 USB30 USB29 15 16 USB32 USB31 11 12 20 5 USB+ USB- 24MHz USB34 USB33 +3_3V 4 6 18 24 34 39 50 10 14 VCC VCC VCC VCC VCC VCC AVCC AVCC GND GND GND GND GND GND AGND AGND 4 7 19 33 35 48 13 17 5 XOBank4_[0..27] XOBank4_[0..27] DI Date: Size B Title Document Number USB Download PHY 5555 NE Moore Ct Hillsboro, OR 97124 1 2 3 HEADER_3 HD3x1 DI J28 JBLOCK JB6 J23 CON8 HD8x1 DI 1 2 3 4 5 6 7 8 PU0 1 Sheet 16 of XO TSALL 1-2: XO I/O Hi-Z 2-3: XO I/O active XOBank6_10 R23 4.7K SM/R_0402 DI TCK_XO TMS_XO XOJTAG2 XOJTAG3 TDO_XO TDI_XO XOJTAG1 XOJTAG0 +3_3V +3_3V XO JTAG header XO_VCCIO0 XO_VCCIO1 XO_VCCIO2 XO_VCCIO3 XO_VCCIO4 XO_VCCIO5 XO_VCCIO6 XO_VCCIO7 +3_3V XOBank7_[0..25] XOBank6_[0..27] XOBank45_[0..1] XOBank5_[0..19] Lattice Semiconductor Corporation PD2 PD3 PD4 PD5 PD6 PD7 CTL0 CTL1 CTL2 RDY1 RDY0 SDA SCL RESETn WAKEUP CLKO IFCLK XO_VCCIO[0..7] XOBank7_[0..25] XOBank6_[0..27] XOBank45_[0..1] XOBank5_[0..19] 1 20 Rev 000 A B C D Lattice Semiconductor LatticeXP2 Standard Evaluation Board User’s Guide Figure 19. USB Download PHY 33 A B C D XOJTAG[0..3] XOBank45_[0..1] XOBank5_[0..19] XOBank4_[0..27] XOBank01_[0..1] XOBank1_[0..28] XOBank0_[0..23] 5 5 XOJTAG[0..3] XOBank45_[0..1] XOBank5_[0..19] XOBank4_[0..27] XOBank01_[0..1] XOBank1_[0..28] XOBank0_[0..23] XOBank01_[0..1] XOBank1_[0..28] XOBank0_[0..23] XOJTAG[0..3] XOBank45_[0..1] XOBank5_[0..19] XOBank4_[0..27] XO_BANK_4_7 H2 XO_BANK_0_3 H1 Page 19 4 XOBank7_[0..25] XOBank6_[0..27] Page 18 XOBank3_[0..28] XOBank2_[0..25] 4 XOBank7_[0..25] XOBank6_[0..27] XOBank3_[0..28] XOBank2_[0..25] XOBank7_[0..25] XOBank6_[0..27] XOBank3_[0..28] XOBank2_[0..25] 3 3 VCCIO[0..7] VCCAUX L7 L8 J6 K6 VCCIO5 VCCIO5 VCCIO6 VCCIO6 A8 T9 G6 H6 L9 L10 VCCIO4 VCCIO4 VCCIO7 VCCIO7 J11 K11 G11 H11 VCCIO2 VCCIO2 VCCIO3 VCCIO3 F9 F10 F7 F8 VCCIO1 VCCIO1 VCCIO0 VCCIO0 2 VCCAUX_0 VCCAUX_1 VCCIO7_0 VCCIO7_1 VCCIO6_0 VCCIO6_1 VCCIO5_0 VCCIO5_1 VCCIO4_0 VCCIO4_1 VCCIO3_0 VCCIO3_1 VCCIO2_0 VCCIO2_1 VCCIO1_0 VCCIO1_1 VCC_3 VCC_2 VCC_1 VCC_0 GND_0 GND_1 GND_2 GND_3 GND_4 GND_5 GND_6 GND_7 GND_8 GND_9 GND_10 GND_11 GND_12 GND_13 GND_14 GND_15 GND_16 GND_17 K7 G7 K10 G10 A16 T16 F11 H10 J10 G9 H9 J9 K9 G8 H8 J8 K8 H7 J7 L6 A1 T1 Date: Size B Title Document Number XO Power 5555 NE Moore Ct Hillsboro, OR 97124 Lattice Semiconductor Corporation XO_640 common VCCIO VCCJ on VCCIO5 XO_640 common VCCIO XO_640 common VCCIO XO_640 common VCCIO MachXO_2280 FPBGA256 VCCIO0_0 VCCIO0_1 U14E DI 2 1 Sheet 1 17 of VCORE 20 Rev 000 A B C D Lattice Semiconductor LatticeXP2 Standard Evaluation Board User’s Guide Figure 20. MachXO Power A B C D B6 B7 A6 A7 B8 C8 XOBank0_18 XOBank0_19 XOBank0_20 XOBank0_21 XOBank0_22 XOBank0_23 5 C6 C7 B4 B5 XOBank0_10 XOBank0_11 XOBank0_16 XOBank0_17 D6 D5 XOBank0_8 XOBank0_9 A5 A4 C4 C5 XOBank0_6 XOBank0_7 XOBank0_14 XOBank0_15 D3 D4 XOBank0_4 XOBank0_5 E7 E6 A2 A3 XOBank0_2 XOBank0_3 XOBank0_12 XOBank0_13 B2 B3 XOBank0_0 XOBank0_1 I/Os in Bank 0 for XO1200 Pin name sequence PT(640,1200,2280) PT4E/PT6C/PT8C PT4F/PT6D/PT8D PT4C/PT6A/PT7C PT4D/PT6B/PT7D PT4A/PT5E/PT7A PT4B/PT5F/PT7B PT3C/PT5C/PT6A PT3D/PT5D/PT6B PT3E/PT5A/PT6C PT3F/PT5B/PT6D NC/PT4C/PT6E NC/PT4D/PT6F PT3A/PT3E/PT5C PT3B/PT3F/PT5D PT2C/PT3C/PT5A PT2D/PT3D/PT5B PT2E/PT4A/PT4A PT2F/PT4B/PT4B NC/PT2C/PT3C NC/PT2D/PT3D PT2A/PT3A/PT3A PT2B/PT3B/PT3B VCCIO1 PT9A/PT7A/PT9C PT9B/PT7B/PT9D I/Os in Bank 1 for XO2280 NC/PT11C/PT16C NC/PT11D/PT16D NC/PT11A/PT16A NC/PT11B/PT16B PT9E/PT10E/PT15C PT9F/PT10F/PT15D NC/PT10C/PT15A NC/PT10D/PT15B PT9C/PT10A/PT14C PT9D/PT10B/PT14D PT7E/PT9E/PT14A PT7F/PT9F/PT14B PT8A/PT9C/PT13C PT8B/PT9D/PT13D PT7A/PT9A/PT12C PT7B/PT9B/PT12D PT7C/PT8E/PT12A PT7D/PT8F/PT12B PT5C/PT8C/PT11A PT5D/PT8D/PT11B PT8C/PT8A/PT10E PT8D/PT8B/PT10F PT6C/PT7E/PT10C PT6D/PT7F/PT10D PT6A/PT7C/PT10A PT6B/PT7D/PT10B/CLK1 XOBank0_[0..23] XOBank1_[0..27] XOBank01_[0..1] XOBank2_[0..25] XOBank3_[0..27] MachXO_2280 FPBGA256 VCCIO0 U14A DI NC/PT2A/PT2C NC/PT2B/PT2D XOBank0_[0..23] XOBank1_[0..27] XOBank01_[0..1] XOBank2_[0..25] XOBank3_[0..27] 5 PT5A/PT6E/PT9A PT5B/PT6F/PT9B/CLK0 D8 D7 34 XOBank01_1 XOBank01_2 XOBank1_20 XOBank1_21 XOBank1_22 XOBank1_23 XOBank1_24 XOBank1_25 XOBank1_26 XOBank1_27 E10 E11 B13 C13 B14 C14 A15 B15 4 XOBank1_18 XOBank1_19 XOBank1_16 XOBank1_17 XOBank1_14 XOBank1_15 XOBank1_12 XOBank1_13 XOBank1_10 XOBank1_11 XOBank1_8 XOBank1_9 XOBank1_6 XOBank1_7 XOBank1_4 XOBank1_5 XOBank1_2 XOBank1_3 XOBank1_0 XOBank1_1 D11 D12 A13 A14 C11 C12 B11 B12 A11 A12 B9 B10 D9 D10 C9 C10 A10 A9 E8 E9 4 3 3 XOBank2_24 XOBank2_25 XOBank2_22 XOBank2_23 XOBank2_20 XOBank2_21 XOBank2_18 XOBank2_19 XOBank2_16 XOBank2_17 XOBank2_14 XOBank2_15 XOBank2_12 XOBank2_13 XOBank2_10 XOBank2_11 XOBank2_8 XOBank2_9 XOBank2_6 XOBank2_7 XOBank2_4 XOBank2_5 XOBank2_2 XOBank2_3 XOBank2_0 XOBank2_1 G15 H15 G14 H14 H12 H13 G12 G13 F16 G16 E15 F15 D16 E16 C15 D15 B16 C16 E14 F14 F13 F12 E13 E12 D14 D13 MachXO_2280 FPBGA256 Pin name sequence PR(640,1200,2280) PR6A/PR8C/PR10C PR6B/PR8D/PR10D PR5C/PR8A/PR10A/LV_T PR5D/PR8B/PR10B/LV_C PR6C/PR7C/PR9C PR6D/PR7D/PR9D PR4C/PR7A/PR9A/LV_T PR4D/PR7B/PR9B/LV_C PR5A/PR6C/PR7C PR5B/PR6D/PR7D PR4A/PR6A/PR7A/LV_T PR4B/PR6B/PR7B/LV_C PR3A/PR5C/PR6C PR3B/PR5D/PR6D PR2C/PR5A/PR6A/LV_T PR2D/PR5B/PR6B/LV_C PR2A/PR4C/PR5C PR2B/PR4D/PR5D PR3C/PR4A/PR5A/LV_T PR3D/PR4B/PR5B/LV_C NC/PR3C/PR4C NC/PR3D/PR4D NC/PR3A/PR4A/LV_T NC/PR3B/PR4B/LV_C NC/PR2A/PR3A/LV_T NC/PR2B/PR3B/LV_C VCCIO2 U14D DI 2 NC/PR16A/PR20A NC/PR16B/PR20B NC/PR15A/PR18A/LV_T NC/PR15B/PR18B/LV_C NC/PR14C/PR17C NC/PR14D/PR17D PR11C/PR14A/PR17A/LV_T PR11D/PR14B/PR17B/LV_C PR11A/PR13C/PR16C PR11B/PR13D/PR16D PR10A/PR13A/PR16A/LV_T PR10B/PR13B/PR16B/LV_C PR10C/PR12C/PR15C PR10D/PR12D/PR15D PR9C/PR12A/PR15A/LV_T PR9D/PR12B/PR15B/LV_C PR9A/PR11C/PR14C PR9B/PR11D/PR14D PR8C/PR11A/PR14A/LV_T PR8D/PR11B/PR14B/LV_C PR8A/PR10C/PR13C PR8B/PR10D/PR13D PR7C/PR10A/PR13A/LV_T PR7D/PR10B/PR13B/LV_C NC/PR9C/PR11C NC/PR9D/PR11D PR7A/PR9A/PR11A/LV_T PR7B/PR9B/PR11B/LV_C VCCIO3 2 XOBank3_26 XOBank3_27 XOBank3_24 XOBank3_25 XOBank3_22 XOBank3_23 XOBank3_20 XOBank3_21 XOBank3_18 XOBank3_19 XOBank3_16 XOBank3_17 XOBank3_14 XOBank3_15 XOBank3_12 XOBank3_13 XOBank3_10 XOBank3_11 XOBank3_8 XOBank3_9 XOBank3_6 XOBank3_7 XOBank3_4 XOBank3_5 XOBank3_2 XOBank3_3 XOBank3_0 XOBank3_1 Date: Size B Title Document Number XO Banks 0-3 5555 NE Moore Ct Hillsboro, OR 97124 Lattice Semiconductor Corporation L11 M11 N13 N12 M12 M13 N15 N14 L12 L13 L14 M14 M16 N16 L15 M15 K16 L16 J13 K13 J14 K14 J15 K15 J12 K12 H16 J16 1 Sheet 1 18 of 20 Rev 000 A B C D Lattice Semiconductor LatticeXP2 Standard Evaluation Board User’s Guide Figure 21. MachXO Banks 0 to 3 A B C D XOBank4_[0..27] XOBank5_[0..19] XOBank45_[0..1] XOBank6_[0..27] XOBank7_[0..25] XOJTAG[0..3] 5 5 N7 M6 P4 R3 XOJTAG0 XOJTAG1 XOJTAG2 XOJTAG3 R6 T6 XOBank5_12 XOBank5_13 R7 R8 T5 T4 XOBank5_10 XOBank5_11 XOBank5_18 XOBank5_19 P5 P6 XOBank5_8 XOBank5_9 T8 T7 R4 R5 XOBank5_6 XOBank5_7 M7 M8 T2 T3 XOBank5_4 XOBank5_5 XOBank5_16 XOBank5_17 N5 N6 XOBank5_2 XOBank5_3 XOBank5_14 XOBank5_15 P2 P3 XOBank5_0 XOBank5_1 XOBank4_[0..27] XOBank5_[0..19] XOBank45_[0..1] XOBank6_[0..27] XOBank7_[0..25] XOJTAG[0..3] MachXO_2280 FPBGA256 I/Os in Bank 5 for XO1200 Pin name sequence PB(640,1200,2280) TDI TDO TMS TCK PB4E/PB6C/PB8C PB4F/PB6D/PB8D NC/PB6A/PB7C NC/PB6B/PB7D PB4C/PB5C/PB6A PB4D/PB5D/PB6B PB4A/PB5A/PB5A PB4B/PB5B/PB5B PB3C/PB4C/PB4C PB3D/PB4D/PB4D PB3A/PB4A/PB4A PB3B/PB4B/PB4B PB2C/PB3C/PB3C PB2D/PB3D/PB3D PB2A/PB3A/PB3A PB2B/PB3B/PB3B NC/PB2C/PB2C NC/PB2D/PB2D NC/PB2A/PB2A NC/PB2B/PB2B VCCIO5 U14C DI PB5C/PB6E/PB9A PB5D/PB6F/PB9B P7 P8 35 XOBank45_0 XOBank45_1 VCCIO4 4 I/Os in Bank 4 for XO2280 NC/PB11C/PB16C NC/PB11D/PB16D SLEEPN PB9F/PB10F/PB15D NC/PB11A/PB16A NC/PB11B/PB16B PB9C/PB10C/PB15A PB9D/PB10D/PB15B PB9A/PB10A/PB14C PB9B/PB10B/PB14D PB8C/PB9E/PB14A PB8D/PB9F/PB14B PB8A/PB9C/PB13C PB8B/PB9D/PB13D PB7E/PB9A/PB13A PB7F/PB9B/PB13B NC/PB8E/PB12C NC/PB8F/PB12D PB7C/PB8C/PB12A PB7D/PB8D/PB12B PB6C/PB8A/PB11C PB6D/PB8B/PB11D PB6A/PB7E/PB10A PB6B/PB7F/PB10B/CLK3 PB7A/PB7C/PB10C PB7B/PB7D/PB10D PB5A/PB7A/PB10E PB5B/PB7B/PB10F/CLK2 4 XOBank4_26 XOBank4_27 3 XOBank7_24 XOBank7_25 XOBank4_24 XOBank4_25 P13 P14 P15 P16 XOBank7_22 XOBank7_23 XOBank4_22 XOBank4_23 XOBank7_20 XOBank7_21 XOBank4_20 XOBank4_21 R15 R16 XOBank7_18 XOBank7_19 XOBank4_18 XOBank4_19 XOBank7_16 XOBank7_17 XOBank7_14 XOBank7_15 XOBank7_12 XOBank7_13 XOBank7_10 XOBank7_11 XOBank7_8 XOBank7_9 R13 R14 XOBank4_16 XOBank4_17 XOBank4_14 XOBank4_15 XOBank4_12 XOBank4_13 XOBank4_10 XOBank4_11 XOBank4_8 XOBank4_9 XOBank7_6 XOBank7_7 XOBank7_4 XOBank7_5 XOBank4_6 XOBank4_7 XOBank7_2 XOBank7_3 XOBank4_4 XOBank4_5 XOBank7_0 XOBank7_1 XOBank4_2 XOBank4_3 XOBank4_0 XOBank4_1 T14 T15 T13 T12 P11 P12 R11 R12 N10 N11 T10 T11 R9 R10 M10 M9 P9 P10 N8 N9 3 G1 H1 H4 H5 G3 H3 G4 G5 E1 F1 F2 G2 D2 D1 B1 C1 C3 C2 E3 E2 F3 F4 F5 F6 E4 E5 MachXO_2280 FPBGA256 VCCIO6 PL7C/PL9C/PL11C PL7D/PL9D/PL11D PL6A/PL9A/PL11A/LV_T PL6B/PL9B/PL11B/LV_C PL11A/PL13C/PL16C PL11B/PL13D/PL16D PL8A/PL13A/PL16A/LV_T PL8B/PL13B/PL16B/LV_C PL9C/PL12C/PL15C PL9D/PL12D/PL15D PL10A/PL12A/PL15A/LV_T PL10B/PL12B/PL15B/LV_C Pin name sequence PL(640,1200,2280) 2 N4 N3 M5 M4 L5 L4 K5 K4 R1 R2 J4 J5 M2 N2 L3 M3 N1 P1 L1 M1 K2 L2 J1 K1 J3 K3 H2 J2 XOBank6_26 XOBank6_27 XOBank6_24 XOBank6_25 XOBank6_22 XOBank6_23 XOBank6_20 XOBank6_21 XOBank6_18 XOBank6_19 XOBank6_16 XOBank6_17 XOBank6_14 XOBank6_15 XOBank6_12 XOBank6_13 XOBank6_10 XOBank6_11 XOBank6_8 XOBank6_9 XOBank6_6 XOBank6_7 XOBank6_4 XOBank6_5 XOBank6_2 XOBank6_3 XOBank6_0 XOBank6_1 Date: Size B Title Document Number XO Banks 4-7 5555 NE Moore Ct Hillsboro, OR 97124 Lattice Semiconductor Corporation PL11C/PL16A/PL19A PL11D/PL16B/PL19B PL5C/PL8C/PL10C NC/PL15A/PL18A/LV_T/PLL0_T_IN PL5D/PL8D/PL10D NC/PL15B/PL18B/LV_C/PLL0_C_IN PL10C/PL14C/PL17C PL10D/PL14D/PL17D NC/PL14A/PL17A/LV_T/PLL0_T_FB NC/PL14B/PL17B/LV_C/PLL0_C_FB NC/PL8A/PL9A/LV_T NC/PL8B/PL9B/LV_C PL4C/PL7C/PL8C PL4D/PL7D/PL8D NC/PL7A/PL8A/LV_T NC/PL7B/PL8B/LV_C PL4A/PL6C/PL7C PL4B/PL6D/PL7D PL9A/PL10C/PL12C PL9B/PL10D/PL12D PL7A/PL11A/PL13A/LV_T PL7B/PL11B/PL13B/LV_C TSALL/PL8C/PL11C/PL14C PL8D/PL11D/PL14D PL5A/PL6A/PL7A/LV_T PL5B/PL6B/PL7B/GSR/LV_C PL3C/PL5C/PL6C PL3D/PL5D/PL6D PL2A/PL5A/PL5A/LV_T PL2B/PL5B/PL5B/LV_C NC/PL4C/PL4C NC/PL4D/PL4D PL2C/PL4A/PL4A/LV_T PL2D/PL4B/PL4B/LV_C PL3A/PL3C/PL3C/PLL1T_IN PL6C/PL10A/PL12A/LV_T PL3B/PL3D/PL3D/PLL1C_IN PL6D/PL10B/PL12B/LV_C NC/PL3A/PL3A/LV_T NC/PL3B/PL3B/LV_C NC/PL2A/PL2A/PLL1T_FB NC/PL2B/PL2B/PLL1C_FB VCCIO7 U14B DI 2 1 Sheet 1 19 of 20 Rev 000 A B C D Lattice Semiconductor LatticeXP2 Standard Evaluation Board User’s Guide Figure 22. MachXO Banks 4 to 7 36 A B C 5 SMA SMA SMA Swtch DIP SW Swtch 7seg soic8 SPI Sense LCD 3.3V Pot Bellnix SRAM Sense Sense OSC SRAM DAC USB A1 POT soic8 5.62" ADJ 4 XP2 4 CF Socket Bellnix 1.2V Pot Sense A1 Sense Bellnix Sense SMA Sense PWR Sense Sense soic16 68013A XO ADC RS232 ADS7842 D SMA 3 3 SMA SMA SMA SMA rs232 tssop16 5 5.26" 2 Primary side layout 2 Date: Size B Title Document Number Placement Proposal 5555 NE Moore Ct Hillsboro, OR 97124 Lattice Semiconductor Corporation 1 1 2 3 2 4 3 5 1 Sheet 20 View from primary side Bellnix component mounted on secondary 4 5 Overlapped layout 1 of 20 Rev 000 A B C D Lattice Semiconductor LatticeXP2 Standard Evaluation Board User’s Guide Figure 23. Placement Proposal SMA 1 dip14