LIF-UC120-CM36ITR1K

Lattice USB Type-C Solution Data Sheet DS1052 Version 1.4, August 2016 Lattice USB Type-C Solution Data Sheet Introduction August 2016 Data Sheet DS1052 General Description The USB Type-C receptacle, plug and cable provide a smaller, thinner and more robust alternative to existing USB interconnects. The Lattice USB Type-C solution targets its use in a variety of platforms ranging from notebooks, PCs, Monitors, down to tablets and smart phones. These solutions are also implemented in Docking Stations, USB chargers and cables where cable detect (CD) electronic intelligence and power delivery (PD) protocols are implemented. The Lattice solution is designed to support USB Type-C cable and Connector and USB Power Delivery specifications with programmable flexibility to support the new and evolving specifications as well as the various levels of complexities required by the end system in a cost effective manner. Features  Two solutions cover majority of USB Type-C Power Delivery (PD) and Cable Detect (CD) Applications: • CD/PD for Charger • CD/PD for hosts/devices • 48 QFN • 81 ucBGA  Ultra-Small Form Factor • As small as 2.078 mm x 2.078 mm  Logic Based PHY Provides Fast Deterministic Response and Low Power • Typical Solution Power 7 mW  Standby Power less than 100 uW  Flexible 8-bit uC Policy Engine Enables Easy Modifications  Supports Fast Development  USB Type-C PHY  USB Type-C Cable Detect (CD) support per USB Cable and Connector Specification v1.0  USB Power Delivery (PD) support per Power Delivery Specification v2.0 • IO capability to drive LED indicator • Industry Proven Solutions Reduce Design Risk • Schematics and BOMS available to minimize system design effort  Wide Range of Packages to Match PCB Technology Table 1-1. USB Type-C Device Table Solution Package, Ball Pitch, Dimension Typical End Equipment OPN CD/PD for Charger 48 QFN, 0.50 mm,  7.00 mm x 7.00 mm Charger LIF-UC110-SG48I CD/PD for  Hosts/Devices 81 ucBGA, 0.40 mm, 4.00 mm x 4.00 mm Tablet LIF-UC140-CM81I © 2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1-1 DS1052 Introduction_01.3 Lattice USB Type-C Solution Data Sheet Architecture August 2016 Data Sheet DS1052 Architecture Overview Figure 2-1. High-level Functional Block for USB Type-C Physical Layer and Power Detect Protocol CPU/ I2C/SPI AC/ /Other EC Policy Management Layer Policy Engine Layer Protocol Layer Capabilities Register Set Soft Reset Handler Construct Message Policy Manager VDM Engine I2C Slave Controller Policy Engine VBUS Current Sense Timer Interface Timer Block CD Interface Protocol Layer Message TX REGISTER Set Cable and Orientation Detect Protocol Layer Message RX Hard Reset Management SS Select Switch Select CC PHY 4B5B Encoder PHY Interface BMC TX BMC Encoder CRC REGISTER Set BIST Engine VBUS_EN VBUS Discharge Voltage Select 4B5B Decoder Stop/Start Detect BMC Decoder BMC RX CRC © 2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 2-1 DS1052 Architecture_01.4 Architecture Lattice USB Type-C Solution Data Sheet USB CD/PD Charger Solution (Captive Cable) Block Diagram Figure 2-2. USB CD/PD Charger Solution (Captive Cable) Block Diagram CD/PD Manager CD/PD PHY CC VBUS VBUS Power Control CD = Cable Detect PD = Power Delivery Features Supported in Schematics • Downstream Facing Port (DFP) • USB Power Delivery Communication between Port partners • Takes advantage of captive cable to minimize component count 2-2 Type C Connector LIF-UC110 2-3 A B C D 0 0 0 12V 19.6V 0V 0 0 1 0 0 1 0 0 100nF 10V 47 46 34 13 40 14 17 15 16 19 18 4K7 4K7 R17 CDONE 7 CRESET_B 8 Refer Note 5 VSEL1 VSEL2 VSEL3 VSEL4 VBUS_PG SPI_MISO SPI_MOSI SPI_SCK SPI_SS_B 20 10uF 10V CDONE CRESET_B IOB_2a IOB_0a IOT_44b IOB_24a RGB1 IOB_32a_SO IOB_33b_SI IOB_34a_SCK IOB_35b_CSN IOB_29b IOB_31b IOB_25b_G3 VCCPLL VCC VCC VPP2V5_Top VCCIO0 SPI_VCCIO1 VCCIO2 U1 VBUS_DSICHARGE_EN R4 QFN48 DEVICE 5 4 RGB0 IOT_41a IOT_42b IOB_6a IOB_9b IOT_38b IOT_36b IOT_46b_G0 IOT_51a IOT_39a IOT_43a IOB_20a IOB_18a IOT_50b IOT_49a IOT_45a_G1 IOT_37a IOB_8a IOB_16a IOB_13b IOT_48b VBUS_DET 1K C1 0.047uF VBUS Sense All VSEL* lines are programmable, they can ben changed based on customer requirement. VSEL4 can be used to select another output voltage 1 30 5 29 100R VCCPLL C11 C12 CLK_IN R16 3V3 33 22 1 2VPP_2V5 24 CDBU0520 1 D1 VSEL1 VSEL2 VSEL3 5V VBUS OUTPUT VOLTAGE SELECT LINES Config / Optional PMIC control via I2C R11 1V2 100nF 100nF 10V 10V 10uF 10V C7 C8 C6 1V2 100nF 100nF 100nF 10V 10V 10V C5 10uF 10V C4 C3 C2 3V3 Schematics 4 VBUS_REF Preliminary VBUS_SOURCE_EN 21 IOB_23b 12 IOB_22a VBUS_DET_PWM 44 IOB_3b_G6 39 RGB2 TH_PAD 49 45 IOB_5b 48 IOB_4a 41 28 31 2 3 27 25 35 42 26 32 11 10 38 43 37 23 4 9 CC1_TX 6 R8 R6 CC1_DET_PWM CC1_DET_REF CC1_RX_REF R18 CC1_RX CC1_DET CC1_TX_EN C14 1K 2 Q2 VBUS_SOURCE_EN 510K R2 N-Channel Q1 P-Channel 10m Current Monitor R1 4K7 100R R9 10V 3 0.047uF 42R2 1K R15 4.7nF 50V C9 VBUS 330pF 16V C10 Q3 N-Channel 1W 100R R3 C13 0.047uF 10V CC1 GND CC1 VBUS 2 Date: Size B Friday,04-Sep-15 Project CD_PD_Charger_Captive Title CD_PD_Charger_Captive 1 Sheet (Preliminary Schematics) Lattice Semiconductor Applications Email: techsupport@Latticesemi.com Phone (503) 268-8001 -or- (800) LATTICE Board Rev 1 of 2 A Schematic Rev 1.7 Notes:1) In case VBUS Current sensing is required, customer can contact Lattice tech support for current sense implementation. 2) CC1_RP resistor value is dependent on current rating. It should be 36KOhm for standard device, 12KOhm for 1.5A device and 4.7KOhm for 3A device. 3)These values are as per Lattice LAB tests. Might need fine-tuning by customer to meet the Eye requirements 4)During configration Lattice device pins are weak pulled-up for time duration of 40ms. 5)RGB0, RGB1 and RGB2 are open drain pins, they required external pull-up. Capacitor C10 is required to meet minimum reciever capacitance 3V3 Q6 N-Channel Q6 is for Device protection CC1_INT 1 not included in BOM Count VBUS_DSICHARGE_EN VBUS Control section Components are VBUS Power Control scheme shown is logical implmentation, for actual implementation please contact Lattice tech support. Refer Note 3 CC1_RP 36 75K R7 510K R5 VBUS VBUS SOURCE 3 ISENSE 5 A B C D Architecture Lattice USB Type-C Solution Data Sheet Schematics Figure 2-3. USB CD/PD Charger Solution (Captive Cable) Schematic Diagram Architecture Lattice USB Type-C Solution Data Sheet Table 2-1. USB CD/PD Mobile System Solution (Captive Cable) BOM Item Quantity Reference Part DESCRIPTION 1 3 C1, C13, C14 0.047 uF 2 3 C2, C6, C12 10 uF CAP CER 10 uf 10 V 10% X5R 0805 3 6 C4, C5, C7, C3, C8, C11 100 nF CAP CER 100 nf 10 V 10% X5R 0402 4 1 C9 4.7 nF CAP CER 3300 pF 10 V 5% U2J 0402 5 1 C10 330 pF CAP CER 3300 pF 16 V 10% X7R 0402 6 1 D1 CDBU0520 DIODE SCHOTTKY 20 V 500 MA 0603 7 1 Q1 P-Channel MOSFET P-CH 20 V 6 A SOT-23 8 1 Q3 N-Channel MOSFET N-CH 20 V 6.3 A SOT-23 CAP CER 0.047 uf 10 V 10% X5R 0402 9 2 Q2, Q6 N-Channel 10 3 R4, R15 1K MOSFET N-CH 30 V 0.85 A SOT23 11 2 R2, R5, R18 510K RES 510 kOhm 1/16 W 5% 0402 12 1 R8 100R RES SMD 100 Ohm 1% 1/16 W 0402 13 3 R6, R16, R17 4K7 RES 150 Ohm 1/16 W 1% 0402 SMD 14 1 R11 100R RES 100 Ohm 1/16 W 5% 0402 15 1 R9 42.2R RES SMD 42.2 Ohm 1% 1/16 W 0402 16 1 R3 100R RES SMD 100 Ohm 1% 1 W 2512 17 1 R7 75K RES SMD 75 kOhm 5% 1/16 W 0402 18 1 R1 10m RES 0.01 Ohm 1/2 W 1% 1206 19 1 U1 LIF-UC RES 1 kOhm 1/16 W 5% 0402 LIF-UC 48-Pin Device Table 2-2. USB CD/PD Mobile System Solution (Captive Cable) BOM Count1, 2 Item Component Count 1 Cap 14 2 FET 1 3 Resistor 11 4 Lattice LIF-UC 1 1. VBUS control section components are not Included in the BOM count. 2. Diode D1 is not included in the BOM count. It is required only during onboard NVCM programming. 2-4 Architecture Lattice USB Type-C Solution Data Sheet USB CD/PD Charger Solution (Non-Captive Cable) Block Diagram Figure 2-4. USB CD/PD Charger Solution (Non-Captive Cable) Block Diagram CD/PD Manager CD/PD PHY CC VBUS VBUS Power Control CD = Cable Detect PD = Power Delivery Features Supported in Schematics • DFP • USB Power Delivery Communication between Port partners • Provides cable flip support needed in chargers with receptacles 2-5 Type C Connector LIF-UC110 A B C D 0 0 0 12V 19.6V 0V 0 0 1 0 0 1 0 30 5 24 100nF 10V 47 46 34 13 40 14 17 15 16 19 18 4K7 7 4K7 CDONE CRESET_B 8 R22 Refer Note 5 VSEL1 VSEL2 VSEL3 VSEL4 VBUS_PG SPI_MISO SPI_MOSI SPI_SCK SPI_SS_B 20 10uF 10V 29 100R VCCPLL C11 C12 CLK_IN R18 3V3 0 VPP_2V5 33 22 1 CDONE CRESET_B IOB_2a IOB_0a IOT_44b IOB_24a RGB1 IOB_32a_SO IOB_33b_SI IOB_34a_SCK IOB_35b_CSN IOB_29b IOB_31b IOB_25b_G3 VCCPLL VCC VCC VPP2V5_Top VCCIO0 SPI_VCCIO1 VCCIO2 U1 VBUS_DSICHARGE_EN R4 5 4 1K C1 0.047uF VBUS Sense RGB0 IOT_41a IOT_42b IOB_6a IOB_9b IOT_38b IOT_36b IOT_46b_G0 IOT_51a IOT_39a IOT_43a IOB_20a IOB_18a IOT_50b IOT_49a IOT_45a_G1 IOT_37a IOB_8a IOB_16a IOB_13b IOT_48b VBUS_DET QFN48 DEVICE All VSEL* lines are programmable, they can be changed based on customer requirement. VSEL4 can be used to select another output voltage. 1 2 CDBU0520 1 D1 VSEL1 VSEL2 VSEL3 5V VBUS OUTPUT VOLTAGE SELECT LINES Config / Optional PMIC control via I2C R11 1V2 100nF 100nF 10V 10V 10uF 10V C7 C8 C6 1V2 100nF 100nF 100nF 10V 10V 10V C5 10uF 10V C4 C3 C2 3V3 Schematics VBUS_REF R13 R12 41 28 31 2 3 27 CC2_DET_PWM CC2_DET_REF CC1_DET_PWM CC1_DET_REF Q2 VBUS_SOURCE_EN N-Channel Q1 10m Current Monitor R1 100R R14 4K7 42R2 4.7nF 50V 3V3 CC1_INT Q6 N-Channel 1K R20 10V R19 VBUS_DSICHARGE_EN VBUS Q3 N-Channel 1W 100R R3 0.047uF 10V C15 3 4K7 R23 4K7 R24 5 7 4 2 9 1 IN2 NC2 NO2 NO1 NC1 IN1 TS5A23159RSER VCONN_5V VCONN_5V VCONN_5V VCONN SPDT Switch U2 COM2 COM1 6 330pF 330pF 16V 16V C14 CC2 CC1 C10 10 GND CC2 TYPE C CC1 VBUS 2 Date: Size B Friday,04-Sep-15 1 Sheet Project CD_PD_Charger_Non_Captive (Preliminary Schematics) Title CD_PD_Charger_Non_Captive Lattice Semiconductor Applications Email: techsupport@Latticesemi.com Phone (503) 268-8001 -or- (800) LATTICE Board Rev 1 of 1 A Schematic Rev 1.8 Notes:1) In case VBUS Current sensing is required, customer can contact Lattice tech support for current sense implementation. 2) CC1_RP and CC2_RP resistor value is dependent on current rating. It should be 36KOhm for standard device, 12KOhm for 1.5A device and 4.7KOhm for 3A device. 3)These values are as per Lattice LAB tests. Might need fine-tuning by customer to meet the Eye requirements 4)During configration Lattice device pins are weak pulled-up for time duration of 40ms. 5)RGB0, RGB1 and RGB2 are open drain pins, they required external pull-up. Q7 N-Channel 0.047uF 10V 3V3 CC2_INT 1K C16 0.047uF 4.7nF 50V C17 1 are not included in BOM Count Capacitor C10 and C14 are required to meet minimum reciever capacitance Q7 is for Device protection Q6 is for Device protection C18 42R2 C9 Sch Rev 1.7 Changes :1.Added VCONN SPDT switch for SOP' support. 1K R21 CC_RX_REF 35 CC2_RX CC2_DET CC2_TX_EN 42 25 4K7 100R R9 Refer Note 3 CC2_TX CC2_RP CC1_VCONN_EN CC1_RX CC1_DET CC2_VCONN_EN 26 32 11 10 38 43 37 23 4 R2 510K P-Channel 2 VBUS Power Control scheme shown is logical implmentation, for actual implementation please contact Lattice tech support. SOURCE Refer Note 3 R8 R6 CC1_TX_EN CC1_TX 6 9 CC1_RP 36 75K R7 510K R5 VBUS 3 VBUS Control section Components ISENSE Preliminary VBUS_SOURCE_EN 21 IOB_23b 12 IOB_22a VBUS_DET_PWM 44 IOB_3b_G6 45 IOB_5b 48 IOB_4a 4 V+ 8 GND 39 RGB2 TH_PAD 49 2-6 3 5 A B C D Architecture Lattice USB Type-C Solution Data Sheet Schematics Figure 2-5. USB CD/PD Charger Solution (Non-Captive Cable) Schematic Diagram Architecture Lattice USB Type-C Solution Data Sheet BOM Table 2-3. USB CD/PD Charger Solution (Non-Captive Cable) BOM Item Quantity 1 4 Reference Part 2 3 C2, C6, C12 10 uF CAP CER 10 uf 10 V 10% X5R 0805 3 6 C4, C5, C7, C3, C8, C11 100 nF CAP CER 100 nf 10 V 10% X5R 0402 4 2 C9, C17 4.7 nF CAP CER 4700 pF 10.V 5% U2J 0402 5 2 C10, C14 330 pF CAP CER 330 pF 16 V 10% X7R 0402 6 1 D1 CDBU0520 DIODE SCHOTTKY 20 V 500 MA 7 1 Q1 P-Channel MOSFET P-CH 20 V 6 A SOT-23 8 1 Q3 N-Channel MOSFET N-CH 20 V 6.3 A SOT-23 9 3 Q2, Q6, Q7 N-Channel MOSFET N-CH 30 V 0.85 A SOT23 10 4 R4, R19, R20 1K 11 2 R2, R5, R21 510K 12 6 R6, R12, R18, R22, R23, R24 13 2 R8, R13 100R 14 2 R9, R14 42.2R RES SMD 42.2 Ohm 1% 1/16 W 0402 15 1 R11 100R RES 100 Ohm 1/16 W 5% 0402 16 1 R3 100R RES SMD 100 Ohm 1% 1 W 2512 17 1 R7 75K 18 1 R1 10m 19 1 U1 LIF-UC 20 1 U2 TS5A23159RSER C1, C15, C16, C18 0.047 uF 4K7 DESCRIPTION CAP CER 0.047 uf 10 V 10% X5R 0402 RES 1K Ohm 1/16 W 5% 0402 RES 510K Ohm 1/16 W 5% 0402 RES 4.7K Ohm 1/16 W 5% 0402 RES SMD 100 Ohm 1% 1/16 W 0402 RES SMD 75 kOhm 5% 1/16 W 0402 RES 0.01 Ohm 1/2 W 1% 1206 LIF-UC 48-Pin Device Switch Dual SPDT BOM Count Table 2-4. USB CD/PD Charger Solution (Non-Captive Cable) BOM Count1, 2 Item Component Count 1 Cap 17 2 FET 2 3 Resistor 17 4 Lattice LIF-UC 1 5 Dual SPDT 1 1. VBUS control section components are not Included in the BOM count. 2. Diode D1 is not included in the BOM count. It is required only during onboard NVCM programming. 2-7 Architecture Lattice USB Type-C Solution Data Sheet CD/PD for Hosts/Devices Block Diagram Figure 2-6. CD/PD for Hosts/Devices Block Diagram Tx1/Rx1 USB Chipset SS Switch Tx/Rx Tx2/Rx2 Type-C Connector Video LIF-UC140 SPI IRPT AP/ CPU/ EC CD/PD Manager CD/PD PHY VBUS Power Control CC VBUS Power Control VBUS CD = Cable Detect PD = Power Delivery Features Supported in Schematics • Dual Role Port (DRP) • USB Power Delivery Communication between Port partners • SS/HS switch control • VBUS Source/Sink and Discharge Control signals • Alternate mode support • SPI Config interface is reused as SPI interface post configuration. SPI is used to interface PD to AP/Controller/Processor. 2-8 A B C H8 CM81 IOT_198_GBIN0 IOT_197_GBIN1 BANK0 CLK D8 E8 100nF C16 5 CM81 IOR_109 IOR_110 IOR_111 IOR_112 IOR_113 IOR_114 IOR_115 IOR_116 IOR_117 IOR_118 IOR_119 IOR_120 IOR_148 TP1 100nF C18 G6 H7 G7 F7 i/o's 100nF C20 AP/EC Optional CONFIGS & R47 4 1K D3 E3 100nF C10 H3 EC_INT EC_CS J8 J9 H9 G9 F8 G8 D6 A9 D7 E7 D9 B9 C9 R31 R32 R33 R34 SS SEL 36K 5K1 36K 5K1 DB_DISABLE CM81 3V3 IOL_13B_GBIN7 IOL_14A_GBIN6 BANK3 VCCIO_3 100K R37 IOL_2B IOL_2A IOL_3A IOL_3B IOL_7A IOL_7B IOL_10B IOL_10A IOL_13A IOL_14B IOL_22B IOL_22A IOL_24A IOL_24B IOL_26B IOL_26A IOB_82_GBIN4 IOB_81_GBIN5 IOB_103_CBSEL0 IOB_104_CBSEL1 CDONE CRESET_B BANK2 B2 C2 B1 C1 D2 C3 E1 D1 E2 E4 F3 F1 G3 G1 H2 G2 IOB_54 IOB_55 IOB_56 IOB_57 IOB_70 VBUS_DET_PWM VBUS_IN CC2_RX_REF 7 CC1_RX_REF 1 100nF C19 U3 R22 R21 510K 510K 2 5 6 3 COMP_2CH 3V3 510K 510K R13 R12 3V3 4 3 2 510K R6 Q7 R15 Q4 P-Channel Q1 P-Channel VBUS N-Channel 100R R46 Refer note 3 4 1 A 10K EN_CC2 U5 4 SN74LV1T04DCKR Y 2 Q13 N-Channel Q10 Size B 510K R36 DNI C12 P-Channel 5K1 R41 R42 CC2 CC1 CC2 CC1 Q11 5K1 330pF 330pF DNI C11 8 5 7 6 VCONN_5V Friday,04-Sep-15 1 Sheet Project CD_PD_Hosts_Devices (Preliminary schematics) Title CD_PD_Hosts_Devices Date: S2 S1 GND VDD Lattice Semiconductor Applications Email: techsupport@Latticesemi.com Phone (503) 268-8001 -or- (800) LATTICE Batttery P-Channel 510K R35 Q8 and Q9 are for Device protection Dead Q9 N-Channel U6 SLG59M1599 D2 D1 ON2 ON1 Switch 3 0R 2 0R VCONN R45 VCONN_5V CC2_VCONN_EN CC1_VCONN_EN Q8 N-Channel 10K EN_CC1 VCONN_5V EN_CC2 2 1 NC R44 R43 3V3 3V3 N-Channel Q2 P-Channel VBUS 510K R7 GND CC2 CC1 VBUS Board Rev 1 of 1 A Schematic Rev 1.7 TYPE C GND VBUS Control section Components are not included in BOM Count Q6 N-Channel VBUS_SINK_EN Q3 P-Channel Q5 VBUS_SOURCE_EN SOURCE SINK VBUS DISCHARGE CC1_INT 1 VBUS Power Control scheme shown is logical implmentation, for actual implementation please contact Lattice tech support. Capacitor C11 and C12 are required to meet minimum reciever capacitance 510K 510K R19 R17 VBUS CC2_INT 3V3 CC1_VCONN_EN CC2_VCONN_EN R39 0.047uF 10V C22 510K 510K R20 R18 Refer Note 5 R16 R14 510K 510K VBUS_DET 3V3 Refer Note 7 510K 510K R9 VBUS_SOURCE_EN VBUS_SINK_EN BMC RX Comparators 1nF C13 1nF C9 1nF C7 R11 R10 510K 510K R8 CC2_INT Refer Note 4 CC1_INT VBUS SENSING 100R 42R2 4.7nF 10V C5 4.7nF 10V 100R 42R2 R4 R5 C4 R1 R3 Refer Note 4 VBUS_REF CC2_TX CC2_TX_EN CC1_TX CC1_TX_EN CC1_DET_REF CC1_DET CC1_DET_PWM VBUS_DISCHARGE_EN CC2_DET_REF CC2_DET CC2_DET_PWM H1 J1 J2 J3 J4 3 1) CC1_RP and CC2_RP resistor value is dependent on current rating. It should be 36Kohms for standard device, 12Kohms R38 for 1.5A device and 4.7KOhms for 3A device. N-Channel 2) Discrete FET based logic can also be used instead of SPDT switch (U2)Contact Lattice tech support for details 5K1 3) VCONN_5V should be sequenced, It should come after Lattice device is configured. 5K1 4) These values are as per Lattice LAB tests. Might need fine-tuning by customer to meet the Eye requirements. 5)Regressive LAB tests ongoing for Sigma Delta ADC 6)During configration Lattice device pins are weak pulled-up for time duration of 40ms. 7)Incase VBUS is greater than 5V, Adjust R19 to map the voltage across R19 is not greter than to 3.3V. Q12 8)BMC RX reference can be generated with internal PWM, To do that mount R47 component, R23 as DNI and replace R26 with 47nF capacitor. Notes:- CC2_RP CC2_RD CC1_RP CC1_RD SS_SEL1 SS_SEL2 SS_SEL3 U1C VCCIO_2 CM81 U1D H4 G4 CDONE CRESET_B 3V3 G5 H5 E6 H6 5K1 J5 100nF R40 C1 3V3 SS Switch selection signals HPD 100nF C17 B8 A8 A7 B7 B6 A6 B5 A4 B4 D5 E5 A3 B3 A2 A1 IOB_105_SDO IOB_106_SDI IOB_107_SCK IOB_108_SS IOR_141_GBIN2 IOR_140_GBIN3 BANK1 VCCIO_1 U1B 1uF 10uF C6 C15 C14 IOT_170 IOT_174 IOT_177 IOT_180 IOT_183 IOT_185 IOT_188 IOT_208 IOT_211 IOT_212 IOT_214 IOT_217 IOT_218 IOT_221 IOT_224 CM81 SPI VCC_SPI U1E Configuration GNDPLL0 GND GND GND GND CM81 VCCIO_0 U1A 1V2 C4 C5 CLK_IN 100nF C21 3V3 A5 100nF C8 3V3 100nF C6 3V3 10uF100nF J6 10V GNDPLL0 10V F9 F4 F5 F6 POWER 3V3 CDBU0520 D1 VPP_2V5 2 1 VPP_FAST 1V2 1 C3 F2 D4 E9 C8 C7 SPI_MISO C2 VCC VCC VCC VPP_2V5 VPP_FAST SPI_MOSI VCCPLL0 SPI_SCK U1F CC_RX_REF J7 100R VCCPLL0 SPI_SS_B D R2 Schematics 8 4 5 CC_RX_REF Preliminary 5 V G 3 2-9 EN_CC1 1V2 A B C D Architecture Lattice USB Type-C Solution Data Sheet Schematics Figure 2-7. CD/PD for Hosts/Devices Schematic Diagram Architecture Lattice USB Type-C Solution Data Sheet BOM Table 2-5. CD/PD for Hosts/Devices BOM Item Quantity 1 11 C1,C3,C6,C8,C10,C16,C17,C18, C19,C20,C21 Reference 100 nF Part CAP CER 100nf 10V 10% X5R 0402 Description 2 2 C2,C14 10 uF CAP CER 10uf 10V 10% X5R 0805 3 2 C4,C5 4.7 nF CAP CER 4700PF 10V 5% U2J 0402 4 3 C7,C9,C13 1 nF CAP CER 1000PF 10V 10% X5R 0402 5 2 C11,C12 330 pF CAP CER 330PF 16V 10% X7R 0402 6 1 C15 1 uF CAP CER 1uf 10V 10% X5R 0402 7 1 C22 0.047uF CAP CER 0.047uf 10V 10% X5R 0402 8 1 D1 CDBU0520 DIODE SCHOTTKY 20V 500MA 0603 9 4 Q1,Q2,Q3,Q4 P-Channel MOSFET P-CH 20V 6A SOT-23 10 6 Q5,Q6,Q8,Q9,Q12,Q13 N-Channel MOSFET N-CH 30V 0.85A SOT23 11 1 Q7 N-Channel MOSFET N-CH 20V 6.3A SOT-23 12 2 Q10,Q11 P-Channel MOSFET P-CH 20V 760MA SOT-416 13 2 R1,R4 100R RES SMD 100 OHM 1% 1/16W 0402 14 1 R2 100R RES 100 OHM 1/16W 5% 0402 15 2 R3,R5 42R2 RES SMD 42.2 OHM 1% 1/16W 0402 16 18 R6,R7,R8,R9,R10,R11,R12,R13, R14,R16,R17,R18,R19,R20,R21, R22,R35,R36 510K RES 510K OHM 1/16W 5% 0402 17 1 R15 100R RES SMD 100 OHM 1% 1W 2512 18 2 R31,R33 36K RES 36K OHM 1/16W 5% 0402 19 7 R32,R34,R38,R39,R40,R41,R42 5K1 RES 5.1K OHM 1/16W 5% 0402 20 1 R37 100K RES 100K OHM 1/16W 5% 0402 21 2 R43,R44 10K RES 10K OHM 1/16W 5% 0402 22 2 R45,R46 0R RES 0.0 OHM 1/16W JUMP 0402 23 1 R47 1K Thick Film Resistors - SMD 1/16watt 1.0Kohms 1% 24 1 U1 LIF-UC LIF-UC 81-Pin Device 25 1 U3 COMP_2CH Analog Comparators Dual,40ns,microPower RRI Comparator 26 1 U5 SN74LV1T04DCKR IC BUFFER GATE SGL CMOS SC70-5 27 1 U6 SLG59M1599 Ultra-small Dual 40 mO 1.0 A GreenFET 3 Load Switch 2-10 Architecture Lattice USB Type-C Solution Data Sheet BOM Count Table 2-6. CD/PD for Hosts/Devices BOM Count1, 2 Item Component Count 1 CAP 22 2 FET 6 3 Resistor 36 4 Load Switch 1 5 Level Translator 1 6 Comparator 1 7 Lattice LIF-UC 1 1. VBUS control section components are not Included in the BOM count. 2. Diode D1 is not included in the BOM count. It is required only during onboard NVCM programming. 2-11 Lattice USB Type-C Solution Data Sheet DC and Switching Characteristics August 2016 Data Sheet DS1052 Absolute Maximum Ratings1, 2, 3 Supply Voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 1.42 V Output Supply Voltage VCCIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.60 V NVCM Supply Voltage VPP_2V5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.60 V PLL Supply Voltage VCCPLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 1.42 V I/O Tri-state Voltage Applied. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.60 V Dedicated Input Voltage Applied . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.60 V Storage Temperature (Ambient). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65 °C to 150 °C Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65 °C to 125 °C 1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. 2. Compliance with the Lattice Thermal Management document is required. 3. All voltages referenced to GND. Recommended Operating Conditions1 Symbol Parameter 1 VCC Core Supply Voltage Slave SPI Configuration VPP_2V5 Min. Max. Units 1.14 1.26 V 1.71 4 3.46 V VPP_2V5 NVCM Programming and Operating Supply Voltage Master SPI Configuration 2.30 3.46 V Configuration from NVCM 2.30 3.46 V NVCM Programming 2.30 3.00 V I/O Driver Supply Voltage VCCIO_0, SPI_VCCIO1, VCCIO_2 1.71 3.46 V PLL Supply Voltage 1.14 1.26 V Junction Temperature Commercial Operation 0 85 °C VCCIO1, 2, 3 VCCPLL tJCOM tJIND Junction Temperature Industrial Operation –40 100 °C tPROG Junction Temperature NVCM Programming 10.00 30.00 °C 1. Like power supplies must be tied together if they are at the same supply voltage and they meet the power up sequence requirement. Please refer to Power-Up Supply Sequencing section. VCC and VCCPLL are recommended to tie to same supply with an RC-based noise filter between them. Please refer to TN1252, iCE40 Hardware Checklist. 2. See recommended voltages by I/O standard in subsequent table. 3. VCCIO pins of unused I/O banks should be connected to the VCC power supply on boards. 4. VPP_2V5 can, optionally, be connected to a 1.8 V (+/-5%) power supply in Slave SPI Configuration mode subject to the condition that none of the HFOSC/LFOSC and RGB LED / IR LED driver features are used. Otherwise, VPP_2V5 must be connected to a power supply with a minimum 2.30 V level. Power Supply Ramp Rates1, 2 Symbol tRAMP Parameter Power supply ramp rates for all power supplies. Min. Max. Units 0.6 10 V/ms 1. Assumes monotonic ramp rates. 2. Power up sequence must be followed. Please refer to Power-Up Supply Sequencing section. © 2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 3-1 DS1052 Architecture_01.2 DC and Switching Characteristics Lattice USB Type-C Solution Data Sheet Power-On Reset All iCE40 Ultra devices have on-chip Power-On-Reset (POR) circuitry to ensure proper initialization of the device. Only three supply rails are monitored by the POR circuitry as follows: (1) VCC, (2) SPI_VCCIO1 and (3) VPP_2V5. All other supply pins have no effect on the power-on reset feature of the device. Note that all supply voltage pins must be connected to power supplies for normal operation (including device configuration). Power-Up Supply Sequencing It is recommended to bring up the power supplies in the following order. Note that there is no specified timing delay between the power supplies, however, there is a requirement for each supply to reach a level of 0.5V, or higher, before any subsequent power supplies in the sequence are applied. 1. VCC and VCCPLL should be the first two supplies to be applied. Note that these two supplies can be tied together subject to the recommendation to include a RC-based noise filter on the VCCPLL (Please refer to TN1252, iCE40 Hardware Checklist.) 2. SPI_VCCIO1 should be the next supply, and can be applied any time after the previous supplies (VCC and VCCPLL) have reached as level of 0.5 V or higher. 3. VPP_2V5 should be the next supply, and can be applied any time after previous supplies (VCC, VCCPLL and SPI_VCCIO1) have reached a level of 0.5 V or higher. 4. Other Supplies (VCCIO0 and VCCIO2) do not affect device power-up functionality, and they can be applied any time after the initial power supplies (VCC and VCCPLL) have reached a level of 0.5 V or greater. There is no power down sequence required. However, when partial power supplies are powered down, it is required the above sequence to be followed when these supplies are repowered up again. External Reset When all power supplies have reached to their minimum operating voltage defined in Minimum Operation Condition Table, it is required to either keep CRESET_B LOW, or toggle CRESET_B from HIGH to LOW, for a duration of tCRESET_B, and release it to go HIGH, to start configuration download from either the internal NVCM or the external Flash memory. Figure 3-1 shows Power-Up sequence when SPI_VCCIO1 and VPP_2V5 are connected separately, and the CRESET_B signal triggers configuration download. Figure 3-2 shows when SPI_VCCIO1 and VPP_2V5 connected together. All power supplies should be powered up during configuration. Before and during configuration, the I/Os are held in tri-state. I/Os are released to user functionality once the device has finished configuration. Figure 3-1. Power Up Sequence with SPI_VCCIO1 and VPP_2V5 Not Connected Together VSUPPLY(MIN) VPP_2V5, VCCIO0 and VCCIO2= 2.5 V / 3.3 V SPI_VCCIO1 = 1.8 V VCC/VCC_PLL = 1.2 V CRESET_B tCRESET_B 0.5 V 3-2 DC and Switching Characteristics Lattice USB Type-C Solution Data Sheet Figure 3-2. Power Up Sequence with All Supplies Connected Together SPI_VCCIO, VPP_2V5, VCCIO0 and VCCIO2= 1.8 V / 2.5 V / 3.3 V VSUPPLY(MIN) VCC/VCC_PLL = 1.2 V tCRESET_B CRESET_B 0.5 V Power-On-Reset Voltage Levels1 Symbol VPORUP VPORDN Parameter Power-On-Reset ramp-up trip point (circuit monitoring VCC, SPI_VCCIO1, VPP_2V5) Power-On-Reset ramp-down trip point (circuit monitoring VCC, SPI_VCCIO1, VPP_2V5) Min. Max. Units VCC 0.62 0.92 V SPI_VCCIO1 0.87 1.50 V VPP_2V5 0.90 1.53 V VCC — 0.79 V SPI_VCCIO1 — 1.50 V VPP_2V5 — 1.53 V 1. These POR trip points are only provided for guidance. Device operation is only characterized for power supply voltages specified under recommended operating conditions. ESD Performance Please contact Lattice Semiconductor for additional information. DC Electrical Characteristics Over Recommended Operating Conditions Symbol Parameter Min. Typ. Max. Units IIL, IIH1, 3, 4 Input or I/O Leakage 0V < VIN < VCCIO + 0.2 V — — +/–10 µA C1 I/O Capacitance, excluding LED Drivers2 VCCIO = 3.3 V, 2.5 V, 1.8 V VCC = Typ., VIO = 0 to VCCIO + 0.2 V — 6 — pF C2 Global Input Buffer Capacitance2 VCCIO = 3.3 V, 2.5 V, 1.8 V VCC = Typ., VIO = 0 to VCCIO + 0.2 V — 6 — pF C3 RGB Pin Capacitance2 VCC = Typ., VIO = 0 to 3.5 V — 15 — pF C4 IRLED Pin Capacitance2 VCC = Typ., VIO = 0 to 3.5 V — 53 — pF VHYST Input Hysteresis VCCIO = 1.8 V, 2.5 V, 3.3 V — 200 — mV –3 –8 –11 — –31 –72 –128 µA IPU Internal PIO Pull-up Current Condition VCCIO = 1.8 V, 0=