CrossLink LIF-MD6000 Master Link Board Revision B
Evaluation Board User Guide
FPGA-EB-02010-1.6
September 2021
CrossLink LIF-MD6000 Master Link Board - Revision B
Evaluation Board User Guide
Disclaimers
Lattice makes no warranty, representation, or guarantee regarding the accuracy of information contained in this document or the suitability of its
products for any particular purpose. All information herein is provided AS IS, with all faults and associated risk the responsibility entirely of the Buyer.
Buyer shall not rely on any data and performance specifications or parameters provided herein. Products sold by Lattice have been subject to limited
testing and it is the Buyer's responsibility to independently determine the suitability of any products and to test and verify the same. No Lattice
products should be used in conjunction with mission- or safety-critical or any other application in which the failure of Lattice’s product could create a
situation where personal injury, death, severe property or environmental damage may occur. The information provided in this document is
proprietary to Lattice Semiconductor, and Lattice reserves the right to make any changes to the information in this document or to any products at
any time without notice.
© 2016-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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CrossLink LIF-MD6000 Master Link Board - Revision B
Evaluation Board User Guide
Contents
Acronyms in This Document ................................................................................................................................................. 5
1. Introduction .................................................................................................................................................................. 6
2. Headers and Test Connections ..................................................................................................................................... 8
3. Programming Circuit ..................................................................................................................................................... 9
3.1.
Bridging Circuit .................................................................................................................................................... 9
3.2.
I2C Expander ...................................................................................................................................................... 10
4. Power Supply .............................................................................................................................................................. 11
5. Status Indicators ......................................................................................................................................................... 13
6. SMA I/O Link Board .................................................................................................................................................... 14
7. Breakout I/O Link Board ............................................................................................................................................. 16
8. Ordering Information ................................................................................................................................................. 19
Appendix A. LIF-MD6000-ML-EVN-BRD Schematics ........................................................................................................... 20
Appendix B. LIF-MD6000-ML-EVN-BRD Bill of Materials .................................................................................................... 28
Appendix C. SMA-IOL-EVN-BRD Schematics ....................................................................................................................... 37
Appendix D. SMA-IOL-EVN-BRD Bill of Materials ............................................................................................................... 38
Appendix E. B-IOL-EVN-BRD Schematics ............................................................................................................................ 39
Appendix F. B-IOL-EVN-BRD Bill of Materials ..................................................................................................................... 40
References .......................................................................................................................................................................... 41
Technical Support Assistance ............................................................................................................................................. 42
Revision History................................................................................................................................................................... 43
© 2016-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02010-1.6
3
CrossLink LIF-MD6000 Master Link Board - Revision B
Evaluation Board User Guide
Figures
Figure 1.1. Top View of Master Link Rev B Board and its Key Components .........................................................................6
Figure 1.2. Bottom View of Master Link Rev B Board ...........................................................................................................7
Figure 3.1. Programming Block .............................................................................................................................................9
Figure 3.2. Bridging Block ...................................................................................................................................................10
Figure 3.3. I2C Expander Block ............................................................................................................................................10
Figure 4.1. Power Supply Block ...........................................................................................................................................11
Figure 6.1. Top View of SMA I/O Link Board .......................................................................................................................15
Figure 6.2. Bottom View of SMA I/O Link Board.................................................................................................................15
Figure 7.1. Top View of Breakout I/O Link Board ...............................................................................................................18
Figure 7.2. Bottom View of Breakout I/O Link Board .........................................................................................................18
Figure A.1. LIF-MD6000 Master Link Rev B Board Block Diagram ......................................................................................20
Figure A.2. FTDI Interface ...................................................................................................................................................21
Figure A.3. Power Regulator Interface................................................................................................................................22
Figure A.4. MIPI Block – MIPI Tx .........................................................................................................................................23
Figure A.5. Bank 1, 2 – LVDS Rx ..........................................................................................................................................24
Figure A.6. Bank0, Flash Interface ......................................................................................................................................25
Figure A.7. I2C Expander .....................................................................................................................................................26
Figure A.8. Layout Guidelines .............................................................................................................................................27
Figure C.1. SMA Debug Board .............................................................................................................................................37
Figure E.1. 100MILS_DEBUG Header ..................................................................................................................................39
Tables
Table 2.1. Headers and Test Connectors ..............................................................................................................................8
Table 4.1. Power LEDs.........................................................................................................................................................11
Table 4.2. Device Power Rail Summary and Test Points .....................................................................................................12
Table 5.1. Status LED I/O Map ............................................................................................................................................13
Table 6.1. Headers and Test Connectors ............................................................................................................................14
Table 6.2. U1 Connector Description ..................................................................................................................................14
Table 7.1. Headers and Test Connectors ............................................................................................................................16
Table 7.2. U1 Connector Description ..................................................................................................................................16
Table 7.3. J2 Header Description ........................................................................................................................................17
Table 8.1. Ordering Information .........................................................................................................................................19
© 2016-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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CrossLink LIF-MD6000 Master Link Board - Revision B
Evaluation Board User Guide
Acronyms in This Document
A list of acronyms used in this document.
Acronym
Definition
CMOS
CSI-2
DSI
FTDI
I2 C
I/O
LVDS
MIPI
SPI
Complementary Metal-Oxide Semiconductor
Camera Serial Interface
Display Serial Interface
Future Technology Devices International
Inter-Integrated Circuit
Input/Output
Low-Voltage Differential Signaling
Mobile Industry Processor Interface
Serial Peripheral Interface
© 2016-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02010-1.6
5
CrossLink LIF-MD6000 Master Link Board - Revision B
Evaluation Board User Guide
1. Introduction
This document describes the Lattice Semiconductor CrossLink™ LIF-MD6000 Master Link Board – Revision B that
supports a variety of demos, encompassing different signaling logic standards bridging with MIPI® CSI-2/DSI interface.
The board‘s key component is the CrossLink Family device that features built in MIPI D-PHY hard blocks to support
different bridging solutions.
For the latest information about this board, including optional Tx/Rx Link boards, demo files, further documentation
and more, see the Lattice website at: www.latticesemi.com/masterlink.
For details about the CrossLink device, refer to CrossLink Family Data Sheet (FPGA-DS-02007).
The content of this user guide includes descriptions of on-board jumper settings, programming circuit, a complete set
of schematics, and bill of materials for LIF-MD6000 Master Link Rev B board.
Refer to Appendix A, B, C, D, E, F for the schematics and BOM of the CrossLink LIF-MD6000 Master Link Rev B board
and the schematics and BOMs of the Breakout I/O Link and SMA I/O Link boards that are included in the demo kit.
Circuits on the development kit board:
Programming Circuit
Mini USB Type-B connector to FTDI
FTDI to CrossLink using SPI
FTDI to XO3LF device using JTAG
CrossLink
MIPI CSI-2/DSI hard block
Bridging of multiple signaling standards
SPI flash configuration
General Purpose Input/Output
LED display
LCMXO3LF-1300E
I2C muxing
Figure 1.1 shows the top view of the LIF-MD6000 Master Link Rev B board and its key components. Figure 1.2 shows
the bottom view of the board.
Tx Connectors 1 and 2 (U9, U7)
XO3 Reset (SW3)
Power Switch (SW1)
Power LEDs
External Power Input
LCMXO3L-1300E (U19)
Debug Header (J18)
External Power Jack (J3)
LIF-MD6000-CSFBGA81
Bank 1, 2 Voltage Selection
Headers (J24, J25)
Debug and
Configuration LEDs
USB 2.0 Mini-B (J2)
Reset and wake-up buttons
Switch (SW2)
JTAG Header (J1)
External Clock SMA Inputs
FTDI Chip (U1)
SPI Flash Device (U14)
Rx Connectors (U11, U12)
Clock Source Selection (J26, J27)
Figure 1.1. Top View of Master Link Rev B Board and its Key Components
© 2016-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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CrossLink LIF-MD6000 Master Link Board - Revision B
Evaluation Board User Guide
Figure 1.2. Bottom View of Master Link Rev B Board
© 2016-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02010-1.6
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CrossLink LIF-MD6000 Master Link Board - Revision B
Evaluation Board User Guide
2. Headers and Test Connections
Figure 1.1 shows the top view of the Master Link Rev B board. The headers and test connections on the board provide
access to LIF-MD6000 Master Link demo board circuits. Table 2.1 lists the headers and test connectors.
Table 2.1. Headers and Test Connectors
Part
Description
Setting
J1
External JTAG interface – For LCMXO3 only
—
J2
Mini-B USB connector
—
J3
External power jack
—
J4
External clock input for MIPI D-PHY reference clock
J7
SW2 selector
J8
External 12 V terminal block
Open
Open
—
OPEN-NOP, SHORT-CONFIGURATION RESET
J9
External 5 V terminal block
J18
External SP/I2C access
J19
SPI Flash chip select
OPEN-OFF, SHORT-ON
J20
LIF-MD6000 chip select
OPEN-OFF, SHORT-ON
J22
External reference clock input for MIPI D-PHY reference clock
—
J23
Debug Header for LCMXO3L device
—
J24
VCCIO1 Bank voltage selector
1-2 (2.5 V), 2-3 (3.3 V), 2-4 (1.2 V)
J25
VCCIO2 Bank voltage selector
1-2 (2.5 V), 2-3 (3.3 V), 2-4 (1.2 V)
J26
Internal/External clock and I2C SDA Mux
J27
Internal/External reference clock and I2C SCL Mux
J28
Reveal analyzer signal connector
—
1-2 (CLK_INT), 2-3 (CLK_EXT), 2-4 (SDA)
1-2 (CLK_INT_REF), 2-3 (CLK_EXT_REF), 2-4 (SCL)
—
J29
Reset signal voltage selector
SW1
External adaptor power ON/OFF
1-2 (VCCIO2), 2-3 (VCCIO0)
—
SW2
Configuration reset for LIF-MD6000
—
SW3
External reset for LCMXO3L device
—
SW4*
External reset for LIF-MD6000 device
—
SW5
PMU WAKEUP Switch
—
U7
Tx Connectors for external interface
—
U9
Tx Connectors for external interface
—
U11
Rx Connectors for external interface
—
U12
Rx Connectors for external interface
—
*Note:
Some CrossLink demos utilize this reset signal to ball G9 of Bank 2 while it is configured as a 1.2 V Bank. However, LVCMOS12
inputs are no longer supported across all 3 Banks. Lattice Diamond® Software 3.9 and later does not allow this signal to be placed on
a 1.2 V Bank. If it is necessary to recompile one of these demo projects, the necessary modifications should be made to the project
and the board to move this reset signal to a non-1.2 V Bank on CrossLink.
© 2016-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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CrossLink LIF-MD6000 Master Link Board - Revision B
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3. Programming Circuit
The Mini-B USB connector is used for programming the board by using Lattice Diamond Programmer software.
Figure 3.1 shows the programming block of LIF-MD6000 Master Link Rev B board.
The Mini-B USB connector interfaces to the FTDI FT2232H IC. The FTDI IC works with Diamond programmer software to
provide interfaces for:
JTAG – to program MachXO3 LCMXO3LF-1300E
SPI – to program both CrossLink, and SPI Flash Memory
SPI Flash (U14)
SPI
USB Mini-B
(J2)
LIF-MD6000
CSFBGA81 (U8)
FTDI Chip (U1)
JTAG
LCMXO3LF-1300E
MG121 (U19)
Figure 3.1. Programming Block
3.1. Bridging Circuit
Figure 3.2 shows the block diagram of bridging of different standard interfaces. The CrossLink device is used as a
bridging device that supports a variety of I/O standards. This demo board supports development of the following
interface bridges:
1:1 MIPI DSI Display Interface Bridge
1:2 MIPI DSI Display Interface Bridge
2:1 MIPI CSI-2 Image Sensor Aggregator Bridge
CMOS to MIPI CSI-2 Image Sensor Interface Bridge
MIPI CSI-2 to CMOS Image Sensor Interface Bridge
MIPI DSI to CMOS Display Interface Bridge
OpenLDI LVDS to MIPI DSI Display Interface Bridge
CMOS to MIPI DSI Display Interface Bridge
© 2016-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02010-1.6
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CrossLink LIF-MD6000 Master Link Board - Revision B
Evaluation Board User Guide
Tx Connector 1
D-PHY I/F
D-PHY Rx/
LVDS/CMOS
Rx Connector 1
LIF-MD6000
CSFBGA81 (U8)
Tx Connector 2
D-PHY Rx/
LVDS/CMOS
D-PHY I/F
Rx Connector 2
Figure 3.2. Bridging Block
3.2. I2C Expander
Figure 3.3 shows the block diagram of the I2C expander. The LCMXO3LF-1200E device is used as an I2C expander and it
supports a single master and multiple slave devices connected to the board. The master I2C interface is connected to
the Tx header and the slave device I2C interface is connected to the Rx connectors supporting any slave device access
from the master based on the slave address.
2 X I2C
Rx Connector 1
Tx
H
e
a
d
e
r
I2C
LCMXO3LF-1200EMG121 (U19)
2 X I2C
Rx Connector 2
LIF-MD6000
CSFBGA81 (U8)
Figure 3.3. I2C Expander Block
© 2016-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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CrossLink LIF-MD6000 Master Link Board - Revision B
Evaluation Board User Guide
4. Power Supply
The power supply to the development kit is provided by the Mini-B USB connector or from an external adaptor.
Figure 4.1 shows the power supply block of the CrossLink LIF-MD6000 Master Link Rev B board. The external adaptor
provides 12 V power source through voltage regulators on the board to CrossLink and LCMXO3LF-1300E, as well as to
the external boards connected to Tx and Rx Headers. The Mini-B USB connector provides 5 V to the various voltage
regulators and is also used for device programming. Each I/O and core voltage rail on the board is accessible by a test
point on the board. The current flowing to each rail can be measured using a 1 Ω resistor placed in the path of each
voltage rail.
U18
J3
12 V
12 V to 5 V
converter
5V
Power adaptor
J2
U15
LDO
1.2 V
U5
5V
LDO
3.3 V
Mini-B USB
U6
LDO
2.5 V
U17
LDO
1.8 V
Figure 4.1. Power Supply Block
Table 4.1 lists the device power rails. There are five voltage regulators on the board used to supply the 5 V, 3.3 V, 2.5 V,
1.8 V, and 1.2 V rails. The input to these regulators is either from the Mini-B USB connector (J2), an external 12 V
adaptor (J3), or an external power supply to the terminal blocks of J8 or J9. Switch SW1 is used to connect or
disconnect the external 12 V adaptor power to the board.
Table 4.1. Power LEDs
Voltage Rail
12
5
3.3
2.5
1.8
1.2
LEDs
D26
D3
D25
D29
D28
D27
Color
Green
Green
Green
Green
Green
Green
© 2016-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02010-1.6
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CrossLink LIF-MD6000 Master Link Board - Revision B
Evaluation Board User Guide
Table 4.2 lists the board voltage rails, including the rail source voltage, test point number, and current sense resistor
number.
Table 4.2. Device Power Rail Summary and Test Points
Voltage Rail
Source Rail
Current Sense Resistor
Test Points
12 V
—
—
12V0
5V
12 V
—
5V0
+3.3 V
5V
—
3V3
+2.5 V
5V
—
2V5
+1.8 V
5V
—
—
+1.2 V
5V
—
1V2
VCCCORE
+1.2 V
R19
VCC_CORE1
VCCIO0
+2.5 V/+3.3 V
R20/R24
VCCIO0
VCCIO1
+1.2 V/+2.5 V/+3.3 V
R21/R25/R434/R448
VCCIO1
VCCIO2
+1.2 V/+2.5 V/+3.3 V
R28/R33/R435/R449
VCCIO2
VCC_DPHY
+1.2 V
R417
VCC_DPHY
1K_VCC_CORE
1.2 V
R190
1K_VCC_CORE1
1K_VCCIO0
+2.5 V/+3.3 V
R410/R411
1K_VCCIO0
1K_VCCIO1
+2.5 V/+3.3 V
R184/R185
1K_VCCIO1
1K_VCCIO2
+2.5 V/+3.3 V
R186/R187
1K_VCCIO2
1K_VCCIO3
+2.5 V/+3.3 V
R188/R189
1K_VCCIO3
© 2016-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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CrossLink LIF-MD6000 Master Link Board - Revision B
Evaluation Board User Guide
5. Status Indicators
The LED status indicators on the board show power, configuration, and application status. Table 5.1 lists the status LED
I/O map.
Table 5.1. Status LED I/O Map
Device
LED
Net Name
Color
CrossLink
D6
CMOS_IO_1
Blue
CrossLink
D7
CMOS_IO_2
Blue
CrossLink
D8
CMOS_IO_3
Blue
CrossLink
D9
CMOS_IO_4
Blue
CrossLink
D10
CDONE
Green
LCMXO3LF-1300E
D23
DONE
Red
© 2016-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02010-1.6
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CrossLink LIF-MD6000 Master Link Board - Revision B
Evaluation Board User Guide
6. SMA I/O Link Board
The SMA I/O Link board connects to the CrossLink LIF-MD6000 Master Link Rev B board’s Tx or Rx connectors (U7, U9,
U11 or U12) and transfers signals to the respective SMA connectors.
Table 6.1. Headers and Test Connectors
Part
J1
J2
J3
J4
J5
J6
J7
J8
J9
Description
SMA connector for DCK_TX_P
SMA connector for DCK_TX_N
SMA connector for DATA0_TX_P
SMA connector for DATA0_TX_N
SMA connector for DATA1_TX_P
SMA connector for DATA1_TX_N
SMA connector for DATA2_TX_P
SMA connector for DATA2_TX_N
SMA connector for DATA3_TX_P
Mapping to U1
Pin 1
Pin 2
Pin 4
Pin 5
Pin 7
Pin 8
Pin 13
Pin 14
Pin 16
J10
J11
J12
J13
J14
U1
SMA connector for DATA3_TX_N
SMA connector for DATA4_TX_P
SMA connector for DATA4_TX_N
SMA connector for DATA5_TX_P
SMA connector for DATA5_TX_N
Connector to interface to CrossLink Master Link Rev B board
Pin 17
Pin 24
Pin 25
Pin 27
Pin 28
N/A
Table 6.2. U1 Connector Description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Name
CH4_DCK_P
CH4_DCK_N
GND
CH4_DATA0_P
CH4_DATA0_N
GND
CH4_DATA1_P
CH4_DATA1_N
GND
SN
SCLK
GND
CH4_DATA2_P
CH4_DATA2_N
GND
CH4_DATA3_P
CH4_DATA3_N
GND
12V
12V
Pin
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Name
TBD
RESETN
PWR_5-0V
GND
GND
PWR_3-3V
GND
GND
PWR_1-8V
MOSI
MISO
PWR_1-8V
GND
GND
PWR_3-3V
GND
GND
PWR_5-0V
SDA
SCL
Note: U1 connector pin names may be different than the actual signal depending on which CrossLink LIF-MD6000 Master Link Rev B
board connector this daughter board is connected to.
© 2016-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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CrossLink LIF-MD6000 Master Link Board - Revision B
Evaluation Board User Guide
Figure 6.1. Top View of SMA I/O Link Board
Figure 6.2. Bottom View of SMA I/O Link Board
© 2016-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02010-1.6
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CrossLink LIF-MD6000 Master Link Board - Revision B
Evaluation Board User Guide
7. Breakout I/O Link Board
The Breakout I/O Link board connects to the CrossLink LIF-MD6000 Master Link Rev B board’s Tx or Rx connectors (U7,
U9, U11 or U12) and transfers signals to the 26-pin header (J2).
Table 7.1. Headers and Test Connectors
Part
Description
Setting
J2
13x2 Header
—
U1
Connector to interface to CrossLink Master Link Rev B board
—
Table 7.2. U1 Connector Description
Pin
Connector Pin Name
Net Name
Pin
Connector Pin Name
Net Name
TBD
NC
1
CH4_DCK_P
CH4_DCK_TX_P
21
2
CH4_DCK_N
CH4_DCK_TX_N
22
RESETN
RESETN
3
GND
GND
23
PWR_5-0V
+5V
4
CH4_DATA0_P
CH4_DATA0_TX_P
24
GND
CH4_DATA4_TX_P
GND
CH4_DATA4_TX_N
5
CH4_DATA0_N
CH4_DATA0_TX_N
25
6
GND
GND
26
PWR_3-3V
+3.3V
7
CH4_DATA1_P
CH4_DATA1_TX_P
27
GND
CH4_DATA5_TX_P
8
CH4_DATA1_N
CH4_DATA1_TX_N
28
GND
CH4_DATA5_TX_N
9
GND
GND
29
PWR_1-8V
+1.8V
10
SN
SN
30
MOSI
MOSI
11
SCLK
SCLK
31
MISO
MISO
PWR_1-8V
+1.8V
12
GND
NC
32
13
CH4_DATA2_P
CH4_DATA2_TX_P
33
GND
GND
14
CH4_DATA2_N
CH4_DATA2_TX_N
34
GND
GND
15
GND
GND
35
PWR_3-3V
+3.3V
GND
NC
16
CH4_DATA3_P
CH4_DATA3_TX_P
36
17
CH4_DATA3_N
CH4_DATA3_TX_N
37
GND
NC
18
GND
GND
38
PWR_5-0V
+5V
19
12V
NC
39
SDA
SDA
20
12V
NC
40
SCL
SCL
Note: U1 connector pin names may be different than the actual signal depending on which CrossLink LIF-MD6000 Master Link Rev B
board connector this daughter board is connected to.
© 2016-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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Table 7.3. J2 Header Description
Pin
Name
Mapping to U1
1
+3.3V
N/A
2
+1.8V
N/A
3
RESETN
4
CH4_DCK_TX_P
Pin 1
5
SDA
Pin 39
6
CH4_DCK_TX_N
Pin 2
7
SCL
Pin 40
8
GND
N/A
9
GND
N/A
10
CH4_DATA0_TX_P
Pin 4
11
CH4_DATA3_TX_P
Pin 16
12
CH4_DATA0_TX_N
Pin 5
13
CH4_DATA3_TX_N
Pin 17
14
GND
15
GND
N/A
16
CH4_DATA1_TX_P
Pin 7
17
CH4_DATA4_TX_P
Pin 24
18
CH4_DATA1_TX_N
Pin 8
19
CH4_DATA4_TX_N
Pin 25
20
GND
N/A
21
GND
N/A
22
CH4_DATA2_TX_P
Pin 13
23
CH4_DATA5_TX_P
Pin 27
24
CH4_DATA2_TX_N
Pin 14
25
CH4_DATA5_TX_N
Pin 28
26
GND
Pin 22
N/A
N/A
© 2016-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02010-1.6
17
CrossLink LIF-MD6000 Master Link Board - Revision B
Evaluation Board User Guide
Figure 7.1. Top View of Breakout I/O Link Board
Figure 7.2. Bottom View of Breakout I/O Link Board
© 2016-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
18
FPGA-EB-02010-1.6
CrossLink LIF-MD6000 Master Link Board - Revision B
Evaluation Board User Guide
8. Ordering Information
Table 8.1. Ordering Information
Description
CrossLink: LIF-MD6000 Master Link Rev B board
(Includes 1 SMA I/O Link Board and 1 Breakout
I/O Link Board)
CrossLink: LIF-MD6000 I/O Link Boards
(Includes 1 SMA I/O Link Board and 1 Breakout
I/O Link Board)
Ordering Part Number
China RoHS Environment-Friendly
Use Period (EFUP)
LIF-MD6000-ML-EVN
LIFMD-IOL-EVN
© 2016-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02010-1.6
19
CrossLink LIF-MD6000 Master Link Board - Revision B
Evaluation Board User Guide
Appendix A. LIF-MD6000-ML-EVN-BRD Schematics
3
2
LVDS RX In
I2C*2
D
BANK-1,2
I2C
MIPI TX I/O
JTAG_I/F/ SPI
FTDI
LIFMD-6000-6MG81I
Targeted FPGA
SPI
C
SPI
MIPI TX I/O
I2C
JTAG
USP Programming only
SPI FLASH
BANK-0
USB to
JTAG / SPI
LVDS RX HEADER1
SPI
I2C*3
USB
CONNECTOR
MIPI TX HEADER2
C
OnBoard
LDO'S & Buck
SPI
I2C
DPHY BLOCK
Ext Power
Adaptor (12V)
MIPI TX HEADER1
1V2,1V8,2V5,3V3,5V
SPI
D
LVDS RX In
LVDS RX HEADER1
1
I2C*1
4
SPI
5
B
B
LCMXO3LF-1300-MG121
BANK-0
BANK-2
I2C
I/O Expander - I2C Switch
A
A
BANK-3,4
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
T i tl e
BLOCK Diagram
Size
B
Date:
5
4
3
Project
LIFMD-6000-6MG81I Snow bridging solution
16-FEB-16
2
Sheet
Schematic Rev
1.0
Board Rev
1 of 8
B
1
Figure A.1. LIF-MD6000 Master Link Rev B Board Block Diagram
© 2016-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
20
FPGA-EB-02010-1.6
CrossLink LIF-MD6000 Master Link Board - Revision B
Evaluation Board User Guide
5
4
3
2
1
+3.3V
L1
2
1
600ohm 500mA
1
+3.3V
C1
4u7
D
D
0.1uF
2
+3.3V
C2
R3 R1 R2
L2
2
1
600ohm 500mA
1
VBUS_5V
L3
C3
4u7
C4
4.7k 4.7k 4.7k
+3.3V
PROGRAMMING INTERFACE
0.1uF
2
1
C5
VCC1_8FT
0.1uF
J1
+3.3V
1
2
3
4
5
6
7
8
600ohm 500mA
U1
FT2232HL
0
C6
0.1uF
VPHY
VPLL
VCC1_8FT
+3.3V
50
49
7
8
C7
C8
10uF
0.1uF
+3.3V
R10
2k2
R11
12k
14
6
+3.3V
U2
B
C9
0.1uF
VCC
NU
ORG
VSS
CS
CLK
DI
DO
1
2
3
4
5
6
7
8
TDO
TDI
TMS
TCK
header_1x8
SKT_MINIUSB_B_RA
C
8
7
6
5
20
31
42
56
R4
R12
R13
R14
10K
10K
10K
FT_EECS
FT_EECLK
FT_EEDATA
63
62
61
1
2
3
4
2
12k
R17
VCCIO
VCCIO
VCCIO
VCCIO
VCC
DD+
ID
GND
SHIELD2
SHIELD1
VCORE
VCORE
VCORE
SHIELD4
SHIELD3
4
9
7
6
1
2
3
4
5
12
37
64
9
8
2
J2
ADBUS0
ADBUS1
ADBUS2
ADBUS3
ADBUS4
ADBUS5
ADBUS6
ADBUS7
VREGIN
VREGOUT
DM
DP
ACBUS0
ACBUS1
ACBUS2
ACBUS3
ACBUS4
ACBUS5
ACBUS6
ACBUS7
RESET#
REF
EECS
EECLK
EEDATA
BDBUS0
BDBUS1
BDBUS2
BDBUS3
BDBUS4
BDBUS5
BDBUS6
BDBUS7
OSCI
X1
93LC56-SO8
1
2
C10
18pF
1
3
G1 G2
3
3
OSCO
4
C11
18pF
12MHZ
13
TEST
FTDI High-Speed USB
FT2232H
R18
C14
C15
C16
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
10
DNI
C13
R5
R6
R7
0
0
0
MCLK 4,5,6
SISPI 4,5,6
SPISO 4,5,6
R167
DNI
CSSPIN
R23
R26
CDONE 6
CRESETB 6
26
27
28
29
30
32
33
34
4,5,6
R9
2k2
38
39
40
41
43
44
45
46
0
0
0
0
R15
R16
R180
R181
TCK 7
TDI 7
TDO 7
TMS 7
B
48
52
53
54
55
57
58
59
60
36
GND
GND
GND
GND
GND
GND
GND
GND
0
AGND
7 12MHZ
C12
PWREN#
SUSPEND#
0
0
0
1
5
11
15
25
35
47
51
+3.3V
BCBUS0
BCBUS1
BCBUS2
BCBUS3
BCBUS4
BCBUS5
BCBUS6
BCBUS7
C
16
17
18
19
21
22
23
24
A
A
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
T i tl e
F T DI I NT E RF A CE
Size
B
Date:
5
4
3
2
Project
LIFMD-6000-6MG81I Snow bridging solution
16-FEB-16
Sheet
Schematic Rev
1.0
Board Rev
2 of 8
B
1
Figure A.2. FTDI Interface
© 2016-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02010-1.6
21
CrossLink LIF-MD6000 Master Link Board - Revision B
Evaluation Board User Guide
4
3
2
12V
J24
NOTE : INPUT VOLTAGE SHOULD BE 12V AT 3A Max
12V_EXT
1
2
1V2
1
VCCIO1/2
3V3
5V
R22 R144
100E 100E
FUSE
C123
1
SL44-E3/57T
VBUS_5V
D14
1
0.1uF
DNI
PJ-032A
DNI
2
2
2
R448
3
R21
+1.2V
R435
1
VCC_1.2V
+1.2V
1
1V2
R417
1
VCC_DPHY1
1
3V3
0
10u
0.1u
C96
C97
L4
2
1
600ohm 500mA
2
1
R33
2
R449
DNI
+2.5V
1
VCCIO2
1
3
R28
VCCIO0
+3.3V
VCCIO0
VCCIO1
VCCIO1
VCCIO2
VCCIO2
Tri-Con
2
2 Position Terminal Block_0
GND
C95
3
C94
1
VCC_DPHY
R24
1
VCCIO1/2
1
U15
R165
R20
VCC_CORE1 +2.5V
VCC_CORE
2V5
1
4
500mA traces
2
1
SL44-E3/57T
J9
OUT
R19
Snow Voltage
Selection
2 Position Terminal Block_0
5V_INT
IN
VCC_DPHY
+3.3V
J25
500mA traces
1
0.1u
VCCIO1
1
Tri-Con
NOTE : Place this gnd test point near J3
10u
VCCIO0+1.2V
D
2
GND3
5V
VCC_CORE +3.3V
+2.5V
1
1
C130
10uF
2
4
D1
2
2
R25
1
D
1
1
1
5V_INT
U3
1
1
3
+1.2V
1
2V5
1
1
J3
+1.2V
R434
J8
1
1
5
+1.2V
AP7313-12SAG-7
1K_VCC_CORE
+3.3V
1K_VCCIO0
+3.3V
1K_VCCIO1
+3.3V
1K_VCCIO2
+3.3V
1K_VCCIO3
C
C
R190
VCC_3.3V
5V
1
R410
1
R184
1
R186
1
R188
1
+3.3V
500mA traces
1K_VCC_CORE1
1K
C21
GND
C22
22uF
D25
Green
0.1uF
1
+2.5V
R185
DNI
1
+2.5V
R187
DNI
1
R189
DNI
1
DNI
2
NCP1117ST33T3G
2
1
+2.5V
R411
1K_VCCIO0
XO3-1K Voltage
Selection
VCC_2.5V
5V
+2.5V
12V_EXT
1K_VCCIO0
1K_VCCIO1
1K_VCCIO1
1K_VCCIO2
1K_VCCIO2
1K_VCCIO3
1K_VCCIO3
1
10uF
+2.5V
1K_VCC_CORE
R233
1
C20
2
1
600ohm 500mA
2
4
1
1K
D3
Green
OUT
TAB
L5
1
1
IN
0
1
3
R36
R37
1
U5
12V
500mA traces
L6
2
1
600ohm 500mA
C29
12V
NCP1117ST25T3G
12V
1V2
+1.2V
2V5
+2.5V
U18
3V3
+3.3V
5V0
5V
GND2 GND1 GND4 GND5
1
0.1uF
12V0
1
22uF
B
GLOBAL POWER TEST POINTS
0.1u
1
1
C25
1
GND
10uF
C24
1
2
4
1
OUT
TAB
1
IN
C23
SW1
PWR
0
1
3
B
R39
1
U6
5V_INT
LT3680
4
C115
10uF
5
1
9
U17
3
C114
A
10uF
IN
R192
OUT
TAB
GND
1
NCP1117ST18T3G
VC
0
2
4
FB
L7
2
1
600ohm 500mA
C113
C112
22uF
0.1uF
10
R229
15K
ON BOARD POWER REGULATORS
C127
680pF
RT
BOOST
8
R232
100K
2
C128
7
R230
34K
C129
47uF
R231
536K
RUN_SS
500mA traces
PG
0.47uF
SW
6
SYNC
EPAD
A
L8
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
3
11
LT3680
Manufacturer = Linear
PART_NUMBER = LT3680EDD#PBF
4.7uH
1
+1.8V
BD
D12
MBRA340T3G
0.3VF
T i tl e
POWER REGULATOR I/F
Size
B
2
VCC_1.8V
5V
VIN
Date:
5
4
3
2
Project
LIFMD-6000-6MG81I Snow bridging solution
16-FEB-16
Sheet
Schematic Rev
1.0
Board Rev
3 of 8
B
1
Figure A.3. Power Regulator Interface
© 2016-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
22
FPGA-EB-02010-1.6
CrossLink LIF-MD6000 Master Link Board - Revision B
Evaluation Board User Guide
5
4
3
2
1
U7
5V +3.3V +1.8V
12V
2,5,6
2,5,6
U8D
C4
C6
0
R51
VCC_DPHY
C41
C42
C171
1uF
4V
0.01uF 470pF
16V 16V
B5
D3
A5
0
R52
VCC_DPHY
C43
C44
C172
1uF
4V
0.01uF 470pF
16V 16V
D7
0
R53
C45
C46
1uF
16V
470pF 0.1uF
16V 16V
GNDPLL_DPHYX
VCCA_DPHY1
VCCA_DPHY1
DPHY1_CKP
DPHY1_CKN
DPHY1_DP0
DPHY1_DN0
DPHY1_DP1
DPHY1_DN1
DPHY1_DP2
DPHY1_DN2
DPHY1_DP3
DPHY1_DN3
A1
A2
B1
B2
A3
B3
C1
C2
A4
B4
CH5_DCK_TX_P
CH5_DCK_TX_N
CH5_DATA0_TX_P
CH5_DATA0_TX_N
CH5_DATA1_TX_P
CH5_DATA1_TX_N
CH5_DATA2_TX_P
CH5_DATA2_TX_N
CH5_DATA3_TX_P
CH5_DATA3_TX_N
4
5
6
CH4_DATA1_TX_P
CH4_DATA1_TX_N
7
8
9
10
11
CSSPIN
MCLK
CSSPIN
MCLK
CH4_DATA2_TX_P
CH4_DATA2_TX_N
12
13
14
CH4_DATA3_TX_P
CH4_DATA3_TX_N
15
16
17
12V
18
19
20
43
44
41
C3
C
VCCPLL_DPHY1
VCCPLL_DPHY0
CH4_DATA0_TX_P
CH4_DATA0_TX_N
GNDA_DPHY1
VCCA_DPHY0
C178
C7
GNDA_DPHY0
DPHY0_CKP
DPHY0_CKN
DPHY0_DP0
DPHY0_DN0
DPHY0_DP1
DPHY0_DN1
DPHY0_DP2
DPHY0_DN2
DPHY0_DP3
DPHY0_DN3
A8
A9
B7
A7
B8
B9
B6
A6
C8
C9
CH4_DCK_TX_P
CH4_DCK_TX_N
CH4_DATA0_TX_P
CH4_DATA0_TX_N
CH4_DATA1_TX_P
CH4_DATA1_TX_N
CH4_DATA2_TX_P
CH4_DATA2_TX_N
CH4_DATA3_TX_P
CH4_DATA3_TX_N
B
TBD
RESETN
PWR_5-0V
CH4_DATA0_P
CH4_DATA0_N
GND
GND
GND
PWR_3-3V
CH4_DATA1_P
CH4_DATA1_N
GND
GND
GND
PWR_1-8V
SN
SCLK
GND
CH4_DATA2_P
CH4_DATA2_N
GND
CH4_DATA3_P
CH4_DATA3_N
GND
12V
12V
21
22
23
24
25
26
+1.8V
C155
C156
C157
C158
0.1uF
0.1uF
0.1uF
0.1uF
D
30
31
MOSI
MISO
GPIO1
GPIO2
32
33
34
PWR_1-8V
GND
GND
0 DNI
0
DNI
R418
R419
0
0
R420
R421
SISPI 2,5,6
SPISO 2,5,6
RPI1
RPI2
35
36
37
PWR_3-3V
GND
GND
38
39
40
0
0
R453
R454
SDA
SCL
5
5
SDA 6,7
SCL 6,7
45
46
Shield5
Shield6
Shield1
+3.3V
27
28
29
PWR_5-0V
SDA
SCL
Shield3
Shield4
5V
R465 RESETN
0
42
Shield2
C
Hirose - FX12 - 40 Pos
U9
CH5_DCK_TX_P
CH5_DCK_TX_N
1
2
3
CH5_DATA0_TX_P
CH5_DATA0_TX_N
4
5
6
CH5_DATA1_TX_P
CH5_DATA1_TX_N
7
8
9
CSSPIN
MCLK
10
11
CH5_DATA2_TX_P
CH5_DATA2_TX_N
12
13
14
CH5_DATA3_TX_P
CH5_DATA3_TX_N
15
16
17
LIFMD6000-csfBGA81
Note :
1) Match length within pair as well as other pairs with +/- 5% tolerence
2)Differential impedance should be 100 Ohms and 50 Ohms as a single ended signals
3)All the power rails should be capable of carrying 1A current
4)Place MIPI TX resistor network as close to bank 0 as possible.
Trace match *HS* P & N channels as well as individual pairs.
Minimize routing and trace match *LP* signals to banks 5 and 0.
CH4_DCK_P
CH4_DCK_N
GND
TX Connector1
VCC_DPHY
1
2
3
12V
18
19
20
43
44
41
5V +3.3V +1.8V
CH5_DCK_P
CH5_DCK_N
GND
TBD
RESETN
PWR_5-0V
CH5_DATA0_P
CH5_DATA0_N
GND
GND
GND
PWR_3-3V
CH5_DATA1_P
CH5_DATA1_N
GND
GND
GND
PWR_1-8V
SN
SCLK
GND
CH5_DATA2_P
CH5_DATA2_N
GND
CH5_DATA3_P
CH5_DATA3_N
GND
12V
12V
Shield3
Shield4
Shield1
TX Connector2
D
CH4_DCK_TX_P
CH4_DCK_TX_N
MOSI
MISO
PWR_1-8V
GND
GND
PWR_3-3V
GND
GND
PWR_5-0V
SDA
SCL
Shield5
Shield6
Shield2
21
22
23
0
R466
RESETN
RESETN
5
24
25
26
27
28
29
12V
30
31
GPIO1
GPIO2
5V
+3.3V
C159
C161
C160
C162
0.1uF
0.1uF
0.1uF
0.1uF
+1.8V
32
33
34
B
35
36
37
38
39
40
45
46
0
0
R455
R456
0 DNI
0
DNI
R481
R482
SDA
SCL
XO3_SCL 7
XO3_SDA 7
42
Hirose - FX12 - 40 Pos
Note : Speed of the bus, < 2.5ps skew for pairs and
across the bus, traces should be 100 Ohms
A
A
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Piggyback Configuration info:
T i tl e
MiPi Block - MIPI TX
1.. 0.001uF and 0.1uF is added as the piggyback c
100nF and 470pF is loaded near DUT and 0.001uF and 0.1uF is made piggy back for the following reference designer
Size
B
C42,C44,C46,C171,C172
Date:
5
4
3
Project
LIFMD-6000-6MG81I Snow bridging solution
16-FEB-16
2
Sheet
Schematic Rev
1.0
Board Rev
4 of 8
B
1
Figure A.4. MIPI Block – MIPI Tx
© 2016-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02010-1.6
23
CrossLink LIF-MD6000 Master Link Board - Revision B
Evaluation Board User Guide
4
3
2
J29
CON3
U8C
D
CH0_DATA0_P
CH0_DATA0_N
EXT_RST
CMOS_IO_3
CH0_DATA2_P
CH0_DATA2_N
CH0_DATA1_P
CH0_DATA1_N
CMOS_IO_2
CMOS_IO_1
CH0_DATA3_P
CH0_DATA3_N
CH0_DCK_P
CH0_DCK_N
0
CMOS_IO_4
VCCIO2
R54
DNI
R5D
7 NI
CMOS_IO_3
DNI
R450
DNI
R59
C52
C53
100nF
16V
6800pF
10V
1uF
4V
1
PB29A/PCLKT1_0
PB29B/PCLKC1_0
PB29C/PCLKT1_1
PB29D/PCLKC1_1
PB34A/GR_PCLK1_0
PB34B
PB34C/MIPI_CLKT1_0
PB34D/MIPI_CLKC1_0
PB38A
PB38B
PB38C
PB38D
PB43C
PB43D
VCCIO1
VCCIO1
10
11
0
0
7 SDA3
7 SCL3
CMOS_IO_7
CMOS_IO_8
1. 0.001uF and 1.5nF is added as the piggyback cap
100nF and 1.5nF is loaded near DUT and 0.001uF and 1.5nF is
made piggy back for the following reference designer
C51,C59
12V
R457
R458
0
0
CMOS_IO_1 0
CMOS_IO_2 0
R467
R468
R60
R61
12
13
14
18
19
20
41
4.7k
C58
C59
C60
C177
100nF
16V
1.5nF
10V
1uF
4V
470pF
16V
Note : Speed of the bus, < 2.5ps skew for pairs and
across the bus, traces should be 100 Ohms
Trace match LVDSI* pins between P and N channels as
well as individual pairs. Minimize routing and trace
match *CD* signals to bank 3 pins.
EXTERNAL RESET
7 SDA4
7 SCL4
A
12V
R461
R462
0
0
U12
1
2
3
CSSPIN
MCLK
CSSPIN
MCLK
4
5
6
7
8
9
10
11
12
13
14
CMOS_IO_1
CMOS_IO_2
0
0
R471
R472
15
16
17
CMOS_IO_3
CMOS_IO_4
0
0
R473
R474
18
19
20
12V
5V
+3.3V
+1.8V
C167
C169
C168
C170
0.1uF
0.1uF
0.1uF
0.1uF
Shield3
Shield4
Shield5
Shield6
Shield1
Shield2
43
44
41
CH0_DCK_P
CH0_DCK_N
GND
CH1_DATA3_P
CH1_DATA3_N
D
30
31
GPIO3
GPIO4
32
33
34
35
36
37
38
39
40
0
0
42
R459
R460
12V
45
46
5V
SDA1 7
SCL1 7
+3.3V
+1.8V
C163
C165
C164
C166
0.1uF
0.1uF
0.1uF
0.1uF
C
GPIO3
GPIO4
CH0_DATA0_P
CH0_DATA0_N
GND
CH0_DATA1_P
CH0_DATA1_N
PWR_3-3V
CH0_DATA2_P
CH0_DATA2_N
GND
CH0_DATA3_P
CH0_DATA3_N
PWR_1-8V
SN
SCLK
PWR_12V
SDA1
SCL1
GND
CH2_DATA0_P
CH2_DATA0_N
GND
CH2_DCK_P
CH2_DCK_N
MOSI
MISO
Shield5
Shield6
Shield2
DNI
CH0_DATA1_P
CH0_DATA1_N
27
28
29
CH0_DATA3_P
CH0_DATA3_N
30
31
GPIO3
GPIO4
CH1_DATA0_P
DNI
R463
R464
B
1
2
3
4
5
6
CMOS_IO_5
CMOS_IO_6
CMOS_IO_7
CMOS_IO_8
CH0_DCK_N
CON6
CH0_DATA1_P
CH0_DATA1_N
DNI
R110
100
CH0_DATA3_P
R119
100
CH1_DATA2_N
CH0_DATA3_N
A
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
DNI
CH1_DCK_P
45
46
CH0_DATA0_P
R113
100
R121
100
CH1_DCK_N
DNI
T i tl e
BANK1,2 - LVDS RX
CH0_DATA0_N
Size
B
DNI
Date:
4
J28
VCCIO1
R117
100
CH1_DATA2_P
SDA2 7
SCL2 7
42
4
4
DNI
CH1_DATA3_P
CH1_DATA3_N
0
0
RPI1
RPI2
CH0_DCK_P
CH1_DATA0_N
CMOS_IO_5
CMOS_IO_6
R424
R425
R114
100
R108
100
R469
R470
0
0
SISPI 2,4,6
SPISO 2,4,6
DNI
DNI
0
0
R422
R423
CH0_DATA2_N
R107
100
DNI
38
39
40
PWR_5-0V
SDA
SCL
R111
100
CH1_DATA1_N
RESETN
24
25
26
35
36
37
PWR_3-3V
CH2_DATA1_P
CH2_DATA1_N
Shield1
R475
32
33
34
PWR_1-8V
GND
GND
Shield3
Shield4
0
0 DNI
0
DNI
CH0_DATA2_P
R106
100
21
22
23
PWR_12-0V
RESETN
PWR_5-0V
Hirose - FX12 - 40 Pos
5
27
28
29
4
Note :
1) Match length within pair as well as other pairs with +/- 5% tolerence
2)Differential impedance should be 100 Ohms and 50 Ohms as a single ended signals
3)All the power rails should be capable of carrying 1A current
+3.3V +1.8V
CH1_DATA1_P
RX Connector1
2,4,6
2,4,6
PWR_5-0V
SDA
SCL
CH1_DATA1_P
CH1_DATA1_N
0.1uF
VCCIO1
NOTE : PLACE ALL THE TERMINATION
RESISTORS ON TOP SIDE AND CLOSE
TO THE U8
CH0_DATA2_P
CH0_DATA2_N
PWR_3-3V
CH3_DATA1_P
CH3_DATA1_N
R476 RESETN
RESETN
0
24
25
26
EXT_RST
R446
LVDS RX TERMINATION RESISTORS
CH0_DATA0_P
CH0_DATA0_N
PWR_1-8V
GND
GND
21
22
23
Hirose - FX12 - 40 Pos
0
12V 5V
CH0_DCK_P
CH0_DCK_N
MOSI
MISO
+3.3V +1.8V
C181
F3
G4
LIFMD6000-csfBGA81
B
CH1_DATA3_P
CH1_DATA3_N
PWR_1-8V
GND
CH3_DCK_P
CH3_DCK_N
R445
SW4
EXT_RST
CH1_DATA2_P
CH1_DATA2_N
GND
GND
CH3_DATA0_P
CH3_DATA0_N
43
44
NOTE : PLACE SWITCH IN THE TOP SIDE
CH1_DATA1_P
CH1_DATA1_N
PWR_3-3V
PWR_12_0V
SDA1
SCL1
15
16
17
PWR_12V
RESETN
PWR_5-0V
CH1_DATA0_P
CH1_DATA0_N
GND
SN
SCLK
2
DNI
Piggyback Configuration
info:
CH1_DCK_P
CH1_DCK_N
CMOS_IO_7
CMOS_IO_8
CH1_DATA1_P
CH1_DATA1_N
CMOS_IO_5
CMOS_IO_6
CH1_DATA0_P
CH1_DATA0_N
CH1_DATA3_P
CH1_DATA3_N
CH1_DATA2_P
CH1_DATA2_N
7
8
9
CSSPIN
MCLK
blue
VCCIO2
G7
G6
J6
H6
D1
D2
J5
H5
E1
E2
J4
H4
J3
H3
CH1_DATA2_P
CH1_DATA2_N
2
D9
680R
CMOS_IO_4
C51
blue
1
4.7k
RESETN
4
5
6
CH1_DCK_P
CH1_DCK_N
GND
2
D8
680R
CH1_DATA0_P
CH1_DATA0_N
blue
1
R56
1
2
3
2
D7
680R
CH1_DCK_P
CH1_DCK_N
blue
1
R55
U8B
C
D6
680R
CMOS_IO_2
VCCIO2
LIFMD6000-csfBGA81
VCCIO0
CMOS_IO_1
E6
F6
VCCIO2
VCCIO2
U11
Default short (J29.2,J29.3)
1
2
3
F9
F8
G9
G8
E9
E8
H9
H8
F7
E7
J9
J8
D9
D8
J7
H7
PB2A
PB2B
PB2C/MIPI_CLKT2_0
PB2D/MIPI_CLKC2_0
PB6A/GR_PCLK2_0
PB6B
PB6C
PB6D
PB12A/GPLLT2_0
PB12B/GPLLC2_0
PB12C
PB12D
PB16A/PCLKT2_0
PB16B/PCLKC2_0
PB16C/PCLKT2_1
PB16D/PCLKC2_1
1
12V 5V
RX Connector2
5
3
Project
LIFMD-6000-6MG81I Snow bridging solution
16-FEB-16
2
Sheet
Schematic Rev
1.0
Board Rev
5 of 8
B
1
Figure A.5. Bank 1, 2 – LVDS Rx
© 2016-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
24
FPGA-EB-02010-1.6
CrossLink LIF-MD6000 Master Link Board - Revision B
Evaluation Board User Guide
5
4
3
2
1
VCCIO0
SW5
WAKE_UP
VCCIO0
NOTE : PLACE SPI FLASH IN THE TOP SIDE
IT SUPPORTS 2.5/3.3 V
R76 R77
CDONE
2
4,7
4
SDA
SDA
In3
Out
SISPI 2,4,5,6
SPISO 2,4,5,6
CSSPIN 2,4,5,6
In2
G3
CON2
2200pF
25V
2
1
LIFMD6000-csfBGA81
C176
470pF
16V
C67
100nF
16V
CLK_SDA
3
CLK_EXT
1K U14
R412
2,4,5,6
SISPI
2,4,5,6
MCLK
4,7
SCL
In3
Out
1uF
4V
SDI
R413
6
0
In2
1
CLK_INT_REF
2
CLK_SCL
2,4,5,6
CON2
3
CLK_EXT_REF
SDO
2
WP
1
CSSPIN
D
10K 10K 10K
R414
0
SPISO
2,4,5,6
SCK
3
In1
4
SCL
CS
SPI FLASH
HOLD
7
M25PX16-VMW6TG
Tri-Con
VCCIO0
J19 TP18
VCCIO0
J20
NOTE : PLACE SWITCH IN THE TOP SIDE
R80
VCCIO2
1
OSCILLATOR
R160
R131
X3
PLACE CLOSE TO U8
680R
C
5
0
100nF
10V
R123R124R125
SPI FLASH
J27
VCCIO0
C66
2
Tri-Con
MCLK
MCLK 2,4,5,6
CRESETB
NOTE : PLACE R83 Close to the snow deviceCRESETB 2
C173
CLK_INT
8
R416
R166
1
VCC
0
C49
J26
In1
CLK_SDA
CDONE
CLK_SCL
SISPI
SPISO
CSSPIN
30E
R83
R415
4
VCCIO0
0
2
1
PB47/PCLKT0_0/USER_SDA
CDONE/PB49/PMU_WKUPN
PB48/PCLKT0_1/USER_SCL
PB50/MOSI
PB51/MISO
PB52/SPI_SS/CSN/SCL
PB53/SPI_SCK/MCK/SDA
CRESET_B
D
J2
H2
F2
F1
J1
G1
H1
G2
GND
2K 2K
U8A
4
J4
C98
CDONE
1
2
3
4
5
4.7k
SW2
SYS_RST
J7
SYS_RST
CRESETB
Green
D10
1
2
1
0
R183
2
STDBY#
1
NOTE : PLACE X3 NEAR U8
NOTE : R159 SHUOULD BE PLACED
NEAR X3
CLK_INT
R159
100nF
10V
50 Ohm Clock Route
73391-0060
GND
OUT
3 0
C
KC3225A27.0000C30E0A
VCC_CORE
C68
J22
2
U8E
CON2
0.1uF
2
3
4
5
SYSTEM RESET
1
0
R433
CLK_EXT_REF
VCCIO2
50 Ohm Clock Route
73391-0060
X4
C179
PLACE CLOSE TO U8
CRESETB
5V
R78
D6
F4
E5
C5
D4
OSCILLATOR
R432
4
12V_EXT
100K
VDD
CLK_EXT
5V
2
100nF
10V
NOTE : PLACE X4 NEAR U8
NOTE : R431 SHUOULD BE PLACED
NEAR X4
R431
CLK_INT_REF
100K
VDD
STDBY#
GND
OUT
1
3 0
F5
GND
GND
GND
GND
GND
VCC
VCC
VCCAUX25VPP
VCCGPLL
E3
E4
D5
0
0
GNDGPLL
LIFMD6000-csfBGA81
R447 +2.5V
G5
C70
C71
100nF
16V
1uF
4V
R90
KC3225A27.0000C30E0A
5V
VCC_CORE
R441
B
R442
R443
B
PLACE DECOUPLING CAPACITORS CLOSE TO THE U8 POWER PINS
R444
10K
VCCIO0
R399
10K
+2.5V
3
2
+1.8V
1
Q11
MMBT2222A
MCLK
SISPI
SPISO
CSSPIN
R400
2
4
6
8
10
SDA
SCL
C72
C73
C74
C75
C76
C77
C78
C175
C174
4700pF
330pF
330pF
1.5nF
330pF
5600pF
1.5nF
1.5nF
1000pF
25V
10K
HEADER 5X2
MH1
MH2
ThruHole
Piggyback Configuration info:
A
1
3
5
7
9
1
2
Q10
MMBT2222A
2
10K
2
R395
J18
D29
Green
3
2
+1.2V
1
Q9
MMBT2222A
1K
D28
Green
3
2
2
1K
D27
Green
1
1K
D26
Green
1
1
1
1K
1. 0.1uF and 1.5nF is added as the piggyback cap
470pF and 1.5nF is loaded near DUT and 0.1uF and 1.5nF is made piggy back for the following reference designer
C66,C75,C78
2. 0.001uF is added as the piggyback cap
100nF is loaded near DUT and 0.001uF is made piggy back for the following reference designer
C176
3. 1.5nF is added as the piggyback cap
1.5nF is loaded near DUT and 1.5nF is made piggy back for the following reference designer
C175
MH3
ThruHole
MH4
ThruHole
MH5
ThruHole
ThruHole
ThruHole
MH10
ThruHole
A
MH6
MH7
ThruHole
MH8
ThruHole
MH9
ThruHole
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
T i tl e
BANK0, Flash I/F
Size
B
Date:
5
4
3
Project
LIFMD-6000-6MG81I Snow bridging solution
16-FEB-16
2
Sheet
Schematic Rev
1.0
Board Rev
6 of 8
B
1
Figure A.6. Bank0, Flash Interface
© 2016-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02010-1.6
25
CrossLink LIF-MD6000 Master Link Board - Revision B
Evaluation Board User Guide
5
4
3
2
1
1K_VCCIO2
U19C
D6
D
C145
C143
C144
C146
10uF
0.1uF
0.1uF
0.01uF
VCCIO0
PT9A
BANK0 PT17A
PT16A
PT15A
PT12C/SCL/PCLKTO_0
PT12B/PCLKC0_1
PT11A
PT10D/TDI
PT10A
PT17B
PT16B
PT15B
PT12D/SDA/PCLKC0_0
PT12A/PCLKTO_1
PT11B
PT10B
PT9B
PT17C/INITN
PT15D/PROGRAMN
PT15C/JTAGENB
PT11D/TMS
PT11C/TCK
PT9C
PT17D/DONE
PT10C/TDO
A10
A2
A3
A4
A5
A6
A7
A8
A9
B2
B3
B4
B5
B6
B7
B8
B9
C3
C4
C5
C6
C7
C8
D4
D7
0
R452
SCL
12MHZ
TDI
C150
C147
C148
10uF
0.1uF
0.1uF
VCCIO2
C149
0.01uF
4,6
2
2
1K_VCCIO1
XO3_RESET
0
R451
SDA
R403 R404 R405
4,6
4.7k
4.7k
INITN
PROGRAMN
JTAGENB
4.7k
1
1
1
TP23
TP24
TP25
TMS 2
TCK 2
DONE
TDO
PB6D/SO/SPISO
PB4A
PB18D
BANK2
PB18C
PB15C
PB11D
PB6C/MCLK/CCLK
PB4B
PB4C/CSSPIN
PB20D/SI/SISPI
PB20B
PB18B
PB15B
PB11B/PCLKC2_1
PB9B/PCLKC2_0
PB9C
PB6A
PB4D
PB20C/SN
PB20A
PB18A
PB15A
PB11A/PCLKT2_1
PB9A/PCLKT2_0
PB9D
PB6B
1K_VCCIO2
H7
H9
J4
J5
J6
J7
J8
J9
K10
K2
K3
K4
K5
K6
K7
K8
K9
L10
L2
L3
L4
L5
L6
L7
L8
L9
1K_VCCIO0
R179
650
R176R175R178R177 R477R478R480R479
D
DONE
4.7k 4.7k 4.7k 4.7k
4.7k 4.7k 4.7k 4.7k
1
H6
U19A
SDA1 5
SCL1 5
SCL2 5
SDA2 5
Red
D23
2
1K_VCCIO0
SDA3 5
SCL3 5
SCL4 5
SDA4 5
2
LCMXO3LF-1200E-MG121
C
C
LCMXO3LF-1200E-MG121
I/O Expander - I2C Muxing
1K_VCCIO3
1K_VCCIO1
U19D
D8
F8
H8
U19B
H5
C153
C151
C152
C154
10uF
0.1uF
0.1uF
0.01uF
B
NOTE : PLACE SWITCH IN THE TOP SIDE
VCCIO0
VCCIO1
PR2C
PR2D
PR2A
PR3B
BANK1
PR3A
PR2B
PR4D
PR4C
PR4B
PR4A
PR5D/PCLKC1_0
PR5C/PCLKT1_0
PR5A
PR5B
PR8A
PR8B
PR8C
PR8D
PR9A
PR9B
PR9C
PR9D
PR10A
PR10C
PR10D
PR10B
B1
C1
C2
D1
D2
D3
E1
E2
E3
E4
F1
F2
F3
F4
G1
G2
G3
G4
H1
H2
H3
H4
J1
J2
J3
K1
C141
C142
C139
10uF
0.1uF
0.1uF
C140
VCCIO3
VCCIO3
VCCIO3
PL2C/L_GPLLT_IN
PL2D/L_GPLLC_IN
PL3A/PCLKT3_2
PL3B/PCLKC3_2
PL2A/L_GPLLT_FB
PL4A
PL4B
PL3C
BANK3
PL4C
PL4D
PL2B/L_GPLLC_FB
PL3D
PL5B/PCLKC3_1
PL5A/PCLKT3_1
PL5C
PL8B
PL8A
PL8D
PL8C
PL9B/PCLKC3_0
PL9A/PCLKT3_0
PL10D
PL10A
PL10C
0.01uF
1K_VCC_CORE
U19E
D5
E5
F7
G7
VCC
VCC
VCC
VCC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
A1
A11
E6
E7
F5
F6
G5
G6
L1
L11
B10
B11
C10
C11
C9
D10
D11
D9
E10
E11
E8
E9
F10
F11
F9
G10
G11
G8
G9
H10
H11
J10
J11
K11
DEBUG1
DEBUG2
DEBUG3
DEBUG4
LED1
LED2
LED3
LED4
R436
1K_VCCIO3
D30
680R
blue
1
LED1
R437
680R
R438
680R
2
D31
blue
1
LED2
2
D32
blue
1
LED3
B
2
R483R484
R439
D33
680R
1
LED4
blue
2
4.7k 4.7k
XO3_SCL 4
XO3_SDA 4
LCMXO3LF-1200E-MG121
R440
LCMXO3LF-1200E-MG121
SW3
SYS_RST
LCMXO3LF-1200E-MG121
4.7k
J23
1K_VCC_CORE
XO3_RESET
A
PLACE DECOUPLING CAPACITORS CLOSE TO THE U5 POWER PINS
0.1uF
C107
C106
C104
C105
C102
C103
10uF
1uF
0.1uF
0.1uF
0.1uF
0.01uF
A
DEBUG1
DEBUG2
DEBUG3
DEBUG4
C180
1
2
3
4
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
T i tl e
I2C Expander
4 HEADER
EXTERNAL RESET
Size
B
Date:
5
4
3
Project
LIFMD-6000-6MG81I Snow bridging solution
16-FEB-16
2
Sheet
Schematic Rev
1.0
Board Rev
7 of 8
B
1
2
Figure A.7. I C Expander
© 2016-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
26
FPGA-EB-02010-1.6
CrossLink LIF-MD6000 Master Link Board - Revision B
Evaluation Board User Guide
5
4
3
2
1
Routing guidlines for MIPI & LVDS
---------------------------------D
D
1)All differential routes are required to have the same length between the positive (true) and the negative (complimentary) routes.
Spacing between the positive (true) and the negative (complimentary) shall be 2 times trace width.
2)Target differential impedance shall be 100 Ohms
3)Trace length matching to be within 1.0 mm (40 mil) across the entire bus.
4)Use small humps for skew corrections
5)Place signal vias close together and remove copper in between vias.
Traces to be fully shielded with GND stitching terminating at both trace end points
6)Board trace impedance results must be within ±10 percent of target and
Power plane impedance to be within +/- 10 percent of target at operating frequency
C
C
MIPI &LVDS Simulation Requirement
---------------------------------1)MIPI Differential Mode insertion Loss shall be > -1.6dB at 750 MHz
2)MIPI Differential Mode Return Loss shall be < -15dB at 750 MHz
3)MIPI Common Mode Return Loss shall be < -15dB at 750 MHz
4)LVDS differential mode return loss shall be < -16.5db at 600 MHz
5)LVDS common mode return loss shall be < -16.5db at 600 MHz
B
B
6)LVDS insertion loss shall be > -1.7db at 600 MHz
7)LVDS Cross coupling shall be < -22 dB for victim IO at 600MHz
8)Power plane impedance to be within +/- 10 percent of target at operating frequency
A
A
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
T i tl e
Layout Guidelines
Size
B
Date:
5
4
3
Project
LIFMD-6000-6MG81I Snow bridging solution
16-FEB-16
2
Sheet
Schematic Rev
1.0
Board Rev
8 of 8
B
1
Figure A.8. Layout Guidelines
© 2016-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02010-1.6
27
CrossLink LIF-MD6000 Master Link Board - Revision B
Evaluation Board User Guide
Appendix B. LIF-MD6000-ML-EVN-BRD Bill of Materials
LIF-MD6000 Master Link Rev B Board Bill of Materials
Item
Reference
Quantity
Part
PCB
Footprint
Comments
PART_NUMBER
Manufacturer
Description
Cap Cer
1
C1, C3
2
4u7
C0603
—
ECJ-1VB0J475K
Panasonic
4.7 µF
6.3 V 10% X5R 0603
C2, C4, C5, C6, C8, C9,
C12, C13, C14, C15, C16,
C22, C25, C68, C112,
C180, C181
17
3
C7, C20, C23, C107, C114,
C141, C145, C150, C153
9
10 µF
C0603
4
C10, C11
2
18 pF
5
C21, C24, C113
3
22 µF
2
0.1 µF
CAP CERAMIC
C0402C104K4RA
CTU
Kemet
—
LMK107BJ106M
ALTD
Taiyo Yuden
C0402
—
C0402C180K3GA
Kemet
CTU
CAP CER 18 pF 25 V C0G
0402
C0805
—
LMK212BJ226M
G-T
CAP CERAMIC
Samsung
10 V X5R 20% SMD 0402
85C Paper T/R
C0402
—
0.1 µF
16 V X7R 0402
Taiyo Yuden
CAP CECAP CER 10 µF
10 V X5R 20% 0603
22 µF 10 V X5R 0805
Cap Ceramic 0.1 µF
6
C29, C95, C97
3
0.1 µF
C0402
—
CL05A104MP5N
NNC
7
C41, C43, C53, C60, C67,
C71
6
1 µF
C0306
—
LLR185C70G105
ME05L
Murata
CAP CER 1µF 4 V X7S 0306
8
C42, C44
2
0.01 µF
C0201
—
GRM033R61C10
3KA12D
Murata
CAP CER 10000 pF 16 V X5R
0201
9
C42, C44, C51, C176
4
0.001 µF
C0201
Piggyback
Configuration
GRM033R71C10
2KA01D
Murata
CAP CER 1000 pF 16 V X7R
0201
10
C45
1
1 µF
C0402
—
GRM155R61C10
5KA12D
Murata
11
C46, C66, C171, C172,
C177
5
470 pF
C0201
—
GRM033R71C47
1KA01D
Murata
12
C46, C66, C171, C172
4
0.1 µF
C0201
Piggyback
Configuration
GRM033R61C10
4KE84D
Murata
CAP CER
1 µF 16 V X5R 0402
CAP CER
470 pF 16 V X7R 0201
CAP CER 0.1 µF
16 V X5R 0201
© 2016-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
28
FPGA-EB-02010-1.6
CrossLink LIF-MD6000 Master Link Board - Revision B
Evaluation Board User Guide
Item
Reference
Quantity
Part
PCB
Footprint
Comments
PART_NUMBER
Manufacturer
Description
CAP CER 100 nF
13
C49, C98, C179
3
100 nF
C0402
—
GRM155R61A10
4KA01D
Murata
14
C51, C58, C70, C176
4
100 nF
C0201
—
C0603X5R1C104
K030BC
TDK
15
C52
1
6800 pF
C0201
—
GRM033R71A68
2KA01D
Murata
CAP CER 6800 pF 10 V X7R
0201
16
C59, C75, C78, C175
4
1.5 nF
C0201
—
GRM033R71A15
2KA01D
Murata
CAP CER 1500 pF 10 V X7R
0201
17
C75, C78, C59, C175
4
1.5 nF
C0201
Piggyback
Configuration
GRM033R71A15
2KA01D
Murata
CAP CER 1500 pF 10 V X7R
0201
18
C72
1
4700 pF
C0306
—
LLL185R71H472
MA01L
Murata
CAP CER 4700 pF 50 V X7R
0306
19
C73, C74, C76
3
330 pF
C0201
—
GRM033R71H33
1KA12D
Murata
20
C77
1
5600 pF
C0201
—
GRM033R71A56
2KA01D
Murata
21
C94, C96
2
10 µF
C0603
—
CL10X106MP8N
RNC
Samsung
22
C102, C104, C105, C139,
C142, C143, C144, C147,
C148, C151, C152
11
0.1 µF
C0201
-—
C0603X5R1C104
K030BC
TDK
23
C103, C140, C146, C149,
C154
5
0.01 µF
C0201
—
CC0201KRX7R7B
B103
Yageo
24
C106
1
1 µF
C0402
—
C0402C105K9PA
CTU
Kemet
25
C115, C130
2
10 µF
C0603
—
CL10A106MA8N
RNC
Samsung
26
C123
1
0.1 µF
C0603
—
GRM188R71E10
4KA01D
Murata
27
C127
1
680 pF
C0603
—
C0603C681J3GA
CTU
Kemet
10 V 10% X5R 0402
CAP CER
0.1 µF 16 V X5R 0201
CAP CER
330 pF 50 V X7R 0201
CAP CER 5600 pF 10 V X7R
0201
CAP CER
10 µF 10 V 20% X6S 0603
CAP CER
0.1 µF 16 V 10% X5R 0201
CAP CER 10000 pF
16 V 10% X7R 0201
CAP CERAMIC
1 µF 6.3 V X5R 0402
CAP CER
10 µF 25 V 20% X5R 0603
CAP CER
0.1 µF 25 V 10% X7R 0603
CAP CER
680 pF 25 V 5% NP0 0603
© 2016-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02010-1.6
29
CrossLink LIF-MD6000 Master Link Board - Revision B
Evaluation Board User Guide
Item
Reference
Quantity
Part
PCB
Footprint
Comments
PART_NUMBER
Manufacturer
Description
28
C128
1
0.47 µF
C0402
—
CL05A474KA5NN
Samsung
NC
CAP CER 0.47 µF 25 V 10%
X5R 0402
29
C129
1
47 µF
C0805
—
C2012X5R1A476
M125AC
TDK
CAP CER
30
C155, C156, C157, C158,
C159, C160, C161, C162,
C163, C164, C165, C166,
C167, C168, C169, C170
16
0.1 µF
C0402
—
04023C104KAT2
A
AVX
31
C173
1
2200 pF
C0201
—
GRM033R71E22
2KA12D
Murata
CAP CER 2200 pF 25 V X7R
0201
32
C174
1
1000 pF
C0201
—
GRM033R61E10
2KA01D
Murata
CAP CER 1000 pF 25 V X5R
0201
33
C178
1
0.1 µF
C0201
—
GRM033R61C10
4KE84D
Murata
34
D1, D14
2
SL44-E3/
57T
SL44E357T
—
SL44-E3/57T
Vishay
semiconductor
Schottky Diodes &
Rectifiers 4.0 A 40 V
35
D3, D25, D26, D27, D28,
D29
6
Green
led_0603
—
LTST-C190KGKT
LITE-On INC
LED SUPER GREEN CLEAR
0603 SMD
36
D6, D7, D8, D9, D30, D31,
D32, D33
8
blue
led_0603
—
LTST-C193TBKT5A
LITE-On INC
Standard LEDs - SMD Blue
470 nm 28mcd 5 mA
37
D10
1
Green
led_0603
—
LG L29K-G2J124-Z
OSRAM
LED SUPER GREEN CLEAR
0603 SMD
38
D12
1
0.3 VF
MBRA340T3
—
G
MBRA340T3G
ON Semi
DIODE SCHOTTKY 40 V 3 A
SMA
39
D23
1
Red
led_0603
LTST-C193KRKT5A
LITE-On INC
Standard LEDs - SMD Red
631 nm 14mcd 5 mA
—
47 µF 10 V 20% X5R 0805
CAP CER
0.1 µF 25 V 10% X7R 0402
CAP CER
0.1 µF 16 V X5R 0201
© 2016-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
30
FPGA-EB-02010-1.6
CrossLink LIF-MD6000 Master Link Board - Revision B
Evaluation Board User Guide
Item
Reference
Quantity
Part
PCB
Footprint
Comments
PART_NUMBER
Manufacturer
Description
—
Square test point, 40 mil
inner diameter,
VCC_DPHY1, VCC_CORE1,
VCCIO1, GND1, VCCIO2,
GND2, GND3, GND4,
GND5, 1K_VCCIO0,
1K_VCC_CORE1,
1K_VCCIO1, 1V2,
1K_VCCIO2, 1K_VCCIO3,
TP18, TP23, TP24, TP25,
2V5, 3V3, 5V0, 12V0,
VCCIO0
24
41
J1
1
header_
1x8
hdr_amp_8
7220_8_1x8
_100
—
22-28-4081
Molex
CONN HEADER 8POS .100
VERT TIN
42
J2
1
SKT_MINIUS skt_miniusb
B_B_RA
_b_ra
—
5075BMR-05SM-CR
Neltron
CONN MINI USB RCPT RA
TYPE B SMD
43
J3
1
PJ-032A
PJ-032A
—
PJ-032A
CUI Inc.
44
J4, J22
2
73391-0060
73391-0060
—
73391-0060
Molex
CONN SMA JACK STR 50
OHM PCB
45
J7, J19, J20
3
CON2
CON2
REGULAR 100
MIL HEADER
—
—
General 100 mils
2 Position header
46
J8, J9
2
2 Position
Terminal
Block_0
TERM_BLOC
K_2POS_10 —
A
1727010
Phoenix
Contact
TERM BLOCK 2POS 3.81
mm PCB GRN
47
J18
1
48
J23
1
49
J24, J25, J26, J27
50
J28
40
TP_S_40_63
HEADER
tp_s_
40_63
DNI
—
63 mil outer diameter
CON PWR JCK
2.0 X 6.5 M VERT
HEADER 2X5
REGULAR 100
MIL HEADER
—
—
General 100 Mils
2*5 header
4 HEADER
CON4
REGULAR 100
MIL HEADER
—
—
General 100 Mils
4 Position Header
4
Tri-Con
TriCon
REGULAR 100
MIL HEADER
—
—
General 100 Mils Header
1
CON6
HDR1X6
REGULAR 100
MIL HEADER
—
—
—
5X2
© 2016-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02010-1.6
31
CrossLink LIF-MD6000 Master Link Board - Revision B
Evaluation Board User Guide
Item
Reference
Quantity
Part
PCB
Footprint
Comments
PART_NUMBER
Manufacturer
Description
CON3
HDR1X3
REGULAR 100
MIL HEADER
—
—
—
FB0603
—
BLM18AG601SN
1D
Murata
Ferrite Bead 600 Ω @100
MHz 500 mA 0603
51
J29
1
52
L1, L2, L3, L4, L5, L6, L7
7
53
L8
1
4.7 uH
MPLC0730L
4R7
—
MPLC0730L4R7
Kemet
54
MH1, MH2, MH3, MH4,
MH5, MH6, MH7, MH8,
MH9, MH10
10
Thru Hole
MTG125
DNL
—
—
—
55
Q9, Q10, Q11
3
MMBT2222
A
SM_
SOT23-3
—
MMBT2222A,21
5
NXP
Semiconductor
TRANS NPN 40 V 0.6 A
SOT23
56
R1, R2, R3, R56, R131,
R175, R176, R177, R178,
R403, R404, R405, R440,
R445, R477, R478, R479,
R480, R483, R484
20
4.7K
R0603
—
CRCW06034K70
FKEA
Vishay
4.7 kΩ HM 1% 1/10 W
0603
57
R4, R5, R6, R7, R15, R16,
R26, R37, R39, R51, R52,
R53, R90, R159, R165,
R167, R180, R181, R183,
R192, R431, R433, R447
23
0
R0603
—
RC0603JR-070RL
Yageo
Res 1/10 W 0.0 Ω 5% 0603
58
R9, R10
2
2K2
R0603
—
CRCW06032K20
FKEA
Vishay
59
R11, R17
2
12K
R0603
—
RC0603FR0712KL
Yageo
60
R12, R13, R14, R123,
R124, R125
6
—
RMCF0603JT10K
0
Stackpole
Electronics Inc
R18, R418, R419, R422,
R423
5
RC0603JR-070RL
Yageo
61
600 Ω
500 mA
10K
0
R0603
R0603
DNI
INDUCTOR POWER
4.7 uH 20% SMD
RES SMD
RES SMD
2.2 kΩ 1% 1/10 W 0603
RES SMD
12 kΩ 1% 1/10 W 0603
RES SMD
10 kΩ 5%
1/10 W 0603
Res 1/10 W 0.0 Ω 5% 0603
© 2016-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
32
FPGA-EB-02010-1.6
CrossLink LIF-MD6000 Master Link Board - Revision B
Evaluation Board User Guide
Item
Reference
Quantity
Part
PCB
Footprint
Comments
PART_NUMBER
Manufacturer
Description
62
R19, R20, R21, R25, R28,
R33, R184, R186, R188,
R190, R410, R417, R434,
R435, R448, R449
16
1
R0603
—
CRCW06031R00J
Vishay/Dale
NEAHP
RES SMD
63
R22, R144
2
100E
R0603
DNI
CRCW0603100R
FKEAHP
Vishay / Dale
RES SMD 100 Ω 1% 1/4W
0603
64
R23
1
0
R0603
DNI
RC0603JR-070RL
Yageo
Res 1/10 W 0.0 Ω 5% 0603
65
R24, R185, R187, R189,
R411
5
1
R0603
DNI
CRCW06031R00J
Vishay/Dale
NEAHP
66
R36, R233
2
1K
R0603
—
RC0603FR-071KL Yageo
67
R54, R55, R57, R59
4
680R
R0402
DNI
RMCF0402JT680
R
Stackpole
Electronics Inc
RES 680 Ω 1/16 W 5% 0402
68
R60, R61, R446, R457,
R458, R459, R460, R461,
R462, R463, R464, R467,
R468, R469, R470, R471,
R472, R473, R474, R475,
R476
21
0
R0402
—
RC0402JR-070RL
Yageo
RES SMD 0.0O HM JUMPER
1/16 W 0402
69
R76, R77
2
2K
R0402
—
ERJ-2RKF2001X
Panasonic
70
R78
1
10K
R0402
—
RMCF0402JT10K
0
Stackpole
Electronics Inc
RES 10 kΩ 1/16 W 5% 0402
71
R80, R436, R437, R438,
R439
5
680R
R0402
—
RMCF0402JT680
R
Stackpole
Electronics Inc
RES 680 Ω 1/16 W 5% 0402
72
R83
1
30E
R0603
—
RC0603FR0730RL
Yageo
73
R106, R107, R108, R110,
R111, R113, R114, R117,
R119, R121
10
100
R0402
DNI
RC0402FR07100RL
Yageo
74
R160, R432
2
100K
R0402
—
RMCF0402JT100
K
Stackpole
Electronics Inc
1 Ω 5% 1/4W 0603
RES SMD
1 Ω 5% 1/4W 0603
RES SMD
1 kΩ 1% 1/10 W 0603
RES SMD
2 kΩ 1% 1/10 W 0402
RES SMD
30 Ω 1% 1/10 W 0603
RES SMD 100 Ω
1% 1/16 W 0402
RES 100 kΩ 1/16 W 5%
0402
© 2016-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02010-1.6
33
CrossLink LIF-MD6000 Master Link Board - Revision B
Evaluation Board User Guide
Item
Reference
Quantity
Part
PCB
Footprint
Comments
PART_NUMBER
Manufacturer
Description
75
R166, R441, R442, R443,
R444
5
1K
R0402
—
RMCF0402JT1K0
0
Stackpole
Electronics Inc
RES 1 kΩ 1/16 W 5% 0402
76
R179
1
650
R0603
—
RC0603FR07649RL
Yageo
RES SMD 649 Ω 1% 1/10 W
0603
77
R229
1
15K
R0402
—
ERJ-2RKF1502X
Panasonic
RES 15 kΩ 1/10 W 1% 0402
SMD
78
R230
1
34K
R0402
—
ERJ-2RKF3402X
Panasonic
RES 34 kΩ 1/10 W 1% 0402
SMD
79
R231
1
536K
R0402
—
ERJ-2RKF5363X
Panasonic
Electronic
Components
RES 536 kΩ 1/10 W 1%
0402 SMD
80
R232
1
100K
R0402
—
ERJ-2RKF1003X
Panasonic
Electronic
Components
RES 100 kΩ 1/10 W 1%
0402 SMD
81
R395, R399, R400
3
10K
R0603
—
ERJ-3EKF1002V
Panasonic
82
R412, R413, R414, R415,
R416, R420, R421, R424,
R425, R451, R452, R453,
R454, R455, R456, R465,
R466
17
0
R0603
—
RC0603JR-070RL
Yageo
Res 1/10 W 0.0 Ω 5% 0603
83
R450
1
0
R0402
DNI
RC0402JR-070RL
Yageo
RES SMD 0.0O HM JUMPER
1/16 W 0402
84
R481, R482
2
0
R0603
DNL
RC0603JR-070RL
Yageo
Res 1/10 W 0.0 Ω 5% 0603
85
SW1
1
PWR
TS01CQE_s
witch
—
TS01CQE
C&K
Components
SWITCH SLIDE SPDT
86
SW2, SW3, SW4
3
2psmd_eswi
—
tch
TL1015AF160QG
E-Switch
SWITCH TACTILE SPST-NO
0.05 A 12 V
87
SW5
1
2psmd_eswi
—
tch
TL1015AF160QG
E-Switch
SWITCH TACTILE SPST-NO
0.05 A 12 V
SYS_
RST
WAKE_
UP
RES SMD
10 kΩ 1% 1/10 W 0603
3 A 120 V
© 2016-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
34
FPGA-EB-02010-1.6
CrossLink LIF-MD6000 Master Link Board - Revision B
Evaluation Board User Guide
Item
Reference
Quantity
Part
PCB
Footprint
Comments
PART_NUMBER
Manufacturer
Description
88
U1
1
FT2232HL
tqfp64_0p5
_12p2x12p2 —
_h1p6
FT2232HL
FTDI
USB to UART / FIFO
89
U2
1
93LC56-SO8
so8_50_244
—
93LC56C-I/SN
Microchip
IC 93LC56 EEPROM
90
U3
1
FUSE
0154004DR
T
—
0154004.DRT
Littlefuse
Surface Mount Fuses
Fuseblock with fuse 4A
OMNI BLOK 154T
91
U5
1
NCP1117ST
33T3G
sot223_4p
—
NCP1117ST33T3
G
On Semi
IC Reg LDO 3.3 V SOT-223
92
U6
1
NCP1117ST
25T3G
sot223_4p
—
NCP1117ST25T3
G
On Semi
IC Reg LDO 2.5 V SOT-223
4
Hirose FX12 - 40
Pos
Hirose-FX12
—
FX12B-40P0.4SV
Hirose Electric
Co Ltd
1
LIFMD6000csfBGA81
LIFMD6000csfBGA81
Customer
supplied
LIF-MD6000csfBGA81
Lattice
Semiconductor
1
M25PX16VMW6TG
SOIC8
—
M25PX16VMW6TG
Micron
Technology Inc
93
94
95
U7, U9, U11, U12
U8
U14
Conn Board to Board PL 40
POS
0.4 mm Solder ST SMD T/R
Lattice Semiconductor 6K
CrossLink FPGA Family
IC FLASH
16 Mbit
75 MHz 8SO
96
U15
1
AP731312SAG-7
SOT23
—
AP7313-12SAG-7 Diodes Inc
LDO Voltage Regulators
LDO SOT-23R
1.2 V/ 150 mA
97
U17
1
NCP1117ST
18T3G
sot223_4p
—
NCP1117ST18T3
G
On Semi
IC Reg LDO 1.8 V SOT-223
98
U18
1
LT3680
LT3680_10Q
—
FN
LT3680EDD#PBF
Linear
5 V Step down converter
99
U19
1
LCMXO3LF1200EMG121
LCMXO3LF1200EMG121
Customer
supplied
LCMXO3LF1200E-MG121
Lattice
Semiconductor
12MHZ
crystal_4p_
3p2x2p5
—
7M12.000MAAJ-T
TXC
100
X1
1
CPLD MachXO3 Family
121-Pin CSFBGA0.5 mm Pitch
12 MHz Crystal
© 2016-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02010-1.6
35
CrossLink LIF-MD6000 Master Link Board - Revision B
Evaluation Board User Guide
Item
Reference
Quantity
Part
PCB
Footprint
Comments
PART_NUMBER
Manufacturer
Description
101
X3, X4
2
KC3225A27.
27MHZ_OSC —
0000C30E0A
KC3225A27.0000 AVX
C30E0A
Corporation
Standard Clock Oscillators
27.000 MHz
102
LIF-MD6000 MASTER
LINK REV B BOARD PCB
1
—
305-PD-16-0154
—
—
—
PACTRON
© 2016-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
36
FPGA-EB-02010-1.6
CrossLink LIF-MD6000 Master Link Board - Revision B
Evaluation Board User Guide
Appendix C. SMA-IOL-EVN-BRD Schematics
5
4
3
2
1
J1
CH4_DCK_TX_P
U1
1
2
3
CH4_DATA0_TX_P
CH4_DATA0_TX_N
4
5
6
CH4_DATA1_TX_P
CH4_DATA1_TX_N
7
8
9
1
1
10
11
SN
SCLK
CH4_DATA2_TX_P
CH4_DATA2_TX_N
12
13
14
CH4_DATA3_TX_P
CH4_DATA3_TX_N
15
16
17
18
19
20
C
43
44
41
CH4_DCK_P
CH4_DCK_N
GND1
TBD
RESETN
PWR_5-0V
CH4_DATA0_P
CH4_DATA0_N
GND2
GND7
GND8
PWR_3-3V
CH4_DATA1_P
CH4_DATA1_N
GND3
GND9
GND10
PWR_1-8V
SN
SCLK
GND4
CH4_DATA2_P
CH4_DATA2_N
GND5
CH4_DATA3_P
CH4_DATA3_N
GND6
12V
12V
MOSI
MISO
PWR_1-8V
GND11
GND12
PWR_3-3V
GND13
GND14
PWR_5-0V
SDA
SCL
Shield3
Shield4
Shield5
Shield6
Shield1
Shield2
21
22
23
CH4_DCK_TX_N
2
3
4
5
+5V +3.3V +1.8V
TX Connector1
CH4_DCK_TX_P
CH4_DCK_TX_N
D
J2
1
73391-0060
J11
1
CH4_DATA4_TX_P
2
3
4
5
73391-0060
1
2
3
4
5
73391-0060
RESETN 1
D
24
25
26
CH4_DATA4_TX_P
CH4_DATA4_TX_N
27
28
29
CH4_DATA5_TX_P
CH4_DATA5_TX_N
J3
CH4_DATA0_TX_P
30
31
MOSI
MISO
J4
1
2
3
4
5
1
1
CH4_DATA0_TX_N
73391-0060
J12
1
CH4_DATA4_TX_N
2
3
4
5
73391-0060
1
2
3
4
5
73391-0060
32
33
34
+1.8V
35
36
37
Note : Plae 0.01uF caps near each connector(U1)
38
39
40
1
SCL
45
46
J5
CH4_DATA1_TX_P
SDA
C1
C2
C3
1uF
0.1uF
0.01uF
J6
1
2
3
4
5
CH4_DATA1_TX_N
73391-0060
J13
1
CH4_DATA5_TX_P
2
3
4
5
73391-0060
1
2
3
4
5
C
73391-0060
1
42
Hirose - FX12 - 40 Pos
J7
CH4_DATA2_TX_P
J8
1
2
3
4
5
CH4_DATA2_TX_N
73391-0060
J14
1
CH4_DATA5_TX_N
2
3
4
5
73391-0060
1
2
3
4
5
73391-0060
+3.3V
Note : Plae 0.01uF caps near each connector(U1)
J9
B
CH4_DATA3_TX_P
C4
C5
C6
1uF
0.1uF
0.01uF
1
J10
2
3
4
5
CH4_DATA3_TX_N
73391-0060
+5V
+3.3V
+1.8V
GND
2
3
4
5
B
73391-0060
GND1
1
+1.8V
1
+3.3V
1
+5V
ThruHole
1
MH2
ThruHole
1
MH1
1
Note : Test point silk screen name should be same as the respective power rails
A
A
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
T i tl e
SMA DEBUG BOARD
Size
B
Date:
5
4
3
Project
LCMXO3L-4300-MG256 MIPI Briding solution
04-May-15
2
Sheet
Schematic Rev
1.0
Board Rev
1 of 1
A
1
Figure C.1. SMA Debug Board
© 2016-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02010-1.6
37
CrossLink LIF-MD6000 Master Link Board - Revision B
Evaluation Board User Guide
Appendix D. SMA-IOL-EVN-BRD Bill of Materials
SMA I/O Link Board Bill of Materials
Item
Reference
Qty
Part
PCB Footprint
Comments
PART_NUMBER
Manufacturer
Description
1
GND1, +5 V, +1.8 V,
+3.3 V, SN, SDA, SCLK,
SCL, RESETN, MOSI,
MISO, GND
12
TP_S_40_63
tp_s_40_63
DNI
—
—
Square test point, 40 mil
inner diameter, 63 mil
outer diameter
2
C1, C4
2
1 µF
C0402
—
C0402C105K9PACTU
Kemet
3
C2, C5
2
0.1 µF
C0402
—
C0402C104K4RACTU
Kemet
4
C3, C6
2
0.01 µF
C0402
—
C0402C103J4RACTU
Kemet
5
J1, J2, J3, J4, J5, J6, J7,
J8, J9, J10, J11, J12,
J13, J14
14
73391-0060
73391-0060
—
73391-0060
Molex
6
MH1, MH2
2
Thru Hole
MTG125
—
—
—
—
7
U1
1
Hirose - FX12 40 Pos
Hirose-FX12S
—
FX12B-40S-0.4SV
Hirose Electric Co
Ltd
Conn Board to Board PL 40
POS
0.4 mm Solder ST SMD T/R
8
SMA IOLINK BOARD
PCB
1
—
—
—
305-PD-15-0589
PACTRON
—
CAP CERAMIC
1 µF 6.3 V X5R 0402
CAP CERAMIC 0.1 µF 16 V
X7R 0402
CAP CERAMIC
10 nF 16 V 5% X7R 0402
Molex Straight 50O
Through Hole SMA
Connector, jack, Solder
Termination
© 2016-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
38
FPGA-EB-02010-1.6
CrossLink LIF-MD6000 Master Link Board - Revision B
Evaluation Board User Guide
Appendix E. B-IOL-EVN-BRD Schematics
5
4
3
U1
2
1
+5V +3.3V +1.8V
+1.8V
CH4_DCK_TX_P
CH4_DCK_TX_N
1
2
3
CH4_DATA0_TX_P
CH4_DATA0_TX_N
4
5
6
CH4_DATA1_TX_P
CH4_DATA1_TX_N
1
1
7
8
9
10
11
SN
SCLK
CH4_DATA2_TX_P
CH4_DATA2_TX_N
12
13
14
CH4_DATA3_TX_P
CH4_DATA3_TX_N
15
16
17
18
19
20
C
43
44
41
CH4_DCK_P
CH4_DCK_N
GND1
TBD
RESETN
PWR_5-0V
CH4_DATA0_P
CH4_DATA0_N
GND2
GND7
GND8
PWR_3-3V
CH4_DATA1_P
CH4_DATA1_N
GND3
SN
SCLK
GND4
CH4_DATA2_P
CH4_DATA2_N
GND5
CH4_DATA3_P
CH4_DATA3_N
GND6
12V
12V
TX Connector1
D
GND9
GND10
PWR_1-8V
MOSI
MISO
PWR_1-8V
GND11
GND12
PWR_3-3V
GND13
GND14
PWR_5-0V
SDA
SCL
Shield3
Shield4
Shield5
Shield6
Shield1
Shield2
Note : Plae 0.01uF caps near each connector(1)
21
22
23
+1.8V
RESETN
24
25
26
CH4_DATA4_TX_P
CH4_DATA4_TX_N
27
28
29
CH4_DATA5_TX_P
CH4_DATA5_TX_N
30
31
MOSI
MISO
C3
C1
C2
1uF
0.1uF
0.01uF
2
4
6
8
10
12
14
16
18
20
22
24
26
CH4_DCK_TX_P
CH4_DCK_TX_N
CH4_DATA0_TX_P
CH4_DATA0_TX_N
CH4_DATA1_TX_P
CH4_DATA1_TX_N
1
1
CH4_DATA2_TX_P
CH4_DATA2_TX_N
32
33
34
+3.3V
J2
35
36
37
1
3
5
7
9
11
13
15
17
19
21
23
25
D
RESETN
SDA
SCL
CH4_DATA3_TX_P
CH4_DATA3_TX_N
CH4_DATA4_TX_P
CH4_DATA4_TX_N
CH4_DATA5_TX_P
CH4_DATA5_TX_N
HEADER 13X2
+3.3V
38
39
40
Note : Plae 0.01uF caps near each connector(1)
SDA
SCL
C
45
46
C4
C5
C6
1uF
0.1uF
0.01uF
42
Hirose - FX12 - 40 Pos
B
B
+5V
+3.3V
+1.8V
GND
GND1
1
+1.8V
1
+3.3V
1
+5V
ThruHole
1
MH2
ThruHole
1
MH1
Note : Test point silk screen name should be same as the respective power rails
A
A
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Title
100MILS_DEBUG HEADER
Size
B
Date:
5
4
3
Project
LCMXO3L-4300-MG256 MIPI Briding solution
04-May-15
2
Sheet
Schematic Rev
1.0
Board Rev
1
of 1
A
1
Figure E.1. 100MILS_DEBUG Header
© 2016-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02010-1.6
39
CrossLink LIF-MD6000 Master Link Board - Revision B
Evaluation Board User Guide
Appendix F. B-IOL-EVN-BRD Bill of Materials
Breakout I/O Link Board Bill of Materials
Item
Reference
Qty
Part
PCB Footprint
Comments
PART_NUMBER
Manufacturer
Description
1
GND1, +5 V, +1.8 V,
+3.3 V, SN, SCLK,
MOSI, MISO, GND
9
TP_S_40_63
tp_s_40_63
DNL
—
—
2
C1, C5
2
0.1 µF
C0402
—
C0402C104K4RACTU
Kemet
3
C2, C6
2
0.01 µF
C0402
—
C0402C103J4RACTU
Kemet
4
C3, C4
2
1 µF
C0402
—
C0402C105K9PACTU
Kemet
5
J2
1
HEADER 13X2
13X2_HDR
REGULAR 100 MIL
HEADER
—
—
—
6
MH1, MH2
2
ThruHole
MTG125
DNL
—
—
—
7
U1
1
Hirose - FX12 40 Pos
Hirose-FX12S
—
FX12B-40S-0.4SV
Hirose Electric Co
Ltd
Conn Board to Board PL 40
POS 0.4 mm Solder ST
SMD T/R
8
BREAKOUT IOLINK
BOARD PCB
1
—
—
—
305-PD-15-0595
PACTRON
—
Square test point, 40 mil
inner diameter,
63 mil outer diameter
CAP CERAMIC 0.1 µF 16 V
X7R 0402
CAP CERAMIC
10 nF 16 V 5% X7R 0402
CAP CERAMIC
1 µF 6.3 V X5R 0402
© 2016-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
40
FPGA-EB-02010-1.6
CrossLink LIF-MD6000 Master Link Board - Revision B
Evaluation Board User Guide
References
For more information, refer to FPGA-DS-02007 (previously DS1055), CrossLink Family Data Sheet.
© 2016-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02010-1.6
41
CrossLink LIF-MD6000 Master Link Board - Revision B
Evaluation Board User Guide
Technical Support Assistance
Submit a technical support case through www.latticesemi.com/techsupport.
© 2016-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
42
FPGA-EB-02010-1.6
CrossLink LIF-MD6000 Master Link Board - Revision B
Evaluation Board User Guide
Revision History
Revision 1.6, September 2021
Section
Change Summary
All
Minor adjustments in formatting across the document.
Updated last page of the document.
Added this section.
Disclaimers
Breakout I/O Link Board
Revision History
Updated Table 7.2 to change Name column to Connector Pin Name and add Net Name
column.
Updated table to new template.
Revision 1.5, June 2018
Section
All
Headers and Test Connections
Programming Circuit
Power Supply
Revision History
Change Summary
Changed document name to CrossLink LIF-MD6000 Master Link Board - Revision B
Evaluation Board User Guide.
Specified Rev B in all references to the board.
Updated Table 2.1.
Corrected device name to MachXO3 LCMXO3LF-1300E.
Updated this section.
Updated table to new template.
Revision 1.4 April 2018
Section
Appendix A. LIF-MD6000-MLEVN-BRD Schematics
Change Summary
Made schematics searchable.
Revision 1.3 March 2018
Section
Headers and Test Connections
Change Summary
Added footnote in Table 2.1.
Revision 1.2 September 2017
Section
All
Headers and Test Connections
Appendix E. B-IOL-EVN-BRD
Schematics
Change Summary
Changed document number from EB105 to FPGA-EB-02010.
Changed J25 from VCCIO1 to VCCIO2 in Table 2.1.
Updated 100MILS_DEBUG header.
Revision 1.1, April 2017
Section
SMA I/O Link Board
Breakout I/O Link Board
Ordering Information
Appendix A. LIF-MD6000-MLEVN-BRD Schematics
Change Summary
Added this section.
Added this section.
Added this section.
Changed “SW4 SYS_RST” to “SW4 EXT_RST” in the Bank 1, 2 – LVDS Rx diagram.
Changed “EXTERNAL RESET” to “SYSTEM RESET” in the Bank0, Flash Interface diagram.
© 2016-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02010-1.6
43
CrossLink LIF-MD6000 Master Link Board - Revision B
Evaluation Board User Guide
Revision 1.0, May 2016
Section
All
Change Summary
First release.
© 2016-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
44
FPGA-EB-02010-1.6
www.latticesemi.com