Low Power Double Data Rate (LPDDR3) SDRAM Controller IP Core User’s Guide
September 2014
IPUG110_1.0
Table of Contents
Chapter 1. Introduction .......................................................................................................................... 4
Quick Facts ........................................................................................................................................................... 4
Features ................................................................................................................................................................ 4
Chapter 2. Functional Description ........................................................................................................ 6
Overview ............................................................................................................................................................... 6
LPDDR3 MC Module............................................................................................................................................. 7
Command Decode Logic.............................................................................................................................. 7
Command Application Logic ........................................................................................................................ 7
On-Die Termination...................................................................................................................................... 7
LPDDR3 PHY Module........................................................................................................................................... 7
Initialization Module............................................................................................................................................... 7
Write Leveling .............................................................................................................................................. 7
Read Training............................................................................................................................................... 8
PHY Control Block ....................................................................................................................................... 8
Data Path Logic............................................................................................................................................ 8
Signal Descriptions ............................................................................................................................................... 9
Using the Local User Interface............................................................................................................................ 11
Initialization Control.................................................................................................................................... 11
Command and Address ............................................................................................................................. 12
User Commands ........................................................................................................................................ 14
WRITE........................................................................................................................................................ 14
WRITEA ..................................................................................................................................................... 15
READ ......................................................................................................................................................... 15
READA....................................................................................................................................................... 16
REFRESH Support .................................................................................................................................... 16
Local-to-Memory Address Mapping .................................................................................................................... 17
Mode Register Access ........................................................................................................................................ 17
Chapter 3. Parameter Settings ............................................................................................................ 19
Type Tab ............................................................................................................................................................. 21
Select Memory ........................................................................................................................................... 21
Clock .......................................................................................................................................................... 21
Memory Type ............................................................................................................................................. 21
Memory Data Bus Size .............................................................................................................................. 21
Configuration.............................................................................................................................................. 21
Chip Select Width....................................................................................................................................... 22
Clock Width ................................................................................................................................................ 22
CKE Width.................................................................................................................................................. 22
Data_rdy to Write Data Delay .................................................................................................................... 22
Write Leveling ............................................................................................................................................ 22
Setting Tab.......................................................................................................................................................... 22
Row Size .................................................................................................................................................... 23
Column Size............................................................................................................................................... 23
Refresh Type.............................................................................................................................................. 23
Refresh Bank ............................................................................................................................................. 23
Auto Refresh Burst Count .......................................................................................................................... 23
External Auto Refresh Port ........................................................................................................................ 23
Burst Length............................................................................................................................................... 23
READ Latency............................................................................................................................................ 23
Write Latency ............................................................................................................................................. 23
© 2014 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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LPDDR3 SDRAM Controller IP Core User’s Guide
Table of Contents
Write Recovery........................................................................................................................................... 23
DS (ohm).................................................................................................................................................... 23
DQ_ODT .................................................................................................................................................... 24
Memory Device Timing Tab ................................................................................................................................ 24
Manually Adjust.......................................................................................................................................... 25
tCLK - Memory clock.................................................................................................................................. 25
Command and Address Timing.................................................................................................................. 25
Calibration Timing ...................................................................................................................................... 25
Refresh, Reset and Power Down Timing ................................................................................................... 25
Write Leveling Timing................................................................................................................................. 25
Chapter 4. IP Core Generation and Evaluation .................................................................................. 26
Getting Started .................................................................................................................................................... 26
Clarity Designer-Created Files and IP Top Level Directory Structure................................................................. 29
LPDDR3 Memory Controller IP File Structure............................................................................................ 31
Simulation Files for IP Evaluation .............................................................................................................. 32
Hardware Evaluation........................................................................................................................................... 33
Enabling Hardware Evaluation in Diamond:............................................................................................... 33
Regenerating/Recreating the IP Core ................................................................................................................. 33
Regenerating an IP Core in Clarity Designer Tool ..................................................................................... 33
Recreating an IP Core in Clarity Designer Tool ......................................................................................... 33
Chapter 5. Application Support........................................................................................................... 35
Understanding Preferences ................................................................................................................................ 35
FREQUENCY Preferences ........................................................................................................................ 35
MAXDELAY NET ....................................................................................................................................... 35
MULTICYCLE / BLOCK PATH................................................................................................................... 35
IOBUF ........................................................................................................................................................ 35
Dummy Logic in Core Evaluation........................................................................................................................ 35
Top-level Wrapper File Only for Evaluation Implementation............................................................................... 35
Top-level Wrapper file for All Simulation Cases and Implementation in a User’s Design ................................... 36
Chapter 6. Core Validation................................................................................................................... 37
Chapter 7. Support Resources ............................................................................................................ 38
Lattice Technical Support.................................................................................................................................... 38
E-mail Support ........................................................................................................................................... 38
Local Support ............................................................................................................................................. 38
Internet ....................................................................................................................................................... 38
JEDEC Website ......................................................................................................................................... 38
References.......................................................................................................................................................... 38
Revision History .................................................................................................................................................. 38
Appendix A. Resource Utilization ....................................................................................................... 39
ECP5 Devices ..................................................................................................................................................... 39
Ordering Part Number................................................................................................................................ 39
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LPDDR3 SDRAM Controller IP Core User’s Guide
Chapter 1:
Introduction
The Lattice Low Power Double Data Rate (LPDDR3) Synchronous Dynamic Random Access Memory (SDRAM)
Controller is a general-purpose memory controller that interfaces with industry standard LPDDR3 memory devices
compliant with JESD209-3, LPDDR3 SDRAM Standard, and provides a generic command interface to user applications. LPDDR3 SDRAM is the next-generation Low Power SDRAM memory technology which offers a higher
data rate, higher density, greater bandwidth and power efficiency. This core reduces the effort required to integrate
the LPDDR3 memory controller with the user application design and minimizes the need to directly deal with the
LPDDR3 memory interface.
Quick Facts
Table 1-1 gives quick facts about the LPDDR3 SDRAM Controller IP core.
Table 1-1. LPDDR3 IP Core Quick Facts1
LPDDR3 IP Configuration
x16
Core
Requirements
FPGA Families
Supported
Minimal Device
Needed
Resource
Utilization
x32
ECP5™
LFE5U-25F-6MG285C/
LAE5UM-25F-6MG285E
Targeted Device
LFE5UM-85F-8BG756CES
Data Path Width
16
LUTs
32
2241
2462
sysMEM EBRs
0
Registers
Design Tool
Support
1599
Lattice
Implementation
1937
®
Lattice Diamond 3.3
Synopsys® Synplify Pro® for Lattice I-2014.03L-SP1
Synthesis
Simulation
LFE5U-25F-6MG285C/
LAE5UM-25F-6MG285E1
Lattice Synthesis Engine (LSE)
Aldec® Active-HDL® 9.3 Lattice Edition II Mixed Language
Mentor Graphics® ModelSim® SE PLUS 6.5 or later
1. LFE5U-25F-6MG381C/LAE5UM-25F-6MG381E for the core evaluation project inside a generated core
Features
The LPDDR3 SDRAM Controller IP core supports the following features:
• Support for all ECP5 devices
• Interfaces to industry standard LPDDR3 SDRAM components and modules compliant with JESD209-3,
LPDDR3 SDRAM Standard
• Interfaces to LPDDR3 SDRAM at speeds up to 400 MHz / 800 Mbps in -8 speed grade devices
• Supports memory data path widths of 16 and 32 bits
• Supports x16 and x32 device configurations
• Supports single rank of an LPDDR3 device (one chip select)
• Supports burst lengths of eight (fixed)
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LPDDR3 SDRAM Controller IP Core User’s Guide
Introduction
• Programmable read and write latency set
• Supports automatic LPDDR3 SDRAM initialization and refresh
• Optional write leveling support for each DQS
• Automatic read training for each DQS
• Supports Deep Power Down mode and Power down mode
• Supports Partial Array Self Refresh (PASR) operations on Bank and Segment
• Supports Dynamic On-Die Termination (ODT) controls
• Automatic programmable interval refresh or user initiated refresh
• Supports Burst or Distributed auto refresh
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LPDDR3 SDRAM Controller IP Core User’s Guide
Chapter 2:
Functional Description
This chapter provides a functional description of the LPDDR3 SDRAM Controller IP core.
Overview
The LPDDR3 memory controller consists of two major parts: Memory controller (MC) module and I/O (PHY) module. This section briefly describes the operation of each of these modules. Figure 2-1 provides a high-level block
diagram illustrating the main functional blocks and the technology used to implement the LPDDR3 SDRAM Controller IP core functions.
Figure 2-1. LPDDR3 SDRAM Controller Block Diagram
init_start
inti_done
addr
DFI
I/F
em_ddr_ca
cmd
cmd_rdy
cmd_valid
cmd_burst_count
ext_auto_ref
ext_auto_ref_ack
aref_brst_enb
clock_stop
em_ddr_cs_n
Command
Decode
Logic
Command
Application
Logic
LPDDR3 MC
datain_rdy
write_data
em_ddr_dqs (+/-)
LPDDR3
PHY
em_ddr_dq
em_ddr_dm
read_data_valid
read_data
rt_req
rt_act
rt_done
rt_err
em_ddr_odt
ODT
Control
em_ddr_clk (+/-)
em_ddr_cke
wl_act
wl_err
sclk
dll_update
Clock Divider
clk_in
update_done
dcntl
eclk
DDRDLL Logic
sysCLOCK PLL
Clock Synchronization Module
The LPDDR3 memory controller consists of three sub modules: Memory Controller (MC) module, Physical Interface (PHY) module and Clock Synchronization Module (CSM). This section briefly describes the operation of each
of these modules.
The LPDDR3 MC module has the following functional sub-modules: Command Decode Logic (CDL) block, Command Application Logic (CAL) block and ODT Control block.
The LPDDR3 PHY modules provide the PHY interface to the memory device. This block mostly consists of ECP5
device DDR I/O primitives supporting compliance to LPDDR3 electrical and timing requirements. In addition, this
module consists of the logic for memory initialization, read training, write/read data path control, address/command
timing control and the optional write leveling.
Along with the LPDDR3 SDRAM Controller IP core, a separate module, called the Clock Synchronization Module
(CSM), is also provided. The CSM generates all the clock signals, such as system clock (SCLK) and edge clock
(ECLK) for the IP core.
The CSM logic ensures that all DDR components in the ECP5 device are synchronized after a system reset. CSM
also provides the logic for the DLL update operation. Without proper synchronization, the bit order on different elements might be off-sync with each other and the entire bus is scrambled. The clock synchronization ensures that all
DDR components start from exactly the same edge clock cycle.
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LPDDR3 SDRAM Controller IP Core User’s Guide
Functional Description
For 400MHz LPDDR3 memory support, the MC module operates with a 200 MHz system clock (SCLK), the I/O
logic works with a 400 MHz edge clock (ECLK). The combination of this operating clock ratio and the double data
rate transfer leads to a user side data bus that is four times the width of the memory side data bus. For example, a
32-bit memory side data width requires a 128-bit read data bus and a128-bit write data bus at the user side interface.
LPDDR3 MC Module
Command Decode Logic
The Command Decode Logic (CDL) block accepts user commands from the local interface and decodes them to
generate a sequence of internal memory commands depending on the current command and the status of current
bank and row. The intelligent bank management logic tracks the open/close status of every bank and stores the
row address of every opened bank. The controller implements a command pipeline of depth 2 to improve throughput. With this capability, the next command in the queue is decoded while the current command is presented at the
memory interface.
Command Application Logic
The Command Application Logic (CAL) block accepts the decoded internal command sequence from the Command Decode Logic and translates each sequence into appropriate memory commands that meet the operational
sequence and timing requirements of the memory device. The CDL and CAL blocks work in parallel to fill and
empty the command queue respectively.
On-Die Termination
The ODT feature is designed to improve the signal integrity of the memory channel by allowing the LPDDR3
SDRAM controller to turn on or turn off the termination resistance for LPDDR3 memory devices.
LPDDR3 PHY Module
The LPDDR3 PHY module implements a set of soft logic in the FPGA fabric for initialization, read training and
read/write paths as well as a set of hard logic, called DDR3 I/O modules, for 1:2 clock gearing and LPDDR3 memory interface. It also supports the optional write leveling. The LPDDR3 I/O modules are ECP5 device primitives that
directly connect to the LPDDR3 memory. These primitives implement all of the interface signals required for memory access. They convert the single data rate (SDR) data from the user to double rate LPDDR3 data for the write
operation and perform the DDR to SDR conversion in the read mode.
Initialization Module
The Initialization block performs the LPDDR3 memory initialization sequence as defined by LPDDR3 JEDEC protocol. After power on or a normal reset of the LPDDR3 controller, the memory must be initialized before sending any
command to the controller. It is the user's responsibility to assert the init_start input to the LPDDR3 controller to initiate the memory initialization sequence. The completion of initialization is indicated by the init_done output provided by this block.
Write Leveling
The write leveling function can be optionally enabled. Once enabled, it aligns the DQS-to-CLK relationship for each
DQS group using the write leveling procedure when the PCB wiring is supported for the write leveling. Write leveling is performed immediately after a memory initialization sequence and before the read training if write leveling is
enabled through the GUI. When the init_done signal is asserted after the initialization process it also indicates the
completion of write leveling. Along with the assertion of init_done, the signal wl_err is also asserted if the write leveling process is not successful. The write leveling scheme of the LPDDR3 SDRAM Controller IP core follows all the
steps stipulated in the JEDEC specification. For more details on write leveling, refer to the JEDEC specification
JESD209-3.
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LPDDR3 SDRAM Controller IP Core User’s Guide
Functional Description
Read Training
For every read operation, the LPDDR3 I/O primitives of the ECP5 device must be initialized at the appropriate time
to identify the incoming DQS preamble. Upon a proper detection of the preamble, the primitive DQSBUFM extracts
a clean signal out of the incoming DQS signal from the memory and generates the DATAVALID output signal that
indicates the correct timing window of the valid read data. The memory controller generates a positioning signal,
READ[1:0], to the primitive DQSBUFM that is used for the above-mentioned operation. In addition to the READ[1:0]
input, another fine control input signal READCLKSEL[2:0] and an output signal, BURSTDET, of the DQSBUFM
block are provided to the controller to accomplish the READ signal positioning. Due to the DQS round trip delay
that includes PCB routing and I/O pad delays, proper internal positioning of the READ signal with respect to the
incoming preamble is crucial for successful read operations. The ECP5 DQSBUFM block supports a dynamic
READ signal positioning function called read training that enables the memory controller to position the internal
READ signal within an appropriate timing window by progressively shifting the READ signal and monitoring the
positioning result. This read training is performed as part of the memory initialization process after the write leveling
operation is complete if enabled. During the read training, the memory controller generates the READ[1:0] pulse as
a coarse positioning control. READCLKSEL[2:0] is also generated to provide a finer position control (1/4 T per
step). The BURSTDET output of DQSBUFM is used to monitor the result of the current position. The READ[1:0]
signal is needed to be set high at least 5.5T before the read preamble starts. The internal READ is progressively
shifted by READ[1:0] and READCLKSEL[2:0] once the rad training routine starts. When the internal READ signal is
properly positioned, the BURSTDET signal will be asserted high to indicate that the preamble has been detected
correctly. This will guarantee that the generated DATAVALID signal is indicating the correct read valid time window.
The READ[1:0] and READSELCLK[2:0] signals are generated in the system clock (SCLK) domain and required to
stay asserted for the total burst length of the read operation.
The memory controller determines the proper position alignment when there is not a single failure on BURSTDET
assertions during the multiple trials. If there is any failure, the memory controller shifts the READCLKSEL[2:0] and
READ[1:0] signals accordingly to position the internal READ to a safer position and tries again until it detects no
BURSTDET failure during the entire read training process. The memory controller stores the delay value of the
successful position of the READCLKSEL[2:0] and READ[1:0] signal for each DQS group. It uses these delay values during a normal read operation to correctly detect the preamble first, followed by the generation of DATAVALID
signal.
PHY Control Block
The PHY Control Block includes the data path control and PHY timing control functions. The data path control function interfaces with the LPDDR3 I/O modules and is responsible for generating the read data and read data valid
signals during the read operations. This block also implements all the logic that are needed to ensure that the
LPDDR3 command/controls and data write/read to and from the memory are properly transferred to the local user
interface in a deterministic and coherent manner.
Data Path Logic
The Data Path Logic (DPL) block interfaces with the LPDDR3 I/O modules and is responsible for generating the
read data and read data valid signals during read operations. This block implements all the logic needed to ensure
that the data write/read to and from the memory is transferred to the local user interface in a deterministic and
coherent manner.
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LPDDR3 SDRAM Controller IP Core User’s Guide
Functional Description
Signal Descriptions
Table 2-1 describes the user interface and memory interface signals at the top level.
Table 2-1. LPDDR3 SDRAM Memory Controller Top-Level I/O List
Port Name
clk_in
Active
State
I/O
N/A
Input
Reference clock to the PLL of the CSM block.
Description
Clock Synchronization Logic (CSM) Interface
sclk
N/A
Input
System clock used by controller’s core module. User may use
this clock for LPDDR3 controller interface logic.
eclk
N/A
Input
Edge clock used by controller’s PHY module. Usually twice the
Frequency of sclk.
clocking_good
High
Input
Signal from CSM module indicating stable clock condition.
update_done
High
Input
DLL update done input from CSM to the core. Upon receiving
an update_done assertion, the core de-asserts dll_update in
the next clock cycle.
High
Output
DLL update request output from the core to the CSM block.
Once asserted, dll_update needs to stay asserted until an
update_done assertion is sampled. The CA bus stays in NOP
during the DLL update.
Low
Input
Asynchronous reset to the entire IP core.
dll_update
Local User Interface
rst_n
init_start
High
Input
Initialization start request. Should be asserted to initiate memory initialization either right after the power-on reset or before
sending the first user command to the memory controller.
Refer to “Initialization Control” on page 11 for more details.
cmd[3:0]
N/A
Input
User command input to the memory controller. Refer to “User
Commands” on page 14 for available commands.
cmd_valid
High
Input
Command and address valid input. When asserted, the addr,
cmd and cmd_burst_cnt inputs are considered valid. Refer to
“Command and Address” on page 12 for more details.
addr[ADDR_WIDTH-1:0]
N/A
Input
User read or write address input to the memory controller.
Refer the section “Local-to-Memory Address Mapping” for further details.
cmd_burst_cnt[4:0]
N/A
Input
Command burst count input – Indicates the number of times a
given read or write command is to be repeated by the controller
automatically. Controller also generates the address for each
repeated command sequentially as per the burst length of the
command. Burst range is from 1 to 32 and “0” indicates 32 repetitions
write_data[DSIZE-1:0]
N/A
Input
Write data input from user logic to the memory controller. The
user side write data width is four times the memory databus.
data_mask[(DSIZE/8)[1:0]
High
Input
Data mask input for write data. Each bit masks a corresponding byte of local write data.
ext_auto_ref
High
Input
Refresh request from user – This signal is available only when
the External Auto Refresh Port is selected in the GUI.
aref_brst_enb
High
Input
Enable or disable Auto refresh Burst mode.
1 = Burst mode
0 = Distributed mode
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LPDDR3 SDRAM Controller IP Core User’s Guide
Functional Description
Table 2-1. LPDDR3 SDRAM Memory Controller Top-Level I/O List (Continued)
Port Name
Active
State
I/O
Description
init_done
High
Output
Initialization done output – Asserted for one clock period after
the core completes memory initialization and write leveling.
When sampled high, the input signal init_start must be immediately deasserted at the same edge of the sampling clock. Refer
to “Initialization Control” on page 11 for more details.
cmd_rdy
High
Output
Command ready output – When asserted, indicates that the
core is ready to accept the next command and the corresponding address. This cmd_rdy signal is active for one clock period.
datain_rdy
High
Output
Data ready output – When asserted, indicates the core is
ready to receive the write data.
read_data[DSIZE-1:0]
N/A
Output
Read data output from memory controller to the user logic.
read_data_valid
High
Output
Read data valid output – When asserted, indicates the data on
the read_data bus is valid.
ext_auto_ref_ack
High
Output
Completion of memory refresh in response to ext_auto_ref signal assertion. This pin is available only when the External Auto
Refresh Port is selected in the GUI.
High
Output
Signal to indicate that write leveling is active. Both wl_act and
wl_err pins are available only when the Write Level option is
selected in the GUI.
High
Output
Write leveling error. Indicates failure in write leveling. The controller will not work properly if there is a write leveling error.
This signal should be checked when init_done signal is
asserted.
clock_stop
High
Input
Signal from the user to stop the LPDDR3 memory clock. The
memory clock stays Low while this signal is asserted High.
Only NOP is allowed on the LPDDR3 bus during clock stop.
rt_req
High
Input
rt_act
High
Output
Signal to indicate that the read pulse training is active.
rt_done
High
Output
Signal to indicate that the read pulse training has been completed.
rt_err
High
Output
Signal to indicate a failure during the read pulse training.
em_ddr_clk[CLKO_WIDTH-1:0]
N/A
Output
Up to 400 MHz differential pair memory clock generated by the
controller.
em_ ddr_cke[CKE_WIDTH-1:0]
High
Output
Memory clock enable generated by the controller.
em_ddr_ca[9:0]
N/A
Output
Memory Command and Address (CA) bus - multiplexed row
address, column address and command to the memory.
em_ ddr_data[DATA_WIDTH-1:0]
N/A
In/Out
Memory bi-directional data bus.
em_ ddr_dm[(DATA_WIDTH/8)-1:0]
High
Output
LPDDR3 memory write data mask – to mask the byte lanes for
byte-level write.
wl_act
wl_err
Read pulse training request from the user.
LPDDR3 SDRAM Memory Interface
em_ ddr_dqs[DQS_WIDTH-1:0]
N/A
In/Out
Memory bi-directional, differential pair data strobe.
em_ ddr_cs_n[CS_WIDTH-1:0]
Low
Output
Memory chip select.
em_ ddr_odt[CS_WIDTH-1:0]
High
Output
Memory on-die termination control.
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LPDDR3 SDRAM Controller IP Core User’s Guide
Functional Description
Using the Local User Interface
The local user interface of the LPDDR3 SDRAM Controller IP core consists of five independent functional groups:
• Initialization Control
• Command and Address
• Data Write
• Data Read
Each functional group and its associated local interface signals as listed in Table 2-2.
Table 2-2. Local User Interface Functional Groups
Functional Group
Signals
Initialization Control
init_start, init_done, rt_req, rt_act, rt_done, rt_err, wl_act, wl_err
Command and Address
addr, cmd, cmd_rdy, cmd_valid, cmd_burst_cnt
Data Write
datain_rdy, write_data, data_mask
Data Read
read_data, read_data_valid
Auto Refresh
aref_brst_enb, ext_auto_ref, ext_auto_ref_ack
Initialization Control
LPDDR3 memory devices must be initialized before the memory controller can access them. The memory controller starts the memory initialization sequence when the init_start signal is asserted by the user
interface. Once asserted, the init_start signal needs to be held high until the initialization process is completed. The output signal init_done is asserted High for one clock cycle indicating that the core has completed the initialization sequence and is now ready to access the memory. The init_start signal must be
deasserted as soon as init_done is sampled high at the rising edge of sclk. If the init_start is left high at the
next rising edge of sclk the memory controller takes it as another request for initialization and starts the
initialization process again. Memory initialization is required only once immediately after the system
reset. As part of Initialization the core performs write leveling for all the available ranks and stores the
write level delay values. The memory controller ensures a minimum gap of 200 µs between em_ddr_cke
assertion and reset command to the memory. Figure 2-2 shows the timing diagram of the initialization control
signals.
Figure 2-2. Timing of Memory Initialization Control
sclk
init_start
init_done
The read training is also performed during the initialization process to find the best read pulse position that detects
the incoming read DQS preamble timing. Since LPDDR3 memory does not use a DLL function, the clock to DQS
driving time can vary significantly with the process, voltage and temperature (PVT) variations. Due to this reason,
periodic retraining of the read pulse position may be necessary for guaranteeing stable read transactions over the
PVT variations during the normal operation. The LPDDR3 IP core provides the user with a function that can perform read retraining for PVT calibration during the normal operation using the following signals:
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LPDDR3 SDRAM Controller IP Core User’s Guide
Functional Description
• rt_req: read retraining request
• rt_act: read training active
• rt_done: read retraining done
The user needs to assert the rt_req signal during the normal operation but only when the LPDDR3 bus is in an idle
state. No activity other than NOP command is allowed when the core enters to the read retraining mode. Once
asserted, rt_req needs to keep holding its assertion state until the rt_done signal is sampled High. The rt_act signal indicates that the IP core is in the read training mode, and the LPDDR3 bus should remain idle with only NOP
commands until the retraining process is completed. The rt_done signal is asserted only for one clock cycle, and
the rt_req signal must be deasserted immediately after the sampling of the rt_done assertion to avoid unnecessary
reentering the training. The rt_err signal is asserted if the read training is not successful. Since a failure during the
read training usually causes the IP core unable to transfer the read data from the LPDDR3 SDRAM device to the
FPGA fabric, rt_err should be the first signal that the user needs to check if the LPDDR3 interface does not work
properly.
Figure 2-3. Timing Diagram for Read Retraining
sclk
rt_req
rt_act
rt_done
Command and Address
Once the memory initialization is done, the core waits for user commands in order to setup and/or access the memory. The user logic needs to provide the command and address to the core along with the control signals. The commands and addresses are delivered to the core using the following procedure.
The memory controller core informs the user logic that it is ready to receive a command by asserting the cmd_rdy
signal for one cycle. If the core finds the cmd_valid signal asserted by the user logic while it’s cmd_rdy is asserted,
it takes the cmd input as a valid user command. Usually cmd_valid is deasserted at the rising edge of the clock that
samples cmd_rdy high. The core also accepts the addr input as a valid start address or mode register programming data depending on the command type. Along with addr input the core also accepts the signals cmd_burst_cnt
and ofly_burst_len. If cmd_valid is not asserted, the cmd and addr inputs become invalid and the core ignores
them. The cmd, addr, cmd_burst_cnt and cmd_valid inputs become “don’t care” while cmd_rdy is de-asserted. The
cmd_rdy signal is asserted again to accept the next command.
The core is designed to ensure maximum throughput at a burst length of eight by asserting cmd_rdy once every
two-clock cycles unless the command queue is full or there is an intervention on the memory interface such as
Auto-Refresh cycles.
When the core is in the command burst operation, it extensively occupies the data bus. During this time, the core
prevents cmd_rdy from being asserted until the command burst is completed. While the core is operating in the
command burst mode, it can keep maximum throughput by internally replicating the command. The memory controller repeats the given READ or WRITE command up to 32 times. The cmd_burst_cnt[4:0] input is used to set the
number of repeats of the given command. The core allows the command burst function to access the memory
addresses within the current page. When the core reaches the boundary of the current page while accessing the
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LPDDR3 SDRAM Controller IP Core User’s Guide
Functional Description
memory in the command burst mode, the next address that the core will access becomes the beginning of the
same page. It will cause overwriting the contents of the location or reading unexpected data. Therefore, the user
must track the accessible address range in the current page while the command burst operation is performed. If an
application requires a fixed command burst size, use of 2-, 4-, 8-, 16- or 32-burst is recommended to ensure that
the command burst accesses do not cross the page boundary. When cmd_burst_cnt is 0, the controller will do 32
commands (reads or writes). The cmd_burst_cnt input is sampled the same way as cmd signal. The timing of the
Command and Address group is shown in Figure 2-4. The timing for burst count in Figure 3 shows only the sampling time of the bus. When cmd_burst_cnt is sampled with a value greater than “00001”and the command queue
becomes full, the cmd_rdy signal will not be asserted and the memory address is automatically increased by the
core until the current command burst cycle is completed.
Figure 2-4. Timing of Command and Address
sclk
cmd
cmd_burst_count
addr
C0
Invalid
C1
C2
BC0
Invalid
BC1
BC2
A0
Invalid
A1
A2
cmd_rdy
cmd_valid
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LPDDR3 SDRAM Controller IP Core User’s Guide
Functional Description
User Commands
The user initiates a request to the memory controller by loading a specific command code in cmd input along with
other information like memory address. The command on the cmd bus must be a valid command. Lattice defines a
set of valid memory commands as shown in Table 2-3. All other values are reserved and considered invalid.
Table 2-3. Defined User Commands
Command
Mnemonic
cmd[3:0]
Read
READ
4'h1
Write
WRITE
4'h2
Read with Auto Precharge
READA
4'h3
Write with Auto Precharge
WRITEA
4'h4
Powerdown Entry
PD_ENT
4'h5
Mode Register Write
MRW
4'h6
Mode Register Read
MRR
4'h7
Self Refresh Entry
SEL_REF_ENT
4'h8
Self Refresh Exit
SEL_REF_EXIT
4'h9
Deep Powerdown Entry
DPD_ENT
4'ha
Powerdown/Deep Powerdown Exit
DPD_EXIT
4'hb
Note:
- The controller accepts only the cmd codes listed above as legal commands. Any other cmd code is discarded as invalid command.
- The controller discards Self Refresh Entry or Deep Power Down Entry command if the memory is already in Self Refresh mode or Power
Down mode respectively.
- The controller discards Self Refresh Exit or Deep Power Down Exit command if the memory is already not in Self Refresh mode or Power
Down mode respectively.
- The controller needs at least 2 sclk gap between DPD_ENT command and DPD_EXIT command.
WRITE
The user initiates a memory write operation by asserting cmd_valid along with the WRITE or WRITEA command
and the address. After the WRITE command is accepted, the memory controller core asserts the datain_rdy signal
when it is ready to receive the write data from the user logic to write into the memory. Since the duration from the
time a write command is accepted to the time the datain_rdy signal is asserted is not fixed, the user logic needs to
monitor the datain_rdy signal. Once datain_rdy is asserted, the core expects valid data on the write_data bus one
or two clock cycles after the datain_rdy signal is asserted. The write data delay is programmable by the user, by
setting desired value for “Data_rdy to Write data delay” in the GUI, providing flexible backend application support.
For example, setting the value to 2 ensures that the core takes the write data in proper time when the local user
interface of the core is connected to a synchronous FIFO module inside the user logic. Figure 2-5 shows two examples of the local user interface data write timing. Both cases are in BL8 mode. The upper diagram shows the case
of one clock cycle delay of write data, while the lower one displays a two clock-cycle delay case. The memory controller considers D0, DM0 through D5, DM5 valid write data.
The controller decodes the addr input to extract the current row and current bank addresses and checks if the current row in the memory device is already opened. If there is no opened row in current bank an ACTIVE command is
generated by the controller to the memory to open the current row first. Then the memory controller issues a
WRITE command to the memory. If there is already an opened row in the current bank and the current row address
is different from the opened row, a PRECHARGE command is generated by the controller to close opened row in
the bank. This is followed with an ACTIVE command to open the current row. Then the memory controller issues a
WRITE command to the memory. If current row is already opened, only a WRITE command (without any ACTIVE
or PRECHARGE commands) is sent to the memory.
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LPDDR3 SDRAM Controller IP Core User’s Guide
Functional Description
Figure 2-5. One-Clock vs. Two-Clock Write Data Delay
BL8, WrRqDDelay = 1
sclk
datain_rdy
write_data
D0
D1
D2
D3
D4
D5
data_mask
DM0
DM1
DM2
DM3
DM4
DM5
BL8, WrRqDDelay = 2
sclk
datain_rdy
write_data
D0
D1
D2
D3
D4
D5
data_mask
DM0
DM1
DM2
DM3
DM4
DM5
Note: WrRqDDelay is Data_rdy to Write data delay.
WRITEA
WRITEA is treated in the same way as WRITE command except for the difference that the core issues a Write with
Auto Precharge command to the memory instead of just a Write command. This causes the memory to automatically close the current row after completing the write operation.
READ
When the READ command is accepted, the memory controller core accesses the memory to read the addressed
data and brings the data back to the local user interface. Once the read data is available on the local user interface,
the memory controller core asserts the read_data_valid signal to tell the user logic that the valid read data is on the
read_data bus. The read data timing on the local user interface is shown in Figure 2-6.
Read operation follows the same row status checking scheme as mentioned in write operation. Depending on current row status the memory controller generates ACTIVE and PRECHARGE commands as required. Refer to the
description mentioned in Write operation for more details.
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Functional Description
Figure 2-6. User-Side Read Operation
sclk
cmd
addr
cmd_ valid
cmd_rdy
read_data_valid
read_data
(for BL8)
D0
D1
D1
D1
READA
READA is treated in the same way as READ command except for the difference that the core issues a Read with
Auto Precharge command to the memory instead of Read command. This makes the memory automatically close
the current row after completing the read operation.
REFRESH Support
Since LPDDR3 memories have at least an 8192-deep Auto Refresh command queue as per JEDEC specification,
Lattice’s LPDDR3 memory controller core can support up to 8192 Auto Refresh commands in one burst. The core
has an internal auto refresh generator that sends out a set of consecutive Auto Refresh commands to the memory
at once when it reaches the time period of the refresh intervals (tREFI) times the Auto refresh burst count selected
in GUI.
It is recommended that the optimum number of burst Refresh commands be used if the LPDDR3 interface throughput is a major concern of the system. If the refresh burst count is set to n, for example, the core will send a set of n
consecutive Auto Refresh commands to the memory at once when it reaches the time period of the n refresh intervals (tREFI x n). Sending out n number of refresh commands in a burst takes about n x 4 x tRFCab ns in All bank
refresh mode. During this time no other command is sent to the memory. When a refresh burst is used, the controller issues a Precharge command only for the first Refresh command and the subsequent Refresh commands of
the burst are issued without the associated Precharge commands. This is to improve the LPDDR3 throughput.
Alternatively, the user can enable the External Auto Refresh Port which will add an input signal ext_auto_ref and an
output signal ext_auto_ref_ack to the core. In this case the internal auto refresh generator is disabled and the core
sends out a burst of refresh commands, as directed by Auto refresh burst count, every time the ext_auto_ref is
asserted. Completion of refresh burst is indicated by the output signal ext_auto_ref_ack.
In an application where explicit memory refresh is not necessary, user can enable External Auto Refresh Port and
keep the ext_auto_ref signal deasserted.
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Functional Description
Local-to-Memory Address Mapping
Mapping local addresses to memory addresses is an important part of a system design when a memory controller
function is implemented. Users must know how the local address lines from the memory controller connect to those
address lines from the memory because proper local-to-memory address mapping is crucial to meet the system
requirements in applications such as a video frame buffer controller. Even for other applications, careful address
mapping is generally necessary to optimize the system performance. In the memory side, the address (A), bank
address (BA) and chip select (CS) inputs are used for addressing a memory device. Users can obtain this information from a given datasheet. Figure 2-7 shows the local-to-memory address mapping of the Lattice LPDDR3 memory controller cores.
Figure 2-7. Local-to-Memory Address Mapping for Memory Access
ADDR_WIDTH - 1
COL_WIDTH +
BSIZE - 1
Row Address
(ROW_WIDTH)
addr[ADDR_WIDTH-1:0]
COL_WIDTH - 1
CS + BA Address
(BSIZE)
0
Column Address
(COL_WIDTH)
ADDR_WIDTH is calculated by the sum of COL_WIDTH, ROW_WIDTH and BSIZE. BSIZE is determined by the
sum of the BANK_WIDTH and CS_WIDTH. For LPDDR3 devices, the bank address size is always 3. Since the
number of chip select is 1, the chip select address size becomes 0. An example of a typical address mapping is
shown in Table 2-4 and Figure 2-8.
Table 2-4. Address Mapping Example
User Selection
Name
User Value
Parameter Name
Parameter Value
Actual Line Size
Local Address
Map
Column Size
11
COL_WIDTH
11
11
addr[10:0]
Bank Size
8
BANK_WIDTH
3
3
addr[13:11]
Chip Select Width
1
CS_WIDTH
1
0
—
Row Size
14
Total Local Address Line Size
ROW_WIDTH
14
14
addr[27:14]
ADDR_WIDTH
29
29
addr[27:0]
Figure 2-8. Mapped Address for the Example
27
14
Row Address (14 )
10
BA Addr
(3)
13
0
Col Address (11 )
11
Mode Register Access
The LPDDR3 SDRAM memory devices are programmed using a set of up to 256 Mode Registers. Mode Register
address and the Opcode to the Mode Register (for MRW only) are sent to the memory device through the
em_ddr_ca bus along with the MRW/MRR command. The memory data bus cannot be used for the Mode Register
programming.
The Lattice LPDDR3 memory controller core uses the local address bus, addr, to program these registers. The
core accepts a user command, MRW, to initiate the programming of mode registers. When MRW is applied on the
cmd bus, the user logic must provide the information for the targeted mode register and the programming data on
the addr bus. When the target mode register is programmed, the memory controller core is also configured to support the new memory setting. Figure 2-9 shows how the local address lines are allocated for the programming of
memory registers.
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LPDDR3 SDRAM Controller IP Core User’s Guide
Functional Description
Figure 2-9. User-to-Memory Address Mapping for MR Programming
Addr[ADDR_WIDTH-1:16]
Unused
Addr[15:8]
Addr[7:0]
Op code for MRW
Unused for MRR
Mode Reg Addr for MRW
and MRR
The register address (8 bits) is provided through the lower side of the addr bus starting from the bit 0 for LSB. The
programming data requires 8 bits of the local address lines.
Table 2-5. Mode Register Selection Using Bank Address Bits
Mode Register
(addr[7:0])
MR0
8'h0
MR1
8'h1
—
—
MR255
8'ff
The initialization process uses the Mode register initial values selected through GUI. If these registers are not further programmed by the user logic, using MRW user command, they will remain in the configurations programmed
during the initialization process. Table 2-6 shows the list of available parameters and their initial default values from
GUI if they are not changed by the user.
Table 2-6. Initialization Default Values for Mode Register Setting
Type
MR1
MR2
MR3
MR11
Register
Value
Description
Local Address
GUI Setting
Burst Length
3'b011
BL=8
addr[10:8]
Yes
Write Recovery
3'b100
6
addr[15:13]
Yes
Read & Write Latency
4'b0100
Yes
RL=6, WR=3
addr[11:8]
nWR programming
1'b0
