Platform Manager
In-System Programmable Power and Digital
Board Management
February 2012
Data Sheet DS1036
Features
Block Diagram
Precision Voltage Monitoring Increases
Reliability
12 Analog
Voltage
Monitor
Inputs
• 12 independent analog monitor inputs
• Differential inputs for remote ground sense
• Two programmable threshold comparators per
analog input
• Hardware window comparison
• 10-bit ADC for I2C monitoring
Digital
Inputs
Power
JTAG I/O
High-Voltage FET Drivers Enable
Integration
• Power supply ramp up/down control
• Programmable current and voltage output
• Independently configurable for FET control or
digital output
Configuration
Memory
Power
II2C/SMBus
Power Supply Margin and Trim Functions
• Trim and margin up to eight power supplies
• Dynamic voltage control through I2C
• Independent Digital Closed-Loop Trim function
for each output
48-Macrocell
CPLD
Margin/Trim
MOSFET
Drivers
Open Drain
Outputs
4 Timers
FPGA
JTAG I/O
640-LUT
FPGA
Digital I/O
Description
The Lattice Platform Manager integrates board power
management (hot-swap, sequencing, monitoring, reset
generation, trimming and margining) and digital board
management functions (reset tree, non-volatile error
logging, glue logic, board digital signal monitoring and
control, system bus interface, etc.) into a single integrated solution.
Programmable Timers Increase Control
Flexibility
• Four independent timers
• 32 s to 2 second intervals for timing sequences
PLD Resources Integrate Power and Digital
Functions
•
•
•
•
10-Bit
ADC
48-macrocell CPLD
640 LUT4s FPGA
Up to 107 digital I/Os
Up to 6.1 Kbits distributed RAM
The Platform Manager device provides 12 independent
analog input channels to monitor up to 12 power supply
test points. Up to 12 of these input channels can be
monitored through differential inputs to support remote
ground sensing. Each of the analog input channels is
monitored through two independently programmable
comparators to support both high/low and in-bounds/
out-of-bounds (window-compare) monitor functions. Up
to six general purpose 5V tolerant digital inputs are also
provided for miscellaneous control functions.
Programmable sysIO™ Buffer Supports a
Range of Interfaces
• LVCMOS 3.3/2.5/1.8/1.5/1.2
• LVTTL
System-Level Support
• Single 3.3V supply operation
• Industrial temperature range: -40°C to +85°C
In-System Programmability Reduces Risk
There are 16 open-drain digital outputs that can be
used for controlling DC-DC converters, low-drop-out
regulators (LDOs) and opto-couplers, as well as for
supervisory and general purpose logic interface functions. Four of these outputs (HVOUT1-HVOUT4) may
be configured as high-voltage MOSFET drivers. In highvoltage mode these outputs can provide up to 12V for
driving the gates of n-channel MOSFETs so that they
can be used as high-side power switches controlling the
supplies with a programmable ramp rate for both ramp
up and ramp down.
• Integrated non-volatile configuration memory
• JTAG programming interface
Package Options
• 128-pin TQFP
• 208-ball ftBGA
• RoHS compliant and halogen-free
© 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other
brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without
notice.
www.latticesemi.com
1
DS1036_01.3
Platform Manager Data Sheet
The board power management function can be implemented using an internal 48-macrocell CPLD. The status of all
of the comparators on the analog input channels as well as the general purpose digital inputs are used as inputs by
the CPLD array, and all digital outputs (open-drain as well as HVOUT) may be controlled by the CPLD.
Four independently programmable timers can create delays and time-outs ranging from 32 s to 2 seconds.
The Platform Manager device incorporates up to eight DACs for generating trimming voltage to control the output
voltage of a DC-DC converter. Additionally, each power supply output voltage can be maintained typically within
0.5% tolerance across various load conditions using the Digital Closed Loop Control mode.
The internal 10-bit A/D converter can both be used to monitor the VMON voltage through the I2C bus as well as for
implementing digital closed loop mode for maintaining the output voltage of all power supplies controlled by the
monitoring and trimming section of the Platform Manager device.
The FPGA section of the Platform Manager is optimized to meet the requirements of board management functions
including reset distribution, boundary scan management, fault logging, FPGA load control, and system bus interface. The FPGA section uses look-up tables (LUTs) and distributed memories for flexible and efficient logic implementation. This instant-on capability enables the Platform Manager devices to integrate control functions that are
required as soon as power is applied to the board.
Power management functions can be integrated into the CPLD and digital board management functions can be
integrated into the FPGA using the LogiBuilder tool provided by PAC-Designer® software. In addition, the FPGA
designs can also be implemented in VHDL or Verilog HDL through the ispLEVER® software design tool.
The Platform Manager IC supports a hardware I2C/SMBus slave interface that can be used to measure voltages
through the Analog to Digital Converter or is used for trimming and margining using a microcontroller.
There are two JTAG ports integrated into the Platform Manager device: Power JTAG and FPGA JTAG. The Power
JTAG interface is used to program the power section of the Platform Manager and the FPGA JTAG is used to configure the FPGA portion of the device. The FPGA configuration memory can be changed in-system without interrupting the operation of the board management section. However, the Power Management section of the platform
Manager cannot be changed without interrupting the power management operation.
Table 1. Platform Manager Family Selection Table
Parameter
LPTM10-1247
LPTM10-12107
Analog Inputs
12
12
Margin and Trim
6
8
Total I/O
47
107
CPLD Macrocells
48
48
FPGA LUTs
Package
640
640
128-pin TQFP
208-ball ftBGA
2
Platform Manager Data Sheet
Figure 1. Typical Platform Manager Application
3.3V
12V Backplane Vin
1.2V
1.0V
12V
Current
Monitor
Hot-Swap
FET Control
VID
SPI Memory
Margin & Trim
Supply Sequencing
4
Platform Manager
Voltage Monitoring
I2C Interface
Reset Distribution
CPU_ Reset
4
SPI
Port
Processor
Interface
Note: See reference design, IP documentation and application notes for more information on implementation of
individual functions called out above.
3
Platform Manager Data Sheet
Absolute Maximum Ratings1, 2, 3
Power Management Core Supply PVCCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 to 4.5V
Power Management Analog Supply PVCCA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 to 4.5V
Power Management Digital Input Supply PVCCA (IN[1:4]) PVCCINP . . . . . . . . . . . . . . . -0.5 to 6V
Power Management JTAG Logic Supply PVCCJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 6V
Power Management Alternate E2 programming supply APS4 . . . . . . . . . . . . . . . . . . . -0.5 to 4V
Power Management Digital Input Voltage (All Digital I/O Pins) VIN . . . . . . . . . . . . . . . -0.5 to 6V
VMON Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 6V
VMON Input Voltage Ground Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 6V
Voltage Applied to Power Management Tri-stated Pins (HVOUT[1:4]) . . . . . . . . . . . -0.5 to 13.3V
Voltage Applied to Power Management Tri-stated Pins (OUT[5:16]) . . . . . . . . . . . . . . -0.5 to 6V
Maximum Sink Current on Any Power Management Output . . . . . . . . . . . . . . . . . . . . . .23 mA
FPGA Supply Voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 3.75V
FPGA Supply Voltage VCCAUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 3.75V
FPGA Output Supply Voltage VCCIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 3.75V
FPGA I/O Tri-state Voltage Applied5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 3.75V
FPGA Dedicated Input Voltage Applied5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 4.25V
Device Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65 to +150°C
Junction Temperature TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C
1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
2. Compliance with the Lattice Thermal Management document is required.
3. All voltages referenced to GND (FPGA section) or GNDA/D (Power sections).
4. The APS pin MUST be left floating when PVCCD and PVCCA are powered.
5. Overshoot and undershoot of -2V to (VIHMAX + 2) volts is permitted for a duration of -100mV, Attenuator =1
TADC Error
Min.
Typ.
Max.
Units
-8
+/-4
8
mV
Total Measurement Error at
Measurement Range 600 mV - 2.048V,
Any Voltage (Differential AnaVMONxGS > -200mV, Attenuator =1
log Inputs)1
Measurement Range 0 - 2.048V,
VMONxGS > -200mV, Attenuator =1
Total Measurement Error at
Any Voltage (Single-Ended
Analog Inputs)2
Measurement Range 600 mV - 2.048V,
Attenuator =1
-8
+/-6
mV
+/-10
mV
+/-4
8
1. Total error, guaranteed by characterization, includes INL, DNL, Gain, Offset, and PSR specifications of the ADC.
2. Single-ended VMON inputs in 128-pin TQFP package only. Single-ended Vmon input pins include: 59 (VMON1), 83 (VMON9), 84
(VMON10), 86 (VMON11), 88 (VMON12).
11
mV
Platform Manager Data Sheet
Digital Specifications – Power Management Section Dedicated Inputs
Over Recommended Operating Conditions
Symbol
Parameter
Conditions
IIL,IIH
Input leakage, no pull-up/pull-down
IPU
Input pull-up current (PTMS, PTDI,
PTDISEL, PATDI, MCLK)
VIL
Voltage input, logic low1
Min.
Typ.
µA
µA
PTDI, PTMS, PATDI,
PTDISEL, 3.3V supply
0.8
PTDI, PTMS, PATDI,
PTDISEL, 2.5V supply
0.7
V
30% PVCCD
IN[1:4]
Voltage input, logic high1
Units
70
SCL, SDA
VIH
Max.
+/-10
30% PVCCINP
PTDI, PTMS, PATDI,
PTDISEL, 3.3V supply
2.0
PTDI,P TMS, PATDI,
PTDISEL, 2.5V supply
1.7
SCL, SDA
IN[1:4]
V
70% PVCCD
PVCCD
70% PVCCINP
PVCCINP
1. SCL, SDA referenced to PVCCD; IN[1:4] referenced to PVCCINP; PTDO, PTDI, PTMS, PATDI, PTDISEL referenced to PVCCJ.
Digital Specifications – Power Management Section Dedicated Outputs
Over Recommended Operating Conditions
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
35
100
µA
V
IOH-HVOUT
Output leakage current
HVOUT[1:4] in open
drain mode and pulled
up to 12V
VOL
HVOUT[1:4] (open drain mode),
ISINK = 10mA
0.8
OUT[5:16]
ISINK = 20mA
0.8
PTDO, MCLK, CPLDCLK, SDA
ISINK = 4mA
0.4
VOH
PTDO, MCLK, CPLDCLK
ISRC = 4mA
PVCCD - 0.4
V
ISINKTOTAL
All digital outputs
130
mA
12
Platform Manager Data Sheet
sysIO Recommended Operating Conditions
VCCIO (V)
Standard
Min.
Typ.
Max.
LVCMOS 3.3
3.135
3.3
3.465
LVCMOS 2.5
2.375
2.5
2.625
LVCMOS 1.8
1.71
1.8
1.89
LVCMOS 1.5
1.425
1.5
1.575
LVCMOS 1.2
1.14
1.2
1.26
LVTTL
3.135
3.3
3.465
sysIO Single-Ended DC Electrical Characteristics
Input/Output
Standard
VIL
VIH
Min. (V)
Max. (V)
Min. (V)
Max. (V)
LVCMOS 3.3
-0.3
0.8
2.0
3.6
LVTTL
-0.3
0.8
2.0
3.6
LVCMOS 2.5
LVCMOS 1.82
LVCMOS 1.52
LVCMOS 1.22
-0.3
-0.3
-0.3
-0.3
0.7
0.35VCCIO
0.35VCCIO
0.42
1.7
0.65VCCIO
0.65VCCIO
0.78
3.6
3.6
3.6
3.6
VOL Max.
(V)
VOH Min.
(V)
IOL1
(mA)
IOH1
(mA)
0.4
VCCIO - 0.4
16, 12, 8, 4
-14, -12, -8, -4
0.2
VCCIO - 0.2
0.1
-0.1
0.4
2.4
16
-16
0.4
VCCIO - 0.4
12, 8, 4
-12, -8, -4
0.2
VCCIO - 0.2
0.1
-0.1
0.4
VCCIO - 0.4
16, 12, 8, 4
-14, -12, -8, -4
0.2
VCCIO - 0.2
0.1
-0.1
0.4
VCCIO - 0.4
16, 12, 8, 4
-14, -12, -8, -4
0.2
VCCIO - 0.2
0.1
-0.1
0.4
VCCIO - 0.4
8, 4
-8, -4
0.2
VCCIO - 0.2
0.1
-0.1
0.4
VCCIO - 0.4
6, 2
-6, -2
0.2
VCCIO - 0.2
0.1
-0.1
1. The average DC current drawn by I/Os between GND connections, or between the last GND in an I/O bank and the end of an I/O bank, as
shown in the logic signal connections table shall not exceed n * 8mA. Where n is the number of I/Os between bank GND connections or
between the last GND in a bank and the end of a bank.
2. Lower voltage operation not supported for VCCIO2 bank pins.
13
Platform Manager Data Sheet
sysIO Differential Electrical Characteristics
LVDS Emulation
FPGA section outputs can support LVDS outputs via emulation (LVDS25E), in addition to the LVDS support that is
available. The output is emulated using complementary LVCMOS outputs in conjunction with resistors across the
driver outputs on all devices. The scheme shown in Figure 3 is one possible solution for LVDS standard implementation. Resistor values in Figure 3 are industry standard values for 1% resistors.
Figure 3. LVDS Using External Resistors (LVDS25E)
VCCIO = 2.5
158
8mA
Zo = 100
VCCIO = 2.5
158
+
100
140
-
8mA
Internal
External
External
Internal
Emulated
LVDS
Buffer
Note: All resistors are ±1%.
BLVDS Emulation
FPGA outputs support the BLVDS standard through emulation. The output is emulated using complementary LVCMOS outputs in conjunction with a parallel external resistor across the driver outputs. BLVDS is intended for use
when multi-drop and bi-directional multi-point differential signaling is required. The scheme shown in Figure 4 is
one possible solution for bi-directional multi-point differential signals.
Figure 4. BLVDS Multi-point Output Example
Heavily loaded backplane, effective Zo ~ 45 to 90 ohms differential
2.5V
2.5V
80
45-90 ohms
45-90 ohms
16mA
16mA
80
2.5V
2.5V
80
16mA
16mA
80
...
2.5V
+
+
-
2.5V
16mA
-
16mA
80
2.5V
16mA
80
+
-
2.5V
16mA
+
80
-
LVPECL Emulation
FPGA outputs support the differential LVPECL standard through emulation. This output standard is emulated using
complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs on all the devices.
The scheme shown in Figure 5 is one possible solution for point-to-point signals.
14
Platform Manager Data Sheet
Figure 5. Differential LVPECL
VCCIO = 3.3V
100 ohms
16mA
+
VCCIO = 3.3V
150 ohms
100 ohms
-
100 ohms
16mA
Transmission line, Zo = 100 ohm differential
Internal
External
External
Internal
For further information on LVPECL, BLVDS and other differential interfaces please see details of additional technical documentation at the end of the data sheet.
RSDS Emulation
FPGA outputs support the differential RSDS standard. The output standard is emulated using complementary
LVCMOS outputs in conjunction with a parallel resistor across the driver outputs on all the devices. The scheme
shown in Figure 6 is one possible solution for RSDS standard implementation. Use LVDS25E mode with suggested
resistors for RSDS operation. Resistor values in Figure 6 are industry standard values for 1% resistors.
Figure 6. RSDS (Reduced Swing Differential Standard)
VCCIO = 2.5V
294
8mA
Zo = 100
+
VCCIO = 2.5V
121
100
-
294
8mA
Internal
External
External
Internal
Emulated
RSDS Buffer
Oscillator Transient Characteristics
Over Recommended Operating Conditions
Symbol
Min.
Typ.
Max.
Units
fCLK
Power Management internal master clock frequency
(MCLK)
7.6
8
8.4
MHz
fCLKEXT
Power Management externally applied master clock
(MCLK)
7.2
8.8
MHz
fPLDCLK
fFPGACLK
Parameter
Conditions
CPLDCLK output frequency fCLK = 8MHz
FPGA internal master clock
frequency
250
18
15
kHz
26
MHz
Platform Manager Data Sheet
Power Management CPLD Timer Transient Characteristics
Over Recommended Operating Conditions
Symbol
Parameter
Conditions
Range of programmable
Timeout Range
timers (128 steps)
fCLK = 8MHz
Resolution
Spacing between available
adjacent timer intervals
Accuracy
Timer accuracy
Min.
Typ.
0.032
fCLK = 8MHz
-6.67
Max.
Units
1966
ms
13
%
-12.5
%
Power Management I2C Port Characteristics
100KHz
Symbol
Definition
Min.
2
400KHz
Max.
Min.
1
Max.
1
Units
FI2C
I C clock/data rate
TSU;STA
After start
4.7
0.6
us
THD;STA
After start
4
0.6
us
TSU;DAT
Data setup
250
100
ns
TSU;STO
Stop setup
4
0.6
THD;DAT
Data hold; SCL= Vih_min = 2.1V
0.3
TLOW
Clock low period
4.7
THIGH
Clock high period
4
TF
Fall time; 2.25V to 0.65V
TR
Rise time; 0.65V to 2.25V
TTIMEOUT
Detect clock low timeout
25
TPOR
Device must be operational after power-on reset
500
500
ms
TBUF
Bus free time between stop and start condition
4.7
1.3
us
100
3.45
400
0.3
us
0.9
1.3
35
us
300
1000
25
us
us
0.6
300
KHz
ns
300
ns
35
ms
1. If FI2C is less than 50kHz, then the ADC DONE status bit is not guaranteed to be set after a valid conversion request is completed. In this
case, waiting for the TCONVERT minimum time after a convert request is made is the only way to guarantee a valid conversion is ready for
readout. When FI2C is greater than 50kHz, ADC conversion complete is ensured by waiting for the DONE status bit.
16
Platform Manager Data Sheet
Timing for Power Management JTAG Operations
Min.
Typ.
Max.
Units
tISPEN
Symbol
Program enable delay time
Parameter
Conditions
10
—
—
µs
tISPDIS
Program disable delay time
30
—
—
µs
tHVDIS
High voltage discharge time, program
30
—
—
µs
tHVDIS
High voltage discharge time, erase
200
—
—
µs
tCEN
Falling edge of PTCK to PTDO active
—
—
15
ns
tCDIS
Falling edge of PTCK to PTDO disable
—
—
15
ns
tSU1
Setup time
5
—
—
ns
tH
Hold time
10
—
—
ns
tCKH
PTCK clock pulse width, high
20
—
—
ns
tCKL
PTCK clock pulse width, low
20
—
—
ns
fMAX
Maximum PTCK clock frequency
—
—
25
MHz
tCO
Falling edge of PTCK to valid output
—
—
15
ns
tPWV
Verify pulse width
30
—
—
µs
tPWP
Programming pulse width
20
—
—
ms
Figure 7. Erase (User Erase or Erase All) Timing Diagram
VIL
tSU1
tH
tCKH
VIH
tSU1
tSU1
tH
tH
tGKL
tCKH
PTCK
VIL
State
Update-IR
Run-Test/Idle (Erase)
Select-DR Scan
Clock to Shift-IR state and shift in the Discharge
Instruction, then clock to the Run-Test/Idle state
VIH
PTMS
tSU1
tH
tCKH
tSU1
tGKL
tSU1
tH
tCKH
tSU2
Specified by the Data Sheet
Run-Test/Idle (Discharge)
Figure 8. Programming Timing Diagram
VIL
tSU1
tH
tCKH
VIH
tSU1
tH
tCKL
tSU1
tH
tPWP
tCKH
PTCK
VIL
State
Update-IR
Run-Test/Idle (Program)
Select-DR Scan
17
Clock to Shift-IR state and shift in the next
Instruction, which will stop the discharge process
VIH
PTMS
tSU1
tH
tCKH
tH
tCKH
tSU1
tCKL
Update-IR
tH
tCKH
Platform Manager Data Sheet
VIH
PTMS
VIL
tSU1
tH
tCKH
tSU1
tH
tSU1
tCKL
tH
tPWV
tCKH
VIH
PTCK
VIL
State
Update-IR
Run-Test/Idle (Program)
Select-DR Scan
Clock to Shift-IR state and shift in the next Instruction
Figure 9. Verify Timing Diagram
tSU1
tH
tSU1
tCKH
tH
tCKL
tCKH
Update-IR
Figure 10. Discharge Timing Diagram
tHVDIS (Actual)
PTMS
VIL
tSU1
tH
tCKH
tSU1
tCKL
tH
tSU1
tPWP
tH
tCKH
VIH
PTCK
VIL
State
Update-IR
Run-Test/Idle (Erase or Program)
Select-DR Scan
18
Clock to Shift-IR state and shift in the Verify
Instruction, then clock to the Run-Test/Idle state
VIH
tSU1
tH
tCKH
tSU1
tCKL
tH
tSU1
tPWV
tCKH
Actual
tPWV
Specified by the Data Sheet
Run-Test/Idle (Verify)
tH
tCKH
Platform Manager Data Sheet
Typical FPGA Building Block Function Performance1
Pin-to-Pin Performance (LVCMOS25 12mA Drive)
Function
Timing
Units
Basic Functions
16-bit decoder
6.7
ns
4:1 MUX
4.5
ns
16:1 MUX
5.1
ns
Timing
Units
16:1 MUX
487
MHz
16-bit adder
292
MHz
16-bit counter
388
MHz
64-bit counter
200
MHz
16x2 Single Port RAM
434
MHz
64x2 Single Port RAM
320
MHz
Register-to-Register Performance
Function
Basic Functions
Distributed Memory Functions
128x4 Single Port RAM
261
MHz
32x2 Pseudo-Dual Port RAM
314
MHz
64x4 Pseudo-Dual Port RAM
271
MHz
1. The above timing numbers are generated using the Platform Manager design tool. Exact performance may vary with
device and tool version. The tool uses internal parameters that have been characterized but are not tested on every
device.
Rev. A 0.19
Derating Logic Timing
Logic Timing provided in the following sections of the data sheet and the Platform Manager design tool are worst
case numbers in the operating range. Actual delays may be much faster. The Platform Manager design tool from
Lattice can provide FPGA logic timing numbers at a particular temperature and voltage.
19
Platform Manager Data Sheet
FPGA Section External Switching Characteristics1
Over Recommended Operating Conditions
Parameter
Description
Min.
Max.
Units
—
4.9
ns
General I/O Pin Parameters (Using Global Clock without PLL)1
tPD
Best Case tPD Through 1 LUT
tCO
Best Case Clock to Output - From PFU
—
5.7
ns
tSU
Clock to Data Setup - To PFU
1.5
—
ns
tH
Clock to Data Hold - To PFU
-0.1
—
ns
fMAX_IO
Clock Frequency of I/O and PFU Register
—
500
MHz
tSKEW_PRI
Global Clock Skew Across Device
—
240
ps
1. General timing numbers based on LVCMOS2.5V, 12 mA.
Rev. A 0.19
FPGA Sleep Mode Timing
Min.
Max.
Units
tPWRDN
Parameter
SLEEPN Low to Power Down
Description
—
400
ns
tPWRUP
SLEEPN High to Power Up
—
600
µs
tWSLEEPN
SLEEPN Pulse Width
400
—
ns
tWAWAKE
SLEEPN Pulse Rejection
—
100
ns
20
Platform Manager Data Sheet
FPGA Section Internal Timing Parameters1
Over Recommended Operating Conditions
Parameter
Description
Min.
Max.
Units
—
0.39
ns
PFU/PFF Logic Mode Timing
tLUT4_PFU
LUT4 delay (A to D inputs to F output)
tLUT6_PFU
LUT6 delay (A to D inputs to OFX output)
—
0.62
ns
tLSR_PFU
Set/Reset to output of PFU
—
1.26
ns
tSUM_PFU
Clock to Mux (M0,M1) input setup time
0.15
—
ns
tHM_PFU
Clock to Mux (M0,M1) input hold time
-0.07
—
ns
tSUD_PFU
Clock to D input setup time
0.18
—
ns
tHD_PFU
Clock to D input hold time
-0.04
—
ns
tCK2Q_PFU
Clock to Q delay, D-type register configuration
—
0.56
ns
tLE2Q_PFU
Clock to Q delay latch configuration
—
0.74
ns
tLD2Q_PFU
D to Q throughput delay when latch is enabled
—
0.77
ns
—
0.56
ns
-0.25
—
ns
PFU Dual Port Memory Mode Timing
tCORAM_PFU
Clock to Output
tSUDATA_PFU
Data Setup Time
tHDATA_PFU
Data Hold Time
tSUADDR_PFU Address Setup Time
tHADDR_PFU
Address Hold Time
0.39
—
ns
-0.65
—
ns
0.99
—
ns
tSUWREN_PFU Write/Read Enable Setup Time
-0.30
—
ns
tHWREN_PFU
0.47
—
ns
Write/Read Enable Hold Time
PIO Input/Output Buffer Timing
tIN_PIO
Input Buffer Delay
—
1.06
ns
tOUT_PIO
Output Buffer Delay
—
1.80
ns
1. Internal parameters are characterized but not tested on every device.
Rev. A 0.19
21
Platform Manager Data Sheet
FPGA Section Timing Adders1, 2, 3
Over Recommended Operating Conditions
Buffer Type
Description
Units
Input Adjusters
LVTTL33
LVTTL
0.01
ns
LVCMOS33
LVCMOS 3.3
0.01
ns
LVCMOS25
LVCMOS 2.5
0.00
ns
LVCMOS18
LVCMOS 1.8
0.10
ns
LVCMOS15
LVCMOS 1.5
0.19
ns
LVCMOS12
LVCMOS 1.2
0.56
ns
LVTTL33_4mA
LVTTL 4mA drive
0.05
ns
LVTTL33_8mA
LVTTL 8mA drive
0.08
ns
LVTTL33_12mA
LVTTL 12mA drive
-0.01
ns
LVTTL33_16mA
LVTTL 16mA drive
0.70
ns
LVCMOS33_4mA
LVCMOS 3.3 4mA drive
0.05
ns
Output Adjusters
LVCMOS33_8mA
LVCMOS 3.3 8mA drive
0.08
ns
LVCMOS33_12mA
LVCMOS 3.3 12mA drive
-0.01
ns
LVCMOS33_14mA
LVCMOS 3.3 14mA drive
0.70
ns
LVCMOS25_4mA
LVCMOS 2.5 4mA drive
0.07
ns
LVCMOS25_8mA
LVCMOS 2.5 8mA drive
0.13
ns
LVCMOS25_12mA
LVCMOS 2.5 12mA drive
0.00
ns
LVCMOS25_14mA
LVCMOS 2.5 14mA drive
0.47
ns
LVCMOS18_4mA
LVCMOS 1.8 4mA drive
0.15
ns
LVCMOS18_8mA
LVCMOS 1.8 8mA drive
0.06
ns
LVCMOS18_12mA
LVCMOS 1.8 12mA drive
-0.08
ns
LVCMOS18_14mA
LVCMOS 1.8 14mA drive
0.09
ns
LVCMOS15_4mA
LVCMOS 1.5 4mA drive
0.22
ns
LVCMOS15_8mA
LVCMOS 1.5 8mA drive
0.07
ns
LVCMOS12_2mA
LVCMOS 1.2 2mA drive
0.36
ns
LVCMOS12_6mA
LVCMOS 1.2 6mA drive
0.07
ns
1. Timing adders are characterized but not tested on every device.
2. LVCMOS timing is measured with the load specified in Switching Test Conditions table.
3. All other standards tested according to the appropriate specifications.
Rev. A 0.19
22
Platform Manager Data Sheet
Flash Download Time
Symbol
tREFRESH
Parameter
VCC or VCCAUX to Device I/O Active
Min.
Typ.
Max.
Units
—
—
0.6
ms
FPGA JTAG Port Timing Specifications
Symbol
Parameter
Min.
Max.
Units
—
25
MHz
FTCK [BSCAN] clock pulse width
40
—
ns
FTCK [BSCAN] clock pulse width high
20
—
ns
tBTCPL
FTCK [BSCAN] clock pulse width low
20
—
ns
tBTS
FTCK [BSCAN] setup time
8
—
ns
tBTH
FTCK [BSCAN] hold time
10
—
ns
tBTRF
FTCK [BSCAN] rise/fall time
50
—
mV/ns
tBTCO
TAP controller falling edge of clock to output valid
—
10
ns
tBTCODIS
TAP controller falling edge of clock to output disabled
—
10
ns
tBTCOEN
TAP controller falling edge of clock to output enabled
—
10
ns
tBTCRS
BSCAN test capture register setup time
8
—
ns
tBTCRH
BSCAN test capture register hold time
25
—
ns
tBUTCO
BSCAN test update register, falling edge of clock to output valid
—
25
ns
tBTUODIS
BSCAN test update register, falling edge of clock to output disabled
—
25
ns
tBTUPOEN
BSCAN test update register, falling edge of clock to output enabled
—
25
ns
fMAX
FTCK [BSCAN] clock frequency
tBTCP
tBTCPH
Rev. A 0.19
23
Platform Manager Data Sheet
Figure 11. FPGA JTAG Port Timing Waveforms
FTMS
FTDI
tBTS
tBTCPH
tBTH
tBTCP
tBTCPL
FTCK
tBTCO
tBTCOEN
FTDO
Valid Data
tBTCRS
Data to be
captured
from I/O
tBTCODIS
Valid Data
tBTCRH
Data Captured
tBTUPOEN
tBUTCO
Data to be
driven out
to I/O
Valid Data
24
tBTUODIS
Valid Data
Platform Manager Data Sheet
FPGA Output Switching Test Conditions
Figure 12 shows the output test load that is used for AC testing. The specific values for resistance, capacitance,
voltage, and other test conditions are shown in Table 2.
Figure 12. Output Test Load, LVTTL and LVCMOS Standards
VT
R1
DUT
Test Poi nt
CL
Table 2. Test Fixture Required Components, Non-Terminated Interfaces
Test Condition
LVTTL and LVCMOS settings (L -> H, H -> L)
R1
CL
0pF
LVTTL and LVCMOS 3.3 (Z -> H)
Other LVCMOS (Z -> L)
VT
—
LVCMOS 2.5 = VCCIO/2
—
LVCMOS 1.8 = VCCIO/2
—
LVCMOS 1.5 = VCCIO/2
—
LVCMOS 1.2 = VCCIO/2
—
1.5
LVTTL and LVCMOS 3.3 (Z -> L)
Other LVCMOS (Z -> H)
Timing Ref.
LVTTL, LVCMOS 3.3 = 1.5V
188
0pF
VOL
VOH
VCCIO/2
VOL
VCCIO/2
VOH
LVTTL + LVCMOS (H -> Z)
VOH - 0.15
VOL
LVTTL + LVCMOS (L -> Z)
VOL - 0.15
VOH
Note: Output test conditions for all other interfaces are determined by the respective standards.
25
Platform Manager Data Sheet
Architecture Details
Analog Monitor Inputs
The Platform Manager provides 12 independently programmable voltage monitor input circuits as shown in
Figure 13. Two individually programmable trip-point comparators are connected to an analog monitoring input.
Each comparator reference has 368 programmable trip points over the range of 0.664V to 5.734V. Additionally, a
75mV ‘zero-detect’ threshold is selectable which allows the voltage monitors to determine if a monitored signal has
dropped to ground level. This feature is especially useful for determining if a power supply’s output has decayed to
a substantially inactive condition after it has been switched off.
Figure 13. Platform Manager Voltage Monitors
Platform Manager
To ADC
Differential
Input Buffer X*
Comp A/Window
Select
Comp A
VMONx
+
Trip Point A
MUX
VMONxGS*
–
Glitch
Filter
VMONxA
Logic
Signal
CPLD
Array
Comp B
+
Trip Point B
Glitch
Filter
–
Window Control
Analog Input
VMONxB
Logic
Signal
Filtering
VMONx Status
I2C Interface
Unit
*Differential Input Buffer X and VMONxGS pins are not present for single-ended VMONx inputs in the 128-pin TQFP package option.
Figure 13 shows the functional block diagram of one of the 12 voltage monitor inputs - ‘x’ (where x = 1...12). Each
voltage monitor can be divided into three sections: Analog Input, Window Control, and Filtering. The first section
provides a differential input buffer to monitor the power supply voltage through VMONx+ (to sense the positive terminal of the supply) and VMONxGS (to sense the power supply ground). Differential voltage sensing minimizes
inaccuracies in voltage measurement with ADC and monitor thresholds due to the potential difference between the
Platform Manager device ground and the ground potential at the sensed node on the circuit board.
The voltage output of the differential input buffer is monitored by two individually programmable trip-point comparators, shown as CompA and CompB. Table 3 shows all 368 trip points spanning the range 0.664V to 5.734V to
which a comparator’s threshold can be set. Note that for the 128-pin TQFP package option, the differential input
buffer shown above is not present for any of the single-ended VMON input pins. Those pins are: 59 (VMON1), 83
(VMON9), 84 (VMON10), 86 (VMON11), 88 (VMON12).
Each comparator outputs a HIGH signal to the CPLD if the voltage at its positive terminal is greater than its programmed trip point setting, otherwise it outputs a LOW signal.
Hysteresis is provided by the comparators to reduce false triggering as a result of input noise. The hysteresis provided by the voltage monitor is a function of the input divider setting. Table 5 lists the typical hysteresis versus voltage monitor trip-point.
26
Platform Manager Data Sheet
AGOOD Logic Signal
All the VMON comparators auto-calibrate immediately after a power-on reset event. During this time, the digital
glitch filters are also initialized. This process completion is signalled by an internally generated logic signal:
AGOOD. All logic using the VMON comparator logic signals must wait for the AGOOD signal to become active.
Programmable Over-Voltage and Under-Voltage Thresholds
Figure 14 (a) shows the power supply ramp-up and ramp-down voltage waveforms. Because of hysteresis, the
comparator outputs change state at different thresholds depending on the direction of excursion of the monitored
power supply.
Monitored Power Supply Votlage
Figure 14. (a) Power Supply Voltage Ramp-up and Ramp-down Waveform and the Resulting Comparator
Output, (b) Corresponding to Upper and Lower Trip Points
UTP
LTP
(a)
(b)
Comparator Logic Output
During power supply ramp-up the comparator output changes from logic 0 to 1 when the power supply voltage
crosses the upper trip point (UTP). During ramp down the comparator output changes from logic state 1 to 0 when
the power supply voltage crosses the lower trip point (LTP). To monitor for over voltage fault conditions, the UTP
should be used. To monitor under-voltage fault conditions, the LTP should be used.
Tables 3 and 4 show both the under-voltage and over-voltage trip points, which are automatically selected in software depending on whether the user is monitoring for an over-voltage condition or an under-voltage condition.
27
Platform Manager Data Sheet
Table 3. Trip Point Table Used For Over-Voltage Detection
Fine
Range
Setting
Coarse Range Setting
1
2
3
4
5
6
7
8
9
10
11
12
1
0.790
0.941
1.120
1.333
1.580
1.885
2.244
2.665
3.156
3.758
4.818
5.734
2
0.786
0.936
1.114
1.326
1.571
1.874
2.232
2.650
3.139
3.738
4.792
5.703
3
0.782
0.930
1.108
1.319
1.563
1.864
2.220
2.636
3.123
3.718
4.766
5.674
4
0.778
0.926
1.102
1.312
1.554
1.854
2.209
2.622
3.106
3.698
4.741
5.643
5
0.773
0.921
1.096
1.305
1.546
1.844
2.197
2.607
3.089
3.678
4.715
5.612
6
0.769
0.916
1.090
1.298
1.537
1.834
2.185
2.593
3.072
3.657
4.689
5.581
7
0.765
0.911
1.084
1.290
1.529
1.825
2.173
2.579
3.056
3.637
4.663
5.550
8
0.761
0.906
1.078
1.283
1.520
1.815
2.161
2.565
3.039
3.618
4.638
5.520
9
0.756
0.901
1.072
1.276
1.512
1.805
2.149
2.550
3.022
3.598
4.612
5.489
10
0.752
0.896
1.066
1.269
1.503
1.795
2.137
2.536
3.005
3.578
4.586
5.459
11
0.748
0.891
1.060
1.262
1.495
1.785
2.125
2.522
2.988
3.558
4.561
5.428
12
0.744
0.886
1.054
1.255
1.486
1.774
2.113
2.507
2.971
3.537
4.535
5.397
13
0.739
0.881
1.048
1.248
1.478
1.764
2.101
2.493
2.954
3.517
4.509
5.366
14
0.735
0.876
1.042
1.240
1.470
1.754
2.089
2.479
2.937
3.497
4.483
5.336
15
0.731
0.871
1.036
1.233
1.461
1.744
2.077
2.465
2.920
3.477
4.457
5.305
16
0.727
0.866
1.030
1.226
1.453
1.734
2.064
2.450
2.903
3.457
4.431
5.274
17
0.723
0.861
1.024
1.219
1.444
1.724
2.052
2.436
2.886
3.437
4.406
5.244
18
0.718
0.856
1.018
1.212
1.436
1.714
2.040
2.422
2.869
3.416
4.380
5.213
19
0.714
0.851
1.012
1.205
1.427
1.704
2.028
2.407
2.852
3.396
4.355
5.183
20
0.710
0.846
1.006
1.198
1.419
1.694
2.016
2.393
2.836
3.376
4.329
5.152
21
0.706
0.841
1.000
1.190
1.410
1.684
2.004
2.379
2.819
3.356
4.303
5.121
22
0.701
0.836
0.994
1.183
1.402
1.673
1.992
2.365
2.802
3.336
4.277
5.090
23
0.697
0.831
0.988
1.176
1.393
1.663
1.980
2.350
2.785
3.316
4.251
5.059
24
0.693
0.826
0.982
1.169
1.385
1.653
1.968
2.337
2.768
3.296
4.225
5.030
25
0.689
0.821
0.976
1.162
1.376
1.643
1.956
2.323
2.752
3.276
4.199
4.999
26
0.684
0.816
0.970
1.155
1.369
1.633
1.944
2.309
2.735
3.256
4.174
4.968
27
0.680
0.810
0.964
1.148
1.361
1.623
1.932
2.294
2.718
3.236
4.149
4.937
28
0.676
0.805
0.958
1.140
1.352
1.613
1.920
2.280
2.701
3.216
4.123
4.906
29
0.672
0.800
0.952
1.133
1.344
1.603
1.908
2.266
2.684
3.196
4.097
4.876
30
0.668
0.795
0.946
1.126
—
1.593
1.896
2.251
—
3.176
4.071
4.845
Low-V
Sense
75mV
28
Platform Manager Data Sheet
Table 4. Trip Point Table Used For Under-Voltage Detection
Fine
Range
Setting
Coarse Range Setting
1
2
3
4
5
6
7
8
9
10
11
12
1
0.786
0.936
1.114
1.326
1.571
1.874
2.232
2.650
3.139
3.738
4.792
5.703
2
0.782
0.930
1.108
1.319
1.563
1.864
2.220
2.636
3.123
3.718
4.766
5.674
3
0.778
0.926
1.102
1.312
1.554
1.854
2.209
2.622
3.106
3.698
4.741
5.643
4
0.773
0.921
1.096
1.305
1.546
1.844
2.197
2.607
3.089
3.678
4.715
5.612
5
0.769
0.916
1.090
1.298
1.537
1.834
2.185
2.593
3.072
3.657
4.689
5.581
6
0.765
0.911
1.084
1.290
1.529
1.825
2.173
2.579
3.056
3.637
4.663
5.550
7
0.761
0.906
1.078
1.283
1.520
1.815
2.161
2.565
3.039
3.618
4.638
5.520
8
0.756
0.901
1.072
1.276
1.512
1.805
2.149
2.550
3.022
3.598
4.612
5.489
9
0.752
0.896
1.066
1.269
1.503
1.795
2.137
2.536
3.005
3.578
4.586
5.459
10
0.748
0.891
1.060
1.262
1.495
1.785
2.125
2.522
2.988
3.558
4.561
5.428
11
0.744
0.886
1.054
1.255
1.486
1.774
2.113
2.507
2.971
3.537
4.535
5.397
12
0.739
0.881
1.048
1.248
1.478
1.764
2.101
2.493
2.954
3.517
4.509
5.366
13
0.735
0.876
1.042
1.240
1.470
1.754
2.089
2.479
2.937
3.497
4.483
5.336
14
0.731
0.871
1.036
1.233
1.461
1.744
2.077
2.465
2.920
3.477
4.457
5.305
15
0.727
0.866
1.030
1.226
1.453
1.734
2.064
2.450
2.903
3.457
4.431
5.274
16
0.723
0.861
1.024
1.219
1.444
1.724
2.052
2.436
2.886
3.437
4.406
5.244
17
0.718
0.856
1.018
1.212
1.436
1.714
2.040
2.422
2.869
3.416
4.380
5.213
18
0.714
0.851
1.012
1.205
1.427
1.704
2.028
2.407
2.852
3.396
4.355
5.183
19
0.710
0.846
1.006
1.198
1.419
1.694
2.016
2.393
2.836
3.376
4.329
5.152
20
0.706
0.841
1.000
1.190
1.410
1.684
2.004
2.379
2.819
3.356
4.303
5.121
21
0.701
0.836
0.994
1.183
1.402
1.673
1.992
2.365
2.802
3.336
4.277
5.090
22
0.697
0.831
0.988
1.176
1.393
1.663
1.980
2.350
2.785
3.316
4.251
5.059
23
0.693
0.826
0.982
1.169
1.385
1.653
1.968
2.337
2.768
3.296
4.225
5.030
24
0.689
0.821
0.976
1.162
1.376
1.643
1.956
2.323
2.752
3.276
4.199
4.999
25
0.684
0.816
0.970
1.155
1.369
1.633
1.944
2.309
2.735
3.256
4.174
4.968
26
0.680
0.810
0.964
1.148
1.361
1.623
1.932
2.294
2.718
3.236
4.149
4.937
27
0.676
0.805
0.958
1.140
1.352
1.613
1.920
2.280
2.701
3.216
4.123
4.906
28
0.672
0.800
0.952
1.133
1.344
1.603
1.908
2.266
2.684
3.196
4.097
4.876
29
0.668
0.795
0.946
1.126
1.335
1.593
1.896
2.251
2.667
3.176
4.071
4.845
30
0.664
0.790
0.940
1.119
—
1.583
1.884
2.236
—
3.156
4.045
4.815
Low-V
Sense
75mV
29
Platform Manager Data Sheet
Table 5. Comparator Hysteresis vs. Trip-Point
Trip-point Range (V)
Low Limit
High Limit
Hysteresis (mV)
0.664
0.79
8
0.79
0.941
10
0.94
1.12
12
1.119
1.333
14
1.326
1.58
17
1.583
1.885
20
1.884
2.244
24
2.236
2.665
28
2.65
3.156
34
3.156
3.758
40
4.045
4.818
51
4.815
5.734
75 mV
61
0 (Disabled)
The window control section of the voltage monitor circuit is an AND gate (with inputs: an inverted COMPA “ANDed”
with COMPB signal) and a multiplexer that supports the ability to develop a ‘window’ function without using any of
the CPLD resources. Through the use of the multiplexer, voltage monitor’s ‘A’ output may be set to report either the
status of the ‘A’ comparator, or the window function of both comparator outputs. The voltage monitor’s ‘A’ output
indicates whether the input signal is between or outside the two comparator thresholds. Important: This windowing
function is only valid in cases where the threshold of the ‘A’ comparator is set to a value higher than that of the ‘B’
comparator. Table 6 shows the operation of window function logic.
Table 6. Voltage Monitor Windowing Logic
Input Voltage
Comp A
Comp B
Window
(B and Not A)
Comment
VIN < Trip-point B < Trip-point A
0
0
0
Outside window, low
Trip-point B < VIN < Trip-point A
0
1
1
Inside window
Trip-point B < Trip-point A < VIN
1
1
0
Outside window, high
Note that when the ‘A’ output of the voltage monitor circuit is set to windowing mode, the ‘B’ output continues to
monitor the output of the ‘B’ comparator. This can be useful in that the ‘B’ output can be used to augment the windowing function by determining if the input is above or below the windowing range.
The third section in the Platform Manager’s input voltage monitor is a digital filter. When enabled, the comparator
output will be delayed by a filter time constant of 64 µs, and is especially useful for reducing the possibility of false
triggering from noise that may be present on the voltages being monitored. When the filter is disabled, the comparator output will be delayed by 16µs. In both cases, enabled or disabled, the filters also provide synchronization of
the input signals to the CPLD clock. This synchronous sampling feature effectively eliminates the possibility of race
conditions from occurring in any subsequent logic that is implemented in the Platform Manager’s internal CPLD
logic.
The comparator status can be read from the I2C interface. For details on the I2C interface, please refer to the I2C/
SMBUS Interface section of this data sheet.
30
Platform Manager Data Sheet
VMON Voltage Measurement with the Internal Analog to Digital Converter (ADC)
The Platform Manager has an internal analog to digital converter that can be used for measuring the voltages at
the VMON inputs. The ADC is also used in closed loop trimming of DC-DC converters. Close loop trimming is covered later in this document.
Figure 15. ADC Monitoring VMON1 to VMON12
VMON1*
VMON2
Programmable
Analog
Attenuator
VMON3
ADC
MUX
3
Programmable
Digital
Multiplier
ADC
1
3
1
10
VMON12*
Internal
VREF2.048V
PVCCA
To Closed
Loop Trim
Circuit
12
To I 2 C
Readout
Register
PVCCINP
4
1
5
Internal
Control Signal
5
From Closed
Loop Trim
Circuit
5
From I 2 C
ADC MUX
Register
*VMON1 and VMON9 to VMON12 are single-ended inputs for the 128-pin TQFP package option.
Figure 15 shows the ADC circuit arrangement within the Platform Manager device. The ADC can measure all analog input voltages through the multiplexer, ADC MUX. The programmable attenuator between the ADC mux and the
ADC can be configured as divided-by-3 or divided-by-1 (no attenuation). The divided-by-3 setting is used to measure voltages from 0V to 6V range and divided-by-1 setting is used to measure the voltages from 0V to 2V range.
Note that for the 128-pin TQFP package option, the VMON1 and VMON9 to VMON12 input pins are single-ended
inputs, not differential as shown above.
A microcontroller can place a request for any VMON voltage measurement at any time through the I2C bus. Upon
the receipt of an I2C command, the ADC will be connected to the I2C selected VMON through the ADC MUX. The
ADC output is then latched into the I2C readout registers.
Calculation
The algorithm to convert the ADC code to the corresponding voltage takes into consideration the attenuation bit
value. In other words, if the attenuation bit is set, then the 10-bit ADC result is automatically multiplied by 3 to calculate the actual voltage at that VMON input. Thus, the I2C readout register is 12 bits instead of 10 bits. The following formula can always be used to calculate the actual voltage from the ADC code.
31
Platform Manager Data Sheet
Voltage at the VMONx Pins
VMON = ADC code (12 bits1, converted to decimal) * 2mV
1
Note: ADC_VALUE_HIGH (8 bits), ADC_VALUE_LOW (4 bits) read from I2C/SMBUS interface
Controlling Power Supply Output Voltage by Margin/Trim Block
One of the key features of the Platform Manager is its ability to make adjustments to the power supplies that it may
also be monitoring and/or sequencing. This is accomplished through the Trim and Margin Block of the device. The
Trim and Margin Block can adjust voltages of up to eight different power supplies through TrimCells as shown in
Figure 16. The DC-DC blocks in the figure represent virtually any type of DC power supply that has a trim or voltage adjustment input. This can be an off-the-shelf unit or custom circuit designed around a switching regulator IC.
The interface between the Platform Manager and the DC power supply is represented by a single resistor (R1 to
R8) to simplify the diagram. Each of these resistors represents a resistor network.
Other control signals driving the Margin/Trim Block are:
• CPLD_VPS[1:0] – Voltage profile selection signals generated by the CPLD. These control signals are common to all eight TrimCells and are used to select the active voltage profile for all TrimCells together.
• ADC input – Used to determine the trimmed DC-DC converter voltage.
• CPLD_CLT_EN – Only from the CPLD, used to enable closed loop trimming of all TrimCells together.
Next to each DC-DC converter, four voltages are shown. These voltages correspond to the operating voltage profile
of the Margin/Trim Block.
When the CPLD_VPS[1:0] = 00, representing Voltage Profile 0: (Voltage Profile 0 is recommended to be used for
the normal circuit operation)
The output voltage of the DC-DC converter controlled by the Trim 1 pin of the Platform Manager will be 1V and that
TrimCell is operating in closed loop trim mode. At the same time, the DC-DC converters controlled by Trim 2, Trim 3
and Trim 8 pins output 1.2V, 1.5V and 3.3V respectively.
When the CPLD_VPS[1:0] = 01, representing Voltage Profile 1 being active:
The DC-DC output voltage controlled by Trim 1, 2, 3, and 8 pins will be 1.05V, 1.26V, 1.57V, and 3.46V. These supply voltages correspond to 5% above their respective normal operating voltage (also called as margin high).
Similarly, when CPLD_VPS[1:0] = 11, all DC-DC converters are margined low by 5%.
32
Platform Manager Data Sheet
Figure 16. Platform Manager Trim and Margin Block
Platform Manager
Margin/Trim Block
TrimCell
#1*
VIN
R1**
Trim 1
DC-DC Output Voltage
Controlled by Profiles
DC-DC
0
1
1V (CLT) 1.05V
2
0.97V
3
0.95V
1.2V (I2C) 1.26V
1.16V
1.14V
1.5V (I2C) 1.57V
1.45V
1.42V
3.3V (EE) 3.46V
3.20V
3.13V
Trim-in
(Closed Loop)
Default
Profile 0
Selected
Digital Closed Loop
and I2C Interface Control
VIN
TrimCell
#2*
R2**
Trim 2
DC-DC
Trim-in
(I2C Update)
VIN
TrimCell
#3
R3**
Trim 3
DC-DC
Trim-in
(I2C Update)
VIN
TrimCell
#8
R8**
Trim 8
DC-DC
Trim-in
(Register 0)
Input From ADC Mux
Read – 10-bit ADC Code
CPLD Control Signals
CPLD_CLT_EN,
CPLD_VPS[0:1]
*TrimCell #1 and TrimCell #2 (Trim 1 and Trim 2) are not available in the 128-pin TQFP package option.
**Indicates resistor network
There are up to eight TrimCells in the Platform Manager device, enabling simultaneous control of up to eight individual power supplies (six in the 128-pin TQFP package option). Each TrimCell can generate up to four trimming
voltages to control the output voltage of the DC-DC converter.
33
Platform Manager Data Sheet
Figure 17. TrimCell Driving a Typical DC-DC Converter
VOUT
VIN
VOUT
DC-DC
Converter
R3
TrimCell
#N
DAC
R1
Trim
R2
Figure 17 shows the resistor network between the TrimCell #N in the Platform Manager and the DC-DC converter.
The values of these resistors depend on the type of DC-DC converter used and its operating voltage range. The
method to calculate the values of the resistors R1, R2, and R3 are described in a separate application note.
Voltage Profile Control
The Platform Manager Margin/TrimBlock consists of up to eight TrimCells. Each of these trim cells integrates four
output voltage configurations. The operational voltage profile of the TrimCell is determined by two bits called voltage profile selection bits. The TrimBlock provides 2-bit voltage profile selection bits which are shared by all eight
TrimCells. The TrimBlock voltage profile can be set to profile zero or can be controlled by the CPLD through signals
CPLD_VPS[0:1]. An E2CMOS® configuration bit determines whether the voltage profile control is set to profile 0 or
it is controlled by CPLD.
34
Platform Manager Data Sheet
Figure 18. Voltage Profile Control
Common Voltage Profile Control Signals
Platform Manager
Margin/Trim Block
INT/EXT
SELECT
(E2CMOS)
2
Trim 1
TrimCell
#2*
Trim 2
TrimCell
#3
Trim 3
TrimCell
#4
Trim 4
TrimCell
#5
Trim 5
TrimCell
#6
Trim 6
TrimCell
#7
Trim 7
TrimCell
#8
Trim 8
2
Common Voltage Profile Control Signals
CPLD Control Signals 2
CPLD_VPS[0:1]
CTRL
MUX
Voltage Profile
Set to 00
TrimCell
#1*
*TrimCell #1 and TrimCell #2 (Trim 1 and Trim 2) are not available in the 128-pin TQFP package option.
TrimCell Architecture
The TrimCell block diagram is shown in Figure 19. The 8-bit DAC at the output provides the trimming voltage
required to set the output voltage of a programmable supply. Each TrimCell can be operated in any one of the four
voltage profiles. In each voltage profile the output trimming voltage can be set to a preset value. There are six 8-bit
registers in each TrimCell that, depending on the operational mode, set the DAC value. Of these, four DAC values
(DAC Register 0 to DAC Register 3) are stored in the E2CMOS memory while the remaining register contents are
stored in volatile registers. Two multiplexers (Mode Mux and Profile Mux) control the routing of the code to the DAC.
The Profile Mux can be controlled by common TrimCell voltage profile control signals.
35
Platform Manager Data Sheet
Figure 19. Platform Manager Output TrimCell
TrimCell Architecture
8
DAC Register 3
(E2CMOS)
Voltage
Profile 2
DAC Register 2
(E2CMOS)
8
DAC Register 1
(E2CMOS)
8
Voltage
Profile 1
DAC Register 0
(E2CMOS)
11
01
00
DAC
TRIMx
2
MODE
MUX
DAC Register
(I2C)
Closed Loop
Trim Register
8
8
8
8
Voltage
Profile 0
10
Profile MUX
Voltage
Profile 3
8
From Closed Loop
Trim Circuit
Voltage Profile 0
Mode Select
(E2CMOS)
Common TrimCell
Voltage Profile
Control
Figure 16 shows four power supply voltages next to each DC-DC converter. When the Profile MUX is set to Voltage
Profile 3, the DC supply controlled by Trim 1 will be at 0.95V, the DC supply controlled by Trim 2 will be at 1.14V,
1.43V for Trim 3 and 3.14V for Trim 8. When Voltage Profile 0 is selected, Trim 1 will set the supply to 1V, Trim 2 and
Trim 3 will be set by the values that have been loaded using I2C at 1.2 and 1.5V, and Trim 8 will be set to 3.3V.
Table 7 summarizes the voltage profile selection and the corresponding DAC output trimming voltage. The voltage
profile selection is common to all eight TrimCells.
Table 7. TrimCell Voltage Profile and Operating Modes
CPLD_VPS[1:0]
Selected Voltage Profile
Selected Mode
Trimming Voltage
is Controlled by
11
Voltage Profile 3
—
DAC Register 3 (E2CMOS)
10
Voltage Profile 2
—
DAC Register 2 (E2CMOS)
01
Voltage Profile 1
—
DAC Register 1 (E2CMOS)
DAC Register 0 Select
DAC Register 0 (E2CMOS)
00
Voltage Profile 0
DAC Register I2C Select
DAC Register (I2C)
Digital Closed Loop Trim
Closed Loop Trim Register
TrimCell Operation in Voltage Profiles 1, 2 and 3: The output trimming voltage is determined by the code stored
in the DAC Registers 1, 2, and 3 corresponding to the selected Voltage Profile.
TrimCell Operation in Voltage Profile 0: The Voltage Profile 0 has three operating modes. They are DAC Register 0 Select mode, DAC Register I2C Select mode and Closed Loop Trim mode. The mode selection is stored in the
E2CMOS configuration memory. Each of the eight TrimCells can be independently set to different operating modes
during Voltage Profile 0 mode of operation.
DAC Register 0 Select Mode: The contents of DAC register 0 are stored in the internal E2CMOS memory. When
Voltage Profile 0 is selected, the DAC will be loaded with the value stored in DAC Register 0.
DAC Register I2C Select Mode: This mode is used if the power management arrangement requires an external
microcontroller to control the DC-DC converter output voltage. The microcontroller updates the contents of the
36
Platform Manager Data Sheet
DAC Register I2C on the fly to set the trimming voltage to a desired value. The DAC Register I2C is a volatile register and is reset to 80H (DAC at Bipolar zero) upon power-on. The external microcontroller writes the correct DAC
code in this DAC Register I2C before enabling the programmable power supply.
Digital Closed Loop Trim Mode
Closed loop trim mode operation can be used when tight control over the DC-DC converter output voltage at a
desired value is required. The closed loop trim mechanism operates by comparing the measured output voltage of
the DC-DC converter with the internally stored voltage setpoint. The difference between the setpoint and the actual
DC-DC converter voltage generates an error voltage. This error voltage adjusts the DC-DC converter output voltage toward the setpoint. This operation iterates until the setpoint and the DC-DC converter voltage are equal.
Figure 20 shows the closed loop trim operation of a TrimCell. At regular intervals (as determined by the Update
Rate Control register) the Platform Manager device initiates the closed loop power supply voltage correction cycle
through the following blocks:
• Non-volatile Setpoint register stores the desired output voltage
• Internal ADC is used to measure the voltage of the DC-DC converter
• Tri-state comparator is used to compare the measured voltage from the ADC with the Setpoint register
contents. The output of the tri-state comparator can be one of the following:
• +1 if the setpoint voltage is greater than the DC-DC converter voltage
• -1 if the setpoint voltage is less than the DC-DC converter voltage
• 0 if the setpoint voltage is equal to the DC-DC converter voltage
• Channel polarity control determines the polarity of the error signal
• Closed loop trim register is used to compute and store the DAC code corresponding to the error voltage.
The contents of the Closed Loop Trim will be incremented or decremented depending on the channel polarity and the tri-state comparator output. If the tri-state comparator output is 0, the closed loop trim register
contents are left unchanged.
• The DAC in the TrimCell is used to generate the analog error voltage that adjusts the attached DC-DC converter output voltage.
Figure 20. Digital Closed Loop Trim Operation
Setpoint
(E2CMOS)
Channel
Polarity
(E2CMOS)
TrimCell
E2CMOS Registers
DAC Register 3
DAC Register 2
DAC Register 1
DAC
TRIMx
DAC Register 0
Tri-State
Digital
Compare
(+1/0/-1)
+/-1
Closed Loop
Trim Register
Update
Rate
Control
Profile Control
(CPLD)
DAC Register I2C
TRIMIN
Profile 0 Mode
Control (E2CMOS)
DC-DC
Converter
VMONx
VOUT
ADC
GND
Platform Manager
CPLD_CLT_EN
The closed loop trim cycle interval is programmable and is set by the update rate control register. The following
table lists the programmable update interval that can be selected by the update rate register.
37
Platform Manager Data Sheet
Table 8. Output DAC Update Rate in Digital Closed Loop Mode
Update Rate
Control Value
Update
Interval
00
580 µs
01
1.15 ms
10
9.22 ms
11
18.5 ms
There is a one-to-one relationship between the selected TrimCell and the corresponding VMON input for the closed
loop operation. For example, if TrimCell 3 is used to control the power supply in the closed loop trim mode, VMON3
must be used to monitor its output power supply voltage.
The closed loop operation can only be started by activating the internally generated CPLD signal, called
CPLD_CLT_EN, in PAC-Designer software. The selection of Voltage Profile 0, however, can be either through the
fixed default value or through the CPLD signals CPLD_VPS0 and CPLD_VPS1.
Closed Loop Start-up Behavior
The contents of the closed loop register, upon power-up, will contain a value 80h (Bipolar-zero) value. The DAC
output voltage will be equal to the programmed Offset voltage. Usually under this condition, the power supply output will be close to its nominal voltage. If the power supply trimming should start after reaching its desired output
voltage, the corresponding DAC code can be loaded into the closed loop trim register through I2C (same address
as the DAC register I2C mode) before activating the CPLD_CLT_EN signal.
Details of the Digital to Analog Converter (DAC)
Each trim cell has an 8-bit bipolar DAC to set the trimming voltage (Figure 21). The full-scale output voltage of the
DAC is +/- 320 mV. A code of 80H results in the DAC output set at its bi-polar zero value.
The voltage output from the DAC is added to a programmable offset value and the resultant voltage is then applied
to the trim output pin. The offset voltage is typically selected to be approximately equal to the DC-DC converter
open circuit trim node voltage. This results in maximizing the DC-DC converter output voltage range.
The programmed offset value can be set to 0.6V, 0.8V, 1.0V or 1.25V. This value selection is stored in E2CMOS
memory and cannot be changed dynamically.
Figure 21. Offset Voltage is Added to DAC Output Voltage to Derive Trim Pad Voltage
TRIMCELL X
8
From
Trim Registers
DAC
7 bits + Sign
(-320mV to +320mV)
TRIMx
Pad
Offset
(0.6V,0.8V,1.0V,1.25V)
E2CMOS
38
Platform Manager Data Sheet
CPLD Block
Figure 22 shows the Platform Manager power management CPLD architecture, which is derived from the Lattice
ispMACH® 4000 CPLD. The power management CPLD architecture allows the flexibility in designing various state
machines and control functions used for power supply management. The AND array has 83 inputs and generates
243 product terms. These 243 product terms are divided into three groups of 81 for each of the generic logic
blocks, GLB1, GLB2, and GLB3. Each GLB is made up of 16 macrocells. In total, there are 48 macrocells in the
Platform Manager device. The output signals of the Platform Manager device are derived from GLBs as shown in
Figure 22. Additionally, GLB3 generates the timer control.
Figure 22. Platform Manager CPLD Architecture
Global Reset
(Resetb pin)
AGOOD
MCLK
IN[1:4]
6
81
HVOUT[1..4],
OUT[5..8]
Input
Register
AND Array
83 Inputs
243 PT
VMON[1-12]
24
GLB1
Generic Logic Block
16 Macrocell
81 PT
Input
Register
GLB2
Generic Logic Block
16 Macrocell
81 PT
81
OUT[9..12] (ftBGA package)
OUT[9..14] (TQFP package)
4
Output
Feedback
GLB3
Generic Logic Block
16 Macrocell
81 PT
81
OUT[13..16] (ftBGA package)
OUT[15..16] (TQFP package)
48
Timer1
Timer2
Timer3
Timer4
IRP
Timer Clock
14
CPLD Clock
Macrocell Architecture
The macrocell shown in Figure 23 is the heart of the CPLD. The basic macrocell has five product terms that feed
the OR gate and the flip-flop. The flip-flop in each macrocell is independently configured. It can be programmed to
function as a D-Type or T-Type flip-flop. Combinatorial functions are realized by bypassing the flip-flop. The polarity
control and XOR gates provide additional flexibility for logic synthesis. The flip-flop’s clock is driven from the common CPLD clock that is generated by dividing the 8 MHz master clock (MCLK) by 32. The macrocell also supports
asynchronous reset and preset functions, derived from either product terms, the global reset input, or the power-on
reset signal. The resources within the macrocells share routing and contain a product term allocation array. The
product term allocation array greatly expands the CPLD’s ability to implement complex logical functions by allowing
logic to be shared between adjacent blocks and distributing the product terms to allow for wider decode functions.
All the digital inputs are registered by MCLK and the VMON comparator outputs are registered by the CPLD Clock
to synchronize them to the CPLD logic.
39
Platform Manager Data Sheet
Figure 23. Macrocell Block Diagram
Global Reset
Power On Reset
Global Polarity Fuse for
Init Product Term
Block Init Product Term
Product Term Allocation
PT4
PT3
PT2
PT1
R
P
PT0
D/T
To ORP
Q
Polarity
CLK
CPLD Clock
Macrocell flip-flop provides
D, T, or combinatorial
output with polarity
Clock and Timer Functions
Figure 24 shows a block diagram of the Platform Manager’s internal clock and timer systems. The master clock
operates at a fixed frequency of 8MHz, from which a fixed 250kHz CPLD clock is derived.
Figure 24. Clock and Timer System
CPLD Clock
Timer 0
Internal
Oscillator
8MHz
Timer 1
SW0
To/From
CPLD
32
Timer 2
SW1
Timer 3*
SW2
MCLK
CPLDCLK
*Used as part of FPGA timer functionality.
The internal oscillator runs at a fixed frequency of 8 MHz. This signal is used as a source for the CPLD and timer
clocks. It is also used for clocking the comparator outputs and clocking the digital filters in the voltage monitor cir40
Platform Manager Data Sheet
cuits, ADC and trim circuits. The Platform Manager can be programmed to operate in two modes: Master mode
and Slave mode. Table 9 summarizes the operating modes of Platform Manager.
Table 9. Platform Manager Operating Modes
Timer
Operating Mode
Master
Slave
SW0
SW1
Condition
Comments
Closed
Closed
When more than one Platform Manager is used in
a board, one of them should be configured to oper- MCLK pin outputs 8MHz clock
ate in this mode.
Open
Closed
When more than one Platform Managers is used in
a board. Other than the master, the rest of the Plat- MCLK pin is input
form Managers should be programmed as slaves.
A divide-by-32 prescaler divides the internal 8MHz oscillator (or external clock, if selected) down to 250kHz for the
CPLD clock and for the programmable timers. This CPLD clock may be made available on the CPLDCLK pin by
closing SW2. Each of the four timers provides independent timeout intervals ranging from 32 µs to 1.96 seconds in
128 steps.
CPLD Digital Outputs
The Platform Manager provides 20 digital outputs, HVOUT[1:4] and OUT[5:16]. Outputs OUT[5:16] are permanently configured as open drain to provide a high degree of flexibility when interfacing to logic signals, LEDs, optocouplers, and power supply control inputs. The HVOUT[1:4] pins can be configured as either high voltage FET drivers or open drain outputs. Each of these outputs may be controlled either from the CPLD or from the I2C bus. The
determination whether a given output is under CPLD or I2C control may be made on a pin-by-pin basis (see
Figure 25). For further details on controlling the outputs through I2C, please see the I2C/SMBUS Interface section of
this data sheet.
Figure 25. Digital Output Pin Configuration
Digital Control
from CPLD
OUTx
Pin
Digital Control
from I2C Register
High Voltage Outputs
In addition to being usable as digital open-drain outputs, the Platform Manager’s HVOUT1-HVOUT4 output pins
can be programmed to operate as high-voltage FET drivers. Figure 26 shows the details of the HVOUT gate drivers. Each of these outputs may be controlled from the CPLD or from the I2C bus (see Figure 26). For further details
on controlling the outputs through I2C, please see the I2C/SMBUS Interface section of this data sheet.
41
Platform Manager Data Sheet
Figure 26. Basic Function Diagram for an Output in High Voltage MOSFET Gate Driver Mode
Charge Pump
(6 to 12V)
Digital Control
from CPLD
ISOURCE
(12.5 to 100 µA)
+
-
HVOUTx
Pin
ISINK
(100 to 500 µA)
+Fast Turn-off
(3000µA)
Input
Supply
Load
Digital Control
from I2C Register
Figure 26 shows the HVOUT circuitry when programmed as a FET driver. In this mode the output either sources
current from a charge pump or sinks current. The maximum voltage that the output level at the pin will rise to is also
programmable between 6V and 12V. The maximum voltage levels that are required depend on the gate-to-source
threshold of the FET being driven and the power supply voltage being switched. The maximum voltage level needs
to be sufficient to bias the gate-to-source threshold on and also accommodate the load voltage at the FET’s
source, since the source pin of the FET to provide a wide range of ramp rates is tied to the supply of the target
board. When the HVOUT pin is sourcing current, charging a FET gate, the source current is programmable
between 12.5µA and 100µA. When the driver is turned to the off state, the driver will sink current to ground, and
this sink current is also programmable between 3000µA and 100µA to control the turn-off rate.
Programmable Output Voltage Levels for HVOUT1- HVOUT4
There are four selectable steps for the output voltage of the FET drivers when in FET driver mode. The voltage that
the pin is capable of driving to can be programmed from 6V to 12V in 2V steps.
Power I2C/SMBUS Interface
I2C and SMBus are low-speed serial interface protocols designed to enable communications among a number of
devices on a circuit board. The Platform Manager supports a 7-bit addressing of the I2C communications protocol,
as well as SMBTimeout and SMBAlert features of the SMBus, enabling it to easily integrated into many types of
modern power management systems. Figure 27 shows a typical I2C configuration, in which one or more Platform
Managers are slaved to a supervisory microcontroller. SDA is used to carry data signals, while SCL provides a synchronous clock signal. The SMBAlert line is only present in SMBus systems. The 7-bit I2C address is fully programmable through the power JTAG port.
42
Platform Manager Data Sheet
Figure 27. Platform Manager in I 2C/SMBUS System
V+
SDA/SMDAT (Data)
SCL/SMCLK (Clock)
To Other
I2C Devices
SMBALERT
SDA
SCL
SDA
INTERRUPT
SCL
OUT5/
SMBA
SDA
Platform Manager
(I2C Slave)
Microprocessor
(I2C Master)
SCL
OUT5/
SMBA
Platform Manager
(I2C Slave)
In both the I2C and SMBus protocols, the bus is controlled by a single master device at any given time. This master
device generates the SCL clock signal and coordinates all data transfers to and from a number of slave devices.
The Platform Manager is configured as a slave device, and cannot independently coordinate data transfers. Each
slave device on a given I2C bus is assigned a unique address. The Platform Manager implements the 7-bit
addressing portion of the standard. Any 7-bit address can be assigned to the Platform Manager device by programming through JTAG. When selecting a device address, one should note that several addresses are reserved by the
I2C and/or SMBus standards, and should not be assigned to Platform Manager devices to assure bus compatibility.
Table 10 lists these reserved addresses.
Table 10. I 2C/SMBus Reserved Slave Device Addresses
I2C function Description
Address
R/W bit
SMBus Function
0000 000
0
General Call Address
General Call Address
0000 000
1
Start Byte
Start Byte
0000 001
x
CBUS Address
CBUS Address
0000 010
x
Reserved
Reserved
0000 011
x
Reserved
Reserved
0000 1xx
x
HS-mode master code
HS-mode master code
0001 000
x
NA
SMBus Host
0001 100
x
NA
SMBus Alert Response Address
0101 000
x
NA
Reserved for ACCESS.bus
0110 111
x
NA
Reserved for ACCESS.bus
1100 001
x
NA
SMBus Device Default Address
1111 0xx
x
10-bit addressing
10-bit addressing
1111 1xx
x
Reserved
Reserved
The Platform Manager’s I2C/SMBus interface allows data to be both written to and read from the device. A data
write transaction (Figure 28) consists of the following operations:
1. Start the bus transaction
2. Transmit the device address (7 bits) along with a low write bit
3. Transmit the address of the register to be written to (8 bits)
4. Transmit the data to be written (8 bits)
5. Stop the bus transaction
43
Platform Manager Data Sheet
To start the transaction, the master device holds the SCL line high while pulling SDA low. Address and data bits are
then transferred on each successive SCL pulse, in three consecutive byte frames of nine SCL pulses. Address and
data are transferred on the first 8 SCL clocks in each frame, while an acknowledge signal is asserted by the slave
device on the 9th clock in each frame. Both data and addresses are transferred in a most-significant-bit-first format.
The first frame contains the 7-bit device address, with bit 8 held low to indicate a write operation. The second frame
contains the register address to which data will be written, and the final frame contains the actual data to be written. Note that the SDA signal is only allowed to change when the SCL is low, as raising SDA when SCL is high signals the end of the transaction.
Figure 28. I 2C Write Operation
SCL
SDA
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
A6
A5
A4
A3
A2
A1
A0
R/W
ACK
R7
R6
R5
R4
R3
R2
R1
R0
ACK
D7
D6
D5
D4
D3
D2
D1
D0
ACK
START
DEVICE ADDRESS (7 BITS)
REGISTER ADDRESS (8 BITS)
WRITE DATA (8 BITS)
STOP
Note: Shaded Bits Asserted by Slave
Reading a data byte from the Platform Manager requires two separate bus transactions (Figure 29). The first transaction writes the register address from which a data byte is to be read. Note that since no data is being written to
the device, the transaction is concluded after the second byte frame. The second transaction performs the actual
read. The first frame contains the 7-bit device address with the R/W bit held High. In the second frame the Platform
Manager asserts data out on the bus in response to the SCL signal. Note that the acknowledge signal in the second frame is asserted by the master device and not the Platform Manager.
Figure 29. I 2C Read Operation
STEP 1: WRITE REGISTER ADDRESS FOR READ OPERATION
SCL
SDA
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
A6
A5
A4
A3
A2
A1
A0
R/W
ACK
R7
R6
R5
R4
R3
R2
R1
R0
ACK
START
DEVICE ADDRESS (7 BITS)
REGISTER ADDRESS (8 BITS)
STOP
STEP 2: READ DATA FROM THAT REGISTER
SCL
SDA
START
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
A6
A5
A4
A3
A2
A1
A0
R/W
ACK
D7
D6
D5
D4
D3
D2
D1
D0
ACK
DEVICE ADDRESS (7 BITS)
READ DATA (8 BITS)
OPTIONAL
STOP
Note: Shaded Bits Asserted by Slave
The Platform Manager provides 26 registers that can be accessed through its I2C interface. These registers provide
the user with the ability to monitor and control the device’s inputs and outputs, and transfer data to and from the
device. Table 11 provides a summary of these registers.
44
Platform Manager Data Sheet
Table 11. I 2C Control Registers
Register Name
Read/Write
0x00
vmon_status0
R
VMON input status Vmon[4:1]
–––– ––––
0x01
vmon_status1
R
VMON input status Vmon[8:5]
–––– ––––
0x02
vmon_status2
R
VMON input status Vmon[12:9]
–––– ––––
0x03
output_status0
R
Output status OUT[8:5], HVOUT[4:1]
–––– ––––
0x04
0x05
output_status1
output_status2
R
R
Description
Value After POR1, 2
Register Address
Output status OUT[12:9]
208-ball ftBGA package
X 12 11 X 10 9 X X
Output status OUT[14:9]
128-pin TQFP package
14 X X 13 10 9 12 11
Output status OUT[16:13]
208-ball ftBGA package
X X X X 16 15 14 13
Output status OUT[16:15]
128-pin TQFP package
– – – – 16 15 X X
0x06
input_status
R
Input status IN[4:1]
XXXX ––––
0x07
adc_value_low
R
ADC D[3:0] and status
–––– XXX1
0x08
adc_value_high
R
ADC D[11:4]
–––– ––––
0x09
adc_mux
R/W
ADC Attenuator and MUX[3:0]
XXX1 1111
0x0A
UES_byte0
R
UES[7:0]
–––– ––––
0x0B
UES_byte1
R
UES[15:8]
–––– ––––
0x0C
UES_byte2
R
UES[23:16]
–––– ––––
0x0D
UES_byte3
R
UES[31:24]
–––– ––––
0x0E
gp_output1
R/W
GPOUT[8:1]
0001 0000
0x0F
0x10
gp_output2
gp_output3
R/W
R/W
0x11
input_value
R/W
0x12
reset
W
0x13
trim1_trim
R/W
GPOUT[12:9]
208-ball ftBGA package
X 12 11 X 10 9 X X
GPOUT[14:9]
128-pin TQFP package
14 X X 13 10 9 12 11
GPOUT[16:13]
208-ball ftBGA package
X X X X 16 15 14 13
GPOUT[16:15]
128-pin TQFP package
– – – – 16 15 X X
CPLD Input Register [6:2]
Resets device on write
Trim DAC 1 [7:0]
3
3
XX00 000X
N/A
1000 0000
0x14
trim2_trim
R/W
Trim DAC 2 [7:0]
0x15
trim3_trim
R/W
Trim DAC 3 [7:0]
1000 0000
1000 0000
0x16
trim4_trim
R/W
Trim DAC 4 [7:0]
1000 0000
0x17
trim5_trim
R/W
Trim DAC 5 [7:0]
1000 0000
0x18
trim6_trim
R/W
Trim DAC 6 [7:0]
1000 0000
0x19
trim7_trim
R/W
Trim DAC 7 [7:0]
1000 0000
0x1A
trim8_trim
R/W
Trim DAC 8 [7:0]
1000 0000
1. “X” = Undefined output states can be observed.
2. “–” = State depends on device configuration or input status. For words 0x04 and 0x05, specific outputs corresponding to bit positions are
called out. In all other cases, bits correspond to the order called out in the Description column.
3. Trim DAC 1 and Trim DAC 2 are not available in the 128-pin TQFP package option.
Several registers are provided for monitoring the status of the analog inputs. The three registers
VMON_STATUS[0:2] provide the ability to read the status of the VMON output comparators. The ability to read
both the ‘a’ and ‘b’ comparators from each VMON input is provided through the VMON input registers. Note that if
45
Platform Manager Data Sheet
a VMON input is configured to window comparison mode, then the corresponding VMONxA register bit will reflect
the status of the window comparison.
Figure 30. VMON Status Registers
0x00 - VMON_STATUS0 (Read Only)
VMON4B
VMON4A
VMON3B
VMON3A
VMON2B
VMON2A
VMON1B
VMON1A
b7
b6
b5
b4
b3
b2
b1
b0
0x01 - VMON_STATUS1 (Read Only)
VMON8B
VMON8A
VMON7B
VMON7A
VMON6B
VMON6A
VMON5B
VMON5A
b7
b6
b5
b4
b3
b2
b1
b0
0x02 - VMON_STATUS2 (Read Only)
VMON12B
VMON12A
VMON11B
VMON11A
VMON10B
VMON10A
VMON9B
VMON9A
b7
b6
b5
b4
b3
b2
b1
b0
It is also possible to directly read the value of the voltage present on any of the VMON inputs by using the Platform
Manager’s ADC. Three registers provide the I2C interface to the ADC (Figure 31).
Figure 31. ADC Interface Registers
0x07 - ADC_VALUE_LOW (Read Only)
D3
D2
D1
D0
1
1
1
DONE
b7
b6
b5
b4
b3
b2
b1
b0
0x08 - ADC_VALUE_HIGH (Read Only)
D11
D10
D9
D8
D7
D6
D5
D4
b7
b6
b5
b4
b3
b2
b1
b0
0x09 - ADC_MUX (Read/Write)
X
X
X
ATTEN
SEL3
SEL2
SEL1
SEL0
b7
b6
b5
b4
b3
b2
b1
b0
To perform an A/D conversion, one must set the input attenuator and channel selector. Two input ranges may be
set using the attenuator, 0 to 2.048V and 0 to 6.144V. Table 12 shows the input attenuator settings.
Table 12. ADC Input Attenuator Control
ATTEN (ADC_MUX.4)
Resolution
Full-Scale Range
0
2mV
2.048 V
1
6mV
6.144 V
The input selector may be set to monitor any one of the twelve VMON inputs, the PVCCA input, or the PVCCINP
input. Table 13 shows the codes associated with each input selection.
46
Platform Manager Data Sheet
Table 13. VMON Address Selection Table
Select Word
SEL3
(ADC_MUX.3)
SEL2
(ADC_MUX.2)
SEL1
(ADC_MUX.1)
SEL0
(ADC_MUX.0)
Input Channel
0
0
0
0
VMON1
0
0
0
1
VMON2
0
0
1
0
VMON3
0
0
1
1
VMON4
0
1
0
0
VMON5
0
1
0
1
VMON6
0
1
1
0
VMON7
0
1
1
1
VMON8
1
0
0
0
VMON9
1
0
0
1
VMON10
1
0
1
0
VMON11
1
0
1
1
VMON12
1
1
0
0
PVCCA
1
1
0
1
PVCCINP
Writing a value to the ADC_MUX register to set the input attenuator and selector will automatically initiate a conversion. When the conversion is in process, the DONE bit (ADC_VALUE_LOW.0) will be reset to 0. When the conversion is complete, this bit will be set to 1. When the conversion is complete, the result may be read out of the ADC by
performing two I2C read operations; one for ADC_VALUE_LOW, and one for ADC_VALUE_HIGH. It is recommended that the I2C master load a second conversion command only after the completion of the current conversion
command (Waiting for the DONE bit to be set to 1). An alternative would be to wait for a minimum specified time
(see TCONVERT value in the specifications) and disregard checking the DONE bit.
Note that if the I2C clock rate falls below 50kHz (see FI2C note in specifications), the only way to insure a valid ADC
conversion is to wait the minimum specified time (TCONVERT), as the operation of the DONE bit at clock rates lower
than that cannot be guaranteed. In other words, if the I2C clock rate is less than 50kHz, the DONE bit may or may
not assert even though a valid conversion result is available.
To insure every ADC conversion result is valid, preferred operation is to clock I2C at more than 50kHz and verify
DONE bit status or wait for the full TCONVERT time period between subsequent ADC convert commands. If an I2C
request is placed before the current conversion is complete, the DONE bit will be set to 1 only after the second
request is complete.
The status of the digital input lines may also be monitored and controlled through I2C commands. Figure 32 shows
the I2C interface to the IN[1:4] digital input lines. The input status may be monitored by reading the INPUT_STATUS
register, while input values to the CPLD array may be set by writing to the INPUT_VALUE register. To be able to set
an input value for the CPLD array, the input multiplexer associated with that bit needs to be set to the I2C register
setting in E2CMOS memory otherwise the CPLD will receive its input from the INx pin.
47
Platform Manager Data Sheet
Figure 32. I 2C Digital Input Interface
CPLD Output/Input_Value Register Select
(E2CMOS Configuration)
4
IN1
MUX
USERJTAG
Bit
3
CPLD
Array
3
IN[2..4]
MUX
3
3
Input_Value
Input_Status
I2C Interface Unit
0x06 - INPUT_STATUS (Read Only)
X
X
X
X
IN4
IN3
IN2
IN1
b7
b6
b5
b4
b3
b2
b1
b0
0x11 - INPUT_VALUE (Read/Write)
X
X
I6*
I5*
I4
I3
I2
X
b7
b6
b5
b4
b3
b2
b1
b0
*I5 and I6 are internal inputs to the CPLD that can only be configured by writing them
via the I2C interface (no external pin connection).
The CPLD digital outputs may also be monitored and controlled through the I2C interface, as shown in Figure 33.
The status of any given digital output may be read by reading the contents of the associated
OUTPUT_STATUS[2:0] register. Note that in the case of the outputs, the status reflected by these registers reflects
the logic signal used to drive the pin, and does not sample the actual level present on the output pin. For example,
if an output is set high but is not pulled up, the output status bit corresponding with that pin will read ‘1’, but a high
output signal will not appear on the pin. Digital inputs I5 and I6 are only accessible via the I2C interface. In other
words, there are no external pin connections to these two inputs.
Digital outputs may also be optionally controlled directly by the I2C bus instead of by the CPLD array. The outputs
may be driven either from the CPLD ORP or from the contents of the GP_OUTPUT[2:0] registers with the choice
user-settable in E2CMOS memory. Each output may be independently set to output from the CPLD or from the
GP_OUTPUT registers.
48
Platform Manager Data Sheet
Figure 33. I 2C Output Monitor and Control Logic
CPLD Output/GP_Output Register Select
(E2CMOS Configuration)
CPLD
Output
Routing
Pool
16
16
16
MUX
HVOUT[1..4]
OUT[5..16]
16
16
GP_Output1
Output_Status0
GP_Output2
Output_Status1
GP_Output3
Output_Status2
I2C Interface Unit
0x03 - OUTPUT_STATUS0 (Read Only)
OUT8
OUT7
OUT6
OUT5
HVOUT4
HVOUT3
HVOUT2
HVOUT1
b7
b6
b5
b4
b3
b2
b1
b0
0x04 - OUTPUT_STATUS1 (Read Only), 208-ball ftBGA package option
X
OUT12
OUT11
X
OUT10
OUT9
X
X
b7
b6
b5
b4
b3
b2
b1
b0
0x05 - OUTPUT_STATUS2 (Read Only), 208-ball ftBGA package option
X
X
X
X
OUT16
OUT15
OUT14
OUT13
b7
b6
b5
b4
b3
b2
b1
b0
0x04 - OUTPUT_STATUS1 (Read Only), 128-pin TQFP package option
OUT14
X
X
OUT13
OUT10
OUT9
OUT11
OUT12
b7
b6
b5
b4
b3
b2
b1
b0
0x05 - OUTPUT_STATUS2 (Read Only), 128-pin TQFP package option
X
X
X
X
OUT16
OUT15
X
X
b7
b6
b5
b4
b3
b2
b1
b0
GP4
GP3
GP2
GP1
b3
b2
b1
b0
0x0E - GP_OUTPUT1 (Read/Write)
GP8
GP7
GP6
b7
b6
b5
GP5_ENb
b4
0x0F - GP_OUTPUT2 (Read/Write), 208-ball ftBGA package option
X
GP12
GP11
X
GP10
GP9
X
X
b7
b6
b5
b4
b3
b2
b1
b0
0x10 - GP_OUTPUT3 (Read/Write), 208-ball ftBGA package option
X
X
X
X
GP16
GP15
GP14
GP13
b7
b6
b5
b4
b3
b2
b1
b0
0x0F - GP_OUTPUT2 (Read/Write), 128-pin TQFP package option
GP14
X
X
GP13
GP10
GP9
GP11
GP12
b7
b6
b5
b4
b3
b2
b1
b0
0x10 - GP_OUTPUT3 (Read/Write), 128-pin TQFP package option
X
X
X
X
GP16
GP15
X
X
b7
b6
b5
b4
b3
b2
b1
b0
49
Platform Manager Data Sheet
The UES word may also be read through the I2C interface, with the register mapping shown in Figure 34.
Figure 34. I 2C Register Mapping for UES Bits
0x0A - UES_BYTE0 (Read Only)
UES7
UES6
UES5
UES4
UES3
UES2
UES1
UES0
b7
b6
b5
b4
b3
b2
b1
b0
0x0B - UES_BYTE1 (Read Only)
UES15
UES14
UES13
UES12
UES11
UES10
UES9
UES8
b7
b6
b5
b4
b3
b2
b1
b0
0x0C - UES_BYTE2 (Read Only)
UES23
UES22
UES21
UES20
UES19
UES18
UES17
UES16
b7
b6
b5
b4
b3
b2
b1
b0
0x0D - UES_BYTE3 (Read Only)
UES31
UES30
UES29
UES28
UES27
UES26
UES25
UES24
b7
b6
b5
b4
b3
b2
b1
b0
The I2C interface also provides the ability to initiate reset operations. The Platform Manager may be reset by issuing a write of any value to the I2C RESET register (Figure 35). Note: The execution of the I2C reset command is
equivalent to toggling the Resetb pin of the device. Refer to the Resetb Signal, RESET Command via JTAG or I2C
section of this data sheet for further information.
Figure 35. I 2C Reset Register
0x12 - RESET (Write Only)
X
X
X
X
X
X
X
X
b7
b6
b5
b4
b3
b2
b1
b0
50
Platform Manager Data Sheet
The Platform Manager also provides the user with the ability to program the trim values over the I2C interface, by
writing the appropriate binary word to the associated trim register (Figure 36).
Figure 36. I 2C Trim Registers
0x13 - TRIM1_TRIM (Read/Write)*
D7
D6
D5
D4
D3
D2
D1
D0
b7
b6
b5
b4
b3
b2
b1
b0
0x14 - TRIM2_TRIM (Read/Write)*
D7
D6
D5
D4
D3
D2
D1
D0
b7
b6
b5
b4
b3
b2
b1
b0
0x15 - TRIM3_TRIM (Read/Write)
D7
D6
D5
D4
D3
D2
D1
D0
b7
b6
b5
b4
b3
b2
b1
b0
0x16 - TRIM4_TRIM (Read/Write)
D7
D6
D5
D4
D3
D2
D1
D0
b7
b6
b5
b4
b3
b2
b1
b0
0x17 - TRIM5_TRIM (Read/Write)
D7
D6
D5
D4
D3
D2
D1
D0
b7
b6
b5
b4
b3
b2
b1
b0
0x18 - TRIM6_TRIM (Read/Write)
D7
D6
D5
D4
D3
D2
D1
D0
b7
b6
b5
b4
b3
b2
b1
b0
0x19 - TRIM7_TRIM (Read/Write)
D7
D6
D5
D4
D3
D2
D1
D0
b7
b6
b5
b4
b3
b2
b1
b0
0x1A - TRIM8_TRIM (Read/Write)
D7
D6
D5
D4
D3
D2
D1
D0
b7
b6
b5
b4
b3
b2
b1
b0
*0x13 Trim 1 and 0x14 Trim 2 I2C registers are not available with 128-pin TQFP package option.
51
Platform Manager Data Sheet
SMBus SMBAlert Function
The Platform Manager provides an SMBus SMBAlert function so that it can request service from the bus master
when it is used as part of an SMBus system. This feature is supported as an alternate function of OUT5. When the
SMBAlert feature is enabled, OUT5 is controlled by a combination of the CPLD ORP and the GP5_ENb bit
(Figure 37). Note: To enable the SMBAlert feature, the SMB_Mode (E2CMOS bit) should be set in software.
Figure 37. Platform Manager SMBAlert Logic
CPLD Output/GP_Output Register Select
(E2CMOS Configuration)
OUT5/SMBA Mode Select
(E2CMOS Configuration)
CPLD
Output
Routing
Pool
MUX
OUT5/SMBA
MUX
GP5_ENb
SMBAlert
Logic
I2C Interface Unit
The typical flow for an SMBAlert transaction is as follows (Figure 38):
1. GP5_ENb bit is forced (Via I2C write) to Low
2. Platform Manager CPLD logic pulls OUT5/SMBA Low
3. Master responds to interrupt from SMBA line
4. Master broadcasts a read operation using the SMBus Alert Response Address (ARA)
5. Platform Manager responds to read request by transmitting its device address
6. If transmitted device address matches Platform Manager address, it sets GP5_ENb bit high.
This releases OUT5/SMBA.
Figure 38. SMBAlert Bus Transaction
SMBA
SCL
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
SDA
0
0
0
1
1
0
0
R/W
ACK
A6
A5
A4
A3
A2
A1
A0
x
ACK
SLAVE
ASSERTS
SMBA
START
SLAVE ADDRESS (7 BITS)
ALERT RESPONSE ADDRESS
(0001 100)
SLAVE
RELEASES
SMBA
STOP
Note: Shaded Bits Asserted by Slave
After OUT5/SMBA has been released, the bus master (typically a microcontroller) may opt to perform some service
functions in which it may send data to or read data from the Platform Manager. As part of the service functions, the
bus master will typically need to clear whatever condition initiated the SMBAlert request, and will also need to reset
GP5_ENb to re-enable the SMBAlert function. For further information on the SMBus, the user should consult the
SMBus Standard.
52
Platform Manager Data Sheet
Designs using the SMBAlert feature are required to set the device’s I2C/SMBus address to the lowest of all the
addresses on that I2C/SMBus.
RESETb Signal, RESET Command via JTAG or I2C
Activating the RESETb signal (Logic 0 applied to the RESETb pin) or issuing a reset instruction via JTAG or I2C will
force the outputs to the following states independent of how these outputs have been configured in the PINS window:
• OUT5-16 will go high-impedance.
• HVOUT pins programmed for open drain operation will go high-impedance.
• HVOUT pins programmed for FET driver mode operation will pull down.
At the conclusion of the RESET event, these outputs will go to the states defined by the PINS window, and if a
sequence has been programmed into the device, it will be re-started at the first step. The analog calibration will be
re-done and consequently, the VMONs, ADCs, and DACs will not be operational until 2.5 milliseconds (max.) after
the conclusion of the RESET event.
CAUTION: Activating the RESETb signal or issuing a RESET command through I2C or JTAG during the Platform
Manager device operation, results in the device aborting all operations and returning to the power-on reset state.
The status of the power supplies which are being enabled by the Platform Manager will be determined by the state
of the outputs shown above.
53
Platform Manager Data Sheet
FPGA Architecture Details
The Platform Manager FPGA architecture contains an array of logic blocks surrounded by Programmable I/O
(PIO). Figure 39 shows the block diagrams of the FPGA block.
The logic blocks are arranged in a two-dimensional grid with rows and columns. The PIO cells are located at the
periphery of the device, arranged into banks. The PIOs utilize a flexible I/O buffer referred to as a sysIO interface
that supports operation with a variety of interface standards. The blocks are connected with many vertical and horizontal routing channel resources. The place and route software tool automatically allocates these routing
resources.
There are two kinds of logic blocks, the Programmable Functional Unit (PFU) and the Programmable Functional
unit without RAM (PFF). The PFU contains the building blocks for logic, arithmetic, RAM, ROM, and register functions. The PFF block contains building blocks for logic, arithmetic, ROM, and register functions. Both the PFU and
PFF blocks are optimized for flexibility, allowing complex designs to be implemented quickly and effectively. Logic
blocks are arranged in a two-dimensional array. Only one type of block is used per row.
The FPGA JTAG port supports programming and configuration of the FPGA as well as access to the user logic.
Figure 39. Top View of the FPGA Section
PIOs Arranged into
sysIO Banks
Programmable
Function Units
without RAM (PFFs)
Programmable
Function Units
with RAM (PFUs)
FPGA JTAG Port
PFU Blocks
The core of the FPGA section consists of PFU and PFF blocks. The PFUs can be programmed to perform Logic,
Arithmetic, Distributed RAM, and Distributed ROM functions. PFF blocks can be programmed to perform Logic,
Arithmetic, and Distributed ROM functions. Except where necessary, the remainder of this data sheet will use the
term PFU to refer to both PFU and PFF blocks.
Each PFU block consists of four interconnected slices, numbered 0 to 3 as shown in Figure 40. There are 53 inputs
and 25 outputs associated with each PFU block.
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Platform Manager Data Sheet
Figure 40. PFU Diagram
From
Routing
FCIN
LUT4 &
CARRY
LUT4 &
CARRY
LUT4 &
CARRY
Slice 0
D
FF/
Latch
D
FF/
Latch
LUT4 &
CARRY
LUT4 &
CARRY
Slice 1
D
FF/
Latch
LUT4 &
CARRY
LUT4 &
CARRY
D
FF/
Latch
FCO
Slice 3
Slice 2
D
FF/
Latch
LUT4 &
CARRY
D
FF/
Latch
D
FF/
Latch
D
FF/
Latch
To
Routing
Slice
Each slice contains two LUT4 lookup tables feeding two registers (programmed to be in FF or Latch mode), and
some associated logic that allows the LUTs to be combined to perform functions such as LUT5, LUT6, LUT7, and
LUT8. There is control logic to perform set/reset functions (programmable as synchronous/asynchronous), clock
select, chip-select, and wider RAM/ROM functions. Figure 41 shows an overview of the internal logic of the slice.
The registers in the slice can be configured for positive/negative and edge/level clocks.
There are 14 input signals: 13 signals from routing and one from the carry-chain (from the adjacent slice/PFU).
There are 7 outputs: 6 to the routing and one to the carry-chain (to the adjacent slice/PFU). Table 14 lists the signals associated with each slice.
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Platform Manager Data Sheet
Figure 41. Slice Diagram
To Adjacent Slice/PFU
Slice
OFX1
A1
B1
C1
D1
CO
LUT4 &
CARRY
F1
F
D
SUM
FF/
Latch
Fast Connection
to I/O Cell*
Q1
CI
From
Routing
To
Routing
M1
M0
A0
OFX0
Fast Connection
to I/O Cell*
LUT
Expansion
Mux
CO
B0
C0
D0
LUT4 &
CARRY
F0
F
SUM
OFX0
CI
Control Signals
selected and
inverted per
Slice in routing
D
FF/
Latch
Q0
CE
CLK
LSR
From Adjacent Slice/PFU
Notes:
Some inter-Slice signals are not shown.
* Only PFUs at the edges have fast connections to the I/O cell.
Table 14. Slice Signal Descriptions
Function
Type
Signal Names
Description
Input
Data signal
A0, B0, C0, D0 Inputs to LUT4
Input
Data signal
A1, B1, C1, D1 Inputs to LUT4
Input
Multi-purpose
M0/M1
Input
Control signal
CE
Multipurpose Input
Clock Enable
Input
Control signal
LSR
Local Set/Reset
Input
Control signal
CLK
System Clock
Input
Inter-PFU signal
FCIN
Fast Carry In1
Output
Data signals
F0, F1
LUT4 output register bypass signals
Output
Data signals
Q0, Q1
Output
Data signals
OFX0
Output of a LUT5 MUX
Output
Data signals
OFX1
Output of a LUT6, LUT7, LUT82 MUX depending on the slice
Output
Inter-PFU signal
FCO
Fast Carry Out1
Register Outputs
1. See Figure 40 for connection details.
2. Requires two PFUs.
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Platform Manager Data Sheet
Modes of Operation
Each slice is capable of four modes of operation: Logic, Ripple, RAM, and ROM. The slice in the PFF is capable of
all modes except RAM. Table 15 lists the modes and the capability of the slice blocks.
Table 15. Slice Modes
Logic
Ripple
RAM
ROM
PFU Slice
LUT 4x2 or LUT 5x1
2-bit Arithmetic Unit
SP 16x2
ROM 16x1 x 2
PFF Slice
LUT 4x2 or LUT 5x1
2-bit Arithmetic Unit
N/A
ROM 16x1 x 2
Logic Mode: In this mode, the LUTs in each slice are configured as 4-input combinatorial lookup tables (LUT4). A
LUT4 can have 16 possible input combinations. Any logic function with four inputs can be generated by programming this lookup table. Since there are two LUT4s per slice, a LUT5 can be constructed within one slice. Larger
lookup tables such as LUT6, LUT7, and LUT8 can be constructed by concatenating other slices.
Ripple Mode: Ripple mode allows the efficient implementation of small arithmetic functions. In ripple mode, the following functions can be implemented by each slice:
•
•
•
•
•
•
•
Addition 2-bit
Subtraction 2-bit
Add/Subtract 2-bit using dynamic control
Up counter 2-bit
Down counter 2-bit
Ripple mode multiplier building block
Comparator functions of A and B inputs
- A greater-than-or-equal-to B
- A not-equal-to B
- A less-than-or-equal-to B
Two additional signals, Carry Generate and Carry Propagate, are generated per slice in this mode, allowing fast
arithmetic functions to be constructed by concatenating slices.
RAM Mode: In this mode, distributed RAM can be constructed using each LUT block as a 16x2-bit memory.
Through the combination of LUTs and slices, a variety of different memories can be constructed.
The Platform Manager design tool supports the creation of a variety of different size memories. Where appropriate,
the software will construct these using distributed memory primitives that represent the capabilities of the PFU.
Table 16 shows the number of slices required to implement different distributed RAM primitives. Figure 42 shows
the distributed memory primitive block diagrams. Dual port memories involve the pairing of two slices. One slice
functions as the read-write port, while the other companion slice supports the read-only port. For more information
on RAM mode in the FPGA section, please see details of additional technical documentation at the end of this data
sheet.
Table 16. Number of Slices Required For Implementing Distributed RAM
SPR16x2
DPR16x2
1
2
Number of Slices
Note: SPR = Single Port RAM, DPR = Dual Port RAM
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Platform Manager Data Sheet
Figure 42. Distributed Memory Primitives
SPR16x2
AD0
AD1
AD2
AD3
DPR16x2
DO0
DI0
DI1
WRE
CK
DO1
WAD0
WAD1
WAD2
WAD3
RAD0
RAD1
RAD2
RAD3
DI0
DI1
WCK
WRE
RDO0
RDO1
WDO0
WDO1
ROM16x1
AD0
AD1
AD2
AD3
DO0
ROM Mode: The ROM mode uses the same principal as the RAM modes, but without the Write port. Pre-loading is
accomplished through the programming interface during configuration.
PFU Modes of Operation
Slices can be combined within a PFU to form larger functions. Table 17 tabulates these modes and documents the
functionality possible at the PFU level.
Table 17. PFU Modes of Operation
Ripple
RAM
ROM
LUT 4x8 or
MUX 2x1 x 8
Logic
2-bit Add x 4
SPR16x2 x 4
DPR16x2 x 2
ROM16x1 x 8
LUT 5x4 or
MUX 4x1 x 4
2-bit Sub x 4
SPR16x4 x 2
DPR16x4 x 1
ROM16x2 x 4
LUT 6x 2 or
MUX 8x1 x 2
2-bit Counter x 4
SPR16x8 x 1
ROM16x4 x 2
LUT 7x1 or
MUX 16x1 x 1
2-bit Comp x 4
ROM16x8 x 1
Routing
There are many resources provided in the FPGA to route signals individually or as buses with related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) segments.
The inter-PFU connections are made with three different types of routing resources: x1 (spans two PFUs), x2
(spans three PFUs) and x6 (spans seven PFUs). The x1, x2, and x6 connections provide fast and efficient connections in the horizontal and vertical directions.
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Platform Manager Data Sheet
The Platform Manager design tool takes the output of the synthesis tool and places and routes the design. Generally, the place and route tool is completely automatic, although an interactive routing editor is available to optimize
the design.
Clock/Control Distribution Network
The FPGA section provides global signals that are available to all PFUs. These signals consist of four primary
clocks and four secondary clocks. Primary clock signals are generated from four 16:1 muxes as shown in
Figure 43. The available clock sources are four dual function clock pins and 12 internal routing signals.
Figure 43. FPGA Primary Clocks
12
4
16:1
16:1
16:1
16:1
Routing
Primary Clock 0
Primary Clock 1
Primary Clock 2
Primary Clock 3
Clock
Pads
Four secondary clocks are generated from four 16:1 muxes as shown in Figure 44. Four of the secondary clock
sources come from dual function clock pins and 12 come from internal routing.
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Platform Manager Data Sheet
Figure 44. FPGA Secondary Clocks
12
4
16:1
16:1
Secondary (Control)
Clocks
16:1
16:1
Routing
Clock
Pads
PIO Groups
FPGA PIO cells are assembled into two different types of PIO groups, those with four PIO cells and those with six PIO
cells. PIO groups with four I/Os are placed on the left and right sides of the device while PIO groups with six I/Os are
placed on the top and bottom. The individual PIO cells are connected to their respective sysIO buffers and pads.
Two adjacent PIOs can be joined to provide a complementary output driver pair. The I/O pin pairs are labeled as “T”
and “C” to distinguish between the true and complement pins.
Figure 45. Group of Four Programmable I/O Cells
This structure is used on the
left and right portion of the FPGA
PIO A
PADA "T"
PIO B
PADB "C"
PIO C
PADC "T"
PIO D
PADD "C"
Four PIOs
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Platform Manager Data Sheet
Figure 46. Group of Six Programmable I/O Cells
This structure is used on the top
and bottom portion of the devices
PIO A
PADA "T"
PIO B
PADB "C"
PIO C
PADC "T"
PIO D
PADD "C"
PIO E
PADE "T"
PIO F
PADF "C"
Six PIOs
PIO
The PIO blocks provide the interface between the sysIO buffers and the internal PFU array blocks. These blocks
receive output data from the PFU array and a fast output data signal from adjacent PFUs. The output data and fast
output data signals are multiplexed and provide a single signal to the I/O pin via the sysIO buffer. Figure 47 shows
the FPGA PIO logic.
The PIO receives an input signal from the pin via the sysIO buffer and provides this signal to the core of the FPGA
fabric. In addition there are programmable elements that can be utilized by the design tools to avoid positive hold
times.
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Platform Manager Data Sheet
Figure 47. PIO Block Diagram
From Routing
TS
From Routing
TO
sysIO
Buffer
Fast Output
Data signal
DO
Input
Data Signal
PAD
1
2
Programmable
Delay Elements
3
Note: Buffer 1 tracks with VCCAUX
Buffer 2 tracks with VCCIO.
Buffer 3 tracks with internal 1.2V VREF.
sysIO Buffer
Each I/O is associated with a flexible buffer referred to as a sysIO buffer. These buffers are arranged around the
periphery of the device in groups referred to as banks. The sysIO buffers allow users to implement the wide variety
of standards that are found in today’s systems including LVCMOS, TTL, BLVDS, LVDS and LVPECL.
FPGA output buffers and ratioed input buffers (LVTTL and LVCMOS) are powered using VCCIO. In addition to the bank
VCCIO supplies, the FPGA fabric has a VCC core logic power supply, and a VCCAUX supply that powers up a variety of
internal circuits.
Top and Bottom sysIO Buffer Pairs
The sysIO buffer pairs in the top and bottom banks of the device consist of two single-ended output drivers and two
sets of single-ended input buffers (for ratioed or absolute input levels). The I/O pairs on the top and bottom of the
devices also support differential input buffers.
Left and Right sysIO Buffer Pairs
The sysIO buffer pairs in the left and right banks of the device consist of two single-ended output drivers and two
sets of single-ended input buffers (supporting ratioed and absolute input levels). The devices also have a differential driver per output pair. The referenced input buffer can also be configured as a differential input buffer. In these
banks the two pads in the pair are described as “true” and “comp”, where the true pad is associated with the positive side of the differential I/O, and the comp (complementary) pad is associated with the negative side of the differential I/O.
Typical I/O Behavior During Power-up
The internal power-on-reset (POR) signal is deactivated when VCC and VCCAUX have reached satisfactory levels.
After the POR signal is deactivated, the FPGA core logic becomes active. It is the user’s responsibility to ensure
that all VCCIO banks are active with valid input logic levels to properly control the output logic states of all the I/O
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Platform Manager Data Sheet
banks that are critical to the application. The default configuration of the I/O pins in a blank device is tri-state with a
weak pull-up to VCCIO. The I/O pins will maintain the blank configuration until VCC, VCCAUX and VCCIO have
reached satisfactory levels at which time the I/Os will take on the user-configured settings.
The VCC and VCCAUX supply the power to the FPGA core fabric, whereas the VCCIO supplies power to the I/O buffers. In order to simplify system design while providing consistent and predictable I/O behavior, the I/O buffers
should be powered up along with the FPGA core fabric. Therefore, VCCIO supplies should be powered up together
with the VCC and VCCAUX supplies. (VCC and VCCAUX must be physically tied together for proper operation).
Supported Standards
The FPGA sysIO buffer supports both single-ended and differential standards. Single-ended standards can be further subdivided into LVCMOS and LVTTL. The buffer supports the LVTTL, LVCMOS 1.2, 1.5, 1.8, 2.5, and 3.3V
standards. In the LVCMOS and LVTTL modes, the buffer has individually configurable options for drive strength,
bus maintenance (weak pull-up, weak pull-down, bus-keeper latch or none) and open drain. BLVDS and LVPECL
output emulation is also supported.
Tables 18 and 19 show the I/O standards (together with their supply and reference voltages) supported by the
FPGA I/Os. For further information on utilizing the sysIO buffer to support a variety of standards please see the
details of additional technical documentation at the end of this data sheet. Note: I/O bank 2 pins do not support
LVCMOS12, LVCMOS15 or LVCMOS18 standards.
Table 18. Supported Input Standards
VCCIO (Typ.)
3.3V
2.5V
1.8V1
1.5V1
1.2V1
LVTTL
X
X
X
X
X
LVCMOS33
X
X
X
X
X
LVCMOS25
X
X
X
X
X
Input Standard
Single Ended Interfaces
LVCMOS18
X
LVCMOS15
X
LVCMOS12
X
X
X
X
X
1. Not supported by I/O Bank 2 (VCCIO2).
Table 19. Supported Output Standards
Output Standard
Drive
VCCIO (Typ.)
4mA, 8mA, 12mA, 16mA
3.3
LVCMOS33
4mA, 8mA, 12mA, 14mA
3.3
LVCMOS25
4mA, 8mA, 12mA, 14mA
2.5
Single-ended Interfaces
LVTTL
1
LVCMOS18
4mA, 8mA, 12mA, 14mA
1.8
LVCMOS151
4mA, 8mA
1.5
2mA, 6mA
1.2
4mA, 8mA, 12mA, 14mA
—
LVCMOS121
LVCMOS33, Open Drain
LVCMOS25, Open Drain
4mA, 8mA, 12mA, 14mA
—
LVCMOS18, Open Drain1
4mA, 8mA, 12mA, 14mA
—
LVCMOS15, Open Drain1
4mA, 8mA
—
LVCMOS12, Open Drain1
2mA, 6mA
—
1. Not supported by I/O Bank 2 (VCCIO2).
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Platform Manager Data Sheet
sysIO Buffer Banks
The FPGA I/O section has four banks (one bank per side).
Each sysIO buffer bank is capable of supporting multiple I/O standards. Each bank has its own I/O supply voltage
(VCCIO) which allows it to be completely independent from the other banks. Figure 48 shows the sysIO banks organization around the FPGA fabric.
Figure 48. FPGA I/O Banks
Bank 3
42
1
40
Bank 2
VCCIO2*
1
VCCIO1
GND
40
37
GND
GND
Bank 0
Bank 1
VCCIO3
GND
VCCIO0
1
1
*VCCIO2 is restricted to either 2.5V or 3.3V operation.
Hot Socketing
The FPGA I/Os have been carefully designed to ensure predictable behavior during power-up and power-down.
Leakage into I/O pins is controlled to within specified limits. This allows for easy integration with the rest of the
system. These capabilities make the FPGA I/Os ideal for many multiple power supply and hot-swap applications.
Sleep Mode
The Platform Manager FPGA section has a sleep mode that allows standby current to be reduced dramatically
during periods of system inactivity. Entry and exit to Sleep mode is controlled by the SLEEPN pin (see Pin Description Table).
During Sleep mode, the FPGA logic is non-operational, register contents are not maintained, and I/Os are tristated. Do not enter Sleep mode during device programming or configuration operation. In Sleep mode, power
supplies are in their normal operating range, eliminating the need for external switching of power supplies.
Table 20 compares the characteristics of Normal, Off and Sleep modes. Sleep mode does not shut down the
power management section of the Platform Manager. If Sleep mode is not used, ensure that the SLEEPN pin is
tied high via an external pull-up to VCC.
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Platform Manager Data Sheet
Table 20. Characteristics of Normal, Off and Sleep Modes
Characteristic
SLEEPN Pin
Static ICC
I/O Leakage
Normal
Off
Sleep
High
—
Low
Typical
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