LPTM21-1AFTG237I

Platform Manager 2 In-System Programmable Hardware Management Controller May 2016 Data Sheet DS1043 Features  Ten Rail Voltage Monitoring and Measurement  FPGA Resources • 1280 LUT, 98 I/O Version (LPTM21)  RAM and Flash Memories  Scalable Hardware Management Architecture • UV/OV Fault Detection Accuracy – 0.2% Typ. • Fault Detection Speed < 100 µs • High Voltage, Single Ended and Differential Sensing • Glueless interface to Hardware Management Expander (L-ASC10) • Migrate between LPTM21 and larger density MachXO2 device to extend logic and I/O resources  Two Channel Wide-Range Current Monitoring and Measurement • High-side current measurement up to 12 V • Programmable OC/UC Fault Detect • Detects Current faults in 0.650 V 0.2 0.7 % Single-ended VMON pins VMON voltage > 0.650 V 0.3 0.9 % 8 0.075 pF VMON HYST Hysteresis of any trip-point (relative to setting) 1 % VMON CMR Differential VMON Common mode rejection ratio 60 dB VZ Sense Low Voltage Sense Trip Point Error – Differential VMON1-4 Low Voltage Sense Trip Point Error – Single-Ended VMON5-9 Trip Point = 0.075 V –5 +5 mV Trip Point = 0.150 V –5 +5 mV Trip Point = 0.300 V –10 +10 mV Trip Point = 0.545 V –15 +15 mV Trip Point = 0.080 V –10 +10 mV Trip Point = 0.155 V –15 +15 mV Trip Point = 0.310 V –25 +25 mV Trip Point = 0.565 V –55 +55 mV 0.3 13.2 Volts 1.0 % +20 mV High Voltage Monitor HVMON Range High Voltage VMON programmable trip-point range HVMON Accuracy HVMON Absolute accuracy of any trip-point VZ Sense Low Voltage Sense Trip Point Error HVMON pin HVMON voltage > 1.8 V 0.4 Trip Point = 0.220 V –20 Trip Point = 0.425 V –35 +35 mV Trip Point = 0.810 V –75 +75 mV Trip Point = 1.280 V –130 +130 mV 1. VMON accuracy may degrade based on SSO conditions of FPGA section, especially bank 1. See the System Connections section for more details. 12 Platform Manager 2 In-System Programmable Hardware Management Controller Current Monitors Symbol Parameter IIMONPleak IMON1P input leakage IMON1N input leakage IIMONNleak IHIMONPleak HIMONP input leakage 2 IMONA/B Accuracy HIMON, IMON1A/B Comparator Trip Point accuracy IMONA/B Gain tIMONF Min Max Units –2 Typ 250 µA Low Side Sense Enabled Fast Trip Point Vsns =  500 mV –2 40 µA Low Side Sense Disabled Fast Trip Point Vsns =  500 mV –2 2 µA Low Side Sense Enabled Fast Trip Point Vsns =  500 mV –200 2 µA 550 µA 350 µA Fast Trip Point Vsns =  500 mV HIMONN_HVMON input leakage IHIMONNleak IMONF Accuracy Conditions Low Side Sense Disabled Fast Trip Point Vsns =  500 mV Programmable Gain Setting 2 Gain = 100x 8 % Gain = 50x 5 % Gain = 25x 3 % Gain = 10x 2 % Four settings in software 10 V/V 25 V/V 50 V/V 100 V/V 8 % Vsns = 200 mV, 250 mV, or 300 mV 5 % Vsns = 400 mV or  500 mV 3 % 1 Fast comparator trip-point accuracy Vsns = 50 mV, 100 mV, or 150 mV Fast comparator response time 1 µs 1. Vsns is the differential voltage between IMON1P and IMON1N (or HIMONP and HIMONN). 2. IMON accuracy may degrade based on SSO conditions of FPGA section, especially bank 1. See the System Connections section for more details. 13 Platform Manager 2 In-System Programmable Hardware Management Controller ADC Characteristics Symbol Parameter Conditions Min Resolution tCONVERT Typ Max 10 2 Conversion Time from I C Request Units Bits 200 µs V Voltage Monitors VVMON-IN LSB EVMON-attenuator Input Range Full scale ADC Step Size Error due to attenuator Programmable  Attenuator = 1 0 2.048 Programmable  Attenuator = 3 0 5.91 Programmable  Attenuator = 1 2 Programmable  Attenuator = 3 6 Programmable  Attenuator = 3 +/– 0.1 mV % High Voltage Monitor VHVMON-IN LSB EHVMON-attenuator Input Range Full scale ADC Step Size Error due to attenuator Programmable  Attenuator = 4 0 8.192 Programmable  Attenuator = 8 0 13.21 V Programmable  Attenuator = 4 8 Programmable  Attenuator = 8 16 Programmable  Attenuator = 4 +/–0.2 % Programmable  Attenuator = 8 +/–0.4 % 1 ms mV Current Monitors tIMON-sample Sample period of HVIMON and IMON1 conversions for averaged value 4 Settings via I2C  command 2 4 8 VIMON-IN LSB 1 Input Range Full scale ADC Step Size Programmable Gain 10x 0 200 Programmable Gain 25x 0 80 Programmable Gain 50x 0 40 Programmable Gain 100x 0 20 Programmable Gain 10x 0.2 Programmable Gain 25x 0.08 Programmable Gain 50x 0.04 Programmable Gain 100x 0.02 1. Differential voltage applied across HIMONP/IMON1P and HIMONN/IMO1N before programmable gain amplification. 14 mV mV Platform Manager 2 In-System Programmable Hardware Management Controller ADC Error Budget Over Entire Operating Temperature Range Symbol TADC Error Parameter Conditions Total ADC Measurement Error Measurement Range 600mV - 2.048 V, at Any Voltage (Differential VMONxGS > -100 mV, Attenuator =1 Analog Inputs)1, 3 Measurement Range 600mV - 2.048 V, VMONxGS > –200 mV, Attenuator =1 Min Typ Max Units –8 +/– 4 8 mV Measurement Range 0 - 2.048 V, VMONxGS > –200 mV, Attenuator =1 Total Measurement Error at Any Voltage (Single-Ended Analog Inputs including IMON)1, 2, 3 Measurement Range 600 mV - 2.048 V, Attenuator =1 –8 +/– 6 mV +/– 10 mV +/– 4 8 mV 1. Total error, guaranteed by characterization, includes INL, DNL, Gain, Offset, and PSR specs of the ADC. 2. Programmable gain error on IMON not included. 3. ADC accuracy may degrade based on SSO conditions of FPGA section, especially bank 1. See the System Connections section for more details Temperature Monitors Symbol Parameter Conditions Min Typ Max Units TMON_REMOTE Accuracy1, 7 Temp Error – Remote Sensor Ta = –40 to +85 ºC Td = –64 to 127 ºC 1 ºC TMON_INT  Accuracy7 Internal Sensor – Relative to ambient6 Ta=–40 to +85 ºC 1 ºC Resolution 0.25 TMON Range Programmable threshold range TMON Offset Temperature offset TMON  Hysteresis tTMON_settle2 ºC –64 155 ºC Programmable in software –63.75 63.75 ºC Hysteresis of trip points Programmable in software 0 63 ºC Temperature measurement settling time3 Measurement Averaging Coefficient = 1 15 ms Measurement Averaging Coefficient = 8 120 ms Tn Ideality Factor n Programmable in software Tlimit Temperature measurement limit4 160 ºC CTMON Maximum Capacitance between TMONP and TMONN pins 200 pF RTMONSeries Equivalent external resistance to sensor5 200 ohms Measurement Averaging Coefficient = 16 240 0.9 ms 2 1. Accuracy number is valid for the use of a grounded collector PNP configuration, programmed with proper ideality factor, and 16x measurement filter enabled. Any other device or configuration can have additional errors, including beta, series resistance and ideality factor accuracy. See Temperature Monitor Inputs section for more details. 2. Settling time based on one TMON enabled. For multiple TMONs, settling time can be multiplied by the number of enabled TMON channels. 3. Settling time is defined as the time is takes a step change to settle to within 1% of the measured value. 4. All values above Tlimit read as 0x3FF over I2C. There is no cold temperature limiting reading, although performance is not specified below – 64 oC. 5. This is the maximum series resistance which the TMON circuit can compensate out. Equivalent series resistance includes all board trace wiring (TMONP and TMONN) as well as parasitic base and emitter resistances. Re=1/gm should not be included as part of series resistance. 6. Internal sensor is subject to self-heating, dependent on PCB design and device configuration. Self-heating not included in published accuracy. 7. TMON accuracy may degrade based on SSO conditions of FPGA section, especially bank 1. See the System Connections section for more details 15 Platform Manager 2 In-System Programmable Hardware Management Controller High Voltage FET Drivers Symbol VPP Parameter Gate driver output voltage Conditions Min Four settings in software Typ Max 12 Units Volts 10 8 6 IOUTSRC Gate driver source current (HIGH state) Four settings in software 12.5 µA 25 50 100 IOUTSINK Gate driver sink current  (LOW state) Four settings in software 100 µA 250 500 3000 Frequency Switched Mode Frequency Two settings in software Duty Cycle Switched Mode Programmable Duty Cycle Range Programmable in software 15.625 kHz 31.25 6.25 Duty Cycle step size 93.75 6.25 % % Margin/Trim DAC Output Characteristics Symbol Parameter Conditions Min Resolution FSR Full scale range LSB LSB step size IOUT Output source/sink current ITRIM_Hi-Z Tri-state mode leakage BPZ Bipolar zero output voltage (code=80h) Typ. Max. 8 (7 + sign) Bits +/– 320 mV 2.5 mV –200 Four settings in software Units 200 µA 0.1 µA 0.6 V 0.8 1.0 1.25 tS TrimCell output voltage settling DAC code changed from 80H to FFH or time1 80H to 00H C_LOAD Maximum load capacitance TOSE Total open loop supply voltage Full scale DAC corresponds to +/– 5% supply voltage variation error2 Single DAC code change 2.5 ms 50 pF +1% V/V 260 –1% µs 1. To 1% of set value with 50 pF load connected to trim pins. 2. Total resultant error in the trimmed power supply output voltage referred to any DAC code due to DAC’s INL, DNL, gain, output impedance, offset error and bipolar offset error across the temperature, VCCA ranges of the device. 16 Platform Manager 2 In-System Programmable Hardware Management Controller Fault Log / User Tag EEPROM Symbol Parameter Conditions Records Number of available fault log records in EEPROM tfaultTrigger Minimum active time of trigger signal to start fault recording tfaultRecord Time to copy fault record to EEPROM Min Typ. Max. 16 Units Records 64 µs 5 ms Analog Sense and Control Oscillator Min Typ. Max. Units CLKASC Symbol Internal ASC0 Clock Parameter Conditions 7.6 8 8.4 MHz CLKext Externally Applied Clock 7.6 8 8.4 MHz FPGA sysIO Recommended Operating Conditions VCCIO (V) VREF (V) Standard Min. Typ. Max. Min. Typ. Max. LVCMOS 3.3 3.135 3.3 3.465 — — — LVCMOS 2.5 2.375 2.5 2.625 — — — LVCMOS 1.8 1.71 1.8 1.89 — — — LVCMOS 1.5 1.425 1.5 1.575 — — — LVCMOS 1.2 1.14 1.2 1.26 — — — LVTTL 3.135 3.3 3.465 — — — PCI3 3.135 3.3 3.465 — — — SSTL25 2.375 2.5 2.625 1.15 1.25 1.35 SSTL18 1.71 1.8 1.89 0.833 0.9 0.969 HSTL18 1.71 1.8 1.89 0.816 0.9 1.08 LVDS251, 2 2.375 2.5 2.625 — — — 1, 2 3.135 3.3 3.465 — — — 3.135 3.3 3.465 — — — 2.375 2.5 2.625 — — — 2.375 2.5 2.625 — — — SSTL18D 1.71 1.8 1.89 — — — SSTL25D 2.375 2.5 2.625 — — — HSTL18D 1.71 1.8 1.89 — — — LVDS33 LVPECL1 BLVDS 1 RSDS1 1. Inputs on-chip. Outputs are implemented with the addition of external resistors. 2. LPTM21 has dedicated LVDS buffers. 3. Input on the bottom bank of the LPTM21 only. 17 Platform Manager 2 In-System Programmable Hardware Management Controller FPGA sysIO Single-Ended DC Electrical Characteristics1, 2 Input/Output Standard LVCMOS 3.3 LVTTL VIL 3 Min. (V) VIH Max. (V) –0.3 0.8 Min. (V) Max. (V) 2.0 3.6 VOL Max. (V) 0.4 0.2 LVCMOS 2.5 LVCMOS 1.8 LVCMOS 1.5 LVCMOS 1.2 -0.3 0.7 –0.3 0.35VCCIO –0.3 0.35VCCIO –0.3 0.35VCCIO 1.7 3.6 0.65VCCIO 3.6 0.65VCCIO 3.6 0.65VCCIO 3.6 VOH Min. (V) IOL Max.4 (mA) IOH Max.4 (mA) 4 –4 VCCIO - 0.4 VCCIO - 0.2 8 –8 12 –12 16 –16 24 –24 0.1 –0.1 4 –4 8 –8 12 –12 0.4 VCCIO - 0.4 0.2 VCCIO - 0.2 0.4 VCCIO - 0.4 12 –12 0.2 VCCIO - 0.2 0.1 –0.1 0.4 VCCIO - 0.4 4 –4 8 –8 0.2 VCCIO - 0.2 0.1 –0.1 4 –2 16 –16 0.1 –0.1 4 –4 8 –8 0.4 VCCIO - 0.4 8 –6 0.2 VCCIO - 0.2 0.1 –0.1 PCI –0.3 0.3VCCIO 0.5VCCIO 3.6 0.1VCCIO 0.9VCCIO 1.5 –0.5 SSTL25 Class I –0.3 VREF - 0.18 VREF + 0.18 3.6 0.54 VCCIO - 0.62 8 8 SSTL25 Class II –0.3 VREF - 0.18 VREF +0.18 3.6 NA NA NA NA SSTL18 Class I –0.3 VREF - 0.125 VREF +0.125 VREF - 0.125 VREF +0.125 3.6 0.40 VCCIO - 0.40 8 8 SSTL18 Class II –0.3 3.6 NA NA NA NA HSTL18 Class I –0.3 VREF - 0.1 VREF +0.1 3.6 0.40 VCCIO - 0.40 8 8 HSTL18 Class II –0.3 VREF - 0.1 VREF +0.1 3.6 NA NA NA NA 1. Platform Manager 2 devices allow LVCMOS inputs to be placed in I/O banks where VCCIO is different from what is specified in the applicable JEDEC specification. This is referred to as a ratioed input buffer. In a majority of cases this operation follows or exceeds the applicable JEDEC specification. The cases where Platform Manager 2 devices do not meet the relevant JEDEC specification are documented in the table below. 2. Platform Manager 2 devices allow for LVCMOS referenced I/Os which follow applicable JEDEC specifications. For more details about mixed mode operation please refer to please refer to TN1202, MachXO2 sysIO Usage Guide. 3. The I2C pins SCL_M and SDA_M are limited to a VIL min of –0.25V or to –0.3V with a duration of 100MHz — 150 ps p-p fOUT < 100MHz — 0.007 UIPP fOUT > 100MHz — 180 ps p-p fOUT < 100MHz — 0.009 UIPP fPFD > 100MHz — 160 ps p-p fPFD < 100MHz — 0.011 UIPP fOUT > 100MHz — 230 ps p-p fOUT < 100MHz — 0.12 UIPP Output Clock Cycle-to-cycle Jitter  (Fractional-N) fOUT > 100MHz — 230 ps p-p fOUT < 100MHz — 0.12 UIPP Static Phase Offset Divider ratio = integer –120 120 ps Output Clock Period Jitter (Fractional-N) tSPO Conditions 3 tW Output Clock Pulse Width 0.9 — ns tLOCK2, 5 PLL Lock-in Time At 90% or 10% — 15 ms tUNLOCK PLL Unlock Time — 50 ns tIPJIT6 Input Clock Period Jitter fPFD  20 MHz — 1,000 ps p-p fPFD < 20 MHz — 0.02 UIPP tHI Input Clock High Time 90% to 90% 0.5 — ns tLO Input Clock Low Time 10% to 10% 0.5 — ns tSTABLE5 STANDBY High to PLL Stable — 15 ms tRST RST/RESETM Pulse Width 1 — ns tRSTREC RST Recovery Time 1 — ns tRST_DIV RESETC/D Pulse Width 10 — ns tRSTREC_DIV RESETC/D Recovery Time 1 — ns tROTATE-SETUP PHASESTEP Setup Time 10 — ns tROTATE_WD 4 — VCO Cycles PHASESTEP Pulse Width 1. Period jitter sample is taken over 10,000 samples of the primary PLL output with a clean reference clock. Cycle-to-cycle jitter is taken over 1000 cycles. Phase jitter is taken over 2000 cycles. All values per JESD65B. 2. Output clock is valid after tLOCK for PLL reset and dynamic delay adjustment. 3. Using LVDS output buffers. 4. CLKOS as compared to CLKOP output for one phase step at the maximum VCO frequency. See TN1199, MachXO2 sysCLOCK PLL Design and Usage Guide for more details. 5. At minimum fPFD. As the fPFD increases the time will decrease to approximately 60% the value listed. 6. Maximum allowed jitter on an input clock. PLL unlock may occur if the input jitter exceeds this specification. Jitter on the input clock may be transferred to the output clocks, resulting in jitter measurements outside the output specifications listed in this table. 7. Edge Duty Trim Accuracy is a percentage of the setting value. Settings available are 70 ps, 140 ps, and 280 ps in addition to the default value of none. 8. Jitter values measured with the internal oscillator operating. The jitter values will increase with loading of the PLD fabric and in the presence of SSO noise. 25 Platform Manager 2 In-System Programmable Hardware Management Controller Analog Sense and Control Propagation Delays Symbol Parameter Conditions Min Typ. Max. Units Voltage Monitors tVMONtoFPGA tVMONtoOCB 2 Propagation delay VMON Glitch Filter Off input to signal update at FPGA Glitch Filter ON 48 µs 96 µs Propagation delay VMON Glitch Filter Off input to output update at OCB Glitch Filter ON 16 µs 64 µs Current Monitors tIMONtoFPGA Propagation delay IMON input Glitch Filter Off to signal update at FPGA Glitch Filter ON tIMONtoOCB2 Propagation delay IMON input Glitch Filter Off to output update at OCB Glitch Filter ON 16 µs 64 µs tIMONFtoOCB2 Propagation delay IMONF input to output update at OCB 1 µs 48 µs 96 µs Temperature Monitors tTMONtoFPGA Propagation delay TMON input to signal update at FPGA1 Monitor Alarm Filter Depth = 1 15 ms Monitor Alarm Filter Depth = 16 240 ms 32 µs GPIO – Inputs tGPIOtoFPGA Propagation delay GPIO input to signal update at FPGA tGPIOtoOCB3 Propagation delay GPIO input to output update at OCB 50 ns GPIO – Outputs tFPGAtoGPIO Propagation delay FPGA signal update to GPIO output tOCBtoGPIO2 Propagation delay OCB input to output update at GPIO 32 µs 50 ns HVOUT tFPGAtoHVOUT Propagation delay FPGA signal update to HVOUT output tOCBtoHVOUT4 Propagation delay OCB input to output update at HVOUT 32 µs 110 ns TRIM DAC tFPGAtoTrimOE Propagation delay FPGA signal update to TRIM-OE update 32 1. Propagation delay based on one TMON enabled. For multiple TMONs, propagation delay can be multiplied by the number of enabled TMON channels. 2. OCB output propagation delays measured using time delay to GPIO output from OCB. Propagation delay is measured on falling GPIO outputs. Rising output propagation will be dependent on external pull-up resistor. 3. OCB input propagation delays measured using time delay from GPIO input to OCB. 4. HVOUT propagation delay measured with HVOUT in open-drain mode, with switched mode disabled. Propagation delay in charge pump mode is dependent on external load and HVOUT settings. 26 µs Platform Manager 2 In-System Programmable Hardware Management Controller JTAG Port Timing Specifications Symbol fMAX Parameter TCK clock frequency Min. Max. Units — 25 MHz tBTCPH TCK [BSCAN] clock pulse width high 20 — ns tBTCPL TCK [BSCAN] clock pulse width low 20 — ns tBTS TCK [BSCAN] setup time 10 — ns tBTH TCK [BSCAN] hold time 8 — ns tBTCO TAP controller falling edge of clock to valid output — 10 ns tBTCODIS TAP controller falling edge of clock to valid disable — 10 ns tBTCOEN TAP controller falling edge of clock to valid enable — 10 ns tBTCRS BSCAN test capture register setup time 8 — ns tBTCRH BSCAN test capture register hold time 20 — ns tBUTCO BSCAN test update register, falling edge of clock to valid output — 25 ns tBTUODIS BSCAN test update register, falling edge of clock to valid disable — 25 ns tBTUPOEN BSCAN test update register, falling edge of clock to valid enable — 25 ns Figure 7. JTAG Port Timing Waveforms TMS TDI tBTS tBTCPH tBTH tBTCP tBTCPL TCK tBTCO tBTCOEN TDO Valid Data tBTCRS Data to be captured from I/O tBTCODIS Valid Data tBTCRH Data Captured tBTUPOEN tBUTCO Data to be driven out to I/O Valid Data 27 tBTUODIS Valid Data Platform Manager 2 In-System Programmable Hardware Management Controller I2C Port Timing Specifications1, 2 Symbol fMAX Parameter Maximum SCL clock frequency Min. Max. Units — 400 kHz 1. Platform Manager 2 supports the following modes: • Standard-mode (Sm), with a bit rate up to 100 kbit/s (user and configuration mode) • Fast-mode (Fm), with a bit rate up to 400 kbit/s (user and configuration mode) 2. Refer to the I2C specification for timing requirements. Switching Test Conditions — FPGA Section Figure 8 shows the output test load used for AC testing. The specific values for resistance, capacitance, voltage, and other test conditions are shown in Table 6. Figure 8. Output Test Load, LVTTL and LVCMOS Standards VT R1 DUT Test Poi nt CL Table 6. Test Fixture Required Components, Non-Terminated Interfaces Test Condition LVTTL and LVCMOS settings (L -> H, H -> L) R1 CL  0pF Timing Ref. VT LVTTL, LVCMOS 3.3 = 1.5 V — LVCMOS 2.5 = VCCIO/2 — LVCMOS 1.8 = VCCIO/2 — LVCMOS 1.5 = VCCIO/2 — LVCMOS 1.2 = VCCIO/2 — LVTTL and LVCMOS 3.3 (Z -> H) 1.5 VOL LVTTL and LVCMOS 3.3 (Z -> L) 1.5 VOH Other LVCMOS (Z -> H) VCCIO/2 VOL Other LVCMOS (Z -> L) 188 0pF VCCIO/2 VOH LVTTL + LVCMOS (H -> Z) VOH - 0.15 VOL LVTTL + LVCMOS (L -> Z) VOL - 0.15 VOH Note: Output test conditions for all other interfaces are determined by the respective standards. 28 Platform Manager 2 In-System Programmable Hardware Management Controller Theory of Operation Hardware Management System The Platform Manager 2 is a fast-reacting, programmable logic based hardware management controller. The Platform Manager 2 includes an Analog Sense and Control (ASC) section and an FPGA section, allowing it to address the Power Management, Thermal Management and Digital Control Plane requirements of a circuit board. The Platform Manager 2 FPGA section includes the hardware management control logic and other plug-in IP components to support functions like Fan Control, Voltage by Identification (VID), and time stamped fault logging to internal or external memory. The FPGA also includes the ASC Interface logic (ASC-I/F) used to communicate with the ASC section (internal to the device) and additional ASC hardware management expanders. The Platform Manager 2 supports a scalable, star-architecture implementation with centralized sequencing and control. This is accomplished by adding additional ASC hardware management expanders to the circuit board. The basic system concept is shown in Figure 9. The necessary connections are shown in detail in the System Connections section. Figure 9. Hardware Management System Analog Sense and Control Section FPGA Section MOSFET & Digital I/O Drive Output Control Block FPGA LUTs (IP Components) Current Sense ASC Interface (ASC-I/F) Fan Control Component Power Sequencing To additional ASCs Temperature Sense Voltage Sense ADC ADC Non Volatile Fault Log Time Stamp Fault Log Component I2C Interface Voltage / Current Monitoring VID / Voltage Scaling User Logic FPGA I/O Ports SPI JTAG I2C Trim & Margin Control To additional ASCs, Microcontrollers, etc. The Hardware Management System is configured using Platform Designer, a part of Lattice Diamond software. Platform Designer provides an easy to use graphical and spreadsheet based interface. Platform Designer automatically generates the device memory configuration based on the options selected in the software. See the For Further Information section for more details 29 Platform Manager 2 In-System Programmable Hardware Management Controller Voltage Monitor Inputs The ASC provides ten independently programmable voltage monitor input circuits. There are nine standard voltage channels and one high voltage channel. The standard voltage channels are shown in Figure 10, while the high voltage channel is described in the High Voltage Monitor section. Two individually programmable trip-point comparators are connected to each voltage monitoring input. Each comparator reference has programmable trip points over the range of 0.075 V to 5.734 V. The 75 mV ‘zero-detect’ threshold allows the voltage monitors to determine if a monitored signal has dropped to ground level. This feature is especially useful for determining if a power supply’s output has decayed to a substantially inactive condition after it has been switched off. Figure 10. ASC Voltage Monitors To ADC Differential Input Buffer X* CompA/Window Select Comp A VMONx VMONx_A Logic Signal Trip Point A MUX VMONxGS* Glitch Filter Comp B VMONx_B Logic Signal Glitch Filter Trip Point B Analog Input TO ASC-I/F & OCB Window Control Filtering VMONx Status 2 I C Interface Unit *Differential Input Buffer X and VMONxGS pins are not present for single-ended VMON x inputs. Figure 10 shows the functional block diagram of one of the nine voltage monitor inputs - ‘x’ (where x = 1...9). Each voltage monitor can be divided into three sections: Analog Input, Window Control, and Filtering. The first section provides a differential input buffer to monitor the power supply voltage through VMONx (to sense the positive terminal of the supply) and VMONxGS (to sense the power supply ground). Differential voltage sensing minimizes inaccuracies in voltage measurement with ADC and monitor thresholds due to the potential difference between the Platform Manager 2 device ground and the ground potential at the sensed node on the circuit board. The voltage output of the differential input buffer is monitored by two individually programmable trip-point comparators, shown as Comp A and Comp B. The differential input buffer shown above is not present for any of the singleended VMON inputs. VMON1-4 are differential inputs, while VMON5-9 are single-ended. Each comparator outputs a HIGH signal to the ASC-I/F if the voltage at its positive terminal is greater than its programmed trip point setting; otherwise it outputs a LOW signal. The VMON4A and VMON9A comparators also output their status signals to the OCB. Hysteresis is provided by the comparators to reduce false triggering as a result of input noise. The hysteresis provided by the voltage monitor is a function of the input divider setting. Table 7 lists the typical hysteresis versus voltage monitor trip-point. AGOOD Logic Signal All the VMON, IMON and TMON comparators auto-calibrate following a power-on reset event. During this time, the digital glitch filters are also initialized. This process completion is signaled by an internally generated logic signal: AGOOD. The ASC-I/F will not begin communicating valid VMON status bits or receiving GPIO control signals until the AGOOD signal is initialized. 30 Platform Manager 2 In-System Programmable Hardware Management Controller Programmable Over-Voltage and Under-Voltage Thresholds Figure 11 shows the power supply ramp-up and ramp-down voltage waveforms. Because of hysteresis, the comparator outputs change state at different thresholds depending on the direction of excursion of the monitored power supply. Monitored Power Supply Voltage Figure 11. Power Supply Voltage Ramp-up and Ramp-down Waveform and the Resulting Comparator Output (a) and Corresponding to Upper and Lower Trip Points (b) UTP LTP (a) (b) Comparator Logic Output During power supply ramp-up the comparator output changes from logic zero to one when the power supply voltage crosses the upper trip point (UTP). During ramp down the comparator output changes from logic state one to zero when the power supply voltage crosses the lower trip point (LTP). To monitor for over voltage fault conditions, the UTP should be used. To monitor under-voltage fault conditions, the LTP should be used. The upper and lower trip points are automatically selected in software depending on whether the user is monitoring for an over-voltage condition or an under-voltage condition. Table 7 shows the comparator hysteresis versus the trip-point range. Table 7. Voltage Monitor Comparator Hysteresis vs. Trip-Point Trip-point Range (V) Hysteresis (mV) Low Limit High Limit 0.66 0.79 8 0.79 0.9 10 0.94 1.12 12 1.12 1.33 14 1.33 1.58 17 1.58 1.88 20 1.88 2.24 24 2.24 2.66 28 2.66 3.16 34 3.16 3.76 40 4.05 4.82 51 4.82 5.73 61 0.075 0.57 0 (Disabled) 31 Platform Manager 2 In-System Programmable Hardware Management Controller The window control section of the voltage monitor circuit is an AND gate (with inputs: an inverted COMPA “ANDed” with COMPB signal) and a multiplexer that supports the ability to develop a ‘window’ function in hardware. Through the use of the multiplexer, voltage monitor’s ‘A’ output may be set to report either the status of the ‘A’ comparator, or the window function of both comparator outputs. The voltage monitor’s ‘A’ output indicates whether the input signal is between or outside the two comparator thresholds. Important: This windowing function is only valid in cases where the threshold of the ‘A’ comparator is set to a value higher than that of the ‘B’ comparator. Table 8 shows the operation of window function logic. Table 8. Voltage Monitoring Window Logic Comp A Comp B Window (B and Not A) Comment VIN < Trip-Point B < Trip-Point A 0 0 0 Outside window, low Trip-Point B