LX256ECCF1005

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LATTICE(莱迪思半导体)
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LX256ECCF1005 - High Performance Interfacing and Switching - Lattice Semiconductor

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LX256ECCF1005 数据手册

ispGDX2™ Family September 2005 Features Includes High, Performance w-Cost Lo “E-Series” High Performance Interfacing and Switching Data Sheet ■ Two Options Available • High-performance sysHSI (standard part number) • Low-cost, no sysHSI (“E-Series”) ■ High Performance Bus Switching • High bandwidth – Up to 12.8 Gbps (SERDES) – Up to 38 Gbps (without SERDES) • Up to 16 (15x10) FIFOs for data buffering • High speed performance – fMAX = 360MHz – tPD = 3.0ns – tCO = 2.9ns – tS = 2.0ns • Built-in programmable control logic capability • I/O intensive: 64 to 256 I/Os • Expanded MUX capability up to 188:1 MUX ■ sysHSI Blocks Provide up to 16 High-speed Channels • • • • • Serializer/de-serializer (SERDES) included Clock Data Recovery (CDR) built in 800 Mbps per channel LVDS differential support 10B/12B support – Encoding / decoding – Bit alignment – Symbol alignment • 8B/10B support – Bit alignment – Symbol alignment • Source Synchronous support ■ sysCLOCK™ PLL • • • • Frequency synthesis and skew management Clock multiply and divide capability Clock shifting up to +/-2.35ns in 335ps steps Up to four PLLs ■ Flexible Programming and Testing • IEEE 1532 compliant In-System Programmability (ISP™) • Boundary scan test through IEEE 1149.1 interface • 3.3V, 2.5V or 1.8V power supplies • 5V tolerant I/O for LVCMOS 3.3 and LVTTL interfaces ■ sysIO™ Interfacing • LVCMOS 1.8, 2.5, 3.3 and LVTTL support for standard board interfaces • SSTL 2/3 Class I and II support • HSTL Class I, III and IV support • GTL+, PCI-X for bus interfaces • LVPECL, LVDS and Bus LVDS differential support • Hot socketing • Programmable drive strength Table 1. ispGDX2 Family Selection Guide ispGDX2-64/E I/Os GDX Blocks tPD tS tCO fMAX (Toggle) Max Bandwidth sysHSI Channels PLLs Package 1. Max number of SERDES channels per device * 800Mbps 2. “E-Series” does not support sysHSI. 3. fMAX (Toggle) * maximum I/Os divided by 2. 2 ispGDX2-128/E 128 8 3.2ns 2.0ns 3.1ns 330MHz 6.4Gbps 21Gbps 8 64 2 208-ball fpBGA ispGDX2-256/E 256 16 3.5ns 2.0ns 3.2ns 300MHz 12.8Gbps 38Gbps 16 128 4 484-ball fpBGA 64 4 3.0ns 2.0ns 2.9ns 360MHz SERDES1, 2 Without SERDES3 3.2Gbps 11Gbps 4 32 2 100-ball fpBGA LVDS/Bus LVDS (Pairs) © 2005 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without notice. www.latticesemi.com 1 gdx2fam_13 Lattice Semiconductor Figure 1. ispGDX2 Block Diagram (256-I/O Device) sysIO Bank sysHSI Block ispGDX2 Family Data Sheet sysIO Bank SERDES FIFO GDX Block SERDES FIFO sysHSI Block sysHSI Block sysCLOCK PLL SERDES FIFO SERDES FIFO GDX Block sysCLOCK PLL sysHSI Block GDX Block GDX Block GDX Block GDX Block SERDES SERDES SERDES SERDES SERDES sysHSI Block FIFO FIFO sysIO Bank Introduction The ispGDX2™ family is Lattice’s second generation in-system programmable generic digital crosspoint switch for high speed bus switching and interface applications. The ispGDX2 family is available in two options. The standard device supports sysHSI capability for ultra fast serial communications while the lower-cost “E-series” supports the same high-performance FPGA fabric without the sysHSI Block. This family of switches combines a ﬂexible switching architecture with advanced sysIO interfaces including high performance sysHSI Blocks, and sysCLOCK PLLs to meet the needs of the today’s high-speed systems. Through a muliplexer-intensive architecture, the ispGDX2 facilitates a variety of common switching functions. The availability of on-chip control logic further enhances the power of these devices. A high-performance solution, the family supports bandwidth up to 38Gbps. Every device in the family has a number of PLLs to provide the system designer with the ability to generate multiple clocks and manage clock skews in their systems. sysIO Bank sysIO Bank GDX Block GDX Block SERDES sysCLOCK PLL FIFO FIFO FIFO FIFO Global Routing Pool (GRP) sysHSI Block GDX Block GDX Block GDX Block FIFO SERDES GDX Block GDX Block SERDES SERDES sysHSI Block FIFO FIFO sysIO Bank GDX Block GDX Block GDX Block FIFO SERDES FIFO SERDES FIFO SERDES sysHSI Block sysCLOCK PLL sysIO Bank sysIO Bank ISP & Boundary Scan Test Port 2 Lattice Semiconductor ispGDX2 Family Data Sheet The sysIO interfaces provide system-level performance and integration. These I/Os support various modes of LVCMOS/LVTTL and support popular high-speed standard interfaces such as GTL+, PCI-X, HSTL, SSTL, LVDS and Bus-LVDS. The sysHSI Blocks further extend this capability by providing high speed serial data transfer capability. Devices in the family can operate at 3.3V, 2.5V or 1.8V core voltages and can be programmed in-system via an IEEE 1149.1 interface that is compliant with the IEEE 1532 standard. Voltages required for the I/O buffers are independent of the core voltage supply. This further enhances the ﬂexibility of this family in system designs. Typical applications for the ispGDX2 include multi-port multi-processor interfaces, wide data and address bus multiplexing, programmable control signal routing and programmable bus interfaces. Table 1 shows the members of the ispGDX2 family and their key features. Architecture The ispGDX2 devices consist of GDX Blocks interconnected by a Global Routing Pool (GRP). Signals interface with the external system via sysIO banks. In addition, each GDX Block is associated with a FIFO and a sysHSI Block to facilitate the transfer of data on- and off-chip. Figure 1 shows the ispGDX2 block diagram. Each GDX Block can be individually conﬁgured in one of four modes: • Basic (No FIFO or SERDES) • FIFO Only • SERDES Only • SERDES and FIFO Each sysIO bank has its own I/O power supply and reference voltage. Designers can use any output standard within a bank that is compatible with the power supply. Any input standard may be used, providing it is compatible with the reference voltage. The banks are independent. Global Routing Pool (GRP) The ispGDX2 architecture is organized into GDX Blocks, which are connected via a Global Routing Pool. The innovative GRP is optimized for routability, ﬂexibility and speed. All the signals enter via the GDX Block. The block supplies these either directly or in registered form to the GRP. The GRP routes the signals to different blocks, and provides separate data and control routing. The data path is optimized to achieve faster speed and routing ﬂexibility for nibble oriented signals. The control routing is optimized to provide high-speed bit oriented routing of control signals. There are some restrictions on the allocation of pins for optimal bus routing. These restrictions are considered by the software in the allocation of pins. GDX Block The blocks are organized in a “block” (nibble) manner, with each GDX Block providing data ﬂow and control logic for 16 I/O buffers. The data ﬂow is organized as four nibbles, each nibble containing four Multiplexer Register Blocks (MRBs). Data for the MRBs is provided from 64 lines from the GRP. Figure 2 illustrates the groups of signals going into and out of a GDX Block. Control signals for the MRBs are provided from the Control Array. The Control Array receives the 32 signals from the GRP and generates 16 control signals: eight MUX Select, four Clock/Clock Enable, two Set/Reset and two Output Enable. Each nibble is controlled via two MUX select signals. The remaining control signals go to all the MRBs. Besides the control signals from the Control Array, the following global signals are available to the MRBs in each GDX Block: four Clock/Clock Enable, one reset/preset, one power-on reset, two of four MUX select (two of two in 64 I/O), four Output Enable (two in 64 I/O) and Test Out Enable (TOE). 3 Lattice Semiconductor MUX and Register Block (MRB) ispGDX2 Family Data Sheet Every MRB Block has a 4:1 MUX (I/O MUX) and a set of three registers which are connected to the I/O buffers, FIFO and sysHSI Blocks. Multiple MRBs can be combined to form large multiplexers as described below. Figure 3 shows the structure of the MRB. Each of the three registers in the MRB can be conﬁgured as edge-triggered D-type ﬂip-ﬂop or as a level sensitive latch. One register operates on the input data, the other output data and the last register synchronizes the output enable function. The input and output data signals can bypass each of their registers. The polarity of the data out and output enable signals can be selected. The Output and OE register share the same clock and clock enable signals. The Input register has a separate clock and clock enable. The initialization signals of each register can be independently conﬁgured as Set or Reset. These registers have programmable polarity control for Clock, Clock Enable and Set/Reset. The output enable register input can be set either by one of the two output enables generated locally from the Control Array or from one of the four (two in 64 I/O) Global OE enable pins. In addition to the local clock and clock enable signals, each MRB has access to Global Clock, Clock Enable, Reset and TOE nets. 4 Lattice Semiconductor Figure 2. GDX Block GRP 32 bits MUX Control Select 8 8 ispGDX2 Family Data Sheet GDX Block sysIO Bank Control Array Nibble 0 OE 8 2 4 bits MUX and Register Block (MRB) 0 IN OUT 8 2 OE MUX and Register Block (MRB) 1 IN OUT 4 bits 8 2 4 bits MUX and Register Block (MRB) 2 OE IN OUT 8 OE 2 4 bits MUX and Register Block (MRB) 3 IN OUT 8 2 16 bits 4 8 2 Nibble 1 MRBs 4-7 OE IN OUT OE IN OUT OE IN OUT Nibble 2 MRBs 8-11 16 bits 4 8 2 16 bits 4 Nibble 3 MRBs 12-15 The output register of the MRB has a built-in bi-directional shift register capability. Each output register corresponding to MRB “n”, receives data output from its two adjacent MRBs, MRB (n-1) and MRB (n+1), to provide shift register capability. Like the output register, each input register of the MRB has built-in shift register capability. Each input register can receive data from its two adjacent MRB input registers, to provide bi-directional shift register capability. The chaining crosses GDX Block boundaries. The chain of input registers and the chain of output registers can be combined as one shift register via the GRP. 5 Lattice Semiconductor ispGDX2 Family Data Sheet The four data inputs to the 4:1 MUX come from the GRP. The output of this MUX connects to the output register. A fast feedback path from the MUX to the GRP allows wider MUXes to be built. Table 2 summarizes the various MUX sizes and delay levels. Table 2. MUX Size Versus Internal Delay MUX Sizes 4:1 Up to 16:1 Up to 64:1 Up to 188:1 (with ispGDX2-256) Levels of Internal GRP Delays One Level Two Levels Three Levels Four Levels Figure 3. ispGDX2 Family MRB MUX Select Control Array Signals Global Signals 4 2-4 GDX Control Array 2 4 2 OE D/L Q CK/CE MUX Select Global Signals OE CK ClK OE Reg/Latch TOE Flags* (FIFO, SERDES or PLL) CE CE Set Reset VCC Set/Reset CK/CE From GRP from Out_Reg(n-1) from Out_Reg(n+1) OE D/L Q to Out_Reg(n-1) to Out_Reg(n+1) ClK Out Reg/Latch CE Set Reset VCC S/R Global Resetb To GRP Delay FIFO Out* from IN_Reg(n-1) from IN_Reg(n+1) CK D/L Q to IN_Reg(n-1) to IN_Reg(n+1) ClK Input Reg/Latch CE CE Set Reset S/R Global Resetb *Selected MRBs see Logic Signal Connection Table for details Control Array The control array generates control signals for the 16 MRBs within a GDX Block. The true and complement forms of 32 inputs from the GRP are available in the control array. The 20 NAND terms can use any or all of these inputs to form the control array outputs. Two AND terms are combined with a NOR term to form Set/Reset and OE signals. Figure 4 illustrates the control array. 6 Lattice Semiconductor Figure 4. ispGDX2 Family Control Array 32 Inputs from Control GRP ispGDX2 Family Data Sheet Each connection is programmable. MUX Select to Nibble 0 MUX Select to Nibble 1 MUX Select to Nibble 2 MUX Select to Nibble 3 To MRB Clock/ Clock Enable On selected blocks, this signal can reset the M Divider of the PLL. To MRB Set/Reset To MRB Output Enable sysIO Banks The inputs and outputs of ispGDX2 devices are divided into eight sysIO banks, where each bank is capable of supporting different I/O standards. The number of I/Os per bank is 32, 16 and 8 for the 256-, 128- and 64-I/O devices respectively. Each sysIO bank has its own I/O supply voltage (VCCO) and reference voltage (VREF), allowing each bank complete independence from the other banks. Each I/O within a bank can be individually conﬁgured to any standard consistent with the VCCO and VREF settings. Figure 5 shows the I/O banks for the ispGDX2-256 device. The I/O of the ispGDX2 devices contain a programmable strength and slew rate tri-state output buffer, a programmable input buffer, a programmable pull-up resistor, a programmable pull-down resistor and a programmable buskeeper latch. These programmable capabilities allow the support of a wide range of I/O standards. 7 Lattice Semiconductor Figure 5. ispGDX2-256 sysIO Banks VCCO4 GND VREF4 GND VREF3 VCCO3 ispGDX2 Family Data Sheet sysIO Bank 4 VCCO5 VREF5 GND sysIO Bank 5 sysIO Bank 3 VCCO2 sysIO Bank 2 VREF2 GND VCCO6 VREF6 GND sysIO Bank 7 sysIO Bank 0 sysIO Bank 6 sysIO Bank 1 VCCO1 VREF1 GND There are three classes of I/O interface standards implemented in the ispGDX2 devices. The ﬁrst is the non-terminated, single-ended interface; it includes the 3.3V LVTTL standard along with the 1.8V, 2.5V and 3.3V LVCMOS interface standards. The slew rate and strength of these output buffers can be controlled individually. Additionally, PCI 3.3, PCI-X and AGP-1X are all subsets of this interface type. The second interface class implemented is the terminated, single-ended interface standard. This group of interfaces includes different versions of SSTL and HSTL interfaces along with CTT and GTL+. Use of these I/O interfaces requires an additional VREF signal. At the system level, a termination voltage, VTT, is also required. Typically, an output will be terminated to VTT at the receiving end of the transmission line it is driving. The ﬁnal types of interfaces implemented are the differential standards LVPECL, LVDS and Bus LVDS. Table 3 shows the I/O standards supported by the ispGDX2 devices along with nominal VCCO, VREF and VTT. The ispGDX2 family also features 5V tolerant I/O. I/O banks with VCCO = 3.3V may have inputs driven to a maximum of 5.5V for easy interfacing with legacy systems. Up to 64 I/O pins per device may be driven by 5V inputs. GND VREF7 VCCO7 GND VREF0 VCCO0 8 Lattice Semiconductor Table 3. ispGDX2 Supported I/O Standards sysIO Standard LVCMOS 3.3 LVCMOS 2.5 LVCMOS 1.8 LVTTL PCI 3.3 PCI -X AGP-1X SSTL3 class I & II SSTL2 class I & II CTT 3.3 CTT 2.5 HSTL class I HSTL class III HSTL class IV GTL+ LVPECL1, 2, 3 LVDS Bus-LVDS Nominal VCCO 3.3V 2.5V 1.8V 3.3V 3.3V 3.3V 3.3V 3.3V 2.5V 3.3V 2.5V 1.5V 1.5V 1.5V 1.8/2.5/3.3V 3.3V 2.5/3.3V 2.5/3.3V Nominal VREF — — — — — — — 1.5V 1.25V 1.5V 1.25V 0.75V 0.9V 0.9V 1.0V — — — ispGDX2 Family Data Sheet Nominal VTT — — — — — — — 1.5V 1.25V 1.5V 1.25V 0.75V 0.75V 1.5V 1.5V — — — 1. LVPECL drivers require three resistor pack (see Figure 17). 2. Depending on the driving LVPECL output speciﬁcation, GDX2 LVPECL input driver may require terminating resistors. 3. For additional information on LVPECL refer to Lattice technical note number TN1000, sysIO Design and Usage Guidelines. The dedicated inputs support a subset of the sysIO standards indicated in Table 4. These inputs are associated with a bank consistent with their location. Table 4. I/O Standards Supported by Dedicated Inputs LVCMOS Global OE Pins Global MUX Select Pins Resetb Global Clock/Clock Enables ispJTAG™ Port TOE 1. LVCMOS as deﬁned by the VCCJ pin voltage. 2. No PCI clamp. LVDS No No No Yes No No All other ASIC I/Os Yes2 Yes2 Yes2 Yes2 No No Yes Yes Yes Yes Yes1 Yes For more information on the sysIO capability, please refer to Lattice technical note number TN1000, sysIO Design and Usage Guidelines. sysCLOCK PLL The sysCLOCK PLL circuitry consists of Phase-Lock Loops (PLLs) along the various dividers and reset and feedback signals associated with the PLLs. This feature gives the user the ability to synthesize clock frequencies and generate multiple clock signals for routing within the device. Furthermore, it can generate clock signals that are deskewed either at the board level or the device level. Figure 6 shows the ispGDX2 PLL block diagram. Each PLL has a set of PLL_RST, PLL_FBK and PLL_LOCK signals. In order to facilitate the multiply and divide capabilities of the PLL, each PLL has associated dividers. The M divider is used to divide the clock signal, while the 9 Lattice Semiconductor ispGDX2 Family Data Sheet N divider is used to multiply the clock signal. The K divider is used to provide a divided clock frequency of the adjacent PLL. This output can be routed to the global clock net. The V divider is used to provide lower frequency output clocks, while maintaining a stable, high frequency output from the PLL’s VCO circuit. The PLL also has a delay feature that allows the output clock to be advanced or delayed to improve set-up and clock-to-out times for better performance. For more information on the PLL, please refer to Lattice technical note number TN1003, sysCLOCK PLL Design and Usage Guidelines. Figure 6. sysCLOCK PLL PLL_LOCK CLK_OUT CLK_IN Input Clock (M) Divider 1 to 32 Programmable +Delay -------------------- PLL (n) Post-scalar (V) Divider 1, 2, 4, 8, 16, 32 Clock Net Programmable -Delay PLL_RST Clock (K) Divider 2, 4, 8, 16, 32 To Adjacent_PLL From Adjacent_PLL Feedback Divider (N) X 1 to 32 PLL_FBK There are four global clock networks routed to each MRB block. These global clocks, CLK0-3, can either be generated by the PLL circuits or supplied externally. External clock pins can be conﬁgured as single-ended or differential (LVDS) input. Figure 7 illustrates how the sysCLOCK PLL inputs and outputs can be routed to the I/O pins or general routing. Figure 10 shows the clock network for the ispGDX2-256 and Figure 8 shows the clock networks for ispGDX2-128 and ispGDX2-64. The Reset (0) pin from the Control Array of selected GDX Blocks can be programmed to reset the M Divider of the PLLs. This provides a means for generating the reset signal internally. Table 5 details which GDX Block provides reset to the PLLs. Table 5. Internal Reset Input of the PLL (M Divider) PLL0 ispGDX2-256 ispGDX2-128 ispGDX2-64 GDX Block 5A GDX Block 2A GDX Block 0A PLL1 GDX Block 7B — — PLL2 GDX Block 1A GDX Block 0A GDX Block 1B PLL3 GDX Block 3B — — 10 Lattice Semiconductor Figure 7. I/O Pin Connection to the sysCLOCK PLL1 PLL_LOCK ispGDX2 Family Data Sheet CLK_OUT Output Reg/ Latch GCLK_IN Input Clock (M) Divider ÷ 1 to 32 Programmable + Delay -------------------Programmable - Delay PLL (n) Post-scalar (V) Divider ÷ 1, 2, 4, 8, 16, 32 Clock Net Clock (K) Divider ÷ 2, 4, 8, 16, 32 To Adjacent_PLL From Adjacent_PLL Feedback Divider (N) x 1 to 32 Input Reg/ Latch Delay GRP GDX Block PLL_FBK PLL_RST Resetb (0) Control Array (from selected blocks) GCLK_IN 1. Some pins are shared. See Logic Signal Connections Table for details. 11 Lattice Semiconductor Figure 8. ispGDX2-64 CLOCK Network sysIO Interface sysCLOCK CLK0 K(0) PLL (0) ispGDX2 Family Data Sheet Clock Net MRB GCLK/CE0 VREF0 CLK_OUT0 + - Clock Net Reg/ Latch GCLK/CE1 VREF1 CLK_OUT2 + - Clock Net Reg/ Latch CLK2 K(2) PLL (2) Reg/ Latch GCLK/CE2 VREF2 + - Clock Net GCLK/CE3 VREF3 + - Clock Net Reg/ Latch Figure 9. ispGDX2-128 CLOCK Network sysIO Interface sysCLOCK CLK0 K(0) PLL (0) Reg/ Latch Clock Net MRB GCLK/CE0 VREF0 CLK_OUT0 + - Clock Net GCLK/CE1 VREF1 CLK_OUT2 + - Clock Net Reg/ Latch CLK2 K(2) PLL (2) Reg/ Latch GCLK/CE2 VREF2 + - Clock Net GCLK/CE3 VREF3 + - Clock Net Reg/ Latch 12 Lattice Semiconductor Figure 10. ispGDX2-256 CLOCK Network sysIO Interface sysCLOCK CLK0 K(0) PLL (0) ispGDX2 Family Data Sheet Clock Net MRB GCLK/CE0 VREF0 CLK_OUT0 + - Clock Net Reg/ Latch CLK1 K(1) PLL (1) GCLK/CE1 VREF1 CLK_OUT1 + - Clock Net Reg/ Latch CLK2 K(2) PLL (2) GCLK/CE2 VREF2 CLK_OUT2 + - Clock Net Reg/ Latch CLK3 K(3) PLL (3) GCLK/CE3 VREF3 CLK_OUT3 + - Clock Net Reg/ Latch 13 Lattice Semiconductor ispGDX2 Family Data Sheet Operating Modes All the GDX Blocks in the ispGDX2 family can be programmed in four modes: Basic, FIFO only, SERDES only, and FIFO with SERDES mode. In basic mode, the SERDES and FIFO are disabled and the MUX output of the MRB connects to the output register. Inputs are connected to the GRP via the MRB. Figure 11 shows the four different operating modes. Precise detail of the FIFO and SERDES connections is provided in their respective sections. Figure 11. Four Operating Modes of ispGDX2 Devices Basic Mode GRP GDX Block FIFO SERDES sysIO Bank FIFO Mode GRP GDX Block FIFO SERDES sysIO Bank SERDES Mode (FIFO in Flow-through Mode) GRP GDX Block FIFO* SERDES sysIO Bank SERDES and FIFO Mode GRP GDX Block FIFO SERDES sysIO Bank *FIFO held in RESET for SERDES-only mode. FIFO Operations Each GDX Block is associated with a 10-bit wide and 15-word deep (10x15) RAM. This RAM, combined with two address counters and two comparators, is used to implement a FIFO as a “circular queue”. The FIFO has separate clocks, the Read Clock (RCLK) and Write Clock (WCLK), for asynchronous operation. The FIFO has three additional control signals Write Enable, Read Enable and FIFO Reset. Three ﬂags show the status of the FIFO: Empty, Full and Start Read. Each FIFO receives the global Power-on Reset and Reset signals. Figure 12 shows the connections to the FIFO. 14 Lattice Semiconductor Figure 12. ispGDX2 FIFO Signals 10 10 ispGDX2 Family Data Sheet Data Out (DOUT) Data In (DIN) Write Clock (WCLK) Write Enable (WE) Read Clock (RCLK) Read Enable (RE) FIFO 10x15 Full (FULL) Empty (EMPTY) Global Reset (RESETb) Power-on Reset (PORb) FIFO Reset (FIFORSTb) Start Read (STRDb) Read Clock and Read Enable are the same as the Clock and Clock Enable signals of the input registers of the associated MRB. These registers are used to register the FIFO outputs, and in modes that utilize the FIFO are conﬁgured to use the same clock and clock enable signals. The Write Clock is selected from one of the GCLK/CE signals or the RECCLK (Recovered Clock) signal from the associated SERDES. The Write Enable is selected from one of the local MRB product term CLK/CE signals. All FIFO operations occur on the rising edge of the clock although clock polarity of these signals can be programmed. The ﬂags from the FIFO, FULL, EMPTY and STRDb (Start Read) are each fed via a MUX in the MRB to an I/O buffer. The STRDb (half full) signal is used in conjunction with SERDES. STRDb is an active low signal, the signal is inactive (high) on FIFO RESET. After the FIFO reset when the FIFO contains data in ﬁve memory locations, at the following write clock transition the STRDb becomes active (low). Note, if the Read Clocks arrive before writing the sixth location, it may take longer than ﬁve write clocks before the STRDb becomes active. When the FIFO has data in the ﬁrst six locations, at the next write clock transition the STRDb becomes inactive (high). Again, if the Read Clocks arrive before writing the seventh location, the STRDb may stay active for longer than one write clock period, even if the FIFO contains data in less than ﬁve locations. After this event, the STRDb stays inactive until the FIFO is RESET again. STRDb does not become active again even if less than six memory locations are occupied in the FIFO. It is the user’s responsibility to monitor the FULL and EMPTY signals to avoid data underﬂow/overﬂow and to take appropriate actions. Figure 13 shows how the FIFO is connected between the I/O banks and the GDX Blocks in FIFO mode. For more information on the FIFO, please refer to Lattice technical note number TN1020, sysHSI Usage Guidelines. 15 Lattice Semiconductor Figure 13. Operation in FIFO Mode2 GRP GDX Block 1 FIFO ispGDX2 Family Data Sheet SERDES Pre-Assigned Pins Input Reg/ Latch Delay 10 10 DOUT RCLK RE 10 TXD Parallel Data Serial Data Out (SOUT) DIN RXD Parallel Data Serial Data In (SIN) Output Reg/ Latch PT-CLK/CE(0:3) WE GCLK/CE(0:3) Input Reg/ Latch RECCLK WCLK CAL Input Reg/ Latch SYDT Output Reg/ Latch FULL EMPTY Output Reg/ Latch CDRRSTb FIFORSTb Notes: 1. For clarity, only a portion of the GDX Block is shown. 2. Some signals share pins. See Logic Signal Connections tables for details. POR RESETb 16 Lattice Semiconductor ispGDX2 Family Data Sheet High Speed Serial Interface Block (sysHSI Block)1 The High Speed Serial Interface (sysHSI) allows high speed serial data transfer over a pair of LVDS I/O. The ispGDX2 devices have multiple sysHSI Blocks. Each sysHSI Block has two SERDES blocks which contain two main sub-blocks, Transmitter (with a serializer) and Receiver (with a deserializer) including Clock/Data Recovery Circuit (CDR). Each SERDES can be used as a full duplex channel. The two SERDES in a given sysHSI Block share a common clock and must operate at the same nominal frequency. Figure 14 shows the sysHSI Block. Device features support two data coding modes: 10B/12B and 8B/10B (for use with other encoding schemes, see Lattice’s sysHSI application notes). The encoding and decoding of the 10B/12B standard are performed within the device in dedicated logic. For the 8B/10B standard, the symbol boundaries are aligned internally but the encoding and decoding are performed outside the device. Each SERDES block receives a single high speed serial data input stream (with embedded clock) from an input, and provide a low speed 10-bit wide data stream and a recovered clock to the device. For transmitting, the SERDES converts a 10-bit wide low-speed data stream to a single high-speed data stream with embedded clock for output. Additionally, multiple sysHSI Blocks can be grouped together to form a source synchronous interface of between 18 channels. Figure 15 shows the connections of the SERDES block with the FIFO, sysIO block and the MRB. Table 6 provides the descriptions of the SERDES. For more information on the SERDES/CDR, refer to Lattice technical note number TN1020, sysHSI Usage Guidelines. Table 6. SERDES Signal Descriptions Signal CDRRSTb SYDT CAL RXD TXD REFCLK SIN SOUT SS_CLKIN SS_CLKOUT RECCLK CSLOCK I/O I O I Internal Internal Internal I O I O Internal Internal Description Resets the CDR circuit of sysHSI block Symbol alignment detect for sysHSI block Initiates source synchronous calibration sequence Parallel data in for sysHSI block Parallel data out for sysHSI block Reference clock received from the clock tree Serial data input for sysHSI block (LVDS input) Serial data output for sysHSI block (LVDS output) Clock input for source synchronous group Clock output for source synchronous group Recovered clock from encoded data by CDR of sysHSI block Lock output of the PLL associated with sysHSI block 1. “E-Series” does not support sysHSI. 17 Lattice Semiconductor Figure 14. sysHSI Block with SERDES and FIFO sysHSI Block ispGDX2 Family Data Sheet Core Logic SERDES SOUT Serializer TXD 10 RXD SIN De-serializer including CDR RECCLK 10 FIFO GDX Block CSLOCK SS_CLKOUT CSLOCK CSPLL SS_CLKIN GRP CAL Shared Source Synchronous pins drive multiple sysHSI blocks SERDES SOUT Serializer TXD 10 RXD SIN De-serializer including CDR RECCLK 10 FIFO GDX Block REFCLK (0:3) Reference clocks from CLK (0:3) Note: Some pins are shared. See Logic Signal Connections table for details 18 Lattice Semiconductor Figure 15. Operation in SERDES Only Mode1, 2 GRP GDX Block FIFO ispGDX2 Family Data Sheet SERDES Pre-Assigned Pins Input Reg/ Latch Delay 10 DOUT RCLK RE 10 TXD Parallel Data Serial Data Out (SOUT) DIN RXD Parallel Data Serial Data In (SIN) Output Reg/ Latch PT-CLK/CE(0:3) WE GCLK/CE(0:3) Input Reg/ Latch RECCLK WCLK CAL Input Reg/ Latch SYDT Output Reg/ Latch FULL EMPTY Output Reg/ Latch CDRRSTb FIFORSTb Notes: 1. Some pins shared. See Logic Signal Connections table for details. 2. For SERDES only mode programmable bit holds FIFO in reset. Input registers used for DOUT, and RECCLK configured as latches and held in pass through. POR RESETb 19 Lattice Semiconductor Figure 16. Operation in SERDES with FIFO Mode GRP GDX Block FIFO ispGDX2 Family Data Sheet SERDES Pre-Assigned Pins Input Reg/ Latch Delay 10 DOUT RCLK RE 10 TXD Parallel Data Serial Data Out (SOUT) DIN RXD Parallel Data Serial Data In (SIN) Output Reg/ Latch PT-CLK/CE(0:3) WE GCLK/CE(0:3) Input Reg/ Latch RECCLK WCLK CAL Input Reg/ Latch SYDT Output Reg/ Latch FULL EMPTY Output Reg/ Latch CDRRSTb FIFORSTb POR RESETb 20 Lattice Semiconductor ispGDX2 Family Data Sheet IEEE 1149.1-Compliant Boundary Scan Testability All ispGDX2 devices have boundary scan cells and are compliant to the IEEE 1149.1 standard. This allows functional testing of the circuit board on which the device is mounted through a serial scan path that can access all critical logic notes. Internal registers are linked internally, allowing test data to be shifted in and loaded directly onto test nodes, or test node data to be captured and shifted out for veriﬁcation. In addition, these devices can be linked into a board-level serial scan path for more board-level testing. The test access port has its own supply voltage that can operate with LVCMOS3.3, 2.5 and 1.8 standards. sysIO Quick Conﬁguration To facilitate the most efﬁcient board test, the physical nature of the I/O cells must be set before running any continuity tests. As these tests are fast, by nature, the overhead and time that is required for conﬁguration of the I/Os' physical nature should be minimal so that board test time is minimized. The ispGDX2 family of devices allows this by offering the user the ability to quickly conﬁgure the physical nature of the sysIO cells. This quick conﬁguration takes milliseconds to complete, whereas it takes seconds for the entire device to be programmed. Lattice's ispVM™ System programming software can either perform the quick conﬁguration through the PC parallel port, or can generate the ATE or test vectors necessary for a third-party test system. IEEE 1532-Compliant In-System Programming In-system programming of devices provides a number of signiﬁcant beneﬁts including rapid prototyping, lower inventory levels, higher quality and the ability to make in-ﬁeld modiﬁcations. All ispGDX2 devices provide In-System Programming (ISP) capability through their Boundary Scan Test Access Port. This capability has been implemented in a manner that ensures that the port remains compliant to the IEEE 1532 standard. By using IEEE 1532 as the communication interface through which ISP is achieved, designers get the beneﬁt of a standard, well deﬁned interface. The ispGDX2 devices can be programmed across the commercial temperature and voltage range. The PC-based Lattice software facilitates in-system programming of ispGDX2 devices. The software takes the JEDEC ﬁle output produced by the design implementation software, along with information about the scan chain, and creates a set of vectors used to drive the scan chain. The software can use these vectors to drive a scan chain via the parallel port of a PC. Alternatively, the software can output ﬁles in formats understood by common automated test equipment. This equipment can then be used to program ispGDX2 devices during the testing of a circuit board. Security Scheme A programmable security scheme is provided on the ispGDX2 devices as a deterrent to unauthorized copying of the array conﬁguration patterns. Once programmed, this scheme prevents readback of the programmed pattern by a device programmer, securing proprietary designs from competitors. The security scheme also prevents programming and veriﬁcation. The entire device must be erased in order to reset the security scheme. Hot Socketing The ispGDX2 devices are well suited for those applications that require hot socketing capability. Hot socketing a device requires that the device, when powered down, can tolerate active signals on the I/Os and inputs without being damaged. Additionally, it requires that the effects of the powered-down device be minimal on active signals. 21 Lattice Semiconductor ispGDX2 Family Data Sheet Absolute Maximum Ratings 1, 2, 3 ispGDX2C (1.8V) ispGDX2B/V (2.5/3.3V) Supply Voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 2.5V . . . . . . . . . . . . . . . . -0.5 to 5.5V PLL Supply Voltage VCCP . . . . . . . . . . . . . . . . . . . . -0.5 to 2.5V . . . . . . . . . . . . . . . . -0.5 to 5.5V Output Supply Voltage VCCO . . . . . . . . . . . . . . . . . -0.5 to 4.5V . . . . . . . . . . . . . . . . -0.5 to 4.5V JTAG Supply Voltage (VCCJ) . . . . . . . . . . . . . . . . . -0.5 to 4.5V . . . . . . . . . . . . . . . . -0.5 to 4.5V Input or I/O Tristate Voltage Applied 4, 5 . . . . . . . . . -0.5 to 5.5V . . . . . . . . . . . . . . . . -0.5 to 5.5V Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . -65 to 150°C . . . . . . . . . . . . . . . -65 to 150°C Junction Temp. (TJ) with Power Applied . . . . . . . . -55 to 150°C . . . . . . . . . . . . . . . -55 to 150°C 1. Stress above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied (while programming, following the programming speciﬁcations). 2. Compliance with the Lattice Thermal Management document is required. 3. All voltages referenced to GND. 4. Overshoot and undershoot of -2V to (VIH (MAX)+2) volts is permitted for a duration of 3.6V is allowed. Recommended Operating Conditions Symbol VCC Parameter Supply Voltage for 1.8V Devices1 Supply Voltage for 2.5V Devices Supply Voltage for 3.3V Devices Supply Voltage for PLL and sysHSI Blocks, 1.8V Devices1 VCCP Supply Voltage for PLL and sysHSI Blocks, 2.5V Devices Supply Voltage for PLL and sysHSI Blocks, 3.3V Devices Power Supply Voltage for JTAG Programming 1.8V Operation VCCJ TJ (COM) TJ (IND) Power Supply Voltage for JTAG Programming 2.5V Operation Power Supply Voltage for JTAG Programming 3.3V Operation Junction Commercial Operation Junction Industrial Operation Min. 1.65 2.3 3 1.65 2.3 3 1.65 2.3 3 0 -40 Max. 1.95 2.7 3.6 1.95 2.7 3.6 1.95 2.7 3.6 90 105 Units V V V V V V V V V °C °C 1. sysHSI speciﬁcation is valid for VCC and VCCP = 1.7V to 1.9V. Erase Reprogram Speciﬁcations Parameter Erase/Reprogram Cycle Note: Valid over commercial temperature range. Min 1,000 Max — Units Cycles Hot Socketing Speciﬁcations1, 2, 3 Symbol IDK 1. 2. 3. 4. 4 Parameter Input or Tristated I/O Leakage Current Condition 0 ≤ VIN ≤ 3.0V Min — Typ +/-50 Max +/-800 Units μA Insensitive to sequence of VCC and VCCO. However, assumes monotonic rise/fall rates for VCC and VCCO, provided (VIN - VCCO) ≤ 3.6V. LVTTL, LVCMOS only. 0 < VCC ≤ VCC (MAX), 0 < VCCO ≤ VCCO (MAX). IDK is additive to IPU, IPD or IBH. Device defaults to pull-up until fuse circuitry is active. 22 Lattice Semiconductor ispGDX2 Family Data Sheet DC Electrical Characteristics Over Recommended Operating Conditions Symbol IIL, IIH1 IIH 3 Parameter Input or I/O Low Leakage Input High Leakage Current I/O Active Pull-up Current I/O Active Pull-down Current Condition 0 ≤ VIN ≤ (VCCO - 0.2V) (VCCO - 0.2V) < VIN ≤ 3.6V 3.6V < VIN ≤ 5.5V and 3.0V ≤ VCCO ≤ 3.6V 0 ≤ VIN ≤ 0.7 VCCO VIL (MAX) ≤ VIN ≤ VIH (MAX) Min. — — — -30 30 30 -30 — — VCCO * 0.35 — — — — — — Typ. — — — — — — — — — — 8 6 6 Max. 10 30 3 -150 150 — — 150 -150 VCCO * 0.65 — — — — — — Units μA μA mA μA μA μA μA μA μA V pf pf pf IPU IPD IBHLS IBHHS IBHLO IBHLH VBHT C1 C2 C3 Bus Hold Low Sustaining Current VIN = VIL (MAX) Bus Hold High Sustaining Current VIN = 0.7 VCCO Bus Hold Low Overdrive Current Bus Hold Trip Points I/O Capacitance2 Clock Capacitance2 Global Input Capacitance2 VCCO = 3.3V, 2.5V, 1.8V VCC = 1.8V, VIO = 0 to VIH (MAX) VCCO = 3.3V, 2.5V, 1.8V VCC = 1.8V, VIO = 0 to VIH (MAX) VCCO = 3.3V, 2.5V, 1.8V VCC = 1.8V, VIO = 0 to VIH (MAX) 0 ≤ VIN ≤ VIH (MAX) Bus Hold High Overdrive Current 0 ≤ VIN ≤ VIH (MAX) 1. Input or I/O leakage current is measured with the pin conﬁgured as an input or as an I/O with the output driver tri-stated. It is not measured with the output driver active. Bus maintenance circuits are disabled. 2. TA = 25°C, f = 1.0MHz. 3. 5V tolerant inputs and I/Os should be placed in banks where 3.0V ≤ VCCO ≤ 3.6V. The JTAG ports are not included for the 5V tolerant interface. Supply Current Over Recommended Operating Conditions (ispGDX2-256)4 Symbol Description Core Logic Power Supply Current ICC1,2 GPLL/sysHSI Logic Power Supply Current VCC Power Pins Vcc (V) 3.3 2.5 1.8 3.3 2.5 1.8 3.3 ICCP2 GPLL/sysHSI CSPLL Power Supply Current VCCP 2.5 1.8 3.3 ICCO3 Bank Power Supply Current VCCO 2.5 1.8 3.3 ICCJ 1. 2. 3. 4. Min. — — — — — — — — — — — — — — — Typ. 59.6 58.7 60.0 118.7 118.7 117.5 14.7 14.7 17.4 35 35 25 1.5 1.0 800 Max. — — — — — — — — — — — — — — — Units mA mA mA mA mA mA mA mA mA mA mA mA mA mA µA JTAG Programming Current VCCJ 2.5 1.8 64-input switching frequency at 20 MHz, with one GRP fanout. One GPLL with fVCO = 400 MHz and one sysHSI Block (two receivers and two transmitters) at 622 MHz data rate. All 8-bank reference circuit currents, all I/Os in tristate, inputs held at valid logic levels, and bus maintenance circuits disabled. TA = 25°C 23 Lattice Semiconductor ispGDX2 Family Data Sheet sysIO Recommended Operating Conditions VCCO (V)1 Standard LVCMOS 3.3 LVCMOS 2.5 LVCMOS 1.8 LVTTL PCI 3.3 PCI-X AGP-1X SSTL 2 SSTL 3 CTT 3.3 CTT 2.5 HSTL Class I HSTL Class III HSTL Class IV GTL+ LVPECL LVDS BLVDS 2 VREF (V) Max. 3.6 2.7 1.95 3.6 3.6 3.6 3.45 2.7 3.6 3.6 2.7 1.6 1.6 1.6 3.6 3.6 3.6 3.6 Min. 1.15 1.3 1.35 1.35 0.68 0.882 Typ. 1.25 1.5 1.5 1.5 0.75 0.9 0.9 1.0 Max. 1.35 1.7 1.65 1.65 0.9 1.122 - Min. 3.0 2.3 1.65 3.0 3.0 3.0 3.15 2.3 3.0 3.0 2.3 1.4 1.4 1.4 1.4 3.0 2.3 2.3 Typ. 3.3 2.5 1.8 3.3 3.3 3.3 3.3 2.5 3.3 3.3 2.5 1.5 1.5 1.5 3.3 2.5/3.3 2.5/3.3 1. Inputs are independent of VCCO setting. However, VCCO must be set within the valid operating range for one of the supported standards. 2. Software default setting. 24 Lattice Semiconductor ispGDX2 Family Data Sheet sysIO Single Ended DC Electrical Characteristics Over Recommended Operating Conditions Input/Output Standard LVCMOS 3.3 VIL Min (V) -0.3 Max (V) 0.8 Min (V) 2.0 VIH Max (V) 5.5 VOL Max (V) 0.4 0.2 LVTTL -0.3 0.8 2.0 5.5 0.4 0.2 0.4 0.2 LVCMOS 1.8 1, 3 VOH Min (V) 2.4 VCCO - 0.2 2.4 VCCO - 0.2 VCCO - 0.4 VCCO - 0.2 VCCO - 0.4 VCCO -0.4 VCCO - 0.2 0.9 VCCO 0.9 VCCO 0.9 VCCO VCCO - 1.1 VCCO - 0.9 VCCO - 0.62 VCCO - 0.43 VREF + 0.4 VREF + 0.4 VCCO - 0.4 VCCO - 0.4 VCCO - 0.4 n/a IOL2 (mA) IOH2 (mA) 20, 16, 12, -20, -16, -12, 8, 5.33, 4 -8, -5.33, -4 0.1 4 0.1 16, 12, 8, 5.33, 4 0.1 8 0.1 1.5 1.5 1.5 8 16 7.6 15.2 8 8 8 24 48 36 -0.1 -4 -0.1 -16, -12, -8, -5.33, -4 -0.1 -8 -0.1 -0.5 -0.5 -0.5 -8 -16 -7.6 -15.2 -8 -8 -8 -8 -8 n/a LVCMOS 2.5 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 0.7 0.68 0.68 1.08 1.26 1.08 VREF - 0.2 VREF - 0.2 1.7 1.07 1.07 1.5 1.5 1.5 VREF + 0.2 VREF + 0.2 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 0.4 0.4 0.2 0.1 VCCO 0.1 VCCO 0.1 VCCO 0.7 0.5 0.54 0.35 VREF - 0.4 VREF - 0.4 0.4 0.4 0.4 0.6 LVCMOS 1.83 PCI 3.34 PCI -X5 AGP-1X4 SSTL3 class I SSTL3 class II SSTL2 class I SSTL2 class II CTT 3.3 CTT 2.5 HSTL class I HSTL class III HSTL class IV GTL+ 12, 5.33, 4 -12, -5.33, -4 VREF - 0.18 VREF + 0.18 VREF - 0.18 VREF + 0.18 VREF - 0.2 VREF - 0.3 VREF - 0.1 VREF - 0.2 VREF - 0.3 VREF - 0.2 VREF + 0.2 VREF + 0.2 VREF + 0.1 VREF + 0.1 VREF + 0.1 VREF + 0.2 1. Software default setting. 2. The average DC current drawn by I/Os between adjacent bank GND connections, or between the last GND in an I/O bank and the end of the I/O bank, as shown in the logic signals connection table, shall not exceed n*8mA. Where n is the number of I/Os between bank GND connections or between the last GND in a bank and the end of a bank. 3. For 1.8V devices (ispGDX2C) these speciﬁcations are VIL = 0.35 VCC and VIH = 0.65VCC 4. For 1.8V power supply devices these speciﬁcations are VIL = 0.3 * VCC * 3.3/1.8, VIH = 0.5 * VCC * 3.3/1.8 5. For 1.8V power supply devices these speciﬁcations are VIL = 0.35 * VCC * 3.3/1.8 and VIH = 0.5 * VCC * 3.3/1.8 25 Lattice Semiconductor ispGDX2 Family Data Sheet sysIO Differential DC Electrical Characteristics Over Recommended Operating Conditions Parameter Symbol LVDS VINP VINM VTHD IIN VOH VOL VOD ΔVOD VOS ΔVOS IOSD Bus LVDS1 VOH VOL VOD ΔVOD VOS ΔVOS IOSD Output High Voltage for VOP or VOM Output Low Voltage for VOP or VOM Output Voltage Differential Change in VOD Between H and L Output Voltage Offset Change in VOS Between H and L Output Short Circuit Current VOD = 0. Driver Outputs Shorted. |VOP - VOM| /2, RT = 27Ω RT = 27Ω RT = 27Ω |VOP - VOM|, RT = 27Ω — 0.95 240 — 1.1 — — 1.4 1.1 300 — 1.3 — 36 1.80 — 460 27 1.5 27 65 V V mV mV V mV mA Input Voltage Differential Input Threshold Input Current Output High Voltage for VOP or VOM Output Low Voltage for VOP or VOM Output Voltage Differential Output Voltage Offset Change in VOS Between H and L Output Short Circuit Current — 0.2V ≤ VCM ≤ 1.8V Power On RT = 100Ω RT = 100Ω (VOP - VOM), RT = 100Ω (VOP - VOM)/2, RT = 100Ω — VOD = 0V. Driver Outputs Shorted. 0 +/-100 — — 0.9 250 — 1.125 — — — — — 1.38 1.03 350 — 1.25 — — 2.4 — +/-10 1.60 — 450 50 1.375 50 24 V mV µA V V mV mV V mV mA Parameter Description Test Conditions Min. Typ. Max. Units Change in VOD Between High and Low — 1. VOP and VOM are the two outputs of the LVDS output buffer. LVPECL VCCO VIH VIL VOH VOL VDIFF 2 1 DC Parameter Parameter Description Output Supply Voltage Input Voltage High Input Voltage Low Output Voltage High Output Voltage Low Differential Input voltage Min. 3.0 1.49 0.86 1.7 0.96 0.3 Max. 2.72 2.125 2.11 1.27 Min. 3.3 1.49 0.86 1.92 1.06 0.3 Max. 2.72 2.125 2.28 1.43 Min. 3.6 1.49 0.86 2.03 1.25 0.3 Max. 2.72 2.125 2.41 1.57 Units V V V V V V 1. These values are valid at the output of the source termination pack as shown above with 100-ohm differential load only (see Figure 17). The VOH levels are 200mV below the standard LVPECL levels and are compatible with devices tolerant of the lower common mode ranges. 2. Valid for 0.2V ≤ VCM ≤ 1.8V. Figure 17. LVPECL Driver with Three Resistor Pack ispGDX2 LVPECL Buffer 1/4 of Bourns P/N CAT 16-PC4F12 A Rs Zo to LVPECL differential receiver Rs Zo 26 RT=100 RD Lattice Semiconductor ispGDX2 Family Data Sheet ispGDX2V/B/C, ispGDX2EV/EB/EC External Switching Characteristics Over Recommended Operating Conditions -3 Parameter Output Paths tPD tPD_SEL tCO tOPS tOPH tOPCES tOPCEH tOPRSTO Input Paths tIPS tIPSZ tIPH tIPHZ tIPCES tIPCEH tIPRSTO tOECO tOES tOEH tOECES tOECEH tGOE/DIS tTOE/DIS tEN/DIS tRW tCW tGW fMAX (Ext) fMAX (Tog, No PLL) Set-up Time Before Global Clock Set-up Time Before Global Clock (Zero Hold Time) Hold Time After Global Clock Hold Time After Global Clock (Zero Hold Time) PT Clock Enable Setup Time Before Global Clock PT Clock Enable Hold Time After Global Clock External Reset Pin to Output Delay Global Clock to Output Enabled Pin Output Enable Register Set-up Time Before Global Clock Hold Time After Global Clock PT Clock Enable Setup Time Before Global Clock PT Clock Enable Hold Time After Global Clock Global OE Input to Output Enable/Disable Test OE Input to Output Enable/Disable Input to Output Enable/Disable Width of Reset Pulse Clock Width Clock Width Clock Frequency with External Feedback 1/(tOPS + tCO) Clock Frequency Maximum Toggle (No PLL) 0.5 2.0 1.0 0.0 3.1 0.0 — — 1.6 0.0 3.5 0.0 — — — 2.5 1.3 1.5 — — — — — — — — 5.6 4.2 — — — — 3.5 5.2 5.2 — — — 204 360 0.5 2.0 1.0 0.0 3.1 0.0 — — 1.6 0.0 3.5 0.0 — — — 2.5 1.5 1.6 — — — — — — — — 6.5 4.5 — — — — 3.8 5.5 5.5 — — — 196 330 0.5 2.0 1.0 0.0 3.1 0.0 — — 2.0 0.0 4.1 0.0 — — — 2.5 1.6 1.6 — — — — — — — — 7.5 5.5 — — — — 4.5 6.2 6.2 — — — 192 300 0.9 3.0 1.7 0.0 5.1 0.0 — — 3.4 0.0 6.9 0.0 — — — 4.1 2.7 2.7 — — — — — — — — 12.5 9.1 — — — — 7.5 10.3 10.3 — — — 119 180 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz Data From Input Pin to Output Pin Data From Global Select Pin to Output Pin Global Clock to Output Set-up Time Before Global Clock Hold Time After Global Clock PT Clock Enable Setup Time Before Global Clock PT Clock Enable Hold Time After Global Clock External Reset Pin to Output Delay — — — 2.0 0.0 3.0 0.0 — 3.0 2.8 2.9 — — — — 5.3 — — — 2.0 0.0 3.0 0.0 — 3.2 3.0 3.1 — — — — 6.0 — — — 2.0 0.0 4.1 0.0 — 3.5 3.3 3.2 — — — — 6.0 — — — 3.0 0.0 6.9 0.0 — 5.0 4.7 5.4 — — — — 10.0 ns ns ns ns ns ns ns ns Description Min. Max. Min. -32 Max. Min. -35 Max. Min. -5 Max. Units Output Enable Paths Clock and Reset Paths 27 Lattice Semiconductor ispGDX2 Family Data Sheet ispGDX2V/B/C, ispGDX2EV/EB/EC External Switching Characteristics Over Recommended Operating Conditions -3 Parameter Description Min. — Max. 360 Min. — fMAX Clock Frequency Maximum Toggle (Tog, PLL) (With PLL) -32 Max. 330 Min. — -35 Max. 300 Min. — -5 Max. Units 180 MHz Timing v.2.2 28 Lattice Semiconductor ispGDX2 Family Data Sheet Timing Model The task of determining the timing through the ispGDX2 family is relatively simple. The timing model provided in Figure 18 shows the speciﬁc delay paths. Once the implementation of a given function is determined either conceptually or from the software report ﬁle, the delay path of the function can easily be determined from the timing model. The Lattice design tools report the timing delays based on the same timing model for a particular design. Note that the internal timing parameters are given for reference only, and are not tested. The external timing parameters are tested and guaranteed for every device. Figure 18. ispGDX2 Timing Model Diagram (I/O Cell) TOE/ GOE t TOE_IN t GOE_IN t IOI TOE path GOE path from GRP t PTOE to sysHSI (REFCLK) to FIFO (WE) GCLK/ GCLKEN tCLK_IN tCLKEN_IN t IOI t GCLK tPLL_DELAY t PTCLKEN from GRP t PTCLK t OEBYPASS tPLL_SEC_DELAY OE Reg. D Q to sysHSI/FIFO (Global Reset) GSR to FIFO (WCLK) t SR_IN t IOI from GRP t PTSR CE S/R from sysHSI (SOUT) from sysHSI/FIFO (Flags) from sysHSI (SSCLKOUT) from GRP tPTSEL from Adjacent Cells (Output) t OPAC from GRP t MUXPD t MUXSEL t OPBYPASS t HSISOUT t HSIFIFOFLAG Output Delays t BUF t EN t DIS t IOO GSEL t SEL_IN t IOI t HSISSCLKOUT OUT Output Reg. D Q CE from Adjacent Cells (Input) from FIFO (DOUT) from sysHSI (RECCLK, SYDT) from PLL (PLL Output) t IN t IOI t INDIO tIPBYPASS to sysHSI/FIFO (SIN, Control, DIN, I/O Reset, SSCLKIN) to sysHSI (TXD) t IPAC S/R t FIFODATAOUT to Adjacent Cells (Output) t HSIOUT Input Reg. S/R t PLLOUT CE IN D Q t ROUTEGRP to GRP to Adjacent Cells (Input) Italicized parameters are optional. Model Version 1.6.7 to FIFO (REN) to FIFO (RCLK) 29 Lattice Semiconductor ispGDX2 Family Data Sheet Figure 19. ispGDX2 Timing Model Diagram (with sysHSI and FIFO Receive Mode) to I/O Cell (RECCLK) from I/O Cell (SIN) tHSISIN Serial Data In sysHSI (RXD) FIFO Data Out (RXD) Recovered Clock tFIFODATAIN Data In tFIFOWCLK Write CLK Data Out to I/O Cell (DOUT) HSI Controls HSI Flags from I/O Cell (Control) tHSICTRLCAL CAL CSLOCK to I/O Cell (Output Path Flag) to I/O Cell (SYDT and Output Path Flags) FIFO Flags to I/O Cell (Output Path Flags) SYDT from I/O Cell (SSCLKIN) Source Synchronous Clock FULL, EMPTY Read Clock Read Enable tHSISSCLKIN from I/O Cell (RCLK) from I/O Cell (REFCLK) tHSIREFCLK Reference Clock RESET from I/O Cell (RE) tFIFORCLK tFIFOREN RESET from I/O Cell (Global RESET) from I/O Cell (I/O RESET) tHSIFIFORST Figure 20. ispGDX2 Timing Model Diagram (with sysHSI Transmit Mode) sysHSI (TXD) from I/O Cell (TXD) tHSITXDATA Data In Serial Data Out to I/O Cell (SOUT) from I/O Cell (REFCLK) tHSIREFCLK Reference Clock Source Synchronous Clock to I/O Cell (SSCLKOUT) 30 Lattice Semiconductor Figure 21. ispGDX2 Timing Model Diagram (in FIFO Only Mode) from I/O Cell (DIN) from I/O Cell (WCLK) from I/O Cell (WE) ispGDX2 Family Data Sheet tFIFODATAIN Data In FIFO Data Out to I/O Cell (DOUT) tFIFOWCLK Write Clock Write Enable tFIFOWEN FIFO Flags FULL, EMPTY to I/O Cell (Output Path Flags) from I/O Cell (RCLK) from I/O Cell (RE) tFIFORCLK Read Clock Read Enable tFIFOREN RESET from I/O Cell (Global RESET) from I/O Cell (I/O RESET) tHSIFIFORST 31 Lattice Semiconductor ispGDX2 Family Data Sheet Sample External Timing Calculations The following equations illustrate the task of determining the timing through the ispGDX2 family. These are only a sample of equations to calculate the timing through the ispGDX2. Figure 18 shows the speciﬁc delay paths and the Internal Timing Parameters table provides the parameter values. Note that the internal timing parameters are given for reference only and are not tested. The external timing parameters are tested and guaranteed for every device. Data from global select pin to output pin: tPD_SEL = tSEL_IN + tMUXSEL + tOPBYPASS + tBUF Global clock to output: tCO = tCLK_IN + tGCLK + tOPCOi + tBUF Input register or latch set-up time before global clock: tIPS = tIN + tIPS - (tCLK + tGCLK) Input register or latch hold time after global clock: tIPH = (tCLK_IN + tGCLK) + tIPHi - tIN Data from product term select to output pin: tPD_PTSEL = tIN + tIPBYPASS + tROUTEGRP + tPTSEL + tMUXSEL + tOPBYPASS + tBUF Product term clock to output: tCO_PT = tIN + tIPBYPASS + tROUTEGRP + tPTCLK + tOPCOi + tBUF Input register or latch set-up time before product term clock: tIPS_PT = tIN + tIPSi_PT - (tIN + tIPBYPASS + tROUTEGRP + tPTCLK) Input register or latch hold time after product term clock: tIPH_PT = (tIN + tIPBYPASS + tROUTEGRP + tPTCLK) + tIPHi - tIN Global OE input to output enable/disable: tGOE/DIS = tGOE_IN + tOEBYPASS + tEN External reset pin to output delay: tOPRSTO = tSR_IN + tOPASROi + tBUF 32 Lattice Semiconductor ispGDX2 Family Data Sheet ispGDX2V/B/C, ispGDX2EV/EB/EC Internal Timing Parameters1 Over Recommended Operating Conditions -3 Parameter Input/Output Delays tBUF tCLK_IN tCLKEN_IN tDIS tEN tGOE_IN tIN tSEL_IN tSR_IN tTOE_IN Output Buffer Delay Global Clock Input Delay Global Clock Enable Input Delay Output Disable Delay Output Enable Delay Global Output Enable Path Delay Input Pin Delay Global MUX Select Input Delay Global Set/Reset Path Delay Test Output Enable Path Delay Input Path Adjacent I/O Cell Delay (Shift Register) Output Path Adjacent I/O Cell Delay (Shift Register) MUX Data Path Delay MUX Select Path Delay FIFO Output to I/O Block Delay Clock Tree Delay HSI/FIFO Flag to I/O Block Delay HSI Output to I/O Cell Block Delay HSI Source Synchronous Clock to I/O Cell Block Delay PLL Delay Increment Clock AND Array Delay Clock Enable AND Array Delay OE AND Array Delay Select AND Array Delay Set/Reset AND Array Delay Global Routing Pool Delay Asynchronous Set/Reset to Output Asynchronous Set/Reset Recovery Register/Latch Bypass Delay Register Clock Enable Hold Time Register Clock Enable Setup Time (Global Clock Enable) Register Clock Enable Setup Time (Product Term Clock Enable) Register Clock to Output Delay Register Hold Time — — — — — — — — — — 0.80 1.00 1.80 1.80 1.50 2.00 0.40 1.60 2.00 3.70 — — — — — — — — — — 0.80 1.00 1.80 1.80 1.80 2.00 0.40 1.60 2.70 3.70 — — — — — — — — — — 0.80 1.00 1.80 2.50 2.50 2.00 0.40 1.60 2.70 3.70 — — — — — — — — — — 1.14 1.67 3.00 4.17 4.17 3.33 0.57 2.29 4.50 6.17 ns ns ns ns ns ns ns ns ns ns Description Min. Max. -32 Min. Max. -35 Min. Max. Min. -5 Max. Units Shift Register and MUX Delays tIPAC tOPAC tMUXPD tMUXSEL tFIFODATAOUT tGCLK tHSIFIFOFLAG tHSIOUT tHSISSCLKOUT tPLL_DELAY tPTCLK tPTCLKEN tPTOE tPTSEL tPTSR tROUTEGRP tOPASROi tOPASRRi tOPBYPASS tOPCEHi tOPCESi tOPCESi_PT tOPCOi tOPHi — — — — — — — — — — — — — — — — — — — 1.30 1.10 1.00 — 0.80 0.80 1.30 0.90 0.40 0.00 0.40 0.00 0.00 0.00 0.33 2.20 2.10 2.40 1.70 1.40 0.90 2.50 2.50 0.00 — — — 0.70 — — — — — — — — — — — — — — — — — — — — 1.30 1.10 1.00 — 0.80 0.80 1.30 0.90 0.40 0.00 0.40 0.00 0.00 0.00 0.33 2.20 2.10 2.40 1.70 1.40 0.90 2.50 2.50 0.20 — — — 0.90 — — — — — — — — — — — — — — — — — — — — 1.30 1.10 2.10 — 0.80 0.80 1.30 0.90 0.40 0.00 0.40 0.00 0.00 0.00 0.33 2.20 2.10 2.40 1.70 2.70 0.90 2.50 2.50 0.50 — — — 1.00 — — — — — — — — — — — — — — — — — — — — 2.17 1.83 3.50 — 1.33 1.33 2.17 1.29 0.57 0.00 0.67 0.00 0.00 0.00 0.33 3.67 3.50 4.00 2.83 4.50 1.29 4.17 4.17 0.71 — — — 1.67 — ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns AND Arrays and Routing Delays Register/Latch Delays, Output Paths 33 Lattice Semiconductor ispGDX2 Family Data Sheet ispGDX2V/B/C, ispGDX2EV/EB/EC Internal Timing Parameters1 (Continued) Over Recommended Operating Conditions -3 Parameter tOPLGOi tOPLHi tOPLPDi tOPLSi tOPLSi_PT tOPSi tOPSi_PT tOPSRPWi tIPASROi tIPASRRi tIPBYPASS tIPCEHi tIPCESi tIPCESi_PT tIPCOi tIPHi tIPLGOi tIPLHi tIPLPDi tIPLSi tIPLSi_PT tIPSi tIPSi_PT tIPSRPWi OE Paths tOEASROi tOEASRRi tOEBYPASS tOECEHi tOECESi tOECESi_PT tOECOi tOEHi tOELGOi tOELHi tOELPDi Asynchronous Set/Reset to Output Asynchronous Set/Reset Recovery Register/Latch Bypass Delay Register Clock Enable Hold Time Register Clock Enable Setup Time (Global Clock Enable) Register Clock Enable Setup Time (Product Term Clock Enable) Register Clock to Output Delay Register Hold Time Latch Gate to Output Delay Latch Hold Time Latch Propagation Delay (Transparent Mode) — — — 1.30 1.20 1.50 — 0.40 — 0.40 — 2.50 2.50 0.00 — — — 1.30 — 1.60 — 0.30 — — — 1.30 1.20 1.50 — 0.40 — 0.40 — 2.50 2.50 0.00 — — — 1.30 — 1.60 — 0.30 — — — 0.80 1.20 2.10 — 0.40 — 0.40 — 2.50 2.50 0.00 — — — 1.60 — 1.60 — 0.30 — — — 1.33 2.00 3.50 — 0.67 — 0.67 — 4.17 4.17 0.00 — — — 2.67 — 2.67 — 0.50 ns ns ns ns ns ns ns ns ns ns ns Description Latch Gate to Output Delay Latch Hold Time Latch Propagation Delay (Transparent Mode) Latch Setup Time (Global Gate) Latch Setup Time (Product Term Gate) Register Setup Time (Global Clock) Register Setup Time (Product Term Clock) Asynchronous Set/Reset Pulse Width Asynchronous Set/Reset to Output Asynchronous Set/Reset Recovery Register/Latch Bypass Delay Register Clock Enable Hold Time Register Clock Enable Setup Time (Global Clock Enable) Register Clock Enable Setup Time (Product Term Clock Enable) Register Clock to Output Delay Register Hold Time Latch Gate to Output Delay Latch Hold Time Latch Propagation Delay (Transparent Mode) Latch Setup Time (Global Term) Latch Setup Time (Product Term Gate) Register Setup Time (Global Clock) Register Setup Time (Product Term Clock) Asynchronous Set/Reset Pulse Width Min. — 0.80 — 1.20 1.00 1.20 1.00 — — — — 1.30 1.10 1.10 — 0.00 — 0.00 — 1.50 1.50 1.50 1.50 — Max. 1.00 — 0.30 — — — — 2.50 1.00 2.50 0.00 — — — 0.80 — 1.00 — 0.30 — — — — 2.50 — 0.80 — 1.20 1.00 1.20 1.00 — — — — 1.30 1.10 1.10 — 0.00 — 0.00 — 1.50 1.50 1.50 1.50 — -32 Min. Max. 1.00 — 0.30 — — — — 2.50 1.00 2.50 0.00 — — — 1.00 — 1.00 — 0.30 — — — — 2.50 — 0.80 — 1.20 1.00 1.20 1.00 — — — — 1.30 1.10 1.10 — 0.00 — 0.00 — 1.50 1.50 1.50 1.50 — -35 Min. Max. 1.00 — 0.30 — — — — 2.50 1.70 2.50 0.00 — — — 1.00 — 1.00 — 0.30 — — — — 2.50 Min. — 1.33 — 2.00 1.67 2.00 1.67 — — — — 2.17 1.83 1.83 — 0.00 — 0.00 — 2.50 2.50 2.50 2.50 — -5 Max. Units 1.67 — 0.50 — — — — 4.17 2.83 4.17 0.00 — — — 1.67 — 1.67 — 0.50 — — — — 4.17 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Register/Latch Delays, Input Paths 34 Lattice Semiconductor ispGDX2 Family Data Sheet ispGDX2V/B/C, ispGDX2EV/EB/EC Internal Timing Parameters1 (Continued) Over Recommended Operating Conditions -3 Parameter tOELSi tOELSi_PT tOESi tOESi_PT tOESRPWi Description Latch Setup Time (Global Gate) Latch Setup Time (Product Term Gate) Register Setup Time (Global Clock) Register Setup Time (Product Term Clock) Asynchronous Set/Reset Pulse Width Min. 1.40 1.00 1.00 1.00 — Max. — — — — 2.50 -32 Min. 1.40 1.00 1.00 1.00 — Max. — — — — 2.50 -35 Min. 1.40 1.00 1.40 1.00 — Max. — — — — 2.50 Min. 2.33 1.67 2.33 1.67 — -5 Max. Units — — — — 4.17 ns ns ns ns ns Timing v.2.2 1. Internal parameters are not tested and are for reference only. Refer to the timing model in this data sheet for details. 2. tPLL_DELAY is the unit of increment by which the clock signal can be incremented. The PLL can adjust the clock signal by up to t RANGE (as given in the sysCLOCK PLL Timing section) in either direction in steps of size tPLL_DELAY. 35 Lattice Semiconductor ispGDX2 Family Data Sheet ispGDX2V/B/C, ispGDX2EV/EB/EC Timing Adjusters -3 Parameter Optional Adders tINDIO tPLL_SEC_DELAY tIOO Output Adjusters Slow Slew LVTTL_out LVCMOS_18_4mA_out LVCMOS_18_5.33mA_out LVCMOS_18_8mA_out LVCMOS_18_12mA_out LVCMOS_25_4mA_out LVCMOS_25_5.33mA_out LVCMOS_25_8mA_out LVCMOS_25_12mA_out LVCMOS_25_16mA_out LVCMOS_33_4mA_out LVCMOS_33_5.33mA_out LVCMOS_33_8mA_out LVCMOS_33_12mA_out LVCMOS_33_16mA_out LVCMOS_33_20mA_out AGP_1X_out BLVDS_out CTT25_out CTT33_out GTL+_out HSTL_I_out HSTL_III_out HSTL_IV_out Using Slow Slew (LVTTL and LVCMOS Outputs Only) Using 3.3V TTL Drive Using 1.8V CMOS Standard, 4mA Drive Using 1.8V CMOS Standard, 5.33mA Drive Using 1.8V CMOS Standard, 8mA Drive Using 1.8V CMOS Standard, 12mA Drive Using 2.5V CMOS Standard, 4mA Drive Using 2.5V CMOS Standard, 5.33mA Drive Using 2.5V CMOS Standard, 8mA Drive Using 2.5V CMOS Standard, 12mA Drive Using 2.5V CMOS Standard, 16mA Drive Using 3.3V CMOS Standard, 4mA Drive Using 3.3V CMOS Standard, 5.33mA Drive Using 3.3V CMOS Standard, 8mA Drive Using 3.3V CMOS Standard, 12mA Drive Using 3.3V CMOS Standard, 16mA Drive Using 3.3V CMOS Standard, 20mA Drive Using AGP 1x Standard Using Bus Low Voltage Differential Signaling (BLVDS) Using CTT 2.5v Using CTT 3.3v Using GTL+ Using HSTL 2.5V, Class I Using HSTL 2.5V, Class III Using HSTL 2.5V, Class IV — — — — — — — — — — — — — — — — — — — — — — — — — 0.90 1.20 0.30 0.30 0.00 0.00 1.20 1.00 0.40 0.40 0.40 1.20 1.20 0.80 0.60 0.60 0.30 0.60 1.00 0.30 0.20 0.50 0.50 0.60 0.60 — — — — — — — — — — — — — — — — — — — — — — — — — 0.90 1.20 0.30 0.30 0.00 0.00 1.20 1.00 0.40 0.40 0.40 1.20 1.20 0.80 0.60 0.60 0.30 0.60 1.00 0.30 0.20 0.50 0.50 0.60 0.60 — — — — — — — — — — — — — — — — — — — — — — — — — 0.90 1.20 0.30 0.30 0.00 0.00 1.20 1.00 0.40 0.40 0.40 1.20 1.20 0.80 0.60 0.60 0.30 0.60 1.00 0.30 0.20 0.50 0.50 0.60 0.60 — — — — — — — — — — — — — — — — — — — — — — — — — 0.90 1.20 0.30 0.30 0.00 0.00 1.20 1.00 0.40 0.40 0.40 1.20 1.20 0.80 0.60 0.60 0.30 0.60 1.00 0.30 0.20 0.50 0.50 0.60 0.60 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Input Delay Secondary PLL Output Delay — — 1.50 1.30 — — 1.50 1.30 — — 1.50 1.30 — — 2.50 1.30 ns ns Description Min. Max. -32 Min. Max. -35 Min. Max. Min. -5 Max. Units 36 Lattice Semiconductor ispGDX2 Family Data Sheet ispGDX2V/B/C, ispGDX2EV/EB/EC Timing Adjusters (Continued) -3 Parameter LVPECL_out LVDS_out PCI_out PCI_X_out SSTL2_I_out SSTL2_II_out SSTL3_I_out SSTL3_II_out tIOI Input Adjusters LVTTL_in LVCMOS_18_in LVCMOS_25_in LVCMOS_33_in AGP_1X_in BLVDS_in CTT25_in CTT33_in GTL+_in HSTL_I_in HSTL_III_in HSTL_IV_in LVPECL_in LVDS_in PCI_in PCI_X_in SSTL2_I_in SSTL2_II_in SSTL3_I_in SSTL3_II_in Using 3.3V TTL Using 1.8V CMOS Using 2.5V CMOS Using 3.3V CMOS Using AGP 1x Using Bus Low Voltage Differential Signaling (BLVDS) Using CTT 2.5V Using CTT 3.3V Using GTL+ Using HSTL 2.5V, Class I Using HSTL 2.5V, Class III Using HSTL 2.5V, Class IV Using Differential Signaling (LVPECL) Using Low Voltage Differential Signaling (LVDS) Using PCI Using PCI-X Using SSTL 2.5V, Class I Using SSTL 2.5V, Class II Using SSTL 3.3V, Class I Using SSTL 3.3V, Class II — — — — — — — — — — — — — — — — — — — — 0.00 0.00 0.00 0.00 1.00 0.50 1.00 1.00 0.50 0.50 0.60 0.60 0.00 0.50 1.00 1.00 0.50 0.50 0.60 0.60 — — — — — — — — — — — — — — — — — — — — 0.00 0.00 0.00 0.00 1.00 0.50 1.00 1.00 0.50 0.50 0.60 0.60 0.00 0.50 1.00 1.00 0.50 0.50 0.60 0.60 — — — — — — — — — — — — — — — — — — — — 0.00 0.00 0.00 0.00 1.00 0.50 1.00 1.00 0.50 0.50 0.60 0.60 0.00 0.50 1.00 1.00 0.50 0.50 0.60 0.60 — — — — — — — — — — — — — — — — — — — — 0.00 0.00 0.00 0.00 1.00 0.50 1.00 1.00 0.50 0.50 0.60 0.60 0.00 0.50 1.00 1.00 0.50 0.50 0.60 0.60 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Timing v.2.2 -32 Max. 0.30 0.80 0.60 0.60 0.30 0.50 0.20 0.40 Min. — — — — — — — — Max. 0.30 0.80 0.60 0.60 0.30 0.50 0.20 0.40 -35 Min. — — — — — — — — Max. 0.30 0.80 0.60 0.60 0.30 0.50 0.20 0.40 Min. — — — — — — — — -5 Max. 0.30 0.80 0.60 0.60 0.30 0.50 0.20 0.40 Units ns ns ns ns ns ns ns ns Description Using LVPECL Differential Signaling Using Low Voltage Differential Signaling (LVDS) Using PCI Standard Using PCI-X Standard Using SSTL 2.5V, Class I Using SSTL 2.5V, Class II Using SSTL 3.3V, Class I Using SSTL 3.3V, Class II Min. — — — — — — — — 37 Lattice Semiconductor ispGDX2 Family Data Sheet ispGDX2V/B/C, ispGDX2EV/EB/EC FIFO Internal Timing -3 Parameter Routing Delays tFIFODATAIN tFIFORCLK tFIFOREN tFIFOWCLK tFIFOWEN Core Delays tFIFOCLKSKEW Global Read Clock to Write Clock Skew tFIFOEMPTY tFIFOFULL tFIFORCEH tFIFORCES tFIFORCLKO tFIFORSTO tFIFORSTPW tFIFORSTR tFIFOSTRD tFIFOTHRU tFIFOWCEH tFIFOWCES tFIFOWCLKH tFIFOWCLKS Read Clock to Empty Flag Delay Write Clock to Full Flag Delay Read Clock Hold after Read Clock Enable Time Read Clock Setup before Read Clock Enable Time Read Clock to FIFO Out Delay Reset to Output Delay Reset Pulse Width Reset Recovery Time Write Clock to Start Read Flag Delay Flow Through Delay Write Clock hold after Write Clock Enable Time Write Clock Setup before Write Clock Enable Time Write Data Hold after Write Clock Time Write Data Setup before Write Clock Time — — — — — — — — — — — — — — — 2.00 1.30 1.30 0.00 1.50 0.50 0.70 2.00 1.20 0.00 0.00 2.00 0.00 0.50 1.00 — — — — — — — — — — — — — — — 2.00 1.80 1.80 0.00 1.50 0.50 0.70 2.00 1.50 0.00 0.00 2.00 0.00 0.50 1.00 — — — — — — — — — — — — — — — 2.00 1.80 1.80 0.00 1.50 0.50 0.70 2.00 2.00 0.00 0.00 2.00 0.00 0.70 1.00 — — — — — — — — — — — — — — — 3.33 3.00 3.00 0.00 2.50 0.83 1.17 3.33 3.33 0.00 0.00 3.33 0.00 1.17 1.67 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Timing v.2.2 -32 Min. Max. — — — — — — 0.00 0.00 0.00 0.00 0.00 0.00 -35 Min. Max. — — — — — — 0.00 0.00 0.00 0.00 0.00 0.00 -5 Min. Max. — — — — — — 0.00 0.00 0.00 0.00 0.00 0.00 Units ns ns ns ns ns ns Description FIFO Input Delay Read Clock Input Delay Read Clock Enable Input Delay Write Clock Input Delay Write Clock Enable Input Delay Min. Max. — — — — — — 0.00 0.00 0.00 0.00 0.00 0.00 tFIFODATAOUT FIFO Output to I/O Core Delay 38 Lattice Semiconductor ispGDX2 Family Data Sheet sysHSI Block Timing Figure 22 provides a graphical representation of the SERDES receiver input requirements. It provides guidance on a number of input parameters, including signal amplitude and rise time limits, noise and jitter limits, and P and N input skew tolerance. Figure 22. Receive Data Eye Diagram Template (Differential) Bit Time V THD 200 mV Differential +/- 100 mV Single Ended jt TH jtTH : Optimum Threshold Crossing Jitter eo SIN jtTH The data pattern eye opening at the receive end of a link is considered the ultimate measure of received signal quality. Almost all detrimental characteristics of a transmit signal and the interconnection link design result in eye closure. This combined with the eye-opening limitations of the line receiver can provide a good indication of a link’s ability to transfer error-free data. Signal jitter is of special interest to system designers. It is often the primary limiting characteristic of long digital links and of systems with high noise level environments. An interesting characteristic of the clock and data recovery (CDR) portion of the ispGDX2 SERDES receiver is its ability to ﬁlter incoming signal jitter that is below the clock recovery PLL bandwidth. For signals with high levels of low frequency jitter, the receiver can detect incoming data error free, with eye openings signiﬁcantly less than that shown in Figure 22. sysHSI Block AC Speciﬁcations Operating Frequency Ranges Symbol fCLK Description Reference Clock Frequency Mode SS:CAL 10B12B 8B10B SS:CAL fSIN2 fSOUT2 Serial Input 10B12B 8B10B Serial Out LVDS with eoSIN with eoSIN with eoSIN CL = 5 pF, RL = 100 Ohms, fCLK with no jitter Test Condition Min. 50 33 40 400 400 400 400 Max. 200 67 80 8001 8001 8001 8001 Units MHz MHz MHz Mbps Mbps Mbps Mbps 1. fSIN (8B/10B and 10B/12B) 800Mbps limit applicable only to the fastest speed grade. Limit is 700Mbps for the lower speed grade. 2. fSIN and fSOUT speeds are supported at VCC and VCCP at 1.7V to 1.9V for ispGDX2C devices. 39 Lattice Semiconductor LOCKIN Time Symbol tSCLOCK tCDRLOCK tSYNC tCAL tSUSYNC tHDSYNC Description CSPLL Lock Time CDRPLL Lock-in Time SyncPat Length CAL Duration SyncPat Set-up Time to CAL SyncPat Hold Time from CAL Mode All SS 10B12B 8B10B SS SS SS SS ispGDX2 Family Data Sheet Condition After input is stabilized With SS mode sync pattern With 10B12B sync pattern With 8B10B idle pattern Min. Max. 25 1024 1024 960 Units μS tRCP1 tRCP tRCP tRCP tRCP tRCP tRCP 1200 1100 50 50 1. REFCLK clock period. REFCLK and SS_CLKIN Timing Symbol tDREFCLK tJPPREFCLK tPWREFCLK tRFREFCLK Description Frequency Deviation Between TX REFCLK and CDRX REFCLK on One Link REFCLK, SS_CLKIN Peak-to-Peak Period Jitter REFCLK, SS_CLKIN Pulse Width, (80% to 80% or 20% to 20%). REFCLK, SS_CLKIN Rise/Fall Time (20% to 80% or 80% to 20%) Mode 8B10B/ 10B12B All All All Random Jitter 1 2 Condition Min. -100 Max. 100 0.01 Units ppm UIPP ns ns Serializer Timing2 Symbol tJPPSOUT tJPP8B10B tRFSOUT tCOSOUT tSKTX tCKOSOUT Description SOUT Peak-to-Peak Output Data Jitter SOUT Peak-to-Peak Random Jitter SOUT Peak-to-Peak Deterministic Jitter SOUT Output Data Rise/Fall Time (20%, 80%) REFCLK to SOUT Delay Skew of SOUT with Respect to SS_CLKOUT SS_CLKOUT to bit0 of SOUT Mode All 8B10B 8B10B LVDS BLVDS SS/8B10B 10B12B SS SS All All Note 3 Note 3 2Bt1 + 2 1Bt1 + 2 Condition fCLK with no jitter 800 Mbps w/K28.7800 Mbps w/K28.5+ Min. Max. 0.25 130 160 700 900 2Bt1 +10 1Bt1 +10 250 2Bt1 - tSKTX 2Bt1 + tSKTX 1.5 1.0 Units UIPP ps ps ps ps ns ns ps ns ns ns tHSITXDDATAS TXD Data Setup Time tHSITXDDATAH TXD Data Hold Time 1. Bt: Bit Time Period. High Speed Serial Bit Time. 2. The SIN and SOUT jitter speciﬁcations listed above are under the condition that the clock tree that drives the REFCLK to sysHSI Block is in sysCLOCK PLL BYPASS mode. 3. Internal timing for reference only. 40 Lattice Semiconductor Deserializer Timing Symbol fDSIN eoSIN ber tHSIOUTVALIDPRE tHSIOUTVALIDPOST tDSIN Description SIN Frequency Deviation from REFCLK SIN Eye Opening Tolerance Bit Error Rate RXD, SYDT Valid Time Before RECCLK Falling Edge RXD, SYDT Valid Time After RECCLK Falling Edge Bit 0 of SIN Delay to RXD Valid at RECCLK Falling edge Mode 8B10B/ 10B12B All All All All All ispGDX2 Family Data Sheet Conditions Min. -100 Max. 100 Units ppm UIPP Notes 1, 2 0.45 10 -12 Bits ns ns Note 3 Note 3 tRCP/2 - 0.7 tRCP/2 - 0.7 1.5 tRCP + 4.5Bt + 2 1.5 tRCP + 4.5Bt + 10 ns 1. Eye opening based on jitter frequency of 100KHz. 2. Lower frequency operation assumes maximum eye closure of 800ps. 3. Internal timing for reference only. Lock-in Timing CDRX_SS LOCK-IN (DE-SKEW) TIMING SIN CAL MIN. 1200 SYNCPAT MIN. 1100 LS CYCLE DATA (SERIAL ) tSUSYNC SYDT RXD(0:7) SYNCPAT TRAINING SEQUENCE tHDSYNC DATA (PARALLEL) SS MODE DATA TRANSFER CDR_10B12B LOCK-IN TIMING SIN SYDT RXD(0:9) SYNCPAT DATA (PARALLEL) 1024 SYNCPAT DATA (SERIAL ) 41 Lattice Semiconductor Lock-in Timing (Continued) CDR_8B10B LOCK-IN TIMING SIN SYDT RXD(0:9) Idle Pattern 240 Idle Pattern(960 TRCP) ispGDX2 Family Data Sheet DATA (SERIAL ) DATA (PARALLEL) SYDT Timing SYDT TIMING FOR CDRX_10B12B RECCLK SYDT RXD(0:9) SYNC PATTERN Data0 Data1 Data2 Data3 Data4 Parallel Data SYDT TIMING FOR CDRX_8B10B RECCLK SYDT RXD(0:9) K28.5 D21.4 D21.5 D21.5 K28.5 D21.4 D21.5 D21.5 D0 D1 D2 IDLE PATTERN IDLE PATTERN Data 42 Lattice Semiconductor Serializer Timing 8B/10B SERIALIZER DELAY TIMING ispGDX2 Family Data Sheet TXD SYMBOL N tCOSOUT SYMBOL N+1 REFCLK SOUT b4 b5 b6 b7 b8 b9 b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b0 b1 b2 SYMBOL N-1 SYMBOL N SYMBOL N+1 10B/12B SERIALIZER DELAY TIMING TXD SYMBOL N t COSOUT SYMBOL N+1 REFCLK SOUT b4 b5 b6 b7 b8 b9 "0" "1" b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 "0" "1" SYMBOL N-1 SYMBOL N SS Mode SERIALIZER DELAY TIMING TXD REFCLK t COSOUT SYMBOL N SYMBOL N+1 SS_CLKOUT t CKOSOUT SOUT b4 b5 b6 b7 b0 b1 b2 b3 t SKTX b4 b5 b6 b7 b0 SYMBOL N+1 SYMBOL N-1 SYMBOL N INTERNAL TIMING FOR sysHSI BLOCK t PWREFCLK REFCLK tHSITXDDATAS TXD tHSITXDDATAH 43 Lattice Semiconductor Deserializer Timing 8B/10B DESERIALIZER DELAY TIMING SYMBOL N SIN SYMBOL N+1 ispGDX2 Family Data Sheet SYMBOL N+2 b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b0 b1 b2 b3 b4 b5 TDSIN RECCLK RXD SYMBOL N-1 SYMBOL N 10B/12B DESERIALIZER DELAY TIMING SYMBOL N SIN SYMBOL N+1 SYMBOL N+2 "1" b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 "0" "1" b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 "0" "1" b0 b1 b2 b3 b4 TTDSIN RECCLK RXD SYMBOL N-2 SYMBOL N-1 SYMBOL N CDRX_SS DESERIALIZER DELAY TIMING SYMBOL N SIN b0 b1 b2 b3 b4 b5 b6 b7 TDSIN RECCLK RXD SYMBOL N-2 SYMBOL N-1 SYMBOL N b0 b1 SYMBOL N+1 b2 b3 b4 b5 b6 b7 b0 b1 SYMBOL N+2 b2 b3 b4 INTERNAL TIMING FOR sysHSI BLOCK RECCLK t HSIOUTVALIDPRE t HSIOUTVALIDPOST SYDT, RXD 44 Lattice Semiconductor ispGDX2 Family Data Sheet sysCLOCK PLL Timing Over Recommended Operating Conditions Symbol tPWH tPWL tR, tF tINSTB fMDIVIN fMDIVOUT fNDIVIN fNDIVOUT fVDIVIN fVDIVOUT tOUTDUTY Parameter Input clock, high time Input clock, low time Input Clock, rise and fall time Input clock stability, cycle to cycle (peak) M Divider input, frequency range M Divider output, frequency range N Divider input, frequency range N Divider output, frequency range V Divider input, frequency range V Divider output, frequency range Output clock, duty cycle Clean reference : 10 MHz ≤ fMDIVOUT ≤ 40 MHz or 100 MHz ≤ fVDIVIN ≤ 160 MHz Clean reference1: 40 MHz ≤ fMDIVOUT ≤ 320 MHz and 160 MHz ≤ fVDIVIN ≤ 400 MHz Clean reference1: 10 MHz ≤ fMDIVOUT ≤ 40 MHz or 100 MHz ≤ fVDIVIN ≤ 160 MHz Clean reference1: 40 MHz ≤ fMDIVOUT ≤ 320 MHz and 160 MHz ≤ fVDIVIN ≤ 400 MHz Internal feedback External feedback Typical = +/- 250ps 1 Conditions 80% to 80% 20% to 20% 20% to 80% Min 0.5 0.5 — — 10 10 10 10 100 10 40 — Max — — 3.0 +/- 300 320 320 320 320 400 320 60 +/- 600 Units ns ns ns ps MHz MHz MHz MHz MHz MHz % ps tJIT(CC) Output clock, cycle to cycle jitter (peak) — +/- 150 ps — +/- 600 ps TJIT(PERIOD) 2 Output clock, period jitter (peak) — — — — +/- 150 3.4 500 25 ps ns ps us ps ns ns tCLK_OUT_DLY tPHASE tLOCK tPLL_DELAY tRANGE tPLL_RSTW Input clock to CLK_OUT delay Input clock to external feedback delta Time to acquire phase lock after input stable Delay increment (Lead/Lag) Total output delay range (lead/lag) Minimum reset pulse width +/- 120 +/- 550 +/- 0.84 +/- 3.85 1.8 — 1. This condition assures that the output phase jitter will remain within speciﬁcation. Jitter speciﬁcation is based on optimized M, N and V settings determined by the ispLEVER software. 2. Accumulated jitter measured over 10,000 waveform samples 45 Lattice Semiconductor ispGDX2 Family Data Sheet Boundary Scan Timing Speciﬁcations Over Recommended Operating Conditions Parameter tBTCP tBTCPH tBTCPL tBTS tBTH tBTRF tBTCO tBTCODIS tBTCOEN tBTCRS tBTCRH tBUTCO tBTUODIS tBTUPOEN TCK [BSCAN] clock pulse width TCK [BSCAN] clock pulse width high TCK [BSCAN] clock pulse width low TCK [BSCAN] setup time TCK [BSCAN] hold time TCK [BSCAN] rise/fall time TAP controller falling edge of clock to valid output TAP controller falling edge of clock to valid disable TAP controller falling edge of clock to valid enable BSCAN test capture register setup time BSCAN test capture register hold time BSCAN test update register, falling edge of clock to valid output BSCAN test update register, falling edge of clock to valid disable BSCAN test update register, falling edge of clock to valid enable Description Min 40 20 20 8 10 50 — — — 8 10 — — — Max — — — — — — 10 10 10 — — 25 25 25 Units ns ns ns ns ns mV/ns ns ns ns ns ns ns ns ns 46 Lattice Semiconductor ispGDX2 Family Data Sheet Power Consumption ICORE 200 150 90 80 70 60 50 40 30 20 10 0 0 200 400 600 800 IHSI 100 IPLL IHSI_D 80 IPLL_D mA mA 100 50 0 0 50 100 150 200 250 300 350 mA IHSI_A 1000 1200 60 40 20 0 0 200 400 600 IPLL_A MHz Mbps MHz Power Estimation Coefﬁcients – Core and PLL Device ispGDX2-256 VCC 3.3 2.5 1.8 IDC (mA) 10.0 10.0 4.0 KREF 3.25 3.13 3.00 KIN 0.0139 0.0139 0.0213 KCORE 0.292 0.292 0.239 KPLLD 0.157 0.157 0.179 KPLLA 0.024 0.024 0.024 IDC: KREF: KIN: KCORE: KPLLD: KPLLA: Blank chip background current Reference voltage circuit current per bank I/O current per input per MHz Core current per MHz with GRP fanout of 1 PLL logic current per MHz per PLL PLL analog portion current per MHz per PLL Power Estimation Coefﬁcients – sysHSI Device ispGDX2-256 VCC 3.3 2.5 1.8 KRXD 0.027 0.027 0.019 KRXSTBY 1.3 1.3 3.7 KRXA 0.0023 0.0023 0.0040 KTXD 0.011 0.011 0.011 KTXSTBY 2.4 2.4 1.2 KTXA 0.0018 0.0018 0.0023 KRXD: KRXSTBY: KRXA: KTXD: KTXSTBY: KTXA: Receiver Logic current per Mbps Receiver Logic standby current Receiver Analog portion current per Mbps Transmitter Logic current per Mbps Transmitter Logic standby current Transmitter Analog portion current per Mbps 47 Lattice Semiconductor ispGDX2 Family Data Sheet Power Consumption (Continued) Power consumption in the ispGDX2 family is the sum of three components: ICC-TOTAL = ICORE + IPLL + IHSI (ICC-TOTAL combines current supplied via VCC pins and VCCP pins) ICORE = IDC + IREF + IIN = Blank chip background current + KREF * Number of Banks with VREF active + (KIN * Number of inputs + KCORE) * Average Input Switching Frequency (MHz) IPLL = IPLL_D + IPLL_A = [KPLLD * FVCO * Number of PLLs used] + [KPLLA * FVCO * Number of PLLs used] = [(KPLLD + KPLLA) * FVCO] * Number of PLLs used IHSI = IRX + ITX = [(KRXD + KRXA) * FRX + IRXSTBY] * Number of Receiver Channels + [(KTXD + KTXA) * FTX + ITXSTBY] * Number of Transmitter Channels Where: FVCO: sysClock PLL VCO Frequency in MHz FRX: sysHSI Receiver Serial Data Rate FTX: sysHSI Transmitter Serial Data Rate IHSI can also be determined by calculating IHSI_D, the current supplied by the VCC pin, and IHSI_A, the current supplied by the VCCP0 and VCCP1. IHSI = IHSI_D + IHSI_A = [(KRXD * FRX + IRXSTBY)* Number of Receiver Channels + (KTXD * FTX + ITXSTBY) * Number of Transmitter Channels] +[(KRXA * FRX) * Number of Receiver Channels + (KTXA * FTX) * Number of Transmitter Channels] The ICCP is supplied through VCCP0 and VCCP1 pins for PLL and sysHSI analog portion. The equation for ICCP can be derived from the equations below. ICCP = IPLL_A + IHSI_A = [(KPLLA * FVCO) * Number of PLLs used] + [(KRXA * FRX) * Number of Receiver Channels + (KTXA * FTX) * Number of Transmitter Channels] Where: IPLL_A: PLL Analog Portion Current IHSI_A: HSI Analog Portion Current Note: For further information about the use of these coefﬁcients, refer to Technical Note TN1034, Power Estimation in the ispGDX2 Family. ICC-TOTAL estimates are based on typical conditions. These values are for estimates only. Since the value of ICCTOTAL is sensitive to operating conditions and the program in the device, the actual current should be veriﬁed. 48 Lattice Semiconductor ispGDX2 Family Data Sheet Switching Test Conditions Figure 23 shows the output test load used for AC testing. Speciﬁc values for resistance, capacitance, voltage and other test conditions are shown in Table 7. Figure 23. Output Test Load, LVTTL and LVCMOS Standards (1.8V) VCCO R1 Device Output R2 CL* Test Point *CL includes Test Fixture and Probe Capacitance. Table 7. Test Fixture Required Components Test Condition Default LVCMOS 1.8 I/O (L -> H, H -> L) LVCMOS I/O (L -> H, H -> L) Default LVCMOS 1.8 I/O (Z -> H) Default LVCMOS 1.8 I/O (Z -> L) Default LVCMOS 1.8 I/O (H -> Z) Default LVCMOS 1.8 I/O (L -> Z) R1 106 — — 106 — 106 R2 106 — 106 — 106 — CL 35pF 35pF 35pF 35pF 5pF 5pF Timing Ref. VCCO/2 LVCMOS3.3 = 1.5V LVCMOS2.5 = VCCO/2 LVCMOS1.8 = VCCO/2 VCCO/2 VCCO/2 VOH - 0.15 VOL + 0.15 VCCO 1.8V LVCMOS3.3 = 3.0V LVCMOS2.5 = 2.3V LVCMOS1.8 = 1.65V 1.65V 1.65V 1.65V 1.65V Note: Output test conditions for all other interfaces are determined by the respective standards. 49 Lattice Semiconductor ispGDX2 Family Data Sheet Signal Descriptions1 Signal Names General Purpose BKx_IOy GCLK/CE0, GCLK/CE1, GCLK/CE2, GCLK/CE3 SEL0, SEL1, SEL22, SEL32 GOE0, GOE1, GOE22, GOE32 RESETb NC GND VCC VCCJ VCCOx VREFx Testing and Programming TMS TCK TDI TDO TOE PLL Functions PLL_FBKz PLL_RSTz CLK_OUTz PLL_LOCKz GNDP0, GNDP1 VCCP0, VCCP1 FIFO Functions FIFOy_DINw FIFOy_DOUTw FIFOy_FIFORSTb FIFOy_FULL FIFOy_EMPTY FIFOy_STRDb SERDES Functions HSImA_SINP, HSImB_SINP HSImA_SINN, HSImB_SINN HSImA_SOUTP, HSImB_SOUTP HSImA_SOUTN, HSImB_SOUTN HSImA_SYDT, HSImB_ SYDT HSImA_RECCLK, HSImB_RECCLK HSImA_CDRRSTb, HSImB_CDRRSTb HSIm_CSLOCK Input – Positive sense serial input for sysHSI BLOCK m channel A, B. Input – Negative (minus) sense serial input for sysHSI BLOCK m channel A, B. Output – Positive sense serial output for sysHSI BLOCK m channel A, B. Output – Negative (minus) sense serial output for sysHSI BLOCK m channel A, B. Output – Symbol alignment detect for sysHSI BLOCK m channel A, B. Internal Signal – Recovered clock for sysHSI BLOCK m channel A, B. Input – Resets the CDR circuit of sysHSI BLOCK m channel A, B. Output – LOCK output of the PLL associated with channel m. Input – DATA IN Bit w of FIFO y. Internal Signal – DATA OUT Bit w of FIFO y Input – Reset input for FIFO y (active low). Output – FULL ﬂag for FIFO y. Output – EMPTY ﬂag for FIFO y. Output – Start read (STRDb) ﬂag for FIFO y. Input – Optional feedback input allows external feedback for PLL z. Input – Optional input resets the M divider in PLL z. Output – Optional clock output from PLL z (clock signal occupies the input path of this I/O pad). Output – Optional lock output from PLL z (lock signal occupies the input path of this I/O pad). GND – Ground for PLLs. VCC – The power supply pins for PLLs. Input – Test Mode Select input, used to control the 1149.1 state machine. Input – Test Clock Input pin, used to clock the 1149.1 state machine. Input – Test Data In pin, used to load data into device using 1149.1 state machine. Output – Test Data Out pin used to shift data out of device using 1149.1. Input – Test Output Enable pin. TOE tristates all I/O pins when driven low. Input/Output – General purpose I/O number y in I/O Bank X. Input – Global clock/clock enable inputs. Input – Global MUX select inputs. Input – Global output enable inputs. Input – Global RESET signal (active low). No connect. GND – Ground. VCC – The power supply pins for core logic. VCC – The power supply for the JTAG logic. VCC – The power supply pins for I/O Bank X. Input – Deﬁnes the reference voltage for I/O Bank X. Description 50 Lattice Semiconductor ispGDX2 Family Data Sheet Signal Descriptions1 (Continued) Signal Names HSImA_TXDw, HSImB_ TXDw HSImA_RXDw, HSImB_ RXDw Source Synchronous Functions SS_SCLKIN0P, SS_SCLKIN1P SS_SCLKIN0N, SS_SCLKIN1N SS_CLKOUT0N, SS_CLKOUT1P SS_CLKOUT0N, SS_CLKOUT1N CAL 1. m, w, x, y and z are variables. 2. Not on ispGDX2-64 Description Internal Signal – Parallel data in bit w for sysHSI BLOCK m channel A, B. Internal Signal – Parallel data out bit w for sysHSI BLOCK m channel A, B. Input – Positive sense clock input for Source Synchronous group A, B. Input – Negative (minus) sense clock input for Source Synchronous group A, B. Output – Positive sense clock output for Source Synchronous group A, B. Output – Negative (minus) sense clock output for Source Synchronous group A, B. Input – Initiates source synchronous calibration sequence. ispGDX2-64 Power Supply and NC Connections1 Signal VCC VCCO0 VCCO1 VCCO2 VCCO3 VCCO4 VCCO5 VCCO6 VCCO7 VCCJ VCCP0 GNDP0 GND J7 F10 E10 B7 B4 E1 F1 K4 K1 G6 G5 A10, B9, C8, E6, E5, F6, F5, H3, J2 ispGDX2-64 (100-Ball fpBGA)2 A1, K10 1. All grounds must be electrically connected at the board level. 2. Pin orientation A1 starts from the upper left corner of the top side view with alphabetical order ascending vertically and numerical order ascending horizontally. 51 Lattice Semiconductor ispGDX2 Family Data Sheet ispGDX2 Power Supply and NC Connections1 Signal VCC ispGDX2-128 (208-Ball fpBGA)3 B15, C14, R15, B2, C3, P3, R2, ispGDX2-256 (484-Ball fpBGA)3 AA3, AA20, B3, B20, C2, C11, C12, C21, H9, H10, H11, H12, H13, H14, J8, J15, K8, K15, L8, L15, L20, M3, M8, M15, M20, N8, N15, P8, P15, R9, R10, R11, R12, R13, R14, Y2, Y11, Y12, Y21 AA14, AB20, Y17 P21, U20, Y22 C22, E20, J21 A20, B14, C17 A3, B9, C6 C1, F3, J2 P2, U3, Y1 AA9, AB3, Y6 L3 K1 N22 J1 K22 VCCO0 VCCO1 VCCO2 VCCO3 VCCO4 VCCO5 VCCO6 VCCO7 VCCJ VCCP0 VCCP1 GNDP0 GNDP1 GND N11, T12 L13, M16 E16, F13 A12, D11 A5, D6 E1, F4 L4, M1 N6, T5 P14 J1 J16 H1 H16 A16, D13, H15, J15, N13, T16, A1, B9, B8, D4, H2, J2, A2, A11, A12, A21, A1, A22, AA1, AA2, AA11, AA12, N4, R8, R9, T1, G7, G8, G9, G10, H7, H8, H9, H10, J7, AA21, AA22, AB1, AB2, AB11, AB12, AB21, AB22, B1, J8, J9, J10, K7, K8, K9, K10 B2, B11, B12, B21, B22, C3, C20, D4, D19, E5, E18, F6, F17, G7, G16, H8, H15, J9, J10, J11, J12, J13, J14, K9, K10, K11, K12, K13, K14, L1, L2, L7, L9, L10, L11, L12, L13, L14,L16, L21, L22, M1, M2, M7, M9, M10, M11, M12,M13, M14, M16, M21, M22, N9, N10, N11, N12, N13, N14, P9, P10, P11, P12, P13, P14, R8, R15, T7, T16, U6, U17, V5, V18, W4, W19,Y3, Y20 A11, B16 D8, D11, E6, E7, E8, E9, E12, E13, E14, E15, E16, F7, F16, G5, G6, G18, G19, H19, K4, K19, L19, M4, M19, N4, P4, P19, R4, R18, T4, T5, T17, T18, U5, U7, U16, V7, V8, V9, V10, V11, V12, V15, V16, V17, W14, Y18 NC2 1. All grounds must be electrically connected at the board level. 2. NC pins should not be connected to any active signals, VCC or GND. 3. Pin orientation A1 starts from the upper left corner of the top side view with alphabetical order ascending vertically and numerical order ascending horizontally. 52 Lattice Semiconductor ispGDX2 Family Data Sheet ispGDX2-64 Logic Signal Connections Signal Name GOE0 BK0_IO0/PLL_LOCK0 BK0_IO1 GND BK0_IO2 BK0_IO3 GND BK0_IO4/PLL_RST0 BK0_IO5 BK0_IO6 BK0_IO7 GND TCK RESETb BK1_IO0/PLL_FBK0 BK1_IO1 BK1_IO2 BK1_IO3/VREF(0,1) GND BK1_IO4 BK1_IO5 GND BK1_IO6 BK1_IO7 GCLK/CE2 GCLK/CE3 BK2_IO0 BK2_IO1 GND BK2_IO2 BK2_IO3 GND BK2_IO4/VREF (2,3) BK2_IO5 BK2_IO6 BK2_IO7 BK3_IO0 BK3_IO1 BK3_IO2 BK3_IO3 GND BK3_IO4 BK3_IO5 GND BK3_IO6 BK3_IO7/CLK_OUT0 sysIO LVDS Bank Pair/Polarity 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 7P 7N CLK2P CLK2N 8N 8P 9N 9P 10N 10P 11N 11P 12P 12N 13P 13N 14P 14N 15P 15N 0A 0A 0B 0B 0B 0B 0B 0B 0B 0B 0B 0B 0B 0B 0B 0B 0B 0B 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 HSI0B_SINP HSI0B_SINN FIFO1_STRDb6 HSI0B_CDRRSTb 0N 0P 1N 1P 2N 2P 3N 3P 4P 4N 5P 5N 6P 6N GDX Block 0A 0A 0A 0A 0A 0A 0A 0A 0A 0A 0A 0A 0A 0A MRB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 SERDES Mode I/O Pin1 HSI0A_CDRRSTb HSI0A_SINN HSI0A_SINP Note 4 HSI0A_SYDT FIFO0_STRDb6 HSI0A_SOUTP HSI0A_SOUTN SS_CLKIN1P SS_CLKIN1N SS_CLKOUT0N SS_CLKOUT0P HSI0B_SOUTN HSI0B_SOUTP HSI0_CSLOCK Note 4 HSI0B_SYDT5 5 SERDES Mode I/O Cell2 HSI0A_RECCLK HSI0A_RXD0/TXD0 HSI0A_RXD1/TXD1 HSI0A_RXD2/TXD2 HSI0A_RXD3/TXD3 HSI0A_RXD4/TXD4 HSI0A_RXD5/TXD5 HSI0A_RXD6/TXD6 HSI0A_RXD7/TXD7 HSI0A_RXD8/TXD8 HSI0A_RXD9/TXD9 HSI0A_SYDT5 HSI0BA_SYDT5 HSI0B_RXD0/TXD0 HSI0B_RXD1/TXD1 HSI0B_RXD2/TXD2 HSI0B_RXD3/TXD3 HSI0B_RXD4/TXD4 HSI0B_RXD5/TXD5 HSI0B_RXD6/TXD6 HSI0B_RXD7/TXD7 HSI0B_RXD8/TXD8 HSI0B_RXD9/TXD9 HSI0B_RECCLK - FIFO Mode I/O Cell/Pin3 FIFO0_FULL FIFO0_FIFORSTb FIFO0_DIN0/DOUT0 FIFO0_DIN1/DOUT1 FIFO0_DIN2/DOUT2 FIFO0_DIN3/DOUT3 FIFO0_DIN4/DOUT4 FIFO0_DIN5/DOUT5 FIFO0_DIN6/DOUT6 FIFO0_DIN7/DOUT7 FIFO0_DIN8/DOUT8 FIFO0_DIN9/DOUT9 FIFO0_ EMPTY FIFO1_FULL FIFO1_EMPTY FIFO1_DIN0 FIFO1_DIN1/DOUT1 FIFO1_DIN2/DOUT2 FIFO1_DIN3/DOUT3 FIFO1_DIN4/DOUT4 FIFO1_DIN5/DOUT5 FIFO1_DIN6/DOUT6 FIFO1_DIN7/DOUT7 FIFO1_DIN8/DOUT8 FIFO1_DIN9/DOUT9 FIFO1_FIFORSTb 100 fpBGA H6 J6 K6 GND G7 H7 GND K7 K8 J8 K9 GND J10 J9 H10 H9 H8 G10 GND G9 G8 GND F9 F8 F7 E7 E8 E9 GND D8 D9 GND D10 C9 C10 B10 A9 B8 A8 A7 GND C7 D7 GND B6 C6 53 Lattice Semiconductor ispGDX2 Family Data Sheet ispGDX2-64 Logic Signal Connections (Continued) Signal Name SEL0 SEL1 BK4_IO0/CLK_OUT2 BK4_IO1 GND BK4_IO2 BK4_IO3 GND BK4_IO4 BK4_IO5 BK4_IO6 BK4_IO7 TMS TDI GND TDO TOE BK5_IO0 BK5_IO1 BK5_IO2 BK5_IO3/Vref(4,5) GND BK5_IO4 BK5_IO5 GND BK5_IO6 BK5_IO7 GCLK/CE0 GCLK/CE1 BK6_IO0 BK6_IO1 GND BK6_IO2 BK6_IO3 GND BK6_IO4/Vref(Bank6,7) BK6_IO5 BK6_IO6 BK6_IO7/PLL_FBK2 BK7_IO0 BK7_IO1 BK7_IO2 BK7_IO3/PLL_RST2 GND BK7_IO4 BK7_IO5 sysIO LVDS Bank Pair/Polarity 4 4 4 4 4 4 4 4 4 4 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 7 7 7 7 7 7 7 20P 20N 21P 21N 22P 22N 23P 23N CLK0P CLK0N 24N 24P 25N 25P 26N 26P 27N 27P 28P 28N 29P 29N 30P 30N 18N 18P 19N 19P 1A 7 GDX Block 1A7 1A7 1A7 1A7 MRB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 SERDES Mode I/O Pin1 HSI1A_CDRRSTb FIFO2_STRDb6 HSI1A_SINN HSI1A_SINP CAL HSI1A_SYDT5 Note 4 HSI1_CSLOCK HSI1A_SOUTP HSI1A_SOUTN SS_CLKIN1P SS_CLKIN1N SS_CLKOUT1N SS_CLKOUT1P HSI1B_SOUTN HSI1B_SOUTP FIFO3_STRDb6 HSI1B_SYDT5 Note 4 HSI1B_SINP HSI1B_SINN SERDES Mode I/O Cell2 HSI1A_RECCLK HSI1A_RXD9/TXD9 HSI1A_RXD8/TXD8 HSI1A_RXD7/TXD7 HSI1A_RXD6/TXD6 HSI1A_RXD5/TXD5 HSI1A_RXD4/TXD4 HSI1A_RXD3/TXD3 HSI1A_RXD2/TXD2 HSI1A_RXD1/TXD1 HSI1A_RXD0/TXD0 HSI1A_SYDT5 HSI1B_SYDT5 HSI1B_RXD9/TXD9 HSI1B_RXD8/TXD8 HSI1B_RXD7/TXD7 HSI1B_RXD6/TXD6 HSI1B_RXD5/TXD5 HSI1B_RXD4/TXD4 HSI1B_RXD3/TXD3 HSI1B_RXD2/TXD2 HSI1B_RXD1/TXD1 HSI1B_RXD0/TXD0 HSI1B_RECCLK FIFO Mode I/O Cell/Pin3 FIFO2_FIFORSTb FIFO2_DIN9/DOUT9 FIFO2_DIN8/DOUT8 FIFO2_DIN7/DOUT7 FIFO2_DIN6/DOUT6 FIFO2_DIN5/DOUT5 FIFO2_DIN4/DOUT4 FIFO2_DIN3/DOUT3 FIFO2_DIN2/DOUT2 FIFO2_DIN1/DOUT1 FIFO2_DIN0/DOUT0 FIFO2_EMPTY FIFO2_FULL FIFO3_EMPTY FIFO3_DIN9/DOUT9 FIFO3_DIN8/DOUT8 FIFO3_DIN7/DOUT7 FIFO3_DIN6/DOUT6 FIFO3_DIN5/DOUT5 FIFO3_DIN4/DOUT4 FIFO3_DIN3/DOUT3 FIFO3_DIN2/DOUT2 FIFO3_DIN1/DOUT1 FIFO3_DIN0/DOUT0 - 100 fpBGA D6 D5 C5 B5 GND D4 C4 GND A6 A5 A4 A3 B3 A2 GND B1 B2 C1 C2 C3 D1 GND D3 D2 GND E2 E3 E4 F4 F3 F2 GND G3 G2 GND G1 H1 H2 J1 J3 K2 J4 K3 GND G4 H4 16N 16P 17N 17P 1A7 1A7 1A7 1A7 1A7 1A7 1A 1A7 1A7 1A7 1A7 1B 1B 1B 1B 1B 1B 1B 1B 1B 1B 1B 1B 1B 1B 7 54 Lattice Semiconductor ispGDX2 Family Data Sheet ispGDX2-64 Logic Signal Connections (Continued) Signal Name GND BK7_IO6 BK7_IO7/PLL_LOCK2 GOE1 sysIO LVDS Bank Pair/Polarity 7 7 7 7 31P 31N GDX Block 1B 1B MRB 14 15 SERDES Mode I/O Pin1 HSI1B_CDRRSTb SERDES Mode I/O Cell2 FIFO Mode I/O Cell/Pin3 FIFO3_FIFORSTb FIFO3_FULL 100 fpBGA GND K5 J5 H5 1. The signals in this column route to/from the assigned pins of the associated I/O cell. 2. The signals in this column use the I/O cell. If a receiver signal is present in the I/O cell, the associated pin is available for output only. When transmit data (TXD) is present in the cell, the associated pin is available for input only. 3. The DOUT outputs are routed to GRP through the input register of the cell and the DIN inputs are routed direct from the associated pins in FIFO only mode. In SERDES with FIFO mode, the FULL and EMPTY ﬂags are routed to the associated pins through the output MUX and the pins. 4. If the Source Synchronous Receiver is used in the HSI Block, this pin is unavailable for another use and must be left unconnected. 5. The SYDT signal has two routing options. If direct output through the dedicated pin is used, the I/O cell (the whole HSI Block) is not available for transmitter. The SYDT in the I/O Cell column is routed to the GRP through the input register of the cell and frees the I/O cell for transmitter. 6. FIFO_STRDb ﬂag output is used in SERDES with FIFO Mode only. 7. sysHSI Source Synchronous Receive Mode is not available for channel 1A. 55 Lattice Semiconductor ispGDX2 Family Data Sheet ispGDX2-128 Logic Signal Connections Signal Name TOE BK0_IO0 BK0_IO1 BK0_IO2 / PLL_LOCK2 / PLL_RST2 BK0_IO3 GND BK0_IO4 BK0_IO5 BK0_IO6 BK0_IO7 BK0_IO8 BK0_IO9 / PLL_FB2 BK0_IO10 BK0_IO11 GND BK0_IO12 BK0_IO13 BK0_IO14 BK0_IO15 / VREF0 GOE3 TDO GND BK1_IO0 / VREF1 BK1_IO1 BK1_IO2 BK1_IO3 BK1_IO4 BK1_IO5 BK1_IO6 BK1_IO7 BK1_IO8 BK1_IO9 BK1_IO10 BK1_IO11 GND BK1_IO12 BK1_IO13 BK1_IO14 BK1_IO15 / CLK_OUT2 GCLK/CE2 SEL2 SEL3 GCLK/CE3 BK2_IO0 BK2_IO1 BK2_IO2 sysIO LVDS Bank Pair/Polarity 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 16N 16P 17N 14P 14N 15P 15N 8P 8N 9P 9N 10P 10N 11P 11N 12P 12N 13P 13N 6N 6P 7N 7P 2N 2P 3N 3P 4N 4P 5N 5P 0A 0A 0A 0A 0A 0A 0A 0A 0A 0B 0B 0B 0B 0B 0B 0B 0B 0B 0B 0B 0B 0B 0B 0B 0B 1A7 1A7 1A7 0N 0P 1N 1P GDX Block MRB 0A 0A 0A 0A 0A 0A 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 SERDES Mode I/O Pin1 HSI0A_SINN HSI0A_SINP Note 4 HSI0A_SOUTN HSI0A_SOUTP HSI0A_SYDT5 HSI0A_CDRRSTb FIFO0A_STRDb Note 4 HSI0B_SOUTP HSI0B_SOUTN HSI0_CSLOCK HSI0B_SYDT5 HSI0B_SINP HSI0B_SINN FIFO0B_STRDb6 HSI0B_CDRRSTb SS_CLKIN1P SS_CLKIN1N SS_CLKOUT1N SS_CLKOUT1P 6 SERDES Mode I/O Cell2 HSI0A_SYDT HSI0A_RXD0/TXD0 HSI0A_RXD1/TXD1 HSI0A_RXD2/TXD2 HSI0A_RXD3/TXD3 HSI0A_RXD4/TXD4 HSI0A_RXD5/TXD5 HSI0A_RXD6/TXD6 HSI0A_RXD7/TXD7 HSI0A_RXD8/TXD8 HSI0A_RXD9/TXD9 HSI0A_RECCLK HSI0B_SYDT 5 5 FIFO Mode I/O Cell/Pin3 FIFO0A_FULL FIFO0A_ EMPTY FIFO0A_DIN0/DOUT0 FIFO0A_DIN1/DOUT1 FIFO0A_DIN2/DOUT2 FIFO0A_DIN3/DOUT3 FIFO0A_DIN4/DOUT4 FIFO0A_DIN5/DOUT5 FIFO0A_DIN6/DOUT6 FIFO0A_DIN7/DOUT7 FIFO0A_DIN8/DOUT8 FIFO0A_DIN9/DOUT9 FIFO0A_FIFORSTb FIFO0B_FULL FIFO0B_DIN0/DOUT0 FIFO0B_DIN1/DOUT1 FIFO0B_DIN2/DOUT2 FIFO0B_DIN3/DOUT3 FIFO0B_DIN4/DOUT4 FIFO0B_DIN5/DOUT5 FIFO0B_DIN6/DOUT6 FIFO0B_DIN7/DOUT7 FIFO0B_DIN8/DOUT8 FIFO0B_DIN9/DOUT9 - 208 fpBGA P8 P9 T10 R10 T11 GND P10 N10 R11 T13 P11 R12 P12 N12 GND T14 R13 T15 P13 T9 R16 GND N14 P15 N15 L14 M14 M13 M15 L15 P16 N16 K14 K13 GND K15 L16 J14 J13 N8 K16 G16 N9 H13 H14 G15 HSI0B_RXD0/TXD0 HSI0B_RXD1/TXD1 HSI0B_RXD2/TXD2 HSI0B_RXD3/TXD3 HSI0B_RXD4/TXD4 HSI0B_RXD5/TXD5 HSI0B_RXD6/TXD6 HSI0B_RXD7/TXD7 HSI0B_RXD8/TXD8 HSI0B_RXD9/TXD9 HSI0B_RECCLK HSI1A_SYDT5 FIFO0B_FIFORSTb FIFO0B_ EMPTY FIFO1A_FULL - 56 Lattice Semiconductor ispGDX2 Family Data Sheet ispGDX2-128 Logic Signal Connections (Continued) Signal Name BK2_IO3 GND BK2_IO4 BK2_IO5 BK2_IO6 BK2_IO7 BK2_IO8 BK2_IO9 BK2_IO10 BK2_IO11 GND BK2_IO12 BK2_IO13 BK2_IO14 BK2_IO15 / VREF2 TCK GOE2 BK3_IO0 / VREF3 BK3_IO1 BK3_IO2 BK3_IO3 GND BK3_IO4 BK3_IO5 BK3_IO6 BK3_IO7 BK3_IO8 BK3_IO9 BK3_IO10 BK3_IO11 GND BK3_IO12 BK3_IO13 BK3_IO14 BK3_IO15 RESET BK4_IO0 BK4_IO1 / PLL_LOCK0 / PLL_RST0 BK4_IO2 BK4_IO3 GND BK4_IO4 BK4_IO5 BK4_IO6 BK4_IO7 sysIO LVDS Bank Pair/Polarity 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 34N 34P 35N 35P 2A 2A 2A 2A 4 5 6 7 32N 32P 33N 33P 30P 30N 31P 31N 26P 26N 27P 27N 28P 28N 29P 29N 1B 1B 1B 1B 1B 1B 1B 1B 1B 1B 1B 1B 2A 2A 2A 2A 24P 24N 25P 25N 22N 22P 23N 23P 18N 18P 19N 19P 20N 20P 21N 21P 17P GDX Block MRB 1A7 1A7 1A7 1A7 1A7 1A7 1A7 1A 1A7 1A 7 7 SERDES Mode I/O Pin1 HSI1A_SINN HSI1A_SINP HSI1_CSLOCK Note 4 CAL HSI1A_SOUTN HSI1A_SOUTP HSI1A_SYDT5 HSI1A_CDRRSTb FIFO1A_STRDb6 Note 4 HSI1B_SOUTP HSI1B_SOUTN HSI1B_SYDT5 HSI1B_SINP HSI1B_SINN HSI1B_CDRRSTb HSI2A_CDRRSTb HSI2A_SINN HSI2A_SINP HSI2A_SYDT5 - SERDES Mode I/O Cell2 HSI1A_RXD0/TXD0 HSI1A_RXD1/TXD1 HSI1A_RXD2/TXD2 HSI1A_RXD3/TXD3 HSI1A_RXD4/TXD4 HSI1A_RXD5/TXD5 HSI1A_RXD6/TXD6 HSI1A_RXD7/TXD7 HSI1A_RXD8/TXD8 HSI1A_RXD9/TXD9 HSI1A_RECCLK HSI1B_RXD0/TXD0 HSI1B_RXD1/TXD1 HSI1B_RXD2/TXD2 HSI1B_RXD3/TXD3 HSI1B_RXD4/TXD4 HSI1B_RXD5/TXD5 HSI1B_RXD6/TXD6 HSI1B_RXD7/TXD7 HSI1B_RXD8/TXD8 HSI1B_RXD9/TXD9 HSI1B_RECCLK HSI1B_SYDT5 HSI2A_SYDT5 HSI2A_RECCLK HSI2A_RXD9/TXD9 HSI2A_RXD8/TXD8 FIFO Mode I/O Cell/Pin3 FIFO1A_DIN0/DOUT0 FIFO1A_DIN1/DOUT1 FIFO1A_DIN2/DOUT2 FIFO1A_DIN3/DOUT3 FIFO1A_DIN4/DOUT4 FIFO1A_DIN5/DOUT5 FIFO1A_DIN6/DOUT6 FIFO1A_DIN7/DOUT7 FIFO1A_DIN8/DOUT8 FIFO1A_DIN9/DOUT9 FIFO1A_FIFORSTb FIFO1A_EMPTY FIFO1B_DIN0/DOUT0 FIFO1B_DIN1/DOUT1 FIFO1B_DIN2/DOUT2 FIFO1B_DIN3/DOUT3 FIFO1B_DIN4/DOUT4 FIFO1B_DIN5/DOUT5 FIFO1B_DIN6/DOUT6 FIFO1B_DIN7/DOUT7 / FIFO1B_STRDb FIFO1B_DIN8/DOUT8 FIFO1B_DIN9/DOUT9 FIFO1B_FULL FIFO1B_FIFORSTb FIFO1B_ EMPTY FIFO2A_EMPTY FIFO2A_FIFORSTb FIFO2A_FULL FIFO2A_DIN9/DOUT9 FIFO2A_DIN8/DOUT8 208 fpBGA F16 GND G13 G14 F14 F15 D16 E15 E13 E14 GND C16 D15 C15 D14 R14 A9 C13 B14 A15 B13 GND D12 C12 A14 A13 B12 C11 D10 C10 GND B11 B10 A10 C9 A7 C8 B7 A6 B6 GND C7 D7 C6 B5 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 1A7 1A7 1A7 1B 1B 1B 1B 57 Lattice Semiconductor ispGDX2 Family Data Sheet ispGDX2-128 Logic Signal Connections (Continued) Signal Name BK4_IO8 BK4_IO9 / PLL_FB0 BK4_IO10 BK4_IO11 GND BK4_IO12 BK4_IO13 BK4_IO14 BK4_IO15 / VREF4 GOE1 TMS GND BK5_IO0 / VREF5 BK5_IO1 BK5_IO2 BK5_IO3 BK5_IO4 BK5_IO5 BK5_IO6 BK5_IO7 BK5_IO8 BK5_IO9 BK5_IO10 BK5_IO11 GND BK5_IO12 BK5_IO13 BK5_IO14 BK5_IO15 / CLK_OUT0 GCLK/CE0 SEL0 SEL1 GCLK/CE1 BK6_IO0 BK6_IO1 BK6_IO2 BK6_IO3 GND BK6_IO4 BK6_IO5 BK6_IO6 BK6_IO7 BK6_IO8 BK6_IO9 BK6_IO10 BK6_IO11 sysIO LVDS Bank Pair/Polarity 4 4 4 4 4 4 4 4 4 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 6 6 6 50N 50P 51N 51P 52N 52P 53N 53P CLK0N 48N 48P 49N 49P 46P 46N 47P 47N CLK0P 40P 40N 41P 41N 42P 42N 43P 43N 44P 44N 45P 45N 2B 2B 2B 2B 2B 2B 2B 2B 2B 2B 2B 2B 2B 2B 2B 2B 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 38N 38P 39N 39P 2A 2A 2A 2A 36N 36P 37N 37P GDX Block MRB 2A 2A 2A 2A 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 SERDES Mode I/O Pin1 FIFO2A_STRDb6 HSI2A_SOUTN HSI2A_SOUTP Note 4 FIFO2B_STRDb6 HSI2B_CDRRSTb HSI2B_SYDT5 HSI2B_SOUTP HSI2B_SOUTN Note 4 HSI2_CSLOCK HSI2B_SINP HSI2B_SINN SS_CLKIN0P SS_CLKIN0N SS_CLKOUT0N SS_CLKOUT0P HSI3A_CDRRSTb FIFO3A_STRDb6 HSI3A_SINN HSI3A_SINP HSI3A_SYDT5 HSI3_CSLOCK HSI3A_SOUTN HSI3A_SOUTP SERDES Mode I/O Cell2 HSI2A_RXD7/TXD7 HSI2A_RXD6/TXD6 HSI2A_RXD5/TXD5 HSI2A_RXD4/TXD4 HSI2A_RXD3/TXD3 HSI2A_RXD2/TXD2 HSI2A_RXD1/TXD1 HSI2A_RXD0/TXD0 HSI2B_RECCLK HSI2B_RXD9/TXD9 HSI2B_RXD8/TXD8 HSI2B_RXD7/TXD7 HSI2B_RXD6/TXD6 HSI2B_RXD5/TXD5 HSI2B_RXD4/TXD4 HSI2B_RXD3/TXD3 HSI2B_RXD2/TXD2 HSI2B_RXD1/TXD1 HSI2B_RXD0/TXD0 HSI2B_SYDT5 HSI3A_RECCLK HSI3A_RXD9/TXD9 HSI3A_RXD8/TXD8 HSI3A_RXD7/TXD7 HSI3A_RXD6/TXD6 HSI3A_RXD5/TXD5 HSI3A_RXD4/TXD4 HSI3A_RXD3/TXD3 FIFO Mode I/O Cell/Pin3 FIFO2A_DIN7/DOUT7 FIFO2A_DIN6/DOUT6 FIFO2A_DIN5/DOUT5 FIFO2A_DIN4/DOUT4 FIFO2A_DIN3/DOUT3 FIFO2A_DIN2/DOUT2 FIFO2A_DIN1/DOUT1 FIFO2A_DIN0/DOUT0 FIFO2B_EMPTY FIFO2B_FIFORSTb FIFO2B_DIN9/DOUT9 FIFO2B_DIN8/DOUT8 FIFO2B_DIN7/DOUT7 FIFO2B_DIN6/DOUT6 FIFO2B_DIN5/DOUT5 FIFO2B_DIN4/DOUT4 FIFO2B_DIN3/DOUT3 FIFO2B_DIN2/DOUT2 FIFO2B_DIN1/DOUT1 FIFO2B_DIN0/DOUT0 FIFO2B_FULL FIFO3A_EMPTY FIFO3A_FIFORSTb FIFO3A_DIN9/DOUT9 FIFO3A_DIN8/DOUT8 FIFO3A_DIN7/DOUT7 FIFO3A_DIN6/DOUT6 FIFO3A_DIN5/DOUT5 FIFO3A_DIN4/DOUT4 FIFO3A_DIN3/DOUT3 208 fpBGA A4 A3 C5 D5 GND B4 A2 B3 C4 A8 R1 GND D3 C2 D2 B1 E3 E4 F3 E2 F2 C1 G3 G4 GND D1 G2 H4 H3 D9 F1 G1 D8 J4 J3 K1 K2 GND K4 K3 L1 L2 N1 M2 M4 M3 58 Lattice Semiconductor ispGDX2 Family Data Sheet ispGDX2-128 Logic Signal Connections (Continued) Signal Name GND BK6_IO12 BK6_IO13 BK6_IO14 BK6_IO15 / VREF6 TDI GOE0 GND BK7_IO0 / VREF7 BK7_IO1 BK7_IO2 BK7_IO3 BK7_IO4 BK7_IO5 BK7_IO6 BK7_IO7 BK7_IO8 BK7_IO9 BK7_IO10 BK7_IO11 GND BK7_IO12 BK7_IO13 BK7_IO14 BK7_IO15 sysIO LVDS Bank Pair/Polarity 6 6 6 6 6 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 62P 62N 63P 63N 56P 56N 57P 57N 58P 58N 59P 59N 60P 60N 61P 61N 54N 54P 55N 55P GDX Block MRB 3A 3A 3A 3A 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SERDES Mode I/O Pin1 Note 4 FIFO3B_STRDb6 HSI3B_CDRRSTb HSI3B_SYDT5 HSI3B_SOUTP HSI3B_SOUTN Note 4 HSI3B_SINP HSI3B_SINN SERDES Mode I/O Cell2 HSI3A_RXD2/TXD2 HSI3A_RXD1/TXD1 HSI3A_RXD0/TXD0 HSI3A_SYDT HSI3B_RECCLK HSI3B_RXD9/TXD9 HSI3B_RXD8/TXD8 HSI3B_RXD7/TXD7 HSI3B_RXD6/TXD6 HSI3B_RXD5/TXD5 HSI3B_RXD4/TXD4 HSI3B_RXD3/TXD3 HSI3B_RXD2/TXD2 HSI3B_RXD1/TXD1 HSI3B_RXD0/TXD0 HSI3B_SYDT5 5 FIFO Mode I/O Cell/Pin3 FIFO3A_DIN2/DOUT2 FIFO3A_DIN1/DOUT1 FIFO3A_DIN0/DOUT0 FIFO3A_ FULL FIFO3B_FIFORSTb FIFO3B_DIN9/DOUT9 FIFO3B_DIN8/DOUT8 FIFO3B_DIN7/DOUT7 FIFO3B_DIN6/DOUT6 FIFO3B_DIN5/DOUT5 FIFO3B_DIN4/DOUT4 FIFO3B_DIN3/DOUT3 FIFO3B_DIN2/DOUT2 FIFO3B_DIN1/DOUT1 FIFO3B_DIN0/DOUT0 FIFO3B_ EMPTY FIFO3B_FULL 208 fpBGA GND L3 N2 P1 P2 N3 T8 GND T2 R3 P4 T3 N5 P5 R4 T4 R5 P6 N7 P7 GND R6 T6 R7 T7 1. The signals in this column route to/from the assigned pins of the associated I/O cell. 2. The signals in this column use the I/O cell. If a receiver signal is present in the I/O cell, the associated pin is available for output only. When transmit data (TXD) is present in the cell, the associated pin is available for input only. 3. The DOUT outputs are routed to GRP through the input register of the cell and the DIN inputs are routed direct from the associated pins in FIFO only mode. In SERDES with FIFO mode, the FULL and EMPTY ﬂags are routed to the associated pins through the output MUX and the pins. 4. If the Source Synchronous Receiver is used in the HSI Block, this pin is unavailable for another use and must be left unconnected. 5. The SYDT signal has two routing options. If direct output through the dedicated pin is used, the I/O cell (the whole HSI Block) is not available for transmitter. The SYDT in the I/O Cell column is routed to the GRP through the input register of the cell and frees the I/O cell for transmitter. 6. FIFO_STRDb ﬂag output is used in SERDES with FIFO Mode only. 7. sysHSI Source Synchronous Receive Mode is not available for channel 1A. 59 Lattice Semiconductor ispGDX2 Family Data Sheet ispGDX2-256 Logic Signal Connections Signal Name BK0_IO0 BK0_IO1 BK0_IO2/ PLL_LOCK2 BK0_IO3 GND BK0_IO4 BK0_IO5 BK0_IO6 BK0_IO7 BK0_IO8 BK0_IO9/ PLL_FB2 BK0_IO10 BK0_IO11 GND BK0_IO12 BK0_IO13 BK0_IO14 BK0_IO15 BK0_IO16 BK0_IO17/ PLL_RST2 BK0_IO18 BK0_IO19 GND BK0_IO20 BK0_IO21/ VREF0 BK0_IO22 BK0_IO23 BK0_IO24 BK0_IO25 BK0_IO26 BK0_IO27 BK0_IO28 BK0_IO29 BK0_IO30 BK0_IO31 GND GOE3 TDO GND BK1_IO0 BK1_IO1 BK1_IO2 BK1_IO3 BK1_IO4 sysIO Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 LVDS GDX Pair/Polarity Block MRB 0N 0P 1N 1P 2N 2P 3N 3P 4N 4P 5N 5P 6N 6P 7N 7P 8N 8P 9N 9P 10N 10P 11N 11P 12N 12P 13N 13P 14N 14P 15N 15P 16P 16N 17P 17N 18P 0A 0A 0A 0A 0A 0A 0A 0A 0A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 0B 0B 0B 0B 0B 0A 0A 0A 0A 0A 0A 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 SERDES Mode I/O Pin1 HSI0A_SINN HSI0A_SINP Note 4 HSI0A_SOUTN HSI0A_SOUTP HSI0A_SYDT5 HSI0A_CDRRSTb FIFO0A_STRDb6 HSI1A_SOUTN HSI1A_SOUTP Note 4 HSI1A_SINN HSI1A_SINP HSI1A_SYDT5 HSI1A_CDRRSTb5 FIFO1A_STRDb6 Note 4 HSI0B_SINP SERDES Mode I/O Cell2 SYDT_HSI0A5 HSI0A_RXD0/TXD0 HSI0A_RXD1/TXD1 HSI0A_RXD2/TXD2 HSI0A_RXD3/TXD3 HSI0A_RXD4/TXD4 HSI0A_RXD5/TXD5 HSI0A_RXD6/TXD6 HSI0A_RXD7/TXD7 HSI0A_RXD8/TXD8 HSI0A_RXD9/TXD9 HSI0A_RECCLK HSI1A_SYDT HSI1A_RXD1/TXD1 HSI1A_RXD2/TXD2 HSI1A_RXD3/TXD3 HSI1A_RXD4/TXD4 HSI1A_RXD5/TXD5 HSI1A_RXD6/TXD6 HSI1A_RXD7/TXD7 HSI1A_RXD8/TXD8 HSI1A_RXD9/TXD9 HSI1A_RECCLK HSI0B_SYDT5 HSI0B_RXD0/TXD0 HSI0B_RXD1/TXD1 HSI0B_RXD2/TXD2 5 FIFO Mode I/O Cell/Pin3 FIFO0A_FULL FIFO0A_ EMPTY FIFO0A_DIN0/DOUT0 FIFO0A_DIN1/DOUT1 FIFO0A_DIN2/DOUT2 FIFO0A_DIN3/DOUT3 FIFO0A_DIN4/DOUT4 FIFO0A_DIN5/DOUT5 FIFO0A_DIN6/DOUT6 FIFO0A_DIN7/DOUT7 FIFO0A_DIN8/DOUT8 FIFO0A_DIN9/DOUT9 FIFO0A_FIFORSTb FIFO1A_FULL FIFO1A_DIN0/DOUT0 FIFO1A_DIN1/DOUT1 FIFO1A_DIN2/DOUT2 FIFO1A_DIN3/DOUT3 FIFO1A_DIN4/DOUT4 FIFO1A_DIN5/DOUT5 FIFO1A_DIN6/DOUT6 FIFO1A_DIN7/DOUT7 FIFO1A_DIN8/DOUT8 FIFO1A_DIN9/DOUT9 FIFO1A_FIFORSTb FIFO1A_EMPTY FIFO0B_ FULL FIFO0B_DIN0/DOUT0 FIFO0B_DIN1/DOUT1 FIFO0B_DIN2/DOUT2 484 fpBGA AB13 AA13 V13 V14 GND U12 U13 W12 Y13 W13 Y14 T12 T13 GND AB14 AB15 Y15 W15 AA15 AA16 Y16 W16 GND U14 U15 AB16 AB17 AA17 W17 T14 T15 AA18 AB18 W18 Y19 GND AA19 AB19 GND W21 W20 V22 W22 P16 HSI1A_RXD0/TXD0 60 Lattice Semiconductor ispGDX2 Family Data Sheet ispGDX2-256 Logic Signal Connections (Continued) Signal Name BK1_IO5 BK1_IO6 BK1_IO7 BK1_IO8 BK1_IO9 BK1_IO10/ VREF1 BK1_IO11 GND BK1_IO12 BK1_IO13 BK1_IO14 BK1_IO15 BK1_IO16 BK1_IO17 BK1_IO18 BK1_IO19 GND BK1_IO20 BK1_IO21 BK1_IO22 BK1_IO23 BK1_IO24 BK1_IO25 BK1_IO26 BK1_IO27 GND BK1_IO28 BK1_IO29 BK1_IO30 BK1_IO31/ CLK_OUT2 GCLK/CE2 SEL2 SEL3 GCLK/CE3 BK2_IO0/ CLK_OUT3 BK2_IO1 BK2_IO2 BK2_IO3 GND BK2_IO4 BK2_IO5 BK2_IO6 BK2_IO7 BK2_IO8 BK2_IO9 sysIO Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 34N 34P 35N 35P 36N 36P 30P 30N 31P 31N CLK2P CLK2N 32N 32P 33N 33P LVDS GDX Pair/Polarity Block MRB 18N 19P 19N 20P 20N 21P 21N 22P 22N 23P 23N 24P 24N 25P 25N 26P 26N 27P 27N 28P 28N 29P 29N 0B 0B 0B 0B 0B 0B 0B 0B 0B 0B 0B 1B 1B 1B 1B 1B 1B 1B 1B 1B 1B 1B 1B 1B 1B 1B 1B 3A7 3A7 3A 3A7 3A 7 7 SERDES Mode I/O Pin1 HSI0B_SINN HSI0_CSLOCK HSI0B_SYDT 5 SERDES Mode I/O Cell2 HSI0B_RXD3/TXD3 HSI0B_RXD4/TXD4 HSI0B_RXD5/TXD5 HSI0B_RXD6/TXD6 HSI0B_RXD7/TXD7 HSI0B_RXD8/TXD8 HSI0B_RXD9/TXD9 HSI0B_RECCLK HSI1B_SYDT 5 FIFO Mode I/O Cell/Pin3 FIFO0B_DIN3/DOUT3 FIFO0B_DIN4/DOUT4 FIFO0B_DIN5/DOUT5 FIFO0B_DIN6/DOUT6 FIFO0B_DIN7/DOUT7 FIFO0B_DIN8/DOUT8 FIFO0B_DIN9/DOUT9 FIFO0B_FIFORSTb FIFO0B_EMPTY FIFO1B_FULL FIFO1B_DIN0/DOUT0 FIFO1B_DIN1/DOUT1 FIFO1B_DIN2/DOUT2 FIFO1B_DIN3/DOUT3 FIFO1B_DIN4/DOUT4 FIFO1B_DIN5/DOUT5 FIFO1B_DIN6/DOUT6 FIFO1B_DIN7/DOUT7 FIFO1B_DIN8/DOUT8 FIFO1B_DIN9/DOUT9 FIFO1B_FIFORSTb FIFO1B_EMPTY FIFO3A_FULL - 484 fpBGA P17 U18 V19 V20 V21 R16 R17 GND U19 T19 U21 U22 R19 T20 T21 T22 GND N16 N17 R20 R21 N19 P20 P18 N18 GND R22 P22 M18 M17 N20 N21 K21 K20 K17 K18 L17 L18 GND J17 J18 J22 J20 H22 H21 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 HSI0B_SOUTP HSI0B_SOUTN HSI0B_CDRRSTb FIFO0B_STRDb6 Note 4 HSI1B_SOUTP HSI1B_SOUTN HSI1_CSLOCK HSI1B_SYDT HSI1B_SINP HSI1B_SINN FIFO1B_STRDb6 HSI1B_CDRRSTb SS_CLKIN1P SS_CLKIN1N SS_CLKOUT1N SS_CLKOUT1P HSI3A_SINN HSI3A_SINP HSI3_CSLOCK Note 4 CAL 5 HSI1B_RXD0/TXD0 HSI1B_RXD1/TXD1 HSI1B_RXD2/TXD2 HSI1B_RXD3/TXD3 HSI1B_RXD4/TXD4 HSI1B_RXD5/TXD5 HSI1B_RXD6/TXD6 HSI1B_RXD7/TXD7 HSI1B_RXD8/TXD8 HSI1B_RXD9/TXD9 HSI1B_RECCLK HSI3A_SYDT HSI3A_RXD1/TXD1 HSI3A_RXD2/TXD2 HSI3A_RXD3/TXD3 HSI3A_RXD4/TXD4 HSI3A_RXD5/TXD5 HSI3A_RXD6/TXD6 5 FIFO3A_DIN0/DOUT0 FIFO3A_DIN1/DOUT1 FIFO3A_DIN2/DOUT2 FIFO3A_DIN3/DOUT3 FIFO3A_DIN4/DOUT4 FIFO3A_DIN5/DOUT5 FIFO3A_DIN6/DOUT6 3A7 HSI3A_RXD0/TXD0 3A7 3A7 3A7 3A7 61 Lattice Semiconductor ispGDX2 Family Data Sheet ispGDX2-256 Logic Signal Connections (Continued) Signal Name BK2_IO10 BK2_IO11 GND BK2_IO12 BK2_IO13 BK2_IO14 BK2_IO15 BK2_IO16 BK2_IO17 BK2_IO18 BK2_IO19 GND BK2_IO20/ PLL_FB3 BK2_IO21/ VREF2 BK2_IO22 BK2_IO23 BK2_IO24 BK2_IO25 BK2_IO26 BK2_IO27 BK2_IO28 BK2_IO29 BK2_IO30 BK2_IO31 GND TCK GOE2 BK3_IO0 BK3_IO1 BK3_IO2 BK3_IO3 GND BK3_IO4 BK3_IO5 BK3_IO6 BK3_IO7 BK3_IO8 BK3_IO9 BK3_IO10/ VREF3 BK3_IO11 GND BK3_IO12 BK3_IO13 BK3_IO14/ PLL_RST3 sysIO Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 LVDS GDX Pair/Polarity Block MRB 37N 37P 38N 38P 39N 39P 40N 40P 41N 41P 42N 42P 43N 43P 44N 44P 45N 45P 46N 46P 47N 47P 48P 48N 49P 49N 50P 50N 51P 51N 52P 52N 53P 53N 54P 54N 55P 3A7 3A7 3A7 3A 7 SERDES Mode I/O Pin1 HSI3A_SOUTN HSI3A_SOUTP HSI3A_SYDT5 HSI3A_CDRRSTb FIFO3A_STRDb6 Note 4 HSI2A_SOUTN HSI2A_SOUTP HSI2_CSLOCK HSI2A_SYDT5 HSI2A_SINN HSI2A_SINP HSI2A_CDRRSTb FIFO2A_STRDb6 Note 4 HSI3B_SINP HSI3B_SINN HSI3B_SYDT5 HSI3B_SOUTP HSI3B_SOUTN FIFO3B_STRDb6 HSI3B_CDRRSTb - SERDES Mode I/O Cell2 HSI3A_RXD7/TXD7 HSI3A_RXD8/TXD8 HSI3A_RXD9/TXD9 HSI3A_RECCLK HSI2A_SYDT5 HSI2A_RXD0/TXD0 HSI2A_RXD1/TXD1 HSI2A_RXD2/TXD2 HSI2A_RXD3/TXD3 HSI2A_RXD4/TXD4 HSI2A_RXD5/TXD5 HSI2A_RXD6/TXD6 HSI2A_RXD7/TXD7 HSI2A_RXD8/TXD8 HSI2A_RXD9/TXD9 HSI2A_RECCLK HSI3B_SYDT5 HSI3B_RXD0/TXD0 HSI3B_RXD1/TXD1 HSI3B_RXD2/TXD2 HSI3B_RXD3/TXD3 HSI3B_RXD4/TXD4 HSI3B_RXD5/TXD5 HSI3B_RXD6/TXD6 HSI3B_RXD7/TXD7 HSI3B_RXD8/TXD8 HSI3B_RXD9/TXD9 HSI3B_RECCLK HSI3B_RECCLK - FIFO Mode I/O Cell/Pin3 FIFO3A_DIN7/DOUT7 FIFO3A_DIN8/DOUT8 FIFO3A_DIN9/DOUT9 FIFO3A_FIFORSTb FIFO3A_EMPTY FIFO2A_FULL FIFO2A_DIN0/DOUT0 FIFO2A_DIN1/DOUT1 FIFO2A_DIN2/DOUT2 FIFO2A_DIN3/DOUT3 FIFO2A_DIN4/DOUT4 FIFO2A_DIN5/DOUT5 FIFO2A_DIN6/DOUT6 FIFO2A_DIN7/DOUT7 FIFO2A_DIN8/DOUT8 FIFO2A_DIN9/DOUT9 FIFO2A_FIFORSTb FIFO2A_EMPTY FIFO3B_FULL FIFO3B_DIN0/DOUT0 FIFO3B_DIN1/DOUT1 FIFO3B_DIN2/DOUT2 FIFO3B_DIN3/DOUT3 FIFO3B_DIN4/DOUT4 FIFO3B_DIN5/DOUT5 FIFO3B_DIN6/DOUT6 FIFO3B_DIN7/DOUT7 FIFO3B_DIN8/DOUT8 FIFO3B_DIN9/DOUT9 FIFO3B_FIFORSTb - 484 fpBGA K16 J16 GND J19 H20 G21 G20 G22 F22 F20 F21 GND H18 G17 E21 F19 E22 D22 H17 H16 E19 F18 D20 D21 GND B19 C19 E17 D18 A19 A18 GND G15 G14 D17 D16 C18 B18 F15 F14 GND B17 A17 A16 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 3A7 3A7 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 62 Lattice Semiconductor ispGDX2 Family Data Sheet ispGDX2-256 Logic Signal Connections (Continued) Signal Name BK3_IO15 BK3_IO16 BK3_IO17 BK3_IO18 BK3_IO19 GND BK3_IO20 BK3_IO21 BK3_IO22 BK3_IO23 BK3_IO24 BK3_IO25 BK3_IO26 BK3_IO27 GND BK3_IO28 BK3_IO29 BK3_IO30/ PLL_LOCK3 BK3_IO31 RESETb BK4_IO0 BK4_IO1/ PLL_LOCK0 BK4_IO2 BK4_IO3 GND BK4_IO4 BK4_IO5 BK4_IO6 BK4_IO7 BK4_IO8 BK4_IO9/ PLL_FB0 BK4_IO10 BK4_IO11 GND BK4_IO12 BK4_IO13 BK4_IO14 BK4_IO15 BK4_IO16 BK4_IO17/ PLL_RST0 BK4_IO18 BK4_IO19 GND BK4_IO20 sysIO Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 70N 70P 71N 71P 72N 72P 73N 73P 74N 4A 4A 4A 4A 5A 5A 5A 5A 5A 66N 66P 67N 67P 68N 68P 69N 69P 4A 4A 4A 4A 4A 4A 4A 4A 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 64N 64P 65N 65P LVDS GDX Pair/Polarity Block MRB 55N 56P 56N 57P 57N 58P 58N 59P 59N 60P 60N 61P 61N 62P 62N 63P 63N 3B 2B 2B 2B 2B 2B 2B 2B 2B 2B 2B 2B 2B 2B 2B 2B 2B 4A 4A 4A 4A 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 SERDES Mode I/O Pin1 Note 4 HSI2B_SOUTP HSI2B_SOUTN FIFO2B_STRDb6 HSI2B_SYDT5 HSI2B_SINP HSI2B_SINN HSI2B_CDRRSTb HSI4A_CDRRSTb HSI4A_SINN HSI4A_SINP HSI4A_SYDT5 FIFO4A_STRDb6 HSI4A_SOUTN HSI4A_SOUTP Note 4 HSI5A_CDRRSTb FIFO5A_STRDb6 HSI5A_SOUTN SERDES Mode I/O Cell2 HSI2B_RXD0/TXD0 HSI2B_RXD1/TXD1 HSI2B_RXD2/TXD2 HSI2B_RXD3/TXD3 HSI2B_RXD4/TXD4 HSI2B_RXD5/TXD5 HSI2B_RXD6/TXD6 HSI2B_RXD7/TXD7 HSI2B_RXD8/TXD8 HSI2B_RXD9/TXD9 HSI2B_RECCLK HSI2B_SYDT5 HSI4A_SYDT5 HSI4A_RECCLK HSI4A_RXD9/TXD9 HSI4A_RXD8/TXD8 HSI4A_RXD7/TXD7 HSI4A_RXD6/TXD6 HSI4A_RXD5/TXD5 HSI4A_RXD4/TXD4 HSI4A_RXD3/TXD3 HSI4A_RXD2/TXD2 HSI4A_RXD1/TXD1 HSI4A_RXD0/TXD0 HSI5A_RECCLK FIFO Mode I/O Cell/Pin3 FIFO3B_EMPTY FIFO2B_DIN0/DOUT0 FIFO2B_DIN1/DOUT1 FIFO2B_DIN2/DOUT2 FIFO2B_DIN3/DOUT3 FIFO2B_DIN4/DOUT4 FIFO2B_DIN5/DOUT5 FIFO2B_DIN6/DOUT6 FIFO2B_DIN7 /DOUT7 FIFO2B_DIN8/DOUT8 FIFO2B_DIN9/DOUT9 FIFO2B_FULL FIFO2B_FIFORSTb FIFO2B_ EMPTY FIFO4A_EMPTY FIFO4A_FIFORSTb FIFO4A_FULL FIFO4A_DIN9/DOUT9 FIFO4A_DIN8/DOUT8 FIFO4A_DIN7 /DOUT7 FIFO4A_DIN6/DOUT6 FIFO4A_DIN5/DOUT5 FIFO4A_DIN4/DOUT4 FIFO4A_DIN3/DOUT3 FIFO4A_DIN2/DOUT2 FIFO4A_DIN1/DOUT1 FIFO4A_DIN0/DOUT0 FIFO5A_EMPTY FIFO5A_FIFORSTb 484 fpBGA C16 D15 D14 B16 C15 GND G13 G12 B15 A15 C14 A14 F13 F12 GND D13 C13 B13 A13 D12 A10 B10 E11 E10 GND F11 F10 C10 C9 D10 D9 G11 G10 GND A9 C8 B8 A8 B7 C7 A7 B6 GND F9 63 Lattice Semiconductor ispGDX2 Family Data Sheet ispGDX2-256 Logic Signal Connections (Continued) Signal Name BK4_IO21/ VREF4 BK4_IO22 BK4_IO23 BK4_IO24 BK4_IO25 BK4_IO26 BK4_IO27 BK4_IO28 BK4_IO29 BK4_IO30 BK4_IO31 GND GOE1 TMS GND BK5_IO0 BK5_IO1 BK5_IO2 BK5_IO3 BK5_IO4 BK5_IO5 BK5_IO6 BK5_IO7 BK5_IO8 BK5_IO9 BK5_IO10/ VREF5 BK5_IO11 GND BK5_IO12 BK5_IO13 BK5_IO14 BK5_IO15 BK5_IO16 BK5_IO17 BK5_IO18 BK5_IO19 GND BK5_IO20 BK5_IO21 BK5_IO22 BK5_IO23 BK5_IO24 BK5_IO25 BK5_IO26 BK5_IO27 sysIO Bank 4 4 4 4 4 4 4 4 4 4 4 4 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 80P 80N 81P 81N 82P 82N 83P 83N 84P 84N 85P 85N 86P 86N 87P 87N 88P 88N 89P 89N 90P 90N 91P 91N 92P 92N 93P 93N 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B LVDS GDX Pair/Polarity Block MRB 74P 75N 75P 76N 76P 77N 77P 78N 78P 79N 79P 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 SERDES Mode I/O Pin1 HSI5A_SOUTP HSI5A_SYDT5 HSI5A_SINN HSI5A_SINP Note 4 FIFO4B_STRDb6 HSI4B_CDRRSTb HSI4B_SINP HSI4B_SINN HSI4B_SYDT5 HSI4_CSLOCK HSI4B_SOUTP HSI4B_SOUTN Note 4 FIFO5B_STRDb6 HSI5B_CDRRSTb HSI5B_SYDT5 HSI5B_SOUTP HSI5B_SOUTN Note 4 HSI5_CSLOCK HSI5B_SINP HSI5B_SINN SERDES Mode I/O Cell2 HSI5A_RXD9/TXD9 HSI5A_RXD8/TXD8 HSI5A_RXD7/TXD7 HSI5A_RXD6/TXD6 HSI5A_RXD5/TXD5 HSI5A_RXD4/TXD4 HSI5A_RXD3/TXD3 HSI5A_RXD2/TXD2 HSI5A_RXD1/TXD1 HSI5A_RXD0/TXD0 HSI5A_SYDT5 HSI4B_RECCLK HSI4B_RXD9/TXD9 HSI4B_RXD8/TXD8 HSI4B_RXD7/TXD7 HSI4B_RXD6/TXD6 HSI4B_RXD5/TXD5 HSI4_RXD4/TXD4 HSI4B_RXD3/TXD3 HSI4B_RXD2/TXD2 HSI4B_RXD1/TXD1 HSI4B_RXD0/TXD0 HSI4B_SYDT5 HSI5B_RECCLK HSI5B_RXD9/TXD9 HSI5B_RXD8/TXD8 HSI5B_RXD7/TXD7 HSI5B_RXD6/TXD6 HSI5B_RXD5/TXD5 HSI5B_RXD4/TXD4 HSI5B_RXD3/TXD3 HSI5B_RXD2/TXD2 HSI5B_RXD1/TXD1 FIFO Mode I/O Cell/Pin3 FIFO5A_DIN9/DOUT9 FIFO5A_DIN8/DOUT8 FIFO5A_DIN7/DOUT7 FIFO5A_DIN6/DOUT6 FIFO5A_DIN5/DOUT5 FIFO5A_DIN4/DOUT4 FIFO5A_DIN3/DOUT3 FIFO5A_DIN2/DOUT2 FIFO5A_DIN1/DOUT1 FIFO5A_DIN0/DOUT0 FIFO5A_FULL FIFO4B_EMPTY FIFO4B_FIFORSTb FIFO4B_DIN9/DOUT9 FIFO4B_DIN8/DOUT8 FIFO4B_DIN7/DOUT7 FIFO4B_DIN6/DOUT6 FIFO4B_DIN5/DOUT5 FIFO4B_DIN4/DOUT4 FIFO4B_DIN3/DOUT3 FIFO4B_DIN2/DOUT2 FIFO4B_DIN1/DOUT1 FIFO4B_DIN0/DOUT0 FIFO4B_FULL FIFO5B_EMPTY FIFO5B_FIFORSTb FIFO5B_DIN9/DOUT9 FIFO5B_DIN8/DOUT8 FIFO5B_DIN7/DOUT7 FIFO5B_DIN6/DOUT6 FIFO5B_DIN5/DOUT5 FIFO5B_DIN4/DOUT4 FIFO5B_DIN3/DOUT3 FIFO5B_DIN2/DOUT2 FIFO5B_DIN1/DOUT1 484 fpBGA F8 D7 D6 A6 A5 G9 G8 C5 B5 D5 C4 GND B4 A4 GND D2 D3 F5 E4 J7 J6 D1 E1 F4 E3 H7 H6 GND E2 F2 G4 H5 F1 G1 G3 G2 GND K7 K6 H4 H3 H1 H2 J5 K5 64 Lattice Semiconductor ispGDX2 Family Data Sheet ispGDX2-256 Logic Signal Connections (Continued) Signal Name GND BK5_IO28 BK5_IO29 BK5_IO30 BK5_IO31/ CLK_OUT0 GCLK/CE0 SEL0 SEL1 GCLK/CE1 BK6_IO0/ CLK_OUT1 BK6_IO1 BK6_IO2 BK6_IO3 GND BK6_IO4 BK6_IO5 BK6_IO6 BK6_IO7 BK6_IO8 BK6_IO9 BK6_IO10 BK6_IO11 GND BK6_IO12 BK6_IO13 BK6_IO14 BK6_IO15 BK6_IO16 BK6_IO17 BK6_IO18 BK6_IO19 GND BK6_IO20/ PLL_FB1 BK6_IO21/ VREF6 BK6_IO22 BK6_IO23 BK6_IO24 BK6_IO25 BK6_IO26 BK6_IO27 BK6_IO28 BK6_IO29 BK6_IO30 BK6_IO31 sysIO Bank 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 LVDS GDX Pair/Polarity Block MRB 94P 94N 95P 95N CLK0P CLK0N 96N 96P 97N 97P 98N 98P 99N 99P 100N 100P 101N 101P 102N 102P 103N 103P 104N 104P 105N 105P 106N 106P 107N 107P 108N 108P 109N 109P 110N 110P 111N 111P 5B 5B 5B 5B 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SERDES Mode I/O Pin1 SS_CLKIN0P SS_CLKIN0N SS_CLKOUT0N SS_CLKOUT0P HSI7A_CDRRST FIFO7A_STRDb6 HSI7A_SINN HSI7A_SINP HSI7A_SYDT5 HSI7_CSLOCK HSI7A_SOUTN HSI7A_SOUTP Note 4 FIFO6A_STRDb6 HSI6A_CDRRSTb HSI6A_SOUTN HSI6A_SOUTP HSI6A_SYDT HSI6_CSLOCK HSI6A_SINN HSI6A_SINP Note 4 5 SERDES Mode I/O Cell2 HSI5B_RXD0/TXD0 HSI5B_SYDT5 HSI7A_RECCLK HSI7A_RXD9/TXD9 HSI7A_RXD8/TXD8 HSI7A_RXD7/TXD7 HSI7A_RXD6/TXD6 HSI7A_RXD5/TXD5 HSI7A_RXD4/TXD4 HSI7A_RXD3/TXD3 HSI7A_RXD2/TXD2 HSI7A_RXD1/TXD1 HSI7A_RXD0/TXD0 HSI7A_SYDT5 HSI6_RECCLK HSI6A_RXD9/TXD9 HSI6A_RXD8/TXD8 HSI6A_RXD7/TXD7 HSI6A_RXD6/TXD6 HSI6A_RXD5/TXD5 HSI6A_RXD4/TXD4 HSI6A_RXD3/TXD3 HSI6A_RXD2/TXD2 HSI6A_RXD1/TXD1 HSI6A_RXD0/TXD0 HSI6A_SYDT5 - FIFO Mode I/O Cell/Pin3 FIFO5B_DIN0/DOUT0 FIFO5B_FULL FIFO7A_EMPTY FIFO7A_FIFORSTb FIFO7A_DIN9/DOUT9 FIFO7A_DIN8/DOUT8 FIFO7A_DIN7/DOUT7 FIFO7A_DIN6/DOUT6 FIFO7A_DIN5/DOUT5 FIFO7A_DIN4/DOUT4 FIFO7A_DIN3/DOUT3 FIFO7A_DIN2/DOUT2 FIFO7A_DIN1/DOUT1 FIFO7A_DIN0/DOUT0 FIFO7A_ FULL FIFO6A_EMPTY FIFO6A_FIFORSTb FIFO6A_DIN9/DOUT9 FIFO6A_DIN8/DOUT8 FIFO6A_DIN7/DOUT7 FIFO6A_DIN6/DOUT6 FIFO6A_DIN5/DOUT5 FIFO6A_DIN4/DOUT4 FIFO6A_DIN3/DOUT3 FIFO6A_DIN2/DOUT2 FIFO6A_DIN1/DOUT1 FIFO6A_DIN0/DOUT0 FIFO6A_ FULL 484 fpBGA GND J4 J3 L6 L5 L4 K3 K2 N1 N6 N5 M5 M6 GND P6 P5 N3 N2 P3 P1 N7 P7 GND R3 R2 R1 T1 T2 T3 U1 U2 GND R5 T6 U4 V4 V3 V2 R6 R7 W1 V1 W2 W3 65 Lattice Semiconductor ispGDX2 Family Data Sheet ispGDX2-256 Logic Signal Connections (Continued) Signal Name GND TDI GOE0 GND BK7_IO0 BK7_IO1 BK7_IO2 BK7_IO3 BK7_IO4 BK7_IO5 BK7_IO6 BK7_IO7 BK7_IO8 BK7_IO9 BK7_IO10/ VREF7 BK7_IO11 GND BK7_IO12 BK7_IO13 BK7_IO14/ PLL_RST1 BK7_IO15 BK7_IO16 BK7_IO17 BK7_IO18 BK7_IO19 GND BK7_IO20 BK7_IO21 BK7_IO22 BK7_IO23 BK7_IO24 BK7_IO25 BK7_IO26 BK7_IO27 GND BK7_IO28 BK7_IO29/ PLL_LOCK1 BK7_IO30 BK7_IO31 sysIO Bank 6 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 LVDS GDX Pair/Polarity Block MRB 112P 112N 113P 113N 114P 114N 115P 115N 116P 116N 117P 117N 118P 118N 119P 119N 120P 120N 121P 121N 122P 122N 123P 123N 124P 124N 125P 125N 126P 126N 127P 127N 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 6B 6B 6B 6B 6B 6B 6B 6B 6B 6B 6B 6B 6B 6B 6B 6B 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SERDES Mode I/O Pin1 FIFO7B_STRDb6 HSI7B_CDRRSTb HSI7B_SYDT5 HSI7B_SINP HSI7B_SINN Note 4 HSI7B_SOUTP HSI7B_SOUTN FIFO6B_STRDb6 HSI6B_CDRRSTb HSI6B_SYDT5 HSI6B_SOUTP HSI6B_SOUTN Note 4 HSI6B_SINP HSI6B_SINN SERDES Mode I/O Cell2 HSI7B_RECCLK HSI7B_RXD9/TXD9 HSI7B_RXD8/TXD8 HSI7B_RXD7/TXD7 HSI7B_RXD6/TXD6 HSI7B_RXD5/TXD5 HSI7B_RXD4/TXD4 HSI7B_RXD3/TXD3 HSI7B_RXD2/TXD2 HSI7B_RXD1/TXD1 HSI7B_RXD0/TXD0 HSI7B_SYDT5 HSI6B_RECCLK HSI6B_RXD9/TXD9 HSI6B_RXD8/TXD8 HSI6B_RXD7/TXD7 HSI6B_RXD6/TXD6 HSI6B_RXD5/TXD5 HSI6B_RXD4/TXD4 HSI6B_RXD3/TXD3 HSI6B_RXD2/TXD2 HSI6B_RXD1/TXD1 HSI6B_RXD0/TXD0 HSI6B_SYDT5 FIFO Mode I/O Cell/Pin3 FIFO7B_ EMPTY FIFO7B_FIFORSTb FIFO7B_DIN9/DOUT9 FIFO7B_DIN8/DOUT8 FIFO7B_DIN7/DOUT7 FIFO7B_DIN6/DOUT6 FIFO7B_DIN5/DOUT5 FIFO7B_DIN4/DOUT4 FIFO7B_DIN3/DOUT3 FIFO7B_DIN2/DOUT2 FIFO7B_DIN1/DOUT1 FIFO7B_DIN0/DOUT0 FIFO7B_FULL FIFO6B_FIFORSTb FIFO6B_DIN9/DOUT9 FIFO6B_DIN8/DOUT8 FIFO6B_DIN7/DOUT7 FIFO6B_DIN6/DOUT6 FIFO6B_DIN5/DOUT5 FIFO6B_DIN4/DOUT4 FIFO6B_DIN3/DOUT3 FIFO6B_DIN2/DOUT2 FIFO6B_DIN1/DOUT1 FIFO6B_DIN0/DOUT0 FIFO6B_ EMPTY FIFO6B_FULL 484 fpBGA GND AA4 Y4 GND AB4 AB5 V6 W5 T8 T9 W6 Y5 AA5 AA6 U8 U9 GND W7 W8 AB6 AB7 Y7 AA7 W9 Y8 GND T10 T11 AA8 AB8 W10 Y9 U10 U11 GND W11 Y10 AA10 AB9 66 Lattice Semiconductor ispGDX2 Family Data Sheet ispGDX2-256 Logic Signal Connections (Continued) Signal Name TOE sysIO Bank LVDS GDX Pair/Polarity Block MRB SERDES Mode I/O Pin1 SERDES Mode I/O Cell2 FIFO Mode I/O Cell/Pin3 484 fpBGA AB10 1. The signals in this column route to/from the assigned pins of the associated I/O cell. 2. The signals in this column use the I/O cell. If a receiver signal is present in the I/O cell, the associated pin is available for output only. When transmit data (TXD) is present in the cell, the associated pin is available for input only. 3. The DOUT outputs are routed to GRP through the input register of the cell and the DIN inputs are routed direct from the associated pins in FIFO only mode. In SERDES with FIFO mode, the FULL and EMPTY ﬂags are routed to the associated pins through the output MUX and the pins. 4. If the Source Synchronous Receiver is used in the HSI Block, this pin is unavailable for another use and must be left unconnected. 5. The SYDT signal has two routing options. If direct output through the dedicated pin is used, the I/O cell (the whole HSI Block) is not available for transmitter. The SYDT in the I/O Cell column is routed to the GRP through the input register of the cell and frees the I/O cell for transmitter. 6. FIFO_STRDb ﬂag output is used in SERDES with FIFO Mode only. 7. sysHSI Source Synchronous Receive Mode is not available for channel 3A. 67 Lattice Semiconductor ispGDX2 Family Data Sheet Part Number Description LX XXX X X – XX FXXX X Device Family LX Device Number 64 = 64 I/Os 128 = 128 I/Os 256 = 256 I/Os sysHSI Support Blank = Supports sysHSI E = No sysHSI support Power Supply Voltage V = 3.3V B = 2.5V C = 1.8V Grade C = Commercial I = Industrial Package F100 = 100-Ball fpBGA FN100 = Lead-Free 100-Ball fpBGA F208 = 208-Ball fpBGA FN208 = Lead-Free 208-Ball fpBGA F484 = 484-Ball fpBGA FN484 = Lead-Free 484-Ball fpBGA Speed 3 = 3.0ns 32 = 3.2ns 35 = 3.5ns 5 = 5.0ns Ordering Information Conventional Packaging Commercial Family LX64V LX128V LX256V LX64B LX128B LX256B LX64C LX128C LX256C Part Number LX64V-3F100C LX64V-5F100C LX128V-32F208C LX128V-5F208C LX256V-35F484C LX256V-5F484C LX64B-3F100C LX64B-5F100C LX128B-32F208C LX128B-5F208C LX256B-35F484C LX256B-5F484C LX64C-3F100C LX64C-5F100C LX128C-32F208C LX128C-5F208C LX256C-35F484C LX256C-5F484C I/Os 64 64 128 128 256 256 64 64 128 128 256 256 64 64 128 128 256 256 Voltage 3.3 3.3 3.3 3.3 3.3 3.3 2.5 2.5 2.5 2.5 2.5 2.5 1.8 1.8 1.8 1.8 1.8 1.8 tPD 3 5 3.2 5 3.5 5 3 5 3.2 5 3.5 5 3 5 3.2 5 3.5 5 Package fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Pins 100 100 208 208 484 484 100 100 208 208 484 484 100 100 208 208 484 484 Grade C C C C C C C C C C C C C C C C C C 68 Lattice Semiconductor “E-Series” Commercial Family LX64EV LX128EV LX256EV LX64EB LX128EB LX256EB LX64EC LX128EC Part Number LX64EV-3F100C LX64EV-5F100C LX128EV-32F208C LX128EV-5F208C LX256EV-35F484C LX256EV-5F484C LX64EB-3F100C LX64EB-5F100C LX128EB-32F208C LX128EB-5F208C LX256EB-35F484C LX256EB-5F484C LX64EC-3F100C LX64EC-5F100C LX128EC-32F208C LX128EC-5F208C I/Os 64 64 128 128 256 256 64 64 128 128 256 256 64 64 128 128 Voltage 3.3 3.3 3.3 3.3 3.3 3.3 2.5 2.5 2.5 2.5 2.5 2.5 1.8 1.8 1.8 1.8 tPD 3 5 3.2 5 3.5 5 3 5 3.2 5 3.5 5 3 5 3.2 5 ispGDX2 Family Data Sheet Package fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Pins 100 100 208 208 484 484 100 100 208 208 484 484 100 100 208 208 Grade C C C C C C C C C C C C C C C C “E-Series” Industrial Family LX64EV LX64EB LX64EC Part Number LX64EV-5F100I LX64EB-5F100I LX64EC-5F100I I/Os 64 64 64 128 128 128 256 256 256 Voltage 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8 tPD 5 5 5 5 5 5 5 5 5 Package fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Pins 100 100 100 208 208 208 484 484 484 Grade I I I I I I I I I LX128EV LX128EV-5F208I LX128EB LX128EB-5F208I LX128EC LX128EC-5F208I LX256EV LX256EV-5F484I LX256EB LX256EB-5F484I LX256EC LX256EC-5F484I 69 Lattice Semiconductor Lead-Free Packaging Commercial Family LX64V LX64B LX64C LX128V LX128B LX128C LX256V LX256B LX256C Part Number LX64V-3FN100C LX64V-5FN100C LX64B-3FN100C LX64B-5FN100C LX64C-3FN100C LX64C-5FN100C LX128V-32FN208C LX128V-5FN208C LX128B-32FN208C LX128B-5FN208C LX128C-32FN208C LX128C-5FN208C LX256V-35FN484C LX256V-5FN484C LX256B-35FN484C LX256B-5FN484C LX256C-35FN484C LX256C-5FN484C I/Os 64 64 64 64 64 64 128 128 128 128 128 128 256 256 256 256 256 256 Voltage 3.3 3.3 2.5 2.5 1.8 1.8 3.3 3.3 2.5 2.5 1.8 1.8 3.3 3.3 2.5 2.5 1.8 1.8 tPD 3.0 5.0 3.0 5.0 3.0 5.0 3.2 5.0 3.2 5.0 3.2 5.0 3.5 5.0 3.5 5.0 3.5 5.0 ispGDX2 Family Data Sheet Package Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Pins 100 100 100 100 100 100 208 208 208 208 208 208 484 484 484 484 484 484 Grade C C C C C C C C C C C C C C C C C C “E-Series” Commercial Family LX64EV LX64EB LX64EC LX128EV LX128EB LX128EC LX256EV LX256EB LX256EC Part Number LX64EV-3FN100C LX64EV-5FN100C LX64EB-3FN100C LX64EB-5FN100C LX64EC-3FN100C LX64EC-5FN100C LX128EV-32FN208C LX128EV-5FN208C LX128EB-32FN208C LX128EB-5FN208C LX128EC-32FN208C LX128EC-5FN208C LX256EV-35FN484C LX256EV-5FN484C LX256EB-35FN484C LX256EB-5FN484C LX256EC-35FN484C LX256EC-5FN484C I/Os 64 64 64 64 64 64 128 128 128 128 128 128 256 256 256 256 256 256 Voltage 3.3 3.3 2.5 2.5 1.8 1.8 3.3 3.3 2.5 2.5 1.8 1.8 3.3 3.3 2.5 2.5 1.8 1.8 tPD 3.0 5.0 3.0 5.0 3.0 5.0 3.2 5.0 3.2 5.0 3.2 5.0 3.5 5.0 3.5 5.0 3.5 5.0 Package Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Pins 100 100 100 100 100 100 208 208 208 208 208 208 484 484 484 484 484 484 Grade C C C C C C C C C C C C C C C C C C 70 Lattice Semiconductor “E-Series” Industrial Family LX64EV LX64EB LX64EC LX128EV LX128EB LX128EC LX256EV LX256EB LX256EC Part Number LX64EV-5FN100I LX64EB-5FN100I LX64EC-5FN100I LX128EV-5FN208I LX128EB-5FN208I LX128EC-5FN208I LX256EV-5FN484I LX256EB-5FN484I LX256EC-5FN484I I/Os 64 64 64 128 128 128 256 256 256 Voltage 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8 tPD 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 ispGDX2 Family Data Sheet Package Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Pins 100 100 100 208 208 208 484 484 484 Grade I I I I I I I I I 71 Lattice Semiconductor ispGDX2 Family Data Sheet For Further Information In addition to this data sheet, the following Lattice technical notes may be helpful when designing with the ispGDX2 Family: • • • • sysIO Design and Usage Guidelines (TN1000) sysCLOCK PLL Design and Usage Guidelines (TN1003) sysHSI Usage Guide (TN1020) Power Estimation in ispGDX2 Devices (TN1021) 72

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