MED-FILT-X2-UT1

Median Filter IP Core User’s Guide December 2010 IPUG87_01.0 Table of Contents Chapter 1. Introduction .......................................................................................................................... 4 Quick Facts ........................................................................................................................................................... 4 Features ................................................................................................................................................................ 4 Chapter 2. Functional Description ........................................................................................................ 6 Key Concepts........................................................................................................................................................ 6 Block Diagram....................................................................................................................................................... 6 Active Region Selection ........................................................................................................................................ 7 Median Arithmetic Unit .......................................................................................................................................... 7 Primary I/O ............................................................................................................................................................ 8 Interface Descriptions ........................................................................................................................................... 8 Video Input/Output ....................................................................................................................................... 8 Timing Specifications ............................................................................................................................................ 9 Chapter 3. Parameter Settings ............................................................................................................ 10 Basic Options Tab............................................................................................................................................... 10 Filter Specifications .................................................................................................................................... 11 Active Region ............................................................................................................................................. 11 Data Features ............................................................................................................................................ 12 Advanced Options Tab........................................................................................................................................ 12 Memory Type ............................................................................................................................................. 12 Optional Ports ............................................................................................................................................ 12 Synthesis Options ...................................................................................................................................... 12 Chapter 4. IP Core Generation............................................................................................................. 13 Licensing the IP Core.......................................................................................................................................... 13 Getting Started .................................................................................................................................................... 13 IPexpress-Created Files and Top Level Directory Structure............................................................................... 15 Instantiating the Core .......................................................................................................................................... 16 Running Functional Simulation ........................................................................................................................... 16 Synthesizing and Implementing the Core in a Top-Level Design ....................................................................... 16 Hardware Evaluation........................................................................................................................................... 17 Enabling Hardware Evaluation in Diamond................................................................................................ 17 Enabling Hardware Evaluation in ispLEVER.............................................................................................. 17 Updating/Regenerating the IP Core .................................................................................................................... 18 Regenerating an IP Core in Diamond ........................................................................................................ 18 Regenerating an IP Core in ispLEVER ...................................................................................................... 18 Chapter 5. Support Resources ............................................................................................................ 20 Lattice Technical Support.................................................................................................................................... 20 Online Forums............................................................................................................................................ 20 Telephone Support Hotline ........................................................................................................................ 20 E-mail Support ........................................................................................................................................... 20 Local Support ............................................................................................................................................. 20 Internet ....................................................................................................................................................... 20 References.......................................................................................................................................................... 20 LatticeECP2/M ........................................................................................................................................... 20 LatticeECP3 ............................................................................................................................................... 20 LatticeXP2.................................................................................................................................................. 20 Revision History .................................................................................................................................................. 20 Appendix A. Resource Utilization ....................................................................................................... 21 LatticeXP2 FPGAs .............................................................................................................................................. 21 Ordering Part Number................................................................................................................................ 21 © 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. IPUG87_01.0, December 2010 2 Median Filter IP Core User’s Guide Lattice Semiconductor Table of Contents LatticeECP3 FPGAs............................................................................................................................................ 21 Ordering Part Number............................................................................................................................... 21 LatticeECP2/S FPGAs ........................................................................................................................................ 21 Ordering Part Number............................................................................................................................... 22 LatticeECP2M/S FPGAs ..................................................................................................................................... 22 Ordering Part Number................................................................................................................................ 22 IPUG87_01.0, December 2010 3 Median Filter IP Core User’s Guide Chapter 1: Introduction This user’s guide provides a description of the Median Filter IP core. Median filtering is a popular method of noise removal, employed extensively in applications involving speech, signal and image processing. This non-linear technique has proven to be a good alternative to linear filtering as it can effectively suppress impulse noise while preserving edge information. The core’s flexible architecture supports a wide variety of video frame sizes on LatticeECP2/S™, LatticeECP2M/S™, LatticeXP2™, and LatticeECP3™ devices. A simple IO handshake makes the core suitable for either streaming or bursty input video data. Quick Facts Table 1-1 gives quick facts about the Median Filter IP core. Table 1-1. Median Filter IP Core Quick Facts Median Filter Core Frame Size:320x240 Window Size: 3x3 FPGA Familes Supported Core Requirements LUTs EBRs Registers LFXP2-5E LFE2-6E LFE2M20E LFE3-17EA LFXP2-5E LFE2-6E LFE2M20E LFE3-17EA LFXP2-17E LFE2-12E LFE2M20E LFE3-17EA 700 2900 11500 1 1 2 550 2200 6900 700 2900 sysDSP blocks 0 LUTs LatticeECP2/S EBRs Registers 1 1 2 2200 6900 700 2900 0 LUTs LatticeECP2M/S EBRs Registers 1 1 2 2200 6900 700 2900 0 LUTs EBRs Registers sysDSP blocks 11500 1 1 2 550 2200 6900 0 Lattice Diamond™ 1.1 or ispLEVER® 8.1SP1 Lattice Implementation Design Tool Support 11500 550 sysDSP blocks LatticeECP3 11500 550 sysDSP blocks Resource Utilization Frame Size:128x128 Window Size: 7x7 LatticeECP2/S, LatticeECP2M/S, LatticeXP2, LatticeECP3 Minimum Device Required LatticeXP2 Frame Size:256x256 Window Size: 5x5 Synopsys® Synplify™ Pro for Lattice D-2010.03L-SP1 Synthesis Aldec® Active-HDL™ 8.2 Lattice Edition II Simulation Mentor Graphics® ModelSim™ SE 6.3F Features • Single color plane • Three filter window sizes: 3x3, 5x5 and 7x7 • Configurable input data width IPUG87_01.0, December 2010 4 Median Filter IP Core User’s Guide Lattice Semiconductor Introduction • Input frame size set at compile-time • Static active region selection • Edge mode handling: COPY, MIRROR or VALUE • Optional clock enable and synchronous reset ports IPUG87_01.0, December 2010 5 Median Filter IP Core User’s Guide Chapter 2: Functional Description Key Concepts Median filter is a spatial filtering operation, so it uses a 2-D mask that is applied to each pixel in the input image. To apply the mask means to centre it on a pixel, evaluating the covered pixel brightness and determining which brightness value is the median value. The median value is determined by placing the brightness in ascending order and selecting the centre value. The obtained median value will be the value for that pixel in the output image. An example is shown in Figure 2-1. Figure 2-1. Example of Median Value Brightness Values -1 0 1 -1 10 30 5 0 25 200 20 1 15 10 35 i Brightness Values in Order 5 10 10 15 20 25 30 35 200 Median j Block Diagram The high-level architecture of the Median Filter core is diagrammed in Figure 2-2. Figure 2-2. Median Filter IP Core Block Diagram dvalid_in frmsync_in din[ ] ready Windowing Logic Line Buffers Active Region Selection actregion upleft Windowing Function Median Logic Arithmetic Unit dvalid_out frmsync_out dout Input data is stored in line buffers, then passed to windowing logic for edge mode handling and data alignment. Optional control inputs allow real-time specification of the portion of the input frame used to generate output pixels (referred to as the “active region”). Windowed data are sent to the median arithmetic unit which chooses the median input pixel value. IPUG87_01.0, December 2010 6 Median Filter IP Core User’s Guide Lattice Semiconductor Functional Description Active Region Selection The Median Filter core may be configured to allow the user to dynamically alter the coordinates of the active region of the input frame. The active region concept is illustrated in Figure 2-3. Figure 2-3. Active Region 0,0 upleftx, uplefty Active Region upleftx+actwidth, uplefty+actheight VWIDTH, VHEIGHT The upleftx and uplefty ports set the coordinates of the first pixel in the input frame that will have a corresponding pixel in the output frame. The actwidth and actheight ports determine the region of pixels in the input frame that will have corresponding pixels in the output frame. Both sets of inputs – upleft and active region – are synchronized internally and delivered to the core logic at the appropriate time to avoid anomalies when moving from frame to frame. Median Arithmetic Unit Different window sizes have different fast algorithms and implementations. The following description is based on the 3×3 window size. The scheme of median arithmetic unit of 3×3 window size is shown in Figure 2-4, which is much better than other solutions, since it needs a much lower number of basic nodes. This scheme uses the minimum exchange network required to produce the median from nine pixels by performing a partial sorting. Figure 2-4. 3x3 Median Arithmetic Unit Scheme Din1 Din2 Sort Sort Sort Sort Sort Sort Din3 Din4 Din5 Sort Dout Din6 Din7 Din8 Din9 Each basic node allows sorting of three elements. To do that, each node compares the three elements by means of three comparators, using its output in three 3:1 multiplexers, as shwon in Figure 2-5. IPUG87_01.0, December 2010 7 Median Filter IP Core User’s Guide Lattice Semiconductor Functional Description Figure 2-5. Scheme for Each Basic Node A Compare B Higher A B Compare Sort C C Lower Compare Primary I/O Table 2-1. Primary I/O Port Size I/O 1 I Description Global Signals clk System clock rstn 1 I System wide asynchronous active-low reset signal ce 1 I Active high clock enable (optional) sr 1 I Active high synchronous reset (optional) ready 1 O Core is ready for input dvalid_in 1 I Input valid Video Input frmsync_in din 1 I Current pixel is at row 0, column 0 4 - 24 I Pixel data in 1 O Output valid 1 O Current output pixel is at row 0, column 0 4 - 24 O Pixel data out Video Output dvalid_out frmsync_out dout Dynamic Frame Size and Active Region Controls (Optional) pwrite 1 I Internal regs write enable paddr 4 I Internal regs address pwdat 8, 16, 32, 64 I Internal regs write data prdat 8, 16, 32, 64 O Internal regs read data Miscellaneous tags_in TAGS_WIDTH I Tags input tags_out TAGS_WIDTH O Tags output Interface Descriptions Video Input/Output The Median Filter uses a simple handshake to pass pixel data into the core. The core asserts its ready output when it is ready to receive data. When the driving module has data to give the core, it drives the core's dvalid_in port to a '1' synchronously with the rising edge of the clk signal, providing the input pixel data on port din. The frmsync_in IPUG87_01.0, December 2010 8 Median Filter IP Core User’s Guide Lattice Semiconductor Functional Description input should be driven to a '1' during the clock cycle when the first pixel of the first row in the incoming video frame is active. Correspondingly, dvalid_out is active when valid output pixel data is available on dout, and frmsync_out marks the first pixel, first row of the output video frame. Timing Specifications Timing diagrams for the Median Filter IP core are given in Figure 2-6 and Figure 2-7. Figure 2-6. Timing Diagram for Median Filter with Continuous Inputs clk ready frmsync_in dvalid_in din d0 d1 d2 d3 d4 d5 d6 d7 d8 d0 d1 d2 d3 d4 d5 d9 d10 d11 d12 d13 d14 d7 d8 d9 d10 d11 frmsync_out dvalid_out dout d6 d12 Figure 2-7. Timing Diagram for Median Filter with Gaps in Inputs clk ready frmsync_in dvalid_in din d0 d1 d2 d3 d4 d5 d6 frmsync_out dvalid_out dout IPUG87_01.0, December 2010 d0 d1 d2 9 d3 d4 Median Filter IP Core User’s Guide Chapter 3: Parameter Settings The IPexpress™ tool is used to create IP and architectural modules in the Diamond or ispLEVER software. Refer to “IP Core Generation” on page 13 for a description of how to generate the IP. The Median Filter IP core can be customized to suit a specific application by adjusting parameters prior to core generation. Since the values of some parameters affect the size of the resultant core, the maximum value for these parameters may be limited by the size of the target device. Table 3-1 provided the list of user configurable parameters for the Median Filter IP core. Table 3-1. Median Filter IP Core Parameters Parameter Range Data width Default 4 - 24 8 Video frame width 100 - 1200 320 Video frame height 100 - 1200 240 0 or 1 0 0 or 1 0 0 – (VWIDTH-1) 0 Dynamic frame size updating Dynamic region selecting Horizontal coordinates of first active pixel Vertical coordinates of first active pixel 0 – (VHEIGHT-1) 0 Active region width 1 – (VWIDTH-UPLEFTX-1) VWIDTH-1 Active region height 1 – (VHEIGHT-UPLEFTY-1) VHEIGHT-1 3x3, 5x5, 7x7 3x3 Edge mode VALUE, COPY, MIRROR VALUE Edge value 0 – (1 Regenerate IP/Module. 2. In the Select a Parameter File dialog box, choose the Lattice Parameter Configuration (.lpc) file of the IP core you wish to regenerate, and click Open. 3. The Select Target Core Version, Design Entry, and Device dialog box shows the current settings for the IP core in the Source Value box. Make your new settings in the Target Value box. 4. If you want to generate a new set of files in a new location, set the location in the LPC Target File box. The base of the .lpc file name will be the base of all the new file names. The LPC Target File must end with an .lpc extension. 5. Click Next. The IP core’s dialog box opens showing the current option settings. IPUG87_01.0, December 2010 18 Median Filter IP Core User’s Guide Lattice Semiconductor IP Core Generation 6. In the dialog box, choose desired options. To get information about the options, click Help. Also, check the About tab in the IPexpress tool for links to technical notes and user guides. The IP core might come with additional information. As the options change, the schematic diagram of the IP core changes to show the I/O and the device resources the IP core will need. 7. Click Generate. 8. Click the Generate Log tab to check for warnings and error messages. IPUG87_01.0, December 2010 19 Median Filter IP Core User’s Guide Chapter 5: Support Resources Lattice Technical Support There are a number of ways to receive technical support as listed below. Online Forums The first place to look is Lattice Forums (www.latticesemi.com/support/forums.cfm). Lattice Forums contain a wealth of knowledge and are actively monitored by Lattice Applications Engineers. Telephone Support Hotline Receive direct technical support for all Lattice products by calling Lattice Applications from 5:30 a.m. to 6 p.m. Pacific Time. • For USA and Canada: 1-800-LATTICE (528-8423) • For other locations: +1 503 268 8001 In Asia, call Lattice Applications from 8:30 a.m. to 5:30 p.m. Beijing Time (CST), +0800 UTC. Chinese and English language only. • For Asia: +86 21 52989090 E-mail Support • techsupport@latticesemi.com • techsupport-asia@latticesemi.com Local Support Contact your nearest Lattice sales office. Internet www.latticesemi.com References LatticeECP2/M • HB1003, LatticeECP2/M Family Handbook LatticeECP3 • HB1009, LatticeECP3 Family Handbook LatticeXP2 • DS1009, Lattice XP2 Datasheet Revision History Date Document Version December 2010 01.0 IPUG87_01.0, December 2010 IP Core Version Change Summary Initial release. 20 Median Filter IP Core User’s Guide Appendix A: Resource Utilization This appendix gives resource utilization information for Lattice FPGAs using the Median Filter IP core. IPexpress is the Lattice IP configuration utility, and is included as a standard feature of the ispLEVER design tools. Details regarding the usage of IPexpress can be found in the IPexpress and ispLEVER help system. For more information on the ispLEVER design tools, visit the Lattice web site at www.latticesemi.com. LatticeXP2 FPGAs Table A-1. Performance and Resource Utilization1 Frame Size Window Size Edge Mode Data Width Input Buffer Type Slices LUTs Registers fMAX 320x240 3x3 VALUE 8 EBR 546 697 568 214 256x256 5x5 VALUE 8 EBR 2198 2943 2211 214 128x128 7x7 VALUE 8 EBR 8132 11482 6934 171 1. Performance and utilization data are generated targeting an LFXP2-30E-7F484C device using Lattice Diamond 1.1 and Synplify Pro D2010.03L-SP1 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeXP2 family. Ordering Part Number The Ordering Part Number (OPN) for the Median Filter IP core on LatticeXP2 devices is MED-FILT-X2-U1. LatticeECP3 FPGAs Table A-2. Performance and Resource Utilization1 Frame Size Window Size Edge Mode Data Width Input Buffer Type Slices LUTs Registers fMAX 320x240 3x3 VALUE 8 EBR 534 680 570 255 256x256 5x5 VALUE 8 EBR 2179 2908 2209 231 128x128 7x7 VALUE 8 EBR 8184 11536 6909 191 1. Performance and utilization data are generated targeting an LFE3-70E-8FN484CES device using Lattice Diamond 1.1 and Synplify Pro D2010.03L-SP1 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP3 family. Ordering Part Number The Ordering Part Number (OPN) for the Median Filter IP core on LatticeECP3 devices is MED-FILT-E3-U1. LatticeECP2/S FPGAs Table A-3. Performance and Resource Utilization1 Frame Size Window Size Edge Mode Data Width Input Buffer Type Slices LUTs Registers fMAX 320x240 3x3 VALUE 8 EBR 546 697 568 225 256x256 5x5 VALUE 8 EBR 2198 2943 2211 223 128x128 7x7 VALUE 8 EBR 8132 11482 6934 206 1. Performance and utilization data are generated targeting an LFE2 35E-7F672C device using Lattice Diamond 1.1 and Synplify Pro D2010.03L-SP1 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP2/S family. IPUG87_01.0, December 2010 21 Median Filter IP Core User’s Guide Lattice Semiconductor Resource Utilization Ordering Part Number The Ordering Part Number (OPN) for the Median Filter IP core on LatticeECP2/S devices is MED-FILT-P2-U1. LatticeECP2M/S FPGAs Table A-4. Performance and Resource Utilization1 Frame Size Window Size Edge Mode Data Width Input Buffer Type Slices LUTs Registers fMAX 320x240 3x3 VALUE 8 EBR 546 697 568 224 256x256 5x5 VALUE 8 EBR 2198 2943 2211 254 128x128 7x7 VALUE 8 EBR 7796 11482 6934 188 1. Performance and utilization data are generated targeting an LFE2M20E-7F484C device using Lattice Diamond 1.1 and Synplify Pro D2010.03L-SP1 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP2M/S family. Ordering Part Number The Ordering Part Number (OPN) for the Median Filter IP core on LatticeECP2M/S devices is MED-FILT-PM-U1. IPUG87_01.0, December 2010 22 Median Filter IP Core User’s Guide