OR2T15A6S208-DB

ORCA™ Series 2 Device Datasheet June 2010 Select Devices Discontinued! Product Change Notifications (PCNs) have been issued to discontinue select devices in this data sheet. The original datasheet pages have not been modified and do not reflect those changes. Please refer to the table below for reference PCN and current product status. Product Line OR2C04A OR2C06A OR2C08A OR2C10A OR2C12A Ordering Part Number OR2C04A4T100-DB OR2C04A3T100I-DB OR2C04A4T144-DB OR2C04A3T144I-DB OR2C04A4J160-DB OR2C04A4S208-DB OR2C06A4T100-DB OR2C06A4T144-DB OR2C06A3T144I-DB OR2C06A4J160-DB OR2C06A3J160I-DB OR2C06A4S208-DB OR2C06A3S208I-DB OR2C06A3S240I-DB OR2C06A4BA256-DB OR2C06A3BA256I-DB OR2C08A3J160I-DB OR2C08A4S208-DB OR2C08A3S208I-DB OR2C08A3S240I-DB OR2C08A3M84I-D OR2C10A4J160-DB OR2C10A3J160I-DB OR2C10A4S208-DB OR2C10A3BA256I-DB OR2C10A4BA352-DB OR2C10A3BA352I-DB OR2C12A3S208-DB OR2C12A4S208-DB OR2C12A3S208I-DB OR2C12A3S240-DB OR2C12A4S240-DB OR2C12A3S240I-DB Product Status Reference PCN Discontinued PCN#02-06 Discontinued PCN#02-06 Discontinued PCN#02-06 Discontinued PCN#02-06 Discontinued PCN#02-06 5555 N.E. Moore Ct. z Hillsboro, Oregon 97124-6421 z Phone (503) 268-8000 z FAX (503) 268-8347 Internet: http://www.latticesemi.com Product Line OR2C12A (Cont’d) OR2C15A OR2C26A OR2C40A OR2T04A OR2T08A Ordering Part Number OR2C12A4BA256-DB OR2C12A3BA256I-DB OR2C12A4S304-DB OR2C12A3S304I-DB OR2C12A4BA352-DB OR2C12A3BA352I-DB OR2C12A4M84-D OR2C15A4S208-DB OR2C15A3S208I-DB OR2C15A3PS208I-DB OR2C15A4S240-DB OR2C15A3S240I-DB OR2C15A4PS240-DB OR2C15A3PS240I-DB OR2C15A4BA256-DB OR2C15A3BA256I-DB OR2C15A4S304-DB OR2C15A4BA352-DB OR2C15A3BA352I-DB OR2C15A3M84I-D OR2C26A4PS208-DB OR2C26A3PS208I-DB OR2C26A4PS208I-DB OR2C26A4PS240-DB OR2C26A3PS240I-DB OR2C26A4PS304-DB OR2C26A3PS304I-DB OR2C40A4PS208-DB OR2C40A3PS208I-DB OR2C40A4PS208I-DB OR2C40A4PS240-DB OR2C40A4PS304-DB OR2C40A3PS304I-DB OR2T04A4T100I-DB OR2T04A4T144-DB OR2T04A4S208I-DB OR2T08A5J160-DB OR2T08A4J160I-DB OR2T08A5S208-DB OR2T08A4S208-DB OR2T08A4S208I-DB OR2T08A4S240I-DB OR2T08A5BA256-DB OR2T08A4BA256-DB OR2T08A4BA256I-DB Product Status Reference PCN Discontinued PCN#02-06 Discontinued PCN#02-06 Discontinued PCN#02-06 Discontinued PCN#02-06 Discontinued PCN#02-06 Discontinued PCN#02-06 5555 N.E. Moore Ct. z Hillsboro, Oregon 97124-6421 z Phone (503) 268-8000 z FAX (503) 268-8347 Internet: http://www.latticesemi.com Product Line OR2T10A OR2T15A OR2T15B OR2T26A OR2T40A OR2T40B Ordering Part Number OR2T10A4J160I-DB OR2T10A4S208-DB OR2T10A4S208I-DB OR2T10A5S240-DB OR2T10A4S240-DB OR2T10A4BA256-DB OR2T15A7S208-DB OR2T15A6S208-DB OR2T15A6S208I-DB OR2T15A7S240-DB OR2T15A6S240-DB OR2T15A6S240I-DB OR2T15A7BA256-DB OR2T15A6BA256-DB OR2T15A7BA352-DB OR2T15A6M84-D OR2T15B8S208-DB OR2T15B7S208-DB OR2T15B7S208I-DB OR2T15B7S240I-DB OR2T15B8BA256-DB OR2T15B7BA256-DB OR2T15B7BA352-DB OR2T15B7BA352I-DB OR2T26A7S208-DB OR2T26A6S208-DB OR2T26A6S208I-DB OR2T26A7PS240-DB OR2T26A6PS240-DB OR2T26A6PS240I-DB OR2T26A6BA352I-DB OR2T26A6BC432-DB OR2T26A6BC432I-DB OR2T40A7PS208-DB OR2T40A6PS208-DB OR2T40A6PS208I-DB OR2T40A7PS240-DB OR2T40A6PS240-DB OR2T40A6PS240I-DB OR2T40A7BA352-DB OR2T40A6BA352I-DB OR2T40B7PS208I-DB OR2T40B8BA352-DB OR2T40B7BA352-DB OR2T40B7BA352I-DB OR2T40B8BC432-DB OR2T40B7BC432-DB OR2T40B7BC432I-DB Product Status Reference PCN Discontinued PCN#02-06 Discontinued PCN#09-10 Active / Orderable Discontinued PCN#12A-09 Discontinued Active / Orderable Discontinued Discontinued PCN#09-10 PCN#02-06 PCN#09-10 Discontinued PCN#02-06 Discontinued PCN#09-10 Active / Orderable Discontinued PCN#06-07 Discontinued PCN#02-06 Discontinued PCN#06-07 Discontinued PCN#02-06 Discontinued PCN#02-06 5555 N.E. Moore Ct. z Hillsboro, Oregon 97124-6421 z Phone (503) 268-8000 z FAX (503) 268-8347 Internet: http://www.latticesemi.com 5555 N.E. Moore Ct. z Hillsboro, Oregon 97124-6421 z Phone (503) 268-8000 z FAX (503) 268-8347 Internet: http://www.latticesemi.com Data Sheet November 2006 SE L D E IS C C T O D N E TI VI N C U E ED S ORCA® Series 2 Field-Programmable Gate Arrays Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High-performance, cost-effective, low-power 0.35 µm CMOS technology (OR2CxxA), 0.3 µm CMOS technology (OR2TxxA), and 0.25 µm CMOS technology (OR2TxxB), (four-input look-up table (LUT) delay less than 1.0 ns with -8 speed grade) High density (up to 43,200 usable, logic-only gates; or 99,400 gates including RAM) Up to 480 user I/Os (OR2TxxA and OR2TxxB I/Os are 5 V tolerant to allow interconnection to both 3.3 V and 5 V devices, selectable on a per-pin basis) Four 16-bit look-up tables and four latches/flip-flops per PFU, nibble-oriented for implementing 4-, 8-, 16-, and/or 32-bit (or wider) bus structures Eight 3-state buffers per PFU for on-chip bus structures Fast, on-chip user SRAM has features to simplify RAM design and increase RAM speed: — Asynchronous single port: 64 bits/PFU — Synchronous single port: 64 bits/PFU — Synchronous dual port: 32 bits/PFU Improved ability to combine PFUs to create larger RAM structures using write-port enable and 3-state buffers Fast, dense multipliers can be created with the multiplier mode (4 x 1 multiplier/PFU): — 8 x 8 multiplier requires only 16 PFUs — 30% increase in speed Flip-flop/latch options to allow programmable priority of synchronous set/reset vs. clock enable Enhanced cascadable nibble-wide data path capabilities for adders, subtractors, counters, multipliers, and comparators including internal fast-carry operation ■ ■ ■ ■ ■ ■ ■ ■ ■ Innovative, abundant, and hierarchical nibbleoriented routing resources that allow automatic use of internal gates for all device densities without sacrificing performance Upward bit stream compatible with the ORCA ATT2Cxx/ ATT2Txx series of devices Pinout-compatible with new ORCA Series 3 FPGAs TTL or CMOS input levels programmable per pin for the OR2CxxA (5 V) devices Individually programmable drive capability: 12 mA sink/6 mA source or 6 mA sink/3 mA source Built-in boundary scan (IEEE *1149.1 JTAG) and 3-state all I/O pins, (TS_ALL) testability functions Multiple configuration options, including simple, low pincount serial ROMs, and peripheral or JTAG modes for insystem programming (ISP) Full PCI bus compliance for all devices Supported by industry-standard CAE tools for design entry, synthesis, and simulation with ispLEVER Development System support (for back-end implementation) New, added features (OR2TxxB) have: — More I/O per package than the OR2TxxA family — No dedicated 5 V supply (VDD5) — Faster configuration speed (40 MHz) — Pin selectable I/O clamping diodes provide 5V or 3.3V PCI compliance and 5V tolerance — Full PCI bus compliance in both 5V and 3.3V PCI systems * IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc. Table 1. ORCA Series 2 FPGAs Device Usable Gates* # LUTs Registers Max User RAM Bits User I/Os Array Size OR2C04A/OR2T04A OR2C06A OR2C08A/OR2T08A OR2C10A/OR2T10A OR2C12A OR2C15A/OR2T15A/OR2T15B OR2C26A/OR2T26A OR2C40A/OR2T40A/OR2T40B 4,800—11,000 6,900—15,900 9,400—21,600 12,300—28,300 15,600—35,800 19,200—44,200 27,600—63,600 43,200—99,400 400 576 784 1024 1296 1600 2304 3600 400 576 724 1024 1296 1600 2304 3600 6,400 9,216 12,544 16,384 20,736 25,600 36,864 57,600 160 192 224 256 288 320 384 480 10 x 10 12 x 12 14 x 14 16 x 16 18 x 18 20 x 20 24 x 24 30 x 30 * The first number in the usable gates column assumes 48 gates per PFU (12 gates per four-input LUT/FF pair) for logic-only designs. The second number assumes 30% of a design is RAM. PFUs used as RAM are counted at four gates per bit, with each PFU capable of implementing a 16 x 4 RAM (or 256 gates) per PFU. Data Sheet November 2006 ORCA Series 2 FPGAs Table of Contents Contents Page Page Boundary-Scan Instructions................................. 57 ORCA Boundary-Scan Circuitry ..........................58 ORCA Timing Characteristics ..................................62 Estimating Power Dissipation ..................................63 OR2CxxA .............................................................63 OR2TxxA .............................................................65 OR2T15B and OR2T40B .....................................67 Pin Information ........................................................68 Pin Descriptions ...................................................68 Package Compatibility .........................................70 Compatibility with Series 3 FPGAs .......................72 Package Thermal Characteristics ..........................128 Theta JA ............................................................128 Theta JC ............................................................128 Theta JC ............................................................128 Theta JB ............................................................128 Package Coplanarity .............................................129 Package Parasitics ................................................129 Absolute Maximum Ratings ...................................131 Recommended Operating Conditions ...................131 Electrical Characteristics .......................................132 Timing Characteristics ...........................................134 Series 2 ..............................................................162 Measurement Conditions .......................................171 Output Buffer Characteristics ................................172 OR2CxxA ...........................................................172 OR2TxxA ...........................................................173 OR2TxxB ...........................................................174 Package Outline Drawings ....................................175 Terms and Definitions ........................................175 84-Pin PLCC ......................................................176 100-Pin TQFP ....................................................177 144-Pin TQFP ....................................................178 160-Pin QFP ......................................................179 208-Pin SQFP ....................................................180 208-Pin SQFP2 ..................................................181 240-Pin SQFP ....................................................182 240-Pin SQFP2 ..................................................183 256-Pin PBGA ...................................................184 304-Pin SQFP ....................................................185 304-Pin SQFP2 ..................................................186 352-Pin PBGA ...................................................187 432-Pin EBGA ...................................................188 Ordering Information .............................................189 SE L D E IS C C T O D N E TI VI N C U E ED S Features ....................................................................1 Description .................................................................3 ispLEVER Development System Overview ...............7 Architecture ...............................................................7 Programmable Logic Cells ........................................7 Programmable Function Unit .................................7 Look-Up Table Operating Modes ..........................9 Latches/Flip-Flops ...............................................17 PLC Routing Resources ......................................19 PLC Architectural Description ..............................24 Programmable Input/Output Cells ...........................27 Inputs ...................................................................27 Outputs ................................................................28 5 V Tolerant I/O (OR2TxxB) ................................29 PCI Compliant I/O ................................................29 PIC Routing Resources .......................................30 PIC Architectural Description ...............................31 PLC-PIC Routing Resources ...............................32 Interquad Routing ....................................................34 Subquad Routing (OR2C40A/OR2T40A Only) ....36 PIC Interquad (MID) Routing ...............................38 Programmable Corner Cells ....................................39 Programmable Routing ........................................39 Special-Purpose Functions ..................................39 Clock Distribution Network ....................................... 39 Primary Clock ......................................................39 Secondary Clock .................................................40 Selecting Clock Input Pins ...................................41 FPGA States of Operation .......................................42 Initialization ..........................................................42 Configuration .......................................................43 Start-Up ...............................................................44 Reconfiguration ...................................................44 Partial Reconfiguration ........................................45 Other Configuration Options ................................45 Configuration Data Format ......................................45 Using ispLEVER to Generate Configuration RAM Data ...................................46 Configuration Data Frame ...................................46 Bit Stream Error Checking .......................................49 FPGA Configuration Modes .....................................49 Master Parallel Mode ...........................................49 Master Serial Mode .............................................50 Asynchronous Peripheral Mode .......................... 51 Synchronous Peripheral Mode ............................51 Slave Serial Mode ...............................................52 Slave Parallel Mode .............................................52 Daisy Chain .........................................................53 Special Function Blocks ..........................................54 Single Function Blocks ........................................54 Boundary Scan ....................................................56 Contents 2 Lattice Semiconductor Data Sheet November 2006 ORCA Series 2 FPGAs Description The PLC architecture provides a balanced mix of logic and routing that allows a higher utilized gate/PFU than alternative architectures. The routing resources carry logic signals between PFUs and I/O pads. The routing in the PLC is symmetrical about the horizontal and vertical axes. This improves routability by allowing a bus of signals to be routed into the PLC from any direction. SE L D E IS C C T O D N E TI VI N C U E ED S The ORCA Series 2 series of SRAM-based FPGAs are an enhanced version of the ATT2C/2T architecture. The latest ORCA series includes patented architectural enhancements that make functions faster and easier to design while conserving the use of PLCs and routing resources. mable input/output cells (PICs). An array of PLCs is surrounded by PICs as shown in Figure 1. Each PLC contains a programmable function unit (PFU). The PLCs and PICs also contain routing resources and configuration RAM. All logic is done in the PFU. Each PFU contains four 16-bit look-up tables (LUTs) and four latches/flip-flops (FFs). The Series 2 devices can be used as drop-in replacements for the ATT2Cxx/ATT2Txx series, respectively, and they are also bit stream compatible with each other. The usable gate counts associated with each series are provided in Table 1. Both series are offered in a variety of packages, speed grades, and temperature ranges. Some examples of the resources required and the performance that can be achieved using these devices are represented in Table 2. The ORCA series FPGA consists of two basic elements: programmable logic cells (PLCs) and programTable 2. ORCA Series 2CA System Performance Function 16-bit loadable up/down counter 16-bit accumulator 8 x 8 parallel multiplier: — Multiplier mode, unpipelined1 — ROM mode, unpipelined2 — Multiplier mode, pipelined3 32 x 16 RAM: — Single port (read and write/ cycle)4 — Single port5 — Dual port6 36-bit parity check (internal) 32-bit address decode (internal) # PFUs Speed Grade Unit -3 -4 4 66.7 87.0 MHz 4 66.7 87.0 MHz 22 9 44 19.3 55.6 69.0 25.1 71.9 82.0 MHz MHz MHz 9 28.6 36.2 MHz 9 16 4 3.25 52.6 52.6 11.0 9.5 69.0 83.3 9.1 7.5 MHz MHz ns ns 1.Implemented using 4 x 1 multiplier mode (unpipelined), register-to-register, two 8-bit inputs, one 16-bit output. 2. Implemented using two 16 x 12 ROMs and one 12-bit adder, one 8-bit input, one fixed operand, one 16-bit output. 3. Implemented using 4 x 1 multiplier mode (fully pipelined), two 8-bit inputs, one 16-bit output (28 of 44 PFUs contain only pipelining registers). 4. Implemented using 16 x 4 synchronous single-port RAM mode allowing both read and write per clock cycle, including write/read address multiplexer. 5. Implemented using 16 x 4 synchronous single-port RAM mode allowing either read or write per clock cycle, including write/read address multiplexer. 6. Implemented using 16 x 2 synchronous dual-port RAM mode. Lattice Semiconductor 3 Data Sheet November 2006 ORCA Series 2 FPGAs Table 3. ORCA Series 2TA System Performance Speed Grade Function 4 Unit -4 -5 -6 -7 87.0 104.2 129.9 144.9 MHz SE L D E IS C C T O D N E TI VI N C U E ED S 16-bit loadable up/down counter 16-bit accumulator 8 x 8 parallel multiplier: — Multiplier mode, unpipelined1 — ROM mode, unpipelined2 — Multiplier mode, pipelined3 32 x 16 RAM: — Single port (read and write/ cycle)4 — Single port5 — Dual port6 36-bit parity check (internal) 32-bit address decode (internal) # PFUs 4 87.0 104.2 129.9 144.9 MHz 22 9 44 25.1 71.9 82.0 31.0 87.7 103.1 36.0 107.5 125.0 40.3 122.0 142.9 MHz MHz MHz 9 36.2 53.8 53.8 62.5 MHz 9 16 4 3.25 69.0 83.3 9.1 7.5 92.6 92.6 7.4 6.1 92.6 92.6 96.2 96.2 MHz MHz ns ns 5.6 5.2 4.6 4.3 1.Implemented using 4 x 1 multiplier mode (unpipelined), register-to-register, two 8-bit inputs, one 16-bit output. 2. Implemented using two 16 x 12 ROMs and one 12-bit adder, one 8-bit input, one fixed operand, one 16-bit output. 3. Implemented using 4 x 1 multiplier mode (fully pipelined), two 8-bit inputs, one 16-bit output (28 of 44 PFUs contain only pipelining registers). 4. Implemented using 16 x 4 synchronous single-port RAM mode allowing both read and write per clock cycle, including write/read address multiplexer. 5. Implemented using 16 x 4 synchronous single-port RAM mode allowing either read or write per clock cycle, including write/read address multiplexer. 6. Implemented using 16 x 2 synchronous dual-port RAM mode. 4 Lattice Semiconductor Data Sheet November 2006 ORCA Series 2 FPGAs Table 4. ORCA Series 2TB System Performance Function Speed Grade Unit -7 -8 4 131.6 149.3 MHz 4 131.6 149.3 MHz 22 9 44 37.7 103.1 123.5 44.8 120.5 142.9 MHz MHz MHz 9 57.5 69.4 MHz 9 16 4 3.25 97.7 97.7 112.4 112.4 6.1 5.1 4.8 4.0 MHz MHz ns ns SE L D E IS C C T O D N E TI VI N C U E ED S 16-bit loadable up/down counter 16-bit accumulator 8 x 8 parallel multiplier: — Multiplier mode, unpipelined1 — ROM mode, unpipelined2 — Multiplier mode, pipelined3 32 x 16 RAM: — Single port (read and write/ cycle)4 — Single port5 — Dual port6 36-bit parity check (internal) 32-bit address decode (internal) # PFUs 1.Implemented using 4 x 1 multiplier mode (unpipelined), register-to-register, two 8-bit inputs, one 16-bit output. 2. Implemented using two 16 x 12 ROMs and one 12-bit adder, one 8-bit input, one fixed operand, one 16-bit output. 3. Implemented using 4 x 1 multiplier mode (fully pipelined), two 8-bit inputs, one 16-bit output (28 of 44 PFUs contain only pipelining registers). 4. Implemented using 16 x 4 synchronous single-port RAM mode allowing both read and write per clock cycle, including write/read address multiplexer. 5. Implemented using 16 x 4 synchronous single-port RAM mode allowing either read or write per clock cycle, including write/read address multiplexer. 6. Implemented using 16 x 2 synchronous dual-port RAM mode. Lattice Semiconductor 5 Data Sheet November 2006 ORCA Series 2 FPGAs Description (continued) PL1 R1C1 R1C2 R1C3 R1C4 R1C5 R1C6 R1C7 R1C8 R1C9 PL2 R2C1 R2C2 R2C3 R2C4 R2C5 R2C6 R2C7 R2C8 R2C9 PL3 R3C1 R3C2 R3C3 R3C4 R3C5 R3C6 R3C7 R3C8 PL4 R4C1 R4C2 R4C3 R4C4 R4C5 R4C6 R4C7 PL5 R5C1 R5C2 R5C3 R5C4 R5C5 R5C6 PL6 R6C1 R6C2 R6C3 R6C4 R6C5 PL7 R7C1 R7C2 R7C3 R7C4 PL8 R8C1 R8C2 R8C3 R9C1 R9C2 R9C3 TMID PT10 PT11 PT12 PT13 PT14 PT15 PT16 PT17 PT18 R1C10 R1C11 R1C12 R1C13 R1C14 R1C15 R1C16 R1C17 R1C18 R2C10 R2C11 R2C12 R2C13 R2C14 R2C15 R2C16 R2C17 R2C18 R3C9 R3C10 R3C11 R3C12 R3C13 R3C14 R3C15 R13C16 R3C17 R3C18 R4C8 R4C9 R4C10 R4C11 R4C12 R4C13 R4C14 R4C15 R4C16 R4C17 R4C18 R5C7 R5C8 R5C9 R5C10 R5C11 R5C12 R5C13 R5C14 R5C15 R5C16 R5C17 R5C18 R6C6 R6C7 R6C8 R6C9 R6C10 R6C11 R6C12 R6C13 R6C14 R6C15 R6C16 R6C17 R6C18 R7C5 R7C6 R7C7 R7C8 R7C9 R7C10 R7C11 R7C12 R7C13 R7C14 R7C15 R7C16 R7C17 R7C18 R8C4 R8C5 R8C6 R8C7 R8C8 R8C9 R8C10 R8C11 R8C12 R8C13 R8C14 R8C15 R8C16 R8C17 R8C18 R9C4 R9C5 R9C6 R9C7 R9C8 R9C9 R9C10 R9C11 R9C12 R9C13 R9C14 R9C15 R9C16 R9C17 R9C18 PR9 PT9 PR8 PT8 PR7 PT7 PR6 PT6 PR5 PT5 PR4 PT4 PR3 PT3 PR2 PT2 PR1 PT1 PL9 SE L D E IS C C T O D N E TI VI N C U E ED S The FPGA’s functionality is determined by internal configuration RAM. The FPGA’s internal initialization/configuration circuitry loads the configuration data at powerup or under system control. The RAM is loaded by using one of several configuration modes. The configuration data resides externally in an EEPROM, EPROM, or ROM on the circuit board, or any other storage media. Serial ROMs provide a simple, low pin count method for configuring FPGAs, while the peripheral and JTAG configuration modes allow for easy, in-system programming (ISP). vIQ LMID PL10 R10C1 R10C2 R10C3 R10C4 R10C5 R10C6 R10C7 R10C8 R10C9 R10C10 R10C11 R10C12 R10C13 R10C14 R10C15 R10C16 R10C17 R10C18 RMID PL11 R11C1 R11C2 R11C3 R11C4 R11C5 R11C6 R11C7 R11C8 R11C9 R11C10 R11C11 R11C12 R11C13 R11C14 R11C15 R11C16 R11C17 R11C18 PR11 PL12 R12C1 R12C2 R12C3 R12C4 R12C5 R12C6 R12C7 R12C8 R12C9 R12C10 R12C11 R12C12 R12C13 R12C14 R12C15 R12C16 R12C17 R12C18 PR12 PL13 R13C1 R13C2 R13C3 R13C4 R13C5 R13C6 R13C7 R13C8 R13C9 R13C10 R13C11 R13C12 R13C13 R13C14 R13C15 R13C16 R13C17 R13C18 PR13 PL14 R14C1 R14C2 R14C3 R14C4 R14C5 R14C6 R14C7 R14C8 R14C9 R14C10 R14C11 R14C12 R14C13 R14C14 R14C15 R14C16 R14C17 R14C18 PR14 PL15 R15C1 R15C2 R15C3 R15C4 R15C5 R15C6 R15C7 R15C8 R15C9 R15C10 R15C11 R15C12 R15C13 R15C14 R15C15 R15C16 R15C17 R15C18 PR15 PL16 R16C1 R16C2 R16C3 R16C4 R16C5 R16C6 R16C7 R16C8 R16C9 R16C10 R16C11 R16C12 R16C13 R16C14 R16C15 R16C16 R16C17 R16C18 PR16 PL17 R17C1 R17C2 R17C3 R17C4 R17C5 R17C6 R17C7 R17C8 R17C9 R17C10 R17C11 R17C12 R17C13 R17C14 R17C15 R17C16 R17C17 R17C18 PR17 PL18 R18C1 R18C2 R18C3 R18C4 R18C5 R18C6 R18C7 R18C8 R18C9 R18C10 R18C11 R18C12 R18C13 R18C14 R18C15 R18C16 R18C17 R18C18 PR18 PR10 hIQ PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 BMID PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 5-6779(F) Figure 1. Series 2 Array 6 Lattice Semiconductor Data Sheet November 2006 ispLEVER Development System Overview or six-input logic functions. In ripple mode, the highspeed carry logic is used for arithmetic functions, the new multiplier function, or the enhanced data path functions. In memory mode, the LUTs can be used as a 16 x 4 read/write or read-only memory (asynchronous mode or the new synchronous mode) or a new 16 x 2 dual-port memory. SE L D E IS C C T O D N E TI VI N C U E ED S The ispLEVER development system interfaces to frontend design entry tools and provides the tools to produce a configured FPGA. In the design flow, the user defines the functionality of the FPGA at two points: at design entry and at the bit stream generation stage. ORCA Series 2 FPGAs Following design entry, the development system’s map, place, and route tools translate the netlist into a routed FPGA. Its bit stream generator is then used to generate the configuration data which is loaded into the FPGA’s internal configuration RAM. When using the bit stream generator, the user selects options that affect the functionality of the FPGA. Combined with the front-end tools, ispLEVER produces configuration data that implements the various logic and routing options discussed in this data sheet. Architecture The ORCA Series FPGA is comprised of two basic elements: PLCs and PICs. Figure 1 shows an array of programmable logic cells (PLCs) surrounded by programmable input/output cells (PICs). The Series 2 has PLCs arranged in an array of 20 rows and 20 columns. PICs are located on all four sides of the FPGA between the PLCs and the IC edge. The location of a PLC is indicated by its row and column so that a PLC in the second row and third column is R2C3. PICs are indicated similarly, with PT (top) and PB (bottom) designating rows and PL (left) and PR (right) designating columns, followed by a number. The routing resources and configuration RAM are not shown, but the interquad routing blocks (hIQ, vIQ) present in the Series 2 series are shown. Each PIC contains the necessary I/O buffers to interface to bond pads. The PICs also contain the routing resources needed to connect signals from the bond pads to/from PLCs. The PICs do not contain any useraccessible logic elements, such as flip-flops. Combinatorial logic is done in look-up tables (LUTs) located in the PFU. The PFU can be used in different modes to meet different logic requirements. The LUT’s configurable medium-/large-grain architecture can be used to implement from one to four combinatorial logic functions. The flexibility of the LUT to handle wide input functions, as well as multiple smaller input functions, maximizes the gate count/PFU. Programmable Logic Cells The programmable logic cell (PLC) consists of a programmable function unit (PFU) and routing resources. All PLCs in the array are identical. The PFU, which contains four LUTs and four latches/FFs for logic implementation, is discussed in the next section. Programmable Function Unit The PFUs are used for logic. Each PFU has 19 external inputs and six outputs and can operate in several modes. The functionality of the inputs and outputs depends on the operating mode. The PFU uses three input data buses (A[4:0], B[4:0], WD[3:0]), four control inputs (C0, CK, CE, LSR), and a carry input (CIN); the last is used for fast arithmetic functions. There is a 5-bit output bus (O[4:0]) and a carry-out (COUT). PROGRAMMABLE LOGIC CELL (PLC) WD3 WD2 WD1 WD0 A4 A3 A2 A1 A0 COUT PROGRAMMABLE FUNCTION UNIT (PFU) O4 O3 O2 O1 O0 B4 B3 B2 B1 B0 CIN C0 CK CE LSR (ROUTING RESOURCES, CONFIGURATION RAM) 5-2750(F).r3 Figure 2. PFU Ports The LUTs can be programmed to operate in one of three modes: combinatorial, ripple, or memory. In combinatorial mode, the LUTs can realize any four-, five-, Lattice Semiconductor 7 Data Sheet November 2006 ORCA Series 2 FPGAs Programmable Logic Cells (continued)) COUT CARRY A4 A3 QLUT3 SE L D E IS C C T O D N E TI VI N C U E ED S A4 A2 A3 F3 C A1 WD3 REG3 CARRY A1 A3 A2 A1 A0 Q3 D3 A2 C PFU_NAND SR F2 EN O4 QLUT2 A4 A0 Q2 D2 O3 REG2 WD2 C CARRY B4 B4 B3 B2 B3 QLUT1 B3 B2 B1 O1 SR EN F0 Q0 D0 QLUT0 WD0 C T T T T T T T C C EN C C0 LSR GSR T REG0 B4 SR CIN O0 REG1 WD1 PFU_XOR C B0 Q1 D1 C CARRY O2 EN F1 PFU_MUX B1 B2 B1 B0 SR C WD[3:0] C CK CKEN TRI 5-4573(F) Key: C = controlled by configuration RAM. Figure 3. Simplified PFU Diagram Figure 2 and Figure 3 show high-level and detailed views of the ports in the PFU, respectively. The ports are referenced with a two- to four-character suffix to a PFU’s location. As mentioned, there are two 5-bit input data buses (A[4:0] and B[4:0]) to the LUT, one 4-bit input data bus (WD[3:0]) to the latches/FFs, and an output data bus (O[4:0]). Figure 3 shows the four latches/FFs (REG[3:0]) and the 64-bit look-up table (QLUT[3:0]) in the PFU. The PFU does combinatorial logic in the LUT and sequential logic in the latches/FFs. The LUT is static random access memory (SRAM) and can be used for read/ write or read-only memory. The eight 3-state buffers 8 found in each PLC are also shown, although they actually reside external to the PFU. Each latch/FF can accept data from the LUT. Alternatively, the latches/FFs can accept direct data from WD[3:0], eliminating the LUT delay if no combinatorial function is needed. The LUT outputs can bypass the latches/FFs, which reduces the delay out of the PFU. It is possible to use the LUT and latches/FFs more or less independently. For example, the latches/FFs can be used as a 4-bit shift register, and the LUT can be used to detect when a register has a particular pattern in it. Lattice Semiconductor Data Sheet November 2006 ORCA Series 2 FPGAs used as LUT inputs. The use of these ports changes based on the PFU operating mode. Table 5 lists the basic operating modes of the LUT. The operating mode affects the functionality of the PFU input and output ports and internal PFU routing. For example, in some operating modes, the WD[3:0] inputs are direct data inputs to the PFU latches/FFs. In the dual 16 x 2 memory mode, the same WD[3:0] inputs are used as a 4-bit data input bus into LUT memory. The functionality of the LUT is determined by its operating mode. The entries in Table 5 show the basic modes of operation for combinatorial logic, ripple, and memory functions in the LUT. Depending on the operating mode, the LUT can be divided into sub-LUTs. The LUT is comprised of two 32-bit half look-up tables, HLUTA and HLUTB. Each half look-up table (HLUT) is comprised of two quarter look-up tables (QLUTs). HLUTA consists of QLUT2 and QLUT3, while HLUTB consists of QLUT0 and QLUT1. The outputs of QLUT0, QLUT1, QLUT2, and QLUT3 are F0, F1, F2, and F3, respectively. SE L D E IS C C T O D N E TI VI N C U E ED S Programmable Logic Cells (continued) The PFU is used in a variety of modes, as illustrated in Figures 4 through 11, and it is these specific modes that are most relevant to PFU functionality. PFU Control Inputs The four control inputs to the PFU are clock (CK), local set/reset (LSR), clock enable (CE), and C0. The CK, CE, and LSR inputs control the operation of all four latches in the PFU. An active-low global set/reset (GSRN) signal is also available to the latches/FFs in every PFU. Their operation is discussed briefly here, and in more detail in the Latches/Flip-Flops section. The polarity of the control inputs can be inverted. The CK input is distributed to each PFU from a vertical or horizontal net. The CE input inhibits the latches/FFs from responding to data inputs. The CE input can be disabled, always enabling the clock. Each latch/FF can be independently programmed to be set or reset by the LSR and the global set/reset (GSRN) signals. Each PFU’s LSR input can be configured as synchronous or asynchronous. The GSRN signal is always asynchronous. The LSR signal applies to all four latches/FFs in a PFU. The LSR input can be disabled (the default). The asynchronous set/reset is dominant over clocked inputs. The C0 input is used as an input into the special PFU gates for wide functions in combinatorial logic mode. In the memory modes, this input is also used as the write-port enable input. The C0 input can be disabled (the default). Table 5. Look-Up Table Operating Modes Mode Function F4A Two functions of four inputs, some inputs shared (QLUT2/QLUT3) F4B Two functions of four inputs, some inputs shared (QLUT0/QLUT1) F5A One function of five inputs (HLUTA) F5B One function of five inputs (HLUTB) R 4-bit ripple (LUT) MA 16 x 2 asynchronous memory (HLUTA) MB 16 x 2 asynchronous memory (HLUTB) SSPM 16 x 4 synchronous single-port memory SDPM 16 x 2 synchronous dual-port memory For combinatorial logic, the LUT can be used to do any single function of six inputs, any two functions of five inputs, or four functions of four inputs (with some inputs shared), and three special functions based on the two five-input functions and C0. Look-Up Table Operating Modes The look-up table (LUT) can be configured to operate in one of three general modes: ■ Combinatorial logic mode ■ Ripple mode ■ Memory mode The combinatorial logic mode uses a 64-bit look-up table to implement Boolean functions. The two 5-bit logic inputs, A[4:0] and B[4:0], and the C0 input are Lattice Semiconductor 9 Data Sheet November 2006 ORCA Series 2 FPGAs Programmable Logic Cells (continued) A4 A4 A3 A3 A2 A2 A1 A1 HLUTA SE L D E IS C C T O D N E TI VI N C U E ED S The LUT ripple mode operation offers standard arithmetic functions, such as 4-bit adders, subtractors, adder/subtractors, and counters. In the ORCA Series 2, there are two new ripple modes available. The first new mode is a 4 x 1 multiplier, and the second is a 4-bit comparator. These new modes offer the advantages of faster speeds as well as denser logic capabilities. independent functions of up to five inputs is shown in Figure 5. In this case, the LUT is configured in the F5A and F5B modes. As a variation, the LUT can do one function of up to five input variables and two four-input functions using F5A and F4B modes or F4A and F5B modes. When the LUT is configured to operate in the memory mode, a 16 x 2 asynchronous memory fits into an HLUT. Both the MA and MB modes were available in previous ORCA architectures, and each mode can be configured in an HLUT separately. In the Series 2, there are two new memory modes available. The first is a 16 x 4 synchronous single-port memory (SSPM), and the second is a 16 x 2 synchronous dual-port memory (SDPM). These new modes offer easier implementation, faster speeds, denser RAMs, and a dual-port capability that wasn’t previously offered as an option in the ATT2Cxx/ATT2Txx families. If the LUT is configured to operate in the ripple mode, it cannot be used for basic combinatorial logic or memory functions. In modes other than the ripple, SSPM, and SDPM modes, combinations of operating modes are possible. For example, the LUT can be configured as a 16 x 2 RAM in one HLUT and a five-input combinatorial logic function in the second HLUT. This can be done by configuring HLUTA in the MA mode and HLUTB in the F5B mode (or vice versa). F4A/F4B Mode—Two Four-Input Functions Each HLUT can be used to implement two four-input combinatorial functions, but the total number of inputs into each HLUT cannot exceed five. The two QLUTs within each HLUT share three inputs. In HLUTA, the A1, A2, and A3 inputs are shared by QLUT2 and QLUT3. Similarly, in HLUTB, the B1, B2, and B3 inputs are shared by QLUT0 and QLUT1. The four outputs are F0, F1, F2, and F3. The results can be routed to the D0, D1, D2, and D3 latch/FF inputs or as an output of the PFU. The use of the LUT for four functions of up to four inputs each is given in Figure 4. F5A/F5B Mode—One Five-Input Variable Function Each HLUT can be used to implement any five-input combinatorial function. The input ports are A[4:0] and B[4:0], and the output ports are F0 and F3. One five or less input function is input into A[4:0], and the second five or less input function is input into B[4:0]. The results are routed to the latch/FF D0 and latch/FF D3 inputs, or as a PFU output. The use of the LUT for two 10 A3 A3 A2 A2 A1 A1 A0 A0 B4 B4 B3 B3 B2 B2 B1 B1 B3 B3 B2 B2 B1 B1 B0 B0 F3 QLUT3 F2 QLUT2 HLUTB F1 QLUT1 F0 QLUT0 5-2753(F).r2 Figure 4. F4 Mode—Four Functions of FourInput Variables HLUTA WEA A4 A3 A3 A2 A2 A1 A1 A0 A0 WD3 WD3 WD2 WD2 QLUT3 QLUT2 F3 F2 c0 WPE HLUTB B4 B4 B3 B3 B2 B2 B1 B1 B0 B0 QLUT1 F0 QLUT0 5-2845(F).r2 Figure 5. F5 Mode—Two Functions of Five-Input Variables Lattice Semiconductor Data Sheet November 2006 ORCA Series 2 FPGAs Programmable Logic Cells (continued) F5M and F5X Modes—Special Function Modes C0 The PFU contains logic to implement two special function modes which are variations on the F5 mode. As with the F5 mode, the LUT implements two independent five-input functions. Figure 6 and Figure 7 show the schematics for F5M and F5X modes, respectively. The F5X and F5M functions differ from the basic F5A/ F5B functions in that there are three logic gates which have inputs from the two 5-input LUT outputs. In some cases, this can be used for faster and/or wider logic functions. A4 A4 A3 A3 A2 A2 F3 QLUT3 SE L D E IS C C T O D N E TI VI N C U E ED S F3 As can be seen, two of the three inputs into the NAND, XOR, and MUX gates, F0 and F3, are from the LUT. The third input is from the C0 input into PFU. Since the C0 input bypasses the LUTs, it has a much smaller delay through the PFU than for all other inputs into the special PFU gates. This allows multiple PFUs to be cascaded together while reducing the delay of the critical path through the PFUs. The output of the first special function (either XOR or MUX) is F1. Since the XOR and MUX share the F1 output, the F5X and F5M modes are mutually exclusive. The output of the NAND PFU gate is F2 and is always available in either mode. To use either the F5M or F5X functions, the LUT must be in the F5A/F5B mode; i.e., only 5-input LUTs allowed. In both the F5X and F5M functions, the outputs of the five-input combinatorial functions, F0 and F3, are also usable simultaneously with the special PFU gate outputs. A1 A1 A0 A0 B4 B4 B3 B3 B2 B2 B1 B1 B0 B0 F2 QLUT2 QLUT1 F0 F1 QLUT0 F0 5-2754(F).r3 Figure 6. F5M Mode—Multiplexed Function of Two Independent Five-Input Variable Functions C0 A4 A4 A3 A3 A2 A2 A1 A1 A0 A0 B4 B4 B3 B3 B2 B2 B1 B1 B0 B0 F3 HLUTA F3 F2 The output of the MUX is: F1 = (HLUTA & C0) + (HLUTB & C0) F1 = (F3 & C0) + (F0 & C0) The output of the exclusive OR is: F1 = HLUTA ⊕ HLUTB ⊕ C0 F1 = F3 ⊕ F0 ⊕ C0 The output of the NAND is: F2 = HLUTA & HLUTB & C0 F2 = F3 & F0 & C0 Lattice Semiconductor HLUTB F1 F0 F0 5-2755(F).r2 Figure 7. F5X Mode—Exclusive OR Function of Two Independent Five-Input Variable Functions 11 Data Sheet November 2006 ORCA Series 2 FPGAs Programmable Logic Cells (continued) two operands are input into A[3:0] and B[3:0]. The four result bits, one per QLUT, are F[3:0] (see Figure 9). The ripple output from QLUT3 can be routed to dedicated carry-out circuitry into any of four adjacent PLCs, or it can be placed on the O4 PFU output, or both. This allows the PLCs to be cascaded in the ripple mode so that nibble-wide ripple functions can be expanded easily to any length. C0 A4 A3 A3 A2 A2 A1 A1 A0 A0 QLUT3 SE L D E IS C C T O D N E TI VI N C U E ED S A4 F3 QLUT2 COUT F1 F3 A3 B3 COUT QLUT3 A3 B2 B2 F2 A2 A2 QLUT2 B1 A1 B1 QLUT1 A1 F1 B0 A0 B0 QLUT0 A0 CIN F0 B3 B4 B4 B3 B3 B2 B2 B1 B1 B0 B0 QLUT1 F0 QLUT0 5-2751(F).r3 Figure 8. F5M Mode—One Six-Input Variable Function F5M Mode—One Six-Input Variable Function The LUT can be used to implement any function of sixinput variables. As shown in Figure 8, five input signals (A[4:0]) are routed into both the A[4:0] and B[4:0] ports, and the C0 port is used for the sixth input. The output port is F1. Ripple Mode The LUT can do nibble-wide ripple functions with highspeed carry logic. Each QLUT has a dedicated carryout net to route the carry to/from the adjacent QLUT. Using the internal carry circuits, fast arithmetic and counter functions can be implemented in one PFU. Similarly, each PFU has carry-in (CIN) and carry-out (COUT) ports for fast-carry routing between adjacent PFUs. The ripple mode is generally used in operations on two 4-bit buses. Each QLUT has two operands and a ripple (generally carry) input, and provides a result and ripple (generally carry) output. A single bit is rippled from the previous QLUT and is used as input into the current QLUT. For QLUT0, the ripple input is from the PFU CIN port. The CIN data can come from either the fast-carry routing or the PFU input B4, or it can be tied to logic 1 or logic 0. CIN 5-2756(F).r32 Figure 9. Ripple Mode The ripple mode can be used in one of four submodes. The first of these is adder/subtractor mode. In this mode, each QLUT generates two separate outputs. One of the two outputs selects whether the carry-in is to be propagated to the carry-out of the current QLUT or if the carry-out needs to be generated. The result of this selection is placed on the carry-out signal, which is connected to the next QLUT or the COUT signal, if it is the last QLUT (QLUT3). The other QLUT output creates the result bit for each QLUT that is connected to F[3:0]. If an adder/subtractor is needed, the control signal to select addition or subtraction is input on A4. The result bit is created in onehalf of the QLUT from a single bit from each input bus, along with the ripple input bit. These inputs are also used to create the programmable propagate. The resulting output and ripple output are calculated by using generate/propagate circuitry. In ripple mode, the 12 Lattice Semiconductor Data Sheet November 2006 ORCA Series 2 FPGAs Programmable Logic Cells (continued) SE L D E IS C C T O D N E TI VI N C U E ED S The second submode is the counter submode (see Figure 10). The present count is supplied to input A[3:0], and then output F[3:0] will either be incremented by one for an up counter or decremented by one for a down counter. If an up counter or down counter is needed, the control signal to select the direction (up or down) is input on A4. Generally, the latches/ FFs in the same PFU are used to hold the present count value. In the third submode, multiplier submode, a single PFU can affect a 4 x 1-bit multiply and sum with a partial product (see Figure 11). The multiplier bit is input at A4, and the multiplicand bits are input at B[3:0], where B3 is the most significant bit (MSB). A[3:0] contains the partial product (or other input to be summed) from a previous stage. If A4 is logical 1, the multiplicand is added to the partial product. If A4 is logical zero, zero is added to the partial product, which is the same as passing the partial product. CIN can hold the carry-in from the less significant PFUs if the multiplicand is wider than 4 bits, and COUT holds any carry-out from the addition, which may then be used as part of the product or routed to another PFU in multiplier mode for multiplicand width expansion. LUT COUT A3 A2 COUT QLUT3 QLUT2 F3 D Q Q3 A3 F2 D Q A2 B3 Q2 B2 A1 B1 A0 B0 0 0 0 0 1 0 1 0 1 0 1 0 A4 COUT A1 A0 QLUT1 QLUT0 CIN F1 F0 D Q + + + F3 F2 F1 F0 CIN Q1 5-4620(F) Figure 11. Multiplier Submode D Q Q0 CIN 5-4643(F).r1 Figure 10. Counter Submode with Flip-Flops Lattice Semiconductor + Ripple mode’s fourth submode features equality comparators, where one 4-bit bus is input on B[3:0], another 4-bit bus is input on B[3:0], and the carry-in is tied to 0 inside the PFU. The carry-out (≠) signal will be 0 if A = B or will be 1 if A ≠ B. If larger than 4 bits, the carry-out (≠) signal can be cascaded using fast-carry logic to the carry-in of any adjacent PFU. Comparators for greater than or equal or less than (>, =,