ORLI10G-2BMN680I

ORCA ORLI10G ® Quad 2.5Gbps, 10Gbps Quad 3.125Gbps, 12.5Gbps Line Interface FPSC January 2005 Data Sheet Introduction The Lattice ORCA Series 4-based ORLI10G FPSC combines a high-speed line interface with a flexible FPGA logic core. Built on the Series 4 reconfigurable embedded System-on-a-Chip (SoC) architecture, the ORLI10G consists of an OIF standard compliant (OIF-SFI4-01.0) SFI-4.1 or IEEE® 802.3ae compliant XSBI, 10 Gbits/s or 12.5 Gbits/s transmit and 10 Gbits/s or 12.5 Gbits/s receive line interface. Both transmit and receive interfaces consist of 16-bit LVDS data at up to 850 Mbits/s, integrated transmit and receive programmable PLLs for data rate conversions between the line-side and system-side data rates, and a programmable logic interface at the system end for use with SONET/SDH, Ethernet, or OTN/digital wrapper with strong FEC system device data standards. In addition to the embedded functionality, the device includes over 400k of usable FPGA gates. The line interface includes logic to divide the data rate down to 212 MHz or less (1/4 line rate) or 106 MHz or less (1/8 line rate) for transfer to the FPGA logic. The ORLI10G is designed to connect to a plethora of industry standard devices on the line side. The programmable logic interface on the system side allows direct connection to a 10 Gbits/s Ethernet MAC, a 10 Gbits/s SONET/SDH framer/data engine, or a 10 Gbits/s/12.5 Gbits/s digital wrapper/FEC framer/data engine. For 10 Gbits/s Ethernet, the ORLI10G supports the Physical Coding Sublayer (PCS), interfaces to the Physical Media Attachment (PMA), and connects to the system interface (host or switch) for the proposed IEEE 802.3ae 10 Gbits/s serial LAN PHY. The ORLI10G FPSC is a high-speed programmable device for 10 Gbits/s data solutions. It can be used as the interface between the line interface and the system interface in a variety of emerging networks, including 10 Gbits/s SONET/SDH (OC-192/STM-48), 10 Gbits/s Optical Transport Networks (OTN) using digital wrapper and strong FEC, or 10 Gbits/s Ethernet. Other functions include use in quad OC-48/ STM-16 SONET/SDH systems, interfaces between quad OC-48/STM-16 and OC-192/STM-64 components, and use as a generic data transfer mechanism between two devices at 10 Gbits/s rates. Data is received at the line interface and then sent to either a 4-bit or 8-bit serial-to-parallel converter. On the transmit interface, either a 4-bit or 8-bit parallel-to-serial converter is used. Thus, the data rate at the internal FPGA interface is either 1/4 or 1/8 the line rate. The programmable PLLs on the ORLI10G provide for great flexibility in handling clock rate conversion due to differing amounts of overhead bits in various system data standards. For example, the ORLI10G can divide down the STS-192/STM-64 SONET/SDH data line rate of 622 MHz by 4 to synchronize with a 155 MHz system clock, or the 12.5 Gbits/s Super-FEC data line rate of 781 MHz can be divided by 8 MHz to 98 MHz system clock or by 8 x 4/5 to provide a 78 MHz system data rate. Table 1. ORCA ORLI10G–Available FPGA Logic (equivalent to ORCA OR4E04) PFU Columns 36 FPGA Max. Total PFUs User I/Os* 1,296 316 EBR Blocks 12 EBR Bits (k) 111 FPGA System Gates (k) 333—643 Device ORLI10G PFU Rows 36 LUTs 10,368 * 316 are available in the 680 PBGAM package. Note: The embedded core, embedded system bus, FPGA interface and MPI are not included in the above gate counts. The System Gate ranges are derived from the following: minimum system gates assumes 100% of the PFUs are used for logic only (no PFU RAM) with 40% EBR usage and 2 PLLs. Maximum system gates assumes 80% of the PFUs are for logic, 20% are used for PFU RAM, with 80% EBR usage and 6 PLLs. © 2005 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1 orli10g_10 Lattice Semiconductor ORCA ORLI10G Data Sheet Embedded Function Features • Provides a line-interface to system-interface with various system standards such as OC-192/STM-64 SONET/SDH, quad OC-48/STM-16 10 Gbits/s Ethernet, and 10 Gbits/s OTN (digital wrapper/strong FEC) or 12.5 Gbits/s SuperFEC. • Embedded PLLs with programmable M/N multiplication/division values provide flexible data rate conversion between line side and system side. • Line-side supports 16-bit LVDS data with multiple line frequencies supported up to 850 MHz, depending on system standard. • Line-side interface, including timing and jitter specifications, compliant to OIF 99.102.5 standard. • Receive-side interface can be split into four separate asynchronous 2.5 Gbits/s interfaces (4-bit LVDS data interface for each) with a separate clock for each for transfer to the FPGA logic. • Data and clock rates divided by 4 or 8 for use in FPGA logic. • LVDS I/Os compliant with EIA®-644 support hot insertion. All embedded LVDS I/Os include both input and output on-board termination to allow high-speed operation. • Low-power LVDS buffers. Programmable Features • High-performance programmable logic: – 0.16 µm 7-level metal technology. – Internal performance of >250 MHz. – Over 400k usable FPGA system gates. – Meets multiple I/O interface standards. – 1.5 V operation (30% less power than 1.8 V operation) translates to greater performance. • Traditional I/O selections: – LVTTL (3.3 V) and LVCMOS (2.5 V, and 1.8 V) I/Os. – Per pin selectable I/O clamping diodes provide 3.3 V PCI compliance. – Individually programmable drive capability: 24 mA sink/12 mA source, 12 mA sink/6 mA source, or 6 mA sink/3 mA source. – Two slew rates supported (fast and slew limited). – Fast-capture input latch and input Flip-Flop latch for reduced input setup time and zero hold time. – Fast open-drain drive capability. – Capability to register 3-state enable signal. – Off-chip clock drive capability. – Two input function generator in output path. • New programmable high-speed I/O: – Single-ended: GTL, GTL+, PECL, SSTL3/2 (class I and II), HSTL (Class I, III, IV), ZBT, and DDR. – Double-ended: LVDS, bused-LVDS, LVPECL. Programmable (on/off) internal parallel termination (100 Ω) also supported for these I/Os. • New capability to (de)multiplex I/O signals: – New DDR on both input and output at rates up to 350 MHz (700 MHz effective rate). – New 2x and 4x downlink and uplink capability per I/O (i.e., 50 MHz internal to 200 MHz I/O). • Enhanced twin-quad Programmable Function Unit (PFU): – Eight 16-bit Look-Up Tables (LUTs) per PFU. – Nine user registers per PFU, one following each LUT, organized to allow two nibbles to act independently, plus one extra for arithmetic operations. – New register control in each PFU has two independent programmable clocks, clock enables, local set/reset, and data selects. 2 Lattice Semiconductor ORCA ORLI10G Data Sheet – New LUT structure allows flexible combinations of LUT4, LUT5, new LUT6, 4 : 1 MUX, new 8 : 1 MUX, and ripple mode arithmetic functions in the same PFU. – 32 x 4 RAM per PFU, configurable as single- or dual-port. Create large, fast RAM/ROM blocks (128 x 8 in only eight PFUs) using the SLIC decoders as bank drivers. – Soft-Wired LUTs (SWL) allow fast cascading of up to three levels of LUT logic in a single PFU through fast internal routing, which reduces routing congestion and improves speed. – Flexible fast access to PFU inputs from routing. – Fast-carry logic and routing to all four adjacent PFUs for nibble-wide, byte-wide, or longer arithmetic functions, with the option to register the PFU carry-out. • Abundant high-speed buffered and nonbuffered routing resources provide 2x average speed improvements over previous architectures. • Hierarchical routing optimized for both local and global routing with dedicated routing resources. This results in faster routing times with predictable and efficient performance. • SLIC provides eight 3-stable buffers, up to a 10-bit decoder, and PAL™-like AND-OR-INVERT (AOI) in each programmable logic cell. • New 200 MHz embedded quad-port RAM blocks, two read ports, two write ports, and two sets of byte lane enables. Each embedded RAM block can be configured as: – 1—512 x 18 (quad-port, two read/two write) with optional built-in arbitration. – 1—256 x 36 (dual-port, one read/one write). – 1—1k x 9 (dual-port, one read/one write). – 2—512 x 9 (dual-port, one read/one write for each). – 2 RAMs with arbitrary number of words whose sum is 512 or less by 18 (dual-port, one read/one write). – Supports joining of RAM blocks. – Two 16 x 8-bit Content Addressable Memory (CAM) support. – FIFO 512 x 18, 256 x 36, 1k x 9, or dual 512 x 9. – Constant multiply (8 x 16 or 16 x 8). – Dual variable multiply (8 x 8). • Embedded 32-bit internal system bus plus 4-bit parity interconnects FPGA logic, MicroProcessor Interface (MPI), embedded RAM blocks, and embedded standard cell blocks with 100 MHz bus performance. Included are builtin system registers that act as the control and status center for the device. • Built-in testability: – Full boundary scan (IEEE 1149.1 and draft 1149.2 JTAG) for the programmable I/Os only. – Programming and readback through boundary-scan port compliant to IEEE Draft 1532:D1.7. – TS_ALL testability function to 3-state all I/O pins. – New temperature-sensing diode. • Improved built-in clock management with Programmable Phase-Locked Loops (PPLLs) provides optimum clock modification and conditioning for phase, frequency, and duty cycle from 20 MHz up to 420 MHz. Multiplication of input frequency up to 64x and division of input frequency down to 1/64x is possible. • New cycle stealing capability allows a typical 15% to 40% internal speed improvement after final place and route. This feature also supports compliance with many setup/hold and clock-to-out I/O specifications, and may provide reduced ground bounce for output buses by allowing flexible delays of switching output buffers. 3 Lattice Semiconductor ORCA ORLI10G Data Sheet Programmable Logic System Features • PCI local bus compliant for FPGA I/Os. • Improved PowerPC ®/PowerQUICC 860, and PowerPC/PowerQUICC II MPC8260 high-speed synchronous microprocessor interface can be used for configuration, readback, device control, and device status, as well as for a general-purpose interface to the FPGA logic, RAMs, and embedded standard-cell blocks. Glueless interface to synchronous PowerPC processors with user-configurable address space is provided. • New embedded AMBA™ specification 2.0 AHB system bus (ARM ® processor) facilitates communication among the microprocessor interface, configuration logic, embedded block RAM, FPGA logic, and embedded standard cell blocks. • Variable-size bused readback of configuration data capability with the built-in microprocessor interface and system bus. • Internal, 3-state, and bidirectional buses with simple control provided by the SLIC. • New clock routing structures for global and local clocking significantly increases speed and reduces skew (