ORSO82G5-G2-PAC-EV

ORSO/ORT82G5 1 Rev. 1/7/03 Lattice Semiconductor Corp. JP4 Schematic page 3 A 7-pin serial connector used for configuration. Serial Connector Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 GND NC PROGRMN DONE D0 CCLK VDD JP6 Schematic page 3 JP6 is an 8-pin JTAG connector. It is physically similar to JP4; an arrow indicates pin 1. JTAG Connector Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 GND INIT_N RD_CFG_N TDO TCK TMS TDI VDD Header Connections Standard 0.100 headers are provided for interconnecting points on the board. This can be accomplished with 0.100 IDC connectors and ribbon cable for bus connections or 0.025 pin socket patch cords(such as Pomona Electronics #5948 www.pomonelectronics.com). D17 & D18 Schematic page 3 These LEDs indicate the status of configuration to the FPGA. When D17 is illuminated this indicates the successful completion of configuration. When D18 illuminates this indicates that the programming was aborted or reinitialized. ORSO/ORT82G5 2 Rev. 1/7/03 Lattice Semiconductor Corp. JP1 & JP2 Schematic page 2 This is a standard header. Pin one is at the bottom left. Pin numbers increment from left to right. The even pins on this header correspond to general I/O pins. The odd pins are connected to ground . JP3 Schematic page 2 This is a standard header (utilizing the even pins only) as described above. This header connects to 16LEDs. When a jumper cable is used, output from the ORSO/ORT82G5 can drive these LEDs to display a pattern from JP1 and JP2. JP35 Schematic pages 4 This is a 3 by 1 header that provids differential input/output from the ORSO/ORT82G5 primary clock spines. The first pin connects to the true side of the pair. Ground is connected to the middle column. The third pin is connected to the complement side of the pair. J39, 40, 41 Schematic page 6 These 96-pin headers fit with the 860 bus to communicate to a Windriver (www.windriver.com) MPC860 development board. JP32 Schematic page 5 This jumper selects the data 0 bit between the 860 bus communications and the 7-pin serial connector (J1). Jumping pins 2 and 3 selects the serial communication. Jumping pins 1 and 2 selects the 860 bus. J52 and J53 Schematic page 4 These SMA connectors provide differential input to the PLL clocks. PLL clocks J52 J53 PLL_CLK0C PLL_CLK0T JP36 Schematic page 4 This 2x2 header allows connection of ac coupling for J52 and J53. Adding a jumper between pins 1 and 2 or pins 3 and 4 removes the ac coupling capacitor. ORSO/ORT82G5 3 Rev. 1/7/03 Lattice Semiconductor Corp. PB1, PB2, PB3 Schematic page 3 These push button switches assert/de-assert the logic levels on the FPGA PRGMN, PRESET, and the SERDES reset. Depressing the button drives a logic level “0” to the device. JP7 Schematic page 3 The 1x2 header enables the de-bounce IC for push-buttons PB1, 2, & 3. Connecting a jumper enables the circuitry. JP9 Schematic page 3 This 1x3 header is connects PB3 to the SERDES reset or can connect the reset pin to GND. JP12, JP13, JP14, JP15, JP16 Schematic page 5 These are 2X10 reference voltage headers are used to connect the specified voltage reference pins used by the FPGA IO pins. JP19, 20, 21, 22,23 Schematic page 8 These jumpers select the input for the VddI/O voltage. Jumper connections are as follows. 1 3 5 2 4 6 1.5V 2.5V 3.3V JP8 Schematic page 3 This 2x4 header is used to drive the correct levels to the device Mode pins. When left without jumpers to the even (2,4,6,8) pins the device is driven to “1”. No jumpers is “1111” for slave serial programming mode. J51 Schematic page 9 This banana jack is connected to the ground plane of the board. ORSO/ORT82G5 4 Rev. 1/7/03 Lattice Semiconductor Corp. JP25, 30, 28, 26, 31 Schematic page 9 These 3-pin headers select the source of the SERDES power supplies. When a jumper is placed between Pin 1 and 2 the source of the supply comes from the on-board power supply. When the jumper is between P2 and 3 this selects the source from the adjacent banana jacks to be connected to an external supply. JP24, 27, 29 Schematic page 9 These 3-pin headers select the source of the device (3.3V, 2.5V, and 1.5V) power supplies. When no jumpers are used the source of the supply comes from the on-board power supply. When the jumper is between P1 and 2 this selects the source from the adjacent banana jacks to be connected to an external supply. J50 Schematic page 9 This banana jack connects to 5VDC supply. JP5 Schematic page 3 JP5 is a ten-pin header for additional dedicated signals from the ORSO/ORT82G5. One column of the header (pins 2,4,6, etc) is connected to ground. J82 Pin 1 Pin 3 Pin 5 Pin 7 Pin 9 LVDS_R RCLK DOUT LDC HDC Pin 2 Pin 4 Pin 6 Pin 8 Pin 10 GND GND GND GND GND JP17, 18 Schematic page 5 These headers are the chip select controls. The default is selected when no jumpers are present. JP10 Schematic page 4 This connector interconnects test points for the SERDES for characterization only. It is not populated for general use. This connector type is an Amp Z-Pack 2mm header. A cable similar to one from W. L. Gore (http://www.wlgore.com/) P/N 2MMA3193-01 adapts the 2mm Z-Pack to individual SMA connectors and is useful to observe signals or connect to other test devices. ORSO/ORT82G5 5 Rev. 1/7/03 Lattice Semiconductor Corp. JP10 Pin A1 Pin A2 Pin A3 Pin A4 GND WD_SYNC GND GND Pin B1 Pin B2 Pin B3 Pin B4 RBC0 GND GND GND Pin C1 Pin C2 Pin C3 Pin C4 GND GND GND GND Pin D1 Pin D2 Pin D3 Pin D4 RBC1 GND GND GND Pin E1 Pin E2 Pin E3 Pin E4 GND BYTE_SYNC GND XCK JP11 Schematic page 4 This connector interconnects test points for the SERDES for characterization only. It is not populated for general use. This connector type is an Amp Z-Pack 2mm header. A cable similar to one from W. L. Gore (http://www.wlgore.com/) P/N 2MMA3192-01 adapts the 2mm Z-Pack to individual SMA connectors and is useful to observe signals or connect to other test devices. JP11 Pin A1 Pin A2 Pin A3 Pin A4 Pin A5 GND LDIO2 GND LDIO6 GND Pin B1 Pin B2 Pin B3 Pin B4 Pin B5 LDIO0 GND LDIO4 GND LDIO8 Pin C1 Pin C2 Pin C3 Pin C4 Pin C5 GND GND GND GND GND Pin D1 Pin D2 Pin D3 Pin D4 Pin D5 LDIO1 GND LDIO5 GND LDIO9 Pin E1 Pin E2 Pin E3 Pin E4 Pin E5 GND LDIO3 GND LDIO7 GND J26 Schematic page 4 This test point is used to observe the CV (code violation) signal from the SERDES. SERDES Reference Clocks Schematic page 4 These SMA connectors connect to the reference clock pins of the SERDES. These pins receive a direct differential reference clock J13 J22 REFCLKA_N REFCLKB_N J14 J23 REFCLKA_P REFCLKB_P SERDES Channels Schematic page 4 These SMA connectors connect to the SERDES Tx and Rx channels of Quad B of the SERDES. These pins receive a direct differential data. J19 J20 J27 J28 J31 J32 J35 J36 ORSO/ORT82G5 INN_BA INP_BA INN_BB INP_BB INN_BC INP_BC INN_BD INP_BD J24 J25 J29 J30 J33 J34 J37 J38 6 Rev. 1/7/03 OUTN_BA OUTP_BA OUTN_BB OUTP_BB OUTN_BC OUTP_BC OUTN_BD OUTP_BD Lattice Semiconductor Corp. JP33 & JP34 Schematic page 3 JP33 and JP34 are unpopulated connections for the SERDES channel A. ORSO/ORT82G5 7 Rev. 1/7/03 Lattice Semiconductor Corp. 5 4 3 2 1 MPI_A[0:17] MPI_D[1:31] MPI_BUS1 CHAR I/O E DIN SERDESB1 MPI_CONNECTORS1 MPI_TSZ0 MPI_TSZ1 MPI_BDIP/ MPI_BURST/ MPI_TEA/ MPI_RTRY/ MPI_ACK/ MPI_CLK 860_D0 MPI_D[1:31] MPI_TSZ0 MPI_A[0:17] MPI_TSZ1 MPI_BDIP/ MPI_BURST/ MPI_TEA/ DIN MPI_RTRY/ 860_D0 MPI_ACK/ MPI_CLK MPI_INT 860_D0 MPI_TSZ0 MPI_TSZ1 MPI_BDIP/ MPI_BURST/ MPI_TEA/ MPI_RTRY/ MPI_ACK/ MPI_CLK 860_D0 E MPI_Connectors GP_I/O1 MPI_BUS/VREFS MPI_D[1:31] MPI_A[0:17] 860_D0 MPI_DP3 MPI_DP2 MPI_DP1 MPI_DP0 SerDesB GP I/O MPI_IRQ/ MPI_STRB/ MPI_RW HS_IN_CHannelB MPI_INTR D VSS1 HSPEED D GP_I/O VSS CONN I/O ORSO/ORT82G5 ORT_GND BYPASS1 VDDIO CTRL C PWR VDD1.5 VDD3.3 PWR INPUT C 5V Input ORT_PWR VDDIB VDDOB VDDRX VDDTX MODE CTRL HS_IN_CHANNELA1 SerDesA B SERIAL 860_D0 MPI_DP3 MPI_DP2 MPI_DP1 MPI_DP0 MPI_RW MPI_STRB/ MPI_IRQ/ MPI_DP3 MPI_DP2 MPI_DP1 MPI_DP0 MPI_RW MPI_STRB/ MPI_IRQ/ DIN B HS_IN_CHannelA\JTAG PROG HSPEED I/O A JTAG A Title ORSO/ORT82G5 Size B Date: 5 4 3 2 Document Number Block Diagra December 19, 2002 Rev Sheet 1 1 of 9 5 4 3 2 1 E PB21B PB21A PB20D PB20A PB20B PB19B PB19A PB18D PB18B PB18A PB17D PB17C PB17B PB17A PT14B PT14D PT15B PT15A PT15C PT15D PT16B PT16A PT16C PT17A PT17B PT18A PT18B PT19B PT19A PT19D PT20A PT20B AM21 AM22 AN21 AK17 AL18 AM18 AM19 AK16 AP21 AP20 AN19 AN18 AK15 AL16 D14 A16 E15 E14 B16 A17 C17 D16 B18 A19 A20 D18 D17 C18 C19 B22 E16 E17 E JP1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 D C 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 UA1B ORSO/ORT82G5_8 VDDIO_BC BANK VDDIO_TC BANK GEN I/O CELL PT20C PT20D PT21A PT21B PT21C PT21D PT22A PT22B PT22C PT22D PT23B PT23C PT23D PT24B PT24D PT25B PT25C PT25D PT26B PT26D PT27A PT27B PT27C PT28A PT28B PT28C PT28D PT29A PT29B A23 B23 A24 A25 C20 C21 E18 E19 D19 D20 B24 C23 C22 C24 A27 B27 B25 B26 A28 D22 E20 E21 C25 D23 D24 D25 D26 E22 E23 JP2 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 D C HEADER 20X2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 HEADER 20X2 PB22A PB22B PB22C PB22D PB23A PB23B PB24A PB24B PB24C PB24D PB25A PB25B PB25C PB26A PB26B PB26C PB27A PB27B PB27C PB27D PB28B PB28C PB29B PB29C PB29D PB30B AP30PB30C AP31PB30D AK24PB31B AM28PB31D AN30PB32B AK25PB32C AL26 PB32D AL27 PB33C AN31PB34B AK26PB34D AM30PB35B AK27PB36B AL30 PB36C AK29PB36D B30 PT36D C30 PT36B D30 PT35D E29 PT35B D29 PT34B B29 PT33D E27 PT32D E26 PT32C A30 PT32B A29 PT31D E24 PT31A B28 PT30D C28 PT30C D28 PT30A C27 PT29D D27 PT29C AL19 AK18 AP24 AN23 AP25 AP26 AK20 AL21 AN24 AM23 AN26 AN25 AK21 AM24 AL23 AP27 AL24 AM25 AP28 AP29 AN29 AM27 AM26 AK22 AK23 AL25 JP3 GP0 GP1 GP2 GP3 GP4 GP5 GP6 GP7 GP8 GP9 GP10 GP11 GP12 GP13 GP14 GP15 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 HEADER 16X2 B B D1 LED A D2 LED D3 LED D4 LED D5 LED D6 LED D7 LED D8 LED D9 D10 LED D11 LED D12 LED D13 LED D14 LED D15 LED 1 GP15 R16 680 2 R15 680 2 R14 680 2 2 R13 680 1 GP14 1 GP13 1 GP12 1 GP11 R12 680 2 R11 680 2 R10 680 2 2 R9 680 LED 1 GP10 1 GP9 1 GP8 1 GP7 R8 680 2 R7 680 2 R6 680 2 2 R5 680 1 GP6 1 GP5 1 GP4 1 GP3 R4 680 2 R3 680 2 2 R2 680 2 R1 680 1 GP2 1 GP1 1 GP0 GP[0:15] D16 LED A Title ORSO/ORT82G5 5 4 3 2 Size B Document Number GP_I/O Headers & LEDS Date: December 19, 2002 Rev Sheet 1 2 of 9 4 3 VDD_3.3 R17 MPI_RW MPI_STRB/ MPI_IRQ/ VDD_3.3 DIN DIN E M33 M34 HDOUTN_AB HDOUTP_AB R20 4.75K R19 4.75K AE1 T3 D5 NC2 NC1 W32 T32 2 4 6 8 10 UHD 8X2 VDD_3.3 SMA J13 SMA VCC /EN 1 19 OUT1 IN1 2 1 3 PB1 PROG 18 OUT2 IN2 3 1 3 PB2 PRESET 17 OUT3 IN3 4 1 R33 0 3 PB3 SRESET 16 OUT4 IN4 5 15 OUT5 IN5 6 14 OUT6 IN6 7 13 OUT7 IN7 8 12 OUT8 IN8 9 11 /CH R40 680 R39 680 B R37 0 R38 0 10 LED A Title Q1 2N2222 /INIT ORSO/ORT82G5 Size B Date: 4 R36 0 MPI_DP3 MPI_DP2 MPI_DP1 MPI_DP0 4.75K 5 R34 0 D18 R41 DONE GND C MAX6818 LED A RESETN HEADER 3 D17 HEADER 2 20 2 4 6 8 1 2 3 VDD_3.3 1 2 RESET JP9 3.32K 1% JP7 PRGM HEADER 4X2 R35 1 2 2 B 1 .1ufd HEADER 8 JP8 J14 C2 U1 1 3 5 7 D VDD_3.3 1 2 3 4 5 6 7 8 VDD_3.3 R32 4.75K HDOUTN_AD HDOUTP_AD R31 4.75K T33 T34 R30 4.75K HDINN_AD HDINP_AD HEADER 7 JP6 /INIT R29 4.75K R33 R34 M0 M1 M2 M3 HDOUTN_AC HDOUTP_AC A14 A13 C13 C12 P33 P34 DP0 DP1 DP2 DP3 2 4 6 8 10 12 14 16 /INIT PRD_CFG_N TDO TCK TMS TDI F1 G5 E4 B6 D10 C7 1 3 5 7 9 HEADER 5X2 AD5 AC5 AM4 AM6 1 3 5 7 9 11 13 15 AJ5 M3 G1 D2 C1 HDINN_AC HDINP_AC G30 PRESERVE03 F33 PRESERVE02 G31 PRESERVE01 JP34 UA2G ORSO/ORT82G5 SERDES_A/CTRL G32 ATMOUT_A N33 N34 4.75K JP5 LVDS_R RDY/BUSY/RCLK DOUT /LDC HDC R21 R28 4.75K HDINN_AB HDINP_AB VDD_3.3 R22 100 R27 4.75K L33 L34 PRGM RESET R26 4.75K HDOUTN_AA HDOUTP_AA E6 D4 D3 F5 C1 .1ufd 7 6 5 4 3 2 1 DONE PCCLK PDONE /PPRGRM /PRESET R25 4.75K K33 K34 JP4 R24 4.75K HDINN_AA HDINP_AA K30 REFCLKN_A K31 REFCLKP_A D J33 J34 VDD_3.3 R23 4.75K UHD 8X2 /WR/MPI_RW /RD/MPI_STRB_N PCFG_MPI_IRQ PSYS_RSSIG_ALL PSYS_DOBISTN PBIST_TEST_ENN PLOOP_TEST_ENN PASB_PDN PMP_TESTCLK PASB_RESETN PASB_TRISTN PMP_TESTCLK_ENN PASB_TESTCLK F31 F30 D32 E30 D31 C32 B32 A33 B31 A32 2 4 6 8 10 12 14 16 R18 4.75K JP33 1 3 5 7 9 11 13 15 C 1 4.75K J31 REXTN_A J30 REXT_A E 2 RESETN 5 3 2 Document Number SerDesA/Program Ctrl December 19, 2002 Rev Sheet 1 3 of 9 CON1 SMA 1 3 2 1 E REFCLKP 1 JP36 1 2 3 AD33 AD34 HDINN_BB HDINP_BB AC33 AC34 HDOUTN_BB HDOUTP_BB AB33 AB34 HDINN_BC HDINP_BC AA33 AA34 HDOUTN_BC HDOUTP_BC Y33 Y34 2 1 W33 W34 SMA J32 2 1 SMA C4 B4 A22 A21 2 F4 G4 AF30 AF31 REFCLKP_B REFCLKN_B AE31 AE30 PSCHAR_XCK PSCHAR_CV PSCHAR_BYTSYNC PSCHAR_WDSYNC PSCHAR_RBC1 PSCHAR_RBC0/TBC AJ33 AH30 AH31 AJ34 AK34 AJ31 R45 R46 R47 R48 R49 R50 0 0 0 0 0 0 PSCHAR_LDIO9 PSCHAR_LDIO8 PSCHAR_LDIO7 PSCHAR_LDIO6 PSCHAR_LDIO5 PSCHAR_LDIO4 PSCHAR_LDIO3 PSCHAR_LDIO2 PSCHAR_LDIO1 PSCHAR_LDIO0 AP32 AP33 AN32 AM31 AL31 AM33 AK30 AL32 AJ30 AK33 R51 R52 R53 R54 R55 R56 R57 R58 R59 R60 0 0 0 0 0 0 0 0 0 0 HDINN_BD HDINP_BD HDOUTN_BD HDOUTP_BD 1 CON1 REXT_B REXTN_B W5 PLCK1T Y5 PLCK1C SMA J26 SERDES_B/CLOCKS AM20PBCK0C AN20PBCK0T 2 1 AK19PBCK1C AL20 PBCK1T SMA J30 UA3A ORSO/ORT82G5_3 PLCK0C PLCK0T 2 1 U4 U5 SMA J33 R43 50 R44 3.32K 1% PLL_CK0C/HPPLL PLL_CK0T/HPPLL HDOUTN_BA HDOUTP_BA PLL_CK1C/PPLL PLL_CK1T/PPLL AE33 AE34 PTCK1C PTCK1T HDINN_BA HDINP_BA PTCK0T PTCK0C ATMOUT_B AF33 AF34 AM2 PLL_CK7T AN1 PLL_CK7C 2 1 AP4 PLL_CK6C AP3 PLL_CK6T 2 SMA J28 B19 B20 AH32 2 2 1 D R42 50 1 SMA C E 1 C179 R148 .01ufd 50 SMA J31 1 J53 J25 J29 REFCLKN SMA 1 SMA HEADER 3 1 J27 J22 2 4 HEADER 2X2 SMA J24 J23 SMA 2 J20 1 J52 SMA R14750 JP35 1 1 2 2 C178 .01ufd J21 SMA J19 3 2 4 2 5 JP10 XCK CV BYTSYNC WDSYNC RBC1 RBC0 D 7 6 5 4 3 2 1 0 HEADER 5X4 JP11 LDIO9 LDIO8 LDIO7 LDIO6 LDIO5 LDIO4 LDIO3 LDIO2 LDIO1 LDIO0 AM3 PTEMP E4 A4 D3 B3 E2 A2 D1 B1 1 D5 B5 E4 A4 D3 B3 E2 A2 D1 B1 9 8 7 6 5 4 3 2 1 0 C 2 HEADER 5X5 SMA J34 All signal traces are 50 ohm characteristic impedance Hand Route, minimize via's and, match trace lengths for the following signal groups: 1 2 1.All differential pairs HDINP,HDINN REFCLKN_B, REFCLKP_B Top Layer 2. All differential pairs HDOUTP,HDOUTN Top Layer 3. Match trace length for LDIO[0:9], RBC[0:1], WDSYNC, XCK, BYTSYNC Top / Bottom layer B 2 1 SMA J36 B 4. Place series resistors as close to device as possible. 5. Place Refclk resistors as close to device as possible. 6. Place REXT resistor as close to device pins as possible. SMA J35 1 2 AMP 5X4 Z-Pack Conn. AMP 5X5 Z-Pack Conn. 1 1 2 2 3 3 SMA J37 2 1 A SMA J38 4 1 A 4 Title b c d e 5 ORSO/ORT82G5 2 a a = Gnd b c d e = Signal Size B Date: 5 4 3 2 Document Number Serdes Channel B I/O December 19, 2002 Rev Sheet 1 4 of 9 5 4 3 2 1 860_D[1:31] MPI_D[1:31] E 860_D1 860_D2 860_D3 860_D4 860_D5 860_D6 860_D7 860_D8 860_D9 860_D10 860_D11 860_D12 860_D13 860_D14 860_D15 860_D16 860_D17 860_D18 860_D19 860_D20 860_D21 860_D22 860_D23 860_D24 860_D25 860_D26 860_D27 860_D28 860_D29 860_D30 860_D31 JP32 860_D0 1 2 3 DIN JP13 1 3 5 7 9 HEADER 3 D0 JP12 2 4 6 8 10 1 3 5 7 9 11 HEADER 5X2 E 2 4 6 8 10 12 HEADER 6X2 E11 E9 D8 B8 J1 J5 H5 D1 AF3 AE5 AF5 AG4 AH3 AL2 AP7 AL8 AL9 AN8 AM8 AL10 AM10 AM11 AP10 AL12 AK12 AP13 AP14 AP15 AL14 AM15 AN16 AP19 1 3 5 7 9 JP14 2 4 6 8 10 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 HEADER 5X2 HEADER 5X2 C JP16 1 3 5 7 2 4 6 8 HEADER 4X2 C26 D21 A26 B21 A18 A15 E28 C29 E25 VREF_TC_01 VREF_TC_02 VREF_TC_03 VREF_TC_04 VREF_TC_05 VREF_TC_06 VREF_TC_07 VREF_TC_08 VREF_TC_09 AE2 AD2 AB2 W3 T2 R3 L2 H1 VREF_CL_08 VREF_CL_07 VREF_CL_06 VREF_CL_05 VREF_CL_04 VREF_CL_03 VREF_CL_02 VREF_CL_01 VREF/MICROBUS MPI_A0 MPI_A1 MPI_A2 MPI_A3 MPI_A4 MPI_A5 MPI_A6 MPI_A7 MPI_A8 MPI_A9 MPI_A10 MPI_A11 MPI_A12 MPI_A13 MPI_A14 MPI_A15 MPI_A16 MPI_A17 B B14 B12 A11 D9 A6 B5 B1 F3 F2 K3 VREF_BL_01 VREF_BL_02 VREF_BL_03 VREF_BL_04 VREF_BL_05 VREF_BL_06 VREF_BL_07 VREF_BL_08 VREF_BL_09 VREF_BL_10 VREF_BL_11 AG3 AH2 AM1 AH4 AL6 AP6 AK10 AN10 AP12 AM14 AP18 MPI_RTRY_N MPI_TEA_N MPI_ACK_N MPI_CLK 2 4 6 8 10 UA4D ORSO/ORT82G5_6 VREF_TL_01 VREF_TL_02 VREF_TL_03 VREF_TL_04 VREF_TL_05 VREF_TL_06 VREF_TL_07 VREF_TL_08 VREF_TL_09 VREF_TL_10 CS1 /CS0 D C G2 H3 VDD_3.3 R61 4.75K C16 A12 C15 E12 1 3 5 7 9 VREF_BC_01 VREF_BC_02 VREF_BC_03 VREF_BC_04 VREF_BC_05 VREF_BC_06 VREF_BC_07 VREF_BC_08 VREF_BC_09 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18/MPI_TSZ0 A19/MPI_TSZ1 A20/MPI_BDIP_N A21/MPI_BURST_N JP15 AL17 AP22 AN22 AL22 AN27 AN28 AM29 AL28 AL29 AF2 AG1 AA5 AB5 AF1 AB3 AB4 AC1 W4 V3 V2 P2 P3 P4 M4 N5 J2 E1 A8 B9 A9 E13 D R62 JP17 100 1 2 B HEADER 2 VDD_3.3 JP18 R63 1 2 MPI_A[0:17] MPI_A[0:17] 100 HEADER 2 R64 4.75K A MPI_TSZ0 MPI_TSZ1 MPI_BDIP/ MPI_BURST/ MPI_RTRY/ MPI_TEA/ MPI_ACK/ MPI_CLK A Title ORSO/ORT82G5 Size B Date: 5 4 3 2 Document Number MPI_BUS/VREFS December 19, 2002 Rev Sheet 1 5 of 9 B MPI_D[1:31] J40 CON96 MPI_TSZ1 MPI_TSZ0 MPI_RW MPI_BURST/ MPI_BDIP/ MPI_STRB/ MPI_ACK/ MPI_TEA/ MPI_CLK MPI_DP0 MPI_DP1 MPI_DP2 MPI_DP3 MPI_RTRY/ MPI_IRQ/ J41 CON96 5 4 MPI_A17 MPI_A16 MPI_A15 MPI_A14 MPI_A13 MPI_A12 MPI_A11 MPI_A10 MPI_A9 MPI_A8 MPI_A7 MPI_A6 MPI_A5 MPI_A4 MPI_A3 MPI_A2 MPI_A1 MPI_A0 860_D31 860_D30 860_D29 860_D28 860_D27 860_D26 860_D25 860_D24 860_D23 860_D22 860_D21 860_D20 860_D19 860_D18 860_D17 860_D16 860_D15 860_D14 860_D13 860_D12 860_D11 860_D10 860_D9 860_D8 860_D7 860_D6 860_D5 860_D4 860_D3 860_D2 860_D1 860_D0 R65 R66 R67 R69 R71 R73 R75 R77 R79 R81 R83 R85 R87 R89 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 3 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 3 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C 4 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 MPI_A17 MPI_A16 MPI_A15 MPI_A14 MPI_A13 MPI_A12 MPI_A11 MPI_A10 MPI_A9 MPI_A8 MPI_A7 MPI_A6 MPI_A5 MPI_A4 MPI_A3 MPI_A2 MPI_A1 MPI_A0 MPI_A[0:17] B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 D 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K MPI_A[0:17] B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 R104 R105 R106 R107 R108 R109 R110 R111 R112 R113 R114 R115 R116 R117 R118 R119 R120 R121 E A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 J39 CON96 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 5 2 A 2 1 Size B Date: December 19, 2002 Sheet 1 VDD_3.3 VDD_3.3 VDD_3.3 R68 1K R70 1K R72 1K R74 1K R76 1K R78 1K R80 1K R82 1K R84 1K R86 1K R88 1K R90 1K R91 1K R92 1K R93 1K R94 1K R95 1K R96 1K R97 1K R98 1K R99 1K R1001K R1011K R1021K R1031K R1221K R1231K R1241K R1251K R1261K R1271K R1281K 6 of E D 860_D0 860_D[1:31] C MPI_TSZ1 MPI_TSZ0 MPI_RW MPI_BURST/ MPI_BDIP/ MPI_STRB/ MPI_ACK/ MPI_TEA/ MPI_CLK MPI_DP0 MPI_DP1 MPI_DP2 MPI_DP3 MPI_RTRY/ MPI_IRQ/ B Title ORSO/ORT82G5 Document Number MPI Connector Interface Rev A 9 5 4 3 2 1 E D V19 W16 W17 W18 W19 Y13 Y14 Y15 Y20 Y21 Y22 AH33 AD31 AC31 AA31 W31 T31 P31 M31 L31 G33 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSSGB_B VSSRX_BA VSSRX_BB VSSRX_BC VSSRX_BD VSSRX_AD VSSRX_AC VSSRX_AB VSSRX_AA VSSGB_A UA5E ORSO/ORT82G5_4 D VSS48 VSS47 VSS46 VSS45 VSS44 VSS43 VSS42 VSS41 VSS40 VSS39 VSS38 VSS37 VSS36 VSS35 VSS34 VSS33 VSS32 VSS31 VSS30 VSS29 VSS28 VSS27 VSS26 VSS25 V18 V17 V16 U19 U18 U17 U16 T19 T18 T17 T16 R22 R21 R20 R15 R14 R13 P22 P21 P20 P15 P14 P13 N22 C A1 VSS1 A34 VSS2 AA13VSS3 AA14VSS4 AA15VSS5 AA20VSS6 AA21VSS7 AA22VSS8 AB13VSS9 AB14VSS10 AB15VSS11 AB20VSS12 AB21VSS13 AB22VSS14 AN33VSS15 AP34VSS16 B2 VSS17 B33 VSS18 E34 VSS19 N13 VSS20 N14 VSS21 N15 VSS22 N20 VSS23 N21 VSS24 C VSSIB_AB VSSOB_AB VSSTX_AB VSSIB_AC VSSOB_AC VSSTX_AC VSSIB_AD VSSOB_AD VSSTX_AD VSSTX_BD VSSOB_BD VSSIB_BD VSSTX_BC VSSOB_BC VSSIB_BC VSSTX_BB VSSOB_BB VSSIB_BB VSSTX_BA VSSOB_BA VSSIB_BA VSSAUX_B V34 V33 V32 U34 U33 U32 N32 M32 J32 H34 H33 H32 H31 H30 AG34 AG33 AG32 AG31 AG30 AF32 AC32 AB32 E B B A A Title ORSO/ORT82G5 Size B Date: 5 4 3 2 Document Number VSS/GND Connections December 19, 2002 Rev Sheet 1 7 of 9 5 4 3 2 1 VDD_1.5 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 .1ufd .01ufd .1ufd .01ufd .1ufd .01ufd .1ufd .01ufd .1ufd .01ufd .1ufd .01ufd .1ufd .01ufd .1ufd .01ufd .1ufd .01ufd .1ufd .01ufd E C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43 C44 C45 C46 C47 C48 .01ufd .1ufd .01ufd .1ufd .01ufd .1ufd .01ufd .1ufd .01ufd .1ufd .01ufd .1ufd .01ufd .1ufd .01ufd .1ufd .01ufd .1ufd .01ufd .1ufd C24 C25 C26 C27 C28 .1ufd .01ufd .1ufd .01ufd .1ufd .01ufd C49 C50 C51 C52 C53 C54 .1ufd .01ufd .1ufd .01ufd .1ufd .01ufd E C70 C71 C72 .1ufd .01ufd .1ufd .01ufd .1ufd .01ufd C79 C80 C81 C82 C83 C84 .1ufd .01ufd .1ufd .01ufd .1ufd .01ufd C91 C92 C93 C94 C95 C96 .1ufd .01ufd .1ufd .01ufd .1ufd .01ufd VDD_3.3 VDD_X C97 C98 C99 C100 C101 C102 C3 AL4 AK5 AK28 AK31 E31 C31 A31 E5 AM32 VDD33_1 VDD33_2 VDD33_3 VDD33_4 VDD33_5 VDD33_6 VDD33_7 VDD33_8 VDD33_9 VDD33_10 R32 P32 AD32 AE32 K32 L32 AA32 Y32 VDDRX_AA_2 VDDRX_AA_1 VDDRX_BA_1 VDDRX_BA_2 VDDTX_BA VDDTX_AA VDDAUX_B VDDAUX_A VDD_1.5 .1ufd .01ufd .1ufd .01ufd .1ufd .01ufd C105 C106 .1ufd .01ufd JP22 VDD_1.5 VDD_2.5 VDD_3.3 1 3 5 UA5F ORSO/ORT82G5_4 VDD3.3 VDDRX/TX VDDIO BANK BC HIGH SPEED PWR VDDIO BANK BL V21 V22 W13 W14 W15 W20 W21 W22 Y16 Y17 Y18 Y19 VDDIO0_TL1 VDDIO0_TL2 VDDIO0_TL3 VDDIO0_TL4 VDDIO0_TL5 VDDIO0_TL6 A2 B3 B7 C5 C9 D7 VDDIO1_TC1 VDDIO1_TC2 VDDIO1_TC3 VDDIO1_TC4 VDDIO1_TC5 VDDIO1_TC6 B13 B15 B17 D11 D13 D15 VDDIO5_BC1 VDDIO5_BC2 VDDIO5_BC3 VDDIO5_BC4 VDDIO5_BC5 VDDIO5_BC6 AL11 AL13 AL15 AN13 AN15 AN17 VDDGB_A VDDGB_B G34 AH34 VDDIO BANK TL VDDIO BANK TC W2 U3 R2 N3 AC2 AA3 B VDD15_53 VDD15_54 VDD15_55 VDD15_56 VDD15_57 VDD15_58 VDD15_59 VDD15_60 VDD15_61 VDD15_62 VDD15_63 VDD15_64 1.5V CORE LOGIC M30 VDDOB_AA L30 VDDIB_AA C69 N31 VDDOB_AB N30 VDDIB_AB C68 VDD15_11 VDD15_10 VDD15_9 VDD15_8 VDD15_7 VDD15_6 VDD15_5 VDD15_4 VDD15_3 VDD15_2 VDD15_1 R31 VDDOB_AC_1 R30 VDDOB_AC_0 P30 VDDIB_AC C67 AL33 AK32 AJ32 AB19 AB18 AB17 AB16 AA19 AA18 AA17 AA16 U31 VDDOB_AD_1 U30 VDDOB_AD_0 T30 VDDIB_AD .01ufd AC30VDDOB_BA AD30VDDIB_BA C60 .1ufd AB31VDDOB_BB AB30VDDIB_BB C59 .01ufd Y31 VDDOB_BC_1 Y30 VDDOB_BC_0 AA30VDDIB_BC C58 .1ufd V31 VDDOB_BD_1 V30 VDDOB_BD_0 W30 VDDIB_BD C57 .01ufd VDDIO6_BL8 VDDIO6_BL7 VDDIO6_BL6 VDDIO6_BL5 VDDIO6_BL4 VDDIO6_BL3 VDDIO6_BL2 VDDIO6_BL1 C C56 .1ufd AP2 AP1 AN7 AN3 AN2 AM9 AM5 AL7 VDD_3.3 C55 VDDIO7_CL6 VDDIO7_CL5 VDDIO7_CL4 VDDIO7_CL3 VDDIO7_CL2 VDDIO7_CL1 D VDD15_12 VDD15_13 VDD15_14 VDD15_15 VDD15_16 VDD15_17 VDD15_18 VDD15_19 VDD15_20 VDD15_21 VDD15_22 VDD15_23 VDD15_24 VDD15_25 VDD15_26 VDD15_27 VDD15_28 VDD15_29 VDD15_30 VDD15_31 VDD15_33 VDD15_34 VDD15_35 VDD15_36 VDD15_37 VDD15_38 VDD15_39 VDD15_40 VDD15_41 VDD15_42 VDD15_43 VDD15_44 VDD15_45 VDD15_46 VDD15_47 VDD15_48 VDD15_49 VDD15_50 VDD15_51 VDD15_52 AL34 AM34 AN34 B34 C33 C34 D33 D34 E32 E33 F32 F34 N16 N17 N18 N19 P16 P17 P18 P19 R16 R17 R18 R19 T13 T14 T15 T20 T21 T22 U13 U14 U15 U20 U21 U22 V13 V14 V15 V20 C29 C23 C61 C62 C63 C64 C65 C66 .1ufd .01ufd .1ufd .01ufd .1ufd .01ufd C73 C74 C75 C76 C77 C78 .1ufd .01ufd .1ufd .01ufd .1ufd .01ufd C85 C86 C87 C88 C89 C90 .1ufd .01ufd .1ufd .01ufd .1ufd .01ufd C JP19 1 3 5 VDD_1.5 VDD_2.5 VDD_3.3 VDD_1.5 VDDIB_A D 2 4 6 HEADER 3X2 JP20 C103 C104 .01ufd .1ufd VDD_1.5 VDD_2.5 VDD_3.3 1 3 5 2 4 6 HEADER 3X2 JP21 C107 C108 .1ufd .01ufd VDD_1.5 VDD_2.5 VDD_3.3 1 3 5 B 2 4 6 HEADER 3X2 VDDIB_B VDD_1.5 2 4 6 C109 C110 C111 C112 C113 C114 C115 C116 .1ufd .01ufd .1ufd .01ufd .1ufd .01ufd .1ufd .01ufd HEADER 3X2 C117 C118 C119 C120 C121 C122 .1ufd .01ufd .1ufd .01ufd .1ufd .01ufd VDDOB_B A VDDOB_A JP23 VDD_1.5 VDD_2.5 VDD_3.3 1 3 5 2 4 6 C123 C124 C125 C126 C127 C128 C129 C130 C131 C132 C133 C134 C135 C136 C137 C138 C139 C140 C141 C142 .1ufd .01ufd .1ufd .01ufd .1ufd .01ufd .1ufd .01ufd .1ufd .01ufd .1ufd .01ufd .1ufd .01ufd .1ufd .01ufd .1ufd .01ufd .1ufd .01ufd ORSO/ORT82G5 Size B HEADER 3X2 Date: 5 4 3 2 A Title Document Number ORSO/ORT8G25 PWR Connections December 19, 2002 Rev Sheet 1 8 of 9 3 2 1 VDD_1.5 JP24 R129 2 VDDIB_A HEADER 3 2 4 NC 2 GND Relay5v FUSE R131 1 Banana J44 VDD_5v 1 2 3 F3 2 1 JP27 FUSE 1 2 3 3 SENSE 1 U5 5 +5v 3 NO .1ufd 2 ADJ AMS1503 U4 R134 124 C159 C160 22ufd .1ufd 4 NC COM GND 2 J45 FUSE FUSE F6 C166 4 VCTRL OUT 3 HEADER 3 +5v 2 ADJ SENSE AMS1503 R139 75 1 U6 VCTRL C167 C168 3 NO 22ufd .1ufd 4 NC 1 2 3 1 GND 2 R138 D20 1 Relay5v LED R141 1 2 3 2 2 1 C174 10uF 2 1 C173 .1uF 2 1 2 C177 .1ufd R142 VDD_5v 1 1 C176 10ufd 2 A 1 0 ohm (1205) Banana J51 VDD_1.5 R143 2 R144 LED R146 Banana 1 R145 Q2 680 2N3906 VCTRL Banana C171 1uF 2 FUSE 680 Q3 ORSO/ORT82G5 Size B Date: 3 A Title 2N2222 4 C170 10uF F8 680 5 C169 .1uF B 4.75K D21 C175 1uF VDD_X HEADER 3 J49 FUSE 2 0 ohm (0603) JP31 Banana 1 C164 1uF FUSE R140 124 F9 C163 10uF HEADER 3 680 J50 C162 .1uF C F7 COM J48 C172 .1ufd VDDOB_B JP30 VDD_3.3 U7 5 .1ufd 2 0 ohm (0603) Banana 1 2 3 6 1 1 FUSE JP29 C165 HEADER 3 R137 J47 2 TAB C158 1uF R136 680 VPWR C157 10uF Banana VDD_5v B 1 R135 124 5 VDDOB_A C156 .1uF LED Banana 10ufd 1 2 3 F5 2 D19 J46 C 2 0 ohm (0603) JP28 Relay5v VCTRL C161 .1ufd 1 F4 1 1 OUT 1 VCTRL VDD_2.5 2 4 D R133 HEADER 3 1 6 2 10ufd TAB C153 1uF HEADER 3 2 C155 VPWR C152 10uF Banana 2 C154 5 VDDIB_B C151 .1uF 2 D 2 0 ohm (0603) JP26 2 R132 30 2 C150 .1ufd 1 J43 2 .1ufd E HEADER 3 1 C149 22ufd FUSE Banana F2 2 C148 R130 124 C145 1uF 1 2 3 1 1 1 SENSE NO 2 2 ADJ 3 1 COM 1 2 OUT +5v 2 VCTRL 5 C144 10uF 1 .1ufd 3 F1 2 10ufd 4 J42 U3 1 C147 JP25 6 1 C146 U2 TAB 1 E VPWR 1 AMS1505 5 C143 .1uF 1 0 ohm (0603) 2 1 1 1 2 3 2 4 1 5 VDD_5v 2 Document Number Power Supply Inputs December 19, 2002 Rev Sheet 1 9 of 9