ORSPI4-2F1156I

厂商：
LATTICE(莱迪思半导体)
封装：
描述：
ORSPI4-2F1156I - Dual SPI4 Interface and High-Speed SERDES FPSC - Lattice Semiconductor

数据手册：

下载ORSPI4-2F1156I.pdf

立即购买

数据手册
价格&库存

ORSPI4-2F1156I 数据手册

ORCA® ORSPI4 Dual SPI4 Interface and High-Speed SERDES FPSC October 2007 Data Sheet Lattice Semiconductor has developed a next-generation FPSC targeted at high-speed data transmission. Built on the Series 4 reconﬁgurable embedded System-on-a-Chip (SoC) architecture, the ORSPI4 FPSC contains two SPI4.2 interface blocks, a high-speed Memory Controller, four channels of 0.6-3.7 Gbits/s SERDES with 8b/10b encoding and decoding and over 600K programmable system gates all on a single chip. Embedded SPI4 Core Features ■ ■ ■ OIF-SPI4-02.0 compliant interfaces Dynamic timing receive interface: • Full bandwidth up to 450 MHz DDR (900 Mbits/s) for all speed grades. • Bit de-skewing up to 16 phases of the clock • Capable of aligning bit-to-bit skews as large as ±1 bit periods Static timing receive interface: • Speeds up to 325 MHz DDR (650 Mbits/s), for all speed grades, including Quarter-Rate mode • Clock aligned or clock centered modes supported DIP-4 and DIP-2 parity generation and checking Transmit Interface: • Speeds up to 450 MHz DDR (900 Mbits/s) • Dedicated LVDS transmit interface for improved data eye integrity • Automatic idle insertion 256 logical ports: • Embedded Calendar-based sequence port polling mechanism and bandwidth allocation. Shadow Calendar support for smooth transition to new Calendar • Up to 32 independent TX and 32 independent RX buffers per SPI4 interface internally. Various aggregation modes to support 1 to 32 separate embedded buffers per TX and RX • Up to 4 independent TX and 4 independent RX clock domain transfers to the FPGA logic FIFO status support modes: • 1/4 rate LVTTL or 1/4 rate LVDS • Automatic status handling or optionally under user control. Credit calculations based on burst size and status are also handled automatically Conﬁguration options as suggested in the OIFSPI4-02.0 standard • Conﬁgures parameters such as maximum burst size, calendar length, main and shadow calendars (1K deep each), length of training sequence etc. Simple FIFO interface to the FPGA logic • Provides ease of design and efﬁcient clock domain transfers Loopback modes provided for system- and chip-level debug Embedded 32-bit internal system bus plus 4-bit parity • Interconnects FPGA logic, microprocessor interface (MPI), embedded RAM blocks, and embedded core blocks • Includes built-in system registers that act as the control and status center for the device Low power operation. • Full-rate SPI4.2 interfaces running at 450 MHz DDR (900 Mbits/sec) with dynamic alignment consumes 1.5 W of power or less. More efﬁcient than FPGAs with soft-IP SPI4 solutions which consume in excess of 10 W. Programmable Minburst capability with selectable burst values ranging from 16 to 240. Interoperability demonstrated with ORSPI4 partners. Quad 600 Mbits/s to 3.7 Gbits/s SERDES: • IEEE 802.3ae XAUI (Link State Machine & Alignment FIFOs embedded) • ANSI X3.230:1994 1G/2G FC-compliant (Link State Machine & Alignment FIFOs embedded) • Proven performance (same SERDES used in ORT82G5/ORT42G5 FPSCs) High Performance Memory Controller for interface to external buffer memory • Required for Layer 2 data buffering • QDR II memory interface: – 36-bit Input and 36-bit Output bus, 18-bit address – 175 MHz clock rates – 20+ Gbits/s bandwidth – Supports 2- or 4-word burst mode – Simple FIFO interface to FPGA – Integrated PLL for optimized performance – Proven performance with multiple memory suppliers ■ ■ ■ ■ ■ ■ ■ ■ ■ Embedded SERDES Core Features ■ ■ Embedded Memory Controller Features ■ ■ Note: The term SPI4 refers to OIF SPI-4.2 throughout this document © 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without notice. www.latticesemi.com 1 ORSPI4_06 Lattice Semiconductor ORCA ORSPI4 Data Sheet High-Speed ORCA Series 4 FPGA ■ ■ ■ ■ ■ Internal performance of > 250 MHz Over 16K programmable logic elements 1.5V operation (30% less power than 1.8 V operation) Comprehensive I/O selections including LVTTL, LVCMOS, GTL, GTL+, PECL, SSTL3/2, HSTL, ZBT, DDR, LVDS, bused-LVDS, and LVPECL 1036-pin ftSBGA package provides enough FPGA user I/Os (498) for 4 full-duplex XGMII interfaces, 4 full-duplex PL-3 interfaces, etc; a 40% smaller 1156-pin fpBGA package is available with 356 FPGA user I/Os Introduction The SPI4 blocks provide dual 10 Gbits/s physical-to-link layer interfaces in conformance to the OIF-SPI4-02.0 speciﬁcation. Each block provides a full-duplex interface with an aggregate bandwidth of 13.6 Gbits/s. This is achieved by using 16 LVDS pairs each for RX and TX operating at a maximum data rate of 900 Mbits/s with a 450 MHz DDR clock. Both static and dynamic alignment are supported at the receive interface. Dynamic alignment is used to compensate for bit-to-bit skew at higher data rates, where it becomes difﬁcult to meet tight setup/hold requirements. DIP-4 and DIP-2 parity generation and checking are supported. Data buffering of 8K bytes for both transmit and receive is provided by embedded Dual-Port RAM in each SPI4 core. Internal 1K deep main and shadow calendar supports scheduling of up to 256 ports. The Transmit and Receive Status FIFOs can also store ﬂow control information for up to 256 ports, the maximum speciﬁed in the SPI4 speciﬁcation. An independent QDRII Memory Controller block provides data buffering between the FPGA logic and external memory and supports a throughput of greater than 20 Gbits/s. Data is transferred to and from memory through two sets of 36-bit unidirectional data lines operating at up to 175 MHz DDR. A set of 72 data signals is available to transfer data across the core-FPGA interface and allows the system to utilize the bandwidth available with secondgeneration Quad Data Rate (QDRII) SRAMs. Of the 72 data signals, 8 signals can be either used for parity or data. A soft IP version of this core is also available to allow a second data buffer on this device. The High-Speed SERDES block supports four serial links, each operating at up to 3.7 Gbits/s (2.96 Gbits/s data rate with 8b/10b encoding and decoding), to provide four full-duplex synchronous interfaces with built-in RX Clock and Data Recovery (CDR) and transmitter preemphasis. The SERDES block is identical to that in the ORT82G5 FPSC, supports embedded 8b/10b encoding/decoding and implements link state machines for both 10G Ethernet, and 1G/2G/10G Fibre Channel. The state machines are IEEE P802.3ae/D4.01 XAUI based and also support FC (ANSI X3.230:1994) link synchronization. Table 1. ORCA ORSPI4 — Available FPGA Logic Device ORSPI4 PFU Rows 46 PFU Columns 44 Total PFUs 2,024 FPGA Max User I/O 498/356 LUTs 16,192 EBR Blocks 16 EBR Bits (K) 148 Usable* Gates (K) 471-899 Note: The embedded core, embedded system bus, FPGA interface and MPI are not included in the above gate counts. The System Gate ranges are derived from the following: Minimum System Gates assumes 100% of the PFU's are used for logic only (No PFU RAM) with 40% EBR usage and 2 PLL's. Maximum System Gates assumes 80% of the PFU's are for logic, 20% are used for PFU RAM, with 80% EBR usage and 4 PLL's. The ORSPI4 device is offered in two packages: 1036 ftSBGA and 1156 fpBGA. The 1036 package offers 498 FPGA User I/Os while the 1156 package offers 356 FPGA User I/Os. Additionally, the SERDES option is not available on the 1156 package. 2 Lattice Semiconductor ORCA ORSPI4 Data Sheet ORSPI4 Overview The ORSPI4 FPSC provides two SPI4.2 interface blocks, a Memory Controller and a 4-channel SERDES block, combined with FPGA logic. Based on the 1.5 V OR4E06 ORCA FPGA, it has a 46 x 44 array of Programmable Logic Cells (PLCs). The embedded core is attached to the right side of the device, as shown below, and is integrated directly into the FPGA array. A top level diagram of the basic chip conﬁguration is shown in Figure 1. Figure 1. ORSPI4 Basic Chip Conﬁguration Memory Controller I/O Serial I/O / SPI4 I/O SPI4 I/O Embedded Core Memory Controller FPGA Programmable I/O SPI4.2 I/F ORCA 4E06-Based Programmable Logic SPI4.2 I/F Shared I/O Quad SERDES Each of the logic blocks in the embedded core is functionally independent from the other blocks. Connections between blocks must be made through the FPGA logic. However, one of the SPI4 blocks and the SERDES block share I/Os. Hence the device may be conﬁgured to provide either two SPI4 interfaces or one SPI4 interface and one serial interface. What Is an FPSC? FPSCs, or Field-Programmable System Chips, are devices that combine ﬁeld-programmable logic with ASIC or mask-programmed logic on a single device. FPSCs provide the time to market and the ﬂexibility of FPGAs, the design effort savings of soft Intellectual Property (IP) cores, and the speed, design density, and economy of ASICs. FPSC Overview Lattice’s Series 4 FPSCs are created from Series 4 ORCA FPGAs. To create a Series 4 FPSC, several columns of Programmable Logic Cells are integrated with an embedded logic core. Other than replacing some FPGA gates with ASIC gates, at greater than 10:1 area efﬁciency, none of the FPGA functionality is changed—all of the Series 4 FPGA capability is retained including the Embedded Block RAMs, MicroProcessor Interface (MPI), boundary scan, etc. Pins from the replaced columns of programmable logic are used as I/O pins for the embedded core. The remainder of the device pins retain their FPGA functionality. FPSC Gate Counting The total gate count for an FPSC is the sum of its embedded core (standard-cell/ASIC gates) and its FPGA gates. Because FPGA gates are generally expressed as a usable range with a nominal value, the total FPSC gate count is sometimes expressed in the same manner. Standard-cell ASIC gates are, however, 10 to 25 times more silicon- 3 Lattice Semiconductor ORCA ORSPI4 Data Sheet area efﬁcient than FPGA gates. Therefore, an FPSC with an embedded function is gate equivalent to an FPGA with a much larger gate count. FPGA/Embedded Core Interface The interface between the FPGA logic and the embedded core has been enhanced to allow for a greater number of interface signals than on previous FPSC architectures. Compared to bringing embedded core signals off-chip, this on-chip interface is much faster and requires less power. All of the delays for the interface are precharacterized and accounted for in the ispLEVER Development System. Series 4 based FPSCs expand this interface by providing a link between the embedded block and the multi-master 32-bit system bus in the FPGA logic. This system bus allows the core easy access to many of the FPGA logic functions including the Embedded Block RAMs and the microprocessor interface. Clock spines also can pass across the FPGA/embedded core boundary. This allows for fast, low-skew clocking between the FPGA and the embedded core. Many of the special signals from the FPGA, such as DONE and global set/reset, are also available to the embedded core, making it possible to fully integrate the embedded core with the FPGA as a system. For even greater system ﬂexibility, FPGA conﬁguration RAMs are available for use by the embedded core. This allows for user-programmable options in the embedded core, in turn allowing for greater ﬂexibility. Multiple embedded core conﬁgurations may be designed into a single device with user-programmable control over which conﬁgurations are implemented, as well as the capability to change core functionality simply by reconﬁguring the device. FPSC Design Kit Development is facilitated by an FPSC design kit which, together with ispLEVER and third-party synthesis and simulation engines, provides all software and documentation required to design and verify an FPSC implementation. Included in the kit are the FPSC conﬁguration manager, and compiled Verilog simulation models, HSPICE and/or IBIS models for I/O buffers, and complete online documentation. The kit's software coupled with the design environment, provides a seamless FPSC design environment. More information can be obtained by visiting the Lattice website at http://www.latticesemi.com. SPI4 Protocol Overview The System Packet Interface Level 4, Phase 2 (SPI4) was deﬁned by the Optical Internetworking Forum (OIF) as an interface for packet and cell transfers between a Physical Layer (PHY) device and a link layer device for applications requiring up to 10 Gbit/s aggregate bandwidth. The system level model for the SPI4 interface is shown in Figure 2. 4 Lattice Semiconductor Figure 2. System Model for SPI4 Interface Link Layer in Model TSTAT[1:0] TSCLK ORCA ORSPI4 Data Sheet PHY Layer in Model Transmit Link Layer Device TDCLK TDAT[15:0] TCTL Physical (PHY) Layer Device RSTAT[1:0] RSCLK Receive Link Layer Device RDCLK RDAT[15:0] RCTL The details of the interface are speciﬁed in the OIF document “Implementation Agreement OIF-SPI4-02.0” (www.oiforum.com). That speciﬁcation is based on the system model shown in the previous ﬁgure, which, in turn, is based on the Open System Interconnect (OSI) reference model. In the system model, a “transmit interface” sends address, start and end of packet signals and error control information from a Link Layer device to a PHY device and receives ﬂow control (status) information from the PHY device. In the other direction, a “receive interface” at the Link Layer receives data from a PHY device and sends status information to the PHY device. While this convention provides a clear framework for deﬁning the system level functions, a clean separation between Link Layer and Physical Layer functionality is not often seen in actual implementations. The ORSPI4 FPSC SPI4 blocks implement the basic functions deﬁned in the standard and also implements additional options, as suggested in the standard, to conﬁgure parameters such as maximum burst size, calendar length, length of training sequence, etc. As required by the speciﬁcation, the transmit and receive interfaces operate completely independently. 5 Lattice Semiconductor ORCA ORSPI4 Data Sheet Embedded Core Overview - Functions and Features The embedded core contains four separate functional blocks, two SPI4 interface blocks, a high-speed Memory Controller block, and a quad SERDES block providing 4 channels of 0.6-3.7 Gbits/s SERDES. Features common to all blocks include: • Improved PowerPC ® 860 and PowerPC II high-speed synchronous MicroProcessor Interface that can be used for conﬁguration, readback, device control, and device status; as well as for a general-purpose interface to the FPGA logic, RAMs, and embedded standard cell blocks. Glueless interface to synchronous PowerPC processors with user-conﬁgurable address space provided. • New embedded AMBA ™ speciﬁcation 2.0 AHB system bus (ARM ® processor) facilitates communication among the MicroProcessor Interface, conﬁguration logic, and embedded core blocks. • FPSC Design Kit available for use with ispLEVER development system software. Supported by industry-standard CAE tools for design entry, synthesis, simulation, and timing analysis. SPI4 Interface Blocks - Overview The ORSPI4 FPSC provides two independent SPI4 interface blocks in the embedded core. The two SPI4 blocks are identical and the following overview applies to both blocks. In the following sections, the SPI4 protocol conventions for “transmit” and “receive” are not followed, since in various applications the ORSPI4 FPSC could be used to perform different functions at various levels in the SPI4 protocol stack. Instead, the “transmit” functions are those used to transmit data to and receive current status information from the device at the other end of the SPI4 link. The “receive” functions are those used to receive data from and transmit current status information to the device at the other end of the SPI4 link. Each SPI4 block supports a standard 10 Gbits/s physical-to-link layer interface in conformance to the speciﬁcation. This is achieved by using 16 LVDS pairs each for RX and TX that operate at a maximum data rate of 900 Mbits/s with a 450 MHz DDR clock. Data buffering of 8 Kbytes each in the transmit and receive direction (example: 256 bytes each for up to 32 ports) is provided by embedded Dual-Port RAM (DPRAM). Aggregation of buffer space is supported for systems with less than 32 ports. The internal calendar and Transmit and Receive Status FIFOs have been sized so that applications with larger numbers of ports can be supported. The ORSPI4 has been designed to support up to 256 ports, the maximum speciﬁed in the SPI4 speciﬁcation. Despite operating independently, both the transmit path and the receive path logic perform similar functions and the partitioning of both logical blocks are quite similar as shown in Figure 3. The top level partitioning is between the logic blocks to transfer and process data and control information, and the logic blocks to generate, transfer and process status information. SPI4 Interface Block Features • Each SPI4 block provides a standard 10 Gbits/s physical-to-link layer interface in conformance to the OIF-SPI402.0 speciﬁcation. Each interface provides an aggregate bandwidth of 13.6 Gbits/s. This is achieved by using 16 LVDS pairs each for RX and TX with a maximum data rate of 900 Mbits/s using a 450 MHz DDR clock. • The blocks can be used for applications such as interconnecting an OC-192 framer with a proprietary packetized interface, to a network processor with a SPI4 based packet interface or vice versa. • Support for “static” or “dynamic” alignment at the receive interface. At clock rates above 350 MHz DDR, it becomes difﬁcult to meet the tight setup/hold requirements at the receiver using static alignment. In this case, dynamic alignment is used to compensate for bit-to-bit skew. • Dynamic alignment automatically compensates for Process, Voltage, and Temperature (PVT) changes in devices and systems. – Full bandwidth up to 450 MHz DDR (900 Mbits/s throughput) – Dynamically performs alignment based on 16 phases of the RX clock for improved accuracy – Alignment algorithm can be done based on excessive bit errors on the DIP-4 calculation – Clock skews up to +/- one clock cycle can be compensated by the dynamic alignment logic 6 Lattice Semiconductor ORCA ORSPI4 Data Sheet • For low speed data, static alignment can be selected through a programmable control bit – Speeds up to 350 MHz DDR (700 Mbits/s throughput) – Dynamic alignment is bypassed and disabled to save power in static alignment mode. – Programmable on-edge or on-center clock/data relationship option at receiver. – Programmable clock delay • Single-link and multi-link operation. • SPI4 transmit data protocol support logic – Combines the data and control words from the transmit FIFO (DPRAMs) into the SPI4 format – Performs DIP-4 calculation over data and control words on the TX side and inserts into the payload control word • Handles all credit calculations based on the status information automatically • Provides optional signals to FPGA interface logic for ﬂow control: – Current transmit Port ID (Calendar Port or user speciﬁed port # per calendar port) – Current BURST_VAL Parameter for that Port – Status from that Port • Embedded Calendar-based port polling sequence mechanism and bandwidth allocation for all 256 ports – Programmable transmit and receive calendar tables support up to 256 ports • Two calendars are supported in each direction – Main Calendar (1K deep) – Shadow Calendar (also 1K deep). User can reconﬁgure second calendar while operating off main calendar, and then switch on the next cycle to allow hitless operation – All calendar conﬁguration parameters speciﬁed in the standard (CALENDAR_LEN, CALENDAR_M, etc.) are supported • Transmit and Receive Status FIFOs provided to store ﬂow control information for up to 256 ports. – Performs Status frame creation – DIP-2 odd parity calculated over the status frames – Supports either quarter-rate LVDS or LVTTL status channels • Support for various options for ﬂow control status creation, selectable per port: – Based on DPRAM FIFO ﬁll levels – Based on status from FPGA interface per port – Both of the above • Dual-port RAM interface to the FPGA supports ﬂexible data widths for both the receive and transmit FPGA/core interfaces. – Scalable data bus enables users to conﬁgure TX interface for their respective port bandwidth requirements – A total of 4 DPRAM banks where each of the DPRAMs can be logically partitioned into 1, 2, 4, or 8 virtual FIFOs – Used for temporary storage and clock domain crossing – Can be conﬁgured to provide 32-, 64-, 128-bit data bus interfaces from the FPGA (plus accompanying control signals) – 32-bit mode: Four banks are separate and accessed independently – 64-bit mode: Banks 0 & 1 become a single aggregation and Banks 2 & 3 become a single aggregation – 128-bit mode: All four banks become a single aggregation – Mixed mode: One 64-bit (two banks become a single aggregation) and two banks are separate and accessed independently • Training pattern generation – User controlled “alpha” repetitions of training pattern in TX_DATA_MAX_T intervals – Automatic generation of training pattern during loss of synchronization 7 Lattice Semiconductor • Automatic idle generation – When no data for a given channel is available for transmit – If the receiver on other end of the link is “satisﬁed” for this channel • Automatic training pattern and idle deletion in receive path ORCA ORSPI4 Data Sheet • Low-power, high performance ASIC LVDS I/Os compliant with EIA®-644 – I/O buffers support hot insertion – I/O buffers proven to operate at over 900 MHz rates (Lattice ORLI10G FPSC uses same LVDS buffers) – On-chip center tap termination for common mode noise reduction • Conﬁguration options as suggested in the OIF-SPI4-02.0 standard are supported to conﬁgure parameters such as maximum burst size, calendar length, length of training sequence, etc. • Support for three forms of loopback: – High-speed near end loopback which involves looping back data from the high-speed transmit block serial output to the high-speed receive block serial input. All of the logic up to the LVDS buffers is included in the loopback path. The LVDS buffers are bypassed – Far end loopback which involves looping back the 128-bit output data from high-speed receive block to the 128-bit input of the high-speed transmit block. Data is received at the high-speed SPI4 RX interface and transmitted at the SPI4 TX interface. The transmit protocol, receive protocol and DPRAM blocks are bypassed. This works for both static and dynamic alignment modes. – Low-speed near end loopback which excludes the high-speed blocks from the loopback path. This involves sourcing data from the FPGA, looping back the output of the transmit protocol block into the receive protocol block and observing data at the core-FPGA boundary • Support for several SPI4 debug options: – Under software control, DIP-4 errors can be forced by inverting the DIP-4 parity bits – DIP-2 errors can be forced by inverting the DIP-2 parity bits – Eight-bit counters are provided for counting DIP-4 and DIP-2 errors • SPI4 Status Reporting Capabilities: – Status information is reported through status registers. – Most conditions can also cause an alarm (interrupt) to be generated – DIP-4, DIP-2 errors – Deskew error from high-speed RX side – DPRAM Virtual FIFO overruns 8 Lattice Semiconductor Figure 3. ORSPI4 SPI4 Interface Block - Top Level Functional Partitioning Transmit Status ORCA ORSPI4 Data Sheet Transmit SPI4 Logic - Status Read Control Sequencer Port Calendar Address Map Descriptor TSTAT[1:0] Protocol Input TSCLK 32, 64, Transmit Data 128 Transmit Buffers SPI4 Logic - Data TDCLK Transmit Control FIFO_FULL Write Control DPRAM Banks Protocol Output TDAT[15:0] TCTL Receive Status Receive Transmit Buffers Address Port Map Descriptor Port Status Sequencer Calendar SPI4 Logic - Status Protocol RSTAT[1:0] Output RSCLK Receive Buffers Read Data 128 SPI4 Logic - Data RDCLK Read Control ReceiveDPRAM Write Center Banks Control Protocol Input RDAT[15:0] RCTL At the embedded core/FPGA interface, data buffering is provided by banks of DPRAM partitioned into FIFOs. FIFO reads and writes are completely decoupled. Data and accompanying address, packet delineation and error identiﬁcation information are written into the selected FIFO as received - either from the FPGA, in the transmit case, or from the receive link. For transmit, reads are performed from the FIFOs based on pre-programmed packet format information, a pre-programmed schedule for link access as read from calendar logic, and far end status information as received from the transmit status logic. In the receive direction, the receive status logic transmits information concerning the states of the receive buffers on the receive status links, while the FPGA logic reads data from the FIFOs as needed under control of the FPGA logic. The read/write control functions are similar if operating with external RAM. In this case, the internal DPRAM can be used as clock domain crossing FIFOs. Formatting/deformatting, ﬂow control processing, and error control logic forms the interface between the DPRAM banks and the SPI4 transmit and receive blocks. This logic performs the necessary conversions between the SPI4 and FPGA/core interface formats. It also performs DIP-2 (status) and DIP-4 (control) generation/checking. Finally, the SPI4 interface blocks perform the MUX/DEMUX functions for rate conversion between the internal core data paths and the SPI4 links and also provides the needed LVDS driver and receiver functions. Either static or dynamic alignment is available at the receiver interface. Dynamic alignment is used to compensate for bit-to-bit skew at higher data rates where it becomes difﬁcult to meet tight setup and hold timing requirements. 9 Lattice Semiconductor SPI4 Transmit Path Overview ORCA ORSPI4 Data Sheet The ﬁrst of the major blocks in the Transmit section contains four DPRAM banks which can be conﬁgured to provide 32-bit, 64-bit or 128-bit data bus interfaces from the FPGA to the embedded core. Providing a scalable data bus enables users to tailor the transmit interface to meet their port bandwidth requirements. For example, with a POSPHY Level 3 (PL3) interface supporting multiple PHYs (ports), a single 32-bit interface to the Transmit DPRAM is required. For an Ethernet 10 Gbits/s interface, a single port will require a single 128-bit interface to the Transmit DPRAM. To realize the various data bus interfaces or aggregation modes, the user must conﬁgure the mode within the embedded core via the MPI interface or the system bus. Multiple DPRAM banks can be aggregated into larger FIFOs. Division of the DPRAM banks into virtual partitions (up to eight) is also possible. The FPGA logic initiates a write to DPRAM by providing Data, Port ID, 3-bit FIFO Address and Write Enable signals to the SPI4 block. The internal FIFO controller latches the data and port control information into a temporary hold register that stores the data until an entire 128-bit line is captured, or an EOP is asserted. The 128-bit line is then written into the selected virtual FIFO. Associated with each FPGA data write interface, there are also control information signals and a transmit clock. The FIFO control logic transparently passes the control information to the Control memory, with the exception of the Byte Enable bits (BE[3:0]), which indicate which bytes of the associated 32-bit Word are valid. The DPRAM read logic blocks poll port data from the DPRAM banks, based on a preconﬁgured calendar sequence and the current status of each active port. The SPI4 calendar is a mechanism that maintains out-of-band statistics of the current status of each port supported across the SPI4 interface. The calendar is a reverse direction ﬂow-control mechanism used to control the dynamic bandwidth allocated for the each supported port. By periodically providing far end receive status for each port, the transmitter can modulate the amount of bandwidth allocated to a particular port dynamically. Writes to the DPRAMs from the FPGA logic are asynchronous to the calendar polling algorithm. The SPI4 transmit logic reads data from the DPRAMs according to a strict calendar sequence algorithm and will generally not read port data from the virtual FIFOs in the sequence it was written. Both a main and a shadow calendar are provided and are each 1K deep. This enables the user to provide ﬁner granularity of the polling sequence based on bandwidth allocated for each port. The length of the calendar table (CALENDAR_LEN) is programmable. CALENDAR_LEN should be at least as large as the number of active ports (channels) in the system and should not exceed the upper threshold set by the parameter (MAX_CALENDAR_LEN). There are two basic modes supported for transmitting data. Within the SPI4 core, the embedded core operates identically for all modes. At the FPGA interface, processing will be done slightly differently, depending upon the mode the user requires. Each mode is discussed below. • Embedded memory mode - This mode is used when the ORSPI4 is interfacing to asynchronous FPGA interfaces, such as POS-PHY Level 3, 1GbE, Utopia Level 3, etc. and storing the data in the virtual DPRAM FIFOs. When operating in this mode, the SPI4 transmit logic will read port data from the FIFOs according to the calendar sequence. If there is no data, it will send idle data and advance to the next port. It is the user's responsibility to ensure the proper port data has been written to the virtual FIFO. • External memory mode - This mode is used in conjunction with the Memory Controller or some other external memory based interface where data is available only after some ﬁxed delay. In this mode the SPI4 transmit logic instructs the FPGA as to what port data to retrieve as well as how many bursts of data to retrieve. The FPGA is responsible to write the data read from the Memory Controller into the DPRAMs. Data is read from the DPRAM devices by the SPI4 transmit logic according to the transmit calendar. The DPRAM read logic also includes a Port Descriptor Memory (PDM) which is a user conﬁgurable memory containing a list of read control parameters for all enabled ports to be polled. The depth of the memory is 256 locations, 10 Lattice Semiconductor ORCA ORSPI4 Data Sheet which corresponds to the maximum number of ports that are supported by SPI4. The PDM data is comprised of three separate segments - a 10-bit dynamic table maintained by the SPI4 logic, a static 20-bit table, and a dynamic 3-bit register ﬁle written by the FIFO Status Update (FSU) logic. The PDM provides a mapping of the SPI4 port number to the FPGA interface device/port number, removing the burden from FPGA logic. When port data is read from the PDM, a status update bit (the U-bit) is ﬁrst examined to see whether the STAT ﬁeld is new or stale. If stale, then the STAT ﬁeld is not considered for the rest of processing. If the STAT ﬁeld is new (Ubit=1) the STAT ﬁeld is used in conjunction with other ﬁeld to calculate what the new Credit ﬁeld for the port should be. A SATISFIED status indicates the corresponding port's FIFO is almost full, and only transfers using the remaining previously granted 16-byte blocks (if any) may be sent to corresponding port until the next status update. No additional transfers to that port are permitted. When a HUNGRY status indication is received, transfers up to MAXBURST2 16-byte blocks or the remainder of what was previously granted (whichever is greater), may be sent to the corresponding port prior to the next status update. A STARVING status indication indicates that buffer underﬂow is imminent in the corresponding PHY port. When STARVING is received, transfers for up to MAXBURST1 16-byte blocks may be sent to the corresponding port prior to the next status update. If the U-bit is cleared, this indicates the STAT ﬁeld has already been used to update the Credit ﬁeld on a previous Port servicing. Therefore, the Credit ﬁeld should simply be reduced by BURST_VAL. Otherwise, the Credit ﬁeld is updated to the new Credit value minus BURST_VAL. In both cases, the output of the logic is used to update the Credit ﬁeld. If the Credit ﬁeld is zero, and the STAT ﬁeld is stale, then the port receives no service. Read accesses of the port control information need to be optimized to minimize any lost bandwidth due to the Credit ﬁeld having a value of zero. Data read from the DPRAMS is sent to the SPI4 transmit block which is responsible for the following functions: • Combining the data and control words from the Transmit FIFO into the data format speciﬁed in the OIF SPI4 standard. • DIP-4 calculation and insertion into the payload control word. • Generation of idle/training control words in programmable intervals. Training words are used to dynamically align the far end receiver. As long as a disabled status ‘11’ is received on the SPI4 status channel, the transmit interface block sends continuous training patterns (10 training control words followed by 10 training data words). When valid status is received on the status channel, user data is normally sent on the SPI4 data link. However, users can also periodically schedule training patterns in TX_DATA_MAX_T periods. The training patterns can be repeated TX_ALPHA times. Both TX_ALPHA and TX_DATA_MAX_T are programmable control register bits. The SPI4 transmit block contains the high-speed serializer which uses the x8 clock, synthesized by an internal PLL, to generate the high-speed data from the low-speed 128-bit FIFO data. Data is transmitted off-chip using a 16-bit LVDS data bus - TDAT[15:0], a LVDS control bit - TCTL, and a source synchronous clock - TDCLK. The 16-bit data bus and control are DDR with respect to TDCLK. In order to support 10 Gbits/s throughput, the minimum frequency of TDCLK needs to be 622 Mbits/s (311 MHz DDR). To allow considerable margin above this minimum data rate a maximum frequency of operation of 900 Mbits/s is supported. The Transmit Status Protocol (S4TSP) block provides the interface to the SPI4 Transmit Status interfaces. These signals can be either LVDS or LVCMOS buffers. The S4TSP block is responsible for the following functions: • FIFO Status Decoding and Buffering. • Framing using the status framing pattern. • DIP-2 checking of incoming status information. 11 Lattice Semiconductor ORCA ORSPI4 Data Sheet The FIFO Status Update logic block reads the Port and Status information and uses this information to update Port Descriptor Memory STAT ﬁeld. Whenever a valid STAT ﬁeld has been updated, the associated U-bit ﬁeld is set as discussed previously. This indicates that the STAT ﬁeld is new and that the Credit ﬁeld for that must be re-evaluated the next time it is selected as a source for transmit data. SPI4 Receive Path Overview In the receive direction, data is received in SPI4 format on the LVDS I/Os at the receive interface. The data is written into DPRAM as received and read from the DPRAMs as requested by the FPGA logic. Control information is also interpreted and buffered and idles and training sequences are removed from the incoming data stream. Receive FIFO status is transmitted from the Receive Status interface according to a pre-conﬁgured polling sequence contained within the Receive Calendar. Data is formatted into the SPI4 Receive Status format and sent to the physical links as either LVDS or LVTTL signals. The SPI4 block contains the high-speed receive logic. Incoming LVDS signals, in SPI4 format, include the 16-bit data bus (RDAT[15:0]), a control bit (RCTL) and a source synchronous DDR clock (RDCLK). The incoming data is deserialized to a 128-bit format and the control information is converted to an 8-bit format. The SPI4 receive block also detects training patterns and performs dynamic alignment of the incoming data. At speeds above 700 Mbit/s (350 MHz) it becomes necessary to use dynamic alignment. Skews of up to ± one clock period can be compensated by the dynamic alignment logic. For low speed incoming data, static alignment can be chosen through a programmable control bit. Various timing options of receive data vs. receive clock are also programmable. The SPI4 block is responsible for decoding the in-band control information. It then forwards both the data and control information, such as link address, SOP, EOP and error, to the virtual FIFOs. The SPI4 block also parses the control words embedded within the incoming data. Using this control information, it performs the following functions: • Checks DIP-4 parity • Monitors for continuous alignment (if more than a programmable number of DIP-4 parity errors exist, there may be an alignment problem). • Removes idle/training words. • Extracts link address and SOP, EOP and valid packet (no error) signals. In the receive direction there are also four Dual Port Memory (DPRAM) banks that contain a total of 8K bytes available for clock domain crossing and/or temporary buffering. As with the transmit buffers, each bank can be further partitioned up to 8 virtual memories, one for each of 8 ports. The following are the characteristics of the DPRAM virtual FIFOs: • The DPRAM memories support asynchronous reads. Each DPRAM bank can be accessed on the FPGA side with an individual clock. • For data buffering beyond 32 ports, the DPRAM banks can be used as clock domain crossing FIFOs before writing the data and control information into an external memory. If fewer ports are supported, the virtual memories can be aggregated, providing more buffer space for each port. • Each DPRAM bank has a 32-bit data and 8-bit control read interface to the FPGA. When using the DPRAM memories, the data can be read as either a 32-, 64-, or 128-bit data bus with associated control signals. • At any time, the user can poll the status of a FIFO within a DPRAM bank by providing just the read address without a valid read enable. • A FIFO empty ﬂag is generated by the read control logic to the FPGA. This empty ﬂag can be programmed to indicate truly empty or < 1/4 full (1/4 full - 1). 12 Lattice Semiconductor ORCA ORSPI4 Data Sheet In addition to formatting received data and sending it to the FPGA logic, the receive block also sends status information to the SPI4 status interface. The Port Status Sequencer (PSS) block is responsible for providing port status to the SPI4 Receive Status block logic according to a pre-conﬁgured calendar sequence. Status is derived from the ﬁll-levels of the DPRAM FIFOs and/or from the FPGA status interface. The SPI4 Receive Status block is responsible for FIFO status encoding, calendar management, status pattern encoding (sync bits “11”), DIP-2 calculation and optional calendar selection word encoding. The SPI4 Receive Status block contains the low speed LVTTL output buffers and LVDS output buffers necessary for the output stage of receive status logic. The option to choose between LVTTL or LVDS outputs is done by setting a control register bit. SPI4 Debugging and Statistics Gathering Support There are also several other features, including three loopback modes incorporated into the embedded core to assist in debugging and statistic gathering. These features involve both the transmit and receive paths. The three forms of loopback supported directly are: • High-speed near-end loopback • Far-end high-speed loopback • Low-speed near-end loopback The SPI4 blocks support the following error insertion and status reporting options for testing: • DIP-4 odd parity is calculated over data and control words and inserted on the TX side. DIP-4 errors can be forced by inverting the DIP-4 parity bits. DIP-4 parity is then checked at the receive interface. • DIP-2 odd parity is calculated over the status frames and inserted on the RX side. DIP-2 errors can be forced by inverting the DIP-2 parity bits. DIP-2 parity is then checked at the transmit status interface. • Eight-bit counters are provided for counting DIP-4 and DIP-2 errors. • Deskew error reporting for high-speed RX side dynamic alignment. This can cause an alarm. • DPRAM FIFO overrun reporting. These can cause an alarm. 13 Lattice Semiconductor Memory Controller - Overview ORCA ORSPI4 Data Sheet The Memory Controller block controls an interface to external Quad Data Rate (QDRII) SRAM for data buffering between the FPGA logic and external memory. The key features of the Memory Controller interface are described below: Memory Controller Features • Independent Memory Controller interface to external Quad Data Rate (QDRII) SRAMs from multiple suppliers for data buffering. – Provides additional packet buffering for > 32 ports – Provides trafﬁc smoothing for any number of ports • The Controller supports a throughput of greater than 20 Gbits/s so that all the data received on the SPI4 interface at 10 Gbits/s can be buffered. • The QDRII SRAM supports this throughput with 36 unidirectional data lines in both the read and write directions. • The controller block provides the ability to access external QDRII SRAM through the FPGA. – A set of 72 data signals across the core-FPGA interface – Of the 72, 8 signals can be either used for parity or data. – Simple asynchronous FIFO interface to FPGA for ease of design. A high-speed clock signal is provided to the FPGA as an option to make the write and read synchronous, if desired. • The core passes the data transparently to and from the QDRII SRAM in two-word or four-word bursts. Interfaces to memory are 36 bits wide and the address buses are 18 bits wide. – Supports the interfaces required for a 512K x 36 bit (18 Mbit) QDRII SRAM in two-word burst mode. – Only 17 address lines are required in four-word burst mode. • Status/Alarm reported to user through registers – Data length mismatch from the write controller state machine – Data instruction coherency error – Write data, Read data FIFO overrun and underrun errors • Additional high-speed Memory Controller can be implemented in FPGA gates if required. SERDES Logic Block - Overview The SERDES logic block in of the ORSPI4 contains four Clock and Data Recovery (CDR) macrocells and four Serializer/Deserializer (SERDES) macrocells to support four channels of 8b/10b (IEEE 802.3.2002) encoded serial links. The logic block also contains Fiber Channel and XAUI-based state machines, logic to support multi-channel alignment and MUX/DEMUX logic for the FPGA/core interface. Figure 4 shows the SERDES top level block diagram and the basic data ﬂow. Boundary scan for the SERDES only includes programmable I/Os and does not include any of the embedded block I/Os. 14 Lattice Semiconductor Figure 4. SERDES Top Level Block Diagram. ORCA ORSPI4 Data Sheet 0.6 Gbits/s TO 3.7 Gbits/s DATA STANDARD FPGA I/Os ORCA SERIES 4 FPGA LOGIC BYTE- SERDES w/ 8b/10b WIDE CLOCK/DATA DECODER/ENCODER DATA RECOVERY 4:1 MUX/1:4 DEMUX CML I/Os 4 FULLDUPLEX SERIAL CHANNELS 0.6 Gbits/s TO 3.7 Gbits/s DATA The serial channels can each operate at up to 3.7 Gbits/s (2.96 Gbits/s data rate) with a full-duplex synchronous interface with built-in clock recovery (CDR). The 8b/10b encoding provides guaranteed ones density for the CDR, byte alignment, and error detection. The core is also capable of frame synchronization and physical link monitoring. An overview of the individual blocks in the embedded core is presented in the following paragraphs. The SERDES portion of the core contains a quad transceiver block for serial data transmission at a selectable data rate of 0.6 to 3.7 Gbits/s. Each SERDES channel features high-speed 8b/10b parallel I/O interfaces to other core blocks and high-speed CML interfaces to the serial links. Serializer and Deserializer (SERDES) The SERDES portion of the core contains a transceiver block for serial data transmission at a selectable data rate of 0.6-3.7 Gbits/s. Each SERDES channel features high-speed 8b/10b parallel I/O interfaces to other core blocks and high-speed CML interfaces to the serial links. The SERDES circuitry consists of receiver, transmitter, and auxiliary functional blocks. The receiver accepts highspeed (up to 3.7 Gbits/s) serial data. Based on data transitions, the receiver locks an analog receive PLL for each channel to retime the data, then demultiplexes the data down to parallel bytes and an accompanying clock. The transmitter operates in the reverse direction. Parallel bytes are multiplexed up to 3.7 Gbits/s serial data for offchip communication. The transmitter generates the necessary clocks from a lower speed reference clock. The transceiver is controlled and conﬁgured through the system bus in the FPGA logic and through the external 8bit microprocessor interface of the FPGA. Each channel has associated dedicated registers that are readable and writable. There are also global registers for control of common circuitry and functions. The SERDES performs 8b/10b encoding and decoding for each channel. The 8b/10b transmission code can support either Ethernet or Fibre Channel speciﬁcations for serial encoding/decoding, special characters, and error detection. The user can disable the 8b/10b decoder to receive raw 10-bit words, which will be rate reduced by the SERDES. If this mode is chosen, the user must also bypass the multichannel alignment FIFOs. The SERDES macrocell contains its own dedicated PLLs for both transmit and receive clock generation. The user provides a reference clock of the appropriate frequency. The receiver PLLs extract the clock from the serial input data and re-time the data with the recovered clock. MUX/DEMUX Block The MUX/DEMUX logic converts the data format for the high-speed serial links to a wide, low-speed format for crossing the CORE/FPGA interface. The intermediate interface to the SERDES macrocell runs at 1/10th the bit 15 Lattice Semiconductor ORCA ORSPI4 Data Sheet rate of the data lane. The MUX/DEMUX converts the data rate and bus width so the interface to the FPGA core can run at 1/4th this intermediate frequency, giving a range of 25.0 to 92.5 MHz for the data rates into and out of the FPGA logic. Multi-Channel Alignment FIFOs In the ORSPI4 SERDES block, the four incoming data channels can be independent of each other or can be synchronized in several ways. Two channels within a SERDES block can be aligned together; channels A and B and/or channels C and D. Finally, four channels in a SERDES block can be aligned together to form a communication channel with a bandwidth of 10 Gbits/s. Individual channels within an alignment group can be disabled (i.e., powered down) without disrupting other channels. XAUI and Fibre Channel Link State Machines Two separate link state machines are included in the architecture. A XAUI-based link state machine is included in the embedded core to implement the IEEE 802.3ae standard. A separate state machine for Fibre Channel is also implemented. FPGA/Embedded Core Interface In 8b/10b mode, the FPGA logic will receive/transmit 32-bits of data (up to 92.5 MHz) and four K_CTRL bits from/to the embedded core. There are 4 data streams in each direction plus additional timing, status and control signals. Data sent to the FPGA can be aligned using comma (/K/) characters or /A/ character as speciﬁed either by Fibre Channel or by IEEE 802.3ae for XAUI based interfaces. The alignment character is made available to the FPGA along with the data. The special characters K28.1, K28.5 and K28.7 are treated as valid comma characters by the SERDES. If the receive channel alignment FIFOs are bypassed, then each channel will provide its own receive clock in addition to data and comma character detect signals. If the 8b/10b decoders are bypassed, then 40-bit data streams are passed to the FPGA logic. No channel alignment can be done in 8b/10b bypass mode. SERDES Features • Four channels of 0.6-3.7G SERDES with 8b/10b encoding/decoding are supported. The SERDES quad is IEEE P802.3ae/D4.01 XAUI based and also supports the FC (ANSI X3.230:1994) link synchronization state machine speciﬁcation. • The high-speed SERDES are programmable and support serial data rates including 622 Mbits/s, 1.0 Gbits/s, 1.25 Gbits/s, 2.5 Gbits/s, 3.125 Gbits/s, and 3.7 Gbits/s. Operation has been demonstrated on design tolerance devices at 3.7 Gbits/s across 26 in. of FR-4 backplane and at 3.2 Gbits/s across 40 in. of FR-4 backplane across temperature and voltage speciﬁcations. • Asynchronous operation per receive channel, with the receiver frequency tolerance based on one reference clock per four channels (separate PLL per channel). • Ability to select full-rate or half-rate operation per transmit or receive channel by setting the appropriate control registers. • Programmable one-half amplitude transmit mode for reduced power in chip-to-chip application. • Transmit preemphasis (programmable) for improved receive data eye opening. • 32-bit (8b/10b) or 40-bit (raw data) parallel internal bus for data processing in FPGA logic. • Provides a 10 Gbits/s backplane interface to a switch fabric using four 2.5 Gbit/s links. Also supports port cards at 2.5 Gbit/s. • 3.125 Gbits/s SERDES compliant with XAUI serial data speciﬁcation for 10 Gigabit Ethernet applications. • Most XAUI features for 10 Gigabit Ethernet are embedded including the required link state machine. • Compliant to Fibre Channel physical layer speciﬁcation. 16 Lattice Semiconductor ORCA ORSPI4 Data Sheet • High-Speed Interface (HSI) function for clock/data recovery serial backplane data transfer without external clocks. • Four-channel HSI functions provide 2.96 Gbits/s serial user data interface per channel (8b/10b encoding and decoding) for a total chip bandwidth of > 10 Gbits/s (full duplex). • SERDES have low-power CML buffers and support 1.5 V or 1.8 V I/Os. This allows use of the SERDES with optical transceiver, coaxial copper media, shielded twisted pair wiring or high-speed backplanes such as FR-4. • Powerdown option of SERDES HSI receiver or transmitter is on a per-channel basis. • Automatic lock to reference clock in the absence of valid receive data. • High-speed and low-speed loopback test modes. • No external components required for clock recovery and frequency synthesis. • Built-in boundary scan (IEEE ® 1149.1 and 1149.2 JTAG) for the programmable I/Os, not including the SERDES interface. • FIFOs can align incoming data either across groups of four channels or groups of two channels. Alignment is done either using comma characters or by using the /A/ character in XAUI mode. Optional ability to bypass the alignment FIFOs for asynchronous operation between channels (Each channel includes its own clock and frame pulse or comma detect). ORSPI4 FPGA Logic Overview The following sections provide a brief overview of the main architectural features of the ORSPI4 FPGA logic. For more detailed information, please refer to the ORCA Series 4 FPGA Data Sheet which can be found under the “Products” folder on the Lattice Semiconductor main Web site: www.latticesemi.com. The ORCA Series 4 FPGA Data Sheet provides detailed information required for designing with the ORSPI4 device. Topics covered in the ORCA Series 4 Data Sheet include: • FPGA Logic Architecture • FPGA Routing Resources • FPGA Clock Routing Resources • FPGA Programmable Input/Output Cells (PICs) • FPGA Embedded Block RAM (EBR) • Microprocessor Interface (MPI) • Phase-Locked Loops (PLLs) • Electrical Characteristics • FPGA Timing Characteristics • Power-up • Conﬁguration ORCA Series 4 FPGA Logic Overview The ORCA Series 4 architecture is a new generation of SRAM-based programmable devices from Lattice. It includes enhancements and innovations geared toward today’s high-speed systems on a single chip. Designed with networking applications in mind, the Series 4 family incorporates system-level features that can further reduce logic requirements and increase system speed. ORCA Series 4 devices contain many new patented enhancements and are offered in a variety of packages and speed grades. 17 Lattice Semiconductor ORCA ORSPI4 Data Sheet The hierarchical architecture of the logic, clocks, routing, RAM, and system-level blocks create a seamless merge of FPGA and ASIC designs. Modular hardware and software technologies enable System-on-Chip integration with true plug-and-play design implementation. The architecture consists of the following basic elements: Programmable Logic Cells (PLCs), Programmable I/O cells (PIOs), Embedded Block RAMs (EBRs), plus supporting system-level features. These elements are interconnected with a rich routing fabric of both global and local wires. An array of PLCs is surrounded by common interface blocks that provide an abundant interface to the adjacent PLCs or system blocks. Routing congestion around these critical blocks is eliminated by the use of the same routing fabric implemented within the programmable logic core. Each PLC contains a Programmable Function Unit (PFU), Supplemental Logic Interconnect Cell (SLIC), local routing resources, and conﬁguration RAM. Most of the FPGA logic is performed in the PFU, but decoders, PAL-like functions, and 3-state buffering can be performed in the SLIC. The PIOs provide device inputs and outputs and can be used to register signals and to perform input demultiplexing, output multiplexing, uplink and downlink functions, and other functions on two output signals. Large blocks of 512 x 18 quad-port RAM complement the existing distributed PFU memory. The RAM blocks can be used to implement RAM, ROM, FIFO, multiplier, and CAM. Some of the other system-level functions include the MPI, PLLs, and the Embedded System Bus (ESB). 18 Lattice Semiconductor Programmable Logic Features ORCA ORSPI4 Data Sheet • High-performance programmable logic: – 0.16 µm, 7-level metal technology. – Internal performance of >250 MHz. – Over 600K usable system gates. – Meets multiple I/O interface standards. – 1.5 V operation (30% less power than 1.8 V operation), translates to greater performance. • Traditional I/O selections: – LVTTL (3.3V) and LVCMOS (2.5 V and 1.8 V) I/Os. – Per pin-selectable I/O clamping diodes provide 3.3 V PCI compliance. – Individually programmable drive capability: 24 mA sink/12 mA source, 12 mA sink/6 mA source, or 6 mA sink/3 mA source. – Two slew rates supported (fast and slew-limited). – Fast-capture input latch and input Flip-Flop (FF)/latch for reduced input setup time and zero hold time. – Fast open-drain drive capability. – Capability to register 3-state enable signal. – Off-chip clock drive capability. – Two-input function generator in output path. • New programmable high-speed I/O: – Single-ended: GTL, GTL+, PECL, SSTL3/2 (Class I and II), HSTL (Class I, III, IV), ZBT, and DDR. – Double-ended: LVDS, bused-LVDS, and LVPECL. Programmable, (on/off) internal parallel termination (100 Ω) is also supported for these I/Os. • New capability to (de)multiplex I/O signals: – New DDR on both input and output at rates up to 350 MHz (700 Mbits/s effective rate). – New 2x and 4x downlink and uplink capability per I/O (i.e., 50 MHz internal to 200 MHz I/O). • Enhanced twin-quad Programmable Function Unit (PFU): – Eight 16-bit Look-Up Tables (LUTs) per PFU. – Nine user registers per PFU, one following each LUT, and organized to allow two nibbles to act independently, plus one extra for arithmetic operations. – New register control in each PFU has two independent programmable clocks, clock enables, local SET/RESET, and data selects. – New LUT structure allows ﬂexible combinations of LUT4, LUT5, new LUT6, 4 → 1 MUX, new 8 → 1 MUX, and ripple mode arithmetic functions in the same PFU. – 32 x 4 RAM per PFU, conﬁgurable as single- or dual-port. Create large, fast RAM/ROM blocks (128 x 8 in only eight PFUs) using the Supplemental Logic and Interconnect Cell (SLIC) decoders as bank drivers. – Soft-Wired LUTs (SWL) allow fast cascading of up to three levels of LUT logic in a single PFU through fast internal routing which reduces routing congestion and improves speed. – Flexible fast access to PFU inputs from routing. – Fast-carry logic and routing to all four adjacent PFUs for nibble-wide, byte-wide, or longer arithmetic functions, with the option to register the PFU carry-out. • Abundant high-speed buffered and non-buffered routing resources provide 2x average speed improvements over previous architectures. • Hierarchical routing optimized for both local and global routing with dedicated routing resources. This results in faster routing times with predictable and efﬁcient performance. • SLIC provides eight 3-state buffers, up to a 10-bit decoder, and PAL™-like AND-OR-Invert (AOI) in each programmable logic cell. • New 200 MHz embedded quad-port RAM blocks, 2 read ports, 2 write ports, and 2 sets of byte lane enables. Each embedded RAM block can be conﬁgured as: – 1—512 x 18 (quad-port, two read/two write) with optional built in arbitration. 19 Lattice Semiconductor – – – – – – – – – ORCA ORSPI4 Data Sheet 1—256 x 36 (dual-port, one read/one write). 1—1K x 9 (dual-port, one read/one write). 2—512 x 9 (dual-port, one read/one write for each). 2 RAMS with an arbitrary number of words whose sum is 512 (or less) x 18 (dual-port, one read/one write). Supports joining of RAM blocks. Two 16 x 8-bit content addressable memory (CAM) support. FIFO 512 x 18, 256 x 36, 1K x 9, or dual 512 x 9. Constant multiply (8 x 16 or 16 x 8). Dual variable multiply (8 x 8). • Embedded 32-bit internal system bus plus 4-bit parity interconnects FPGA logic, MicroProcessor interface (MPI), embedded RAM blocks, and embedded standard cell blocks with 100 MHz bus performance. Included are builtin system registers that act as the control and status center for the device. • Built-in testability: – Full boundary scan (IEEE 1149.1 and Draft 1149.2 JTAG). – Programming and readback through boundary scan port compliant to IEEE Draft 1532:D1.7. – TS_ALL testability function to 3-state all I/O pins. – New temperature-sensing diode. • Improved built-in clock management with Programmable Phase-Locked Loops (PPLLs) provide optimum clock modiﬁcation and conditioning for phase, frequency, and duty cycle from 20 MHz up to 420 MHz. Multiplication of the input frequency up to 64x and division of the input frequency down to 1/64x possible. • New cycle stealing capability allows a typical 15% to 40% internal speed improvement after ﬁnal place and route. This feature also enables compliance with many setup/hold and clock to out I/O speciﬁcations and may provide reduced ground bounce for output buses by allowing ﬂexible delays of switching output buffers. Programmable Logic System Features • PCI local bus compliant for FPGA I/Os. • Improved PowerPC ® 860 and PowerPC II high-speed synchronous microprocessor interface can be used for conﬁguration, readback, device control, and device status, as well as for a general-purpose interface to the FPGA logic, RAMs, and embedded standard cell blocks. Glueless interface to synchronous PowerPC processors with user-conﬁgurable address space provided. • New embedded AMBA ™ speciﬁcation 2.0 AHB system bus (ARM ® processor) facilitates communication among the microprocessor interface, conﬁguration logic, Embedded Block RAM, FPGA logic, and embedded standard cell blocks. • Variable size bused readback of conﬁguration data capability with the built-in microprocessor interface and system bus. • Internal, 3-state, and bidirectional buses with simple control provided by the SLIC. • New clock routing structures for global and local clocking signiﬁcantly increases speed and reduces skew ( 8 mA IOL > -8 mA IOH > 16 mA IOL > -16 mA Min 1.425 0.64 -REFI + 100mV -0.3 VDDH - 0.4 -VDDH - 0.4 -Typical 1.5 0.75 0.75 0.85 0.65 1.1 -1.1 -Max 1.575 0.87 VDDH + 0.3 REFI -100 mV -0.4 -0.4 Unit V V V V V V V V V 1. 50% VDDH 2. VDDH - 400 mV. 189 Lattice Semiconductor Figure 98. HSTL Termination Scheme VDDH (1.5V) VDDMEM_IO 2 ORCA ORSPI4 Data Sheet 75 ohm PMIK(N) & HSTL-II Output Buffer Z = 50 ohm VTERM = VDDH 2 VDDMEM_IO 2 VDDMEM_IO (1.5V) PMIC(N) Signals 75 ohm Z = 50 ohm REFI = VDDH 2 VDDH (1.5V) VDDMEM_IO 2 PMID, PMIA, PMIWN, PMIRN & PMIQ 50 ohm HSTL-II Output Buffer 25 ohm Z = 50 ohm VDDMEM_IO 2 VTERM = VDDH 2 VDDMEM_IO (1.5V) 50 ohm Signals REFI = VDDH 2 Z = 50 ohm EXT_1K ORSPI4 QDR Memory Device * * Refer to memory specification for specific terminations 1.5 Kohm Note: Refer to Technical Note TN1046 for more detailed board design guidelines for the ORSPI4 QDR Memory Controller. 190 Lattice Semiconductor ORCA ORSPI4 Data Sheet Supported Data Rates The Memory Controller on the ORSPI4 device can support the following data rates. Table 74. Supported Data Rates (36-Bit QDR-II, 32 bit Considered Data) Data Rate -1 Clock Frequency (DDR) 156 MHz Data Rate1, 2 19.97 Gbps 3 -2 Clock Frequency (DDR) Data Rate 165 MHz 1, 2 3 -3 Clock Frequency (DDR) 175 MHz Data Rate1, 2 22.40 Gbps3 21.12 Gbps 1. Data Rate = (Max. write data rate + Max. read data rate) for 32 bits of data. 2. Characterized with 200 Mhz rated QDR-II SRAM devices with their DLL enabled. Duty cycle of PMIC and PMICN signals was close to 50%. 3. Assumes board trace lengths of 3 inches or less. Memory Controller Input/Output Timing Speciﬁcation Figure 99. Memory Controller Output Timing Speciﬁcations PMIK DPMIK(N) PMIKN Tav Tai PMIA Tdv T di PMID Table 75. Memory Controller Output Timing Speciﬁcations Symbol tai tav tdi tdv DPMIK(N) Description PMIK to previous address invalid PMIK to address valid PMIK to previous data invalid PMIK to data valid PMIK/PMINKN duty cycle Min Value 1.2 2.0 1.0 2.65 40% Max Value – – – – 60% Units ns ns ns ns PMIK/PMIKN Clock Cycle 191 Lattice Semiconductor Figure 100. Memory Controller Input Timing Speciﬁcations ORCA ORSPI4 Data Sheet PMIC PMICN PMIQ T rs Trh Tfs T rs Table 76. Memory Controller Input Timing Speciﬁcations Symbol trs trh tfs tfh Description PMIQ data in setup with respect to PMIC clock rising edge PMIQ data in hold with respect to PMIC clock rising edge PMIQ data in setup with respect to PMICN clock rising edge PMIQ data in hold with respect to PMICN clock rising edge Min Value -0.5 2.0 -0.5 2.0 Units ns ns ns ns 192 Lattice Semiconductor ORCA ORSPI4 Data Sheet Power Supplies for ORSPI4 Power Supply Descriptions Table 77 shows the ORSPI4 FPGA and embedded core power supply groupings. VDD33 Is a 3.3V positive power supply used for 3.3 V conﬁguration RAMs. VDD33_FPGAPLL is a 3.3V positive power supply for internal PLLs. When using PLLs, this power supply should be well isolated from all other power supplies on the board for proper operation. The ﬁve VDDIO supplies are positive power supply used by the FPGA I/O banks. The 1.5 volt digital power supplies are used for the FPGA and the embedded core transmit and receive digital logic including the microprocessor logic. The 1.5 volt analog power supply is used for SERDES high-speed analog circuitry in the embedded core between the I/O buffers and the digital logic. The SERDES VDDIB and VDDOB power supplies can be independently set to 1.5 V or 1.8 V, depending on the end application. The SERDES guard band supplies are independent connection brought out to pins. Table 77. Power Supplies FPGA Supplies VDD15 VDD33 VDD33_FPGAPLL VDDIO0 VDDIO1 VDDIO5 VDDIO6 VDDIO7 The ORSPI4 SPI4 embedded core requires an isolated 1.5V supply connected to four dedicated VDDA_SPI[A:D] pins. This supply is used to power the analog circuitry of the core between the LVDS I/O and the digital logic. The LVDS bus also requires connections to pins used for AC center-tap termination. The dedicated LVCTAP pins should be connected to GND through a 0.01 uFd capacitor. The QDR memory controller portion of the embedded core has dedicated HSTL I/O buffers which require an additional 1.5V supply known as VDDH. The HSTL input buffers uses an external reference voltage. The reference voltage connects to the REFI_[1:4] pins. The REFI pins should ideally be connected to a noise immune source that is exactly 1/2 the value of the VDDH supply. Table 78. Embedded Core Power Supplies Supply Description SERDES Input Buffers (1.5/1.8V) SERDES Guardband (1.5V) SERDES Output Buffers (1.5/1.8V) SERDES Analog (1.5V) SPI (1.5V) Memory Controller PLL (3.3V) HSTL Input Buffer Reference Voltage (VDDH/2) VDDA_SPIA VDDOB_A VDDIB_A VDDIB_B VDDGB VDDOB_B VDDA_SPIB VDDOB_C VDDA_SPIC VDDOB_D VDDA_SPID VDD_ANA VDDA_PLL REFI_1 REFI_2 REFI_3 REFI_4 HSTL Output Buffer Supply (1.5V) VDDH Name VDDIB_C VDDIB_D 193 Lattice Semiconductor Recommended Power Supply Connections Ideally, a board should have the power supplies described below: • VDD33, VDD33_FPGAPLL and VDDIO supplies for the FPGA Logic • A single 1.5 V source to supply power to FPGA and core digital logic. (VDD15) ORCA ORSPI4 Data Sheet • A dedicated 1.5 V power supply for the SERDES analog power pins. This will allow the end user to minimize noise. The guard band pins can also be sourced from the analog power supplies. (VDD_ANA, VDDGB) • SERDES TX output buffer power. The power supplies to the SERDES TX output buffers should be isolated from the rest of the board power supplies. Special care must be taken to minimize noise when providing board level power to these output buffers. The power supply can be 1.5 V or 1.8 V depending on the end application. (VDDOB) • SERDES RX input buffer power. The power supplies to the SERDES RX input buffers should be isolated from the rest of the board power supplies. Special care must be taken to minimize noise when providing board level power to these input buffers. The power supply can be 1.5 V or 1.8 V depending on the end application. (VDDIB) • An isolated 1.5V supply for the VDDA_SPI to minimize noise from the common 1.5V board supply. (VDD_SPI[A:D]) • The memory controller bus requires a dedicated 1.5V supply connected to the VDDH pins for HSTL output buffer supply voltage. (VDDH) • The HSTL input buffers of the Memory Controller require a voltage reference connected to the REFI pins which is half the VDDH supply. This supply should be ﬁltered, and should not exceed a peak-to-peak AC noise of 2% of the VREF (DC). The HSTL buffer scheme also requires a termination resistor per signal. It is recommended that the clock pin termination be ﬁltered separately from the data/control pin termination to minimize noise. • The VDDA_PLL supply pin requires a noise minimized 3.3V supply. Recommended Power Supply Filtering Scheme The board connections of the various SERDES VDD and VSS pins are critical to system performance. An example demonstration board schematic is available at www.latticesemi.com. Power supply ﬁltering is in the form of: • A parallel bypass capacitor network consisting of 10 µf, 0.1 µf, and 1.0 µf caps close to the power source. • A parallel bypass capacitor network consisting of 0.01 µf and 0.1 µf close to the pin. • The decoupling capacitor sizes are important as is the employment of various styles of capacitors. This provides frequency response coverage across a greater frequency bandwidth. General decoupling guidelines can be found in Lattice Semiconductor Application Note TN1068. • Example connections are shown in Figure 101. The naming convention for the power supply sources shown in the ﬁgure are as follows: – Supply_1.5 V – All digital, auxiliary power pins. – Supply_VDDIB – Input RX buffer power pins for SERDES. – Supply_VDDOB – Output TX buffer power pins for SERDES. – Supply_VDDANA – TX analog power pins, RX analog power pins, guard band power pins for SERDES. – Supply_VDD33, VDDA_PLL - FPGA and Embedded PLL power pins. – Supply VDDA_SPIA, VDDA_SPIB, VDDA_SPIC, VDDA_SPID - Analog core 1.5V SPI supplies. – Supply VDDH - HSTL output buffer power supply of the QDR Memory Controller. – Supply REFI_1, REFI_2, REFI_3, REFI_4 - Voltage reference for HSTL input buffer of the QDR Memory Controller should be one-half VDDH 194 Lattice Semiconductor Figure 101. Power Supply Filtering SOURCE SUPPLY_1.5 V ORCA ORSPI4 Data Sheet 4.7 μH PIN VDD15 0.1 μf 10 μf 1 μf 0.01 μf 0.1 μf —1 NETWORK FOR EVERY 2 PINS SUPPLY_VDD Analog 4.7 μH VDD_ANA 0.1 μf 10 μf 1 μf 0.01 μf 0.1 μf —1 NETWORK FOR EVERY 2 PINS —1 EACH FOR VDDGB_[A,B] SUPPLY_VDDIB 4.7 μH VDDIB 0.1 μf 10 μf 1 μf 0.01 μf 0.1 μf —1 NETWORK FOR EVERY 2 PINS SUPPLY_VDDOB 4.7 μH VDDOB 0.1 μf 10 μf 1 μf 0.01 μf 0.1 μf —1 NETWORK FOR EVERY 2 PINS 4.7 μH SUPPLY_1.5 V PIN VDDH 0.1 μf 10 μf 1 μf 0.01 μf 0.1 μf —1 NETWORK FOR EVERY 2 PINS 195 Lattice Semiconductor Power Supply Filtering (Continued) SOURCE SUPPLY_1.5 V ORCA ORSPI4 Data Sheet 4.7 μH PIN VDDA_SPI 0.1 μf 10 μf 1 μf 0.01 μf 0.1 μf —1 NETWORK FOR EVERY 2 PINS SUPPLY_3.3 V 4.7 μH VDDA_PLL 0.1 μf 10 μf 1 μf 0.01 μf 0.1 μf —1 NETWORK FOR EVERY 2 PINS SUPPLY_3.3 V 4.7 μH VDD33_FPGAPLL 0.1 μf 10 μf 1 μf 0.01 μf 0.1 μf —1 NETWORK FOR EVERY 2 PINS 1 μH VDDH 1K Precision REFI[1:4] 1K Precision 0.01 μf 0.1 μf —1 NETWORK FOR REFI_1 REFI_2 REFI_3 REFI_4 196 Lattice Semiconductor ORCA ORSPI4 Data Sheet Pin Descriptions This section describes the pins found on the Series 4 FPGAs. Any pin not described in this table is a user-programmable I/O. During conﬁguration, the user-programmable I/Os are 3-stated with an internal pull-up resistor. If any pin is not used (or not bonded to a package pin), it is also 3-stated with an internal pull-up resistor after conﬁguration. The pin descriptions in Table and throughout this data sheet show active-low signals with an overscore. The package pinout tables that follow, show this as a signal ending with _N. For example LDC and LDC_N are equivalent. Table 79. Pin Descriptions Symbol Dedicated Pins VDD33 VDD33_FPGAPLL VDD15 VDDIO VSS PTEMP RESET — 3.3V positive power supply. This power supply is used for 3.3 V conﬁguration RAMs. — 3.3V positive power supply. This power supply is used for 3.3 V internal PLLs. This power supply should be well isolated from all other power supplies on the board for proper operation. — 1.5 V positive power supply for internal logic. — Positive power supply used by I/O banks. — Ground. I I Temperature sensing diode pin. Dedicated input. During conﬁguration, RESET forces the restart of conﬁguration and a pull-up is enabled. After conﬁguration, RESET can be used as a general FPGA input or as a direct input, which causes all PLC latches/FFs to be asynchronously set/reset. In the master and asynchronous peripheral modes, CCLK is an output which strobes conﬁguration data in. In the slave or readback after conﬁguration, CCLK is input synchronous with the data on DIN or D[7:0]. CCLK is an output for daisy-chain operation when the lead device is in master, peripheral, or system bus modes. As an input, a low level on DONE delays FPGA start-up after conﬁguration.1 As an active-high, open-drain output, a high level on this signal indicates that conﬁguration is complete. DONE has an optional pull-up resistor. PRGRM is an active-low input that forces the restart of conﬁguration and resets the boundaryscan circuitry. This pin always has an active pull-up. I/O Description CCLK O I DONE I O PRGRM RD_CFG I I This pin must be held high during device initialization until the INIT pin goes high. This pin always has an active pull-up. During conﬁguration, RD_CFG is an active-low input that activates the TS_ALL function and 3-states all of the I/O. After conﬁguration, RD_CFG can be selected (via a bit stream option) to activate the TS_ALL function as described above, or, if readback is enabled via a bit stream option, a high-to-low transition on RD_CFG will initiate readback of the conﬁguration data, including PFU output states, starting with frame address 0. RD_DATA/TDO is a dual-function pin. If used for readback, RD_DATA provides conﬁguration data out. If used in boundary-scan, TDO is test data out. During JTAG, slave, master, and asynchronous peripheral conﬁguration assertion on this CFG_IRQ (active-low) indicates an error or errors for block RAM or FPSC initialization. MPI active-low interrupt request output, when the MPI is used. Reference resistor connection for controlled impedance termination of Series 4 FPGA LVDS inputs. During power up and initialization, M0—M3 are used to select the conﬁguration mode with their values latched on the rising edge of INIT. During conﬁguration, a pull-up is enabled. Semi-dedicated PLL clock pins. During conﬁguration they are 3-stated with a pull up. Pins dedicated for the primary clock. Input pins on the middle of each side with differential pairing. RD_DATA/TDO CFG_IRQ/MPI_IRQ O O LVDS_R Special-Purpose Pins M[3:0] - I I/O After conﬁguration, these pins are user-programmable I/O.1 PLL_CK[0:7][TC] P[TBLR]CLK[1:0][TC] I I I/O These pins are user-programmable I/O pins if not used by PLLs after conﬁguration. I/O After conﬁguration these pins are user programmable I/O, if not used for clock inputs. 197 Lattice Semiconductor Table 79. Pin Descriptions (Continued) Symbol TDI, TCK, TMS I/O I Description ORCA ORSPI4 Data Sheet If boundary-scan is used, these pins are test data in, test clock, and test mode select inputs. If boundary-scan is not selected, all boundary-scan functions are inhibited once conﬁguration is complete. Even if boundary-scan is not used, either TCK or TMS must be held at logic 1 during conﬁguration. Each pin has a pull-up enabled during conﬁguration. During conﬁguration in asynchronous peripheral mode, RDY/RCLK indicates another byte can be written to the FPGA. If a read operation is done when the device is selected, the same status is also available on D7 in asynchronous peripheral mode. During the master parallel conﬁguration mode, RCLK is a read output signal to an external memory. This output is not normally used. High During Conﬁguration is output high until conﬁguration is complete. It is used as a control output, indicating that conﬁguration is not complete. Low During Conﬁguration is output low until conﬁguration is complete. It is used as a control output, indicating that conﬁguration is not complete. I/O After conﬁguration, these pins are user-programmable I/O if boundary scan is not used.1 RDY/BUSY/RCLK O I/O After conﬁguration this pin is a user-programmable I/O pin.1 HDC O I/O After conﬁguration, this pin is a user-programmable I/O pin.1 LDC O I/O After conﬁguration, this pin is a user-programmable I/O pin.1 INIT I/O INIT is a bidirectional signal before and during conﬁguration. During conﬁguration, a pull-up is enabled, but an external pull-up resistor is recommended. As an active-low open-drain output, INIT is held low during power stabilization and internal clearing of memory. As an active-low input, INIT holds the FPGA in the wait-state before the start of conﬁguration. After conﬁguration, this pin is a user-programmable I/O pin.1 I CS0 and CS1 are used in the asynchronous peripheral, slave parallel, and microprocessor conﬁguration modes. The FPGA is selected when CS0 is low and CS1 is high. During conﬁguration, a pull-up is enabled. RD is used in the asynchronous peripheral conﬁguration mode. A low on RD changes D[7:3] into a status output. WR and RD should not be used simultaneously. If they are, the write strobe overrides. This pin is also used as the MPI data transfer strobe. As a status indication, a high indicates ready, and a low indicates busy. CS0, CS1 I/O After conﬁguration, if MPI is not used, these pins are user-programmable I/O pins.1 RD/MPI_STRB I WR/MPI_RW I WR is used in asynchronous peripheral mode. A low on WR transfers data on D[7:0] to the FPGA. In MPI mode, a high on MPI_RW allows a read from the data bus, while a low causes a write transfer to the FPGA. During MPI mode the PPC_A[14:31] are used as the address bus driven by the PowerPC bus master utilizing the least-signiﬁcant bits of the PowerPC 32-bit address. MPI_BURST is driven low to indicate a burst transfer is in progress in MPI mode. Driven high indicates that the current transfer is not a burst. MPI_BDIP is driven by the PowerPC processor in MPI mode. Assertion of this pin indicates that the second beat in front of the current one is requested by the master. Negated before the burst transfer ends to abort the burst data phase. MPI_TSZ[0:1] signals are driven by the bus master in MPI mode to indicate the data transfer size for the transaction. Set 01 for byte, 10 for half-word, and 00 for word. During master parallel mode A[21:0] address the conﬁguration EPROMs up to 4M bytes. In MPI mode this is driven low indicating the MPI received the data on the write cycle or returned data on a read cycle. I/O After conﬁguration, if the MPI is not used, WR/MPI_RW is a user-programmable I/O pin.1 PPC_A[14:31] MPI_BURST MPI_BDIP I I I MPI_TSZ[0:1] A[21:0] MPI_ACK I O O I/O If not used for MPI these pins are user-programmable I/O pins after conﬁguration.1 I/O If not used for MPI these pins are user-programmable I/O pins after conﬁguration.1 198 Lattice Semiconductor Table 79. Pin Descriptions (Continued) Symbol MPI_CLK I/O I Description ORCA ORSPI4 Data Sheet This is the PowerPC synchronous, positive-edge bus clock used for the MPI interface. It can be a source of the clock for the Embedded System Bus. If MPI is used this will be the AMBA bus clock. A low on the MPI transfer error acknowledge indicates that the MPI detects a bus error on the internal system bus for the current transaction. This pin requests the MPC860 to relinquish the bus and retry the cycle. I/O If not used for MPI these pins are user-programmable I/O pins after conﬁguration.1 MPI_TEA O I/O If not used for MPI these pins are user-programmable I/O pins after conﬁguration.1 MPI_RTRY D[0:31] O I/O If not used for MPI these pins are user-programmable I/O pins after conﬁguration.1 I/O Selectable data bus width from 8, 16, 32-bit in MPI mode. Driven by the bus master in a write transaction and driven by MPI in a read transaction. I D[7:0] receive conﬁguration data during master parallel, peripheral, and slave parallel conﬁguration modes when WR is low and each pin has a pull-up enabled. During serial conﬁguration modes, D0 is the DIN input. D[7:3] output internal status for asynchronous peripheral mode when RD is low. O DP[0:3] I/O After conﬁguration, if MPI is not used, the pins are user-programmable I/O pins.1 I/O Selectable parity bus width in MPI mode from 1, 2, 4-bit, DP[0] for D[0:7], DP[1] for D[8:15], DP[2] for D[16:23], and DP[3] for D[24:31]. After conﬁguration, if MPI is not used, the pins are user-programmable I/O pin.1 I During slave serial or master serial conﬁguration modes, DIN accepts serial conﬁguration data synchronous with CCLK. During parallel conﬁguration modes, DIN is the D0 input. During conﬁguration, a pull-up is enabled. During conﬁguration, DOUT is the serial data output that can drive the DIN of daisy-chained slave devices. Data out on DOUT changes on the rising edge of CCLK. DIN I/O After conﬁguration, this pin is a user-programmable I/O pin.1 DOUT O TESTCFG 1 I/O After conﬁguration, DOUT is a user-programmable I/O pin. I During conﬁguration this pin should be held high, to allow conﬁguration to occur. A pull up is enabled during conﬁguration. I/O After conﬁguration, TESTCFG is a user programmable I/O pin.1 1. The FPGA States of Operation section in the ORCA Series 4 FPGAs data sheet contains more information on how to control these signals during start-up. The timing of DONE release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other conﬁguration pins (and the activation of all user I/Os) is controlled by a second set of options. 199 Lattice Semiconductor ORSPI4 SPI4 External I/O Description ORCA ORSPI4 Data Sheet This section describes device I/O signals to/from the SPI4 interface. Table 80 and Table 81 lists the external signals that interface to the SPI4 block. Table 80. SPI4 External Transmit Path Interface Signals Pin Name (j = A or B) TSCLKj TSTATj[1:0] jTSCLKN jTSCLKP jTSTATN[1:0] jTSTATP[1:0] jTDATN[15:0] jTDATP[15:0] jTCTLN jTCTLP jTDCLKN jTDCLKP jTREFCLK Direction O = FPSC Output I = FPSC Input I I I I I I O O O O O O I Description LVTTL transmit status clock input. LVTTL transmit status input LVDS (negative) transmit status clock input LVDS (positive) transmit status clock input LVDS (negative) transmit status data input LVDS (positive) transmit status data input LVDS (negative) transmit SPI4 data output LVDS (positive) transmit SPI4 data output LVDS (negative) transmit SPI4 control signal output LVDS (positive) transmit SPI4 control signal output LVDS (negative) transmit SPI4 clock reference. (100 - > 450 MHz) LVDS (positive) transmit SPI4 clock reference. (100 - >450 MHz) SPI4 clock reference input. Table 81. SPI4 External Receive Path Interface Signals Pin Name (j = A or B) RSCLKj RSTATj[1:0] jRSCLKN jRSCLKP] jRSTATN[1:0] jRSTATP[1:0 jRDATN[15:0] jRDATP[15:0] jRCTLN jRCTLP jRDCLKN jRDCLKP Direction O = FPSC Output I = FPSC Input O O O O O O I I I I I I Description LVTTL receive status clock output. LVTTL receive status output LVDS (negative) receive status clock output LVDS (positive) receive status clock output LVDS (negative) receive status data output LVDS (positive) receive status data output LVDS (negative) receive SPI4 data input LVDS (positive) receive SPI4 data input LVDS (negative) receive SPI4 control signal input LVDS (positive) receive SPI4 control signal input LVDS (negative) receive SPI4 clock reference. (100 - >450 MHz) LVDS (positive) receive SPI4 clock reference. (100 - >450 MHz) 200 Lattice Semiconductor Table 82. SPI4 Miscellaneous System Signals Pin Name (j = A or B) REF10 REF14 RESHI RESLO ALVCTAP1 ALVCTAP2 ALVCTAP3 ALVCTAP4 ALVCTAP5 BLVCTAP1 BLVCTAP2 BLVCTAP3 BLVCTAP4 BLVCTAP5 SPARE_1 SPARE_2 Direction O = FPSC Output I = FPSC Input I I I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ORCA ORSPI4 Data Sheet Description LVDS Reference voltage: 1.0 V +/- 3% LVDS Reference voltage: 1.4 V +/- 3% LVDS resistor high pin (100 Ω. in series with RESLO) LVDS resistor low pin (100 Ω. in series with RESHI) LVDS input center tap (use 0.01 μF to GND) LVDS input center tap (use 0.01 μF to GND) LVDS input center tap (use 0.01 μF to GND) LVDS input center tap (use 0.01 μF to GND) LVDS input center tap (use 0.01 μF to GND) LVDS input center tap (use 0.01 μF to GND) LVDS input center tap (use 0.01 μF to GND) LVDS input center tap (use 0.01 μF to GND) LVDS input center tap (use 0.01 μF to GND) LVDS input center tap (use 0.01 μF to GND) Reserved Reserved 201 Lattice Semiconductor ORSPI4 SERDES External I/O Description ORCA ORSPI4 Data Sheet This section describes device I/O signals to/from the SERDES. Table 83 lists the external signals that interface to the SERDES block. Table 83. SERDES External Interface Signals Direction O = FPSC Output I = FPSC Input Pin Name SERDES Interface Pins HDINP_A HDINN_A HDINP_B HDINN_B HDINP_C HDINN_C HDINP_D HDINN_D HDOUTP_A HDOUTN_A HDOUTP_B HDOUTN_B HDOUTP_C HDOUTN_C HDOUTP_D HDOUTN_D REFCLKP REFCLKN REXT REXTN Description I I I I O O O O I --- Serial Input for channel A Serial Input for channel B Serial Input for channel C Serial Input for channel D Serial Output for channel A Serial Output for channel B Serial Output for channel C Serial Output for channel D Reference clock to SERDES quad Reference resistor Reference resistor. A 3.32 KW ± 1% resistor must be connected across REXT and REXTN. This current should handle a total of 300μA. Global Reset Integrated 50K pull-down allows chip to stay in reset state when external driver loses power LVTTL test mode pins with integrated 50K pull-ups that default chip into operational mode when un-driven. Power-down active low. Puts Core into low-power (non-functional) state. Active low control input causes all output pins to be disabled. (See Note 1) Chip test pin. Integrated 50K pull-up Misc System Signals RESETN I TESTMD[1:0]N PDN TRISTN TESTCLK I I I I 1. Should be externally connected on board to 3.3 V pullup resistor. 202 Lattice Semiconductor ORSPI4 Memory Controller External I/O Description ORCA ORSPI4 Data Sheet This section describes device I/O signals to/from the Memory Controller. Table 84 lists the external signals that interface to the Memory Controller block. Table 84. Memory Controller External Interface Signals QDRII SDRAM Pin Name K,K# D(35:0) SA(17:0) W# R# CQ,CQ# Q(35:0) Direction O = FPSC Output I = FPSC Input O O O O O I I I I I Pin Name PMIK, PMIKN PMID(35:0) PMIA(17:0) PMIWN PMIRN PMIC, PMICN PMIQ(35:0) REFCLK Source Inputs MCREFCLK ATREFCLK BTREFCLK Other Signals EXT_1K Description Clock for write data D, address SA, and enables W# and R# Write data bus Address bus Write enable (active-LO) Read enable (active-LO) Clock for read data Q Read data bus Dedicated Memory Controller reference clock (HSTL) SPIA reference clock (LVTTL). Note that this signal also is fed to the SPIA block. SPIB reference clock, (LVTTL). Note that this signal also is fed to the SPIB block. Reference resistor. Connect to a 1.5 K Ω ± 1% precision resistor to ground. This current should handle a total of 700 μA. Interface to QDRII SDRAM - - 203 Lattice Semiconductor Package I/O Table 85. I/O Summary ORCA ORSPI4 Data Sheet Package I/O Type User programmable I/O Available programmable differential pair pins FPGA conﬁguration pins FPGA dedicated function pins Core function pins VDD15 VDD33 VDD33_FPGAPLL VDDIO VSS VDDGB VDDIB VDDOB VDD_ANA VDDA_SPI[A:D] VDDA_PLL VDDH HSTL VREF No connect Total package pins FTE1036 498 498 7 2 322 42 14 8 30 79 1 4 8 4 4 1 8 4 0 1036 F1156/FN1156 356 356 7 2 301 80 30 8 50 187 0 0 0 0 4 1 30 4 96 1156 204 Lattice Semiconductor Pin Tables ORCA ORSPI4 Data Sheet The ORSPI4 FPSC is available in two package types; a 1156-pin fpBGA package, and a 1036-pin ftSBGA package. Both packages are 1.0 mm pitch packages. The 1036-pin package offers two SPI4 interfaces, or one SPI4 interface and a quad 0.6-3.7 Gbps SERDES, a highspeed QDR-II SRAM Memory Controller, and 498 user I/Os on the FPGA array. The 1156-pin package offers two SPI4 interfaces (no SERDES available on this package offering), a high-speed QDR-II SRAM Memory Controller, and 356 user I/Os on the FPGA array. Table 86. 1156 fpBGA Pin Table F1156 VDDIO Ball Bank F4 G4 H4 J4 H5 H6 J6 J5 H3 J3 K4 K5 G2 G1 L5 L4 H2 H1 J2 J1 K2 K1 K3 L3 L2 L1 M4 M5 N5 N4 M3 N3 P4 VREF Group O I I I IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO I/O Pin Description PRD_DATA PRESET_N PRD_CFG_N PPRGRM_N PL2D PL2C PL3D PL3C PL4D PL4C PL5D PL5C PL6D PL6C PL7D PL7C PL8D PL8C PL9D PL9C PL10D PL10C PL11D PL11C PL12D PL12C PL13D PL13C PL14D PL14C PL15D PL15C PL16D Additional Function RD_DATA/TDO RESET_N RD_CFG_N PRGRM_N PLL_CK0C/HPPLL PLL_CK0T/HPPLL VREF_0_07 D5 D6 VREF_0_08 HDC LDC_N TESTCFG D7 VREF_0_09 A17/PPC_A31 CS0_N CS1 INIT_N DOUT VREF_0_10 A16/PPC_A30 A15/PPC_A29 A14/PPC_A28 VREF_7_01 L1C L1T L2C L2T L3C L3T L4C L4T L5C L5T L6C L6T L7C L7T L8C L8T L9C L9T L10C L10T L11C L11T L12C L12T L13C L13T L14C L14T L15C F1156 Pair 0 (TL) 7 0 (TL) 7 0 (TL) 7 0 (TL) 7 0 (TL) 7 0 (TL) 7 0 (TL) 8 0 (TL) 8 0 (TL) 8 0 (TL) 8 0 (TL) 8 0 (TL) 8 0 (TL) 9 0 (TL) 9 0 (TL) 9 0 (TL) 9 0 (TL) 9 0 (TL) 9 0 (TL) 10 0 (TL) 10 0 (TL) 10 0 (TL) 10 0 (TL) 10 0 (TL) 10 7 (CL) 1 7 (CL) 1 7 (CL) 1 7 (CL) 1 7 (CL) 1 205 Lattice Semiconductor Table 86. 1156 fpBGA Pin Table (Continued) F1156 VDDIO Ball Bank P3 M2 M1 N2 N1 P5 R5 R4 R3 P2 P1 T3 T4 R1 R2 R6 T6 T5 U5 U3 U4 T1 T2 V3 V4 U1 U2 V5 W5 W3 W4 V1 V2 W1 W2 Y1 Y2 AA1 AA2 Y3 W6 AA3 7 (CL) 1 7 (CL) 2 7 (CL) 2 7 (CL) 2 7 (CL) 2 7 (CL) 2 7 (CL) 2 7 (CL) 3 7 (CL) 3 7 (CL) 3 7 (CL) 3 7 (CL) 3 7 (CL) 3 7 (CL) 4 VREF Group IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO I/O Pin Description PL16C PL17D PL17C PL18D PL18C PL19D PL19C PL20D PL20C PL21D PL21C PL22D PL22C PL23D PL23C PL24D PL24B PL24C PL24A PL25D PL25C PL26D PL26C PL27D PL27C PL28D PL28C PL29D PL29C PL30D PL30C PL31D PL31C PL32D PL32C PL33D PL33C PL34D PL34C PL35D PL35B PL35C D4 - ORCA ORSPI4 Data Sheet Additional Function F1156 Pair L15T L16C L16T L17T L18C L18T L19C L19T L20C L20T L21C L21T L22C L22T L23C L178C L23T L178T L24C L24T L25C L25T L26C L26T L27C L27T L28C L28T L29C L29T L30C L30T L31C L31T L32C L32T L33C L33T L34C L35C L34T RDY/BUSY_N/RCLK L17C VREF_7_02 A13/PPC_A27 A12/PPC_A26 A11/PPC_A25 VREF_7_03 RD_N/MPI_STRB_ N VREF_7_04 PLCK0C PLCK0T A10/PPC_A24 A9/PPC_A23 A8/PPC_A22 VREF_7_05 PLCK1C PLCK1T VREF_7_06 A7/PPC_A21 A6/PPC_A20 A5/PPC_A19 WR_N/MPI_RW VREF_7_07 A4/PPC_A18 VREF_7_08 A3/PPC_A17 A2/PPC_A16 7 (CL) 4 7 (CL) 4 7 (CL) 4 7 (CL) 4 7 (CL) 4 7 (CL) 5 7 (CL) 5 7 (CL) 5 7 (CL) 5 7 (CL) 5 7 (CL) 5 7 (CL) 6 7 (CL) 6 7 (CL) 6 7 (CL) 6 7 (CL) 6 7 (CL) 6 7 (CL) 7 7 (CL) 7 7 (CL) 7 7 (CL) 7 7 (CL) 7 7 (CL) 7 7 (CL) 8 7 (CL) 8 7 (CL) 8 7 (CL) 8 7 (CL) 8 206 Lattice Semiconductor Table 86. 1156 fpBGA Pin Table (Continued) F1156 VDDIO Ball Bank Y6 AB1 Y5 AB2 Y4 AC1 AA5 AC2 AA4 AD1 AA6 AD2 AB6 AB3 AB4 AC3 AB5 AE1 AC4 AE2 AC5 AF1 AD5 AF2 AD4 AD3 AE4 AE3 AE5 AG1 AF4 AG2 AF5 AH1 AC6 AH2 AD6 AF3 AE6 AG3 AF6 AJ1 AJ2 7 (CL) 8 7 (CL) 8 7 (CL) 8 7 (CL) 8 7 (CL) 8 7 (CL) 8 7 (CL) 8 7 (CL) 8 7 (CL) 8 6 (BL) 1 6 (BL) 1 6 (BL) 1 6 (BL) 1 6 (BL) 1 6 (BL) 1 6 (BL) 1 6 (BL) 1 6 (BL) 2 6 (BL) 2 6 (BL) 2 6 (BL) 2 6 (BL) 2 6 (BL) 2 6 (BL) 2 6 (BL) 2 6 (BL) 3 6 (BL) 3 6 (BL) 3 6 (BL) 3 6 (BL) 3 6 (BL) 3 6 (BL) 3 6 (BL) 3 6 (BL) 3 6 (BL) 4 6 (BL) 3 6 (BL) 4 6 (BL) 4 6 (BL) 4 6 (BL) 4 6 (BL) 4 6 (BL) 4 6 (BL) 4 VREF Group IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO I/O Pin Description PL35A PL36D PL36B PL36C PL36A PL37D PL37B PL37C PL37A PL38D PL38B PL38C PL38A PL39D PL39B PL39C PL39A PL40D PL40B PL40C PL40A PL41D PL41B PL41C PL41A PL42D PL42B PL42C PL42A PL43D PL43B PL43C PL43A PL44D PL44B PL44C PL44A PL45D PL45B PL45C PL45A PL46D PL46C - ORCA ORSPI4 Data Sheet Additional Function A1/PPC_A15 A0/PPC_A14 DP0 DP1 D8 VREF_6_01 D9 D10 VREF_6_02 D11 D12 VREF_6_03 D13 VREF_6_04 - F1156 Pair L35T L36C L37C L36T L37T L38C L39C L38T L39T L40C L41C L40T L41T L42C L43C L42T L43T L44C L45C L44T L45T L46C L47C L46T L47T L48C L49C L48T L49T L50C L51C L50T L51T L52C L53C L52T L53T L54C L55C L54T L55T L56C L56T 207 Lattice Semiconductor Table 86. 1156 fpBGA Pin Table (Continued) F1156 VDDIO Ball Bank AH3 AJ3 AG4 AH4 AH6 AN5 AH7 AP5 AN6 AP6 AK6 AK7 AJ6 AL6 AJ7 AL7 AG7 AM6 AG8 AM7 AG9 AN7 AG10 AP7 AH8 AN8 AJ8 AP8 AH9 AK8 AJ9 AK9 AJ10 AL8 AH10 AL9 AM8 AM9 AJ11 AN9 AH11 AP9 AG11 6 (BL) 4 6 (BL) 4 VREF Group IO IO I IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO I/O Pin Description PL47D PL47C PTEMP LVDS_R PB2A PB2C PB2B PB2D PB3C PB3D PB4C PB4D PB5A PB5C PB5B PB5D PB6A PB6C PB6B PB6D PB7A PB7C PB7B PB7D PB8A PB8C PB8B PB8D PB9A PB9C PB9B PB9D PB10A PB10C PB10B PB10D PB11C PB11D PB12A PB12C PB12B PB12D PB13A ORCA ORSPI4 Data Sheet Additional Function PLL_CK7C/HPPLL PLL_CK7T/HPPLL PTEMP LVDS_R DP2 PLL_CK6T/PPLL PLL_CK6C/PPLL VREF_6_05 DP3 VREF_6_06 D14 D15 D16 D17 D18 VREF_6_07 D19 D20 D21 VREF_6_08 D22 - F1156 Pair L57C L57T L58T L59T L58C L59C L60T L60C L61T L61C L62T L63T L62C L63C L64T L65T L64C L65C L66T L67T L66C L67C L68T L69T L68C L69C L70T L71T L70C L71C L72T L73T L72C L73C L74T L74C L75T L76T L75C L76C L77T 6 (BL) 5 6 (BL) 5 6 (BL) 5 6 (BL) 5 6 (BL) 5 6 (BL) 5 6 (BL) 5 6 (BL) 5 6 (BL) 6 6 (BL) 6 6 (BL) 6 6 (BL) 6 6 (BL) 6 6 (BL) 6 6 (BL) 6 6 (BL) 6 6 (BL) 6 6 (BL) 6 6 (BL) 6 6 (BL) 6 6 (BL) 7 6 (BL) 7 6 (BL) 7 6 (BL) 7 6 (BL) 7 6 (BL) 7 6 (BL) 7 6 (BL) 7 6 (BL) 7 6 (BL) 7 6 (BL) 7 6 (BL) 7 6 (BL) 8 6 (BL) 8 6 (BL) 8 6 (BL) 8 6 (BL) 8 6 (BL) 8 6 (BL) 9 208 Lattice Semiconductor Table 86. 1156 fpBGA Pin Table (Continued) F1156 VDDIO Ball Bank AK10 AG12 AK11 AJ12 AN10 AH12 AP10 AJ13 AL10 AH13 AL11 AJ14 AM10 AH14 AM11 AJ16 AN11 AH16 AP11 AJ17 AK12 AH17 AK13 AG13 AN12 AG14 AP12 AH15 AL12 AJ15 AL13 AJ18 AM12 AH18 AM13 AJ19 AN13 AH19 AP13 AP14 AN14 AG15 AK14 6 (BL) 9 6 (BL) 9 6 (BL) 9 6 (BL) 9 6 (BL) 9 6 (BL) 9 6 (BL) 9 6 (BL) 9 6 (BL) 9 6 (BL) 9 6 (BL) 9 6 (BL) 10 6 (BL) 10 6 (BL) 10 6 (BL) 10 6 (BL) 10 6 (BL) 10 6 (BL) 10 6 (BL) 10 6 (BL) 10 6 (BL) 10 6 (BL) 10 6 (BL) 10 6 (BL) 11 6 (BL) 11 6 (BL) 11 6 (BL) 11 6 (BL) 11 6 (BL) 11 6 (BL) 11 6 (BL) 11 5 (BC) 1 5 (BC) 1 5 (BC) 1 5 (BC) 1 5 (BC) 1 5 (BC) 1 5 (BC) 1 5 (BC) 1 5 (BC) 2 5 (BC) 2 5 (BC) 2 5 (BC) 2 VREF Group IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO I/O Pin Description PB13C PB13B PB13D PB14A PB14C PB14B PB14D PB15A PB15C PB15B PB15D PB16A PB16C PB16B PB16D PB17A PB17C PB17B PB17D PB18A PB18C PB18B PB18D PB19A PB19C PB19B PB19D PB20A PB20C PB20B PB20D PB21A PB21C PB21B PB21D PB22A PB22C PB22B PB22D PB23C PB23D PB24A PB24C D23 D24 - ORCA ORSPI4 Data Sheet Additional Function F1156 Pair L78T L77C L78C L79T L80T L79C L80C L81T L82T L81C L82C L83T L84T L83C L84C L85T L86T L85C L86C L87T L88T L87C L88C L89T L90T L89C L90C L91T L92T L91C L92C L93T L94T L93C L94C L95T L96T L95C L96C L97T L97C L99T L98T VREF_6_09 D25 D26 D27 VREF_6_10 D28 D29 D30 VREF_6_11 D31 VREF_5_01 PBCK0T PBCK0C VREF_5_02 209 Lattice Semiconductor Table 86. 1156 fpBGA Pin Table (Continued) F1156 VDDIO Ball Bank AG16 AK15 AL14 AL15 AM14 AM15 AG18 AN15 AG17 AP15 AL16 AM16 AN16 AP16 AK16 AK17 AN17 AP17 AL17 AM17 AK18 AL18 AN18 AP18 AN19 AP19 AM18 AM19 AN20 AP20 AL19 AL20 AK19 AK20 AM20 AM21 AN21 AP21 AN22 AP22 AL21 AL22 AK21 5 (BC) 2 5 (BC) 2 5 (BC) 2 5 (BC) 2 5 (BC) 3 5 (BC) 3 5 (BC) 3 5 (BC) 3 5 (BC) 3 5 (BC) 3 5 (BC) 3 5 (BC) 3 5 (BC) 4 5 (BC) 4 5 (BC) 4 5 (BC) 4 5 (BC) 4 5 (BC) 4 5 (BC) 5 5 (BC) 5 5 (BC) 5 5 (BC) 5 5 (BC) 5 5 (BC) 5 5 (BC) 6 5 (BC) 6 5 (BC) 6 5 (BC) 6 5 (BC) 7 5 (BC) 7 5 (BC) 7 5 (BC) 7 5 (BC) 7 5 (BC) 7 5 (BC) 8 5 (BC) 8 5 (BC) 8 5 (BC) 8 5 (BC) 8 5 (BC) 8 5 (BC) 9 5 (BC) 9 5 (BC) 9 VREF Group IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO I/O Pin Description PB24B PB24D PB25C PB25D PB26C PB26D PB27A PB27C PB27B PB27D PB28C PB28D PB29C PB29D PB30C PB30D PB31C PB31D PB32C PB32D PB33C PB33D PB34C PB34D PB35C PB35D PB36C PB36D PB37C PB37D PB38C PB38D PB39C PB39D PB40C PB40D PB41C PB41D PB42C PB42D PB43C PB43D PB44C - ORCA ORSPI4 Data Sheet Additional Function F1156 Pair L99C L98C L100T L100C L101T L101C L102T L103T L102C L103C L104T L104C L105T L105C L106T L106C L107T L107C L108T L108C L109T L109C L110T L110C L111T L111C L112T L112C L113T L113C L114T L114C L115T L115C L116T L116C L117T L117C L118T L118C L119T L119C L120T VREF_5_03 PBCK1T PBCK1C VREF_5_04 VREF_5_05 VREF_5_06 VREF_5_07 VREF_5_08 - 210 Lattice Semiconductor Table 86. 1156 fpBGA Pin Table (Continued) F1156 VDDIO Ball Bank AK22 AM22 AM23 AN23 AP23 AL23 AK23 AP24 AN24 AM24 AL24 AK24 AP25 AN25 AG22 AM25 AH23 AL25 AH24 AK30 AL31 AJ30 AK31 AM31 AE27 AL32 AF29 AH30 AG28 AM32 AF28 AM33 AE28 AK32 AL33 AJ32 AL34 AJ31 AE26 AH31 AD26 AK33 AJ33 5 (BC) 9 5 (BC) 9 5 (BC) 9 5 (BC) 10 5 (BC) 10 VREF Group IO IO IO IO IO I I I I I I I I I I I O O O I I I I I I/O I I I/O I I I I I O O O O O O O O O O I/O Pin Description PB44D PB45C PB45D PB46C PB46D RESETN TRISTN TESTMD1N TESTMD0N PDN ATREFCLK TESTCLK BTREFCLK TSTAT1B TSTAT0B TSCLKB RSTAT1B RSTAT0B RSCLKB ATSTAT1N ATSTAT0N ATSTAT1P ATSTAT0P ATSCLKN ALVCTAP5 ATSCLKP BTSCLKN BLVCTAP5 BTSCLKP BTSTAT1N BTSTAT0N BTSTAT1P BTSTAT0P BRSTAT1N BRSTAT0N BRSTAT1P BRSTAT0P BRSCLKN ARSCLKN BRSCLKP ARSCLKP ARSTAT1N ARSTAT0N - ORCA ORSPI4 Data Sheet Additional Function VREF_5_09 F1156 Pair L120C L121T L121C L122T L122C R1C R2C R1T R2T R3C R3T R4C R4T R5C R6C R5T R6T R7C R8C R7T R8T R9C R10C R9T R10T R11C R12C VREF_5_10 - 211 Lattice Semiconductor Table 86. 1156 fpBGA Pin Table (Continued) F1156 VDDIO Ball Bank AK34 AJ34 AF31 AD28 AG31 AE29 AH32 AG29 AG32 AG30 AH33 AD27 AH34 AC27 AG33 AE30 AG34 AF30 AF32 AD30 AE32 AD29 AF33 AB26 AF34 AC26 AE31 AD31 AC28 AE33 AC29 AE34 AD32 AB28 AC32 AB29 AD33 AC30 AD34 AB30 AC31 AB27 AB31 VREF Group O O I I I I O O O O O O O O O O O O O O O O O O O O VDDA_SPIA VSS O O O O O O O O O O O O O O O I/O Pin Description ARSTAT1P ARSTAT0P RESLO RESHI REF14 REF10 BTDAT15N BTDAT14N BTDAT15P BTDAT14P BTDAT13N BTDAT12N BTDAT13P BTDAT12P BTDAT11N BTDAT10N BTDAT11P BTDAT10P BTDAT9N BTDAT8N BTDAT9P BTDAT8P BTCTLN BTDCLKN BTCTLP BTDCLKP VDDA_SPIA VSS BTDAT7N BTDAT6N BTDAT7P BTDAT6P BTDAT5N BTDAT4N BTDAT5P BTDAT4P BTDAT3N BTDAT2N BTDAT3P BTDAT2P BTDAT1N BTDAT0N BTDAT1P - ORCA ORSPI4 Data Sheet Additional Function F1156 Pair R11T R12T R13C R14C R13T R14T R15C R16C R15T R16T R17C R18C R17T R18T R19C R20C R19T R20T R21C R22C R21T R22T R23C R24C R23T R24T R25C R26C R25T R26T R27C R28C R27T R28T R29C R30C R29T 212 Lattice Semiconductor Table 86. 1156 fpBGA Pin Table (Continued) F1156 VDDIO Ball Bank AA27 AC33 AA29 AC34 AA30 AA31 AA26 AB33 Y26 AB34 AA28 AB32 Y28 AA32 Y30 AA33 Y29 Y31 Y27 Y32 W27 AA34 W28 Y34 W30 Y33 W29 W33 W26 W31 V26 W32 V28 W34 V30 V34 V29 V33 V27 V32 U27 V31 U31 VREF Group O I I I I I/O I I I I I I I I I I/O I I I I I I I/O I I I I I I I I I I/O I I I I I I I I VSS VDDA_SPIB I/O Pin Description BTDAT0P BRDCLKN BRDAT15N BRDCLKP BRDAT15P BLVCTAP1 BRDAT14N BRDAT13N BRDAT14P BRDAT13P BRDAT12N BRDAT11N BRDAT12P BRDAT11P BRDAT10N BLVCTAP2 BRDAT10P BRDAT9N BRDAT8N BRDAT9P BRDAT8P BRCTLN BLVCTAP3 BRCTLP BRDAT7N BRDAT6N BRDAT7P BRDAT6P BRDAT5N BRDAT4N BRDAT5P BRDAT4P BLVCTAP4 BRDAT3N BRDAT2N BRDAT3P BRDAT2P BRDAT1N BRDAT0N BRDAT1P BRDAT0P VSS VDDA_SPIB - ORCA ORSPI4 Data Sheet Additional Function F1156 Pair R31T R32C R33C R32T R33T R34C R35C R34T R35T R36C R37C R36T R37T R38C R38T R39C R40C R39T R40T R41C R41T R42C R43C R42T R43T R44C R45C R44T R45T R46C R47C R46T R47T R48C R49C R48T R49T - 213 Lattice Semiconductor Table 86. 1156 fpBGA Pin Table (Continued) F1156 VDDIO Ball Bank U28 U32 U29 U33 U34 U30 T34 T29 T33 T32 U26 T31 T26 R34 T28 R33 T30 R32 T27 R31 R27 P34 R28 P33 R29 N34 R30 N33 P30 P32 R26 P31 P26 M34 P28 M33 P29 N31 M32 N32 L34 P27 L33 VREF Group O VSS O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O VSS VDDA_SPIC VSS I I I I/O Pin Description ATDAT15N VSS ATDAT15P ATDAT14N ATDAT14P ATDAT13N ATDAT12N ATDAT13P ATDAT12P ATDAT11N ATDAT10N ATDAT11P ATDAT10P ATDAT9N ATDAT8N ATDAT9P ATDAT8P ATCTLN ATDCLKN ATCTLP ATDCLKP ATDAT7N ATDAT6N ATDAT7P ATDAT6P ATDAT5N ATDAT4N ATDAT5P ATDAT4P ATDAT3N ATDAT2N ATDAT3P ATDAT2P ATDAT1N ATDAT0N ATDAT1P ATDAT0P VSS VDDA_SPIC VSS ARDCLKN ARDAT15N ARDCLKP - ORCA ORSPI4 Data Sheet Additional Function - F1156 Pair R50C R50T R51C R51T R52C R53C R52T R53T R54C R55C R54T R55T R56C R57C R56T R57T R58C R59C R58T R59T R60C R61C R60T R61T R62C R63C R62T R63T R64C R65C R64T R65T R66C R67C R66T R67T R68C R69C R68T 214 Lattice Semiconductor Table 86. 1156 fpBGA Pin Table (Continued) F1156 VDDIO Ball Bank N27 L32 N30 K34 M30 K33 N28 J32 N29 K32 L30 M31 N26 L31 M26 J34 M28 J33 M29 K31 L27 H34 M27 H33 L29 J31 K30 H31 L28 G34 J30 G33 H30 F34 L26 F33 K26 H32 G32 G30 G31 H29 F32 VREF Group I I/O I I I I I I I I I/O I I I I I I I I I/O I I I I I I I I I/O I I I I I I I I VDDA_SPID VSS I I I O I/O Pin Description ARDAT15P ALVCTAP1 ARDAT14N ARDAT13N ARDAT14P ARDAT13P ARDAT12N ARDAT11N ARDAT12P ARDAT11P ALVCTAP2 ARDAT10N ARDAT9N ARDAT10P ARDAT9P ARDAT8N ARCTLN ARDAT8P ARCTLP ALVCTAP3 ARDAT7N ARDAT6N ARDAT7P ARDAT6P ARDAT5N ARDAT4N ARDAT5P ARDAT4P ALVCTAP4 ARDAT3N ARDAT2N ARDAT3P ARDAT2P ARDAT1N ARDAT0N ARDAT1P ARDAT0P VDDA_SPID VSS TSTAT1A TSTAT0A TSCLKA RSTAT1A - ORCA ORSPI4 Data Sheet Additional Function - F1156 Pair R69T R70C R71C R70T R71T R72C R73C R72T R73T R74C R75C R74T R75T R76C R77C R76T R77T R78C R79C R78T R79T R80C R81C R80T R81T R82C R83C R82T R83T R84C R85C R84T R85T - 215 Lattice Semiconductor Table 86. 1156 fpBGA Pin Table (Continued) F1156 VDDIO Ball Bank K29 E34 E33 D34 K28 D33 G29 C33 K27 E32 D32 C32 G28 B32 J29 C31 J28 D31 J27 F30 H27 E31 H28 F31 F29 E30 F28 D30 E27 C30 F27 B31 G27 A31 E26 B30 F26 A30 G26 E29 H26 E28 E25 VREF Group O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VREF I/O I/O I/O I/O I/O I/O I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin Description RSTAT0A RSCLKA PMIA17 PMIA16 PMIA15 PMIA14 PMIA13 PMIA12 PMIA11 PMIA10 PMIA9 PMIA8 PMIWN PMIRN PMIA7 REFI_1 PMIA6 PMIA5 PMIA4 PMIA3 PMIA2 PMIA1 PMIA0 EXT_1K PMID35 PMID34 PMID33 PMID32 PMID31 PMID30 PMID29 PMID28 PMID27 PMID26 PMID25 PMID24 PMID23 PMID22 PMID21 PMID20 PMID19 PMID18 PMID17 - ORCA ORSPI4 Data Sheet Additional Function - F1156 Pair 216 Lattice Semiconductor Table 86. 1156 fpBGA Pin Table (Continued) F1156 VDDIO Ball Bank D29 C29 F25 B29 G25 A29 H25 D28 E24 C28 F24 B28 G24 A28 H24 D27 E23 C27 F23 B27 A27 G23 D26 H23 C26 E22 B26 F22 A26 E21 D25 G22 C25 F21 B25 G20 A25 F20 D24 E20 C24 G21 B24 VREF Group I/O VREF I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VREF I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin Description PMID16 REFI_2 PMIK PMIKN PMID15 PMID14 PMID13 PMID12 PMID11 PMID10 PMID9 PMID8 PMID7 PMID6 PMID5 PMID4 PMID3 PMID2 PMID1 PMID0 REFI_3 PMIC PMICN PMIQ35 PMIQ34 PMIQ33 PMIQ32 PMIQ31 PMIQ30 PMIQ29 PMIQ28 PMIQ27 PMIQ26 PMIQ25 PMIQ24 PMIQ23 PMIQ22 PMIQ21 PMIQ20 PMIQ19 PMIQ18 PMIQ17 PMIQ16 - ORCA ORSPI4 Data Sheet Additional Function - F1156 Pair 217 Lattice Semiconductor Table 86. 1156 fpBGA Pin Table (Continued) F1156 VDDIO Ball Bank H22 A24 E19 D23 F19 C23 G19 B23 H21 A23 H20 D22 H19 C22 H18 B22 E18 A22 F18 C21 G18 B21 A21 A20 A19 C20 B20 B19 A18 C19 D19 B18 A17 C18 D18 B17 C17 A16 B16 A15 B15 A14 B14 VREF Group I/O I/O I/O VREF I/O I/O I/O VDDA_PLL I/O VSS I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO I/O Pin Description MCREFCLK SPARE_2 PMIQ15 REFI_4 PMIQ14 PMIQ13 PMIQ12 VDDA_PLL PMIQ11 VSS PMIQ10 PMIQ9 PMIQ8 PMIQ7 PMIQ6 PMIQ5 PMIQ4 PMIQ3 PMIQ2 PMIQ1 PMIQ0 PT46D PT46C PT45D PT45C PT44D PT44C PT43D PT43C PT42D PT42C PT41D PT41C PT40D PT40C PT39D PT39C PT38D PT38C PT37D PT37C PT36D PT36C - ORCA ORSPI4 Data Sheet Additional Function - F1156 Pair 1 (TC) 7 1 (TC) 7 1 (TC) 7 1 (TC) 7 1 (TC) 8 1 (TC) 8 1 (TC) 8 1 (TC) 8 1 (TC) 8 1 (TC) 8 1 (TC) 9 1 (TC) 9 1 (TC) 9 1 (TC) 9 1 (TC) 9 1 (TC) 9 1 (TC) 10 1 (TC) 10 1 (TC) 10 1 (TC) 10 1 (TC) 10 1 (TC) 10 L123C L123T L124C L124T L125C L125T L126C L126T L127C L127T L128C L128T L129C L129T L130C L130T L131C L131T L132C L132T L133C L133T VREF_1_07 VREF_1_08 VREF_1_09 VREF_1_10 - 218 Lattice Semiconductor Table 86. 1156 fpBGA Pin Table (Continued) F1156 VDDIO Ball Bank E17 H17 E16 G17 C16 G15 C15 F15 D17 F14 D16 G14 F17 H16 F16 G16 A13 F13 B13 F12 C14 G13 C13 H13 D15 G12 D14 H12 A12 H15 B12 H14 D13 D12 E15 E14 A11 J14 A10 J13 C12 C11 B11 1 (TC) 1 1 (TC) 1 1 (TC) 1 1 (TC) 1 1 (TC) 1 1 (TC) 1 1 (TC) 1 1 (TC) 1 1 (TC) 1 1 (TC) 1 1 (TC) 1 1 (TC) 1 1 (TC) 2 1 (TC) 2 1 (TC) 2 1 (TC) 2 1 (TC) 2 1 (TC) 2 1 (TC) 2 1 (TC) 2 1 (TC) 2 1 (TC) 2 1 (TC) 2 1 (TC) 2 1 (TC) 3 1 (TC) 3 1 (TC) 3 1 (TC) 3 1 (TC) 3 1 (TC) 3 1 (TC) 3 1 (TC) 3 1 (TC) 3 1 (TC) 3 1 (TC) 4 1 (TC) 4 1 (TC) 4 1 (TC) 4 1 (TC) 4 1 (TC) 4 1 (TC) 4 1 (TC) 4 1 (TC) 5 VREF Group IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO I/O Pin Description PT35D PT35B PT35C PT35A PT34D PT34B PT34C PT34A PT33D PT33B PT33C PT33A PT32D PT32B PT32C PT32A PT31D PT31B PT31C PT31A PT30D PT30B PT30C PT30A PT29D PT29B PT29C PT29A PT28D PT28B PT28C PT28A PT27D PT27C PT26D PT26C PT25D PT25B PT25C PT25A PT24D PT24C PT23D - ORCA ORSPI4 Data Sheet Additional Function F1156 Pair L134C L135C L134T L135T L136C L137C L136T L137T L138C L139C L138T L139T L140C L141C L140T L141T L142C L143C L142T L143T L144C L145C L144T L145T L146C L147C L146T L147T L148C L149C L148T L149T L150C L150T L151C L151T L152C L153C L152T L153T L154C L154T L155C VREF_1_01 VREF_1_02 VREF_1_03 VREF_1_04 PTCK1C 219 Lattice Semiconductor Table 86. 1156 fpBGA Pin Table (Continued) F1156 VDDIO Ball Bank B10 E13 E12 A9 B9 C10 C9 D11 D10 A8 B8 H11 G11 H10 G10 A7 B7 C8 C7 E11 E10 F11 F10 D9 D8 H9 G9 H7 G7 A6 B6 E9 E8 F9 F8 C6 C5 D7 D6 E7 G8 E6 H8 1 (TC) 5 1 (TC) 5 1 (TC) 5 1 (TC) 5 1 (TC) 5 1 (TC) 6 1 (TC) 6 1 (TC) 6 1 (TC) 6 0 (TL) 1 0 (TL) 1 0 (TL) 1 0 (TL) 1 0 (TL) 1 0 (TL) 1 0 (TL) 2 0 (TL) 2 0 (TL) 2 0 (TL) 2 0 (TL) 2 0 (TL) 2 0 (TL) 3 0 (TL) 3 0 (TL) 3 0 (TL) 3 0 (TL) 3 0 (TL) 3 0 (TL) 4 0 (TL) 4 0 (TL) 4 0 (TL) 4 0 (TL) 4 0 (TL) 4 0 (TL) 5 0 (TL) 5 0 (TL) 5 0 (TL) 5 0 (TL) 5 0 (TL) 5 0 (TL) 6 0 (TL) 6 0 (TL) 6 0 (TL) 6 VREF Group IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO I/O Pin Description PT23C PT22D PT22C PT21D PT21C PT20D PT20C PT19D PT19C PT18D PT18C PT17D PT17C PT16D PT16C PT15D PT15C PT14D PT14C PT13D PT13C PT12D PT12C PT11D PT11C PT10D PT10C PT9D PT9C PT8D PT8C PT7D PT7C PT6D PT6C PT5D PT5C PT4D PT4C PT3D PT3B PT3C PT3A ORCA ORSPI4 Data Sheet Additional Function PTCK1T PTCK0C PTCK0T VREF_1_05 VREF_1_06 MPI_RTRY_N MPI_ACK_N VREF_0_01 M0 M1 MPI_CLK M2 M3 VREF_0_02 MPI_TEA_N VREF_0_03 D0 TMS A20/MPI_BDIP_N A19/MPI_TSZ1 A18/MPI_TSZ0 D3 VREF_0_04 D1 D2 VREF_0_05 TDI TCK VREF_0_06 - F1156 Pair L155T L156C L156T L157C L157T L158C L158T L159C L159T L160C L160T L161C L161T L162C L162T L163C L164C L164T L165C L165T L166C L166T L167C L167T L168C L168T L169C L169T L170C L170T L171C L171T L172C L172T L173C L173T L174C L174T L175C L176C L175T L176T A21/MPI_BURST_N L163T 220 Lattice Semiconductor Table 86. 1156 fpBGA Pin Table (Continued) F1156 VDDIO Ball Bank F7 F6 G5 G6 F5 AA24 AA8 AA9 AB8 AB9 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC23 AC8 AC9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD8 AE10 AE11 AE12 AE13 AE14 AE15 AE16 0 (TL) 6 0 (TL) 6 VREF Group IO IO O IO IO VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 I/O Pin Description PT2D PT2C PCFG_MPI_IRQ PCCLK PDONE VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 ORCA ORSPI4 Data Sheet Additional Function PLL_CK1C/PPLL PLL_CK1T/PPLL CFG_IRQ_N/MPI_I RQ_N CCLK DONE - F1156 Pair L177C L177T - 221 Lattice Semiconductor Table 86. 1156 fpBGA Pin Table (Continued) F1156 VDDIO Ball Bank AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE9 K10 K11 K12 K9 L10 L11 L12 L13 L14 L15 L16 L8 M13 M14 M8 M9 N8 N9 P8 P9 R8 R9 T8 T9 U8 U9 V24 V8 V9 W24 W8 W9 Y24 Y8 Y9 VREF Group VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 I/O Pin Description VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 - ORCA ORSPI4 Data Sheet Additional Function - F1156 Pair 222 Lattice Semiconductor Table 86. 1156 fpBGA Pin Table (Continued) F1156 VDDIO Ball Bank AA25 AB24 AB25 AC24 AC25 AD24 AD25 AE24 AE25 AF22 AF23 AF24 AF25 AG23 AG24 AG25 AH22 N24 N25 P24 P25 R24 R25 T24 T25 U24 U25 V25 W25 Y25 J7 K8 AE8 AF7 AH20 AH21 D20 D21 J19 J20 J21 J23 J25 VREF Group VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDDH VDDH VDDH VDDH VDDH I/O Pin Description VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33_FPGAPLL VDD33_FPGAPLL VDD33_FPGAPLL VDD33_FPGAPLL VDD33_FPGAPLL VDD33_FPGAPLL VDD33_FPGAPLL VDD33_FPGAPLL VDDH VDDH VDDH VDDH VDDH - ORCA ORSPI4 Data Sheet Additional Function - F1156 Pair 223 Lattice Semiconductor Table 86. 1156 fpBGA Pin Table (Continued) F1156 VDDIO Ball Bank K19 K20 K21 K23 K25 L18 L19 L20 L21 L23 M18 M19 M20 M21 M23 M25 N18 N19 N20 N21 N23 P18 P19 P20 P21 J10 J11 J12 J8 J9 K7 L7 M7 N7 P7 J15 J16 J17 J18 K13 K14 K15 K16 VREF Group VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDIO0 VDDIO0 VDDIO0 VDDIO0 VDDIO0 VDDIO0 VDDIO0 VDDIO0 VDDIO0 VDDIO0 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO1 I/O Pin Description VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDIO0 VDDIO0 VDDIO0 VDDIO0 VDDIO0 VDDIO0 VDDIO0 VDDIO0 VDDIO0 VDDIO0 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO1 - ORCA ORSPI4 Data Sheet Additional Function - F1156 Pair 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) - 224 Lattice Semiconductor Table 86. 1156 fpBGA Pin Table (Continued) F1156 VDDIO Ball Bank K17 K18 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AG19 AG20 AG21 AC7 AD7 AE7 AF10 AF11 AF12 AF13 AF14 AF8 AF9 AA7 AB7 R7 T7 U6 U7 V6 V7 W7 Y7 B5 D5 C34 D4 D3 D2 E5 E4 E3 E2 E1 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) VREF Group VDDIO1 VDDIO1 VDDIO5 VDDIO5 VDDIO5 VDDIO5 VDDIO5 VDDIO5 VDDIO5 VDDIO5 VDDIO5 VDDIO5 VDDIO6 VDDIO6 VDDIO6 VDDIO6 VDDIO6 VDDIO6 VDDIO6 VDDIO6 VDDIO6 VDDIO6 VDDIO7 VDDIO7 VDDIO7 VDDIO7 VDDIO7 VDDIO7 VDDIO7 VDDIO7 VDDIO7 VDDIO7 NC NC NC NC NC NC NC NC NC NC NC I/O Pin Description VDDIO1 VDDIO1 VDDIO5 VDDIO5 VDDIO5 VDDIO5 VDDIO5 VDDIO5 VDDIO5 VDDIO5 VDDIO5 VDDIO5 VDDIO6 VDDIO6 VDDIO6 VDDIO6 VDDIO6 VDDIO6 VDDIO6 VDDIO6 VDDIO6 VDDIO6 VDDIO7 VDDIO7 VDDIO7 VDDIO7 VDDIO7 VDDIO7 VDDIO7 VDDIO7 VDDIO7 VDDIO7 - ORCA ORSPI4 Data Sheet Additional Function - F1156 Pair 225 Lattice Semiconductor Table 86. 1156 fpBGA Pin Table (Continued) F1156 VDDIO Ball Bank F3 B4 F2 F1 G3 P6 N6 M6 A5 L6 K6 AL5 AL4 AL3 AL2 AL1 AK5 AK4 AK3 A4 AK2 AK1 AM5 AM4 AM3 AM2 AN4 AN3 AP4 AJ5 B3 AJ4 AH5 AG5 AG6 AJ20 AJ25 AJ24 AJ23 AJ22 AJ21 C4 AJ29 VREF Group NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC I/O Pin Description - ORCA ORSPI4 Data Sheet Additional Function - F1156 Pair 226 Lattice Semiconductor Table 86. 1156 fpBGA Pin Table (Continued) F1156 VDDIO Ball Bank AJ28 AJ27 AJ26 AH27 AH26 AG27 AG26 AF27 AF26 C3 AH25 AH29 AH28 AK29 AK28 AK27 AK26 AK25 AP29 AP28 C2 AP27 AP26 AN29 AN28 AN27 AN26 AM29 AM28 AM27 AM26 D1 AL29 AL28 AL27 AL26 A32 A33 A34 AL30 B34 B33 A1 VREF Group NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC VSS VSS I/O Pin Description - ORCA ORSPI4 Data Sheet Additional Function - F1156 Pair 227 Lattice Semiconductor Table 86. 1156 fpBGA Pin Table (Continued) F1156 VDDIO Ball Bank A2 A3 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AC10 AC11 AC12 AC20 AC21 AC22 AD9 AM1 AM30 AM34 AN1 AN2 AN30 VREF Group VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS I/O Pin Description VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS - ORCA ORSPI4 Data Sheet Additional Function - F1156 Pair 228 Lattice Semiconductor Table 86. 1156 fpBGA Pin Table (Continued) F1156 VDDIO Ball Bank AN31 AN32 AN33 AN34 AP1 AP2 AP3 AP30 AP31 AP32 AP33 AP34 B1 B2 C1 L17 L9 M10 M11 M12 M15 M16 M17 N10 N11 N12 N13 N14 N15 N16 N17 P10 P11 P12 P13 P14 P15 P16 P17 R10 R11 R12 R13 VREF Group VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS I/O Pin Description VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS - ORCA ORSPI4 Data Sheet Additional Function - F1156 Pair 229 Lattice Semiconductor Table 86. 1156 fpBGA Pin Table (Continued) F1156 VDDIO Ball Bank R14 R15 R16 R17 T10 T11 T12 T13 T14 T15 T16 T17 U10 U11 U12 U13 U14 U15 U16 U17 U18 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 V23 W10 W11 W12 W13 W14 W15 W16 W17 VREF Group VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS I/O Pin Description VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS - ORCA ORSPI4 Data Sheet Additional Function - F1156 Pair 230 Lattice Semiconductor Table 86. 1156 fpBGA Pin Table (Continued) F1156 VDDIO Ball Bank W18 W19 W20 W21 W22 W23 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 J22 J24 J26 K22 K24 L22 L24 L25 M22 M24 N22 P22 P23 R18 R19 R20 R21 R22 R23 T18 T19 T20 T21 VREF Group VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS I/O Pin Description VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS - ORCA ORSPI4 Data Sheet Additional Function - F1156 Pair 231 Lattice Semiconductor Table 86. 1156 fpBGA Pin Table (Continued) F1156 VDDIO Ball Bank T22 T23 U19 U20 U21 U22 U23 VREF Group VSS VSS VSS VSS VSS VSS VSS I/O Pin Description VSS VSS VSS VSS VSS VSS VSS - ORCA ORSPI4 Data Sheet Additional Function - F1156 Pair Note: All differential pairs use adjacent balls. 232 Lattice Semiconductor ORCA ORSPI4 Data Sheet Table 87. 1036 ftSBGA Pin Table FTE1036 VDDIO Ball Bank J44 K42 J43 K43 K44 M42 M41 M40 L38 A1 M39 L39 N42 G30 N41 N40 L40 A2 N39 L41 P44 C42 P43 P42 L42 G31 P41 L43 R44 A11 R43 R42 M43 D42 R41 M44 T44 G36 T43 T42 N44 A22 VREF Group VDD33 O I I I IO IO IO IO VSS IO IO IO VDDIO0 IO IO IO VSS IO IO IO VDD15 IO IO IO VDDIO0 IO IO IO VSS IO IO IO VDD15 IO IO IO VDDIO0 IO IO IO VSS I/O Pin Description VDD33_FPGAPLL PRD_DATA PRESET_N PRD_CFG_N PPRGRM_N PL2D PL2C PL3D PL3B VSS PL3C PL3A PL4D VDDIO0 PL4C PL5D PL5B VSS PL5C PL5A PL6D VDD15 PL6C PL7D PL7B VDDIO0 PL7C PL7A PL8D VSS PL8C PL9D PL9B VDD15 PL9C PL9A PL10D VDDIO0 PL10C PL11D PL11B VSS RD_DATA/TDO RESET_N RD_CFG_N PRGRM_N PLL_CK0C/HPPLL PLL_CK0T/HPPLL VREF_0_07 D5 D6 VREF_0_08 HDC LDC_N TESTCFG D7 VREF_0_09 A17/PPC_A31 CS0_N CS1 Additional Function L1C L1T L3C L4C L3T L4T L5C L5T L7C L8C L7T L8T L9C L9T L11C L12C L11T L12T L13C L13T L15C L16C L15T L16T L17C L17T L19C L20C FTE1036 Pair 0 (TL) 7 0 (TL) 7 0 (TL) 7 0 (TL) 7 0 (TL) 7 0 (TL) 7 0 (TL) 7 0 (TL) 0 (TL) 7 0 (TL) 8 0 (TL) 8 0 (TL) 8 0 (TL) 8 0 (TL) 8 0 (TL) 8 0 (TL) 8 0 (TL) 8 0 (TL) 0 (TL) 8 0 (TL) 8 0 (TL) 9 0 (TL) 9 0 (TL) 9 0 (TL) 9 0 (TL) 9 0 (TL) 9 0 (TL) 9 0 (TL) 0 (TL) 9 0 (TL) 10 0 (TL) 10 - 233 Lattice Semiconductor Table 87. 1036 ftSBGA Pin Table (Continued) FTE1036 VDDIO Ball Bank T41 N43 U44 E40 U43 U42 P40 U41 P39 V44 B2 V43 G34 V42 R40 G35 V41 R39 W44 T40 W38 W43 T39 W42 U40 B43 W41 U39 Y44 V40 G37 Y43 V39 Y42 W40 Y38 Y41 W39 AA44 Y40 B44 AA43 Y39 0 (TL) 10 0 (TL) 10 0 (TL) 10 0 (TL) 10 0 (TL) 10 0 (TL) 10 0 (TL) 10 0 (TL) 10 7 (CL) 1 7 (CL) 1 7 (CL) 1 7 (CL) 1 7 (CL) 1 7 (CL) 1 7 (CL) 1 7 (CL) 1 7 (CL) 7 (CL) 1 7 (CL) 1 7 (CL) 2 7 (CL) 2 7 (CL) 2 7 (CL) 2 7 (CL) 2 7 (CL) 2 7 (CL) 2 7 (CL) 2 7 (CL) 2 7 (CL) 2 7 (CL) 7 (CL) 2 7 (CL) 2 7 (CL) 3 7 (CL) 3 7 (CL) 3 7 (CL) 3 VREF Group IO IO IO VDD15 IO IO IO IO IO IO VSS IO VSS IO IO VDD15 IO IO IO IO VDDIO7 IO IO IO IO VSS IO IO IO IO VDD15 IO IO IO IO VDDIO7 IO IO IO IO VSS IO IO I/O Pin Description PL11C PL11A PL12D VDD15 PL12C PL13D PL13B PL13C PL13A PL14D VSS PL14C VSS PL15D PL15B VDD15 PL15C PL15A PL16D PL16B VDDIO7 PL16C PL16A PL17D PL17B VSS PL17C PL17A PL18D PL18B VDD15 PL18C PL18A PL19D PL19B VDDIO7 PL19C PL19A PL20D PL20B VSS PL20C PL20A - ORCA ORSPI4 Data Sheet Additional Function FTE1036 Pair L19T L20T L21C L21T L23C L24C L23T L24T L25C L25T L27C L28C L27T L28T L29C L30C L29T L30T L31C L32C L31T L32T L34C L33T L34T L35C L36C L35T L36T L37C L38C L37T L38T INIT_N DOUT VREF_0_10 A16/PPC_A30 A15/PPC_A29 A14/PPC_A28 VREF_7_01 D4 VREF_7_02 A13/PPC_A27 A12/PPC_A26 - RDY/BUSY_N/RCLK L33C 234 Lattice Semiconductor Table 87. 1036 ftSBGA Pin Table (Continued) FTE1036 VDDIO Ball Bank AA42 AA40 H38 AA41 AA39 AB44 AB40 AB38 AB43 AB39 AB42 AC40 G20 AB41 AC39 AC44 AD40 AC43 AD39 AC42 AE40 AC38 AC41 AE39 AD44 AF40 G23 AD43 AF39 AD42 AG44 J38 AD41 AG43 AE44 AG42 AE38 AE43 AG41 AE42 AG40 G26 7 (CL) 3 7 (CL) 3 7 (CL) 3 7 (CL) 3 7 (CL) 3 7 (CL) 3 7 (CL) 7 (CL) 3 7 (CL) 3 7 (CL) 4 VREF Group IO IO VDD15 IO IO IO IO VDDIO7 IO IO IO IO VSS IO IO IO IO IO IO IO IO VDDIO7 IO IO IO IO VSS IO IO IO IO VDD15 IO IO IO IO VDDIO7 IO IO IO IO VSS I/O Pin Description PL21D PL21B VDD15 PL21C PL21A PL22D PL22B VDDIO7 PL22C PL22A PL23D PL23B VSS PL23C PL23A PL24D PL24B PL24C PL24A PL25D PL25B VDDIO7 PL25C PL25A PL26D PL26B VSS PL26C PL26A PL27D PL27B VDD15 PL27C PL27A PL28D PL28B VDDIO7 PL28C PL28A PL29D PL29B VSS - ORCA ORSPI4 Data Sheet Additional Function A11/PPC_A25 FTE1036 Pair L39C L40C L39T L40T L41C L42C L41T L42T L43C L44C L43T L44T L45C L46C L45T L46T L47C L48C L47T L48T L49C L50C L49T L50T L51C L52C L51T L52T L53C L54C L53T L54T L55C L56C - VREF_7_03 RD_N/MPI_STRB_ N VREF_7_04 PLCK0C PLCK0T A10/PPC_A24 A9/PPC_A23 A8/PPC_A22 VREF_7_05 PLCK1C PLCK1T VREF_7_06 - 7 (CL) 4 7 (CL) 4 7 (CL) 4 7 (CL) 4 7 (CL) 4 7 (CL) 4 7 (CL) 4 7 (CL) 5 7 (CL) 5 7 (CL) 7 (CL) 5 7 (CL) 5 7 (CL) 5 7 (CL) 5 7 (CL) 5 7 (CL) 5 7 (CL) 5 7 (CL) 5 7 (CL) 5 7 (CL) 5 7 (CL) 6 7 (CL) 6 7 (CL) 7 (CL) 6 7 (CL) 6 7 (CL) 6 7 (CL) 6 - 235 Lattice Semiconductor Table 87. 1036 ftSBGA Pin Table (Continued) FTE1036 VDDIO Ball Bank AE41 AG39 AF44 AH40 N38 AF43 AH39 AF42 AJ40 AF38 AF41 AJ39 AH44 AK42 G29 AH43 AK41 AH42 AK40 R7 AH41 AK39 AJ44 AJ43 AJ42 AM44 G32 AJ41 AM43 AK44 AL40 T38 AK43 AL39 AL44 AN43 AL43 AP43 AL42 AR43 AB1 AL41 AR42 7 (CL) 6 7 (CL) 6 7 (CL) 6 7 (CL) 6 7 (CL) 6 7 (CL) 6 7 (CL) 7 7 (CL) 7 7 (CL) 7 (CL) 7 7 (CL) 7 7 (CL) 7 7 (CL) 7 7 (CL) 7 7 (CL) 7 7 (CL) 7 7 (CL) 7 7 (CL) 7 7 (CL) 7 7 (CL) 8 7 (CL) 8 7 (CL) 8 7 (CL) 8 7 (CL) 8 7 (CL) 8 7 (CL) 8 7 (CL) 8 7 (CL) 8 7 (CL) 8 7 (CL) 8 7 (CL) 8 7 (CL) 8 7 (CL) 8 6 (BL) 1 6 (BL) 1 6 (BL) 1 6 (BL) 1 VREF Group IO IO IO IO VDD15 IO IO IO IO VDDIO7 IO IO IO IO VSS IO IO IO IO VDD15 IO IO IO IO IO IO VSS IO IO IO IO VDD15 IO IO IO IO IO IO IO IO VSS IO IO I/O Pin Description PL29C PL29A PL30D PL30B VDD15 PL30C PL30A PL31D PL31B VDDIO7 PL31C PL31A PL32D PL32B VSS PL32C PL32A PL33D PL33B VDD15 PL33C PL33A PL34D PL34C PL35D PL35B VSS PL35C PL35A PL36D PL36B VDD15 PL36C PL36A PL37D PL37B PL37C PL37A PL38D PL38B VSS PL38C PL38A - ORCA ORSPI4 Data Sheet Additional Function A7/PPC_A21 A6/PPC_A20 A5/PPC_A19 WR_N/MPI_RW VREF_7_07 A4/PPC_A18 VREF_7_08 A3/PPC_A17 A2/PPC_A16 A1/PPC_A15 A0/PPC_A14 DP0 DP1 D8 VREF_6_01 - FTE1036 Pair L55T L56T L57C L58C L57T L58T L59C L60C L59T L60T L61C L62C L61T L62T L63C L64C L63T L64T L65C L65T L67C L68C L67T L68T L69C L70C L69T L70T L71C L72C L71T L72T L73C L74C L73T L74T 236 Lattice Semiconductor Table 87. 1036 ftSBGA Pin Table (Continued) FTE1036 VDDIO Ball Bank AM42 AN40 U7 AM41 AN39 AM40 AP40 AJ38 AM39 AP39 AP44 AN42 AD7 AR44 AN41 AP42 AT44 Y7 AP41 AT43 AU44 AV44 AM38 AU43 AV43 AU42 AW44 AD38 AT42 AY44 AR41 BB44 AC7 AR40 BA44 AU41 AR38 AT41 AT40 AG7 AT39 AG38 AR39 6 (BL) 1 6 (BL) 1 6 (BL) 1 6 (BL) 1 6 (BL) 2 6 (BL) 2 6 (BL) 6 (BL) 2 6 (BL) 2 6 (BL) 2 6 (BL) 2 6 (BL) 2 6 (BL) 2 6 (BL) 3 6 (BL) 3 6 (BL) 3 6 (BL) 3 6 (BL) 3 6 (BL) 3 6 (BL) 6 (BL) 3 6 (BL) 3 6 (BL) 3 6 (BL) 4 6 (BL) 3 6 (BL) 4 6 (BL) 4 6 (BL) 4 6 (BL) 4 6 (BL) 4 6 (BL) 4 6 (BL) 6 (BL) 4 6 (BL) 4 6 (BL) 4 VREF Group IO IO VDD15 IO IO IO IO VDDIO6 IO IO IO IO VSS IO IO IO IO VDD15 IO IO IO IO VDDIO6 IO IO IO IO VSS IO IO IO IO VDD15 IO IO IO VDDIO6 IO IO VSS IO VSS I I/O Pin Description PL39D PL39B VDD15 PL39C PL39A PL40D PL40B VDDIO6 PL40C PL40A PL41D PL41B VSS PL41C PL41A PL42D PL42B VDD15 PL42C PL42A PL43D PL43B VDDIO6 PL43C PL43A PL44D PL44B VSS PL44C PL44A PL45D PL45B VDD15 PL45C PL45A PL46D VDDIO6 PL46C PL47D VSS PL47C VSS PTEMP D9 D10 - ORCA ORSPI4 Data Sheet Additional Function FTE1036 Pair L75C L76C L75T L76T L77C L78C L77T L78T L79C L80C L79T L80T L81C L82C L81T L82T L83C L84C L83T L84T L85C L86C L85T L86T L87C L88C L87T L88T L89C L89T L91C L91T - VREF_6_02 D11 D12 VREF_6_03 D13 VREF_6_04 PLL_CK7C/HPPLL PLL_CK7T/HPPLL PTEMP 237 Lattice Semiconductor Table 87. 1036 ftSBGA Pin Table (Continued) FTE1036 VDDIO Ball Bank AV29 AE7 BC33 BA42 AK7 AV42 AH38 BB43 BC42 AV32 BA43 BD42 BC41 AK38 BD41 BC40 AJ7 BD40 AW43 BA37 AV35 AY43 BB37 AW42 BC37 AN1 AY42 BD37 AW41 BA36 AL38 AV41 BB36 AY41 BC36 BA41 BD36 AU40 BA35 AN7 AU39 BB35 AW40 6 (BL) VREF Group VDDIO6 VDD15 IO VDD33 VSS VDD33 VDD15 IO IO VDDIO6 IO IO IO VSS IO IO VDD15 IO IO IO VDDIO6 IO IO IO IO VSS IO IO IO IO VDD15 IO IO IO IO IO IO IO IO VSS IO IO IO I/O Pin Description VDDIO6 VDD15 LVDS_R VDD33_FPGAPLL VSS VDD33_FPGAPLL VDD15 PB2A PB2C VDDIO6 PB2B PB2D PB3C VSS PB3D PB4C VDD15 PB4D PB5A PB5C VDDIO6 PB5B PB5D PB6A PB6C VSS PB6B PB6D PB7A PB7C VDD15 PB7B PB7D PB8A PB8C PB8B PB8D PB9A PB9C VSS PB9B PB9D PB10A - ORCA ORSPI4 Data Sheet Additional Function - FTE1036 Pair LVDS_R DP2 PLL_CK6T/PPLL PLL_CK6C/PPLL VREF_6_05 DP3 VREF_6_06 D14 D15 D16 D17 D18 - 6 (BL) 5 6 (BL) 5 6 (BL) 6 (BL) 5 6 (BL) 5 6 (BL) 5 6 (BL) 5 6 (BL) 5 6 (BL) 5 6 (BL) 6 6 (BL) 6 6 (BL) 6 (BL) 6 6 (BL) 6 6 (BL) 6 6 (BL) 6 6 (BL) 6 6 (BL) 6 6 (BL) 6 6 (BL) 6 6 (BL) 6 6 (BL) 6 6 (BL) 7 6 (BL) 7 6 (BL) 7 6 (BL) 7 6 (BL) 7 6 (BL) 7 6 (BL) 7 6 (BL) 7 6 (BL) 7 L93T L94T L93C L94C L96T L96C L98T L98C L99T L100T L99C L100C L101T L102T L101C L102C L103T L104T L103C L104C L105T L106T L105C L106C L107T L108T L107C L108C L109T 238 Lattice Semiconductor Table 87. 1036 ftSBGA Pin Table (Continued) FTE1036 VDDIO Ball Bank BC35 AV40 BD35 BA34 BB34 BA40 BC34 BB40 BD34 AV39 BA33 AW39 BB33 BB39 BA32 BA39 BB32 BC39 BC32 BD39 BD32 BB38 BA31 BA38 BB31 AW38 BC31 AY38 BD31 BC38 BA30 BD38 BB30 AW37 BC30 AY37 BD30 AW36 BA29 AY36 BB29 AW35 BC29 6 (BL) 7 6 (BL) 7 6 (BL) 7 6 (BL) 8 6 (BL) 8 6 (BL) 8 6 (BL) 8 6 (BL) 8 6 (BL) 8 6 (BL) 9 6 (BL) 9 6 (BL) 9 6 (BL) 9 6 (BL) 9 6 (BL) 9 6 (BL) 9 6 (BL) 9 6 (BL) 9 6 (BL) 9 6 (BL) 9 6 (BL) 9 6 (BL) 10 6 (BL) 10 6 (BL) 10 6 (BL) 10 6 (BL) 10 6 (BL) 10 6 (BL) 10 6 (BL) 10 6 (BL) 10 6 (BL) 10 6 (BL) 10 6 (BL) 10 6 (BL) 11 6 (BL) 11 6 (BL) 11 6 (BL) 11 6 (BL) 11 6 (BL) 11 6 (BL) 11 6 (BL) 11 5 (BC) 1 5 (BC) 1 VREF Group IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO I/O Pin Description PB10C PB10B PB10D PB11C PB11D PB12A PB12C PB12B PB12D PB13A PB13C PB13B PB13D PB14A PB14C PB14B PB14D PB15A PB15C PB15B PB15D PB16A PB16C PB16B PB16D PB17A PB17C PB17B PB17D PB18A PB18C PB18B PB18D PB19A PB19C PB19B PB19D PB20A PB20C PB20B PB20D PB21A PB21C D19 D20 D21 - ORCA ORSPI4 Data Sheet Additional Function VREF_6_07 FTE1036 Pair L110T L109C L110C L112T L112C L113T L114T L113C L114C L115T L116T L115C L116C L117T L118T L117C L118C L119T L120T L119C L120C L121T L122T L121C L122C L123T L124T L123C L124C L125T L126T L125C L126C L127T L128T L127C L128C L129T L130T L129C L130C L131T L132T VREF_6_08 D22 D23 D24 VREF_6_09 D25 D26 D27 VREF_6_10 D28 D29 D30 VREF_6_11 D31 - 239 Lattice Semiconductor Table 87. 1036 ftSBGA Pin Table (Continued) FTE1036 VDDIO Ball Bank AN38 AY35 BD29 AW34 BA28 AM7 AY34 BB28 AW33 BC28 AV17 BD28 BA27 AY33 BB27 AW32 BC27 AP38 AY32 BD27 AW31 BA26 AV20 AY31 BB26 AW30 BC26 AN44 AY30 BD26 AW29 BA25 AR7 AY29 BB25 AW28 BC25 AV21 AY28 BD25 AW27 BA24 AV7 5 (BC) 1 5 (BC) 1 5 (BC) 1 5 (BC) 1 5 (BC) 1 5 (BC) 1 5 (BC) 2 5 (BC) 2 5 (BC) 5 (BC) 2 5 (BC) 2 5 (BC) 2 5 (BC) 2 5 (BC) 2 5 (BC) 2 5 (BC) 2 5 (BC) 2 5 (BC) 3 5 (BC) 3 5 (BC) 5 (BC) 3 5 (BC) 3 5 (BC) 3 5 (BC) 3 5 (BC) 3 5 (BC) 3 5 (BC) 3 5 (BC) 3 5 (BC) 3 5 (BC) 3 5 (BC) 3 5 (BC) 4 5 (BC) 5 (BC) 3 5 (BC) 4 5 (BC) 4 5 (BC) 4 VREF Group VSS IO IO IO IO VDD15 IO IO IO IO VDDIO5 IO IO IO IO IO IO VDD15 IO IO IO IO VDDIO5 IO IO IO IO VSS IO IO IO IO VDD15 IO IO IO IO VDDIO5 IO IO IO IO VSS I/O Pin Description VSS PB21B PB21D PB22A PB22C VDD15 PB22B PB22D PB23A PB23C VDDIO5 PB23D PB24C PB24B PB24D PB25A PB25C VDD15 PB25B PB25D PB26A PB26C VDDIO5 PB26B PB26D PB27A PB27C VSS PB27B PB27D PB28A PB28C VDD15 PB28B PB28D PB29A PB29C VDDIO5 PB29B PB29D PB30A PB30C VSS - ORCA ORSPI4 Data Sheet Additional Function - FTE1036 Pair L131C L132C L133T L134T L133C L134C L135T L136T L136C L138T L137C L138C L139T L140T L139C L140C L141T L142T L141C L142C L143T L144T L143C L144C L145T L146T L145C L146C L147T L148T L147C L148C L149T L150T - VREF_5_01 PBCK0T PBCK0C VREF_5_02 VREF_5_03 PBCK1T PBCK1C - 240 Lattice Semiconductor Table 87. 1036 ftSBGA Pin Table (Continued) FTE1036 VDDIO Ball Bank AY27 BB24 AW26 BC24 AT7 AY26 BD24 AW25 BA23 AV23 AY25 BB23 AW23 BC23 AV18 AY23 BD23 AW24 BA22 AT38 AY24 BB22 AW22 BD21 AV25 AY22 BC21 BD20 AV22 BC20 AY21 BB20 AU7 AW21 BA20 BA21 BD19 AV26 BB21 BC19 AY20 BB19 AV24 5 (BC) 4 5 (BC) 4 5 (BC) 4 5 (BC) 4 5 (BC) 4 5 (BC) 4 5 (BC) 5 5 (BC) 5 5 (BC) 5 (BC) 5 5 (BC) 5 5 (BC) 5 5 (BC) 5 5 (BC) 5 5 (BC) 5 5 (BC) 5 5 (BC) 5 5 (BC) 5 5 (BC) 5 5 (BC) 6 5 (BC) 6 5 (BC) 5 (BC) 6 5 (BC) 6 5 (BC) 6 5 (BC) 6 5 (BC) 7 5 (BC) 7 5 (BC) 7 5 (BC) 7 5 (BC) 7 5 (BC) 7 5 (BC) 5 (BC) 7 5 (BC) 7 5 (BC) 7 5 (BC) 7 VREF Group IO IO IO IO VDD15 IO IO IO IO VDDIO5 IO IO IO IO VSS IO IO IO IO VDD15 IO IO IO IO VDDIO5 IO IO IO VSS IO IO IO VDD15 IO IO IO IO VDDIO5 IO IO IO IO VSS I/O Pin Description PB30B PB30D PB31A PB31C VDD15 PB31B PB31D PB32A PB32C VDDIO5 PB32B PB32D PB33A PB33C VSS PB33B PB33D PB34A PB34C VDD15 PB34B PB34D PB35A PB35C VDDIO5 PB35B PB35D PB36C VSS PB36D PB37A PB37C VDD15 PB37B PB37D PB38A PB38C VDDIO5 PB38B PB38D PB39A PB39C VSS - ORCA ORSPI4 Data Sheet Additional Function VREF_5_04 VREF_5_05 VREF_5_06 VREF_5_07 - FTE1036 Pair L149C L150C L151T L152T L151C L152C L153T L154T L153C L154C L155T L156T L155C L156C L157T L158T L157C L158C L159T L160T L159C L160C L162T L162C L163T L164T L163C L164C L165T L166T L165C L166C L167T L168T - 241 Lattice Semiconductor Table 87. 1036 ftSBGA Pin Table (Continued) FTE1036 VDDIO Ball Bank AW20 BA19 AY19 BD18 AW19 BC18 AY18 BB18 AW18 BA18 AY17 BD17 AV27 AW17 BC17 AY16 BB17 AW16 BA17 BD13 BD16 BC13 BC16 BB16 AV30 BA16 BD12 BD14 BC12 BD15 BC15 BC14 BC11 AV33 BD7 BD8 BB1 BB2 AV15 BD6 BC8 AV38 BC7 5 (BC) 7 5 (BC) 7 5 (BC) 8 5 (BC) 8 5 (BC) 8 5 (BC) 8 5 (BC) 8 5 (BC) 8 5 (BC) 8 5 (BC) 8 5 (BC) 8 5 (BC) 8 5 (BC) 8 5 (BC) 8 5 (BC) 9 5 (BC) 9 5 (BC) 9 5 (BC) 9 5 (BC) 9 5 (BC) 9 5 (BC) 9 5 (BC) 9 5 (BC) 9 5 (BC) 9 5 (BC) 10 5 (BC) 10 5 (BC) 10 5 (BC) 10 5 (BC) 10 5 (BC) 10 VREF Group IO IO IO IO IO IO IO IO IO IO IO IO VSS IO IO IO IO IO IO IO IO IO IO IO VSS IO IO IO IO IO IO IO VDD33 VSS VDD33 I I I I VDDGB I VSS I I/O Pin Description PB39B PB39D PB40A PB40C PB40B PB40D PB41A PB41C PB41B PB41D PB42A PB42C VSS PB42B PB42D PB43A PB43C PB43B PB43D PB44A PB44C PB44B PB44D PB45C VSS PB45D PB46A PB46C PB46B PB46D PB47C PB47D VDD33_FPGAPLL VSS VDD33_FPGAPLL SPARE_1 RESETN TRISTN TESTMD1N VDDGB TESTMD0N VSS PDN - ORCA ORSPI4 Data Sheet Additional Function FTE1036 Pair L167C L168C L169T L170T L169C L170C L171T L172T L171C L172C L173T L174T L173C L174C L175T L176T L175C L176C L177T L178T L177C L178C L180T L180C L181T L182T L181C L182C L184T L184C - VREF_5_08 VREF_5_09 VREF_5_10 PLL_CK5T/PPLL PLL_CK5C/PPLL - 242 Lattice Semiconductor Table 87. 1036 ftSBGA Pin Table (Continued) FTE1036 VDDIO Ball Bank BD5 BD4 BD3 BC3 AV13 BB7 BC6 BC4 BC5 AW8 AW15 AY15 BA15 BB15 AY14 AW10 BA14 AV10 BB14 AW12 AW13 AY13 BA13 BB13 AY12 AW14 BA12 AV12 BB12 BC9 AW11 AY11 BA11 BB11 AV14 AY10 BC10 BA10 BB10 BD9 AW9 AY9 BA9 VREF Group I I I I I I O O O VSS VDDOB O O VDDOB I VSS I VDD_ANA VDDIB VSS VDDOB O O VDDOB I VSS I VDD_ANA VDDIB VSS VDDOB O O VDDOB VDD_ANA I VSS I VDDIB VSS VDDOB O O I/O Pin Description ATREFCLK TESTCLK BTREFCLK TSTAT1B TSTAT0B TSCLKB RSTAT1B RSTAT0B RSCLKB VSS VDDOB_D HDOUTP_D HDOUTN_D VDDOB_D HDINP_D VSS HDINN_D VDD_ANA VDDIB_D VSS VDDOB_C HDOUTP_C HDOUTN_C VDDOB_C HDINP_C VSS HDINN_C VDD_ANA VDDIB_C VSS VDDOB_B HDOUTP_B HDOUTN_B VDDOB_B VDD_ANA HDINP_B VSS HDINN_B VDDIB_B VSS VDDOB_A HDOUTP_A HDOUTN_A - ORCA ORSPI4 Data Sheet Additional Function - FTE1036 Pair HSP_1 HSN_1 HSP_2 HSN_2 HSP_3 HSN_3 HSP_4 HSN_4 HSP_5 HSN_5 HSP_6 HSN_6 HSP_7 HSN_7 243 Lattice Semiconductor Table 87. 1036 ftSBGA Pin Table (Continued) FTE1036 VDDIO Ball Bank BB9 AV8 AY8 BD10 BA8 BB8 AW7 AY7 BA7 AV11 AW4 AU6 AW3 AV6 AV3 T6 AV9 T7 AV2 AY2 AR6 AW2 BC1 AT4 BC2 BB5 AT3 BB6 AU38 AV16 AR5 BC22 BA1 AR4 AY1 AP5 W6 AW1 W7 AP4 AV1 BC43 AN6 VREF Group VDDOB VDD_ANA I VSS I VDDIB I I O O I I I I I VDD33 I/O VDD33 I I I/O I VSS I VSS I I I VDD15 VDD15 O VSS O O O O VDD33 O VDD33 O O VSS O I/O Pin Description VDDOB_A VDD_ANA HDINP_A VSS HDINN_A VDDIB_A REFCLKP REFCLKN REXTN REXT ATSTAT1N ATSTAT0N ATSTAT1P ATSTAT0P ATSCLKN VDD33 ALVCTAP5 VDD33 ATSCLKP BTSCLKN BLVCTAP5 BTSCLKP VSS BTSTAT1N VSS BTSTAT0N BTSTAT1P BTSTAT0P VDD15 VDD15 BRSTAT1N VSS BRSTAT0N BRSTAT1P BRSTAT0P BRSCLKN VDD33 ARSCLKN VDD33 BRSCLKP ARSCLKP VSS ARSTAT1N - ORCA ORSPI4 Data Sheet Additional Function - FTE1036 Pair HSP_8 HSN_8 HSP_9 HSN_9 R1C R2C R1T R2T R3C R3T R4C R4T R5C R6C R5T R6T R7C R8C R7T R8T R9C R10C R9T R10T R11C 244 Lattice Semiconductor Table 87. 1036 ftSBGA Pin Table (Continued) FTE1036 VDDIO Ball Bank BA5 BC44 AN5 BA6 AV19 AV28 AU1 AP1 BD1 AR1 BA2 AB6 AB7 AM6 BD2 BA4 AM5 BA3 AM4 AV31 AY4 AM3 AV34 AY3 AL5 BD11 AW5 AL4 AW6 AF6 AL3 AF7 AV5 AL2 AV4 BD22 AK6 BD33 AU5 AK5 AU4 AV36 AK4 VREF Group O VSS O O VDD15 VDD15 I I VSS I I VDD33 VDD33 O VSS O O O O VDD15 O O VDD15 O O VSS O O O VDD33 O VDD33 O O O VSS O VSS O O O VDD15 VDDA_SPIA I/O Pin Description ARSTAT0N VSS ARSTAT1P ARSTAT0P VDD15 VDD15 RESLO RESHI VSS REF14 REF10 VDD33 VDD33 BTDAT15N VSS BTDAT14N BTDAT15P BTDAT14P BTDAT13N VDD15 BTDAT12N BTDAT13P VDD15 BTDAT12P BTDAT11N VSS BTDAT10N BTDAT11P BTDAT10P VDD33 BTDAT9N VDD33 BTDAT8N BTDAT9P BTDAT8P VSS BTCTLN VSS BTDCLKN BTCTLP BTDCLKP VDD15 VDDA_SPIA - ORCA ORSPI4 Data Sheet Additional Function - FTE1036 Pair R12C R11T R12T R13C R14C R13T R14T R15C R16C R15T R16T R17C R18C R17T R18T R19C R20C R19T R20T R21C R22C R21T R22T - 245 Lattice Semiconductor Table 87. 1036 ftSBGA Pin Table (Continued) FTE1036 VDDIO Ball Bank AV37 AK3 AU3 AJ6 BD43 AU2 AJ5 AJ4 AH6 AT6 AJ3 AH7 AT5 AH5 AT2 BD44 AH4 AT1 AH3 AY5 AR3 AH2 AY6 AP3 AG6 AR2 AG5 AP2 AF1 AL6 AN4 AL7 AG4 AN3 AG3 AM2 AF3 AM1 AF2 AL1 AF4 AK1 AE6 VREF Group VDD15 VSS O O VSS O O O VDD33 O O VDD33 O O O VSS O O O VDD15 O O VDD15 O I I I I I/O VDD33 I VDD33 I I I I I I I I I/O I I I/O Pin Description VDD15 VSS BTDAT7N BTDAT6N VSS BTDAT7P BTDAT6P BTDAT5N VDD33 BTDAT4N BTDAT5P VDD33 BTDAT4P BTDAT3N BTDAT2N VSS BTDAT3P BTDAT2P BTDAT1N VDD15 BTDAT0N BTDAT1P VDD15 BTDAT0P BRDCLKN BRDAT15N BRDCLKP BRDAT15P BLVCTAP1 VDD33 BRDAT14N VDD33 BRDAT13N BRDAT14P BRDAT13P BRDAT12N BRDAT11N BRDAT12P BRDAT11P BRDAT10N BLVCTAP2 BRDAT10P BRDAT9N - ORCA ORSPI4 Data Sheet Additional Function - FTE1036 Pair R23C R24C R23T R24T R25C R26C R25T R26T R27C R28C R27T R28T R29C R30C R29T R31T R32C R33C R32T R33T R34C R35C R34T R35T R36C R37C R36T R37T R38C R38T R39C 246 Lattice Semiconductor Table 87. 1036 ftSBGA Pin Table (Continued) FTE1036 VDDIO Ball Bank AK2 AE5 AJ2 AE4 AN2 AE3 AP6 AJ1 AP7 AD6 AH1 AD5 AG2 AD4 AG1 AD3 AF5 AC6 AE2 AC5 AE1 AC4 AD2 AC3 AD1 W1 V1 AC1 U1 AC2 AA1 AA2 AB2 AA3 AB3 AA4 Y1 V2 Y2 U2 Y3 AB5 Y4 VREF Group I I I I I/O I VDD33 I VDD33 I I I I I I I I/O I I I I I I I I VSS VDDA_SPIB O VSS O O O O O O O O O O O O O O I/O Pin Description BRDAT8N BRDAT9P BRDAT8P BRCTLN BLVCTAP3 BRCTLP VDD33 BRDAT7N VDD33 BRDAT6N BRDAT7P BRDAT6P BRDAT5N BRDAT4N BRDAT5P BRDAT4P BLVCTAP4 BRDAT3N BRDAT2N BRDAT3P BRDAT2P BRDAT1N BRDAT0N BRDAT1P BRDAT0P VSS VDDA_SPIB ATDAT15N VSS ATDAT15P ATDAT14N ATDAT14P ATDAT13N ATDAT12N ATDAT13P ATDAT12P ATDAT11N ATDAT10N ATDAT11P ATDAT10P ATDAT9N ATDAT8N ATDAT9P - ORCA ORSPI4 Data Sheet Additional Function FTE1036 Pair R40C R39T R40T R41C R41T R42C R43C R42T R43T R44C R45C R44T R45T R46C R47C R46T R47T R48C R49C R48T R49T R50C R50T R51C R51T R52C R53C R52T R53T R54C R55C R54T R55T R56C R57C R56T 247 Lattice Semiconductor Table 87. 1036 ftSBGA Pin Table (Continued) FTE1036 VDDIO Ball Bank AB4 W2 AA5 W3 Y5 W4 AA6 W5 Y6 T1 V3 R1 U3 T2 V4 R2 U4 T3 R4 R3 R5 T4 U5 U6 P1 V5 P2 V6 T5 M3 P3 M4 P4 P5 N1 P6 N2 R6 N3 N5 N4 N6 M1 VREF Group O O O O O O O O O O O O O O O O O O O O O VSS VDDA_SPIC VSS I I I I I/O I I I I I I I I I/O I I I I I I/O Pin Description ATDAT8P ATCTLN ATDCLKN ATCTLP ATDCLKP ATDAT7N ATDAT6N ATDAT7P ATDAT6P ATDAT5N ATDAT4N ATDAT5P ATDAT4P ATDAT3N ATDAT2N ATDAT3P ATDAT2P ATDAT1N ATDAT0N ATDAT1P ATDAT0P VSS VDDA_SPIC VSS ARDCLKN ARDAT15N ARDCLKP ARDAT15P ALVCTAP1 ARDAT14N ARDAT13N ARDAT14P ARDAT13P ARDAT12N ARDAT11N ARDAT12P ARDAT11P ALVCTAP2 ARDAT10N ARDAT9N ARDAT10P ARDAT9P ARDAT8N - ORCA ORSPI4 Data Sheet Additional Function FTE1036 Pair R57T R58C R59C R58T R59T R60C R61C R60T R61T R62C R63C R62T R63T R64C R65C R64T R65T R66C R67C R66T R67T R68C R69C R68T R69T R70C R71C R70T R71T R72C R73C R72T R73T R74C R75C R74T R75T R76C 248 Lattice Semiconductor Table 87. 1036 ftSBGA Pin Table (Continued) FTE1036 VDDIO Ball Bank L2 M2 L3 G1 M6 K1 M5 K2 K3 J1 J3 J2 H3 H1 L5 H2 L4 G2 K4 G3 J4 L6 K5 F1 L7 E1 D4 H4 D1 K6 F2 J5 C4 G4 E2 E5 G5 F3 G9 J6 F4 H5 F6 VREF Group I I I I/O I I I I I I I I I/O I I I I I I I I VDDA_SPID VSS I I I VSS O O O I/O I/O I/O I/O I/O VSS I/O I/O VSS I/O I/O I/O VDDH I/O Pin Description ARCTLN ARDAT8P ARCTLP ALVCTAP3 ARDAT7N ARDAT6N ARDAT7P ARDAT6P ARDAT5N ARDAT4N ARDAT5P ARDAT4P ALVCTAP4 ARDAT3N ARDAT2N ARDAT3P ARDAT2P ARDAT1N ARDAT0N ARDAT1P ARDAT0P VDDA_SPID VSS TSTAT1A TSTAT0A TSCLKA VSS RSTAT1A RSTAT0A RSCLKA PMIA17 PMIA16 PMIA15 PMIA14 PMIA13 VSS PMIA12 PMIA11 VSS PMIA10 PMIA9 PMIA8 VDDH - ORCA ORSPI4 Data Sheet Additional Function FTE1036 Pair R77C R76T R77T R78C R79C R78T R79T R80C R81C R80T R81T R82C R83C R82T R83T R84C R85C R84T R85T - 249 Lattice Semiconductor Table 87. 1036 ftSBGA Pin Table (Continued) FTE1036 VDDIO Ball Bank E3 D2 E4 D3 G13 G6 G15 H6 H7 C1 G7 C3 F5 E6 K7 C2 G10 M7 P7 D7 D5 G12 C5 D6 G8 F7 C6 E7 G14 D8 B3 E8 B4 B9 A3 C7 A4 G16 C8 A9 B5 C10 D10 VREF Group I/O I/O I/O VREF VSS I/O VSS I/O I/O I/O VDDH I/O I/O I/O VSS I VDDH VSS VSS I/O I/O VDDH I/O I/O I/O I/O I/O I/O VDDH I/O I/O I/O I/O I/O I/O I/O I/O VDDH I/O I/O I/O I/O VREF I/O Pin Description PMIWN PMIRN PMIA7 REFI_1 VSS PMIA6 VSS PMIA5 PMIA4 PMIA3 VDDH PMIA2 PMIA1 PMIA0 VSS EXT_1K VDDH VSS VSS PMID35 PMID34 VDDH PMID33 PMID32 PMID31 PMID30 PMID29 PMID28 VDDH PMID27 PMID26 PMID25 PMID24 PMID23 PMID22 PMID21 PMID20 VDDH PMID19 PMID18 PMID17 PMID16 REFI_2 - ORCA ORSPI4 Data Sheet Additional Function - FTE1036 Pair 250 Lattice Semiconductor Table 87. 1036 ftSBGA Pin Table (Continued) FTE1036 VDDIO Ball Bank F8 B10 D9 A10 E9 B11 C9 C11 J7 F9 D11 B6 E11 B7 C12 N7 A5 D12 B8 B12 A12 C13 D13 A7 B13 A8 A13 A6 C14 F11 D14 G11 B14 F10 A14 E10 C15 F12 D15 E12 B15 F13 A15 VREF Group I/O I/O I/O I/O I/O I/O I/O I/O VDDH I/O I/O I/O I/O I/O I/O VDDH I/O I/O I/O I/O VREF I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin Description PMIK PMIKN PMID15 PMID14 PMID13 PMID12 PMID11 PMID10 VDDH PMID9 PMID8 PMID7 PMID6 PMID5 PMID4 VDDH PMID3 PMID2 PMID1 PMID0 REFI_3 PMIC PMICN PMIQ35 PMIQ34 PMIQ33 PMIQ32 PMIQ31 PMIQ30 PMIQ29 PMIQ28 PMIQ27 PMIQ26 PMIQ25 PMIQ24 PMIQ23 PMIQ22 PMIQ21 PMIQ20 PMIQ19 PMIQ18 PMIQ17 PMIQ16 - ORCA ORSPI4 Data Sheet Additional Function - FTE1036 Pair 251 Lattice Semiconductor Table 87. 1036 ftSBGA Pin Table (Continued) FTE1036 VDDIO Ball Bank E13 C16 F14 D16 E14 B16 F15 A16 E15 C17 F16 D17 E16 B17 F17 A17 E17 A18 D18 B18 C18 A19 B19 E18 G17 F18 C19 AY39 E21 D19 F21 E19 L1 F19 C20 G18 E23 D20 F23 E20 AY40 E24 F20 VREF Group I/O I/O I/O VREF I/O I/O I/O VDDA_PLL I/O VSS I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD33 VDD33 IO VDDIO1 IO IO VDD15 IO IO IO IO VSS IO IO VDDIO1 IO IO IO IO VDD15 IO IO I/O Pin Description MCREFCLK SPARE_2 PMIQ15 REFI_4 PMIQ14 PMIQ13 PMIQ12 VDDA_PLL PMIQ11 VSS PMIQ10 PMIQ9 PMIQ8 PMIQ7 PMIQ6 PMIQ5 PMIQ4 PMIQ3 PMIQ2 PMIQ1 PMIQ0 VDD33_FPGAPLL VDD33_FPGAPLL PT47D VDDIO1 PT47C PT46D VDD15 PT46B PT46C PT46A PT45D VSS PT45C PT44D VDDIO1 PT44B PT44C PT44A PT43D VDD15 PT43B PT43C - ORCA ORSPI4 Data Sheet Additional Function - FTE1036 Pair 1 (TC) 7 1 (TC) 1 (TC) 7 1 (TC) 7 1 (TC) 7 1 (TC) 7 1 (TC) 7 1 (TC) 7 1 (TC) 7 1 (TC) 8 1 (TC) 1 (TC) 8 1 (TC) 8 1 (TC) 8 1 (TC) 8 1 (TC) 8 1 (TC) 8 PLL_CK2C/PPLL PLL_CK2T/PPLL VREF_1_07 - L185C L185T L187C L188C L187T L188T L189C L189T L191C L192C L191T L192T L193C L194C L193T 252 Lattice Semiconductor Table 87. 1036 ftSBGA Pin Table (Continued) FTE1036 VDDIO Ball Bank F24 B20 L44 F22 A20 G22 C21 G21 E26 D21 F26 B21 BB3 E25 A21 F25 D22 M38 E28 E22 F28 C22 G24 E29 B22 F29 C23 BB4 E27 D23 F27 B23 R38 A23 C24 G27 C31 D24 D31 B24 BB41 E31 A24 1 (TC) 8 1 (TC) 8 1 (TC) 8 1 (TC) 8 1 (TC) 8 1 (TC) 9 1 (TC) 1 (TC) 9 1 (TC) 9 1 (TC) 9 1 (TC) 9 1 (TC) 9 1 (TC) 9 1 (TC) 9 1 (TC) 9 1 (TC) 9 1 (TC) 9 1 (TC) 9 1 (TC) 10 1 (TC) 1 (TC) 10 1 (TC) 10 1 (TC) 10 1 (TC) 10 1 (TC) 10 1 (TC) 10 1 (TC) 10 1 (TC) 10 1 (TC) 10 1 (TC) 1 1 (TC) 1 (TC) 1 1 (TC) 1 1 (TC) 1 1 (TC) 1 1 (TC) 1 1 (TC) 1 VREF Group IO IO VSS IO IO IO IO VDDIO1 IO IO IO IO VDD15 IO IO IO IO VSS IO IO IO IO VDDIO1 IO IO IO IO VDD15 IO IO IO IO VSS IO IO VDDIO1 IO IO IO IO VDD15 IO IO I/O Pin Description PT43A PT42D VSS PT42B PT42C PT42A PT41D VDDIO1 PT41B PT41C PT41A PT40D VDD15 PT40B PT40C PT40A PT39D VSS PT39B PT39C PT39A PT38D VDDIO1 PT38B PT38C PT38A PT37D VDD15 PT37B PT37C PT37A PT36D VSS PT36C PT35D VDDIO1 PT35B PT35C PT35A PT34D VDD15 PT34B PT34C - ORCA ORSPI4 Data Sheet Additional Function VREF_1_08 VREF_1_09 VREF_1_10 VREF_1_01 - FTE1036 Pair L194T L195C L196C L195T L196T L197C L198C L197T L198T L199C L200C L199T L200T L201C L202C L201T L202T L203C L204C L203T L204T L205C L206C L205T L206T L207C L207T L209C L210C L209T L210T L211C L212C L211T 253 Lattice Semiconductor Table 87. 1036 ftSBGA Pin Table (Continued) FTE1036 VDDIO Ball Bank F31 C25 V7 E30 D25 F30 B25 G28 E32 A25 F32 C26 BB42 D33 D26 E33 B26 V38 F33 A26 G33 C27 E34 D27 F34 B27 E35 A27 F35 C28 AA7 C35 D28 D35 B28 A37 A28 B37 C29 E36 D29 F36 B29 1 (TC) 1 1 (TC) 1 1 (TC) 1 1 (TC) 1 1 (TC) 1 1 (TC) 2 1 (TC) 1 (TC) 2 1 (TC) 2 1 (TC) 2 1 (TC) 2 1 (TC) 2 1 (TC) 2 1 (TC) 2 1 (TC) 2 1 (TC) 2 1 (TC) 2 1 (TC) 2 1 (TC) 3 1 (TC) 3 1 (TC) 3 1 (TC) 3 1 (TC) 3 1 (TC) 3 1 (TC) 3 1 (TC) 3 1 (TC) 3 1 (TC) 3 1 (TC) 3 1 (TC) 3 1 (TC) 4 1 (TC) 4 1 (TC) 4 1 (TC) 4 1 (TC) 4 1 (TC) 4 1 (TC) 4 1 (TC) 4 1 (TC) 4 VREF Group IO IO VSS IO IO IO IO VDDIO1 IO IO IO IO VDD15 IO IO IO IO VSS IO IO IO IO IO IO IO IO IO IO IO IO VSS IO IO IO IO IO IO IO IO IO IO IO IO I/O Pin Description PT34A PT33D VSS PT33B PT33C PT33A PT32D VDDIO1 PT32B PT32C PT32A PT31D VDD15 PT31B PT31C PT31A PT30D VSS PT30B PT30C PT30A PT29D PT29B PT29C PT29A PT28D PT28B PT28C PT28A PT27D VSS PT27B PT27C PT27A PT26D PT26B PT26C PT26A PT25D PT25B PT25C PT25A PT24D - ORCA ORSPI4 Data Sheet Additional Function FTE1036 Pair L212T L213C L214C L213T L214T L215C L216C L215T L216T L217C L218C L217T L218T L219C L220C L219T L220T L221C L222C L221T L222T L223C L224C L223T L224T L225C L226C L225T L226T L227C L228C L227T L228T L229C L230C L229T L230T L231C VREF_1_02 VREF_1_03 - 254 Lattice Semiconductor Table 87. 1036 ftSBGA Pin Table (Continued) FTE1036 VDDIO Ball Bank AA38 C37 A29 D37 A30 E37 B30 F37 D30 A38 C30 B38 A31 C38 B31 D38 A32 E38 B32 F38 C32 E43 D32 E44 A34 A33 F44 B34 F43 B33 G38 F41 C33 F42 C34 F40 G39 D34 G40 A35 A43 H40 B35 1 (TC) 4 1 (TC) 4 1 (TC) 4 1 (TC) 5 1 (TC) 5 1 (TC) 5 1 (TC) 5 1 (TC) 5 1 (TC) 5 1 (TC) 5 1 (TC) 5 1 (TC) 5 1 (TC) 5 1 (TC) 5 1 (TC) 5 1 (TC) 6 1 (TC) 6 1 (TC) 6 1 (TC) 6 1 (TC) 6 1 (TC) 6 1 (TC) 6 1 (TC) 6 0 (TL) 1 0 (TL) 1 0 (TL) 1 0 (TL) 1 0 (TL) 1 0 (TL) 0 (TL) 1 0 (TL) 1 0 (TL) 1 0 (TL) 1 0 (TL) 2 0 (TL) 1 0 (TL) 2 0 (TL) 2 0 (TL) 2 0 (TL) 2 VREF Group VSS IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO VSS IO IO IO IO VDDIO0 IO IO IO IO VDD15 IO IO IO IO VSS IO IO I/O Pin Description VSS PT24B PT24C PT24A PT23D PT23B PT23C PT23A PT22D PT22B PT22C PT22A PT21D PT21B PT21C PT21A PT20D PT20B PT20C PT20A PT19D PT19B PT19C PT19A PT18D VSS PT18B PT18C PT18A PT17D VDDIO0 PT17B PT17C PT17A PT16D VDD15 PT16B PT16C PT16A PT15D VSS PT15B PT15C - ORCA ORSPI4 Data Sheet Additional Function - FTE1036 Pair L232C L231T L232T L233C L234C L233T L234T L235C L236C L235T L236T L237C L238C L237T L238T L239C L240C L239T L240T L241C L242C L241T L242T L243C L244C L243T L244T L245C L246C L245T L246T L247C L248C L247T L248T L249C L250C VREF_1_04 PTCK1C PTCK1T PTCK0C PTCK0T VREF_1_05 VREF_1_06 MPI_RTRY_N MPI_ACK_N VREF_0_01 M0 M1 MPI_CLK - A21/MPI_BURST_N L249T 255 Lattice Semiconductor Table 87. 1036 ftSBGA Pin Table (Continued) FTE1036 VDDIO Ball Bank H39 A36 P38 B36 C36 G19 G41 D36 G42 A39 A44 A40 A41 U38 G43 A42 G44 B39 G25 B40 B41 B1 H44 B42 H43 C39 C40 D39 J42 D40 J41 E39 F39 C41 J40 D41 J39 E41 E42 C43 H42 D43 H41 0 (TL) 2 0 (TL) 2 0 (TL) 0 (TL) 2 0 (TL) 2 0 (TL) 2 0 (TL) 2 0 (TL) 2 0 (TL) 3 0 (TL) 3 0 (TL) 3 0 (TL) 0 (TL) 3 0 (TL) 3 0 (TL) 3 0 (TL) 3 0 (TL) 3 0 (TL) 4 0 (TL) 4 0 (TL) 4 0 (TL) 4 0 (TL) 4 0 (TL) 4 0 (TL) 4 0 (TL) 4 0 (TL) 4 0 (TL) 4 0 (TL) 5 0 (TL) 5 0 (TL) 5 0 (TL) 5 0 (TL) 5 0 (TL) 5 0 (TL) 5 0 (TL) 5 0 (TL) 6 0 (TL) 6 0 (TL) 6 0 (TL) 6 VREF Group IO IO VDDIO0 IO IO VDD15 IO IO IO IO VSS IO IO VDDIO0 IO IO IO IO VDD15 IO IO VSS IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO I/O Pin Description PT15A PT14D VDDIO0 PT14C PT13D VDD15 PT13B PT13C PT13A PT12D VSS PT12C PT11D VDDIO0 PT11B PT11C PT11A PT10D VDD15 PT10C PT9D VSS PT9B PT9C PT9A PT8D PT8C PT7D PT7B PT7C PT7A PT6D PT6C PT5D PT5B PT5C PT5A PT4D PT4C PT3D PT3B PT3C PT3A M2 M3 ORCA ORSPI4 Data Sheet Additional Function FTE1036 Pair L250T L251C L251T L253C L254C L253T L254T L255C L255T L257C L258C L257T L258T L259C L259T L261C L262C L261T L262T L263C L263T L265C L266C L265T L266T L267C L267T L269C L270C L269T L270T L271C L271T L273C L274C L273T L274T VREF_0_02 MPI_TEA_N VREF_0_03 D0 TMS A20/MPI_BDIP_N A19/MPI_TSZ1 A18/MPI_TSZ0 D3 VREF_0_04 D1 D2 VREF_0_05 TDI TCK VREF_0_06 - 256 Lattice Semiconductor Table 87. 1036 ftSBGA Pin Table (Continued) FTE1036 VDDIO Ball Bank C44 D44 K38 K39 K40 K41 0 (TL) 6 0 (TL) 6 VREF Group IO IO O IO IO VDD33 I/O Pin Description PT2D PT2C PCFG_MPI_IRQ PCCLK PDONE VDD33_FPGAPLL ORCA ORSPI4 Data Sheet Additional Function PLL_CK1C/PPLL PLL_CK1T/PPLL CFG_IRQ_N/MPI_I RQ_N CCLK DONE - FTE1036 Pair L275C L275T - Note: All differential pairs use adjacent balls. 257 Lattice Semiconductor ORCA ORSPI4 Data Sheet Package Information Package Thermal Characteristics Summary There are three thermal parameters that are in common use: ΘJA, ψJC, and ΘJC. It should be noted that all the parameters are affected, to varying degrees, by package design (including paddle size) and choice of materials, the amount of copper in the test board or system board, and system airﬂow. ΘJA This is the thermal resistance from junction to ambient (theta-JA, R-theta, etc.): TJ – TA Θ JA = -----------------Q (1) where TJ is the junction temperature, TA, is the ambient air temperature, and Q is the chip power. Experimentally, ΘJA is determined when a special thermal test die is assembled into the package of interest, and the part is mounted on the thermal test board. The diodes on the test chip are separately calibrated in an oven. The package/board is placed either in a JEDEC natural convection box or in the wind tunnel, the latter for forced convection measurements. A controlled amount of power (Q) is dissipated in the test chip’s heater resistor, the chip’s temperature (TJ) is determined by the forward drop on the diodes, and the ambient temperature (TA) is noted. Note that ΘJA is expressed in units of °C/W. ψJC This JEDEC designated parameter correlates the junction temperature to the case temperature. It is generally used to infer the junction temperature while the device is operating in the system. It is not considered a true thermal resistance and it is deﬁned by: ψ JC = T J – T C ------------------Q (2) where TC is the case temperature at top dead center, TJ is the junction temperature, and Q is the chip power. During the ΘJA measurements described above, besides the other parameters measured, an additional temperature reading, TC, is made with a thermocouple attached at top-dead-center of the case. ψJC is also expressed in units of °C/W. ΘJC This is the thermal resistance from junction to case. It is most often used when attaching a heat sink to the top of the package. It is deﬁned by: TJ – TC Θ JC = ------------------Q (3) The parameters in this equation have been deﬁned above. However, the measurements are performed with the case of the part pressed against a water-cooled heat sink to draw most of the heat generated by the chip out the top of the package. It is this difference in the measurement process that differentiates ΘJC from ψJC. ΘJC is a true thermal resistance and is expressed in units of °C/W. ΘJB This is the thermal resistance from junction to board. It is deﬁned by: TJ – TB Θ JB = -----------------Q (4) where TB is the temperature of the board adjacent to a lead measured with a thermocouple. The other parameters on the right-hand side have been deﬁned above. This is considered a true thermal resistance, and the measure258 Lattice Semiconductor ORCA ORSPI4 Data Sheet ment is made with a water-cooled heat sink pressed against the board to draw most of the heat out of the leads. Note that ΘJB is expressed in units of °C/W and that this parameter and the way it is measured are still being discussed by the JEDEC committee. FPSC Maximum Junction Temperature Once the power dissipated by the FPSC has been determined, the maximum junction temperature of the FPSC can be found. This is needed to determine if speed derating of the device from the 85 °C junction temperature used in all of the delay tables is needed. Using the maximum ambient temperature, TAmax, and the power dissipated by the device, Q (expressed in °C), the maximum junction temperature is approximated by: TJmax = TAmax + (Q • ΘJA) Package Thermal Characteristics The thermal characteristics of the 1036-ball ftSBGA and the 1156-ball fpBGA used for the ORSPI4 are available at the Thermal Management section of the Lattice Semiconductor web site at www.latticesemi.com. Heat Sink Vendors for BGA Packages The estimated worst-case power requirements for the ORSPI4 is in the 8 W to 10 W range. Consequently, for most applications an external heat sink will be required. Table 88 lists, in alphabetical order, heat sink vendors who advertise heat sinks aimed at the BGA market. Table 88. Heat Sink Vendors Vendor Aavid Thermalloy Chip Coolers IERC R-Theta Sanyo Denki Wakeﬁeld Thermal Solutions Location Concord, NH Warwick, RI Burbank, CA Buffalo, NY Torrance, CA Pelham, NH Phone (603) 224-9988 (800) 227-0254 (818) 842-7277 (800) 388-5428 (310) 783-5400 (800) 325-1426 Package Parasitics The electrical performance of an IC package, such as signal quality and noise sensitivity, is directly affected by the package parasitics. Figure 102. Package Parasitics LSW PAD N RW LSL Pad N C1 C2 LML Circuit Board Pads Package Pads LMW CM PAD N + 1 LSW RW C1 LSL C2 Pad N+1 259 Lattice Semiconductor Package Outline Drawings ORCA ORSPI4 Data Sheet Package Outline Drawings for the 1036-ball ftSBGA and the 1156-ball fpBGA used for the ORSPI4 are available in the Package Diagrams section of the Lattice Semiconductor web site at www.latticesemi.com. 260 Lattice Semiconductor ORCA ORSPI4 Data Sheet Ordering Information ORSPI4 - X XXXXXX X XX Device Family Speed Grade Optional Suffix Blank = Production ES = Engineering Samples Grade C = Commercial I = Industrial Package FTE1036 = 1036-ball ftSBGA (Thermally Enhanced Fine-Pitch Thin BGA) FE1036 = 1036-ball fpSBGA (Thermally Enhanced Fine-Pitch BGA) - Replaced by FTE1036 F1156 = 1156-ball fpBGA (Fine-Pitch BGA) FN1156 = Lead-Free1156-ball fpBGA (Fine-Pitch BGA) Table 89. Device Type Options Device ORSPI4 Voltage 1.5 V internal 3.3 V/2.5 V/1.8 V/ 1.5 V I/O Table 90. Commercial Ordering Information1 Device Family Part Number ORSPI4-3FTE1036C ORSPI4-2FTE1036C ORSPI4-1FTE1036C ORSPI4-3FE1036C ORSPI4 ORSPI4-1FE1036C ORSPI4-3F1156C ORSPI4-2F1156C ORSPI4-1F1156C 2 Speed Grade 3 2 1 3 2 1 3 2 1 Package Type ftSBGA Ball Count 1036 Grade C C C C ORSPI4-2FE1036C2 2 fpSBGA 1036 C C C fpBGA 1156 C C Table 91. Industrial Ordering Information1 Device Family Part Number ORSPI4-2FTE1036I ORSPI4-1FTE1036I ORSPI4 ORSPI4-2FE1036I ORSPI4-2F1156I ORSPI4-1F1156I 2 Speed Grade 2 1 2 1 2 1 Package Type ftSBGA fpSBGA fpBGA Ball Count 1036 1036 1156 Grade I I I I I I ORSPI4-1FE1036I2 Table 92. Pb-free Commercial Ordering Information1 Device Family ORSPI4 Part Number ORSPI4-3FN1156C ORSPI4-2FN1156C ORSPI4-1FN1156C Speed Grade 3 2 1 Pb-free fpBGA 1156 Package Type Ball Count Grade C C C 261 Lattice Semiconductor Table 93. Pb-free Industrial Ordering Information1 Device Family ORSPI4 Part Number ORSPI4-2FN1156I ORSPI4-1FN1156I Speed Grade 2 1 ORCA ORSPI4 Data Sheet Package Type Pb-free fpBGA Ball Count 1156 Grade I I 1. For all but the slowest commercial speed grade, the speed grades on these devices are dual marked. For example, the commercial speed grade -3XXXXXC is also marked with the industrial grade -2XXXXXI. The commercial grade is always one speed grade faster than the associated dual mark industrial grade. The slowest commercial speed grade is marked as commercial grade only. 2. Convert to FTE package per PCN#16A-07. Revision History Date – July 2004 Version – 02.0 Previous Lattice releases. Phase-Locked Loops description has been updated. ORSPI Transmit FPGA/Embedded Core Interface description has been updated. SPIA Core Transmit FPGA Interface in 32-Bit Mode. SPIA Core Transmit FPGA Interface in 64-Bit Mode, and Table 4. SPIA Core Transmit FPGA Interface in 128-Bit Mode have been updated. Link Disable section has been updated. TX DPRAM section has been updated. Port Credit Field Update Flow Chart has been added and the description has been updated. Calendar Programming section has been updated to "After programming the calendar memory, the TX_CAL_MEM_SEL bit is set to '0'." SPIA Core Receive FPGA Interface in 32-Bit Mode has been updated. RDI Block description has been updated. Far End Loopback Setup section has been added. ORSPI4 QDRII Memory Controller Block Diagram has been updated. FPGA/Embedded Core Signals has been updated. ORSPI4 Memory Controller Interface to FPGA - Write Timing Diagram has been updated. ORSPI4 Memory Controller Interface to QDRII: 4-Word Burst Mode has been updated. ORSPI4 Memory Controller Interface to FPGA - Read Timing Diagram has been updated. Memory Controller Instruction Latency section has been updated. Memory Map has been updated. ORSPI4 Post conﬁguration Standby Current has been added. ORSPI4 SERDES Worst Case Power Table has been updated with footnote 2. Supported Data Rates has been updated. SPI4.2 Data Interface has been added." Timing Reference Points with Respect to Clock Edge has been updated. Data Path Interface Timing for Static Alignment has been updated. Status Path Interface OIF-SPI4-02.2 Speciﬁcation Timing (Reference) has been updated. Status Path Interface ORSPI4 Timing in Centered (OIF) Mode has been updated. Status Channel Reference Points with Respect to Clock Edge has been updated. Status Path Interface ORSPI4 Timing in Legacy Mode has been updated. Channel Output Jitter (3.125 Gbits/s) has been updated. Channel Output Jitter (2.5 Gbits/s) has been updated." Memory Controller Input/Output Timing Speciﬁcation has been added. Memory Controller Output Timing Speciﬁcation has been added. Memory Controller Input Timing Speciﬁcation has been added. Change Summary 262 Lattice Semiconductor Date October 2004 Version 03.0 ORCA ORSPI4 Data Sheet Change Summary Datasheet is now Final Status for production release of the device. Clock Rates under High Performance Memory Controller for Interface to External Buffer Memory has been updated to 175MHz DDR performance has been updated to 175MHz in the introduction section. FPGA Logic Overview section has been updated. Recommended Operating Conditions has been updated. ORSPI4 Post-Conﬁguration Stabdby CurrentTable has been updated. ORSPI4 Combined SPIA and SPIB Worst Case Power Table has been updated. ORSPI4 QDR Memory Controller Worst Case Power Table has been updated. ORSPI4 SERDES Worst Case Power Table has been updated with footnote 2. Supported Data Rates Table has been updated. System Timing Reference Points has been updated. SPI4.2 Timing Points with Respect to Clock Edge has been added. SPI4.2 Data Interface Table has been updated. SPI4.2 Receive Timing Points with Respect to Clock Edge has been added." SPI4.2 Receive Data Interface Timing has been updated. Data Path Interface Timing for Static Alignment has been updated. Data Path Parameters for Dynamic Alignment has been updated. Status Channel Reference Points with Respect to Clock Edge (LVDS and LVTTL I/Os) has been updated. Status Path Interface ORSPI4 Timing in Centered (OIF) Mode Status Channel Reference Points with Respect to Clock Edge (Edge Aligned Legacy Mode) has been updated. Status Path Interface ORSPI4 Timing in Legacy Mode has been updated. Channel Output Jiffer (3.125 Gbits/s) has been updated. Channel Output Jitter (2.5 Gbits/s) has been updated. HSTL Class I and II section has been updated. HSTL Class II DC Operating Speciﬁcations has been updated. Supported Data Rtes (36-Bit QDR-II, 32 bit Considered Data) Table has been updated. Memory Controller Output Timing Speciﬁcations has been updated. Memory Controller Input Timing Speciﬁcations have been updated. Memory Controller Input Timing Speciﬁcations have been updated. Recommended Power Supply Connections section has been updated. Recommended Power Supply Filtering Scheme section has been updated. Commercial Ordering Information Table and Industrial Ordering Information Table have been updated for production release of the ORSPI4. Released 1156-fpBGA Pb-free devices. Added 1036-ball ftSBGA information per PCN#16A-07 (package conversion from 1036fpSBGA to 1036-ftSBGA). February 2005 04.0 April 2005 October 2007 05.0 06.0 263

下载 PDF

ORSPI4-2F1156I 价格&库存

-> 查询更多价格&库存

很抱歉，暂时无法提供与“ORSPI4-2F1156I”相匹配的价格&库存，您可以联系我们找货

免费人工找货

搜索历史

ORSPI4-2F1156I

推荐型号

相关技术文章